Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.53 97.79 93.72 97.44 71.88 96.17 98.17 71.55


Total test records in report: 2974
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html
T2814 /workspace/coverage/default/16.usbdev_in_stall.1055031169 Jul 27 07:37:28 PM PDT 24 Jul 27 07:37:29 PM PDT 24 140693823 ps
T2815 /workspace/coverage/default/48.usbdev_setup_trans_ignored.4025863339 Jul 27 07:43:16 PM PDT 24 Jul 27 07:43:17 PM PDT 24 183749910 ps
T2816 /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2207101659 Jul 27 07:41:25 PM PDT 24 Jul 27 07:44:19 PM PDT 24 5879244932 ps
T2817 /workspace/coverage/default/26.usbdev_bitstuff_err.4071402928 Jul 27 07:39:21 PM PDT 24 Jul 27 07:39:22 PM PDT 24 194851809 ps
T2818 /workspace/coverage/default/5.usbdev_low_speed_traffic.3403602790 Jul 27 07:35:01 PM PDT 24 Jul 27 07:39:14 PM PDT 24 8841918716 ps
T2819 /workspace/coverage/default/32.usbdev_link_in_err.4276914123 Jul 27 07:40:24 PM PDT 24 Jul 27 07:40:25 PM PDT 24 172886342 ps
T2820 /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.2705460328 Jul 27 07:37:18 PM PDT 24 Jul 27 07:37:41 PM PDT 24 2496225472 ps
T2821 /workspace/coverage/default/37.usbdev_stream_len_max.464891355 Jul 27 07:41:26 PM PDT 24 Jul 27 07:41:29 PM PDT 24 1097816659 ps
T2822 /workspace/coverage/default/22.usbdev_pkt_received.3494019488 Jul 27 07:38:42 PM PDT 24 Jul 27 07:38:42 PM PDT 24 175833075 ps
T2823 /workspace/coverage/default/21.usbdev_in_trans.3269213508 Jul 27 07:38:25 PM PDT 24 Jul 27 07:38:26 PM PDT 24 286292032 ps
T2824 /workspace/coverage/default/30.usbdev_stream_len_max.548665749 Jul 27 07:40:12 PM PDT 24 Jul 27 07:40:15 PM PDT 24 1425621218 ps
T2825 /workspace/coverage/default/3.usbdev_disable_endpoint.2897969617 Jul 27 07:34:10 PM PDT 24 Jul 27 07:34:11 PM PDT 24 426109119 ps
T2826 /workspace/coverage/default/43.usbdev_data_toggle_restore.249211093 Jul 27 07:42:16 PM PDT 24 Jul 27 07:42:18 PM PDT 24 669649055 ps
T2827 /workspace/coverage/default/42.usbdev_disconnected.3825582108 Jul 27 07:42:11 PM PDT 24 Jul 27 07:42:12 PM PDT 24 146209974 ps
T2828 /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.1920668084 Jul 27 07:34:47 PM PDT 24 Jul 27 07:38:19 PM PDT 24 6952310934 ps
T2829 /workspace/coverage/default/47.usbdev_min_length_in_transaction.1885922789 Jul 27 07:43:03 PM PDT 24 Jul 27 07:43:04 PM PDT 24 176405747 ps
T2830 /workspace/coverage/default/31.usbdev_in_iso.2861824250 Jul 27 07:40:18 PM PDT 24 Jul 27 07:40:19 PM PDT 24 229783177 ps
T2831 /workspace/coverage/default/19.usbdev_low_speed_traffic.823833714 Jul 27 07:38:04 PM PDT 24 Jul 27 07:41:35 PM PDT 24 7506823919 ps
T2832 /workspace/coverage/default/41.usbdev_fifo_rst.1874353287 Jul 27 07:41:54 PM PDT 24 Jul 27 07:41:57 PM PDT 24 334268190 ps
T2833 /workspace/coverage/default/6.usbdev_max_usb_traffic.2522217314 Jul 27 07:35:10 PM PDT 24 Jul 27 07:37:40 PM PDT 24 5033063210 ps
T2834 /workspace/coverage/default/34.usbdev_link_resume.3743176786 Jul 27 07:40:44 PM PDT 24 Jul 27 07:41:12 PM PDT 24 23340954698 ps
T2835 /workspace/coverage/default/16.usbdev_phy_pins_sense.1890500077 Jul 27 07:37:34 PM PDT 24 Jul 27 07:37:35 PM PDT 24 36438714 ps
T2836 /workspace/coverage/default/20.usbdev_disable_endpoint.3177061736 Jul 27 07:38:13 PM PDT 24 Jul 27 07:38:14 PM PDT 24 480121208 ps
T2837 /workspace/coverage/default/10.usbdev_pkt_received.512069780 Jul 27 07:36:17 PM PDT 24 Jul 27 07:36:18 PM PDT 24 148329297 ps
T2838 /workspace/coverage/default/24.usbdev_in_iso.415437066 Jul 27 07:39:00 PM PDT 24 Jul 27 07:39:01 PM PDT 24 220831680 ps
T2839 /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.2847214579 Jul 27 07:39:32 PM PDT 24 Jul 27 07:40:31 PM PDT 24 5667969865 ps
T2840 /workspace/coverage/default/34.usbdev_out_trans_nak.3188200944 Jul 27 07:40:51 PM PDT 24 Jul 27 07:40:52 PM PDT 24 179815137 ps
T2841 /workspace/coverage/default/4.usbdev_rand_bus_resets.2156136623 Jul 27 07:34:49 PM PDT 24 Jul 27 07:41:15 PM PDT 24 13786684744 ps
T2842 /workspace/coverage/default/5.usbdev_device_timeout.3707249183 Jul 27 07:34:55 PM PDT 24 Jul 27 07:35:09 PM PDT 24 2323367813 ps
T2843 /workspace/coverage/default/0.usbdev_phy_pins_sense.2255189854 Jul 27 07:33:05 PM PDT 24 Jul 27 07:33:06 PM PDT 24 32087915 ps
T2844 /workspace/coverage/default/22.usbdev_random_length_out_transaction.3818747176 Jul 27 07:38:42 PM PDT 24 Jul 27 07:38:44 PM PDT 24 188078479 ps
T2845 /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3465664668 Jul 27 07:41:10 PM PDT 24 Jul 27 07:41:11 PM PDT 24 176957796 ps
T2846 /workspace/coverage/default/9.usbdev_rx_crc_err.549294597 Jul 27 07:36:02 PM PDT 24 Jul 27 07:36:03 PM PDT 24 224585841 ps
T2847 /workspace/coverage/default/7.usbdev_aon_wake_resume.1154673946 Jul 27 07:35:17 PM PDT 24 Jul 27 07:35:43 PM PDT 24 23325319504 ps
T2848 /workspace/coverage/default/21.usbdev_in_iso.4099228084 Jul 27 07:38:25 PM PDT 24 Jul 27 07:38:27 PM PDT 24 212214370 ps
T2849 /workspace/coverage/default/15.usbdev_invalid_sync.3614506637 Jul 27 07:37:28 PM PDT 24 Jul 27 07:38:21 PM PDT 24 5613971507 ps
T2850 /workspace/coverage/default/32.usbdev_enable.2976132205 Jul 27 07:40:25 PM PDT 24 Jul 27 07:40:26 PM PDT 24 43201717 ps
T2851 /workspace/coverage/default/39.usbdev_disable_endpoint.4170239893 Jul 27 07:41:34 PM PDT 24 Jul 27 07:41:36 PM PDT 24 423071086 ps
T2852 /workspace/coverage/default/39.usbdev_in_stall.408608339 Jul 27 07:41:37 PM PDT 24 Jul 27 07:41:38 PM PDT 24 139602264 ps
T2853 /workspace/coverage/default/37.usbdev_rx_crc_err.2549925529 Jul 27 07:41:26 PM PDT 24 Jul 27 07:41:27 PM PDT 24 186312231 ps
T2854 /workspace/coverage/default/3.usbdev_pending_in_trans.1269419630 Jul 27 07:34:32 PM PDT 24 Jul 27 07:34:33 PM PDT 24 165266208 ps
T2855 /workspace/coverage/default/37.usbdev_out_iso.149624987 Jul 27 07:41:15 PM PDT 24 Jul 27 07:41:16 PM PDT 24 157329745 ps
T2856 /workspace/coverage/default/24.usbdev_alert_test.3697176875 Jul 27 07:39:03 PM PDT 24 Jul 27 07:39:04 PM PDT 24 77439649 ps
T2857 /workspace/coverage/default/1.usbdev_in_stall.3895920140 Jul 27 07:33:28 PM PDT 24 Jul 27 07:33:29 PM PDT 24 162427928 ps
T2858 /workspace/coverage/default/0.usbdev_link_in_err.2858175088 Jul 27 07:32:56 PM PDT 24 Jul 27 07:32:57 PM PDT 24 244356445 ps
T2859 /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2208719072 Jul 27 07:40:53 PM PDT 24 Jul 27 07:44:17 PM PDT 24 6766241254 ps
T2860 /workspace/coverage/default/7.usbdev_disconnected.3138448315 Jul 27 07:35:29 PM PDT 24 Jul 27 07:35:30 PM PDT 24 182506349 ps
T2861 /workspace/coverage/default/9.usbdev_setup_trans_ignored.988477820 Jul 27 07:36:02 PM PDT 24 Jul 27 07:36:03 PM PDT 24 146161856 ps
T2862 /workspace/coverage/default/3.usbdev_max_usb_traffic.4069225394 Jul 27 07:34:24 PM PDT 24 Jul 27 07:37:40 PM PDT 24 6493996365 ps
T209 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2158501882 Jul 27 06:34:06 PM PDT 24 Jul 27 06:34:08 PM PDT 24 112640237 ps
T205 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.237799812 Jul 27 06:33:50 PM PDT 24 Jul 27 06:33:53 PM PDT 24 265642069 ps
T206 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4241210707 Jul 27 06:34:06 PM PDT 24 Jul 27 06:34:08 PM PDT 24 77848954 ps
T230 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1422293760 Jul 27 06:33:27 PM PDT 24 Jul 27 06:33:28 PM PDT 24 62489811 ps
T210 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3460613310 Jul 27 06:33:36 PM PDT 24 Jul 27 06:33:46 PM PDT 24 1081697104 ps
T271 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.941851686 Jul 27 06:34:07 PM PDT 24 Jul 27 06:34:08 PM PDT 24 121797738 ps
T207 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1900481925 Jul 27 06:33:17 PM PDT 24 Jul 27 06:33:21 PM PDT 24 724737793 ps
T228 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2547910174 Jul 27 06:33:57 PM PDT 24 Jul 27 06:34:00 PM PDT 24 401661807 ps
T216 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1177459219 Jul 27 06:33:09 PM PDT 24 Jul 27 06:33:10 PM PDT 24 87268697 ps
T213 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1710589279 Jul 27 06:34:13 PM PDT 24 Jul 27 06:34:14 PM PDT 24 40496407 ps
T259 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1654119626 Jul 27 06:34:04 PM PDT 24 Jul 27 06:34:05 PM PDT 24 44542633 ps
T2863 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2213327708 Jul 27 06:33:28 PM PDT 24 Jul 27 06:33:30 PM PDT 24 325980933 ps
T260 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.828757508 Jul 27 06:33:09 PM PDT 24 Jul 27 06:33:18 PM PDT 24 1192096197 ps
T229 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1619518438 Jul 27 06:34:04 PM PDT 24 Jul 27 06:34:06 PM PDT 24 155207103 ps
T272 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1166225670 Jul 27 06:34:03 PM PDT 24 Jul 27 06:34:04 PM PDT 24 180584190 ps
T234 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1033380892 Jul 27 06:33:57 PM PDT 24 Jul 27 06:34:01 PM PDT 24 508380829 ps
T245 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2088113771 Jul 27 06:33:46 PM PDT 24 Jul 27 06:33:48 PM PDT 24 81641406 ps
T214 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1709001155 Jul 27 06:34:16 PM PDT 24 Jul 27 06:34:17 PM PDT 24 86368716 ps
T261 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2511998474 Jul 27 06:33:29 PM PDT 24 Jul 27 06:33:36 PM PDT 24 495671162 ps
T246 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.343458540 Jul 27 06:33:45 PM PDT 24 Jul 27 06:33:47 PM PDT 24 80260759 ps
T235 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1313481860 Jul 27 06:34:09 PM PDT 24 Jul 27 06:34:13 PM PDT 24 247423353 ps
T215 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3339842026 Jul 27 06:34:06 PM PDT 24 Jul 27 06:34:08 PM PDT 24 85096600 ps
T236 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.465527757 Jul 27 06:33:09 PM PDT 24 Jul 27 06:33:13 PM PDT 24 291811434 ps
T308 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.932158968 Jul 27 06:34:05 PM PDT 24 Jul 27 06:34:05 PM PDT 24 51009589 ps
T322 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1243896204 Jul 27 06:33:50 PM PDT 24 Jul 27 06:33:53 PM PDT 24 338600863 ps
T309 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4161415075 Jul 27 06:34:16 PM PDT 24 Jul 27 06:34:17 PM PDT 24 50913808 ps
T310 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2033241971 Jul 27 06:33:57 PM PDT 24 Jul 27 06:33:58 PM PDT 24 89060135 ps
T267 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3549554697 Jul 27 06:34:09 PM PDT 24 Jul 27 06:34:10 PM PDT 24 50123951 ps
T262 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1965552972 Jul 27 06:33:19 PM PDT 24 Jul 27 06:33:21 PM PDT 24 221257843 ps
T273 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4178582519 Jul 27 06:34:06 PM PDT 24 Jul 27 06:34:07 PM PDT 24 45276117 ps
T247 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2559729048 Jul 27 06:33:50 PM PDT 24 Jul 27 06:33:52 PM PDT 24 100792430 ps
T318 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.675099243 Jul 27 06:33:27 PM PDT 24 Jul 27 06:33:30 PM PDT 24 447110014 ps
T274 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2716648892 Jul 27 06:34:05 PM PDT 24 Jul 27 06:34:06 PM PDT 24 66677047 ps
T285 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4085559053 Jul 27 06:33:50 PM PDT 24 Jul 27 06:33:51 PM PDT 24 90090679 ps
T286 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3622266659 Jul 27 06:34:16 PM PDT 24 Jul 27 06:34:17 PM PDT 24 53460361 ps
T241 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2797179913 Jul 27 06:34:08 PM PDT 24 Jul 27 06:34:10 PM PDT 24 93237257 ps
T248 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1721636319 Jul 27 06:33:36 PM PDT 24 Jul 27 06:33:38 PM PDT 24 136906940 ps
T263 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1958234020 Jul 27 06:33:19 PM PDT 24 Jul 27 06:33:21 PM PDT 24 76632032 ps
T311 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1327427136 Jul 27 06:33:23 PM PDT 24 Jul 27 06:33:24 PM PDT 24 43022791 ps
T240 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3452676629 Jul 27 06:34:05 PM PDT 24 Jul 27 06:34:08 PM PDT 24 228911015 ps
T2864 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1656438389 Jul 27 06:34:04 PM PDT 24 Jul 27 06:34:06 PM PDT 24 157396937 ps
T264 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.374571165 Jul 27 06:33:45 PM PDT 24 Jul 27 06:33:46 PM PDT 24 76316693 ps
T265 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3531415616 Jul 27 06:33:37 PM PDT 24 Jul 27 06:33:41 PM PDT 24 312583695 ps
T2865 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.460190335 Jul 27 06:33:53 PM PDT 24 Jul 27 06:33:54 PM PDT 24 171120138 ps
T266 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1399326095 Jul 27 06:34:09 PM PDT 24 Jul 27 06:34:10 PM PDT 24 70616338 ps
T2866 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2854050219 Jul 27 06:33:46 PM PDT 24 Jul 27 06:33:48 PM PDT 24 404441212 ps
T281 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.616403028 Jul 27 06:33:08 PM PDT 24 Jul 27 06:33:09 PM PDT 24 66032412 ps
T2867 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1486143889 Jul 27 06:33:37 PM PDT 24 Jul 27 06:33:38 PM PDT 24 49779157 ps
T2868 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3024584367 Jul 27 06:33:19 PM PDT 24 Jul 27 06:33:22 PM PDT 24 1268926949 ps
T282 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2905091510 Jul 27 06:34:04 PM PDT 24 Jul 27 06:34:07 PM PDT 24 729103364 ps
T312 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.466405461 Jul 27 06:34:16 PM PDT 24 Jul 27 06:34:17 PM PDT 24 103906201 ps
T314 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1677338117 Jul 27 06:34:13 PM PDT 24 Jul 27 06:34:14 PM PDT 24 44277297 ps
T2869 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.441358736 Jul 27 06:33:49 PM PDT 24 Jul 27 06:33:50 PM PDT 24 33580414 ps
T315 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3795158024 Jul 27 06:33:53 PM PDT 24 Jul 27 06:33:54 PM PDT 24 39161315 ps
T283 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2818919861 Jul 27 06:33:18 PM PDT 24 Jul 27 06:33:19 PM PDT 24 145095828 ps
T2870 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2339630978 Jul 27 06:33:39 PM PDT 24 Jul 27 06:33:40 PM PDT 24 159534772 ps
T284 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1835083789 Jul 27 06:33:44 PM PDT 24 Jul 27 06:33:47 PM PDT 24 422830593 ps
T2871 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.463082166 Jul 27 06:34:07 PM PDT 24 Jul 27 06:34:10 PM PDT 24 520057031 ps
T2872 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.4185244288 Jul 27 06:33:29 PM PDT 24 Jul 27 06:33:30 PM PDT 24 46443073 ps
T2873 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1786151462 Jul 27 06:33:20 PM PDT 24 Jul 27 06:33:28 PM PDT 24 1537289392 ps
T323 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2877062394 Jul 27 06:33:54 PM PDT 24 Jul 27 06:33:57 PM PDT 24 636371767 ps
T2874 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2022252479 Jul 27 06:34:04 PM PDT 24 Jul 27 06:34:05 PM PDT 24 98877640 ps
T239 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1181210050 Jul 27 06:33:18 PM PDT 24 Jul 27 06:33:21 PM PDT 24 222389942 ps
T242 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3393775478 Jul 27 06:34:04 PM PDT 24 Jul 27 06:34:08 PM PDT 24 341208974 ps
T2875 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2738034726 Jul 27 06:34:18 PM PDT 24 Jul 27 06:34:19 PM PDT 24 52561402 ps
T313 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1024510646 Jul 27 06:34:09 PM PDT 24 Jul 27 06:34:10 PM PDT 24 78108400 ps
T320 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3884600635 Jul 27 06:33:38 PM PDT 24 Jul 27 06:33:42 PM PDT 24 709689625 ps
T2876 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.246563823 Jul 27 06:33:49 PM PDT 24 Jul 27 06:33:51 PM PDT 24 243522057 ps
T2877 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3397922309 Jul 27 06:34:15 PM PDT 24 Jul 27 06:34:16 PM PDT 24 57049243 ps
T2878 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2430827710 Jul 27 06:34:14 PM PDT 24 Jul 27 06:34:15 PM PDT 24 48515037 ps
T2879 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2818469130 Jul 27 06:34:13 PM PDT 24 Jul 27 06:34:14 PM PDT 24 42389721 ps
T2880 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.932037678 Jul 27 06:33:38 PM PDT 24 Jul 27 06:33:39 PM PDT 24 112899571 ps
T2881 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.155022539 Jul 27 06:33:54 PM PDT 24 Jul 27 06:33:55 PM PDT 24 96995220 ps
T2882 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3662886129 Jul 27 06:33:56 PM PDT 24 Jul 27 06:33:57 PM PDT 24 43597488 ps
T2883 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.907250423 Jul 27 06:33:19 PM PDT 24 Jul 27 06:33:21 PM PDT 24 167243385 ps
T2884 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2329842570 Jul 27 06:33:49 PM PDT 24 Jul 27 06:33:50 PM PDT 24 63118345 ps
T2885 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2097905579 Jul 27 06:34:07 PM PDT 24 Jul 27 06:34:09 PM PDT 24 124631625 ps
T2886 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3394182165 Jul 27 06:33:19 PM PDT 24 Jul 27 06:33:20 PM PDT 24 73881739 ps
T2887 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4186779863 Jul 27 06:34:17 PM PDT 24 Jul 27 06:34:18 PM PDT 24 47881548 ps
T2888 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.723786928 Jul 27 06:33:29 PM PDT 24 Jul 27 06:33:33 PM PDT 24 306378267 ps
T270 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1097195063 Jul 27 06:33:31 PM PDT 24 Jul 27 06:33:32 PM PDT 24 119516102 ps
T2889 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3523393226 Jul 27 06:33:55 PM PDT 24 Jul 27 06:33:57 PM PDT 24 75372475 ps
T2890 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2191914381 Jul 27 06:33:20 PM PDT 24 Jul 27 06:33:21 PM PDT 24 121370644 ps
T2891 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3259736307 Jul 27 06:34:07 PM PDT 24 Jul 27 06:34:09 PM PDT 24 461772992 ps
T319 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1218631463 Jul 27 06:33:46 PM PDT 24 Jul 27 06:33:49 PM PDT 24 470175888 ps
T2892 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2162361937 Jul 27 06:34:16 PM PDT 24 Jul 27 06:34:17 PM PDT 24 105702601 ps
T2893 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3364992333 Jul 27 06:33:53 PM PDT 24 Jul 27 06:33:56 PM PDT 24 110994573 ps
T2894 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.651978006 Jul 27 06:33:29 PM PDT 24 Jul 27 06:33:29 PM PDT 24 41244743 ps
T2895 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.4273696249 Jul 27 06:33:37 PM PDT 24 Jul 27 06:33:37 PM PDT 24 40643282 ps
T268 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.562104526 Jul 27 06:33:10 PM PDT 24 Jul 27 06:33:12 PM PDT 24 129908761 ps
T2896 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3561404324 Jul 27 06:34:16 PM PDT 24 Jul 27 06:34:16 PM PDT 24 61576696 ps
T2897 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3989292948 Jul 27 06:34:14 PM PDT 24 Jul 27 06:34:14 PM PDT 24 40720294 ps
T269 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3612284059 Jul 27 06:33:54 PM PDT 24 Jul 27 06:33:56 PM PDT 24 96330132 ps
T2898 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2893106214 Jul 27 06:33:30 PM PDT 24 Jul 27 06:33:32 PM PDT 24 88332994 ps
T2899 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3773807698 Jul 27 06:33:24 PM PDT 24 Jul 27 06:33:25 PM PDT 24 51627711 ps
T2900 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1773189763 Jul 27 06:34:16 PM PDT 24 Jul 27 06:34:17 PM PDT 24 32903654 ps
T2901 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2994914033 Jul 27 06:33:40 PM PDT 24 Jul 27 06:33:41 PM PDT 24 68192393 ps
T2902 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4000111916 Jul 27 06:34:08 PM PDT 24 Jul 27 06:34:08 PM PDT 24 45923765 ps
T2903 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2976976054 Jul 27 06:33:46 PM PDT 24 Jul 27 06:33:47 PM PDT 24 59598781 ps
T2904 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2451510118 Jul 27 06:34:14 PM PDT 24 Jul 27 06:34:15 PM PDT 24 94069000 ps
T2905 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3262401654 Jul 27 06:33:18 PM PDT 24 Jul 27 06:33:20 PM PDT 24 76775307 ps
T2906 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2651866223 Jul 27 06:33:52 PM PDT 24 Jul 27 06:33:55 PM PDT 24 125708591 ps
T2907 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2871983769 Jul 27 06:33:10 PM PDT 24 Jul 27 06:33:10 PM PDT 24 40254304 ps
T2908 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2368440945 Jul 27 06:33:54 PM PDT 24 Jul 27 06:33:55 PM PDT 24 92452475 ps
T2909 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2834496253 Jul 27 06:34:07 PM PDT 24 Jul 27 06:34:08 PM PDT 24 46615995 ps
T2910 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.520299114 Jul 27 06:34:15 PM PDT 24 Jul 27 06:34:16 PM PDT 24 52190435 ps
T2911 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3667193941 Jul 27 06:34:04 PM PDT 24 Jul 27 06:34:05 PM PDT 24 80192343 ps
T2912 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2612065147 Jul 27 06:34:06 PM PDT 24 Jul 27 06:34:07 PM PDT 24 52112688 ps
T2913 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4243823283 Jul 27 06:33:54 PM PDT 24 Jul 27 06:33:57 PM PDT 24 104294247 ps
T2914 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1145731296 Jul 27 06:34:07 PM PDT 24 Jul 27 06:34:11 PM PDT 24 126707287 ps
T2915 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3573756839 Jul 27 06:34:07 PM PDT 24 Jul 27 06:34:08 PM PDT 24 31138683 ps
T2916 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.227605718 Jul 27 06:33:20 PM PDT 24 Jul 27 06:33:22 PM PDT 24 101883132 ps
T2917 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3793159602 Jul 27 06:34:06 PM PDT 24 Jul 27 06:34:09 PM PDT 24 505931096 ps
T2918 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1994628854 Jul 27 06:33:23 PM PDT 24 Jul 27 06:33:24 PM PDT 24 119250572 ps
T2919 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.670232343 Jul 27 06:33:39 PM PDT 24 Jul 27 06:33:41 PM PDT 24 324018955 ps
T2920 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3198273827 Jul 27 06:33:19 PM PDT 24 Jul 27 06:33:22 PM PDT 24 96264905 ps
T2921 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1945219219 Jul 27 06:34:07 PM PDT 24 Jul 27 06:34:08 PM PDT 24 88701210 ps
T2922 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2570328357 Jul 27 06:34:06 PM PDT 24 Jul 27 06:34:10 PM PDT 24 483107580 ps
T2923 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2593237570 Jul 27 06:34:03 PM PDT 24 Jul 27 06:34:04 PM PDT 24 52701550 ps
T2924 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2369840221 Jul 27 06:33:44 PM PDT 24 Jul 27 06:33:47 PM PDT 24 227405910 ps
T2925 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2426460014 Jul 27 06:33:09 PM PDT 24 Jul 27 06:33:15 PM PDT 24 1128625147 ps
T2926 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3400531145 Jul 27 06:33:10 PM PDT 24 Jul 27 06:33:15 PM PDT 24 708016308 ps
T2927 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.615426282 Jul 27 06:33:49 PM PDT 24 Jul 27 06:33:51 PM PDT 24 91545192 ps
T2928 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3043557976 Jul 27 06:34:05 PM PDT 24 Jul 27 06:34:06 PM PDT 24 99910900 ps
T324 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.436725332 Jul 27 06:34:04 PM PDT 24 Jul 27 06:34:09 PM PDT 24 875479701 ps
T2929 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3945220645 Jul 27 06:33:17 PM PDT 24 Jul 27 06:33:21 PM PDT 24 220323740 ps
T2930 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.734240019 Jul 27 06:33:56 PM PDT 24 Jul 27 06:33:58 PM PDT 24 114155357 ps
T326 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3005468339 Jul 27 06:33:39 PM PDT 24 Jul 27 06:33:42 PM PDT 24 613559893 ps
T2931 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.343997607 Jul 27 06:33:54 PM PDT 24 Jul 27 06:33:56 PM PDT 24 126264920 ps
T2932 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3248875622 Jul 27 06:33:52 PM PDT 24 Jul 27 06:33:53 PM PDT 24 69192042 ps
T2933 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1025616225 Jul 27 06:34:13 PM PDT 24 Jul 27 06:34:14 PM PDT 24 36091132 ps
T2934 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2093695608 Jul 27 06:33:37 PM PDT 24 Jul 27 06:33:38 PM PDT 24 46706821 ps
T2935 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2706682116 Jul 27 06:34:06 PM PDT 24 Jul 27 06:34:07 PM PDT 24 72205982 ps
T2936 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4181778466 Jul 27 06:33:49 PM PDT 24 Jul 27 06:33:50 PM PDT 24 101505698 ps
T2937 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3059843132 Jul 27 06:33:19 PM PDT 24 Jul 27 06:33:20 PM PDT 24 124633846 ps
T2938 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2928531720 Jul 27 06:33:36 PM PDT 24 Jul 27 06:33:40 PM PDT 24 293775277 ps
T2939 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2420075920 Jul 27 06:34:15 PM PDT 24 Jul 27 06:34:15 PM PDT 24 54541181 ps
T321 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4026544762 Jul 27 06:33:54 PM PDT 24 Jul 27 06:33:58 PM PDT 24 943059629 ps
T2940 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1458262341 Jul 27 06:34:13 PM PDT 24 Jul 27 06:34:14 PM PDT 24 45474222 ps
T2941 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3915599228 Jul 27 06:33:49 PM PDT 24 Jul 27 06:33:50 PM PDT 24 61195431 ps
T2942 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.458223689 Jul 27 06:33:40 PM PDT 24 Jul 27 06:33:41 PM PDT 24 65848701 ps
T2943 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2243256138 Jul 27 06:33:20 PM PDT 24 Jul 27 06:33:21 PM PDT 24 104635464 ps
T2944 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2738319572 Jul 27 06:34:07 PM PDT 24 Jul 27 06:34:08 PM PDT 24 35249932 ps
T2945 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3208661559 Jul 27 06:34:07 PM PDT 24 Jul 27 06:34:09 PM PDT 24 139014160 ps
T2946 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2648718008 Jul 27 06:33:37 PM PDT 24 Jul 27 06:33:38 PM PDT 24 80554513 ps
T2947 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1180629261 Jul 27 06:33:28 PM PDT 24 Jul 27 06:33:30 PM PDT 24 170709623 ps
T2948 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2622491169 Jul 27 06:34:06 PM PDT 24 Jul 27 06:34:07 PM PDT 24 56577323 ps
T2949 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4155122010 Jul 27 06:33:21 PM PDT 24 Jul 27 06:33:23 PM PDT 24 74874569 ps
T2950 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2716854194 Jul 27 06:33:55 PM PDT 24 Jul 27 06:33:57 PM PDT 24 149395252 ps
T327 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.709378835 Jul 27 06:34:06 PM PDT 24 Jul 27 06:34:11 PM PDT 24 966271546 ps
T2951 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.140184505 Jul 27 06:34:03 PM PDT 24 Jul 27 06:34:06 PM PDT 24 107135920 ps
T2952 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3700600931 Jul 27 06:34:03 PM PDT 24 Jul 27 06:34:04 PM PDT 24 140872940 ps
T2953 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2954403451 Jul 27 06:34:16 PM PDT 24 Jul 27 06:34:16 PM PDT 24 42476988 ps
T2954 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.283936600 Jul 27 06:34:04 PM PDT 24 Jul 27 06:34:05 PM PDT 24 74445557 ps
T2955 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.606452356 Jul 27 06:33:46 PM PDT 24 Jul 27 06:33:47 PM PDT 24 41529149 ps
T2956 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3230661334 Jul 27 06:34:03 PM PDT 24 Jul 27 06:34:04 PM PDT 24 53393193 ps
T2957 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1425842736 Jul 27 06:33:21 PM PDT 24 Jul 27 06:33:22 PM PDT 24 42667817 ps
T2958 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1480692687 Jul 27 06:33:36 PM PDT 24 Jul 27 06:33:41 PM PDT 24 637406358 ps
T2959 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.826422962 Jul 27 06:33:21 PM PDT 24 Jul 27 06:33:22 PM PDT 24 68543807 ps
T325 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.581777139 Jul 27 06:33:18 PM PDT 24 Jul 27 06:33:23 PM PDT 24 1550325291 ps
T2960 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1825045143 Jul 27 06:33:19 PM PDT 24 Jul 27 06:33:21 PM PDT 24 132759721 ps
T2961 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2068966651 Jul 27 06:33:17 PM PDT 24 Jul 27 06:33:19 PM PDT 24 188660788 ps
T2962 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.986728702 Jul 27 06:33:20 PM PDT 24 Jul 27 06:33:22 PM PDT 24 56672564 ps
T2963 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2144559127 Jul 27 06:33:29 PM PDT 24 Jul 27 06:33:31 PM PDT 24 48493020 ps
T2964 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.209729889 Jul 27 06:33:45 PM PDT 24 Jul 27 06:33:47 PM PDT 24 194098089 ps
T2965 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.37863000 Jul 27 06:34:06 PM PDT 24 Jul 27 06:34:07 PM PDT 24 86699517 ps
T2966 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1056427489 Jul 27 06:33:17 PM PDT 24 Jul 27 06:33:20 PM PDT 24 100802924 ps
T2967 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1866003915 Jul 27 06:33:39 PM PDT 24 Jul 27 06:33:41 PM PDT 24 195387602 ps
T2968 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.257020004 Jul 27 06:33:55 PM PDT 24 Jul 27 06:33:56 PM PDT 24 42576391 ps
T2969 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2658058238 Jul 27 06:34:13 PM PDT 24 Jul 27 06:34:14 PM PDT 24 41560645 ps
T2970 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2824555490 Jul 27 06:34:13 PM PDT 24 Jul 27 06:34:14 PM PDT 24 39053028 ps
T2971 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3219964479 Jul 27 06:33:39 PM PDT 24 Jul 27 06:33:40 PM PDT 24 64916194 ps
T2972 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2017579792 Jul 27 06:33:24 PM PDT 24 Jul 27 06:33:29 PM PDT 24 1059191048 ps
T2973 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4217553521 Jul 27 06:33:46 PM PDT 24 Jul 27 06:33:48 PM PDT 24 46082250 ps
T2974 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.381535858 Jul 27 06:33:54 PM PDT 24 Jul 27 06:33:55 PM PDT 24 43074945 ps

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.23856373
Short name T2
Test name
Test status
Simulation time 3793817660 ps
CPU time 6.16 seconds
Started Jul 27 07:35:51 PM PDT 24
Finished Jul 27 07:35:57 PM PDT 24
Peak memory 207280 kb
Host smart-e9b09383-b471-42cb-88d4-cae7880cf18f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23856373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_
wake_disconnect.23856373
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1482019516
Short name T6
Test name
Test status
Simulation time 5360532991 ps
CPU time 162.3 seconds
Started Jul 27 07:42:38 PM PDT 24
Finished Jul 27 07:45:20 PM PDT 24
Peak memory 215612 kb
Host smart-b7a4dcf8-43b4-4e8d-b4de-6cbb2bfa626a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14820
19516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1482019516
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.4276757891
Short name T4
Test name
Test status
Simulation time 13841798468 ps
CPU time 94.36 seconds
Started Jul 27 07:42:06 PM PDT 24
Finished Jul 27 07:43:40 PM PDT 24
Peak memory 207272 kb
Host smart-11d07837-0e87-4fa6-a64d-a5490d300881
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4276757891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.4276757891
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.932158968
Short name T308
Test name
Test status
Simulation time 51009589 ps
CPU time 0.74 seconds
Started Jul 27 06:34:05 PM PDT 24
Finished Jul 27 06:34:05 PM PDT 24
Peak memory 206148 kb
Host smart-d4aee2cc-f048-4fd7-adb8-43aa34a89b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=932158968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.932158968
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.191080302
Short name T68
Test name
Test status
Simulation time 11939162397 ps
CPU time 88.42 seconds
Started Jul 27 07:34:36 PM PDT 24
Finished Jul 27 07:36:05 PM PDT 24
Peak memory 223660 kb
Host smart-4be0daac-f88c-4050-9791-09318b787c90
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191080302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.191080302
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.3161453564
Short name T165
Test name
Test status
Simulation time 446996532 ps
CPU time 1.34 seconds
Started Jul 27 07:41:07 PM PDT 24
Finished Jul 27 07:41:09 PM PDT 24
Peak memory 207108 kb
Host smart-87562e50-27a6-42a6-936c-5d460fd51358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31614
53564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.3161453564
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1900481925
Short name T207
Test name
Test status
Simulation time 724737793 ps
CPU time 4.4 seconds
Started Jul 27 06:33:17 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 206456 kb
Host smart-8f061896-51fa-46b6-b93c-35cc0ef496da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1900481925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1900481925
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1465681087
Short name T112
Test name
Test status
Simulation time 187887317 ps
CPU time 0.93 seconds
Started Jul 27 07:41:57 PM PDT 24
Finished Jul 27 07:41:58 PM PDT 24
Peak memory 207100 kb
Host smart-0c7c900a-b242-417f-816e-2f5375f0106a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14656
81087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1465681087
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_smoke.749256905
Short name T42
Test name
Test status
Simulation time 238237003 ps
CPU time 0.99 seconds
Started Jul 27 07:43:11 PM PDT 24
Finished Jul 27 07:43:12 PM PDT 24
Peak memory 207144 kb
Host smart-5d2a5c2b-a08d-47f0-a020-ccaf5438c2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74925
6905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.749256905
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2149378411
Short name T299
Test name
Test status
Simulation time 150970116 ps
CPU time 0.86 seconds
Started Jul 27 07:36:49 PM PDT 24
Finished Jul 27 07:36:50 PM PDT 24
Peak memory 207084 kb
Host smart-daf7984f-e313-4261-a170-3c51536055fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21493
78411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2149378411
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.4178613984
Short name T144
Test name
Test status
Simulation time 218980306 ps
CPU time 1.06 seconds
Started Jul 27 07:43:03 PM PDT 24
Finished Jul 27 07:43:04 PM PDT 24
Peak memory 206604 kb
Host smart-be6cf395-6b43-4957-a5dc-2df445107e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41786
13984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.4178613984
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.848351798
Short name T150
Test name
Test status
Simulation time 20327706499 ps
CPU time 55.62 seconds
Started Jul 27 07:41:39 PM PDT 24
Finished Jul 27 07:42:35 PM PDT 24
Peak memory 215588 kb
Host smart-baa0540d-0ef2-4bb8-827c-6602861d7de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84835
1798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.848351798
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.374571165
Short name T264
Test name
Test status
Simulation time 76316693 ps
CPU time 1.01 seconds
Started Jul 27 06:33:45 PM PDT 24
Finished Jul 27 06:33:46 PM PDT 24
Peak memory 206136 kb
Host smart-7fd4acc9-4b92-4796-97a3-30a1ab5a43d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=374571165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.374571165
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3579594305
Short name T23
Test name
Test status
Simulation time 54806147 ps
CPU time 0.72 seconds
Started Jul 27 07:41:18 PM PDT 24
Finished Jul 27 07:41:19 PM PDT 24
Peak memory 207104 kb
Host smart-eefa4e0a-e189-4eec-9c48-086a97875522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35795
94305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3579594305
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.4160686407
Short name T202
Test name
Test status
Simulation time 408914122 ps
CPU time 1.21 seconds
Started Jul 27 07:34:30 PM PDT 24
Finished Jul 27 07:34:32 PM PDT 24
Peak memory 222864 kb
Host smart-f3e82eca-5022-40df-83a6-f4986292780c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4160686407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.4160686407
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3048875187
Short name T243
Test name
Test status
Simulation time 302723250 ps
CPU time 1.06 seconds
Started Jul 27 07:40:29 PM PDT 24
Finished Jul 27 07:40:30 PM PDT 24
Peak memory 207096 kb
Host smart-799c37ce-ab1b-4d3f-8b0f-9213804f6966
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3048875187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3048875187
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.3784818384
Short name T86
Test name
Test status
Simulation time 9647343733 ps
CPU time 21.81 seconds
Started Jul 27 07:42:22 PM PDT 24
Finished Jul 27 07:42:44 PM PDT 24
Peak memory 207416 kb
Host smart-597de955-9ba0-4e4d-912a-88346c92b8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37848
18384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.3784818384
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1024510646
Short name T313
Test name
Test status
Simulation time 78108400 ps
CPU time 0.76 seconds
Started Jul 27 06:34:09 PM PDT 24
Finished Jul 27 06:34:10 PM PDT 24
Peak memory 206156 kb
Host smart-09681f72-d3d8-4c2a-8e89-90c9987eef30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1024510646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1024510646
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.974527716
Short name T75
Test name
Test status
Simulation time 304888112 ps
CPU time 1.08 seconds
Started Jul 27 07:33:04 PM PDT 24
Finished Jul 27 07:33:06 PM PDT 24
Peak memory 207084 kb
Host smart-8655ffa3-2389-4f34-a52b-8cb43dcb2dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97452
7716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.974527716
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1313481860
Short name T235
Test name
Test status
Simulation time 247423353 ps
CPU time 3.24 seconds
Started Jul 27 06:34:09 PM PDT 24
Finished Jul 27 06:34:13 PM PDT 24
Peak memory 206472 kb
Host smart-a7641069-e700-4c67-be3e-bb4ef91b8434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1313481860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1313481860
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.3369440240
Short name T39
Test name
Test status
Simulation time 20173539589 ps
CPU time 25.73 seconds
Started Jul 27 07:33:12 PM PDT 24
Finished Jul 27 07:33:37 PM PDT 24
Peak memory 207132 kb
Host smart-7ad60bbb-a86a-4078-8dad-ddec669ce771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33694
40240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.3369440240
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3113746438
Short name T13
Test name
Test status
Simulation time 23428296992 ps
CPU time 26.41 seconds
Started Jul 27 07:40:19 PM PDT 24
Finished Jul 27 07:40:46 PM PDT 24
Peak memory 207380 kb
Host smart-853a082d-8861-4d0c-8075-28076a6893d0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113746438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.3113746438
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4161415075
Short name T309
Test name
Test status
Simulation time 50913808 ps
CPU time 0.71 seconds
Started Jul 27 06:34:16 PM PDT 24
Finished Jul 27 06:34:17 PM PDT 24
Peak memory 206180 kb
Host smart-834a587c-f6da-4de8-86db-73743c1014ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4161415075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.4161415075
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1386251698
Short name T523
Test name
Test status
Simulation time 146184102 ps
CPU time 0.86 seconds
Started Jul 27 07:33:23 PM PDT 24
Finished Jul 27 07:33:24 PM PDT 24
Peak memory 207092 kb
Host smart-9da4e56f-0750-4f84-ad32-cdcea0e11f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13862
51698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1386251698
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.471479167
Short name T517
Test name
Test status
Simulation time 140651206 ps
CPU time 0.77 seconds
Started Jul 27 07:33:43 PM PDT 24
Finished Jul 27 07:33:44 PM PDT 24
Peak memory 207072 kb
Host smart-8cab2e64-5076-4c16-a4ef-a1c9b07d3c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47147
9167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.471479167
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.4162450849
Short name T2316
Test name
Test status
Simulation time 493429177 ps
CPU time 1.56 seconds
Started Jul 27 07:33:17 PM PDT 24
Finished Jul 27 07:33:19 PM PDT 24
Peak memory 207144 kb
Host smart-faf497d1-f5eb-4049-a050-1ccebd91c756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41624
50849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.4162450849
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/18.usbdev_device_address.2537946925
Short name T292
Test name
Test status
Simulation time 17650718732 ps
CPU time 42.94 seconds
Started Jul 27 07:37:55 PM PDT 24
Finished Jul 27 07:38:38 PM PDT 24
Peak memory 207400 kb
Host smart-f50966ec-8118-487d-a302-0644bc368c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25379
46925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.2537946925
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.1023294751
Short name T233
Test name
Test status
Simulation time 5860264198 ps
CPU time 42.46 seconds
Started Jul 27 07:35:10 PM PDT 24
Finished Jul 27 07:35:53 PM PDT 24
Peak memory 215620 kb
Host smart-17d1edfe-9c94-497b-8704-3a4fcf51195b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10232
94751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1023294751
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.1989929867
Short name T60
Test name
Test status
Simulation time 503442059 ps
CPU time 1.47 seconds
Started Jul 27 07:32:52 PM PDT 24
Finished Jul 27 07:32:54 PM PDT 24
Peak memory 207124 kb
Host smart-03216751-68b9-4e85-afc9-744e09c77091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19899
29867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.1989929867
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.2416816210
Short name T115
Test name
Test status
Simulation time 13469646437 ps
CPU time 129.6 seconds
Started Jul 27 07:33:43 PM PDT 24
Finished Jul 27 07:35:53 PM PDT 24
Peak memory 223772 kb
Host smart-5f8f35ec-bbf1-4f83-9644-8683c20efbba
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416816210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.2416816210
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2227265820
Short name T79
Test name
Test status
Simulation time 184198420 ps
CPU time 0.94 seconds
Started Jul 27 07:37:42 PM PDT 24
Finished Jul 27 07:37:43 PM PDT 24
Peak memory 207088 kb
Host smart-db6a71f5-1386-45e5-964b-af5aae16afa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22272
65820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2227265820
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.2659208191
Short name T782
Test name
Test status
Simulation time 39444889 ps
CPU time 0.65 seconds
Started Jul 27 07:33:16 PM PDT 24
Finished Jul 27 07:33:17 PM PDT 24
Peak memory 207140 kb
Host smart-b39b46e0-13f0-47c7-a909-f878fcc30dc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2659208191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.2659208191
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_device_address.4232007977
Short name T1438
Test name
Test status
Simulation time 17704777919 ps
CPU time 39.41 seconds
Started Jul 27 07:43:14 PM PDT 24
Finished Jul 27 07:43:54 PM PDT 24
Peak memory 207412 kb
Host smart-d09f710b-ae5b-48fb-9b33-6849dc9876ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42320
07977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.4232007977
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3464738248
Short name T471
Test name
Test status
Simulation time 13333011142 ps
CPU time 14.37 seconds
Started Jul 27 07:33:17 PM PDT 24
Finished Jul 27 07:33:32 PM PDT 24
Peak memory 207340 kb
Host smart-989501fe-bc68-47ab-9e8a-ed8fafc7fbbd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464738248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3464738248
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1710589279
Short name T213
Test name
Test status
Simulation time 40496407 ps
CPU time 0.71 seconds
Started Jul 27 06:34:13 PM PDT 24
Finished Jul 27 06:34:14 PM PDT 24
Peak memory 206176 kb
Host smart-aea7f755-808c-44c7-b3d1-4008a78dfc4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1710589279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1710589279
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2651071958
Short name T629
Test name
Test status
Simulation time 200468553 ps
CPU time 0.98 seconds
Started Jul 27 07:37:03 PM PDT 24
Finished Jul 27 07:37:04 PM PDT 24
Peak memory 207104 kb
Host smart-595b9f1d-d390-4ea2-ba66-05968a09d540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26510
71958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2651071958
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3348337131
Short name T297
Test name
Test status
Simulation time 166128656 ps
CPU time 0.94 seconds
Started Jul 27 07:36:48 PM PDT 24
Finished Jul 27 07:36:49 PM PDT 24
Peak memory 207136 kb
Host smart-97bf7a04-37eb-4704-b573-7c92dc203435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33483
37131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3348337131
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.480658217
Short name T203
Test name
Test status
Simulation time 1012139880 ps
CPU time 1.76 seconds
Started Jul 27 07:33:17 PM PDT 24
Finished Jul 27 07:33:19 PM PDT 24
Peak memory 222900 kb
Host smart-5b3b78fc-4567-4cc5-9c2e-22df5aa5d0fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=480658217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.480658217
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.963577884
Short name T430
Test name
Test status
Simulation time 153720037 ps
CPU time 0.88 seconds
Started Jul 27 07:38:11 PM PDT 24
Finished Jul 27 07:38:12 PM PDT 24
Peak memory 207124 kb
Host smart-0d2700aa-c057-4165-96ef-77508a9ed964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96357
7884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.963577884
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_device_address.2798956735
Short name T188
Test name
Test status
Simulation time 19795335974 ps
CPU time 43.18 seconds
Started Jul 27 07:38:24 PM PDT 24
Finished Jul 27 07:39:07 PM PDT 24
Peak memory 207608 kb
Host smart-70c1184d-e4fe-4aa8-908d-5ca7e7b97705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27989
56735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.2798956735
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.1405473534
Short name T105
Test name
Test status
Simulation time 215908485 ps
CPU time 0.89 seconds
Started Jul 27 07:32:40 PM PDT 24
Finished Jul 27 07:32:41 PM PDT 24
Peak memory 207084 kb
Host smart-c44c7296-4cfb-48b5-be3f-95edd737021c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14054
73534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.1405473534
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.324347487
Short name T201
Test name
Test status
Simulation time 151156478 ps
CPU time 0.87 seconds
Started Jul 27 07:33:06 PM PDT 24
Finished Jul 27 07:33:07 PM PDT 24
Peak memory 207112 kb
Host smart-6ba956f7-1c46-40a0-a776-3e32fde6704f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32434
7487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.324347487
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2877062394
Short name T323
Test name
Test status
Simulation time 636371767 ps
CPU time 2.55 seconds
Started Jul 27 06:33:54 PM PDT 24
Finished Jul 27 06:33:57 PM PDT 24
Peak memory 206540 kb
Host smart-1510ec33-4506-4dba-bd8e-83181e9157de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2877062394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2877062394
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1835083789
Short name T284
Test name
Test status
Simulation time 422830593 ps
CPU time 2.8 seconds
Started Jul 27 06:33:44 PM PDT 24
Finished Jul 27 06:33:47 PM PDT 24
Peak memory 206440 kb
Host smart-36b43461-2ff0-4a4c-8120-a87c60ddc147
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1835083789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1835083789
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2966030194
Short name T306
Test name
Test status
Simulation time 5109259089 ps
CPU time 36.41 seconds
Started Jul 27 07:32:52 PM PDT 24
Finished Jul 27 07:33:29 PM PDT 24
Peak memory 207404 kb
Host smart-b819d81b-e648-4bf6-99fd-933e0ef7b446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29660
30194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2966030194
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2457584269
Short name T106
Test name
Test status
Simulation time 176179496 ps
CPU time 0.85 seconds
Started Jul 27 07:38:18 PM PDT 24
Finished Jul 27 07:38:19 PM PDT 24
Peak memory 207056 kb
Host smart-4cfa2ba1-39a1-4cf3-99ee-8bb6d9251fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24575
84269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2457584269
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.158203987
Short name T171
Test name
Test status
Simulation time 10197465758 ps
CPU time 195.41 seconds
Started Jul 27 07:34:48 PM PDT 24
Finished Jul 27 07:38:03 PM PDT 24
Peak memory 215564 kb
Host smart-395745f1-41cc-4ced-b3fe-96346a0d6bb7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=158203987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.158203987
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.366549192
Short name T48
Test name
Test status
Simulation time 264468597 ps
CPU time 1.13 seconds
Started Jul 27 07:33:15 PM PDT 24
Finished Jul 27 07:33:17 PM PDT 24
Peak memory 207132 kb
Host smart-fd0f494b-675f-475f-9123-64305496374e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36654
9192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.366549192
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.2797688292
Short name T152
Test name
Test status
Simulation time 4483881569 ps
CPU time 44.79 seconds
Started Jul 27 07:38:57 PM PDT 24
Finished Jul 27 07:39:42 PM PDT 24
Peak memory 216888 kb
Host smart-59c5f637-8a75-4990-baaf-7222291b87df
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2797688292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.2797688292
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.2533423036
Short name T80
Test name
Test status
Simulation time 398713623 ps
CPU time 1.18 seconds
Started Jul 27 07:37:29 PM PDT 24
Finished Jul 27 07:37:30 PM PDT 24
Peak memory 207068 kb
Host smart-224f5966-22ec-4ea4-ae64-92e430de5ee9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2533423036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.2533423036
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1033380892
Short name T234
Test name
Test status
Simulation time 508380829 ps
CPU time 4.21 seconds
Started Jul 27 06:33:57 PM PDT 24
Finished Jul 27 06:34:01 PM PDT 24
Peak memory 206460 kb
Host smart-58191263-e4a9-4ec7-adef-4a933c073acb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1033380892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1033380892
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4026544762
Short name T321
Test name
Test status
Simulation time 943059629 ps
CPU time 3.5 seconds
Started Jul 27 06:33:54 PM PDT 24
Finished Jul 27 06:33:58 PM PDT 24
Peak memory 206460 kb
Host smart-49c1f744-fcb9-4743-a6b6-33b3acf850f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4026544762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.4026544762
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2905091510
Short name T282
Test name
Test status
Simulation time 729103364 ps
CPU time 2.94 seconds
Started Jul 27 06:34:04 PM PDT 24
Finished Jul 27 06:34:07 PM PDT 24
Peak memory 206512 kb
Host smart-b8b54dc3-b960-42e0-9d52-c85b0651c9e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2905091510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2905091510
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3005468339
Short name T326
Test name
Test status
Simulation time 613559893 ps
CPU time 3.03 seconds
Started Jul 27 06:33:39 PM PDT 24
Finished Jul 27 06:33:42 PM PDT 24
Peak memory 206456 kb
Host smart-349c5f0d-9ce8-45d0-b67e-b3fdd311a3e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3005468339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3005468339
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.730105354
Short name T304
Test name
Test status
Simulation time 95122588728 ps
CPU time 141.12 seconds
Started Jul 27 07:32:52 PM PDT 24
Finished Jul 27 07:35:13 PM PDT 24
Peak memory 207404 kb
Host smart-2fb09232-1bb9-4bb7-a74a-91f2bfe46324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730105354 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.730105354
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.847632531
Short name T467
Test name
Test status
Simulation time 120103454074 ps
CPU time 181.61 seconds
Started Jul 27 07:32:48 PM PDT 24
Finished Jul 27 07:35:50 PM PDT 24
Peak memory 207268 kb
Host smart-8cc4e75a-dc65-4412-8a7e-65cf69127303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84763
2531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.847632531
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.1415609219
Short name T2811
Test name
Test status
Simulation time 6433709538 ps
CPU time 189.13 seconds
Started Jul 27 07:36:45 PM PDT 24
Finished Jul 27 07:39:54 PM PDT 24
Peak memory 215588 kb
Host smart-8c5a5bcd-fe8d-4290-ad2e-d910cfca1d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14156
09219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.1415609219
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.355529020
Short name T295
Test name
Test status
Simulation time 206618562 ps
CPU time 0.91 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:29 PM PDT 24
Peak memory 207092 kb
Host smart-0e6407fc-bdb7-4502-9a77-880e1c8ca81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35552
9020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.355529020
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.196210533
Short name T383
Test name
Test status
Simulation time 189751098 ps
CPU time 0.91 seconds
Started Jul 27 07:33:55 PM PDT 24
Finished Jul 27 07:33:56 PM PDT 24
Peak memory 207064 kb
Host smart-0f57cd4a-aa0e-415a-8567-3d0537694c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19621
0533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.196210533
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_device_address.1145437389
Short name T999
Test name
Test status
Simulation time 9978412020 ps
CPU time 25.15 seconds
Started Jul 27 07:38:17 PM PDT 24
Finished Jul 27 07:38:42 PM PDT 24
Peak memory 207396 kb
Host smart-b9fa42ae-7b69-4571-ab24-2102558ef9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11454
37389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.1145437389
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3309618462
Short name T1322
Test name
Test status
Simulation time 13484321193 ps
CPU time 17.87 seconds
Started Jul 27 07:39:04 PM PDT 24
Finished Jul 27 07:39:22 PM PDT 24
Peak memory 207356 kb
Host smart-8c700fb2-7cf0-4b06-b9d0-a412d553839b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309618462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3309618462
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.465527757
Short name T236
Test name
Test status
Simulation time 291811434 ps
CPU time 3.18 seconds
Started Jul 27 06:33:09 PM PDT 24
Finished Jul 27 06:33:13 PM PDT 24
Peak memory 222676 kb
Host smart-9683e368-9d3c-4716-bb09-f50c629c8880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=465527757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.465527757
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.1399141265
Short name T56
Test name
Test status
Simulation time 150039077 ps
CPU time 0.85 seconds
Started Jul 27 07:33:17 PM PDT 24
Finished Jul 27 07:33:18 PM PDT 24
Peak memory 207104 kb
Host smart-80612134-97ad-4405-8d8c-dbbffab61d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13991
41265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.1399141265
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1526148976
Short name T107
Test name
Test status
Simulation time 175077758 ps
CPU time 1.77 seconds
Started Jul 27 07:33:26 PM PDT 24
Finished Jul 27 07:33:28 PM PDT 24
Peak memory 207352 kb
Host smart-55e8767b-e62c-40ef-8e7c-89218a0f8cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15261
48976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1526148976
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.788551841
Short name T157
Test name
Test status
Simulation time 8226103216 ps
CPU time 81.76 seconds
Started Jul 27 07:36:58 PM PDT 24
Finished Jul 27 07:38:20 PM PDT 24
Peak memory 215520 kb
Host smart-8ff5ab06-a3aa-474c-a9ff-ab2c3691693d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=788551841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.788551841
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1869625925
Short name T26
Test name
Test status
Simulation time 37899901 ps
CPU time 0.74 seconds
Started Jul 27 07:40:17 PM PDT 24
Finished Jul 27 07:40:18 PM PDT 24
Peak memory 207096 kb
Host smart-e9d15eb7-bb32-435d-8980-ec1f3553dc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18696
25925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1869625925
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.2275762819
Short name T44
Test name
Test status
Simulation time 172505431 ps
CPU time 0.85 seconds
Started Jul 27 07:32:40 PM PDT 24
Finished Jul 27 07:32:41 PM PDT 24
Peak memory 207116 kb
Host smart-e6d4190d-7c96-4f86-98c3-59b715486b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22757
62819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.2275762819
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3383865108
Short name T58
Test name
Test status
Simulation time 4160727630 ps
CPU time 10.33 seconds
Started Jul 27 07:32:48 PM PDT 24
Finished Jul 27 07:32:58 PM PDT 24
Peak memory 207336 kb
Host smart-9f9bcf92-33dd-4dda-959d-31c813a5b4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33838
65108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3383865108
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.3420642447
Short name T59
Test name
Test status
Simulation time 171899694 ps
CPU time 0.88 seconds
Started Jul 27 07:32:57 PM PDT 24
Finished Jul 27 07:32:58 PM PDT 24
Peak memory 207092 kb
Host smart-5b31be7e-c033-4863-bfff-4464dd4a18e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34206
42447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.3420642447
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.1680402936
Short name T2700
Test name
Test status
Simulation time 180254898 ps
CPU time 0.92 seconds
Started Jul 27 07:33:11 PM PDT 24
Finished Jul 27 07:33:12 PM PDT 24
Peak memory 207120 kb
Host smart-01f26d9b-b838-4fcb-b09f-fbc04f6e1125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16804
02936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.1680402936
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.244657589
Short name T50
Test name
Test status
Simulation time 150773695 ps
CPU time 0.85 seconds
Started Jul 27 07:33:45 PM PDT 24
Finished Jul 27 07:33:46 PM PDT 24
Peak memory 207188 kb
Host smart-e0030464-d9ae-4c4f-9941-ba9222a4e4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24465
7589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.244657589
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1039123505
Short name T2687
Test name
Test status
Simulation time 192220260 ps
CPU time 0.96 seconds
Started Jul 27 07:33:06 PM PDT 24
Finished Jul 27 07:33:07 PM PDT 24
Peak memory 207188 kb
Host smart-f5997f99-c727-4263-b531-dd4989553d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10391
23505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1039123505
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2072792142
Short name T134
Test name
Test status
Simulation time 228018500 ps
CPU time 0.9 seconds
Started Jul 27 07:33:31 PM PDT 24
Finished Jul 27 07:33:32 PM PDT 24
Peak memory 207108 kb
Host smart-3d36327c-f496-4900-aa99-a2f0ad7ee6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20727
92142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2072792142
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.74410025
Short name T170
Test name
Test status
Simulation time 10464185768 ps
CPU time 90.74 seconds
Started Jul 27 07:33:36 PM PDT 24
Finished Jul 27 07:35:07 PM PDT 24
Peak memory 215556 kb
Host smart-3e9ec3a7-6ad0-4b8b-8237-4cc4fcac2781
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=74410025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.74410025
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3636924458
Short name T2026
Test name
Test status
Simulation time 192118478 ps
CPU time 0.92 seconds
Started Jul 27 07:36:16 PM PDT 24
Finished Jul 27 07:36:17 PM PDT 24
Peak memory 207092 kb
Host smart-829c517c-bc35-4425-826e-81c11234d037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36369
24458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3636924458
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.805055720
Short name T130
Test name
Test status
Simulation time 195647200 ps
CPU time 0.92 seconds
Started Jul 27 07:36:45 PM PDT 24
Finished Jul 27 07:36:46 PM PDT 24
Peak memory 207088 kb
Host smart-bdd12361-24b6-4d7b-97ad-d1754f2863ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80505
5720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.805055720
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1829975235
Short name T1564
Test name
Test status
Simulation time 207540035 ps
CPU time 0.96 seconds
Started Jul 27 07:37:31 PM PDT 24
Finished Jul 27 07:37:32 PM PDT 24
Peak memory 207140 kb
Host smart-ce2c7afa-bb91-43db-bcde-9b1aecf374dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18299
75235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1829975235
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2805538012
Short name T136
Test name
Test status
Simulation time 213368861 ps
CPU time 0.96 seconds
Started Jul 27 07:37:38 PM PDT 24
Finished Jul 27 07:37:39 PM PDT 24
Peak memory 207124 kb
Host smart-eed951ed-7871-452e-982b-28c767afef28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28055
38012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2805538012
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2546459559
Short name T149
Test name
Test status
Simulation time 210857591 ps
CPU time 1.03 seconds
Started Jul 27 07:38:02 PM PDT 24
Finished Jul 27 07:38:04 PM PDT 24
Peak memory 207156 kb
Host smart-d2f03a71-83d0-4daa-9b58-cf0ec7059744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25464
59559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2546459559
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.400958224
Short name T73
Test name
Test status
Simulation time 15094562851 ps
CPU time 125.08 seconds
Started Jul 27 07:34:05 PM PDT 24
Finished Jul 27 07:36:10 PM PDT 24
Peak memory 217252 kb
Host smart-91f7ee1f-c29d-46ef-81a8-0471d7ee330e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400958224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.400958224
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.254841368
Short name T142
Test name
Test status
Simulation time 224369223 ps
CPU time 0.98 seconds
Started Jul 27 07:38:21 PM PDT 24
Finished Jul 27 07:38:22 PM PDT 24
Peak memory 207112 kb
Host smart-b9b91450-1b9b-4592-a4dd-553da42f1fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25484
1368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.254841368
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2585243401
Short name T1658
Test name
Test status
Simulation time 257356084 ps
CPU time 1.02 seconds
Started Jul 27 07:39:22 PM PDT 24
Finished Jul 27 07:39:23 PM PDT 24
Peak memory 207092 kb
Host smart-cc8549df-9ea1-49ed-a0ac-1c877337b717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25852
43401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2585243401
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3643693717
Short name T3
Test name
Test status
Simulation time 173757468 ps
CPU time 0.86 seconds
Started Jul 27 07:34:23 PM PDT 24
Finished Jul 27 07:34:24 PM PDT 24
Peak memory 207128 kb
Host smart-3ac115e5-214e-48ef-b3e9-42ffe801947e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36436
93717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3643693717
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3360648111
Short name T118
Test name
Test status
Simulation time 198017846 ps
CPU time 0.93 seconds
Started Jul 27 07:40:06 PM PDT 24
Finished Jul 27 07:40:07 PM PDT 24
Peak memory 207132 kb
Host smart-6b58743b-e87c-4787-a53a-68feda3b1d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33606
48111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3360648111
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.907250423
Short name T2883
Test name
Test status
Simulation time 167243385 ps
CPU time 2.08 seconds
Started Jul 27 06:33:19 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 206360 kb
Host smart-a7961973-a63b-492d-a66a-0b4f6bc3fcfa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=907250423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.907250423
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.828757508
Short name T260
Test name
Test status
Simulation time 1192096197 ps
CPU time 8.89 seconds
Started Jul 27 06:33:09 PM PDT 24
Finished Jul 27 06:33:18 PM PDT 24
Peak memory 206456 kb
Host smart-9e7deb6d-dd4e-43c3-8423-d32f3d476222
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=828757508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.828757508
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1177459219
Short name T216
Test name
Test status
Simulation time 87268697 ps
CPU time 0.91 seconds
Started Jul 27 06:33:09 PM PDT 24
Finished Jul 27 06:33:10 PM PDT 24
Peak memory 206208 kb
Host smart-20f6648c-a2b2-41f0-94c6-6b610ca34e7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1177459219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1177459219
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3059843132
Short name T2937
Test name
Test status
Simulation time 124633846 ps
CPU time 1.61 seconds
Started Jul 27 06:33:19 PM PDT 24
Finished Jul 27 06:33:20 PM PDT 24
Peak memory 214804 kb
Host smart-692ae516-7008-46e0-b7bf-b0d7496f942b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059843132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3059843132
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.616403028
Short name T281
Test name
Test status
Simulation time 66032412 ps
CPU time 0.85 seconds
Started Jul 27 06:33:08 PM PDT 24
Finished Jul 27 06:33:09 PM PDT 24
Peak memory 206136 kb
Host smart-9017f092-3b6f-4f67-9477-a1fd76ef609a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=616403028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.616403028
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2871983769
Short name T2907
Test name
Test status
Simulation time 40254304 ps
CPU time 0.72 seconds
Started Jul 27 06:33:10 PM PDT 24
Finished Jul 27 06:33:10 PM PDT 24
Peak memory 206128 kb
Host smart-bfd888fa-43c1-4744-8516-f2516853948a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2871983769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2871983769
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.562104526
Short name T268
Test name
Test status
Simulation time 129908761 ps
CPU time 2.51 seconds
Started Jul 27 06:33:10 PM PDT 24
Finished Jul 27 06:33:12 PM PDT 24
Peak memory 206372 kb
Host smart-188c9738-ec4d-400b-aa8d-2daf7595c992
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=562104526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.562104526
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3400531145
Short name T2926
Test name
Test status
Simulation time 708016308 ps
CPU time 4.77 seconds
Started Jul 27 06:33:10 PM PDT 24
Finished Jul 27 06:33:15 PM PDT 24
Peak memory 206416 kb
Host smart-e8512a4a-bd40-4768-8e3c-ea29f40c8845
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3400531145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3400531145
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3394182165
Short name T2886
Test name
Test status
Simulation time 73881739 ps
CPU time 1.06 seconds
Started Jul 27 06:33:19 PM PDT 24
Finished Jul 27 06:33:20 PM PDT 24
Peak memory 206552 kb
Host smart-7db981d8-6baa-42c3-844a-89865b172ed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3394182165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3394182165
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2426460014
Short name T2925
Test name
Test status
Simulation time 1128625147 ps
CPU time 5.03 seconds
Started Jul 27 06:33:09 PM PDT 24
Finished Jul 27 06:33:15 PM PDT 24
Peak memory 206548 kb
Host smart-2987b000-5bcb-4b5f-86bd-182f05e5f9f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2426460014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2426460014
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3262401654
Short name T2905
Test name
Test status
Simulation time 76775307 ps
CPU time 1.95 seconds
Started Jul 27 06:33:18 PM PDT 24
Finished Jul 27 06:33:20 PM PDT 24
Peak memory 206348 kb
Host smart-8096ce22-5876-4504-be5d-6f84ffcff3d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3262401654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3262401654
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1786151462
Short name T2873
Test name
Test status
Simulation time 1537289392 ps
CPU time 8.14 seconds
Started Jul 27 06:33:20 PM PDT 24
Finished Jul 27 06:33:28 PM PDT 24
Peak memory 206500 kb
Host smart-df07fe43-93b8-42b0-acc2-7ae8b9507a0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1786151462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1786151462
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2818919861
Short name T283
Test name
Test status
Simulation time 145095828 ps
CPU time 0.86 seconds
Started Jul 27 06:33:18 PM PDT 24
Finished Jul 27 06:33:19 PM PDT 24
Peak memory 206064 kb
Host smart-9dd89d8c-5e99-4177-b521-c2a10919b71a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2818919861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2818919861
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2243256138
Short name T2943
Test name
Test status
Simulation time 104635464 ps
CPU time 1.17 seconds
Started Jul 27 06:33:20 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 214532 kb
Host smart-127d461c-5ef7-4acb-bee9-4b7b70b089c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243256138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2243256138
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.826422962
Short name T2959
Test name
Test status
Simulation time 68543807 ps
CPU time 0.87 seconds
Started Jul 27 06:33:21 PM PDT 24
Finished Jul 27 06:33:22 PM PDT 24
Peak memory 206272 kb
Host smart-1dede211-2247-43a5-a648-fa816624179b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=826422962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.826422962
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3773807698
Short name T2899
Test name
Test status
Simulation time 51627711 ps
CPU time 0.73 seconds
Started Jul 27 06:33:24 PM PDT 24
Finished Jul 27 06:33:25 PM PDT 24
Peak memory 206156 kb
Host smart-6f2c43bf-5888-4fd3-8bcd-7ba9f4b79309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3773807698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3773807698
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1965552972
Short name T262
Test name
Test status
Simulation time 221257843 ps
CPU time 2.2 seconds
Started Jul 27 06:33:19 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 206372 kb
Host smart-a82109c0-c8af-4c1a-9434-e434cfed56b9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1965552972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1965552972
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3945220645
Short name T2929
Test name
Test status
Simulation time 220323740 ps
CPU time 4.19 seconds
Started Jul 27 06:33:17 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 206428 kb
Host smart-9950df03-4506-4828-97c3-d46ed5776933
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3945220645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3945220645
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1825045143
Short name T2960
Test name
Test status
Simulation time 132759721 ps
CPU time 1.06 seconds
Started Jul 27 06:33:19 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 206468 kb
Host smart-6351dfeb-aa62-4d62-9d98-29810350d644
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1825045143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1825045143
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1181210050
Short name T239
Test name
Test status
Simulation time 222389942 ps
CPU time 2.24 seconds
Started Jul 27 06:33:18 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 222608 kb
Host smart-317710c7-df81-47fe-b510-04037c13565e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1181210050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1181210050
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3024584367
Short name T2868
Test name
Test status
Simulation time 1268926949 ps
CPU time 3.21 seconds
Started Jul 27 06:33:19 PM PDT 24
Finished Jul 27 06:33:22 PM PDT 24
Peak memory 206344 kb
Host smart-40006f4d-b28d-4ec9-a3fc-dfea7b31a773
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3024584367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3024584367
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.155022539
Short name T2881
Test name
Test status
Simulation time 96995220 ps
CPU time 1.31 seconds
Started Jul 27 06:33:54 PM PDT 24
Finished Jul 27 06:33:55 PM PDT 24
Peak memory 222824 kb
Host smart-de6796ed-c0ad-4d6f-b7d1-b6cc7d89fddb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155022539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.155022539
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3248875622
Short name T2932
Test name
Test status
Simulation time 69192042 ps
CPU time 0.8 seconds
Started Jul 27 06:33:52 PM PDT 24
Finished Jul 27 06:33:53 PM PDT 24
Peak memory 206264 kb
Host smart-65dbdca3-e3ad-4eeb-b49b-8e6dc00c0465
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3248875622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3248875622
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3662886129
Short name T2882
Test name
Test status
Simulation time 43597488 ps
CPU time 0.74 seconds
Started Jul 27 06:33:56 PM PDT 24
Finished Jul 27 06:33:57 PM PDT 24
Peak memory 206204 kb
Host smart-91aa7edb-6e24-465d-87b1-e812ac8b0fb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3662886129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3662886129
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.734240019
Short name T2930
Test name
Test status
Simulation time 114155357 ps
CPU time 1.15 seconds
Started Jul 27 06:33:56 PM PDT 24
Finished Jul 27 06:33:58 PM PDT 24
Peak memory 206304 kb
Host smart-c9e05fff-33d4-4aaa-9cc9-fc1a564e3e4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=734240019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.734240019
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.237799812
Short name T205
Test name
Test status
Simulation time 265642069 ps
CPU time 3.19 seconds
Started Jul 27 06:33:50 PM PDT 24
Finished Jul 27 06:33:53 PM PDT 24
Peak memory 206484 kb
Host smart-c6455836-81cb-41e8-9dd1-cc8742f713fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=237799812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.237799812
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2547910174
Short name T228
Test name
Test status
Simulation time 401661807 ps
CPU time 2.6 seconds
Started Jul 27 06:33:57 PM PDT 24
Finished Jul 27 06:34:00 PM PDT 24
Peak memory 206488 kb
Host smart-1a35df97-50b4-4f82-afd7-a41ddd31c635
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2547910174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2547910174
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2716854194
Short name T2950
Test name
Test status
Simulation time 149395252 ps
CPU time 1.73 seconds
Started Jul 27 06:33:55 PM PDT 24
Finished Jul 27 06:33:57 PM PDT 24
Peak memory 222968 kb
Host smart-0474b67f-459c-4c12-93f8-d984533963ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716854194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2716854194
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3612284059
Short name T269
Test name
Test status
Simulation time 96330132 ps
CPU time 0.95 seconds
Started Jul 27 06:33:54 PM PDT 24
Finished Jul 27 06:33:56 PM PDT 24
Peak memory 206260 kb
Host smart-61d5b511-273c-48d5-828a-610dbe04ae99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3612284059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3612284059
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2033241971
Short name T310
Test name
Test status
Simulation time 89060135 ps
CPU time 0.76 seconds
Started Jul 27 06:33:57 PM PDT 24
Finished Jul 27 06:33:58 PM PDT 24
Peak memory 206124 kb
Host smart-6a43f8bd-e727-460a-b501-e4d711840ef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2033241971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2033241971
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.343997607
Short name T2931
Test name
Test status
Simulation time 126264920 ps
CPU time 1.7 seconds
Started Jul 27 06:33:54 PM PDT 24
Finished Jul 27 06:33:56 PM PDT 24
Peak memory 206480 kb
Host smart-09e9903b-ea74-44ce-9daf-b00c9aef7683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=343997607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.343997607
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3523393226
Short name T2889
Test name
Test status
Simulation time 75372475 ps
CPU time 2.01 seconds
Started Jul 27 06:33:55 PM PDT 24
Finished Jul 27 06:33:57 PM PDT 24
Peak memory 206468 kb
Host smart-3e91c65b-bd97-4778-afa7-ca44612798c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3523393226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3523393226
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3364992333
Short name T2893
Test name
Test status
Simulation time 110994573 ps
CPU time 2.67 seconds
Started Jul 27 06:33:53 PM PDT 24
Finished Jul 27 06:33:56 PM PDT 24
Peak memory 214720 kb
Host smart-69b5a009-4657-4c81-8da5-016c2578d427
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364992333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.3364992333
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.381535858
Short name T2974
Test name
Test status
Simulation time 43074945 ps
CPU time 0.79 seconds
Started Jul 27 06:33:54 PM PDT 24
Finished Jul 27 06:33:55 PM PDT 24
Peak memory 206080 kb
Host smart-3e3ba2d3-0497-4d29-9b45-904900eeba51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=381535858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.381535858
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3795158024
Short name T315
Test name
Test status
Simulation time 39161315 ps
CPU time 0.72 seconds
Started Jul 27 06:33:53 PM PDT 24
Finished Jul 27 06:33:54 PM PDT 24
Peak memory 206180 kb
Host smart-54a90c28-7248-4b40-b866-086eaca4e1d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3795158024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3795158024
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.460190335
Short name T2865
Test name
Test status
Simulation time 171120138 ps
CPU time 1.29 seconds
Started Jul 27 06:33:53 PM PDT 24
Finished Jul 27 06:33:54 PM PDT 24
Peak memory 206492 kb
Host smart-e3964a88-a7f9-45c0-96b5-b219747dd4e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=460190335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.460190335
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2651866223
Short name T2906
Test name
Test status
Simulation time 125708591 ps
CPU time 2.48 seconds
Started Jul 27 06:33:52 PM PDT 24
Finished Jul 27 06:33:55 PM PDT 24
Peak memory 206440 kb
Host smart-2cbfcc28-17e6-4b8a-9401-c4219f45f5a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2651866223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2651866223
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1656438389
Short name T2864
Test name
Test status
Simulation time 157396937 ps
CPU time 2.01 seconds
Started Jul 27 06:34:04 PM PDT 24
Finished Jul 27 06:34:06 PM PDT 24
Peak memory 214792 kb
Host smart-e70473f4-eaf7-4eba-b472-28ecbb463b4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656438389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1656438389
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2368440945
Short name T2908
Test name
Test status
Simulation time 92452475 ps
CPU time 0.93 seconds
Started Jul 27 06:33:54 PM PDT 24
Finished Jul 27 06:33:55 PM PDT 24
Peak memory 206164 kb
Host smart-12c3f1e2-a689-46b3-8e93-9d654786aabd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2368440945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2368440945
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.257020004
Short name T2968
Test name
Test status
Simulation time 42576391 ps
CPU time 0.72 seconds
Started Jul 27 06:33:55 PM PDT 24
Finished Jul 27 06:33:56 PM PDT 24
Peak memory 206208 kb
Host smart-9f084b43-83f0-4e53-a4f8-5ad10cb90316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=257020004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.257020004
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3043557976
Short name T2928
Test name
Test status
Simulation time 99910900 ps
CPU time 1.09 seconds
Started Jul 27 06:34:05 PM PDT 24
Finished Jul 27 06:34:06 PM PDT 24
Peak memory 206180 kb
Host smart-4ef432a1-0ea2-4f4e-b277-a60986b9f557
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3043557976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3043557976
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4243823283
Short name T2913
Test name
Test status
Simulation time 104294247 ps
CPU time 2.8 seconds
Started Jul 27 06:33:54 PM PDT 24
Finished Jul 27 06:33:57 PM PDT 24
Peak memory 214612 kb
Host smart-4fe94539-7f23-4c75-b868-79055409a2ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4243823283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4243823283
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2097905579
Short name T2885
Test name
Test status
Simulation time 124631625 ps
CPU time 1.42 seconds
Started Jul 27 06:34:07 PM PDT 24
Finished Jul 27 06:34:09 PM PDT 24
Peak memory 214624 kb
Host smart-3d56c14a-b6cd-4427-9f86-c1f5047d8e9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097905579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2097905579
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1654119626
Short name T259
Test name
Test status
Simulation time 44542633 ps
CPU time 0.78 seconds
Started Jul 27 06:34:04 PM PDT 24
Finished Jul 27 06:34:05 PM PDT 24
Peak memory 206132 kb
Host smart-a4119b79-36c9-4783-ab5f-5696bc1c326a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1654119626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1654119626
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2738319572
Short name T2944
Test name
Test status
Simulation time 35249932 ps
CPU time 0.71 seconds
Started Jul 27 06:34:07 PM PDT 24
Finished Jul 27 06:34:08 PM PDT 24
Peak memory 206224 kb
Host smart-537d1391-f418-44d6-954f-b117979e833a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2738319572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.2738319572
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1166225670
Short name T272
Test name
Test status
Simulation time 180584190 ps
CPU time 1.19 seconds
Started Jul 27 06:34:03 PM PDT 24
Finished Jul 27 06:34:04 PM PDT 24
Peak memory 206476 kb
Host smart-e70c274e-7609-4a43-9c2f-7c819fabffc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1166225670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1166225670
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3208661559
Short name T2945
Test name
Test status
Simulation time 139014160 ps
CPU time 1.73 seconds
Started Jul 27 06:34:07 PM PDT 24
Finished Jul 27 06:34:09 PM PDT 24
Peak memory 206472 kb
Host smart-04a5e02f-bc17-478c-b8f1-b8d8eae0814c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3208661559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3208661559
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2570328357
Short name T2922
Test name
Test status
Simulation time 483107580 ps
CPU time 2.87 seconds
Started Jul 27 06:34:06 PM PDT 24
Finished Jul 27 06:34:10 PM PDT 24
Peak memory 206404 kb
Host smart-1bfced86-1059-46f1-899b-3c2ab0dd515a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2570328357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2570328357
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2022252479
Short name T2874
Test name
Test status
Simulation time 98877640 ps
CPU time 1.31 seconds
Started Jul 27 06:34:04 PM PDT 24
Finished Jul 27 06:34:05 PM PDT 24
Peak memory 214656 kb
Host smart-6fc3fc77-356a-4b88-8e1c-4ab4344063c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022252479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2022252479
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1399326095
Short name T266
Test name
Test status
Simulation time 70616338 ps
CPU time 0.88 seconds
Started Jul 27 06:34:09 PM PDT 24
Finished Jul 27 06:34:10 PM PDT 24
Peak memory 206140 kb
Host smart-37d376b8-930f-40ee-8a64-39c65d726d75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1399326095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1399326095
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2593237570
Short name T2923
Test name
Test status
Simulation time 52701550 ps
CPU time 0.72 seconds
Started Jul 27 06:34:03 PM PDT 24
Finished Jul 27 06:34:04 PM PDT 24
Peak memory 206076 kb
Host smart-f6c6bd28-7b94-4257-88e5-a00570023657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2593237570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2593237570
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3259736307
Short name T2891
Test name
Test status
Simulation time 461772992 ps
CPU time 1.8 seconds
Started Jul 27 06:34:07 PM PDT 24
Finished Jul 27 06:34:09 PM PDT 24
Peak memory 206368 kb
Host smart-3e70ee62-3aac-4b61-b316-72aadbb9e9ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3259736307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3259736307
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2797179913
Short name T241
Test name
Test status
Simulation time 93237257 ps
CPU time 1.59 seconds
Started Jul 27 06:34:08 PM PDT 24
Finished Jul 27 06:34:10 PM PDT 24
Peak memory 206452 kb
Host smart-49f85bbd-d1cc-44ad-9ff8-a6748dda9ac0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2797179913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2797179913
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2706682116
Short name T2935
Test name
Test status
Simulation time 72205982 ps
CPU time 1.25 seconds
Started Jul 27 06:34:06 PM PDT 24
Finished Jul 27 06:34:07 PM PDT 24
Peak memory 214732 kb
Host smart-8aceb04f-05f8-4ced-8629-b91076922df6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706682116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2706682116
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3667193941
Short name T2911
Test name
Test status
Simulation time 80192343 ps
CPU time 1.03 seconds
Started Jul 27 06:34:04 PM PDT 24
Finished Jul 27 06:34:05 PM PDT 24
Peak memory 206260 kb
Host smart-503f694c-0582-42b5-af02-4b129a17202f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3667193941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3667193941
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3230661334
Short name T2956
Test name
Test status
Simulation time 53393193 ps
CPU time 0.79 seconds
Started Jul 27 06:34:03 PM PDT 24
Finished Jul 27 06:34:04 PM PDT 24
Peak memory 206136 kb
Host smart-61c6157e-9de0-48db-a704-d0e448d6a9b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3230661334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3230661334
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2158501882
Short name T209
Test name
Test status
Simulation time 112640237 ps
CPU time 1.12 seconds
Started Jul 27 06:34:06 PM PDT 24
Finished Jul 27 06:34:08 PM PDT 24
Peak memory 206444 kb
Host smart-f476f0e3-844c-4f3e-af80-5d74d0d1be37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2158501882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2158501882
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.463082166
Short name T2871
Test name
Test status
Simulation time 520057031 ps
CPU time 2.64 seconds
Started Jul 27 06:34:07 PM PDT 24
Finished Jul 27 06:34:10 PM PDT 24
Peak memory 206524 kb
Host smart-9ff08701-0e71-46ec-9e63-cf96e88707b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=463082166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.463082166
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.140184505
Short name T2951
Test name
Test status
Simulation time 107135920 ps
CPU time 2.87 seconds
Started Jul 27 06:34:03 PM PDT 24
Finished Jul 27 06:34:06 PM PDT 24
Peak memory 214720 kb
Host smart-310180a2-e3dd-4a72-961b-89b3a017c200
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140184505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.140184505
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3549554697
Short name T267
Test name
Test status
Simulation time 50123951 ps
CPU time 0.77 seconds
Started Jul 27 06:34:09 PM PDT 24
Finished Jul 27 06:34:10 PM PDT 24
Peak memory 206128 kb
Host smart-166c4739-c32a-4dc0-8273-b3c15496b846
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3549554697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3549554697
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2834496253
Short name T2909
Test name
Test status
Simulation time 46615995 ps
CPU time 0.69 seconds
Started Jul 27 06:34:07 PM PDT 24
Finished Jul 27 06:34:08 PM PDT 24
Peak memory 206172 kb
Host smart-6bfdfa71-1258-415c-9bc1-fff7278d513a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2834496253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2834496253
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.941851686
Short name T271
Test name
Test status
Simulation time 121797738 ps
CPU time 1.23 seconds
Started Jul 27 06:34:07 PM PDT 24
Finished Jul 27 06:34:08 PM PDT 24
Peak memory 206332 kb
Host smart-34ae9362-365a-4d1c-8742-e1125c10eb36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=941851686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.941851686
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3393775478
Short name T242
Test name
Test status
Simulation time 341208974 ps
CPU time 3.49 seconds
Started Jul 27 06:34:04 PM PDT 24
Finished Jul 27 06:34:08 PM PDT 24
Peak memory 222528 kb
Host smart-e2ffc4b2-503a-4e77-9d82-f3817220dcc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3393775478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3393775478
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.436725332
Short name T324
Test name
Test status
Simulation time 875479701 ps
CPU time 4.79 seconds
Started Jul 27 06:34:04 PM PDT 24
Finished Jul 27 06:34:09 PM PDT 24
Peak memory 206468 kb
Host smart-90902435-4d49-44b9-8b35-450b4508c921
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=436725332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.436725332
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1619518438
Short name T229
Test name
Test status
Simulation time 155207103 ps
CPU time 1.81 seconds
Started Jul 27 06:34:04 PM PDT 24
Finished Jul 27 06:34:06 PM PDT 24
Peak memory 214796 kb
Host smart-7bfe5d29-0a51-4196-9553-3c5908172180
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619518438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1619518438
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4178582519
Short name T273
Test name
Test status
Simulation time 45276117 ps
CPU time 0.81 seconds
Started Jul 27 06:34:06 PM PDT 24
Finished Jul 27 06:34:07 PM PDT 24
Peak memory 206240 kb
Host smart-180dddeb-6a52-4c2a-a250-d87d3dc3367f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4178582519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.4178582519
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1945219219
Short name T2921
Test name
Test status
Simulation time 88701210 ps
CPU time 0.79 seconds
Started Jul 27 06:34:07 PM PDT 24
Finished Jul 27 06:34:08 PM PDT 24
Peak memory 206224 kb
Host smart-1f1400e1-3675-4a76-85fb-22fa5b7e637d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1945219219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1945219219
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3700600931
Short name T2952
Test name
Test status
Simulation time 140872940 ps
CPU time 1.16 seconds
Started Jul 27 06:34:03 PM PDT 24
Finished Jul 27 06:34:04 PM PDT 24
Peak memory 206360 kb
Host smart-17e6e714-a380-447b-ad1d-dfdd78fbc39b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3700600931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3700600931
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1145731296
Short name T2914
Test name
Test status
Simulation time 126707287 ps
CPU time 3.32 seconds
Started Jul 27 06:34:07 PM PDT 24
Finished Jul 27 06:34:11 PM PDT 24
Peak memory 214580 kb
Host smart-9c9bf94c-26fc-488b-bdbb-7a8123f43736
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1145731296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1145731296
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3793159602
Short name T2917
Test name
Test status
Simulation time 505931096 ps
CPU time 3 seconds
Started Jul 27 06:34:06 PM PDT 24
Finished Jul 27 06:34:09 PM PDT 24
Peak memory 206460 kb
Host smart-0b3d5b37-7624-425a-ad58-6f73e06a0c9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3793159602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3793159602
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4241210707
Short name T206
Test name
Test status
Simulation time 77848954 ps
CPU time 1.34 seconds
Started Jul 27 06:34:06 PM PDT 24
Finished Jul 27 06:34:08 PM PDT 24
Peak memory 214724 kb
Host smart-eea33323-41db-4809-a0a4-3782bd9a7026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241210707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.4241210707
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.37863000
Short name T2965
Test name
Test status
Simulation time 86699517 ps
CPU time 1 seconds
Started Jul 27 06:34:06 PM PDT 24
Finished Jul 27 06:34:07 PM PDT 24
Peak memory 206272 kb
Host smart-002cae3d-e89c-4292-804e-091ea6763265
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=37863000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.37863000
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2716648892
Short name T274
Test name
Test status
Simulation time 66677047 ps
CPU time 1 seconds
Started Jul 27 06:34:05 PM PDT 24
Finished Jul 27 06:34:06 PM PDT 24
Peak memory 206160 kb
Host smart-6f120eba-db59-4b7b-8723-091b83e6aa1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2716648892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2716648892
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3452676629
Short name T240
Test name
Test status
Simulation time 228911015 ps
CPU time 2.51 seconds
Started Jul 27 06:34:05 PM PDT 24
Finished Jul 27 06:34:08 PM PDT 24
Peak memory 206476 kb
Host smart-38deebdc-16d8-4c9e-933d-bda27c747391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3452676629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3452676629
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.709378835
Short name T327
Test name
Test status
Simulation time 966271546 ps
CPU time 4.75 seconds
Started Jul 27 06:34:06 PM PDT 24
Finished Jul 27 06:34:11 PM PDT 24
Peak memory 206472 kb
Host smart-55ced517-8fec-49ec-8bb1-f9d6ec3251e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=709378835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.709378835
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2068966651
Short name T2961
Test name
Test status
Simulation time 188660788 ps
CPU time 2.02 seconds
Started Jul 27 06:33:17 PM PDT 24
Finished Jul 27 06:33:19 PM PDT 24
Peak memory 206404 kb
Host smart-ff75e2c0-d90b-476a-8eab-795f60b30adb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2068966651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2068966651
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2017579792
Short name T2972
Test name
Test status
Simulation time 1059191048 ps
CPU time 5.46 seconds
Started Jul 27 06:33:24 PM PDT 24
Finished Jul 27 06:33:29 PM PDT 24
Peak memory 206460 kb
Host smart-dade6961-9ad9-4e37-9ee6-6ea061ee5154
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2017579792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2017579792
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1994628854
Short name T2918
Test name
Test status
Simulation time 119250572 ps
CPU time 0.88 seconds
Started Jul 27 06:33:23 PM PDT 24
Finished Jul 27 06:33:24 PM PDT 24
Peak memory 206140 kb
Host smart-98acb4df-e1e1-4d50-baeb-ac1ef0310ddf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1994628854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1994628854
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3198273827
Short name T2920
Test name
Test status
Simulation time 96264905 ps
CPU time 2.37 seconds
Started Jul 27 06:33:19 PM PDT 24
Finished Jul 27 06:33:22 PM PDT 24
Peak memory 214692 kb
Host smart-15a1f468-1230-46b3-8f58-245418d8f5fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198273827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3198273827
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1958234020
Short name T263
Test name
Test status
Simulation time 76632032 ps
CPU time 1 seconds
Started Jul 27 06:33:19 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 206312 kb
Host smart-8850ae0b-71ad-4058-868f-841e74320783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1958234020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1958234020
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1425842736
Short name T2957
Test name
Test status
Simulation time 42667817 ps
CPU time 0.75 seconds
Started Jul 27 06:33:21 PM PDT 24
Finished Jul 27 06:33:22 PM PDT 24
Peak memory 206176 kb
Host smart-de89c3e8-87c4-4863-a7bc-3923414b41a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1425842736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1425842736
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.986728702
Short name T2962
Test name
Test status
Simulation time 56672564 ps
CPU time 1.42 seconds
Started Jul 27 06:33:20 PM PDT 24
Finished Jul 27 06:33:22 PM PDT 24
Peak memory 206376 kb
Host smart-21be5f4e-8c97-49dc-bfa6-4908d2a4b7f4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=986728702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.986728702
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.227605718
Short name T2916
Test name
Test status
Simulation time 101883132 ps
CPU time 2.37 seconds
Started Jul 27 06:33:20 PM PDT 24
Finished Jul 27 06:33:22 PM PDT 24
Peak memory 206404 kb
Host smart-5a22f9a2-0540-4089-b460-c1298713334d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=227605718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.227605718
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2191914381
Short name T2890
Test name
Test status
Simulation time 121370644 ps
CPU time 1.42 seconds
Started Jul 27 06:33:20 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 206464 kb
Host smart-6b4d6b00-e343-4177-aa5a-d37c13fd8a5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2191914381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2191914381
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4155122010
Short name T2949
Test name
Test status
Simulation time 74874569 ps
CPU time 1.89 seconds
Started Jul 27 06:33:21 PM PDT 24
Finished Jul 27 06:33:23 PM PDT 24
Peak memory 206480 kb
Host smart-f9121e38-4565-4c2d-8023-3c2bb428edd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4155122010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.4155122010
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.581777139
Short name T325
Test name
Test status
Simulation time 1550325291 ps
CPU time 4.96 seconds
Started Jul 27 06:33:18 PM PDT 24
Finished Jul 27 06:33:23 PM PDT 24
Peak memory 206448 kb
Host smart-2f0b1f01-2853-493e-a3a6-ba8bf9db60d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=581777139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.581777139
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2622491169
Short name T2948
Test name
Test status
Simulation time 56577323 ps
CPU time 0.69 seconds
Started Jul 27 06:34:06 PM PDT 24
Finished Jul 27 06:34:07 PM PDT 24
Peak memory 206160 kb
Host smart-2449ef32-c2b3-4d12-8e9e-fbf0f0270663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2622491169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2622491169
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3573756839
Short name T2915
Test name
Test status
Simulation time 31138683 ps
CPU time 0.67 seconds
Started Jul 27 06:34:07 PM PDT 24
Finished Jul 27 06:34:08 PM PDT 24
Peak memory 206172 kb
Host smart-38bd5a1e-c785-4cfc-947a-41cec1b5c480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3573756839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3573756839
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2612065147
Short name T2912
Test name
Test status
Simulation time 52112688 ps
CPU time 0.73 seconds
Started Jul 27 06:34:06 PM PDT 24
Finished Jul 27 06:34:07 PM PDT 24
Peak memory 206172 kb
Host smart-9064fb88-f07d-4c6f-88ac-1fb8f0635c30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2612065147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2612065147
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3339842026
Short name T215
Test name
Test status
Simulation time 85096600 ps
CPU time 0.82 seconds
Started Jul 27 06:34:06 PM PDT 24
Finished Jul 27 06:34:08 PM PDT 24
Peak memory 206100 kb
Host smart-5c299a64-b16b-4026-8006-f3fff4a205f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3339842026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3339842026
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4000111916
Short name T2902
Test name
Test status
Simulation time 45923765 ps
CPU time 0.75 seconds
Started Jul 27 06:34:08 PM PDT 24
Finished Jul 27 06:34:08 PM PDT 24
Peak memory 206176 kb
Host smart-73d2bff7-4730-4476-baf2-d11d4933f6ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4000111916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4000111916
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.283936600
Short name T2954
Test name
Test status
Simulation time 74445557 ps
CPU time 0.77 seconds
Started Jul 27 06:34:04 PM PDT 24
Finished Jul 27 06:34:05 PM PDT 24
Peak memory 206188 kb
Host smart-57785da1-c792-4715-86f4-f54fd6250255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=283936600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.283936600
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2430827710
Short name T2878
Test name
Test status
Simulation time 48515037 ps
CPU time 0.78 seconds
Started Jul 27 06:34:14 PM PDT 24
Finished Jul 27 06:34:15 PM PDT 24
Peak memory 206100 kb
Host smart-d40aaaf9-bc6a-42f5-a255-fb345d653249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2430827710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2430827710
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2658058238
Short name T2969
Test name
Test status
Simulation time 41560645 ps
CPU time 0.71 seconds
Started Jul 27 06:34:13 PM PDT 24
Finished Jul 27 06:34:14 PM PDT 24
Peak memory 206212 kb
Host smart-88df5d59-c8c3-4b9e-8e2f-13884223672b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2658058238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2658058238
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2162361937
Short name T2892
Test name
Test status
Simulation time 105702601 ps
CPU time 0.8 seconds
Started Jul 27 06:34:16 PM PDT 24
Finished Jul 27 06:34:17 PM PDT 24
Peak memory 206060 kb
Host smart-2c98a9c4-de2c-4bd2-874c-ec33b52d8a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2162361937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2162361937
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1180629261
Short name T2947
Test name
Test status
Simulation time 170709623 ps
CPU time 2.07 seconds
Started Jul 27 06:33:28 PM PDT 24
Finished Jul 27 06:33:30 PM PDT 24
Peak memory 206340 kb
Host smart-cacaa369-bbcd-47fe-b2e9-75a9530db75f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1180629261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1180629261
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2511998474
Short name T261
Test name
Test status
Simulation time 495671162 ps
CPU time 6.99 seconds
Started Jul 27 06:33:29 PM PDT 24
Finished Jul 27 06:33:36 PM PDT 24
Peak memory 206380 kb
Host smart-91147813-f96f-4f6b-994b-3011c387b96a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2511998474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2511998474
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1097195063
Short name T270
Test name
Test status
Simulation time 119516102 ps
CPU time 0.96 seconds
Started Jul 27 06:33:31 PM PDT 24
Finished Jul 27 06:33:32 PM PDT 24
Peak memory 206164 kb
Host smart-00c9c187-7587-41d3-8688-ffa3e6298b84
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1097195063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1097195063
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2893106214
Short name T2898
Test name
Test status
Simulation time 88332994 ps
CPU time 1.26 seconds
Started Jul 27 06:33:30 PM PDT 24
Finished Jul 27 06:33:32 PM PDT 24
Peak memory 214672 kb
Host smart-cb04386f-3890-41ac-9b0f-6880a2778cb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893106214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2893106214
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.4185244288
Short name T2872
Test name
Test status
Simulation time 46443073 ps
CPU time 0.95 seconds
Started Jul 27 06:33:29 PM PDT 24
Finished Jul 27 06:33:30 PM PDT 24
Peak memory 206168 kb
Host smart-931e60e4-a9a6-45c5-bcea-05f61cf8340f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4185244288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.4185244288
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1327427136
Short name T311
Test name
Test status
Simulation time 43022791 ps
CPU time 0.71 seconds
Started Jul 27 06:33:23 PM PDT 24
Finished Jul 27 06:33:24 PM PDT 24
Peak memory 206156 kb
Host smart-279385a5-0e90-4a00-923b-667656051d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1327427136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1327427136
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2144559127
Short name T2963
Test name
Test status
Simulation time 48493020 ps
CPU time 1.42 seconds
Started Jul 27 06:33:29 PM PDT 24
Finished Jul 27 06:33:31 PM PDT 24
Peak memory 214660 kb
Host smart-dd99ef13-10e3-4bbf-9ad0-cdf54c7423c3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2144559127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2144559127
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2213327708
Short name T2863
Test name
Test status
Simulation time 325980933 ps
CPU time 2.5 seconds
Started Jul 27 06:33:28 PM PDT 24
Finished Jul 27 06:33:30 PM PDT 24
Peak memory 206464 kb
Host smart-15e15e43-8db0-49e6-b422-db515de78637
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2213327708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2213327708
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1422293760
Short name T230
Test name
Test status
Simulation time 62489811 ps
CPU time 1.04 seconds
Started Jul 27 06:33:27 PM PDT 24
Finished Jul 27 06:33:28 PM PDT 24
Peak memory 206400 kb
Host smart-8fa0d030-89af-459a-afbf-ffcc2de5afb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1422293760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1422293760
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1056427489
Short name T2966
Test name
Test status
Simulation time 100802924 ps
CPU time 2.54 seconds
Started Jul 27 06:33:17 PM PDT 24
Finished Jul 27 06:33:20 PM PDT 24
Peak memory 206536 kb
Host smart-c4557273-3993-4707-9352-debfbf4ef0da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1056427489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1056427489
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3561404324
Short name T2896
Test name
Test status
Simulation time 61576696 ps
CPU time 0.74 seconds
Started Jul 27 06:34:16 PM PDT 24
Finished Jul 27 06:34:16 PM PDT 24
Peak memory 206224 kb
Host smart-7d555316-bff4-453b-9787-4d412675c2e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3561404324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3561404324
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1025616225
Short name T2933
Test name
Test status
Simulation time 36091132 ps
CPU time 0.71 seconds
Started Jul 27 06:34:13 PM PDT 24
Finished Jul 27 06:34:14 PM PDT 24
Peak memory 206172 kb
Host smart-3fb24b4d-b145-409b-a469-69f10e2fe83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1025616225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1025616225
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1677338117
Short name T314
Test name
Test status
Simulation time 44277297 ps
CPU time 0.7 seconds
Started Jul 27 06:34:13 PM PDT 24
Finished Jul 27 06:34:14 PM PDT 24
Peak memory 206188 kb
Host smart-85e5e5ee-49f2-4191-b250-94a90e4d7b4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1677338117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1677338117
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1458262341
Short name T2940
Test name
Test status
Simulation time 45474222 ps
CPU time 0.74 seconds
Started Jul 27 06:34:13 PM PDT 24
Finished Jul 27 06:34:14 PM PDT 24
Peak memory 206180 kb
Host smart-dabb28e0-d466-4332-8180-e54746a182f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1458262341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1458262341
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3989292948
Short name T2897
Test name
Test status
Simulation time 40720294 ps
CPU time 0.71 seconds
Started Jul 27 06:34:14 PM PDT 24
Finished Jul 27 06:34:14 PM PDT 24
Peak memory 206272 kb
Host smart-4abd3c7f-546d-4401-8e70-c8d2704048af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3989292948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3989292948
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3622266659
Short name T286
Test name
Test status
Simulation time 53460361 ps
CPU time 0.76 seconds
Started Jul 27 06:34:16 PM PDT 24
Finished Jul 27 06:34:17 PM PDT 24
Peak memory 206108 kb
Host smart-0ea5b0f6-5e64-4d00-9e2c-a87e59d7d283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3622266659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3622266659
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1709001155
Short name T214
Test name
Test status
Simulation time 86368716 ps
CPU time 0.8 seconds
Started Jul 27 06:34:16 PM PDT 24
Finished Jul 27 06:34:17 PM PDT 24
Peak memory 206176 kb
Host smart-38d159b0-8c90-4600-adde-93447d9cf56c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1709001155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1709001155
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2738034726
Short name T2875
Test name
Test status
Simulation time 52561402 ps
CPU time 0.76 seconds
Started Jul 27 06:34:18 PM PDT 24
Finished Jul 27 06:34:19 PM PDT 24
Peak memory 206060 kb
Host smart-155d0d23-1eeb-4fcc-9f0c-c6ad0d86bcc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2738034726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2738034726
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3531415616
Short name T265
Test name
Test status
Simulation time 312583695 ps
CPU time 3.43 seconds
Started Jul 27 06:33:37 PM PDT 24
Finished Jul 27 06:33:41 PM PDT 24
Peak memory 206452 kb
Host smart-2ee87f95-96bd-4aae-8400-b566af39b076
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3531415616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3531415616
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3460613310
Short name T210
Test name
Test status
Simulation time 1081697104 ps
CPU time 9.92 seconds
Started Jul 27 06:33:36 PM PDT 24
Finished Jul 27 06:33:46 PM PDT 24
Peak memory 206516 kb
Host smart-559d2400-da7c-488e-9d80-888a6633c887
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3460613310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3460613310
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.458223689
Short name T2942
Test name
Test status
Simulation time 65848701 ps
CPU time 0.79 seconds
Started Jul 27 06:33:40 PM PDT 24
Finished Jul 27 06:33:41 PM PDT 24
Peak memory 206196 kb
Host smart-9059f69d-80c8-482a-8d11-c9c9730dcc09
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=458223689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.458223689
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1721636319
Short name T248
Test name
Test status
Simulation time 136906940 ps
CPU time 1.32 seconds
Started Jul 27 06:33:36 PM PDT 24
Finished Jul 27 06:33:38 PM PDT 24
Peak memory 222888 kb
Host smart-7156bb61-4eb0-4bde-8e05-856fca4a7c81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721636319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1721636319
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2648718008
Short name T2946
Test name
Test status
Simulation time 80554513 ps
CPU time 0.83 seconds
Started Jul 27 06:33:37 PM PDT 24
Finished Jul 27 06:33:38 PM PDT 24
Peak memory 206264 kb
Host smart-37926a60-d360-4139-8268-a2452a78a333
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2648718008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2648718008
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.651978006
Short name T2894
Test name
Test status
Simulation time 41244743 ps
CPU time 0.69 seconds
Started Jul 27 06:33:29 PM PDT 24
Finished Jul 27 06:33:29 PM PDT 24
Peak memory 206140 kb
Host smart-69a0a65f-6465-4f51-a5e3-bdb287a80fb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=651978006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.651978006
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1866003915
Short name T2967
Test name
Test status
Simulation time 195387602 ps
CPU time 2.39 seconds
Started Jul 27 06:33:39 PM PDT 24
Finished Jul 27 06:33:41 PM PDT 24
Peak memory 214688 kb
Host smart-e497c4ac-9886-4ed7-8abf-54ac242ad4f1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1866003915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1866003915
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1480692687
Short name T2958
Test name
Test status
Simulation time 637406358 ps
CPU time 4.42 seconds
Started Jul 27 06:33:36 PM PDT 24
Finished Jul 27 06:33:41 PM PDT 24
Peak memory 206328 kb
Host smart-d9c95be6-874b-4155-a260-9d616a19b090
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1480692687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1480692687
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2339630978
Short name T2870
Test name
Test status
Simulation time 159534772 ps
CPU time 1.41 seconds
Started Jul 27 06:33:39 PM PDT 24
Finished Jul 27 06:33:40 PM PDT 24
Peak memory 206484 kb
Host smart-bb80deeb-6ed1-424f-8205-6fe402e77931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2339630978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2339630978
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.723786928
Short name T2888
Test name
Test status
Simulation time 306378267 ps
CPU time 3.36 seconds
Started Jul 27 06:33:29 PM PDT 24
Finished Jul 27 06:33:33 PM PDT 24
Peak memory 222888 kb
Host smart-26e1b0ed-998f-4ef7-ade7-d6869a41dfca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=723786928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.723786928
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.675099243
Short name T318
Test name
Test status
Simulation time 447110014 ps
CPU time 2.76 seconds
Started Jul 27 06:33:27 PM PDT 24
Finished Jul 27 06:33:30 PM PDT 24
Peak memory 206528 kb
Host smart-aaf553c4-dec6-4c02-b057-08a86cb28295
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=675099243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.675099243
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2824555490
Short name T2970
Test name
Test status
Simulation time 39053028 ps
CPU time 0.71 seconds
Started Jul 27 06:34:13 PM PDT 24
Finished Jul 27 06:34:14 PM PDT 24
Peak memory 206208 kb
Host smart-b5515547-ab6c-417b-bb78-872191a30d1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2824555490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2824555490
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.520299114
Short name T2910
Test name
Test status
Simulation time 52190435 ps
CPU time 0.69 seconds
Started Jul 27 06:34:15 PM PDT 24
Finished Jul 27 06:34:16 PM PDT 24
Peak memory 206188 kb
Host smart-6011e0b7-b152-498a-b3ba-51558a7f0481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=520299114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.520299114
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2420075920
Short name T2939
Test name
Test status
Simulation time 54541181 ps
CPU time 0.74 seconds
Started Jul 27 06:34:15 PM PDT 24
Finished Jul 27 06:34:15 PM PDT 24
Peak memory 206176 kb
Host smart-509be21e-ef0e-4f8b-85be-02db15fd1ccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2420075920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2420075920
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3397922309
Short name T2877
Test name
Test status
Simulation time 57049243 ps
CPU time 0.74 seconds
Started Jul 27 06:34:15 PM PDT 24
Finished Jul 27 06:34:16 PM PDT 24
Peak memory 206136 kb
Host smart-9b6a292b-d8c4-44de-8449-de6caea3537e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3397922309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3397922309
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1773189763
Short name T2900
Test name
Test status
Simulation time 32903654 ps
CPU time 0.74 seconds
Started Jul 27 06:34:16 PM PDT 24
Finished Jul 27 06:34:17 PM PDT 24
Peak memory 206180 kb
Host smart-8433a75b-a567-43bf-b612-babcd0cf1756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1773189763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1773189763
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2451510118
Short name T2904
Test name
Test status
Simulation time 94069000 ps
CPU time 0.75 seconds
Started Jul 27 06:34:14 PM PDT 24
Finished Jul 27 06:34:15 PM PDT 24
Peak memory 206152 kb
Host smart-f3a7ca11-bbb4-44da-a6ed-0182bf633041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2451510118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2451510118
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4186779863
Short name T2887
Test name
Test status
Simulation time 47881548 ps
CPU time 0.78 seconds
Started Jul 27 06:34:17 PM PDT 24
Finished Jul 27 06:34:18 PM PDT 24
Peak memory 206180 kb
Host smart-f064d786-eb79-4427-a4f2-f030536dfc00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4186779863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.4186779863
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2818469130
Short name T2879
Test name
Test status
Simulation time 42389721 ps
CPU time 0.74 seconds
Started Jul 27 06:34:13 PM PDT 24
Finished Jul 27 06:34:14 PM PDT 24
Peak memory 206188 kb
Host smart-651d93b7-5f8d-49cd-aa1e-626860edfac7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2818469130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2818469130
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2954403451
Short name T2953
Test name
Test status
Simulation time 42476988 ps
CPU time 0.72 seconds
Started Jul 27 06:34:16 PM PDT 24
Finished Jul 27 06:34:16 PM PDT 24
Peak memory 206192 kb
Host smart-79fc7a37-2162-4614-9e42-60adef66d19d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2954403451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2954403451
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.466405461
Short name T312
Test name
Test status
Simulation time 103906201 ps
CPU time 0.78 seconds
Started Jul 27 06:34:16 PM PDT 24
Finished Jul 27 06:34:17 PM PDT 24
Peak memory 206104 kb
Host smart-0ceeba53-e381-4bf5-876a-b193cca04e17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=466405461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.466405461
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.932037678
Short name T2880
Test name
Test status
Simulation time 112899571 ps
CPU time 1.36 seconds
Started Jul 27 06:33:38 PM PDT 24
Finished Jul 27 06:33:39 PM PDT 24
Peak memory 214760 kb
Host smart-a1507fc0-68d3-403b-bd14-2dc22a4c2ac8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932037678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.932037678
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2093695608
Short name T2934
Test name
Test status
Simulation time 46706821 ps
CPU time 0.91 seconds
Started Jul 27 06:33:37 PM PDT 24
Finished Jul 27 06:33:38 PM PDT 24
Peak memory 206280 kb
Host smart-3c07c8ee-0fce-4adf-83fd-70dfe29c8da7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2093695608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2093695608
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.4273696249
Short name T2895
Test name
Test status
Simulation time 40643282 ps
CPU time 0.72 seconds
Started Jul 27 06:33:37 PM PDT 24
Finished Jul 27 06:33:37 PM PDT 24
Peak memory 206136 kb
Host smart-9524c779-9c70-426e-9122-e010a6c270b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4273696249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.4273696249
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.670232343
Short name T2919
Test name
Test status
Simulation time 324018955 ps
CPU time 1.81 seconds
Started Jul 27 06:33:39 PM PDT 24
Finished Jul 27 06:33:41 PM PDT 24
Peak memory 206512 kb
Host smart-3da9161d-9742-4840-a85c-874def04ecef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=670232343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.670232343
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2928531720
Short name T2938
Test name
Test status
Simulation time 293775277 ps
CPU time 3.5 seconds
Started Jul 27 06:33:36 PM PDT 24
Finished Jul 27 06:33:40 PM PDT 24
Peak memory 222736 kb
Host smart-72b416b1-8ec4-4ee8-9193-beb19ef067c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2928531720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2928531720
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2088113771
Short name T245
Test name
Test status
Simulation time 81641406 ps
CPU time 1.3 seconds
Started Jul 27 06:33:46 PM PDT 24
Finished Jul 27 06:33:48 PM PDT 24
Peak memory 214772 kb
Host smart-7d4740af-ab68-4151-9982-837532542ea9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088113771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2088113771
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1486143889
Short name T2867
Test name
Test status
Simulation time 49779157 ps
CPU time 0.83 seconds
Started Jul 27 06:33:37 PM PDT 24
Finished Jul 27 06:33:38 PM PDT 24
Peak memory 206292 kb
Host smart-df815bce-5ede-4e59-b415-8b72bdb51415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1486143889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1486143889
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2994914033
Short name T2901
Test name
Test status
Simulation time 68192393 ps
CPU time 0.69 seconds
Started Jul 27 06:33:40 PM PDT 24
Finished Jul 27 06:33:41 PM PDT 24
Peak memory 206104 kb
Host smart-608ffd32-4de7-4976-affc-c0af7b4d03c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2994914033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2994914033
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4181778466
Short name T2936
Test name
Test status
Simulation time 101505698 ps
CPU time 1.15 seconds
Started Jul 27 06:33:49 PM PDT 24
Finished Jul 27 06:33:50 PM PDT 24
Peak memory 206512 kb
Host smart-13aef9f9-4de2-4a54-97c3-e616098a8b19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4181778466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.4181778466
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3219964479
Short name T2971
Test name
Test status
Simulation time 64916194 ps
CPU time 1.32 seconds
Started Jul 27 06:33:39 PM PDT 24
Finished Jul 27 06:33:40 PM PDT 24
Peak memory 206468 kb
Host smart-70faa67d-65ac-462b-8005-fb963120def8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3219964479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3219964479
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3884600635
Short name T320
Test name
Test status
Simulation time 709689625 ps
CPU time 4.4 seconds
Started Jul 27 06:33:38 PM PDT 24
Finished Jul 27 06:33:42 PM PDT 24
Peak memory 206540 kb
Host smart-e8afbc89-f642-4f2d-ac02-a2f67940e2ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3884600635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3884600635
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2559729048
Short name T247
Test name
Test status
Simulation time 100792430 ps
CPU time 1.78 seconds
Started Jul 27 06:33:50 PM PDT 24
Finished Jul 27 06:33:52 PM PDT 24
Peak memory 214696 kb
Host smart-4168d8f2-bc74-456f-bc85-721a43edd351
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559729048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2559729048
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3915599228
Short name T2941
Test name
Test status
Simulation time 61195431 ps
CPU time 0.92 seconds
Started Jul 27 06:33:49 PM PDT 24
Finished Jul 27 06:33:50 PM PDT 24
Peak memory 206268 kb
Host smart-08048346-58b6-4ec8-a00d-c8ed34e6e282
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3915599228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3915599228
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.606452356
Short name T2955
Test name
Test status
Simulation time 41529149 ps
CPU time 0.71 seconds
Started Jul 27 06:33:46 PM PDT 24
Finished Jul 27 06:33:47 PM PDT 24
Peak memory 206160 kb
Host smart-84204bea-7670-4040-b8db-fa3e58e94791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=606452356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.606452356
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2854050219
Short name T2866
Test name
Test status
Simulation time 404441212 ps
CPU time 2.08 seconds
Started Jul 27 06:33:46 PM PDT 24
Finished Jul 27 06:33:48 PM PDT 24
Peak memory 206724 kb
Host smart-c9088a85-346e-4f11-8412-9cd101075471
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2854050219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2854050219
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2369840221
Short name T2924
Test name
Test status
Simulation time 227405910 ps
CPU time 2.53 seconds
Started Jul 27 06:33:44 PM PDT 24
Finished Jul 27 06:33:47 PM PDT 24
Peak memory 214640 kb
Host smart-211d2477-252d-40ea-9ccd-2df98a5c8bd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2369840221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2369840221
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1243896204
Short name T322
Test name
Test status
Simulation time 338600863 ps
CPU time 2.47 seconds
Started Jul 27 06:33:50 PM PDT 24
Finished Jul 27 06:33:53 PM PDT 24
Peak memory 206452 kb
Host smart-5cf12f07-3209-42cd-9c7f-3021c086545c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1243896204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1243896204
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.343458540
Short name T246
Test name
Test status
Simulation time 80260759 ps
CPU time 1.67 seconds
Started Jul 27 06:33:45 PM PDT 24
Finished Jul 27 06:33:47 PM PDT 24
Peak memory 214720 kb
Host smart-52594d83-eac9-44b1-b893-bedc2fc684fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343458540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.343458540
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.441358736
Short name T2869
Test name
Test status
Simulation time 33580414 ps
CPU time 0.66 seconds
Started Jul 27 06:33:49 PM PDT 24
Finished Jul 27 06:33:50 PM PDT 24
Peak memory 206184 kb
Host smart-4bc68ec7-f6a0-4462-81d0-af13ebbf35e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=441358736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.441358736
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.246563823
Short name T2876
Test name
Test status
Simulation time 243522057 ps
CPU time 1.65 seconds
Started Jul 27 06:33:49 PM PDT 24
Finished Jul 27 06:33:51 PM PDT 24
Peak memory 206536 kb
Host smart-13e13613-a958-4bb3-a6b3-4b1b95adf174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=246563823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.246563823
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.209729889
Short name T2964
Test name
Test status
Simulation time 194098089 ps
CPU time 2.33 seconds
Started Jul 27 06:33:45 PM PDT 24
Finished Jul 27 06:33:47 PM PDT 24
Peak memory 222080 kb
Host smart-ba9bdc2c-46d9-45c1-9a38-b6b7d96f505c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=209729889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.209729889
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1218631463
Short name T319
Test name
Test status
Simulation time 470175888 ps
CPU time 2.56 seconds
Started Jul 27 06:33:46 PM PDT 24
Finished Jul 27 06:33:49 PM PDT 24
Peak memory 206512 kb
Host smart-7ae581de-c949-41a1-ba3b-ce7adfaac0ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1218631463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1218631463
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.615426282
Short name T2927
Test name
Test status
Simulation time 91545192 ps
CPU time 1.68 seconds
Started Jul 27 06:33:49 PM PDT 24
Finished Jul 27 06:33:51 PM PDT 24
Peak memory 214660 kb
Host smart-51b96a3b-2a5b-4b23-888f-c582fabec891
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615426282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.615426282
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2976976054
Short name T2903
Test name
Test status
Simulation time 59598781 ps
CPU time 0.86 seconds
Started Jul 27 06:33:46 PM PDT 24
Finished Jul 27 06:33:47 PM PDT 24
Peak memory 206264 kb
Host smart-2f975d1e-2dc3-4663-8bed-9163ee9b5424
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2976976054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2976976054
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4085559053
Short name T285
Test name
Test status
Simulation time 90090679 ps
CPU time 0.79 seconds
Started Jul 27 06:33:50 PM PDT 24
Finished Jul 27 06:33:51 PM PDT 24
Peak memory 206156 kb
Host smart-3b0fc176-53a6-4754-9e80-48a08decb999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4085559053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.4085559053
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2329842570
Short name T2884
Test name
Test status
Simulation time 63118345 ps
CPU time 1 seconds
Started Jul 27 06:33:49 PM PDT 24
Finished Jul 27 06:33:50 PM PDT 24
Peak memory 206460 kb
Host smart-ef6e1e31-82d9-4d37-ae6c-9248a363aed2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2329842570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2329842570
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4217553521
Short name T2973
Test name
Test status
Simulation time 46082250 ps
CPU time 1.21 seconds
Started Jul 27 06:33:46 PM PDT 24
Finished Jul 27 06:33:48 PM PDT 24
Peak memory 206432 kb
Host smart-36433d3c-f301-4781-b58a-3e9a536992c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4217553521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.4217553521
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1429102077
Short name T1377
Test name
Test status
Simulation time 3786880329 ps
CPU time 5.59 seconds
Started Jul 27 07:32:39 PM PDT 24
Finished Jul 27 07:32:45 PM PDT 24
Peak memory 207380 kb
Host smart-1940b73b-3545-45a5-bc2c-93bea0604182
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429102077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.1429102077
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.177848343
Short name T2274
Test name
Test status
Simulation time 13352602898 ps
CPU time 17.73 seconds
Started Jul 27 07:32:40 PM PDT 24
Finished Jul 27 07:32:57 PM PDT 24
Peak memory 207360 kb
Host smart-00de5cb5-c028-4f02-ad93-4aacdaf6989c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=177848343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.177848343
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3586801484
Short name T871
Test name
Test status
Simulation time 23436961361 ps
CPU time 29.13 seconds
Started Jul 27 07:32:40 PM PDT 24
Finished Jul 27 07:33:10 PM PDT 24
Peak memory 207328 kb
Host smart-dedda7f9-4987-428a-a064-cf78aaad4f79
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586801484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.3586801484
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1406773618
Short name T593
Test name
Test status
Simulation time 176539639 ps
CPU time 0.89 seconds
Started Jul 27 07:32:41 PM PDT 24
Finished Jul 27 07:32:42 PM PDT 24
Peak memory 207144 kb
Host smart-c56fe321-0896-415d-8e64-3e87813c6484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14067
73618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1406773618
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.619117745
Short name T1633
Test name
Test status
Simulation time 185067339 ps
CPU time 0.85 seconds
Started Jul 27 07:32:40 PM PDT 24
Finished Jul 27 07:32:41 PM PDT 24
Peak memory 207112 kb
Host smart-59481571-6be1-4edc-b277-1a6d45373461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61911
7745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.619117745
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.3632148041
Short name T1075
Test name
Test status
Simulation time 624751631 ps
CPU time 1.86 seconds
Started Jul 27 07:32:44 PM PDT 24
Finished Jul 27 07:32:46 PM PDT 24
Peak memory 207352 kb
Host smart-ccc40e70-7933-4369-a97f-cfdb03e3acff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36321
48041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3632148041
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.4135902732
Short name T1778
Test name
Test status
Simulation time 1281581727 ps
CPU time 3.24 seconds
Started Jul 27 07:32:44 PM PDT 24
Finished Jul 27 07:32:48 PM PDT 24
Peak memory 207384 kb
Host smart-7694f73d-0d72-4982-b290-f02daafb2923
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4135902732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.4135902732
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.423412745
Short name T346
Test name
Test status
Simulation time 18973101234 ps
CPU time 42.64 seconds
Started Jul 27 07:32:51 PM PDT 24
Finished Jul 27 07:33:34 PM PDT 24
Peak memory 207372 kb
Host smart-064a9441-f2a6-491b-94d4-6310529d3b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42341
2745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.423412745
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.3304348594
Short name T813
Test name
Test status
Simulation time 1551441677 ps
CPU time 35.42 seconds
Started Jul 27 07:32:49 PM PDT 24
Finished Jul 27 07:33:25 PM PDT 24
Peak memory 207292 kb
Host smart-79188afb-b712-43b0-af9d-a4fd291a45a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304348594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.3304348594
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.2299004978
Short name T1244
Test name
Test status
Simulation time 322985388 ps
CPU time 1.24 seconds
Started Jul 27 07:32:49 PM PDT 24
Finished Jul 27 07:32:51 PM PDT 24
Peak memory 207072 kb
Host smart-28776de3-ad7f-4956-90a8-c9a15b0ba2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22990
04978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.2299004978
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.2106616318
Short name T1733
Test name
Test status
Simulation time 160995272 ps
CPU time 0.84 seconds
Started Jul 27 07:32:50 PM PDT 24
Finished Jul 27 07:32:51 PM PDT 24
Peak memory 207116 kb
Host smart-eddb6d41-9b74-4c05-978d-e3bb0cae407f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21066
16318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2106616318
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.1570985963
Short name T2175
Test name
Test status
Simulation time 33678571 ps
CPU time 0.7 seconds
Started Jul 27 07:32:48 PM PDT 24
Finished Jul 27 07:32:49 PM PDT 24
Peak memory 207104 kb
Host smart-552fc0df-f2f9-417b-8c52-0bd475125b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15709
85963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1570985963
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2467782889
Short name T1582
Test name
Test status
Simulation time 849689635 ps
CPU time 2.26 seconds
Started Jul 27 07:32:50 PM PDT 24
Finished Jul 27 07:32:52 PM PDT 24
Peak memory 207468 kb
Host smart-5e025a3b-cb19-4d46-a499-d84ee9fe1e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24677
82889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2467782889
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3940713941
Short name T2301
Test name
Test status
Simulation time 334742096 ps
CPU time 2.87 seconds
Started Jul 27 07:32:49 PM PDT 24
Finished Jul 27 07:32:51 PM PDT 24
Peak memory 207276 kb
Host smart-b362e1d6-358b-4bc4-8a5d-d717b5e58461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39407
13941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3940713941
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.2923931254
Short name T2530
Test name
Test status
Simulation time 88177095736 ps
CPU time 144.78 seconds
Started Jul 27 07:32:50 PM PDT 24
Finished Jul 27 07:35:15 PM PDT 24
Peak memory 207336 kb
Host smart-bd513223-ea93-45b4-a96e-f432fab2426d
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2923931254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2923931254
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2645964732
Short name T305
Test name
Test status
Simulation time 95221636034 ps
CPU time 148.24 seconds
Started Jul 27 07:32:48 PM PDT 24
Finished Jul 27 07:35:16 PM PDT 24
Peak memory 207476 kb
Host smart-d59029e1-80c1-4772-b2db-7e8784f42343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645964732 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2645964732
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.2405413869
Short name T2804
Test name
Test status
Simulation time 82162454572 ps
CPU time 116.8 seconds
Started Jul 27 07:32:50 PM PDT 24
Finished Jul 27 07:34:47 PM PDT 24
Peak memory 207428 kb
Host smart-f2e08f51-9060-4ce0-9b70-ea1bbbe720c0
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2405413869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.2405413869
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.460088995
Short name T866
Test name
Test status
Simulation time 166762713 ps
CPU time 0.89 seconds
Started Jul 27 07:32:51 PM PDT 24
Finished Jul 27 07:32:52 PM PDT 24
Peak memory 207132 kb
Host smart-a710e0de-2f49-47d8-9f41-12e9b35de967
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=460088995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.460088995
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.667368648
Short name T738
Test name
Test status
Simulation time 143887213 ps
CPU time 0.84 seconds
Started Jul 27 07:33:03 PM PDT 24
Finished Jul 27 07:33:04 PM PDT 24
Peak memory 207112 kb
Host smart-1e6b8131-5dec-4840-ae0a-6e8048fca6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66736
8648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.667368648
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.743422682
Short name T2005
Test name
Test status
Simulation time 217211248 ps
CPU time 0.95 seconds
Started Jul 27 07:32:57 PM PDT 24
Finished Jul 27 07:32:58 PM PDT 24
Peak memory 207132 kb
Host smart-621fed09-fb23-4ff9-a182-36f5afad7f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74342
2682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.743422682
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.3995978290
Short name T453
Test name
Test status
Simulation time 7938553873 ps
CPU time 61.43 seconds
Started Jul 27 07:32:51 PM PDT 24
Finished Jul 27 07:33:52 PM PDT 24
Peak memory 216876 kb
Host smart-07b9b5b9-255b-484c-adfd-d873dda5e0b3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3995978290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.3995978290
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.1243265080
Short name T1437
Test name
Test status
Simulation time 6354809445 ps
CPU time 44.23 seconds
Started Jul 27 07:32:58 PM PDT 24
Finished Jul 27 07:33:43 PM PDT 24
Peak memory 207340 kb
Host smart-f734773b-1624-4357-a6dd-41a596106285
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1243265080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.1243265080
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.2858175088
Short name T2858
Test name
Test status
Simulation time 244356445 ps
CPU time 1.05 seconds
Started Jul 27 07:32:56 PM PDT 24
Finished Jul 27 07:32:57 PM PDT 24
Peak memory 207132 kb
Host smart-56dad946-b973-4a92-a807-24d86e7738de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28581
75088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2858175088
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.1135187372
Short name T61
Test name
Test status
Simulation time 430915307 ps
CPU time 1.38 seconds
Started Jul 27 07:32:59 PM PDT 24
Finished Jul 27 07:33:00 PM PDT 24
Peak memory 207140 kb
Host smart-d0593416-bd44-4f4d-9fd8-eb46946cf491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11351
87372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.1135187372
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.1752567865
Short name T2548
Test name
Test status
Simulation time 23266693476 ps
CPU time 29.76 seconds
Started Jul 27 07:32:57 PM PDT 24
Finished Jul 27 07:33:26 PM PDT 24
Peak memory 207280 kb
Host smart-ba272d16-66a9-425b-bbdc-e93cb8bb2d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17525
67865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.1752567865
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.2833889553
Short name T461
Test name
Test status
Simulation time 3363361522 ps
CPU time 5.37 seconds
Started Jul 27 07:33:01 PM PDT 24
Finished Jul 27 07:33:07 PM PDT 24
Peak memory 207372 kb
Host smart-eb4f7121-b3d4-409c-9876-e00af535bde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28338
89553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.2833889553
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3207794921
Short name T2249
Test name
Test status
Simulation time 6696540617 ps
CPU time 62.44 seconds
Started Jul 27 07:33:03 PM PDT 24
Finished Jul 27 07:34:06 PM PDT 24
Peak memory 217760 kb
Host smart-5e990632-d79b-4732-a4da-e6ba2f0db065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32077
94921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3207794921
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3651927318
Short name T395
Test name
Test status
Simulation time 3980869146 ps
CPU time 115.02 seconds
Started Jul 27 07:32:59 PM PDT 24
Finished Jul 27 07:34:54 PM PDT 24
Peak memory 215620 kb
Host smart-73a5d524-ee82-41a5-8f90-7fdb8cde95d2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3651927318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3651927318
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1762797884
Short name T2708
Test name
Test status
Simulation time 248397200 ps
CPU time 1.03 seconds
Started Jul 27 07:32:58 PM PDT 24
Finished Jul 27 07:32:59 PM PDT 24
Peak memory 207140 kb
Host smart-f28f8535-5bd3-4208-a126-188d181e1793
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1762797884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1762797884
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1582898535
Short name T978
Test name
Test status
Simulation time 202129980 ps
CPU time 0.91 seconds
Started Jul 27 07:32:57 PM PDT 24
Finished Jul 27 07:32:58 PM PDT 24
Peak memory 207108 kb
Host smart-e0590d4a-73f5-4f0a-8f5f-93387983b5fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15828
98535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1582898535
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.1865712200
Short name T531
Test name
Test status
Simulation time 5030619593 ps
CPU time 141.79 seconds
Started Jul 27 07:32:58 PM PDT 24
Finished Jul 27 07:35:20 PM PDT 24
Peak memory 215536 kb
Host smart-942c971a-b80e-4353-a82e-814610e4a44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18657
12200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.1865712200
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.311935792
Short name T2803
Test name
Test status
Simulation time 5746446196 ps
CPU time 40.76 seconds
Started Jul 27 07:32:56 PM PDT 24
Finished Jul 27 07:33:37 PM PDT 24
Peak memory 217036 kb
Host smart-5c6d0079-ee5d-4b6b-bdf3-8a0149ba038f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=311935792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.311935792
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.2285896909
Short name T1509
Test name
Test status
Simulation time 166212899 ps
CPU time 0.89 seconds
Started Jul 27 07:32:57 PM PDT 24
Finished Jul 27 07:32:58 PM PDT 24
Peak memory 207124 kb
Host smart-40ef84b2-a1ad-4792-ab3c-5ca2ba74eb45
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2285896909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.2285896909
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2965694765
Short name T844
Test name
Test status
Simulation time 176330234 ps
CPU time 0.85 seconds
Started Jul 27 07:33:07 PM PDT 24
Finished Jul 27 07:33:08 PM PDT 24
Peak memory 207120 kb
Host smart-f98408bf-245d-4e89-96a4-947d80c3059a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29656
94765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2965694765
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2082924710
Short name T62
Test name
Test status
Simulation time 486758238 ps
CPU time 1.53 seconds
Started Jul 27 07:33:05 PM PDT 24
Finished Jul 27 07:33:07 PM PDT 24
Peak memory 207116 kb
Host smart-49293109-fc2e-47ba-b694-a3d3ba0b0cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20829
24710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2082924710
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.1865966562
Short name T2106
Test name
Test status
Simulation time 248380403 ps
CPU time 1 seconds
Started Jul 27 07:33:08 PM PDT 24
Finished Jul 27 07:33:09 PM PDT 24
Peak memory 207132 kb
Host smart-bb71f134-3f9a-49e5-a73a-a322486709b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18659
66562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.1865966562
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.7312016
Short name T2409
Test name
Test status
Simulation time 180704471 ps
CPU time 0.88 seconds
Started Jul 27 07:33:05 PM PDT 24
Finished Jul 27 07:33:06 PM PDT 24
Peak memory 207100 kb
Host smart-89bbecb3-4d9e-4c18-96ba-11b09ac43010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73120
16 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.7312016
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.19880181
Short name T2761
Test name
Test status
Simulation time 180984372 ps
CPU time 0.88 seconds
Started Jul 27 07:33:06 PM PDT 24
Finished Jul 27 07:33:07 PM PDT 24
Peak memory 207120 kb
Host smart-03bed9f1-113c-4610-bde0-fde333c66f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19880
181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.19880181
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.4187796547
Short name T191
Test name
Test status
Simulation time 164009006 ps
CPU time 0.82 seconds
Started Jul 27 07:33:06 PM PDT 24
Finished Jul 27 07:33:07 PM PDT 24
Peak memory 207120 kb
Host smart-ada8ec05-9046-418e-ab73-4a6fed28bef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41877
96547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.4187796547
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1026258964
Short name T2315
Test name
Test status
Simulation time 153025579 ps
CPU time 0.85 seconds
Started Jul 27 07:33:06 PM PDT 24
Finished Jul 27 07:33:07 PM PDT 24
Peak memory 207092 kb
Host smart-5ca08b89-25bf-4a3b-8a41-afb49c1ea6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10262
58964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1026258964
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.500996430
Short name T1606
Test name
Test status
Simulation time 221748927 ps
CPU time 1.01 seconds
Started Jul 27 07:33:07 PM PDT 24
Finished Jul 27 07:33:08 PM PDT 24
Peak memory 207100 kb
Host smart-efd8e4be-d908-4f84-8e4c-d2c76d71f6f5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=500996430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.500996430
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.399999814
Short name T1706
Test name
Test status
Simulation time 243042019 ps
CPU time 0.98 seconds
Started Jul 27 07:33:05 PM PDT 24
Finished Jul 27 07:33:06 PM PDT 24
Peak memory 207336 kb
Host smart-f5e801a4-6921-4475-a391-f393ee7989b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39999
9814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.399999814
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.3755655514
Short name T940
Test name
Test status
Simulation time 262202991 ps
CPU time 1 seconds
Started Jul 27 07:33:07 PM PDT 24
Finished Jul 27 07:33:08 PM PDT 24
Peak memory 207108 kb
Host smart-27808d3a-d295-4706-ac33-333e97994389
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3755655514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.3755655514
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.810192682
Short name T211
Test name
Test status
Simulation time 201927566 ps
CPU time 0.98 seconds
Started Jul 27 07:33:06 PM PDT 24
Finished Jul 27 07:33:07 PM PDT 24
Peak memory 207136 kb
Host smart-04cda7ae-9b81-49ca-8303-134bcefb2fd8
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=810192682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.810192682
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2255189854
Short name T2843
Test name
Test status
Simulation time 32087915 ps
CPU time 0.66 seconds
Started Jul 27 07:33:05 PM PDT 24
Finished Jul 27 07:33:06 PM PDT 24
Peak memory 207036 kb
Host smart-a050a7e5-dc44-4d09-b47f-4858bf8ac727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22551
89854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2255189854
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.939282568
Short name T2547
Test name
Test status
Simulation time 18792953263 ps
CPU time 48.64 seconds
Started Jul 27 07:33:16 PM PDT 24
Finished Jul 27 07:34:05 PM PDT 24
Peak memory 223804 kb
Host smart-f7a02b4b-8be9-4ec7-b569-7f55837cf957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93928
2568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.939282568
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.509889935
Short name T1724
Test name
Test status
Simulation time 207073293 ps
CPU time 0.94 seconds
Started Jul 27 07:33:12 PM PDT 24
Finished Jul 27 07:33:13 PM PDT 24
Peak memory 207116 kb
Host smart-32b0f7ed-5f77-408d-bbff-e28ae9a02d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50988
9935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.509889935
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1843253730
Short name T154
Test name
Test status
Simulation time 197904529 ps
CPU time 0.92 seconds
Started Jul 27 07:33:10 PM PDT 24
Finished Jul 27 07:33:11 PM PDT 24
Peak memory 207192 kb
Host smart-63f09b60-e41b-4751-bdfc-ff3eb6ccdc2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18432
53730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1843253730
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2564090648
Short name T186
Test name
Test status
Simulation time 8717866690 ps
CPU time 45.44 seconds
Started Jul 27 07:33:12 PM PDT 24
Finished Jul 27 07:33:57 PM PDT 24
Peak memory 215472 kb
Host smart-2bc469b4-902e-43b4-ab6a-b05182054ac9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564090648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2564090648
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2455190787
Short name T168
Test name
Test status
Simulation time 8604811078 ps
CPU time 133.45 seconds
Started Jul 27 07:33:11 PM PDT 24
Finished Jul 27 07:35:25 PM PDT 24
Peak memory 215484 kb
Host smart-cdd51f3b-2914-4f9c-ae35-63ff31b8502d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2455190787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2455190787
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.3513671181
Short name T651
Test name
Test status
Simulation time 14342688336 ps
CPU time 101.38 seconds
Started Jul 27 07:33:10 PM PDT 24
Finished Jul 27 07:34:52 PM PDT 24
Peak memory 223740 kb
Host smart-6788c1ca-22dd-43d7-971a-660d74fa031c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513671181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.3513671181
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3968829215
Short name T2797
Test name
Test status
Simulation time 162246471 ps
CPU time 0.91 seconds
Started Jul 27 07:33:12 PM PDT 24
Finished Jul 27 07:33:13 PM PDT 24
Peak memory 207104 kb
Host smart-d3033b5b-c6d5-4d6a-924b-5de8f9d92b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39688
29215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3968829215
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.1451562866
Short name T2755
Test name
Test status
Simulation time 186059284 ps
CPU time 0.89 seconds
Started Jul 27 07:33:10 PM PDT 24
Finished Jul 27 07:33:11 PM PDT 24
Peak memory 207072 kb
Host smart-d6b3ede3-d503-4157-af95-ad05256703e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14515
62866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.1451562866
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.233949920
Short name T1449
Test name
Test status
Simulation time 201705052 ps
CPU time 0.9 seconds
Started Jul 27 07:33:12 PM PDT 24
Finished Jul 27 07:33:13 PM PDT 24
Peak memory 207060 kb
Host smart-931e298a-f824-4041-aea4-e79c1524dee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23394
9920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.233949920
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.862734382
Short name T1895
Test name
Test status
Simulation time 196738452 ps
CPU time 0.97 seconds
Started Jul 27 07:33:11 PM PDT 24
Finished Jul 27 07:33:12 PM PDT 24
Peak memory 207044 kb
Host smart-b1a7cfba-2327-43b6-bd44-f9427b1cc08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86273
4382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.862734382
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.4270564788
Short name T697
Test name
Test status
Simulation time 156099544 ps
CPU time 0.84 seconds
Started Jul 27 07:33:11 PM PDT 24
Finished Jul 27 07:33:12 PM PDT 24
Peak memory 207056 kb
Host smart-c4aeadc1-8259-411e-a124-2bf654f605d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42705
64788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.4270564788
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1604052043
Short name T2652
Test name
Test status
Simulation time 159560830 ps
CPU time 0.84 seconds
Started Jul 27 07:33:16 PM PDT 24
Finished Jul 27 07:33:17 PM PDT 24
Peak memory 207144 kb
Host smart-98971827-31e8-4253-b2aa-1d9cba7865fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16040
52043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1604052043
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1317900709
Short name T2197
Test name
Test status
Simulation time 236195619 ps
CPU time 1.04 seconds
Started Jul 27 07:33:13 PM PDT 24
Finished Jul 27 07:33:14 PM PDT 24
Peak memory 207088 kb
Host smart-d8a2ee36-ce19-409d-9dad-a32edf5564e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13179
00709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1317900709
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.1725911830
Short name T1454
Test name
Test status
Simulation time 5274513811 ps
CPU time 41.89 seconds
Started Jul 27 07:33:18 PM PDT 24
Finished Jul 27 07:34:00 PM PDT 24
Peak memory 215580 kb
Host smart-de98d76c-0c87-4eb7-a2b4-674d31c79e67
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1725911830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1725911830
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.132271780
Short name T1422
Test name
Test status
Simulation time 187751654 ps
CPU time 0.9 seconds
Started Jul 27 07:33:24 PM PDT 24
Finished Jul 27 07:33:26 PM PDT 24
Peak memory 207140 kb
Host smart-09090908-6f0d-4867-84ee-0162c6f6fe80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13227
1780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.132271780
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3905670197
Short name T2593
Test name
Test status
Simulation time 193981509 ps
CPU time 0.88 seconds
Started Jul 27 07:33:17 PM PDT 24
Finished Jul 27 07:33:18 PM PDT 24
Peak memory 207132 kb
Host smart-11b342e4-b50e-4162-aca2-95b8c1d4b32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39056
70197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3905670197
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1437458199
Short name T502
Test name
Test status
Simulation time 523693406 ps
CPU time 1.72 seconds
Started Jul 27 07:33:18 PM PDT 24
Finished Jul 27 07:33:19 PM PDT 24
Peak memory 206996 kb
Host smart-1b5d2524-1894-4565-8dc7-4f843f715e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14374
58199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1437458199
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.2740117010
Short name T1198
Test name
Test status
Simulation time 4969880749 ps
CPU time 145.18 seconds
Started Jul 27 07:33:24 PM PDT 24
Finished Jul 27 07:35:50 PM PDT 24
Peak memory 215572 kb
Host smart-4a002201-c54e-4de9-9345-85f1acf95867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27401
17010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.2740117010
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.1957656863
Short name T1381
Test name
Test status
Simulation time 1251751542 ps
CPU time 29.51 seconds
Started Jul 27 07:32:48 PM PDT 24
Finished Jul 27 07:33:18 PM PDT 24
Peak memory 207296 kb
Host smart-c89db3d4-658f-4499-8c3a-6a6cd37f9f08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957656863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host
_handshake.1957656863
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.2508020457
Short name T634
Test name
Test status
Simulation time 50729908 ps
CPU time 0.67 seconds
Started Jul 27 07:33:44 PM PDT 24
Finished Jul 27 07:33:45 PM PDT 24
Peak memory 207164 kb
Host smart-a7e02bdf-278f-496c-8e83-e9ab47eacc2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2508020457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.2508020457
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.3175540789
Short name T434
Test name
Test status
Simulation time 3525648649 ps
CPU time 5.79 seconds
Started Jul 27 07:33:19 PM PDT 24
Finished Jul 27 07:33:25 PM PDT 24
Peak memory 207400 kb
Host smart-dfbd8099-2159-4df5-aebb-856a9e5ec874
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175540789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.3175540789
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1800122469
Short name T2010
Test name
Test status
Simulation time 23331611625 ps
CPU time 33.3 seconds
Started Jul 27 07:33:17 PM PDT 24
Finished Jul 27 07:33:50 PM PDT 24
Peak memory 207388 kb
Host smart-f65132e1-4961-4c29-bb05-86c2ce4fda5b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800122469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.1800122469
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3302704238
Short name T1255
Test name
Test status
Simulation time 191287565 ps
CPU time 0.91 seconds
Started Jul 27 07:33:18 PM PDT 24
Finished Jul 27 07:33:19 PM PDT 24
Peak memory 207092 kb
Host smart-38eedbaf-1285-487c-89aa-786513a7e99a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33027
04238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3302704238
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.2374649924
Short name T45
Test name
Test status
Simulation time 153650994 ps
CPU time 0.86 seconds
Started Jul 27 07:33:24 PM PDT 24
Finished Jul 27 07:33:25 PM PDT 24
Peak memory 207136 kb
Host smart-6f06b349-8913-4aa4-857e-a9c30e39930b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23746
49924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2374649924
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.203736398
Short name T1330
Test name
Test status
Simulation time 638140638 ps
CPU time 1.96 seconds
Started Jul 27 07:33:23 PM PDT 24
Finished Jul 27 07:33:25 PM PDT 24
Peak memory 207140 kb
Host smart-ee059f88-303f-4c66-b4ed-3c782559bd7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20373
6398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.203736398
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.470060413
Short name T1808
Test name
Test status
Simulation time 1160365951 ps
CPU time 2.92 seconds
Started Jul 27 07:33:23 PM PDT 24
Finished Jul 27 07:33:26 PM PDT 24
Peak memory 207356 kb
Host smart-14ba6563-38f9-4654-9b17-9311573e6dd6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=470060413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.470060413
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.955358481
Short name T1939
Test name
Test status
Simulation time 18074464712 ps
CPU time 36.21 seconds
Started Jul 27 07:33:23 PM PDT 24
Finished Jul 27 07:33:59 PM PDT 24
Peak memory 207396 kb
Host smart-1129b6df-9b8c-4530-a85a-35acba9643ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95535
8481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.955358481
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.2809654205
Short name T920
Test name
Test status
Simulation time 2507534789 ps
CPU time 20.81 seconds
Started Jul 27 07:33:23 PM PDT 24
Finished Jul 27 07:33:44 PM PDT 24
Peak memory 207440 kb
Host smart-0bbad98a-7347-46aa-87c8-0bab92774184
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809654205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.2809654205
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.3466801287
Short name T291
Test name
Test status
Simulation time 449761119 ps
CPU time 1.35 seconds
Started Jul 27 07:33:27 PM PDT 24
Finished Jul 27 07:33:29 PM PDT 24
Peak memory 207036 kb
Host smart-da002034-056a-430d-9e7f-c37d86df2749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34668
01287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.3466801287
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.4188493504
Short name T2446
Test name
Test status
Simulation time 175997565 ps
CPU time 0.84 seconds
Started Jul 27 07:33:27 PM PDT 24
Finished Jul 27 07:33:28 PM PDT 24
Peak memory 207040 kb
Host smart-85a860c8-09f1-4982-97f6-d8ffad883a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41884
93504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.4188493504
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3982075796
Short name T831
Test name
Test status
Simulation time 40739019 ps
CPU time 0.71 seconds
Started Jul 27 07:33:26 PM PDT 24
Finished Jul 27 07:33:27 PM PDT 24
Peak memory 207116 kb
Host smart-1080dc63-81f4-4c0d-8bfa-58a5a4389c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39820
75796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3982075796
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.391789202
Short name T2615
Test name
Test status
Simulation time 860728371 ps
CPU time 2.49 seconds
Started Jul 27 07:33:24 PM PDT 24
Finished Jul 27 07:33:26 PM PDT 24
Peak memory 207416 kb
Host smart-2f8275de-2309-4d0d-a500-6b0bae7c5995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39178
9202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.391789202
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.2553339086
Short name T726
Test name
Test status
Simulation time 85253145333 ps
CPU time 137.3 seconds
Started Jul 27 07:33:23 PM PDT 24
Finished Jul 27 07:35:41 PM PDT 24
Peak memory 207420 kb
Host smart-889bdfa3-0576-43a8-bc3d-2e0ccfacc9e0
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2553339086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.2553339086
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.4114969573
Short name T303
Test name
Test status
Simulation time 118434336290 ps
CPU time 193.6 seconds
Started Jul 27 07:33:27 PM PDT 24
Finished Jul 27 07:36:41 PM PDT 24
Peak memory 207276 kb
Host smart-f49d0d86-dc7e-4532-ac90-ec5571cc1a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114969573 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.4114969573
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.276016559
Short name T1040
Test name
Test status
Simulation time 120097855630 ps
CPU time 192.64 seconds
Started Jul 27 07:33:24 PM PDT 24
Finished Jul 27 07:36:37 PM PDT 24
Peak memory 207384 kb
Host smart-bf397665-2aea-4b20-b68f-f312730dae78
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=276016559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.276016559
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.948956326
Short name T2458
Test name
Test status
Simulation time 98124986491 ps
CPU time 156.04 seconds
Started Jul 27 07:33:23 PM PDT 24
Finished Jul 27 07:35:59 PM PDT 24
Peak memory 207344 kb
Host smart-02d502eb-a1bf-42d5-ba00-0b0166106087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948956326 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.948956326
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.1827903991
Short name T2497
Test name
Test status
Simulation time 117177791978 ps
CPU time 193.95 seconds
Started Jul 27 07:33:27 PM PDT 24
Finished Jul 27 07:36:41 PM PDT 24
Peak memory 207416 kb
Host smart-46026fc3-f77b-4bb0-a555-27ac37adb99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18279
03991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.1827903991
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2900232221
Short name T370
Test name
Test status
Simulation time 270439559 ps
CPU time 1.14 seconds
Started Jul 27 07:33:24 PM PDT 24
Finished Jul 27 07:33:26 PM PDT 24
Peak memory 207324 kb
Host smart-97d59198-f3d0-457f-bbf6-ceacd259c7c1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2900232221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2900232221
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3895920140
Short name T2857
Test name
Test status
Simulation time 162427928 ps
CPU time 0.86 seconds
Started Jul 27 07:33:28 PM PDT 24
Finished Jul 27 07:33:29 PM PDT 24
Peak memory 207112 kb
Host smart-e4d6a6d5-9a08-4618-a756-12344b1285e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38959
20140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3895920140
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3568836718
Short name T1563
Test name
Test status
Simulation time 218613400 ps
CPU time 0.97 seconds
Started Jul 27 07:33:23 PM PDT 24
Finished Jul 27 07:33:24 PM PDT 24
Peak memory 207116 kb
Host smart-7d64d03c-fcf6-4214-804d-c5b2530e10fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35688
36718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3568836718
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.3093893026
Short name T1356
Test name
Test status
Simulation time 8495261391 ps
CPU time 243.15 seconds
Started Jul 27 07:33:25 PM PDT 24
Finished Jul 27 07:37:28 PM PDT 24
Peak memory 215584 kb
Host smart-c946164b-1b71-48fa-8e1a-8ca0df3075f5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3093893026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.3093893026
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.2711058077
Short name T991
Test name
Test status
Simulation time 12639338751 ps
CPU time 83.41 seconds
Started Jul 27 07:33:32 PM PDT 24
Finished Jul 27 07:34:55 PM PDT 24
Peak memory 207352 kb
Host smart-7743de76-da69-4bc1-a13d-fd52a8574720
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2711058077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.2711058077
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.671435502
Short name T2179
Test name
Test status
Simulation time 194787517 ps
CPU time 0.94 seconds
Started Jul 27 07:33:30 PM PDT 24
Finished Jul 27 07:33:31 PM PDT 24
Peak memory 207144 kb
Host smart-4714b52c-dc7c-4940-985a-2c4e6e47f69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67143
5502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.671435502
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.162712699
Short name T1749
Test name
Test status
Simulation time 23353028056 ps
CPU time 27.89 seconds
Started Jul 27 07:33:31 PM PDT 24
Finished Jul 27 07:33:59 PM PDT 24
Peak memory 207292 kb
Host smart-4e293cdc-0b6d-43fb-ae41-324ed1453bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16271
2699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.162712699
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.2824072047
Short name T1018
Test name
Test status
Simulation time 3373336643 ps
CPU time 5.01 seconds
Started Jul 27 07:33:30 PM PDT 24
Finished Jul 27 07:33:35 PM PDT 24
Peak memory 207384 kb
Host smart-bc2a9463-d135-4eef-bfc5-edef11006568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28240
72047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.2824072047
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2472145471
Short name T1649
Test name
Test status
Simulation time 7187584506 ps
CPU time 51.66 seconds
Started Jul 27 07:33:30 PM PDT 24
Finished Jul 27 07:34:22 PM PDT 24
Peak memory 217676 kb
Host smart-04f91f24-0a79-44dd-80a2-02fc8dbddb9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24721
45471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2472145471
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.2996284679
Short name T2176
Test name
Test status
Simulation time 4964805521 ps
CPU time 140.2 seconds
Started Jul 27 07:33:29 PM PDT 24
Finished Jul 27 07:35:49 PM PDT 24
Peak memory 223484 kb
Host smart-a571ef68-a011-47c9-8fd2-e0574ffd92cb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2996284679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2996284679
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.2354000552
Short name T2666
Test name
Test status
Simulation time 251396258 ps
CPU time 1.04 seconds
Started Jul 27 07:33:30 PM PDT 24
Finished Jul 27 07:33:31 PM PDT 24
Peak memory 207172 kb
Host smart-57d3fe06-d671-4965-9faf-68e5412a7318
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2354000552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.2354000552
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.4223641456
Short name T1331
Test name
Test status
Simulation time 192068618 ps
CPU time 0.96 seconds
Started Jul 27 07:33:32 PM PDT 24
Finished Jul 27 07:33:33 PM PDT 24
Peak memory 207080 kb
Host smart-b96c619e-971a-4a0c-af7a-726a8db7e312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42236
41456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.4223641456
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.4179875658
Short name T2614
Test name
Test status
Simulation time 4524178833 ps
CPU time 32.93 seconds
Started Jul 27 07:33:31 PM PDT 24
Finished Jul 27 07:34:04 PM PDT 24
Peak memory 216968 kb
Host smart-6068e676-6b59-4b61-aa16-d9518175c285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41798
75658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.4179875658
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.4207244920
Short name T94
Test name
Test status
Simulation time 5202865188 ps
CPU time 39.19 seconds
Started Jul 27 07:33:32 PM PDT 24
Finished Jul 27 07:34:12 PM PDT 24
Peak memory 207308 kb
Host smart-624ed629-6adc-4cff-8cf5-858500d213d7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4207244920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.4207244920
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2467391448
Short name T1933
Test name
Test status
Simulation time 170250154 ps
CPU time 0.85 seconds
Started Jul 27 07:33:30 PM PDT 24
Finished Jul 27 07:33:31 PM PDT 24
Peak memory 207212 kb
Host smart-7998e105-f159-434c-a3f5-e3b244f337ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2467391448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2467391448
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.4207651965
Short name T1552
Test name
Test status
Simulation time 175754411 ps
CPU time 0.85 seconds
Started Jul 27 07:33:30 PM PDT 24
Finished Jul 27 07:33:31 PM PDT 24
Peak memory 207108 kb
Host smart-6af2e206-7800-4bbe-a273-28d76aacdb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42076
51965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.4207651965
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3981429456
Short name T114
Test name
Test status
Simulation time 153140185 ps
CPU time 0.87 seconds
Started Jul 27 07:33:30 PM PDT 24
Finished Jul 27 07:33:31 PM PDT 24
Peak memory 207112 kb
Host smart-84267b51-fc5d-449b-a73f-59b741d77aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39814
29456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3981429456
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3054986264
Short name T608
Test name
Test status
Simulation time 178142166 ps
CPU time 0.89 seconds
Started Jul 27 07:33:33 PM PDT 24
Finished Jul 27 07:33:34 PM PDT 24
Peak memory 207036 kb
Host smart-04bc808d-8672-4d04-8f8a-a8043e63c534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30549
86264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3054986264
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1056547647
Short name T1962
Test name
Test status
Simulation time 202972287 ps
CPU time 0.85 seconds
Started Jul 27 07:33:30 PM PDT 24
Finished Jul 27 07:33:31 PM PDT 24
Peak memory 207112 kb
Host smart-d644e07e-0ebf-4c7e-8ca6-fa8c44b5f965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10565
47647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1056547647
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3237289022
Short name T767
Test name
Test status
Simulation time 154760666 ps
CPU time 0.87 seconds
Started Jul 27 07:33:33 PM PDT 24
Finished Jul 27 07:33:34 PM PDT 24
Peak memory 207028 kb
Host smart-47fc24c6-2545-49f4-b6f5-d03a1022fbee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32372
89022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3237289022
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.2280612652
Short name T1918
Test name
Test status
Simulation time 228492741 ps
CPU time 1.04 seconds
Started Jul 27 07:33:30 PM PDT 24
Finished Jul 27 07:33:32 PM PDT 24
Peak memory 207040 kb
Host smart-528d10f7-6834-49e8-8189-42af97109dc9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2280612652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.2280612652
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.1764199652
Short name T1525
Test name
Test status
Simulation time 201862180 ps
CPU time 1.02 seconds
Started Jul 27 07:33:40 PM PDT 24
Finished Jul 27 07:33:41 PM PDT 24
Peak memory 207012 kb
Host smart-adbeff4f-07db-4b04-9ff0-e8e8c416c7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17641
99652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.1764199652
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1004706965
Short name T989
Test name
Test status
Simulation time 146221413 ps
CPU time 0.78 seconds
Started Jul 27 07:33:36 PM PDT 24
Finished Jul 27 07:33:37 PM PDT 24
Peak memory 207112 kb
Host smart-397a52e0-ca04-4329-a989-930a81da9549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10047
06965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1004706965
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3073225920
Short name T2084
Test name
Test status
Simulation time 37446407 ps
CPU time 0.65 seconds
Started Jul 27 07:33:36 PM PDT 24
Finished Jul 27 07:33:37 PM PDT 24
Peak memory 207100 kb
Host smart-1d8629bf-f06e-4bb4-bc1c-d36f7cd0616c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30732
25920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3073225920
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2096009238
Short name T2573
Test name
Test status
Simulation time 19434694797 ps
CPU time 44.17 seconds
Started Jul 27 07:33:37 PM PDT 24
Finished Jul 27 07:34:22 PM PDT 24
Peak memory 215668 kb
Host smart-f8e29771-8e33-4a50-bbc0-2cd53ebdaed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20960
09238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2096009238
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.4041575588
Short name T1151
Test name
Test status
Simulation time 183910945 ps
CPU time 0.98 seconds
Started Jul 27 07:33:39 PM PDT 24
Finished Jul 27 07:33:40 PM PDT 24
Peak memory 207116 kb
Host smart-9a6836b6-1bde-42e4-8692-e05447588db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40415
75588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.4041575588
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2992057789
Short name T2424
Test name
Test status
Simulation time 241574966 ps
CPU time 1.02 seconds
Started Jul 27 07:33:40 PM PDT 24
Finished Jul 27 07:33:41 PM PDT 24
Peak memory 206984 kb
Host smart-3abe17ee-f7c1-4446-9f57-acca75b55de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29920
57789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2992057789
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1494558940
Short name T2632
Test name
Test status
Simulation time 7253362477 ps
CPU time 30.3 seconds
Started Jul 27 07:33:39 PM PDT 24
Finished Jul 27 07:34:09 PM PDT 24
Peak memory 218212 kb
Host smart-8095fd4b-0072-4767-b706-9005dba814c8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494558940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1494558940
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3766980091
Short name T967
Test name
Test status
Simulation time 10307241372 ps
CPU time 216.83 seconds
Started Jul 27 07:33:36 PM PDT 24
Finished Jul 27 07:37:13 PM PDT 24
Peak memory 215584 kb
Host smart-2620a9e8-d094-4e22-9fba-3112cf35d042
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766980091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3766980091
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3282341725
Short name T2672
Test name
Test status
Simulation time 223573567 ps
CPU time 1.05 seconds
Started Jul 27 07:33:38 PM PDT 24
Finished Jul 27 07:33:39 PM PDT 24
Peak memory 207144 kb
Host smart-50d276fe-6d7d-4997-8632-867caffdb7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32823
41725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3282341725
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.2230755064
Short name T1818
Test name
Test status
Simulation time 149266906 ps
CPU time 0.83 seconds
Started Jul 27 07:33:37 PM PDT 24
Finished Jul 27 07:33:38 PM PDT 24
Peak memory 207068 kb
Host smart-bb1916f9-b134-4e48-8438-518ba6ea5e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22307
55064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2230755064
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.271291396
Short name T72
Test name
Test status
Simulation time 194966686 ps
CPU time 0.89 seconds
Started Jul 27 07:33:47 PM PDT 24
Finished Jul 27 07:33:48 PM PDT 24
Peak memory 207132 kb
Host smart-78108c86-0d53-478b-862b-6a94c34bb462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27129
1396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.271291396
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3581195492
Short name T217
Test name
Test status
Simulation time 1119639618 ps
CPU time 2.03 seconds
Started Jul 27 07:33:46 PM PDT 24
Finished Jul 27 07:33:48 PM PDT 24
Peak memory 223936 kb
Host smart-3d2ec8bd-f106-4bb3-b70f-3348fb022684
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3581195492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3581195492
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.2794324146
Short name T46
Test name
Test status
Simulation time 531170458 ps
CPU time 1.61 seconds
Started Jul 27 07:33:45 PM PDT 24
Finished Jul 27 07:33:47 PM PDT 24
Peak memory 207056 kb
Host smart-a30a58a0-90d2-4472-a490-de4c11f377c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27943
24146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.2794324146
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.1464300932
Short name T1393
Test name
Test status
Simulation time 210181279 ps
CPU time 0.94 seconds
Started Jul 27 07:33:44 PM PDT 24
Finished Jul 27 07:33:45 PM PDT 24
Peak memory 207136 kb
Host smart-dde0d52a-af43-4d23-98a0-e8f2d9f2fce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14643
00932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.1464300932
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.4211335805
Short name T1890
Test name
Test status
Simulation time 239031928 ps
CPU time 0.91 seconds
Started Jul 27 07:33:44 PM PDT 24
Finished Jul 27 07:33:45 PM PDT 24
Peak memory 207000 kb
Host smart-a0923f56-a5f2-4878-96db-565c64fb1c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42113
35805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.4211335805
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2962330624
Short name T1968
Test name
Test status
Simulation time 146129179 ps
CPU time 0.87 seconds
Started Jul 27 07:33:45 PM PDT 24
Finished Jul 27 07:33:46 PM PDT 24
Peak memory 207104 kb
Host smart-2d61f32b-47db-4bc0-bf27-835bbe6af9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29623
30624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2962330624
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2511948530
Short name T607
Test name
Test status
Simulation time 265118053 ps
CPU time 1.05 seconds
Started Jul 27 07:33:43 PM PDT 24
Finished Jul 27 07:33:45 PM PDT 24
Peak memory 207148 kb
Host smart-4ba9e0a6-8116-4a9f-9e6b-de9ce0bae314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25119
48530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2511948530
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.3709592442
Short name T465
Test name
Test status
Simulation time 6565046882 ps
CPU time 190.33 seconds
Started Jul 27 07:33:43 PM PDT 24
Finished Jul 27 07:36:53 PM PDT 24
Peak memory 215604 kb
Host smart-dbb109f8-7dae-45a8-9fbd-985d129a75c8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3709592442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.3709592442
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1758607128
Short name T1759
Test name
Test status
Simulation time 181160890 ps
CPU time 0.93 seconds
Started Jul 27 07:33:44 PM PDT 24
Finished Jul 27 07:33:45 PM PDT 24
Peak memory 207096 kb
Host smart-80403560-a26c-4f4f-b9bb-7eca09ee53fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17586
07128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1758607128
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3724750794
Short name T1471
Test name
Test status
Simulation time 160298302 ps
CPU time 0.9 seconds
Started Jul 27 07:33:45 PM PDT 24
Finished Jul 27 07:33:46 PM PDT 24
Peak memory 207104 kb
Host smart-893ea9a9-5e4a-4fb6-ad2a-dabceed9b718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37247
50794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3724750794
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.1711126181
Short name T653
Test name
Test status
Simulation time 666819698 ps
CPU time 1.81 seconds
Started Jul 27 07:33:46 PM PDT 24
Finished Jul 27 07:33:48 PM PDT 24
Peak memory 207096 kb
Host smart-bed215a1-8d9e-4d53-a5cf-0885463fd254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17111
26181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.1711126181
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.908734000
Short name T2338
Test name
Test status
Simulation time 5000928619 ps
CPU time 39.29 seconds
Started Jul 27 07:33:46 PM PDT 24
Finished Jul 27 07:34:25 PM PDT 24
Peak memory 217088 kb
Host smart-7ee817ea-704e-4c8f-be80-0b7126a03cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90873
4000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.908734000
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.323097820
Short name T947
Test name
Test status
Simulation time 5032610978 ps
CPU time 32.93 seconds
Started Jul 27 07:33:24 PM PDT 24
Finished Jul 27 07:33:58 PM PDT 24
Peak memory 207412 kb
Host smart-2e22cc93-8b32-474a-8f01-ad67002a51d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323097820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host_
handshake.323097820
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.2549701734
Short name T2644
Test name
Test status
Simulation time 41285364 ps
CPU time 0.63 seconds
Started Jul 27 07:36:16 PM PDT 24
Finished Jul 27 07:36:17 PM PDT 24
Peak memory 207128 kb
Host smart-1a89fe30-354d-4964-b6b2-9b12bafe4c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2549701734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.2549701734
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3477668213
Short name T409
Test name
Test status
Simulation time 4136241435 ps
CPU time 5.92 seconds
Started Jul 27 07:36:02 PM PDT 24
Finished Jul 27 07:36:08 PM PDT 24
Peak memory 207340 kb
Host smart-5ec6d817-7113-433e-8afb-32b3be028481
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477668213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.3477668213
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2657720694
Short name T11
Test name
Test status
Simulation time 13355412018 ps
CPU time 17.63 seconds
Started Jul 27 07:36:02 PM PDT 24
Finished Jul 27 07:36:20 PM PDT 24
Peak memory 207396 kb
Host smart-2d46857d-2d41-4f5d-8e3f-2e1588b74ef3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657720694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2657720694
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3541480598
Short name T1942
Test name
Test status
Simulation time 23328203841 ps
CPU time 26.82 seconds
Started Jul 27 07:36:06 PM PDT 24
Finished Jul 27 07:36:32 PM PDT 24
Peak memory 207404 kb
Host smart-ead1ca06-8a56-404d-9763-40eb64bf2151
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541480598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.3541480598
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1800852961
Short name T808
Test name
Test status
Simulation time 143363882 ps
CPU time 0.88 seconds
Started Jul 27 07:36:03 PM PDT 24
Finished Jul 27 07:36:04 PM PDT 24
Peak memory 207140 kb
Host smart-62ed3310-6d63-4a5f-b5f3-778df14c3a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18008
52961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1800852961
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.2225203820
Short name T2262
Test name
Test status
Simulation time 148776645 ps
CPU time 0.87 seconds
Started Jul 27 07:36:02 PM PDT 24
Finished Jul 27 07:36:03 PM PDT 24
Peak memory 207092 kb
Host smart-e5894b3c-c4c5-4215-830e-6db68b939b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22252
03820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.2225203820
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.950504645
Short name T2266
Test name
Test status
Simulation time 534517135 ps
CPU time 1.64 seconds
Started Jul 27 07:36:03 PM PDT 24
Finished Jul 27 07:36:05 PM PDT 24
Peak memory 207100 kb
Host smart-faa0f819-f6cc-4343-8bb9-e0c57e99bfa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95050
4645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.950504645
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3466782858
Short name T1906
Test name
Test status
Simulation time 1301708901 ps
CPU time 3.24 seconds
Started Jul 27 07:36:08 PM PDT 24
Finished Jul 27 07:36:11 PM PDT 24
Peak memory 207292 kb
Host smart-a636ca80-5f4f-4876-99b0-5db23bb36e3b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3466782858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3466782858
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.2170252581
Short name T1597
Test name
Test status
Simulation time 13635769956 ps
CPU time 28.41 seconds
Started Jul 27 07:36:00 PM PDT 24
Finished Jul 27 07:36:29 PM PDT 24
Peak memory 207312 kb
Host smart-19429317-99f8-4dcd-858a-f26ad96fe2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21702
52581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.2170252581
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.1662880215
Short name T886
Test name
Test status
Simulation time 8366949556 ps
CPU time 50.67 seconds
Started Jul 27 07:36:01 PM PDT 24
Finished Jul 27 07:36:52 PM PDT 24
Peak memory 207312 kb
Host smart-0ba38699-a547-4097-8eec-44822447ee04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662880215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.1662880215
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2436303324
Short name T1115
Test name
Test status
Simulation time 374036413 ps
CPU time 1.4 seconds
Started Jul 27 07:36:11 PM PDT 24
Finished Jul 27 07:36:12 PM PDT 24
Peak memory 207108 kb
Host smart-7731a354-e3b8-434d-aa02-c1dbdbf319db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24363
03324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2436303324
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.1105103404
Short name T516
Test name
Test status
Simulation time 165096501 ps
CPU time 0.91 seconds
Started Jul 27 07:36:13 PM PDT 24
Finished Jul 27 07:36:14 PM PDT 24
Peak memory 207076 kb
Host smart-242c2f7e-5853-4b8e-8ba0-5a6f436110ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11051
03404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.1105103404
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3150657090
Short name T1429
Test name
Test status
Simulation time 82148773 ps
CPU time 0.71 seconds
Started Jul 27 07:36:08 PM PDT 24
Finished Jul 27 07:36:09 PM PDT 24
Peak memory 206996 kb
Host smart-50720d75-804d-4bc7-b847-09e6a1215eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31506
57090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3150657090
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2954523779
Short name T2325
Test name
Test status
Simulation time 808792388 ps
CPU time 2.25 seconds
Started Jul 27 07:36:08 PM PDT 24
Finished Jul 27 07:36:10 PM PDT 24
Peak memory 207308 kb
Host smart-8f528cd0-1bad-45c7-98a0-cb94bcf2d8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29545
23779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2954523779
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.421141293
Short name T1093
Test name
Test status
Simulation time 300084746 ps
CPU time 1.86 seconds
Started Jul 27 07:36:11 PM PDT 24
Finished Jul 27 07:36:13 PM PDT 24
Peak memory 207320 kb
Host smart-6dd730e7-3efb-4143-9900-bb96136b7de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42114
1293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.421141293
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1542444484
Short name T371
Test name
Test status
Simulation time 204230160 ps
CPU time 0.96 seconds
Started Jul 27 07:36:09 PM PDT 24
Finished Jul 27 07:36:10 PM PDT 24
Peak memory 207084 kb
Host smart-a4df110f-0f06-4129-bc5c-d470f907c72b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1542444484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1542444484
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1788263466
Short name T620
Test name
Test status
Simulation time 143256951 ps
CPU time 0.8 seconds
Started Jul 27 07:36:07 PM PDT 24
Finished Jul 27 07:36:08 PM PDT 24
Peak memory 207104 kb
Host smart-f2b38404-e7be-44a7-9ec4-a9b131e58bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17882
63466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1788263466
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1225363287
Short name T1144
Test name
Test status
Simulation time 227616269 ps
CPU time 0.97 seconds
Started Jul 27 07:36:08 PM PDT 24
Finished Jul 27 07:36:09 PM PDT 24
Peak memory 207112 kb
Host smart-4a3569dd-a617-440a-8e4e-a2185e77c780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12253
63287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1225363287
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.835407521
Short name T1610
Test name
Test status
Simulation time 10663716253 ps
CPU time 109.32 seconds
Started Jul 27 07:36:07 PM PDT 24
Finished Jul 27 07:37:56 PM PDT 24
Peak memory 216796 kb
Host smart-3ce88665-1241-4a15-b342-18751f9f747c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=835407521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.835407521
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.1757112358
Short name T5
Test name
Test status
Simulation time 4684221422 ps
CPU time 60.02 seconds
Started Jul 27 07:36:16 PM PDT 24
Finished Jul 27 07:37:17 PM PDT 24
Peak memory 207232 kb
Host smart-d505355e-76f5-4b41-978c-d66986dc66d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1757112358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.1757112358
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3454867099
Short name T997
Test name
Test status
Simulation time 183767199 ps
CPU time 0.91 seconds
Started Jul 27 07:36:08 PM PDT 24
Finished Jul 27 07:36:09 PM PDT 24
Peak memory 207144 kb
Host smart-2ac227d7-072d-4960-bb4c-5ee8956a4dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34548
67099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3454867099
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.408163850
Short name T1106
Test name
Test status
Simulation time 23315960901 ps
CPU time 29.29 seconds
Started Jul 27 07:36:16 PM PDT 24
Finished Jul 27 07:36:46 PM PDT 24
Peak memory 207248 kb
Host smart-83711489-b14d-44da-8e97-41923c9ba928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40816
3850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.408163850
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.3158867941
Short name T756
Test name
Test status
Simulation time 3286299641 ps
CPU time 5 seconds
Started Jul 27 07:36:09 PM PDT 24
Finished Jul 27 07:36:14 PM PDT 24
Peak memory 207280 kb
Host smart-e6abc899-ed60-434c-945a-2d95545e4cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31588
67941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.3158867941
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.4178809798
Short name T1927
Test name
Test status
Simulation time 8387772460 ps
CPU time 247.37 seconds
Started Jul 27 07:36:09 PM PDT 24
Finished Jul 27 07:40:17 PM PDT 24
Peak memory 215500 kb
Host smart-4cef14e0-9700-4065-b763-7b187006a0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41788
09798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.4178809798
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.3201131706
Short name T2713
Test name
Test status
Simulation time 3127257073 ps
CPU time 24.51 seconds
Started Jul 27 07:36:07 PM PDT 24
Finished Jul 27 07:36:31 PM PDT 24
Peak memory 216848 kb
Host smart-7c1a320a-ac2b-4d61-9629-4c55f54b59a6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3201131706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.3201131706
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1499334409
Short name T2758
Test name
Test status
Simulation time 252950011 ps
CPU time 1.04 seconds
Started Jul 27 07:36:12 PM PDT 24
Finished Jul 27 07:36:13 PM PDT 24
Peak memory 207120 kb
Host smart-abc874fa-de02-4a8d-a3ce-9c798b6e7c89
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1499334409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1499334409
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1912036733
Short name T1830
Test name
Test status
Simulation time 223113302 ps
CPU time 0.93 seconds
Started Jul 27 07:36:06 PM PDT 24
Finished Jul 27 07:36:07 PM PDT 24
Peak memory 207104 kb
Host smart-1d25715e-7332-40a5-aa44-44ad0d1ee287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19120
36733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1912036733
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2172504700
Short name T2014
Test name
Test status
Simulation time 5802389874 ps
CPU time 58.81 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:37:16 PM PDT 24
Peak memory 215576 kb
Host smart-437cc2fe-a7f7-43a4-a855-a49d854577f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21725
04700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2172504700
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.2687744233
Short name T396
Test name
Test status
Simulation time 7368751005 ps
CPU time 56.5 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:37:13 PM PDT 24
Peak memory 207376 kb
Host smart-2f832e77-203f-489d-aa93-11253bb0ec60
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2687744233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.2687744233
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.249079024
Short name T1051
Test name
Test status
Simulation time 163587308 ps
CPU time 0.89 seconds
Started Jul 27 07:36:07 PM PDT 24
Finished Jul 27 07:36:08 PM PDT 24
Peak memory 207124 kb
Host smart-ccc3ab23-522e-46c0-84c1-aca265728c6d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=249079024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.249079024
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3444401030
Short name T350
Test name
Test status
Simulation time 167733479 ps
CPU time 0.89 seconds
Started Jul 27 07:36:11 PM PDT 24
Finished Jul 27 07:36:12 PM PDT 24
Peak memory 207160 kb
Host smart-cef110da-c10d-427d-ab06-d711507d71db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34444
01030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3444401030
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.3964481202
Short name T2333
Test name
Test status
Simulation time 204028093 ps
CPU time 0.95 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:36:18 PM PDT 24
Peak memory 207028 kb
Host smart-a5fc0cae-f130-4288-893f-08d27f9eeeb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39644
81202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.3964481202
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2858411237
Short name T1520
Test name
Test status
Simulation time 176938932 ps
CPU time 0.94 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:36:18 PM PDT 24
Peak memory 207096 kb
Host smart-253c690e-5375-46c3-aa9d-998e2bf2cbd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28584
11237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2858411237
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.920469205
Short name T1376
Test name
Test status
Simulation time 147984410 ps
CPU time 0.79 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:36:18 PM PDT 24
Peak memory 207140 kb
Host smart-2fd094ef-1740-4f4f-b7d5-a39645e5a5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92046
9205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.920469205
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1280671937
Short name T185
Test name
Test status
Simulation time 163288245 ps
CPU time 0.87 seconds
Started Jul 27 07:36:15 PM PDT 24
Finished Jul 27 07:36:16 PM PDT 24
Peak memory 207192 kb
Host smart-4922901d-cec7-4179-bda5-12b2cde730fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12806
71937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1280671937
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.381366453
Short name T927
Test name
Test status
Simulation time 242771799 ps
CPU time 0.97 seconds
Started Jul 27 07:36:15 PM PDT 24
Finished Jul 27 07:36:16 PM PDT 24
Peak memory 207348 kb
Host smart-5d64ad76-eed0-4811-b8ef-569a6f314d34
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=381366453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.381366453
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3454375533
Short name T2465
Test name
Test status
Simulation time 151000079 ps
CPU time 0.85 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:36:18 PM PDT 24
Peak memory 207064 kb
Host smart-a011dd8d-7ce9-43ec-a6bc-5c29733fde27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34543
75533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3454375533
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3732252305
Short name T2720
Test name
Test status
Simulation time 37934399 ps
CPU time 0.67 seconds
Started Jul 27 07:36:16 PM PDT 24
Finished Jul 27 07:36:16 PM PDT 24
Peak memory 207104 kb
Host smart-2986720f-0070-4371-82d0-3e49e6094f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37322
52305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3732252305
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3919211915
Short name T2739
Test name
Test status
Simulation time 14919002808 ps
CPU time 39.89 seconds
Started Jul 27 07:36:16 PM PDT 24
Finished Jul 27 07:36:56 PM PDT 24
Peak memory 219208 kb
Host smart-7ec36a96-16ce-4a1e-9c44-926cf286d984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39192
11915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3919211915
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.512069780
Short name T2837
Test name
Test status
Simulation time 148329297 ps
CPU time 0.83 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:36:18 PM PDT 24
Peak memory 207104 kb
Host smart-68d2fbec-bfe5-4f3e-9687-a9a419986f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51206
9780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.512069780
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1972944870
Short name T569
Test name
Test status
Simulation time 263986475 ps
CPU time 1.02 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:36:18 PM PDT 24
Peak memory 207088 kb
Host smart-529ed2b1-5463-47ac-bdb6-516f4a5f57ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19729
44870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1972944870
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3012527465
Short name T427
Test name
Test status
Simulation time 228104469 ps
CPU time 0.95 seconds
Started Jul 27 07:36:15 PM PDT 24
Finished Jul 27 07:36:16 PM PDT 24
Peak memory 207100 kb
Host smart-a7355568-aeec-4832-b99c-7893500a8509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30125
27465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3012527465
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.2095578585
Short name T1492
Test name
Test status
Simulation time 179106391 ps
CPU time 0.92 seconds
Started Jul 27 07:36:18 PM PDT 24
Finished Jul 27 07:36:19 PM PDT 24
Peak memory 206988 kb
Host smart-af113aa0-abe6-4032-9359-5b74b302f650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20955
78585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.2095578585
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.190511661
Short name T1177
Test name
Test status
Simulation time 141130028 ps
CPU time 0.87 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:36:18 PM PDT 24
Peak memory 207012 kb
Host smart-71c08fea-2e1a-4776-99e1-d3497ad4a5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19051
1661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.190511661
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3143264104
Short name T450
Test name
Test status
Simulation time 153613244 ps
CPU time 0.84 seconds
Started Jul 27 07:36:16 PM PDT 24
Finished Jul 27 07:36:17 PM PDT 24
Peak memory 207036 kb
Host smart-e76b990b-8f8c-4e6d-95e1-6a1d32e87f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31432
64104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3143264104
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.2771460773
Short name T2053
Test name
Test status
Simulation time 163227615 ps
CPU time 0.85 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:36:18 PM PDT 24
Peak memory 207108 kb
Host smart-e345119f-c8ba-4f54-9324-bb60084ae098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27714
60773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2771460773
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2344634886
Short name T2206
Test name
Test status
Simulation time 283821394 ps
CPU time 1.08 seconds
Started Jul 27 07:36:16 PM PDT 24
Finished Jul 27 07:36:17 PM PDT 24
Peak memory 207108 kb
Host smart-990ca353-7b38-4db5-b7c9-ed6fe98d896a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23446
34886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2344634886
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2160274469
Short name T632
Test name
Test status
Simulation time 5768942427 ps
CPU time 48.86 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:37:06 PM PDT 24
Peak memory 217148 kb
Host smart-882938af-edcb-40a3-9a04-2469d6284e01
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2160274469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2160274469
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.503731670
Short name T2782
Test name
Test status
Simulation time 158688533 ps
CPU time 0.84 seconds
Started Jul 27 07:36:15 PM PDT 24
Finished Jul 27 07:36:16 PM PDT 24
Peak memory 207140 kb
Host smart-73e65488-917e-4997-8220-074023e4df22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50373
1670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.503731670
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2019724386
Short name T1170
Test name
Test status
Simulation time 174400357 ps
CPU time 0.93 seconds
Started Jul 27 07:36:15 PM PDT 24
Finished Jul 27 07:36:16 PM PDT 24
Peak memory 207140 kb
Host smart-751dac0e-7ca4-4da3-b360-69fc8c7bbbed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20197
24386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2019724386
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.769840427
Short name T1347
Test name
Test status
Simulation time 1132680026 ps
CPU time 2.6 seconds
Started Jul 27 07:36:18 PM PDT 24
Finished Jul 27 07:36:21 PM PDT 24
Peak memory 207252 kb
Host smart-f6049958-3a42-4b1a-93ec-d926b4742c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76984
0427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.769840427
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.3808949556
Short name T544
Test name
Test status
Simulation time 4778781497 ps
CPU time 37.81 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:36:55 PM PDT 24
Peak memory 216712 kb
Host smart-1e896ca5-93de-4ffe-ac78-40fd67b2bf02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38089
49556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3808949556
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.2436886634
Short name T1479
Test name
Test status
Simulation time 3936449953 ps
CPU time 33.09 seconds
Started Jul 27 07:36:16 PM PDT 24
Finished Jul 27 07:36:50 PM PDT 24
Peak memory 207376 kb
Host smart-b2922ed2-05de-484d-9812-6a1bb19781eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436886634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.2436886634
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.2784632218
Short name T1316
Test name
Test status
Simulation time 30554488 ps
CPU time 0.66 seconds
Started Jul 27 07:36:35 PM PDT 24
Finished Jul 27 07:36:36 PM PDT 24
Peak memory 207152 kb
Host smart-ca60663a-fd2d-4246-9f03-479a05cd13f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2784632218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.2784632218
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.2418899302
Short name T10
Test name
Test status
Simulation time 4309461756 ps
CPU time 6.28 seconds
Started Jul 27 07:36:16 PM PDT 24
Finished Jul 27 07:36:22 PM PDT 24
Peak memory 207384 kb
Host smart-d5037e01-04b6-4065-adba-e2092b9a1f7b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418899302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.2418899302
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2053437473
Short name T555
Test name
Test status
Simulation time 13455446795 ps
CPU time 17.5 seconds
Started Jul 27 07:36:22 PM PDT 24
Finished Jul 27 07:36:39 PM PDT 24
Peak memory 207392 kb
Host smart-e365b6ee-0cff-49fc-b4c8-c901ab36768f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053437473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2053437473
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.961758266
Short name T1892
Test name
Test status
Simulation time 23303226914 ps
CPU time 32.93 seconds
Started Jul 27 07:36:17 PM PDT 24
Finished Jul 27 07:36:50 PM PDT 24
Peak memory 207368 kb
Host smart-7cd38f99-0a1f-45da-9c90-ed47078c3160
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961758266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_ao
n_wake_resume.961758266
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2072949582
Short name T657
Test name
Test status
Simulation time 166877531 ps
CPU time 0.84 seconds
Started Jul 27 07:36:34 PM PDT 24
Finished Jul 27 07:36:35 PM PDT 24
Peak memory 207152 kb
Host smart-05944a79-eb6e-44ed-bb88-b249a0e49315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20729
49582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2072949582
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.197003994
Short name T74
Test name
Test status
Simulation time 171791246 ps
CPU time 0.85 seconds
Started Jul 27 07:36:30 PM PDT 24
Finished Jul 27 07:36:30 PM PDT 24
Peak memory 207132 kb
Host smart-a6376d06-5aac-45e5-a68a-275b84351a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19700
3994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.197003994
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.2012782604
Short name T550
Test name
Test status
Simulation time 282813670 ps
CPU time 1.15 seconds
Started Jul 27 07:36:26 PM PDT 24
Finished Jul 27 07:36:27 PM PDT 24
Peak memory 207216 kb
Host smart-93c09b0a-5dc2-44bc-85be-f30f90076a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20127
82604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.2012782604
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.538736434
Short name T2533
Test name
Test status
Simulation time 1245763438 ps
CPU time 3.12 seconds
Started Jul 27 07:36:24 PM PDT 24
Finished Jul 27 07:36:27 PM PDT 24
Peak memory 207280 kb
Host smart-ec45ecb2-8302-4e96-9972-b823aa5a5f1f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=538736434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.538736434
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1876229829
Short name T2490
Test name
Test status
Simulation time 6006807854 ps
CPU time 12.4 seconds
Started Jul 27 07:36:25 PM PDT 24
Finished Jul 27 07:36:38 PM PDT 24
Peak memory 207332 kb
Host smart-fc54ee6a-8d31-4639-a02d-856d35e6d0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18762
29829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1876229829
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.2671370291
Short name T585
Test name
Test status
Simulation time 1367120068 ps
CPU time 30.91 seconds
Started Jul 27 07:36:32 PM PDT 24
Finished Jul 27 07:37:03 PM PDT 24
Peak memory 207320 kb
Host smart-76eaf5c9-98d1-47c6-a67a-6b340a5794da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671370291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.2671370291
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2129570825
Short name T2059
Test name
Test status
Simulation time 522325866 ps
CPU time 1.47 seconds
Started Jul 27 07:36:26 PM PDT 24
Finished Jul 27 07:36:28 PM PDT 24
Peak memory 207092 kb
Host smart-e3226f08-2e28-413c-8d9f-7f6f5e433988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21295
70825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2129570825
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1653624015
Short name T1460
Test name
Test status
Simulation time 148549252 ps
CPU time 0.85 seconds
Started Jul 27 07:36:30 PM PDT 24
Finished Jul 27 07:36:31 PM PDT 24
Peak memory 207108 kb
Host smart-281c420b-4c2a-4d7c-8ba4-41be05334c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16536
24015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1653624015
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2809243916
Short name T2196
Test name
Test status
Simulation time 80904550 ps
CPU time 0.75 seconds
Started Jul 27 07:36:30 PM PDT 24
Finished Jul 27 07:36:31 PM PDT 24
Peak memory 206988 kb
Host smart-878d7da3-66ac-495b-a103-b8586e307f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28092
43916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2809243916
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3588686747
Short name T2688
Test name
Test status
Simulation time 1022843069 ps
CPU time 2.87 seconds
Started Jul 27 07:36:26 PM PDT 24
Finished Jul 27 07:36:29 PM PDT 24
Peak memory 207360 kb
Host smart-4d56a6dd-e206-4504-856c-841fc6917b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35886
86747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3588686747
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.426340132
Short name T1528
Test name
Test status
Simulation time 320814427 ps
CPU time 2.85 seconds
Started Jul 27 07:36:25 PM PDT 24
Finished Jul 27 07:36:28 PM PDT 24
Peak memory 207304 kb
Host smart-6055515d-d467-4531-9661-2b5d01510377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42634
0132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.426340132
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.616137685
Short name T966
Test name
Test status
Simulation time 258275644 ps
CPU time 1.26 seconds
Started Jul 27 07:36:28 PM PDT 24
Finished Jul 27 07:36:29 PM PDT 24
Peak memory 215548 kb
Host smart-0627bd58-a935-41ca-84e0-afbae3f9333e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=616137685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.616137685
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.454336205
Short name T2356
Test name
Test status
Simulation time 142956689 ps
CPU time 0.84 seconds
Started Jul 27 07:36:26 PM PDT 24
Finished Jul 27 07:36:26 PM PDT 24
Peak memory 207096 kb
Host smart-655519ff-fe1f-4542-86ae-ebe10f6046b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45433
6205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.454336205
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.364901307
Short name T1004
Test name
Test status
Simulation time 251202597 ps
CPU time 1.03 seconds
Started Jul 27 07:36:26 PM PDT 24
Finished Jul 27 07:36:28 PM PDT 24
Peak memory 207100 kb
Host smart-363ad19f-3078-45e9-a4b0-bc2266c7b28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36490
1307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.364901307
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.3573107868
Short name T2500
Test name
Test status
Simulation time 9125590461 ps
CPU time 261.88 seconds
Started Jul 27 07:36:25 PM PDT 24
Finished Jul 27 07:40:47 PM PDT 24
Peak memory 215568 kb
Host smart-c27b1d95-711f-4146-8bda-fa1eed623b8e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3573107868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.3573107868
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.1593129897
Short name T2140
Test name
Test status
Simulation time 8873571042 ps
CPU time 55.33 seconds
Started Jul 27 07:36:36 PM PDT 24
Finished Jul 27 07:37:31 PM PDT 24
Peak memory 207384 kb
Host smart-ee1ed659-343e-428a-b32e-fcaebc7de52b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1593129897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.1593129897
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.22726406
Short name T1753
Test name
Test status
Simulation time 192439002 ps
CPU time 0.94 seconds
Started Jul 27 07:36:26 PM PDT 24
Finished Jul 27 07:36:27 PM PDT 24
Peak memory 206908 kb
Host smart-244cdf39-0af6-4f51-a263-be40d9ddfd71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22726
406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.22726406
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.1102049945
Short name T437
Test name
Test status
Simulation time 23325501626 ps
CPU time 26.58 seconds
Started Jul 27 07:36:26 PM PDT 24
Finished Jul 27 07:36:52 PM PDT 24
Peak memory 207336 kb
Host smart-7fe942df-faf2-4d74-b241-1fd6b02332ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11020
49945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.1102049945
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1830617047
Short name T1435
Test name
Test status
Simulation time 3265075053 ps
CPU time 4.45 seconds
Started Jul 27 07:36:25 PM PDT 24
Finished Jul 27 07:36:29 PM PDT 24
Peak memory 207320 kb
Host smart-776b9d3a-7012-4390-84a7-59793d50aa4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18306
17047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1830617047
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.982934050
Short name T2723
Test name
Test status
Simulation time 8748683759 ps
CPU time 89.01 seconds
Started Jul 27 07:36:24 PM PDT 24
Finished Jul 27 07:37:53 PM PDT 24
Peak memory 217284 kb
Host smart-a3f08fab-32ab-4e2e-8566-99f39c01ba26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98293
4050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.982934050
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3684816934
Short name T518
Test name
Test status
Simulation time 3212710539 ps
CPU time 31.6 seconds
Started Jul 27 07:36:23 PM PDT 24
Finished Jul 27 07:36:55 PM PDT 24
Peak memory 216672 kb
Host smart-3dad9af8-a437-4f8c-a16f-ef62185a496f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3684816934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3684816934
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1037315121
Short name T1183
Test name
Test status
Simulation time 253424892 ps
CPU time 0.97 seconds
Started Jul 27 07:36:26 PM PDT 24
Finished Jul 27 07:36:27 PM PDT 24
Peak memory 207144 kb
Host smart-c12ff541-eef5-4fec-a051-c8d415c1acd1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1037315121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1037315121
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1526134306
Short name T1879
Test name
Test status
Simulation time 273150335 ps
CPU time 1.03 seconds
Started Jul 27 07:36:33 PM PDT 24
Finished Jul 27 07:36:34 PM PDT 24
Peak memory 207104 kb
Host smart-d177a228-0cef-43c6-8d07-add205bd7a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15261
34306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1526134306
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.1294641072
Short name T1341
Test name
Test status
Simulation time 4542714214 ps
CPU time 46.97 seconds
Started Jul 27 07:36:26 PM PDT 24
Finished Jul 27 07:37:13 PM PDT 24
Peak memory 215600 kb
Host smart-d6a66426-a7d1-4f42-8a46-bca56df43910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12946
41072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1294641072
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.314729159
Short name T1770
Test name
Test status
Simulation time 7426783859 ps
CPU time 58.17 seconds
Started Jul 27 07:36:27 PM PDT 24
Finished Jul 27 07:37:25 PM PDT 24
Peak memory 207488 kb
Host smart-0c41d732-5522-473e-959a-58084278de1f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=314729159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.314729159
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2599667009
Short name T1550
Test name
Test status
Simulation time 199623131 ps
CPU time 0.88 seconds
Started Jul 27 07:36:29 PM PDT 24
Finished Jul 27 07:36:30 PM PDT 24
Peak memory 207120 kb
Host smart-1bbd7d83-0fda-4c13-bfe2-3220aae32408
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2599667009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2599667009
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3135915959
Short name T1929
Test name
Test status
Simulation time 155795326 ps
CPU time 0.85 seconds
Started Jul 27 07:36:25 PM PDT 24
Finished Jul 27 07:36:26 PM PDT 24
Peak memory 207088 kb
Host smart-631091a1-ff19-490b-9c04-3b7630245b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31359
15959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3135915959
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2722367174
Short name T133
Test name
Test status
Simulation time 207562034 ps
CPU time 0.97 seconds
Started Jul 27 07:36:29 PM PDT 24
Finished Jul 27 07:36:30 PM PDT 24
Peak memory 207140 kb
Host smart-7a20b3b1-0512-4479-bded-5ad0f2191a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27223
67174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2722367174
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.3952589830
Short name T1320
Test name
Test status
Simulation time 155652988 ps
CPU time 0.9 seconds
Started Jul 27 07:36:26 PM PDT 24
Finished Jul 27 07:36:27 PM PDT 24
Peak memory 206812 kb
Host smart-333438b9-9455-4f61-bc80-dd3f22d7b38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39525
89830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.3952589830
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2780665551
Short name T600
Test name
Test status
Simulation time 176571224 ps
CPU time 0.81 seconds
Started Jul 27 07:36:27 PM PDT 24
Finished Jul 27 07:36:28 PM PDT 24
Peak memory 207108 kb
Host smart-490442a8-f60d-46f9-8253-fcf5ce2c7c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27806
65551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2780665551
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3541979571
Short name T1465
Test name
Test status
Simulation time 160265594 ps
CPU time 0.87 seconds
Started Jul 27 07:36:28 PM PDT 24
Finished Jul 27 07:36:28 PM PDT 24
Peak memory 207192 kb
Host smart-23825349-75af-43b0-a325-2c3cee77d0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35419
79571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3541979571
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1854144034
Short name T160
Test name
Test status
Simulation time 156565807 ps
CPU time 0.86 seconds
Started Jul 27 07:36:31 PM PDT 24
Finished Jul 27 07:36:32 PM PDT 24
Peak memory 207216 kb
Host smart-fc54054b-66d6-44e4-b599-6f39cc77adb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18541
44034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1854144034
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.2326723116
Short name T819
Test name
Test status
Simulation time 237707582 ps
CPU time 1.05 seconds
Started Jul 27 07:36:25 PM PDT 24
Finished Jul 27 07:36:26 PM PDT 24
Peak memory 207120 kb
Host smart-c25f6a21-7423-4975-a31d-c3e79fd6af5f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2326723116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.2326723116
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2521406836
Short name T1292
Test name
Test status
Simulation time 153346549 ps
CPU time 0.84 seconds
Started Jul 27 07:36:37 PM PDT 24
Finished Jul 27 07:36:38 PM PDT 24
Peak memory 207104 kb
Host smart-e084432a-63c1-4904-8dde-09a3b9fe1a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25214
06836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2521406836
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.256026576
Short name T33
Test name
Test status
Simulation time 66097272 ps
CPU time 0.71 seconds
Started Jul 27 07:36:50 PM PDT 24
Finished Jul 27 07:36:51 PM PDT 24
Peak memory 206908 kb
Host smart-9686cb2b-d2ba-47f3-9fb4-a3e1a906be1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25602
6576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.256026576
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1553833425
Short name T2523
Test name
Test status
Simulation time 10424435414 ps
CPU time 24.48 seconds
Started Jul 27 07:36:35 PM PDT 24
Finished Jul 27 07:37:00 PM PDT 24
Peak memory 215580 kb
Host smart-a31026b0-a3ec-4ae8-a192-93a12ea6ae74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15538
33425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1553833425
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3411278577
Short name T2677
Test name
Test status
Simulation time 182833024 ps
CPU time 0.93 seconds
Started Jul 27 07:36:37 PM PDT 24
Finished Jul 27 07:36:38 PM PDT 24
Peak memory 207144 kb
Host smart-ab7ca011-282e-4348-afd2-50888bcbf319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34112
78577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3411278577
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3055830686
Short name T2286
Test name
Test status
Simulation time 236457555 ps
CPU time 0.95 seconds
Started Jul 27 07:36:50 PM PDT 24
Finished Jul 27 07:36:51 PM PDT 24
Peak memory 207008 kb
Host smart-9abf004f-3bea-4c4d-a40e-16589d0de363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30558
30686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3055830686
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.1106457364
Short name T543
Test name
Test status
Simulation time 217893853 ps
CPU time 0.96 seconds
Started Jul 27 07:36:36 PM PDT 24
Finished Jul 27 07:36:37 PM PDT 24
Peak memory 207100 kb
Host smart-6fa34942-60d7-4894-a32f-cf459ed7f14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11064
57364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.1106457364
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.2325056969
Short name T1020
Test name
Test status
Simulation time 183179029 ps
CPU time 0.84 seconds
Started Jul 27 07:36:33 PM PDT 24
Finished Jul 27 07:36:34 PM PDT 24
Peak memory 207092 kb
Host smart-26e863d4-c143-4278-8b00-43909f0773dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23250
56969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2325056969
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1268799671
Short name T2293
Test name
Test status
Simulation time 153449653 ps
CPU time 0.84 seconds
Started Jul 27 07:36:37 PM PDT 24
Finished Jul 27 07:36:38 PM PDT 24
Peak memory 207064 kb
Host smart-2e97e87b-5466-494f-b194-854ae6d24ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12687
99671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1268799671
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3278849818
Short name T2390
Test name
Test status
Simulation time 155387919 ps
CPU time 0.82 seconds
Started Jul 27 07:36:36 PM PDT 24
Finished Jul 27 07:36:37 PM PDT 24
Peak memory 207112 kb
Host smart-3d547a18-5110-4dd0-9b62-67dde41501f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32788
49818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3278849818
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.769926577
Short name T1202
Test name
Test status
Simulation time 239025694 ps
CPU time 0.95 seconds
Started Jul 27 07:36:35 PM PDT 24
Finished Jul 27 07:36:36 PM PDT 24
Peak memory 207072 kb
Host smart-6d84e3ce-3606-4ae9-b5cc-ab4191e93776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76992
6577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.769926577
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3432532671
Short name T823
Test name
Test status
Simulation time 244474364 ps
CPU time 1.05 seconds
Started Jul 27 07:36:37 PM PDT 24
Finished Jul 27 07:36:38 PM PDT 24
Peak memory 207136 kb
Host smart-e887bae6-dc4e-41aa-9748-a34499eb64e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34325
32671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3432532671
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.4139288418
Short name T30
Test name
Test status
Simulation time 6173391105 ps
CPU time 175.69 seconds
Started Jul 27 07:36:33 PM PDT 24
Finished Jul 27 07:39:29 PM PDT 24
Peak memory 215576 kb
Host smart-d2e9d712-3816-49d3-93c1-8ce2a046a265
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4139288418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.4139288418
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1229739536
Short name T1236
Test name
Test status
Simulation time 149141460 ps
CPU time 0.83 seconds
Started Jul 27 07:36:34 PM PDT 24
Finished Jul 27 07:36:35 PM PDT 24
Peak memory 207128 kb
Host smart-5b093b3a-d644-474b-acf7-fd636e1fdb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12297
39536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1229739536
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3329620709
Short name T2378
Test name
Test status
Simulation time 218191664 ps
CPU time 0.96 seconds
Started Jul 27 07:36:34 PM PDT 24
Finished Jul 27 07:36:35 PM PDT 24
Peak memory 207216 kb
Host smart-38e472fe-bdf0-4b0c-96c8-5b67d8ab5efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33296
20709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3329620709
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.3362904963
Short name T98
Test name
Test status
Simulation time 1246783579 ps
CPU time 3.12 seconds
Started Jul 27 07:36:33 PM PDT 24
Finished Jul 27 07:36:37 PM PDT 24
Peak memory 207260 kb
Host smart-1f40b91a-7fac-4549-8e43-1e70aa590d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33629
04963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.3362904963
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.3044279705
Short name T156
Test name
Test status
Simulation time 3606930336 ps
CPU time 106.96 seconds
Started Jul 27 07:36:38 PM PDT 24
Finished Jul 27 07:38:25 PM PDT 24
Peak memory 215580 kb
Host smart-34daa1cd-5d57-4a2d-9320-908eeb84eea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30442
79705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.3044279705
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.2832470858
Short name T1886
Test name
Test status
Simulation time 147208224 ps
CPU time 0.85 seconds
Started Jul 27 07:36:27 PM PDT 24
Finished Jul 27 07:36:28 PM PDT 24
Peak memory 207108 kb
Host smart-05f7039d-98ba-4015-9746-c2e8a8f4a911
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832470858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.2832470858
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.1178521088
Short name T2057
Test name
Test status
Simulation time 45835415 ps
CPU time 0.65 seconds
Started Jul 27 07:36:47 PM PDT 24
Finished Jul 27 07:36:48 PM PDT 24
Peak memory 207156 kb
Host smart-feef124d-c3a2-4891-bb98-97d5f92acf97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1178521088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.1178521088
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.2035963839
Short name T445
Test name
Test status
Simulation time 3642515468 ps
CPU time 5.7 seconds
Started Jul 27 07:36:34 PM PDT 24
Finished Jul 27 07:36:40 PM PDT 24
Peak memory 207384 kb
Host smart-03ba6482-c73d-4fed-940e-803b41c07fdc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035963839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_disconnect.2035963839
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.864959679
Short name T2203
Test name
Test status
Simulation time 13471309167 ps
CPU time 16.34 seconds
Started Jul 27 07:36:39 PM PDT 24
Finished Jul 27 07:36:55 PM PDT 24
Peak memory 207412 kb
Host smart-2972ff15-b494-4afe-a0ad-243a34a2084a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=864959679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.864959679
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.615167208
Short name T1651
Test name
Test status
Simulation time 23401792483 ps
CPU time 31.51 seconds
Started Jul 27 07:36:45 PM PDT 24
Finished Jul 27 07:37:16 PM PDT 24
Peak memory 207272 kb
Host smart-77779463-fb78-4499-84ee-bf0519df76fb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615167208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ao
n_wake_resume.615167208
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2753508138
Short name T2012
Test name
Test status
Simulation time 177392979 ps
CPU time 0.87 seconds
Started Jul 27 07:36:33 PM PDT 24
Finished Jul 27 07:36:34 PM PDT 24
Peak memory 207104 kb
Host smart-ed4045ce-34e8-4297-9fa9-d7ab69e3c3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27535
08138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2753508138
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.4077699270
Short name T1329
Test name
Test status
Simulation time 150993221 ps
CPU time 0.81 seconds
Started Jul 27 07:36:35 PM PDT 24
Finished Jul 27 07:36:36 PM PDT 24
Peak memory 207040 kb
Host smart-182280a5-a5d5-4c09-8d6b-cd708918317b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40776
99270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.4077699270
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2142523723
Short name T2359
Test name
Test status
Simulation time 568343445 ps
CPU time 1.77 seconds
Started Jul 27 07:36:34 PM PDT 24
Finished Jul 27 07:36:36 PM PDT 24
Peak memory 207092 kb
Host smart-1f137c75-d5ae-4ce4-9758-49329d35ad0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21425
23723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2142523723
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1878997479
Short name T2300
Test name
Test status
Simulation time 1037541159 ps
CPU time 2.68 seconds
Started Jul 27 07:36:37 PM PDT 24
Finished Jul 27 07:36:40 PM PDT 24
Peak memory 207272 kb
Host smart-24cd8986-6dcf-4ea4-beba-11cbd2665653
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1878997479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1878997479
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1778773248
Short name T2603
Test name
Test status
Simulation time 6398558171 ps
CPU time 13.5 seconds
Started Jul 27 07:36:37 PM PDT 24
Finished Jul 27 07:36:50 PM PDT 24
Peak memory 207384 kb
Host smart-405e71d8-8c80-4176-b2ff-61248670728d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17787
73248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1778773248
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.1187017916
Short name T2320
Test name
Test status
Simulation time 634607231 ps
CPU time 5.05 seconds
Started Jul 27 07:36:47 PM PDT 24
Finished Jul 27 07:36:52 PM PDT 24
Peak memory 207180 kb
Host smart-4cfc4162-7e3d-485e-a4ce-bafa5763673e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187017916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.1187017916
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.2369346533
Short name T752
Test name
Test status
Simulation time 398756922 ps
CPU time 1.42 seconds
Started Jul 27 07:36:50 PM PDT 24
Finished Jul 27 07:36:52 PM PDT 24
Peak memory 206948 kb
Host smart-12793d07-4fa5-49bf-993a-ddecdf71f62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23693
46533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.2369346533
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_enable.3652212473
Short name T238
Test name
Test status
Simulation time 46583777 ps
CPU time 0.69 seconds
Started Jul 27 07:36:42 PM PDT 24
Finished Jul 27 07:36:43 PM PDT 24
Peak memory 206996 kb
Host smart-5f3888a7-2e5e-47ce-b096-bfb3484a438a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36522
12473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3652212473
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.3534783635
Short name T2800
Test name
Test status
Simulation time 909770396 ps
CPU time 2.58 seconds
Started Jul 27 07:36:50 PM PDT 24
Finished Jul 27 07:36:53 PM PDT 24
Peak memory 207368 kb
Host smart-808169be-a81c-4b75-b9ce-af621397b237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35347
83635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3534783635
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2269240592
Short name T1403
Test name
Test status
Simulation time 157741373 ps
CPU time 1.27 seconds
Started Jul 27 07:36:42 PM PDT 24
Finished Jul 27 07:36:43 PM PDT 24
Peak memory 207264 kb
Host smart-5a933633-26e6-4e1c-930c-3d20a0532a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22692
40592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2269240592
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3957684410
Short name T394
Test name
Test status
Simulation time 199458526 ps
CPU time 1 seconds
Started Jul 27 07:36:44 PM PDT 24
Finished Jul 27 07:36:45 PM PDT 24
Peak memory 215532 kb
Host smart-d3e45350-22e4-46d3-8c55-1b4c78a4c9a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3957684410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3957684410
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.402669033
Short name T693
Test name
Test status
Simulation time 158201476 ps
CPU time 0.9 seconds
Started Jul 27 07:36:45 PM PDT 24
Finished Jul 27 07:36:46 PM PDT 24
Peak memory 207064 kb
Host smart-759a32cc-742d-4c66-ae4b-61c7e725d399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40266
9033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.402669033
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2335131915
Short name T424
Test name
Test status
Simulation time 204729281 ps
CPU time 0.96 seconds
Started Jul 27 07:36:47 PM PDT 24
Finished Jul 27 07:36:48 PM PDT 24
Peak memory 207128 kb
Host smart-d356817d-f379-4ea0-8dfc-e984b42e28f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23351
31915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2335131915
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.4218819040
Short name T1398
Test name
Test status
Simulation time 9737384193 ps
CPU time 281.98 seconds
Started Jul 27 07:36:44 PM PDT 24
Finished Jul 27 07:41:26 PM PDT 24
Peak memory 215580 kb
Host smart-57230f34-10d8-48ca-83c1-4e9b8b12780c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4218819040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.4218819040
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.4218814360
Short name T393
Test name
Test status
Simulation time 5585391628 ps
CPU time 68.81 seconds
Started Jul 27 07:36:42 PM PDT 24
Finished Jul 27 07:37:51 PM PDT 24
Peak memory 207340 kb
Host smart-bbdffe03-761f-4b5f-8ebe-5999eda88d69
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4218814360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.4218814360
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.4209548148
Short name T1168
Test name
Test status
Simulation time 282986945 ps
CPU time 1.11 seconds
Started Jul 27 07:36:48 PM PDT 24
Finished Jul 27 07:36:49 PM PDT 24
Peak memory 207112 kb
Host smart-a2c8c351-f29a-4239-9374-06dd036a07f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42095
48148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.4209548148
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.4043769679
Short name T407
Test name
Test status
Simulation time 23319687262 ps
CPU time 27.7 seconds
Started Jul 27 07:36:46 PM PDT 24
Finished Jul 27 07:37:14 PM PDT 24
Peak memory 207384 kb
Host smart-ca934f64-c0a7-4910-abce-3e1f711db865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40437
69679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.4043769679
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.935440441
Short name T2531
Test name
Test status
Simulation time 3340090982 ps
CPU time 5.31 seconds
Started Jul 27 07:36:47 PM PDT 24
Finished Jul 27 07:36:52 PM PDT 24
Peak memory 207320 kb
Host smart-c3c813c8-ae3a-4366-b625-ee016f36d20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93544
0441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.935440441
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.1353485305
Short name T2277
Test name
Test status
Simulation time 5765923196 ps
CPU time 53.12 seconds
Started Jul 27 07:36:50 PM PDT 24
Finished Jul 27 07:37:43 PM PDT 24
Peak memory 217604 kb
Host smart-812a4ab0-634c-4eb3-939d-dd835e0916fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13534
85305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.1353485305
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.883244005
Short name T1615
Test name
Test status
Simulation time 4912966090 ps
CPU time 140.16 seconds
Started Jul 27 07:36:43 PM PDT 24
Finished Jul 27 07:39:03 PM PDT 24
Peak memory 215552 kb
Host smart-7ba48e63-1c1d-42fe-b617-314075fb7cae
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=883244005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.883244005
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.1606647200
Short name T377
Test name
Test status
Simulation time 236998906 ps
CPU time 1.05 seconds
Started Jul 27 07:36:47 PM PDT 24
Finished Jul 27 07:36:48 PM PDT 24
Peak memory 207084 kb
Host smart-3080b23c-f14d-4edb-9a0e-0f6d62c48888
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1606647200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.1606647200
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.16651875
Short name T854
Test name
Test status
Simulation time 201573750 ps
CPU time 0.95 seconds
Started Jul 27 07:36:43 PM PDT 24
Finished Jul 27 07:36:44 PM PDT 24
Peak memory 207100 kb
Host smart-e83fa8f9-1767-4eb6-9e2f-6659e971c7f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16651
875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.16651875
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.4011820694
Short name T1516
Test name
Test status
Simulation time 6926069359 ps
CPU time 66.21 seconds
Started Jul 27 07:36:48 PM PDT 24
Finished Jul 27 07:37:54 PM PDT 24
Peak memory 217212 kb
Host smart-6e10bafe-784e-48aa-aeca-135163f4be28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40118
20694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.4011820694
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.221169111
Short name T2151
Test name
Test status
Simulation time 5149765796 ps
CPU time 148.04 seconds
Started Jul 27 07:36:43 PM PDT 24
Finished Jul 27 07:39:12 PM PDT 24
Peak memory 215596 kb
Host smart-45b4e268-4ab2-4db7-aa66-8ecb596d48e5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=221169111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.221169111
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.1958525645
Short name T2288
Test name
Test status
Simulation time 180851447 ps
CPU time 0.89 seconds
Started Jul 27 07:36:47 PM PDT 24
Finished Jul 27 07:36:48 PM PDT 24
Peak memory 207084 kb
Host smart-703ec33f-d7b4-49e1-ac7a-9d8bb291dcbc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1958525645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.1958525645
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2857080712
Short name T2494
Test name
Test status
Simulation time 153351967 ps
CPU time 0.86 seconds
Started Jul 27 07:36:47 PM PDT 24
Finished Jul 27 07:36:48 PM PDT 24
Peak memory 207164 kb
Host smart-0b6f2125-4e0f-4fc0-acde-cd524b479dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28570
80712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2857080712
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3874776128
Short name T2772
Test name
Test status
Simulation time 214286443 ps
CPU time 0.99 seconds
Started Jul 27 07:36:50 PM PDT 24
Finished Jul 27 07:36:51 PM PDT 24
Peak memory 207120 kb
Host smart-fa33b591-806b-4c41-932d-3867bde42b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38747
76128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3874776128
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1140424388
Short name T2054
Test name
Test status
Simulation time 156804669 ps
CPU time 0.85 seconds
Started Jul 27 07:36:43 PM PDT 24
Finished Jul 27 07:36:44 PM PDT 24
Peak memory 207144 kb
Host smart-e1970474-f2f0-459c-a07a-d09569b13e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11404
24388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1140424388
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.3306377804
Short name T2281
Test name
Test status
Simulation time 163465505 ps
CPU time 0.87 seconds
Started Jul 27 07:36:45 PM PDT 24
Finished Jul 27 07:36:46 PM PDT 24
Peak memory 207100 kb
Host smart-dcf025fb-d5d3-4657-825c-9e52c98d4f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33063
77804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.3306377804
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.1136424347
Short name T76
Test name
Test status
Simulation time 258268999 ps
CPU time 1.03 seconds
Started Jul 27 07:36:50 PM PDT 24
Finished Jul 27 07:36:51 PM PDT 24
Peak memory 207048 kb
Host smart-81b80f54-dac1-4003-9ed7-af3db906e1ee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1136424347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.1136424347
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1726859923
Short name T2643
Test name
Test status
Simulation time 151131595 ps
CPU time 0.85 seconds
Started Jul 27 07:36:47 PM PDT 24
Finished Jul 27 07:36:48 PM PDT 24
Peak memory 207128 kb
Host smart-25954389-37e8-41d7-a1d0-b5c3feec95f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17268
59923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1726859923
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.254840361
Short name T2143
Test name
Test status
Simulation time 40811588 ps
CPU time 0.7 seconds
Started Jul 27 07:36:52 PM PDT 24
Finished Jul 27 07:36:53 PM PDT 24
Peak memory 206992 kb
Host smart-cc361628-a42f-4ff7-b646-5541d84f3b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25484
0361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.254840361
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1393552201
Short name T2724
Test name
Test status
Simulation time 9208895494 ps
CPU time 23.03 seconds
Started Jul 27 07:36:47 PM PDT 24
Finished Jul 27 07:37:10 PM PDT 24
Peak memory 215604 kb
Host smart-fe27f348-c97c-4608-86e5-898b36b2f3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13935
52201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1393552201
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2238656923
Short name T1029
Test name
Test status
Simulation time 192630865 ps
CPU time 0.95 seconds
Started Jul 27 07:36:44 PM PDT 24
Finished Jul 27 07:36:45 PM PDT 24
Peak memory 207108 kb
Host smart-7c48dd9b-6bc1-422a-bb87-95ebdc401415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22386
56923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2238656923
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.122443395
Short name T420
Test name
Test status
Simulation time 232208685 ps
CPU time 0.92 seconds
Started Jul 27 07:36:46 PM PDT 24
Finished Jul 27 07:36:47 PM PDT 24
Peak memory 207084 kb
Host smart-76bc75f7-5a8c-42ff-98e7-42b9e6f25458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12244
3395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.122443395
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1519960068
Short name T153
Test name
Test status
Simulation time 200256736 ps
CPU time 0.92 seconds
Started Jul 27 07:36:44 PM PDT 24
Finished Jul 27 07:36:45 PM PDT 24
Peak memory 207068 kb
Host smart-d2d8746a-1c4a-4e86-8259-dea7eae123bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15199
60068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1519960068
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.670843360
Short name T454
Test name
Test status
Simulation time 182080791 ps
CPU time 0.9 seconds
Started Jul 27 07:36:46 PM PDT 24
Finished Jul 27 07:36:47 PM PDT 24
Peak memory 207084 kb
Host smart-5d488bcc-9346-4441-9130-c45996cfe39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67084
3360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.670843360
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.4013885873
Short name T700
Test name
Test status
Simulation time 137375253 ps
CPU time 0.81 seconds
Started Jul 27 07:36:47 PM PDT 24
Finished Jul 27 07:36:48 PM PDT 24
Peak memory 207048 kb
Host smart-946b43b8-5e98-4c6c-a9f4-965aa44b2123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40138
85873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.4013885873
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2429881234
Short name T2002
Test name
Test status
Simulation time 161956588 ps
CPU time 0.87 seconds
Started Jul 27 07:36:43 PM PDT 24
Finished Jul 27 07:36:44 PM PDT 24
Peak memory 207100 kb
Host smart-4cde8fc6-aa60-4d43-9799-46557a3eee35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24298
81234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2429881234
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1531179135
Short name T1049
Test name
Test status
Simulation time 158679140 ps
CPU time 0.79 seconds
Started Jul 27 07:36:43 PM PDT 24
Finished Jul 27 07:36:44 PM PDT 24
Peak memory 207140 kb
Host smart-0ead658b-e53a-406a-a6ca-c3e385cb12fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15311
79135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1531179135
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2848100775
Short name T1805
Test name
Test status
Simulation time 227683814 ps
CPU time 1.01 seconds
Started Jul 27 07:36:44 PM PDT 24
Finished Jul 27 07:36:45 PM PDT 24
Peak memory 207068 kb
Host smart-e0b758f4-e6e0-4f5e-a783-6d8048e32354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28481
00775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2848100775
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.753700795
Short name T2745
Test name
Test status
Simulation time 3670618476 ps
CPU time 26.24 seconds
Started Jul 27 07:36:47 PM PDT 24
Finished Jul 27 07:37:14 PM PDT 24
Peak memory 215584 kb
Host smart-79f603e2-bf01-49c6-ade5-b56f5b983a37
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=753700795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.753700795
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1593635542
Short name T2407
Test name
Test status
Simulation time 172437254 ps
CPU time 0.9 seconds
Started Jul 27 07:36:48 PM PDT 24
Finished Jul 27 07:36:49 PM PDT 24
Peak memory 207084 kb
Host smart-c29acfe6-ba83-458f-a0c9-63431118f29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15936
35542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1593635542
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.3911728262
Short name T2399
Test name
Test status
Simulation time 175416114 ps
CPU time 0.84 seconds
Started Jul 27 07:36:42 PM PDT 24
Finished Jul 27 07:36:43 PM PDT 24
Peak memory 207112 kb
Host smart-f8c3f9b4-6885-4999-a326-00797f08689c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39117
28262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.3911728262
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.139394127
Short name T2183
Test name
Test status
Simulation time 957273326 ps
CPU time 2.84 seconds
Started Jul 27 07:36:49 PM PDT 24
Finished Jul 27 07:36:52 PM PDT 24
Peak memory 207348 kb
Host smart-cf6ee536-7fac-46a8-a217-c219cbda0662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13939
4127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.139394127
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.1337742424
Short name T373
Test name
Test status
Simulation time 1114126488 ps
CPU time 25.18 seconds
Started Jul 27 07:36:45 PM PDT 24
Finished Jul 27 07:37:10 PM PDT 24
Peak memory 207260 kb
Host smart-1ba56e94-6e65-4bab-acd4-b1fa4d571a9c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337742424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.1337742424
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.2576344328
Short name T2587
Test name
Test status
Simulation time 31599037 ps
CPU time 0.66 seconds
Started Jul 27 07:37:01 PM PDT 24
Finished Jul 27 07:37:02 PM PDT 24
Peak memory 207164 kb
Host smart-d1de709f-6eab-41f1-a792-a8681dc1487c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2576344328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.2576344328
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.559114041
Short name T2434
Test name
Test status
Simulation time 3534438450 ps
CPU time 5.52 seconds
Started Jul 27 07:36:44 PM PDT 24
Finished Jul 27 07:36:49 PM PDT 24
Peak memory 207380 kb
Host smart-f6c13149-13a1-4d4b-ae94-5416ebe3a2e1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559114041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_ao
n_wake_disconnect.559114041
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.1590894732
Short name T1657
Test name
Test status
Simulation time 13442531693 ps
CPU time 16.53 seconds
Started Jul 27 07:36:46 PM PDT 24
Finished Jul 27 07:37:02 PM PDT 24
Peak memory 207360 kb
Host smart-633badaf-38be-4ede-aeee-0a2a046e5d4e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590894732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1590894732
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.2705452332
Short name T2498
Test name
Test status
Simulation time 23334140320 ps
CPU time 31.03 seconds
Started Jul 27 07:36:47 PM PDT 24
Finished Jul 27 07:37:18 PM PDT 24
Peak memory 207380 kb
Host smart-4b294c4f-9c41-4842-b8fd-0e5ce16a1463
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705452332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.2705452332
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1184882328
Short name T1896
Test name
Test status
Simulation time 175429809 ps
CPU time 0.89 seconds
Started Jul 27 07:36:44 PM PDT 24
Finished Jul 27 07:36:45 PM PDT 24
Peak memory 207140 kb
Host smart-475c141e-b78e-4bfd-924e-94db57406015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11848
82328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1184882328
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.629807662
Short name T2256
Test name
Test status
Simulation time 152231734 ps
CPU time 0.91 seconds
Started Jul 27 07:36:48 PM PDT 24
Finished Jul 27 07:36:49 PM PDT 24
Peak memory 207032 kb
Host smart-389fe476-34bc-4cbb-a888-39c6b6a29b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62980
7662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.629807662
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2176370754
Short name T1143
Test name
Test status
Simulation time 454150752 ps
CPU time 1.69 seconds
Started Jul 27 07:36:52 PM PDT 24
Finished Jul 27 07:36:54 PM PDT 24
Peak memory 207208 kb
Host smart-51abdaf4-d23a-4d41-9ec9-20f106ac0f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21763
70754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2176370754
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2073069090
Short name T1901
Test name
Test status
Simulation time 432094600 ps
CPU time 1.42 seconds
Started Jul 27 07:36:53 PM PDT 24
Finished Jul 27 07:36:54 PM PDT 24
Peak memory 207028 kb
Host smart-12632574-91e6-4964-9f8e-6ff84729a960
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2073069090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2073069090
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.869960469
Short name T2430
Test name
Test status
Simulation time 12177813037 ps
CPU time 23.11 seconds
Started Jul 27 07:36:54 PM PDT 24
Finished Jul 27 07:37:17 PM PDT 24
Peak memory 207332 kb
Host smart-56b6e7b0-b413-491a-836c-a844778c7cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86996
0469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.869960469
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.9699490
Short name T2647
Test name
Test status
Simulation time 144772107 ps
CPU time 0.86 seconds
Started Jul 27 07:36:51 PM PDT 24
Finished Jul 27 07:36:52 PM PDT 24
Peak memory 207128 kb
Host smart-5a7a4cbb-d427-4456-82be-7b14412d8743
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9699490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.9699490
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.3018072664
Short name T2673
Test name
Test status
Simulation time 486245813 ps
CPU time 1.51 seconds
Started Jul 27 07:36:52 PM PDT 24
Finished Jul 27 07:36:53 PM PDT 24
Peak memory 207076 kb
Host smart-89080ae1-6f01-4e01-848b-0d214e633196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30180
72664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.3018072664
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.2444924102
Short name T401
Test name
Test status
Simulation time 137119099 ps
CPU time 0.82 seconds
Started Jul 27 07:36:52 PM PDT 24
Finished Jul 27 07:36:53 PM PDT 24
Peak memory 207064 kb
Host smart-cdb78a45-7b13-47d7-b32d-a09d3a01bc15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24449
24102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2444924102
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.3336052415
Short name T1201
Test name
Test status
Simulation time 38184039 ps
CPU time 0.7 seconds
Started Jul 27 07:36:51 PM PDT 24
Finished Jul 27 07:36:52 PM PDT 24
Peak memory 207064 kb
Host smart-6b8ec718-d066-4e4e-b94a-132f4cd02746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33360
52415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3336052415
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2811355424
Short name T1709
Test name
Test status
Simulation time 981753859 ps
CPU time 2.39 seconds
Started Jul 27 07:36:52 PM PDT 24
Finished Jul 27 07:36:55 PM PDT 24
Peak memory 207392 kb
Host smart-8c5bbd1f-eb71-4dbb-8208-f657a15693b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28113
55424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2811355424
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.41444846
Short name T1611
Test name
Test status
Simulation time 243481211 ps
CPU time 1.68 seconds
Started Jul 27 07:36:53 PM PDT 24
Finished Jul 27 07:36:55 PM PDT 24
Peak memory 207248 kb
Host smart-05793699-1cf6-412a-ab57-57da9e687e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41444
846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.41444846
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3410357040
Short name T1044
Test name
Test status
Simulation time 251967769 ps
CPU time 1.08 seconds
Started Jul 27 07:36:51 PM PDT 24
Finished Jul 27 07:36:52 PM PDT 24
Peak memory 207328 kb
Host smart-b72704de-afc1-420d-89fc-ca19949b3345
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3410357040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3410357040
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.945739430
Short name T1068
Test name
Test status
Simulation time 160760431 ps
CPU time 0.9 seconds
Started Jul 27 07:36:58 PM PDT 24
Finished Jul 27 07:36:59 PM PDT 24
Peak memory 207028 kb
Host smart-6c449298-8316-49c0-b77c-473eab5d29f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94573
9430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.945739430
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.3057748058
Short name T2331
Test name
Test status
Simulation time 242398145 ps
CPU time 0.99 seconds
Started Jul 27 07:36:52 PM PDT 24
Finished Jul 27 07:36:53 PM PDT 24
Peak memory 207140 kb
Host smart-7396bcc9-d81c-450b-9448-377a2c53d897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30577
48058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.3057748058
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.3952947089
Short name T2792
Test name
Test status
Simulation time 6362590940 ps
CPU time 46.99 seconds
Started Jul 27 07:36:52 PM PDT 24
Finished Jul 27 07:37:39 PM PDT 24
Peak memory 207352 kb
Host smart-36a3f5fc-c4e1-46c9-837f-36a6025f4bce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3952947089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.3952947089
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2534095086
Short name T1498
Test name
Test status
Simulation time 199600472 ps
CPU time 0.9 seconds
Started Jul 27 07:36:51 PM PDT 24
Finished Jul 27 07:36:53 PM PDT 24
Peak memory 207128 kb
Host smart-a1d6e42c-efa4-46b7-a2ed-162f74ff4f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25340
95086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2534095086
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.2235616277
Short name T351
Test name
Test status
Simulation time 23364838606 ps
CPU time 35.83 seconds
Started Jul 27 07:36:50 PM PDT 24
Finished Jul 27 07:37:26 PM PDT 24
Peak memory 207436 kb
Host smart-a85e633c-1c2e-4266-9e84-8a2548ad522f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22356
16277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.2235616277
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.830715614
Short name T1362
Test name
Test status
Simulation time 3337592342 ps
CPU time 4.77 seconds
Started Jul 27 07:36:56 PM PDT 24
Finished Jul 27 07:37:01 PM PDT 24
Peak memory 207392 kb
Host smart-ce252595-0bcd-46ea-9c8b-58ab154db558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83071
5614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.830715614
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2236216300
Short name T1598
Test name
Test status
Simulation time 7917233515 ps
CPU time 83.09 seconds
Started Jul 27 07:36:53 PM PDT 24
Finished Jul 27 07:38:16 PM PDT 24
Peak memory 217116 kb
Host smart-b6992d0c-0e9f-4ea7-a202-8ea69ff26188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22362
16300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2236216300
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1725738645
Short name T721
Test name
Test status
Simulation time 4209900208 ps
CPU time 33.99 seconds
Started Jul 27 07:36:54 PM PDT 24
Finished Jul 27 07:37:28 PM PDT 24
Peak memory 207340 kb
Host smart-11cb80b2-c7a3-4416-b2e6-d2f923f8d41c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1725738645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1725738645
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2723496283
Short name T573
Test name
Test status
Simulation time 233559377 ps
CPU time 0.98 seconds
Started Jul 27 07:36:51 PM PDT 24
Finished Jul 27 07:36:53 PM PDT 24
Peak memory 207116 kb
Host smart-cef1526e-261c-4403-9f01-ef818cdc56b3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2723496283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2723496283
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.4209532026
Short name T2412
Test name
Test status
Simulation time 192455035 ps
CPU time 0.99 seconds
Started Jul 27 07:36:54 PM PDT 24
Finished Jul 27 07:36:55 PM PDT 24
Peak memory 207120 kb
Host smart-e8466da3-7c1d-4b63-80b2-22a9483a6026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42095
32026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.4209532026
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.226872724
Short name T159
Test name
Test status
Simulation time 4908245352 ps
CPU time 46.87 seconds
Started Jul 27 07:36:53 PM PDT 24
Finished Jul 27 07:37:40 PM PDT 24
Peak memory 215628 kb
Host smart-846f01e6-41b9-4f3d-a5e8-b1f41c547f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22687
2724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.226872724
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.2968552520
Short name T1428
Test name
Test status
Simulation time 4056948964 ps
CPU time 30.14 seconds
Started Jul 27 07:36:53 PM PDT 24
Finished Jul 27 07:37:23 PM PDT 24
Peak memory 216412 kb
Host smart-9d8d49c2-a0d0-44ee-bb6a-564c4864ef9d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2968552520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.2968552520
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2264532927
Short name T1785
Test name
Test status
Simulation time 145717997 ps
CPU time 0.86 seconds
Started Jul 27 07:36:52 PM PDT 24
Finished Jul 27 07:36:53 PM PDT 24
Peak memory 207152 kb
Host smart-c53fb9fa-643a-4b6e-beae-6f4b7ea3fa91
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2264532927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2264532927
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1073849638
Short name T2344
Test name
Test status
Simulation time 162644907 ps
CPU time 0.9 seconds
Started Jul 27 07:36:52 PM PDT 24
Finished Jul 27 07:36:53 PM PDT 24
Peak memory 207152 kb
Host smart-d0e8f1e5-6880-4c79-9f7a-86d98f6faa27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10738
49638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1073849638
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2745531692
Short name T131
Test name
Test status
Simulation time 198407287 ps
CPU time 0.93 seconds
Started Jul 27 07:36:58 PM PDT 24
Finished Jul 27 07:36:59 PM PDT 24
Peak memory 207056 kb
Host smart-4740f460-86c1-49cc-a60b-c7141a74d1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27455
31692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2745531692
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.2550215420
Short name T1875
Test name
Test status
Simulation time 148119349 ps
CPU time 0.86 seconds
Started Jul 27 07:36:51 PM PDT 24
Finished Jul 27 07:36:52 PM PDT 24
Peak memory 207104 kb
Host smart-3db3e1ad-ab1f-4e52-92ee-4e6b29ceb78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25502
15420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.2550215420
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2680351823
Short name T2186
Test name
Test status
Simulation time 169709971 ps
CPU time 0.88 seconds
Started Jul 27 07:36:52 PM PDT 24
Finished Jul 27 07:36:53 PM PDT 24
Peak memory 207096 kb
Host smart-d6ea14db-7058-49dd-973b-d40f4dcce01a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26803
51823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2680351823
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.742064291
Short name T2071
Test name
Test status
Simulation time 225858665 ps
CPU time 0.95 seconds
Started Jul 27 07:36:54 PM PDT 24
Finished Jul 27 07:36:55 PM PDT 24
Peak memory 207136 kb
Host smart-88bf8199-2fef-4708-9946-b5b9fa81ebe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74206
4291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.742064291
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2626753317
Short name T1872
Test name
Test status
Simulation time 189533903 ps
CPU time 0.85 seconds
Started Jul 27 07:36:52 PM PDT 24
Finished Jul 27 07:36:53 PM PDT 24
Peak memory 207136 kb
Host smart-016f83a2-8a44-4b7a-9ff1-7ab15af286ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26267
53317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2626753317
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.947942223
Short name T1399
Test name
Test status
Simulation time 233651759 ps
CPU time 1.04 seconds
Started Jul 27 07:36:58 PM PDT 24
Finished Jul 27 07:36:59 PM PDT 24
Peak memory 207060 kb
Host smart-d236e2d9-4a09-4fc4-a34a-9a4f5d25ba40
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=947942223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.947942223
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3501864437
Short name T647
Test name
Test status
Simulation time 169695435 ps
CPU time 0.86 seconds
Started Jul 27 07:36:55 PM PDT 24
Finished Jul 27 07:36:55 PM PDT 24
Peak memory 207132 kb
Host smart-d3bd41e4-e90a-438b-91bf-f2828d9102ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35018
64437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3501864437
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1452481858
Short name T32
Test name
Test status
Simulation time 34975358 ps
CPU time 0.68 seconds
Started Jul 27 07:36:51 PM PDT 24
Finished Jul 27 07:36:52 PM PDT 24
Peak memory 207296 kb
Host smart-a64bbb88-e80f-4c8c-95ef-4460f2deacd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14524
81858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1452481858
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3045701675
Short name T959
Test name
Test status
Simulation time 14797303028 ps
CPU time 34.06 seconds
Started Jul 27 07:36:58 PM PDT 24
Finished Jul 27 07:37:32 PM PDT 24
Peak memory 215500 kb
Host smart-5f808390-15df-4d00-88f5-a8abb86558a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30457
01675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3045701675
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.224578935
Short name T2492
Test name
Test status
Simulation time 214877033 ps
CPU time 0.98 seconds
Started Jul 27 07:37:00 PM PDT 24
Finished Jul 27 07:37:01 PM PDT 24
Peak memory 207108 kb
Host smart-598c277d-efb1-49dd-82a3-8db33c0248c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22457
8935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.224578935
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.3159262781
Short name T1480
Test name
Test status
Simulation time 209364832 ps
CPU time 1 seconds
Started Jul 27 07:37:04 PM PDT 24
Finished Jul 27 07:37:05 PM PDT 24
Peak memory 207124 kb
Host smart-97070332-bba2-46d0-84b3-eb40abac7fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31592
62781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.3159262781
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.3803575636
Short name T2726
Test name
Test status
Simulation time 204550879 ps
CPU time 0.93 seconds
Started Jul 27 07:37:02 PM PDT 24
Finished Jul 27 07:37:03 PM PDT 24
Peak memory 207096 kb
Host smart-28fc165d-1089-4806-a608-aeb75ddec1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38035
75636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.3803575636
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3981742157
Short name T983
Test name
Test status
Simulation time 192457420 ps
CPU time 0.89 seconds
Started Jul 27 07:37:01 PM PDT 24
Finished Jul 27 07:37:02 PM PDT 24
Peak memory 207104 kb
Host smart-d90bd0ed-59dc-4f88-9680-ab8e2fefcf90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39817
42157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3981742157
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.802060752
Short name T1122
Test name
Test status
Simulation time 170468244 ps
CPU time 0.96 seconds
Started Jul 27 07:37:02 PM PDT 24
Finished Jul 27 07:37:03 PM PDT 24
Peak memory 207084 kb
Host smart-0360c3ca-a04e-4065-b92b-a41900e07d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80206
0752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.802060752
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.973090902
Short name T1632
Test name
Test status
Simulation time 165097195 ps
CPU time 0.9 seconds
Started Jul 27 07:37:05 PM PDT 24
Finished Jul 27 07:37:06 PM PDT 24
Peak memory 207128 kb
Host smart-c23e4b44-a093-4b43-b97b-a1c08995b455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97309
0902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.973090902
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3626646438
Short name T1905
Test name
Test status
Simulation time 222518585 ps
CPU time 1.07 seconds
Started Jul 27 07:37:02 PM PDT 24
Finished Jul 27 07:37:03 PM PDT 24
Peak memory 207144 kb
Host smart-81562cc8-43f3-400b-b011-0bf34cab8417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36266
46438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3626646438
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.2171306489
Short name T964
Test name
Test status
Simulation time 4818296770 ps
CPU time 137.8 seconds
Started Jul 27 07:37:02 PM PDT 24
Finished Jul 27 07:39:20 PM PDT 24
Peak memory 215580 kb
Host smart-f15c20ec-affe-4a14-82cf-636e1459bdbf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2171306489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2171306489
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.737370773
Short name T1475
Test name
Test status
Simulation time 197074108 ps
CPU time 0.94 seconds
Started Jul 27 07:37:00 PM PDT 24
Finished Jul 27 07:37:01 PM PDT 24
Peak memory 207144 kb
Host smart-f0216c9e-7154-4537-b0ee-8207e8a0c888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73737
0773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.737370773
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.2483532067
Short name T27
Test name
Test status
Simulation time 180146393 ps
CPU time 0.85 seconds
Started Jul 27 07:37:00 PM PDT 24
Finished Jul 27 07:37:01 PM PDT 24
Peak memory 207012 kb
Host smart-624b18ba-2b9d-4e88-b539-99e73adaba91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24835
32067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2483532067
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.846513785
Short name T2808
Test name
Test status
Simulation time 964988874 ps
CPU time 2.31 seconds
Started Jul 27 07:37:06 PM PDT 24
Finished Jul 27 07:37:09 PM PDT 24
Peak memory 207356 kb
Host smart-7f53a644-52ad-402c-ac8d-7b2c7b35694a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84651
3785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.846513785
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3024459923
Short name T2694
Test name
Test status
Simulation time 3915001837 ps
CPU time 117.61 seconds
Started Jul 27 07:37:01 PM PDT 24
Finished Jul 27 07:38:59 PM PDT 24
Peak memory 215596 kb
Host smart-dd2c2c2f-4113-46c3-9124-1decc98e811a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244
59923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3024459923
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.2459150241
Short name T637
Test name
Test status
Simulation time 1963961177 ps
CPU time 13.33 seconds
Started Jul 27 07:36:55 PM PDT 24
Finished Jul 27 07:37:08 PM PDT 24
Peak memory 207336 kb
Host smart-7999418d-f0ce-4e68-b38f-e53f88ef1458
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459150241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.2459150241
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2812092066
Short name T1768
Test name
Test status
Simulation time 93281887 ps
CPU time 0.73 seconds
Started Jul 27 07:37:17 PM PDT 24
Finished Jul 27 07:37:18 PM PDT 24
Peak memory 207152 kb
Host smart-845c74bc-e675-492b-9f63-9fcbd9054b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2812092066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2812092066
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.2462676838
Short name T2606
Test name
Test status
Simulation time 3386068522 ps
CPU time 4.93 seconds
Started Jul 27 07:37:00 PM PDT 24
Finished Jul 27 07:37:05 PM PDT 24
Peak memory 207372 kb
Host smart-9abed5df-6d33-4aa5-b370-ff263360928e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462676838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.2462676838
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2845317536
Short name T2423
Test name
Test status
Simulation time 13326444169 ps
CPU time 15.69 seconds
Started Jul 27 07:37:00 PM PDT 24
Finished Jul 27 07:37:16 PM PDT 24
Peak memory 207468 kb
Host smart-5d5dfe85-8f1c-480c-b47f-55ebcf5f333d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845317536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2845317536
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1816911251
Short name T8
Test name
Test status
Simulation time 23353622738 ps
CPU time 29.62 seconds
Started Jul 27 07:37:02 PM PDT 24
Finished Jul 27 07:37:31 PM PDT 24
Peak memory 207372 kb
Host smart-6570da58-4056-414e-a5f7-635b944299bc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816911251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.1816911251
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2292141776
Short name T1416
Test name
Test status
Simulation time 193173034 ps
CPU time 0.92 seconds
Started Jul 27 07:37:05 PM PDT 24
Finished Jul 27 07:37:07 PM PDT 24
Peak memory 207140 kb
Host smart-3a5091ca-004f-4731-a1a2-2c6f422c5131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22921
41776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2292141776
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.147809817
Short name T2520
Test name
Test status
Simulation time 169865922 ps
CPU time 0.85 seconds
Started Jul 27 07:37:02 PM PDT 24
Finished Jul 27 07:37:03 PM PDT 24
Peak memory 207104 kb
Host smart-953ac241-1b78-4476-ac79-199da91e9da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14780
9817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.147809817
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.2399931316
Short name T1935
Test name
Test status
Simulation time 545910022 ps
CPU time 1.67 seconds
Started Jul 27 07:37:02 PM PDT 24
Finished Jul 27 07:37:04 PM PDT 24
Peak memory 207136 kb
Host smart-cc5d26dd-b3df-44dc-99ec-3c3af940c71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23999
31316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.2399931316
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2611894886
Short name T834
Test name
Test status
Simulation time 434062984 ps
CPU time 1.33 seconds
Started Jul 27 07:37:03 PM PDT 24
Finished Jul 27 07:37:04 PM PDT 24
Peak memory 207100 kb
Host smart-04060959-07e5-41fc-bb3c-3026effc180a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2611894886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2611894886
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.3633051750
Short name T2483
Test name
Test status
Simulation time 14175372418 ps
CPU time 32.69 seconds
Started Jul 27 07:37:13 PM PDT 24
Finished Jul 27 07:37:46 PM PDT 24
Peak memory 207396 kb
Host smart-687fa7f4-9692-4bf2-94ea-02ed75f54080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36330
51750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.3633051750
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.662730200
Short name T2060
Test name
Test status
Simulation time 2468875557 ps
CPU time 21.73 seconds
Started Jul 27 07:37:14 PM PDT 24
Finished Jul 27 07:37:36 PM PDT 24
Peak memory 207420 kb
Host smart-f237ae94-9697-4001-9984-34a317b15437
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662730200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.662730200
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.1762619349
Short name T2473
Test name
Test status
Simulation time 420120679 ps
CPU time 1.48 seconds
Started Jul 27 07:37:10 PM PDT 24
Finished Jul 27 07:37:11 PM PDT 24
Peak memory 207076 kb
Host smart-6b824b35-02da-43b0-a8da-704a96fdd902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17626
19349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.1762619349
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3216469513
Short name T510
Test name
Test status
Simulation time 148913068 ps
CPU time 0.86 seconds
Started Jul 27 07:37:11 PM PDT 24
Finished Jul 27 07:37:13 PM PDT 24
Peak memory 207080 kb
Host smart-289cd0c6-a415-4901-9da3-c4de412b623f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32164
69513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3216469513
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1557661731
Short name T1125
Test name
Test status
Simulation time 98841892 ps
CPU time 0.75 seconds
Started Jul 27 07:37:09 PM PDT 24
Finished Jul 27 07:37:10 PM PDT 24
Peak memory 207080 kb
Host smart-7408c3c9-2776-4584-ab46-1a3effcabe74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15576
61731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1557661731
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.892788705
Short name T2194
Test name
Test status
Simulation time 960518175 ps
CPU time 2.69 seconds
Started Jul 27 07:37:10 PM PDT 24
Finished Jul 27 07:37:12 PM PDT 24
Peak memory 207408 kb
Host smart-cc8d9b5a-6eec-40a0-8f34-343f10e7c570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89278
8705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.892788705
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.719873925
Short name T906
Test name
Test status
Simulation time 212405383 ps
CPU time 1.41 seconds
Started Jul 27 07:37:15 PM PDT 24
Finished Jul 27 07:37:16 PM PDT 24
Peak memory 207264 kb
Host smart-ed068f2c-c873-44ec-bdf2-13197e20c27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71987
3925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.719873925
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.4016989133
Short name T929
Test name
Test status
Simulation time 250446312 ps
CPU time 1.11 seconds
Started Jul 27 07:37:09 PM PDT 24
Finished Jul 27 07:37:11 PM PDT 24
Peak memory 215516 kb
Host smart-4b7a601e-747e-4cc7-a6d2-2e869a81c67e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4016989133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.4016989133
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3508863957
Short name T770
Test name
Test status
Simulation time 132743248 ps
CPU time 0.79 seconds
Started Jul 27 07:37:09 PM PDT 24
Finished Jul 27 07:37:10 PM PDT 24
Peak memory 207176 kb
Host smart-2c51c7e8-7217-400d-a0be-fc0108010c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35088
63957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3508863957
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.84793760
Short name T1127
Test name
Test status
Simulation time 202253641 ps
CPU time 0.89 seconds
Started Jul 27 07:37:12 PM PDT 24
Finished Jul 27 07:37:13 PM PDT 24
Peak memory 207120 kb
Host smart-9172b3ec-150b-48a2-a78c-b4b38f829c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84793
760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.84793760
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.3202985959
Short name T501
Test name
Test status
Simulation time 7114969387 ps
CPU time 72.6 seconds
Started Jul 27 07:37:09 PM PDT 24
Finished Jul 27 07:38:22 PM PDT 24
Peak memory 215608 kb
Host smart-84e7564b-08ee-498d-9828-b67df9cdf1dc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3202985959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.3202985959
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.4157636080
Short name T1066
Test name
Test status
Simulation time 9520900059 ps
CPU time 118.84 seconds
Started Jul 27 07:37:14 PM PDT 24
Finished Jul 27 07:39:13 PM PDT 24
Peak memory 207376 kb
Host smart-20649c26-1e82-4cbb-83d0-b4227dca6f1d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4157636080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.4157636080
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.1146598199
Short name T694
Test name
Test status
Simulation time 240576841 ps
CPU time 0.98 seconds
Started Jul 27 07:37:11 PM PDT 24
Finished Jul 27 07:37:13 PM PDT 24
Peak memory 207096 kb
Host smart-e7efa9d6-9b01-4dd7-9c78-fa55aff615f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11465
98199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.1146598199
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.592672872
Short name T1276
Test name
Test status
Simulation time 23297674947 ps
CPU time 29.22 seconds
Started Jul 27 07:37:11 PM PDT 24
Finished Jul 27 07:37:40 PM PDT 24
Peak memory 207352 kb
Host smart-4dc92433-2a3d-4624-ae12-2ef084ea3d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59267
2872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.592672872
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1878854443
Short name T1522
Test name
Test status
Simulation time 3337842258 ps
CPU time 5.17 seconds
Started Jul 27 07:37:14 PM PDT 24
Finished Jul 27 07:37:19 PM PDT 24
Peak memory 207348 kb
Host smart-625a719a-c13b-40e8-b186-0527fadf52c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18788
54443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1878854443
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.2091140100
Short name T1094
Test name
Test status
Simulation time 7412552799 ps
CPU time 223.65 seconds
Started Jul 27 07:37:10 PM PDT 24
Finished Jul 27 07:40:54 PM PDT 24
Peak memory 215592 kb
Host smart-87fb2662-4905-401e-9f0c-a61e422bfe69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20911
40100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.2091140100
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2522574056
Short name T1291
Test name
Test status
Simulation time 4736261585 ps
CPU time 34.82 seconds
Started Jul 27 07:37:11 PM PDT 24
Finished Jul 27 07:37:46 PM PDT 24
Peak memory 216956 kb
Host smart-363a1607-f4bd-4cd6-a971-9f6e669bbd0b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2522574056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2522574056
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2622029694
Short name T1936
Test name
Test status
Simulation time 269377140 ps
CPU time 0.96 seconds
Started Jul 27 07:37:11 PM PDT 24
Finished Jul 27 07:37:12 PM PDT 24
Peak memory 207120 kb
Host smart-dd1b053c-588d-4412-8666-4b35f909d388
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2622029694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2622029694
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2140050129
Short name T2323
Test name
Test status
Simulation time 185771722 ps
CPU time 0.92 seconds
Started Jul 27 07:37:09 PM PDT 24
Finished Jul 27 07:37:10 PM PDT 24
Peak memory 207128 kb
Host smart-c2dd6903-2d71-4fea-879e-cb57ee8e58be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21400
50129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2140050129
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.936435724
Short name T602
Test name
Test status
Simulation time 4151211563 ps
CPU time 39.1 seconds
Started Jul 27 07:37:11 PM PDT 24
Finished Jul 27 07:37:50 PM PDT 24
Peak memory 217236 kb
Host smart-48c90e99-b616-4abb-8ce6-7da8af671bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93643
5724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.936435724
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.3506849739
Short name T1819
Test name
Test status
Simulation time 4159437575 ps
CPU time 41.35 seconds
Started Jul 27 07:37:09 PM PDT 24
Finished Jul 27 07:37:50 PM PDT 24
Peak memory 207428 kb
Host smart-0934f65b-1f9b-4198-a278-72268ca69bab
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3506849739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.3506849739
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.3476141286
Short name T2786
Test name
Test status
Simulation time 145120674 ps
CPU time 0.84 seconds
Started Jul 27 07:37:12 PM PDT 24
Finished Jul 27 07:37:13 PM PDT 24
Peak memory 207140 kb
Host smart-2fe2a1f1-8eff-4e15-8bb2-e6ac9a94d387
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3476141286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.3476141286
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2511909189
Short name T1832
Test name
Test status
Simulation time 140772492 ps
CPU time 0.83 seconds
Started Jul 27 07:37:08 PM PDT 24
Finished Jul 27 07:37:09 PM PDT 24
Peak memory 207112 kb
Host smart-dbbcce06-999d-40fa-b21e-379fd47922c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25119
09189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2511909189
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.963731613
Short name T146
Test name
Test status
Simulation time 227068628 ps
CPU time 0.96 seconds
Started Jul 27 07:37:09 PM PDT 24
Finished Jul 27 07:37:10 PM PDT 24
Peak memory 207112 kb
Host smart-b31592ac-be3c-42b2-b077-0a989b6ef600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96373
1613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.963731613
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.3554582379
Short name T2306
Test name
Test status
Simulation time 221109869 ps
CPU time 0.96 seconds
Started Jul 27 07:37:11 PM PDT 24
Finished Jul 27 07:37:12 PM PDT 24
Peak memory 207188 kb
Host smart-c0349c85-44d6-423b-9944-c03d9399e30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35545
82379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3554582379
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3275329572
Short name T1107
Test name
Test status
Simulation time 193822347 ps
CPU time 0.89 seconds
Started Jul 27 07:37:13 PM PDT 24
Finished Jul 27 07:37:14 PM PDT 24
Peak memory 207068 kb
Host smart-97caa114-986c-4332-be54-7f149d710f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32753
29572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3275329572
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.463160009
Short name T2374
Test name
Test status
Simulation time 193056987 ps
CPU time 0.89 seconds
Started Jul 27 07:37:13 PM PDT 24
Finished Jul 27 07:37:15 PM PDT 24
Peak memory 207072 kb
Host smart-ca1a755b-c068-410d-94e4-b0836c0f7614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46316
0009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.463160009
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.1684276008
Short name T172
Test name
Test status
Simulation time 211048716 ps
CPU time 1.01 seconds
Started Jul 27 07:37:14 PM PDT 24
Finished Jul 27 07:37:15 PM PDT 24
Peak memory 207144 kb
Host smart-cc281c6d-4bee-4cb3-8e08-5ea549a11849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16842
76008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1684276008
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.183282566
Short name T2392
Test name
Test status
Simulation time 182955776 ps
CPU time 0.94 seconds
Started Jul 27 07:37:15 PM PDT 24
Finished Jul 27 07:37:16 PM PDT 24
Peak memory 207128 kb
Host smart-3fc887a2-357f-421a-9964-67b591a5809f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=183282566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.183282566
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2024097043
Short name T1220
Test name
Test status
Simulation time 151502581 ps
CPU time 0.87 seconds
Started Jul 27 07:37:10 PM PDT 24
Finished Jul 27 07:37:11 PM PDT 24
Peak memory 206984 kb
Host smart-aad7ca18-0929-43a3-9730-9cdb0aba20a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20240
97043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2024097043
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3921607193
Short name T1646
Test name
Test status
Simulation time 34302471 ps
CPU time 0.68 seconds
Started Jul 27 07:37:15 PM PDT 24
Finished Jul 27 07:37:16 PM PDT 24
Peak memory 207040 kb
Host smart-f34eb322-9ec1-437d-99f1-1536a4a08e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39216
07193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3921607193
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.112911284
Short name T1052
Test name
Test status
Simulation time 17261882532 ps
CPU time 45.39 seconds
Started Jul 27 07:37:13 PM PDT 24
Finished Jul 27 07:37:59 PM PDT 24
Peak memory 215512 kb
Host smart-e933b8e9-4ae3-4631-9697-e88ccd4adb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11291
1284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.112911284
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.843244105
Short name T1993
Test name
Test status
Simulation time 160491192 ps
CPU time 0.91 seconds
Started Jul 27 07:37:11 PM PDT 24
Finished Jul 27 07:37:13 PM PDT 24
Peak memory 207116 kb
Host smart-4fe01b1d-0df6-4c0b-a7dc-4248898d920f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84324
4105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.843244105
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3739892489
Short name T1088
Test name
Test status
Simulation time 195927071 ps
CPU time 0.98 seconds
Started Jul 27 07:37:14 PM PDT 24
Finished Jul 27 07:37:15 PM PDT 24
Peak memory 207116 kb
Host smart-37266345-e1ad-4b6b-bb0b-20971123d5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37398
92489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3739892489
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3556744375
Short name T1222
Test name
Test status
Simulation time 230358905 ps
CPU time 0.96 seconds
Started Jul 27 07:37:15 PM PDT 24
Finished Jul 27 07:37:16 PM PDT 24
Peak memory 207072 kb
Host smart-a3169889-538d-49c6-9f12-0892ab8fa720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35567
44375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3556744375
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.4257413471
Short name T1213
Test name
Test status
Simulation time 205157776 ps
CPU time 0.91 seconds
Started Jul 27 07:37:17 PM PDT 24
Finished Jul 27 07:37:18 PM PDT 24
Peak memory 207024 kb
Host smart-a2ae19dd-8352-4993-822a-b3a2c241a081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42574
13471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.4257413471
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3887610273
Short name T2363
Test name
Test status
Simulation time 189928952 ps
CPU time 0.83 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:29 PM PDT 24
Peak memory 207088 kb
Host smart-fc576877-65b7-4db7-8091-ad6af21e21c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38876
10273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3887610273
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3531371370
Short name T1977
Test name
Test status
Simulation time 162851804 ps
CPU time 0.84 seconds
Started Jul 27 07:37:17 PM PDT 24
Finished Jul 27 07:37:18 PM PDT 24
Peak memory 206984 kb
Host smart-a8535a57-9a74-480f-9925-fc2dc545b439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35313
71370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3531371370
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3432426865
Short name T2159
Test name
Test status
Simulation time 151251734 ps
CPU time 0.88 seconds
Started Jul 27 07:37:19 PM PDT 24
Finished Jul 27 07:37:20 PM PDT 24
Peak memory 207108 kb
Host smart-35752815-6ea0-435f-9c00-c61a10662c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34324
26865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3432426865
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3449515608
Short name T436
Test name
Test status
Simulation time 243889700 ps
CPU time 1.03 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:30 PM PDT 24
Peak memory 207124 kb
Host smart-ccb903c5-a8c5-4339-8144-6438c6761fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34495
15608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3449515608
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.4165838084
Short name T754
Test name
Test status
Simulation time 4797029427 ps
CPU time 36.5 seconds
Started Jul 27 07:37:26 PM PDT 24
Finished Jul 27 07:38:03 PM PDT 24
Peak memory 217228 kb
Host smart-c9a3fa3e-74ba-460b-b365-7d0edad47b70
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4165838084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.4165838084
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.4020908505
Short name T1556
Test name
Test status
Simulation time 202213131 ps
CPU time 0.94 seconds
Started Jul 27 07:37:20 PM PDT 24
Finished Jul 27 07:37:21 PM PDT 24
Peak memory 207140 kb
Host smart-433560e0-4c23-4ae6-bca4-a5f7c66bfa06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40209
08505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.4020908505
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3118908159
Short name T109
Test name
Test status
Simulation time 164572045 ps
CPU time 0.88 seconds
Started Jul 27 07:37:16 PM PDT 24
Finished Jul 27 07:37:17 PM PDT 24
Peak memory 207136 kb
Host smart-c3a4f9c9-1bef-48b4-92ce-4f65d778ba74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31189
08159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3118908159
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.3307644353
Short name T2260
Test name
Test status
Simulation time 1314837316 ps
CPU time 3.23 seconds
Started Jul 27 07:37:17 PM PDT 24
Finished Jul 27 07:37:20 PM PDT 24
Peak memory 207360 kb
Host smart-85badceb-5bce-4e3d-9ba9-759c348cd483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33076
44353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.3307644353
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.1373297481
Short name T1820
Test name
Test status
Simulation time 7004664236 ps
CPU time 67.18 seconds
Started Jul 27 07:37:20 PM PDT 24
Finished Jul 27 07:38:27 PM PDT 24
Peak memory 207368 kb
Host smart-1af89bc1-432a-4b0f-aef3-96b4dd70947d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13732
97481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1373297481
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.4230861395
Short name T2016
Test name
Test status
Simulation time 187174247 ps
CPU time 0.9 seconds
Started Jul 27 07:37:09 PM PDT 24
Finished Jul 27 07:37:10 PM PDT 24
Peak memory 207088 kb
Host smart-cc237bf8-069d-4e7a-8e9c-c551ae1002d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230861395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.4230861395
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2187441962
Short name T195
Test name
Test status
Simulation time 68530269 ps
CPU time 0.67 seconds
Started Jul 27 07:37:33 PM PDT 24
Finished Jul 27 07:37:33 PM PDT 24
Peak memory 207140 kb
Host smart-fadcb6d6-4624-49f1-ad4c-a70541d95ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2187441962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2187441962
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.1651186547
Short name T899
Test name
Test status
Simulation time 3711384176 ps
CPU time 6 seconds
Started Jul 27 07:37:18 PM PDT 24
Finished Jul 27 07:37:24 PM PDT 24
Peak memory 207348 kb
Host smart-f4ccc310-88a8-49cf-b34b-67c68e3cf458
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651186547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.1651186547
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.1932991112
Short name T858
Test name
Test status
Simulation time 13365077143 ps
CPU time 15.29 seconds
Started Jul 27 07:37:18 PM PDT 24
Finished Jul 27 07:37:34 PM PDT 24
Peak memory 207336 kb
Host smart-cd9a430f-5a40-4d37-aea0-90c92c29a59c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932991112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.1932991112
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.4061380755
Short name T1612
Test name
Test status
Simulation time 23369212649 ps
CPU time 28.39 seconds
Started Jul 27 07:37:23 PM PDT 24
Finished Jul 27 07:37:51 PM PDT 24
Peak memory 207308 kb
Host smart-4815717d-1157-41da-a143-183ae91e9cd9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061380755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.4061380755
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3544316719
Short name T2319
Test name
Test status
Simulation time 142001431 ps
CPU time 0.87 seconds
Started Jul 27 07:37:18 PM PDT 24
Finished Jul 27 07:37:19 PM PDT 24
Peak memory 207128 kb
Host smart-2e7311e9-e2fe-47e2-a034-767f03546104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35443
16719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3544316719
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.2295487485
Short name T2770
Test name
Test status
Simulation time 148844743 ps
CPU time 0.8 seconds
Started Jul 27 07:37:17 PM PDT 24
Finished Jul 27 07:37:18 PM PDT 24
Peak memory 207108 kb
Host smart-32dd192a-18cd-4d02-8499-e34430b5aaa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22954
87485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.2295487485
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1957540172
Short name T2284
Test name
Test status
Simulation time 603289365 ps
CPU time 1.86 seconds
Started Jul 27 07:37:18 PM PDT 24
Finished Jul 27 07:37:20 PM PDT 24
Peak memory 207404 kb
Host smart-5b67cff2-719c-40e0-9d41-6547eed3f8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19575
40172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1957540172
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.628703256
Short name T900
Test name
Test status
Simulation time 1354613879 ps
CPU time 3.24 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:31 PM PDT 24
Peak memory 207356 kb
Host smart-0c33322d-2efe-4105-903a-900f402a58bc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=628703256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.628703256
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3363521115
Short name T1569
Test name
Test status
Simulation time 16666318612 ps
CPU time 36.61 seconds
Started Jul 27 07:37:18 PM PDT 24
Finished Jul 27 07:37:55 PM PDT 24
Peak memory 207316 kb
Host smart-4ef85794-26c0-4359-9156-a23a5fe25dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33635
21115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3363521115
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.3004425373
Short name T2361
Test name
Test status
Simulation time 9036834433 ps
CPU time 62.86 seconds
Started Jul 27 07:37:18 PM PDT 24
Finished Jul 27 07:38:21 PM PDT 24
Peak memory 207388 kb
Host smart-3b5db75f-d541-4de2-9423-53905ef30325
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004425373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.3004425373
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3185337512
Short name T1000
Test name
Test status
Simulation time 426492851 ps
CPU time 1.4 seconds
Started Jul 27 07:37:20 PM PDT 24
Finished Jul 27 07:37:22 PM PDT 24
Peak memory 207032 kb
Host smart-297a1703-07f8-408d-bc70-ad583a75060d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31853
37512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3185337512
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.4120352952
Short name T38
Test name
Test status
Simulation time 151820683 ps
CPU time 0.82 seconds
Started Jul 27 07:37:25 PM PDT 24
Finished Jul 27 07:37:26 PM PDT 24
Peak memory 207164 kb
Host smart-246add00-48b3-4df0-b171-81805dbe2af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41203
52952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.4120352952
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.936991988
Short name T2169
Test name
Test status
Simulation time 39669162 ps
CPU time 0.68 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:30 PM PDT 24
Peak memory 207092 kb
Host smart-05be8f89-fe05-4029-ba67-f9bed183cd00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93699
1988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.936991988
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.119370470
Short name T650
Test name
Test status
Simulation time 886630274 ps
CPU time 2.54 seconds
Started Jul 27 07:37:27 PM PDT 24
Finished Jul 27 07:37:30 PM PDT 24
Peak memory 207360 kb
Host smart-e202585e-65d3-412a-a244-d700c1c124a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11937
0470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.119370470
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1153783016
Short name T1037
Test name
Test status
Simulation time 186831367 ps
CPU time 1.97 seconds
Started Jul 27 07:37:23 PM PDT 24
Finished Jul 27 07:37:25 PM PDT 24
Peak memory 207224 kb
Host smart-f2b008cc-becf-42a9-98c5-3b0a8c210f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11537
83016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1153783016
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1497228624
Short name T1081
Test name
Test status
Simulation time 212490635 ps
CPU time 1.1 seconds
Started Jul 27 07:37:25 PM PDT 24
Finished Jul 27 07:37:27 PM PDT 24
Peak memory 215556 kb
Host smart-a3b90adb-1944-4630-88b8-8a3c46050fa6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1497228624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1497228624
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.961221606
Short name T93
Test name
Test status
Simulation time 145222960 ps
CPU time 0.84 seconds
Started Jul 27 07:37:27 PM PDT 24
Finished Jul 27 07:37:28 PM PDT 24
Peak memory 207092 kb
Host smart-67981f45-2a55-4de4-ac31-ce7ec7df6a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96122
1606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.961221606
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.509599974
Short name T1829
Test name
Test status
Simulation time 192939231 ps
CPU time 0.93 seconds
Started Jul 27 07:37:26 PM PDT 24
Finished Jul 27 07:37:27 PM PDT 24
Peak memory 207156 kb
Host smart-b946e98d-691d-4e35-8ab0-a138e48dda1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50959
9974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.509599974
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.3614506637
Short name T2849
Test name
Test status
Simulation time 5613971507 ps
CPU time 52.94 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:38:21 PM PDT 24
Peak memory 215580 kb
Host smart-449cc24b-e157-47c5-8d5d-dea217449668
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3614506637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3614506637
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.873393678
Short name T2297
Test name
Test status
Simulation time 6808995033 ps
CPU time 47.68 seconds
Started Jul 27 07:37:21 PM PDT 24
Finished Jul 27 07:38:09 PM PDT 24
Peak memory 207360 kb
Host smart-43982fda-cbe1-465c-b3f5-4de903e14f31
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=873393678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.873393678
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1376977416
Short name T1108
Test name
Test status
Simulation time 186353456 ps
CPU time 0.85 seconds
Started Jul 27 07:37:25 PM PDT 24
Finished Jul 27 07:37:26 PM PDT 24
Peak memory 207192 kb
Host smart-f7e5bbdb-b4b0-4d74-9695-833449196f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13769
77416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1376977416
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.963086248
Short name T656
Test name
Test status
Simulation time 23265443666 ps
CPU time 29.91 seconds
Started Jul 27 07:37:26 PM PDT 24
Finished Jul 27 07:37:56 PM PDT 24
Peak memory 207416 kb
Host smart-0d87d0be-137d-4a71-a711-acf2d66c2976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96308
6248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.963086248
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2227696148
Short name T1791
Test name
Test status
Simulation time 3321757215 ps
CPU time 5.08 seconds
Started Jul 27 07:37:27 PM PDT 24
Finished Jul 27 07:37:32 PM PDT 24
Peak memory 207328 kb
Host smart-1a82ed4b-1985-443b-951b-d1d26ac4006c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22276
96148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2227696148
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2928859381
Short name T2680
Test name
Test status
Simulation time 4634260212 ps
CPU time 47.47 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:38:16 PM PDT 24
Peak memory 223616 kb
Host smart-0a2f2953-f56a-4c72-aa96-2f5672d5c0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29288
59381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2928859381
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.252357786
Short name T785
Test name
Test status
Simulation time 4673586751 ps
CPU time 133.77 seconds
Started Jul 27 07:37:27 PM PDT 24
Finished Jul 27 07:39:41 PM PDT 24
Peak memory 215504 kb
Host smart-06c9a247-b334-446d-abf5-0a8400296d46
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=252357786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.252357786
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.1590488777
Short name T1688
Test name
Test status
Simulation time 244669473 ps
CPU time 0.99 seconds
Started Jul 27 07:37:26 PM PDT 24
Finished Jul 27 07:37:27 PM PDT 24
Peak memory 207124 kb
Host smart-96bacbaa-06ad-4490-81c0-e5bcdddb3665
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1590488777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.1590488777
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2192411608
Short name T367
Test name
Test status
Simulation time 201488980 ps
CPU time 0.96 seconds
Started Jul 27 07:37:31 PM PDT 24
Finished Jul 27 07:37:32 PM PDT 24
Peak memory 207124 kb
Host smart-d89af8c3-6f0f-4cd3-8067-ceb9f726612a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21924
11608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2192411608
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1668114790
Short name T1624
Test name
Test status
Simulation time 5077391297 ps
CPU time 41.12 seconds
Started Jul 27 07:37:32 PM PDT 24
Finished Jul 27 07:38:13 PM PDT 24
Peak memory 216796 kb
Host smart-a50a4f6f-1775-4af8-9dd0-736b3ee7a5c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16681
14790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1668114790
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.3313755647
Short name T1019
Test name
Test status
Simulation time 5975763557 ps
CPU time 176.74 seconds
Started Jul 27 07:37:27 PM PDT 24
Finished Jul 27 07:40:24 PM PDT 24
Peak memory 215544 kb
Host smart-d2a41910-b615-487f-9cb0-54f141d64a6d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3313755647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.3313755647
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3757735199
Short name T448
Test name
Test status
Simulation time 189710816 ps
CPU time 0.88 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:30 PM PDT 24
Peak memory 207092 kb
Host smart-25ce74ea-aa1e-4e60-9487-6129c3ea3bdc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3757735199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3757735199
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.531562762
Short name T1616
Test name
Test status
Simulation time 149762891 ps
CPU time 0.86 seconds
Started Jul 27 07:37:26 PM PDT 24
Finished Jul 27 07:37:27 PM PDT 24
Peak memory 207164 kb
Host smart-430559da-e0d7-4aae-ad1e-0db83e25ef59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53156
2762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.531562762
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.231407347
Short name T880
Test name
Test status
Simulation time 157793165 ps
CPU time 0.87 seconds
Started Jul 27 07:37:26 PM PDT 24
Finished Jul 27 07:37:27 PM PDT 24
Peak memory 207132 kb
Host smart-9a7009b4-39dd-4a3f-a466-99cf94bf8527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23140
7347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.231407347
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3477984499
Short name T2353
Test name
Test status
Simulation time 229334408 ps
CPU time 0.93 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:29 PM PDT 24
Peak memory 207092 kb
Host smart-2a1945f7-f3ab-4dd1-a8ab-80952ab64949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34779
84499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3477984499
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.248931419
Short name T1745
Test name
Test status
Simulation time 158269303 ps
CPU time 0.86 seconds
Started Jul 27 07:37:26 PM PDT 24
Finished Jul 27 07:37:28 PM PDT 24
Peak memory 207096 kb
Host smart-5731b246-d466-4261-971a-54d02318f11e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24893
1419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.248931419
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3745902325
Short name T2150
Test name
Test status
Simulation time 150915131 ps
CPU time 0.84 seconds
Started Jul 27 07:37:27 PM PDT 24
Finished Jul 27 07:37:28 PM PDT 24
Peak memory 207132 kb
Host smart-3ed9815e-8fc0-49b2-9de2-b8b8d237c740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37459
02325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3745902325
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.3622630123
Short name T788
Test name
Test status
Simulation time 257347537 ps
CPU time 1.04 seconds
Started Jul 27 07:37:31 PM PDT 24
Finished Jul 27 07:37:32 PM PDT 24
Peak memory 207136 kb
Host smart-2cd0dfa2-666c-4d82-8240-b322e230c29f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3622630123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.3622630123
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3105453946
Short name T200
Test name
Test status
Simulation time 149026838 ps
CPU time 0.81 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:30 PM PDT 24
Peak memory 207128 kb
Host smart-b757fbfc-84aa-4618-ae05-912469b9c4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31054
53946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3105453946
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.85728540
Short name T2807
Test name
Test status
Simulation time 60992503 ps
CPU time 0.73 seconds
Started Jul 27 07:37:27 PM PDT 24
Finished Jul 27 07:37:28 PM PDT 24
Peak memory 207108 kb
Host smart-078de7aa-7348-4ee7-9670-ce12a9be4013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85728
540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.85728540
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1182317317
Short name T2105
Test name
Test status
Simulation time 24206219792 ps
CPU time 61.23 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:38:30 PM PDT 24
Peak memory 215540 kb
Host smart-3d94330a-073a-429f-bade-71aad014e4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11823
17317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1182317317
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1858356021
Short name T2588
Test name
Test status
Simulation time 183325372 ps
CPU time 0.92 seconds
Started Jul 27 07:37:25 PM PDT 24
Finished Jul 27 07:37:26 PM PDT 24
Peak memory 207100 kb
Host smart-f7262e58-5a84-471b-9b1e-605b6b2cc723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18583
56021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1858356021
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3668418814
Short name T1490
Test name
Test status
Simulation time 183385393 ps
CPU time 0.87 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:30 PM PDT 24
Peak memory 207140 kb
Host smart-7f02abf9-4589-467b-a1a1-626d9dba4c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36684
18814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3668418814
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3644982174
Short name T1994
Test name
Test status
Simulation time 253806086 ps
CPU time 1.07 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:30 PM PDT 24
Peak memory 207352 kb
Host smart-8c69624f-599e-487e-9ae2-06b3ccad67bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36449
82174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3644982174
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1452931073
Short name T1340
Test name
Test status
Simulation time 187576566 ps
CPU time 0.98 seconds
Started Jul 27 07:37:26 PM PDT 24
Finished Jul 27 07:37:27 PM PDT 24
Peak memory 207100 kb
Host smart-d4dea041-28ec-48a2-9fd0-a692677f9100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14529
31073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1452931073
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2203728778
Short name T1710
Test name
Test status
Simulation time 141758161 ps
CPU time 0.84 seconds
Started Jul 27 07:37:29 PM PDT 24
Finished Jul 27 07:37:30 PM PDT 24
Peak memory 207076 kb
Host smart-3ae71e58-0141-49b7-8931-0d3cdf1041e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22037
28778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2203728778
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3735883870
Short name T1158
Test name
Test status
Simulation time 152039519 ps
CPU time 0.82 seconds
Started Jul 27 07:37:30 PM PDT 24
Finished Jul 27 07:37:31 PM PDT 24
Peak memory 207104 kb
Host smart-29a3c8f5-d80a-45d1-af24-caae46538751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37358
83870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3735883870
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.853628036
Short name T1247
Test name
Test status
Simulation time 184075816 ps
CPU time 0.86 seconds
Started Jul 27 07:37:33 PM PDT 24
Finished Jul 27 07:37:34 PM PDT 24
Peak memory 207156 kb
Host smart-5ad58a87-b29d-4152-8729-dc9bf23617da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85362
8036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.853628036
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2837328526
Short name T664
Test name
Test status
Simulation time 184838363 ps
CPU time 0.96 seconds
Started Jul 27 07:37:26 PM PDT 24
Finished Jul 27 07:37:27 PM PDT 24
Peak memory 207140 kb
Host smart-4131c9be-d075-49ea-a0c4-62beda3fd670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28373
28526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2837328526
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2031380951
Short name T1461
Test name
Test status
Simulation time 3870897545 ps
CPU time 110.68 seconds
Started Jul 27 07:37:27 PM PDT 24
Finished Jul 27 07:39:18 PM PDT 24
Peak memory 215676 kb
Host smart-982d7a48-f063-41ab-b6d2-7f1ee176ee02
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2031380951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2031380951
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.1469984575
Short name T1054
Test name
Test status
Simulation time 157171230 ps
CPU time 0.83 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:29 PM PDT 24
Peak memory 207112 kb
Host smart-3a7b1e90-c234-41cd-8adf-1e60fbeaee92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14699
84575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1469984575
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.639794332
Short name T2793
Test name
Test status
Simulation time 560794849 ps
CPU time 1.61 seconds
Started Jul 27 07:37:29 PM PDT 24
Finished Jul 27 07:37:31 PM PDT 24
Peak memory 207036 kb
Host smart-e758df80-47ad-4248-b220-896eab8c7e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63979
4332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.639794332
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.2728517931
Short name T845
Test name
Test status
Simulation time 4827310555 ps
CPU time 134.91 seconds
Started Jul 27 07:37:31 PM PDT 24
Finished Jul 27 07:39:47 PM PDT 24
Peak memory 223480 kb
Host smart-71e264ff-6661-4d86-9c84-6368dde01f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27285
17931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.2728517931
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.2705460328
Short name T2820
Test name
Test status
Simulation time 2496225472 ps
CPU time 22.75 seconds
Started Jul 27 07:37:18 PM PDT 24
Finished Jul 27 07:37:41 PM PDT 24
Peak memory 207324 kb
Host smart-432faf2f-7d5f-4514-8ce8-16779902a484
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705460328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.2705460328
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.101770266
Short name T2681
Test name
Test status
Simulation time 55481928 ps
CPU time 0.69 seconds
Started Jul 27 07:37:41 PM PDT 24
Finished Jul 27 07:37:42 PM PDT 24
Peak memory 207144 kb
Host smart-bf0514fe-410a-4664-a402-5d04da9f51be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=101770266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.101770266
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3416492314
Short name T2212
Test name
Test status
Simulation time 4303940763 ps
CPU time 6.93 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:35 PM PDT 24
Peak memory 207376 kb
Host smart-e64a2330-65fa-4ae8-b6a0-7a7997d617cf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416492314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.3416492314
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2908264727
Short name T212
Test name
Test status
Simulation time 13327014123 ps
CPU time 16.72 seconds
Started Jul 27 07:37:29 PM PDT 24
Finished Jul 27 07:37:46 PM PDT 24
Peak memory 207396 kb
Host smart-aca40e1b-27cc-4671-97b4-b8f0f80508b5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908264727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2908264727
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2464762297
Short name T2722
Test name
Test status
Simulation time 23383238933 ps
CPU time 27.09 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:56 PM PDT 24
Peak memory 207332 kb
Host smart-b656ef32-7941-491c-8410-ca7ef0e5244e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464762297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.2464762297
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3422863091
Short name T955
Test name
Test status
Simulation time 168338837 ps
CPU time 0.86 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:29 PM PDT 24
Peak memory 207088 kb
Host smart-0e40edbf-e971-48e6-9b57-84e1758109b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34228
63091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3422863091
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.4266553934
Short name T1074
Test name
Test status
Simulation time 151902618 ps
CPU time 0.88 seconds
Started Jul 27 07:37:27 PM PDT 24
Finished Jul 27 07:37:28 PM PDT 24
Peak memory 207056 kb
Host smart-48bb1de8-ad4a-4fd6-8f09-6fceb76b147c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42665
53934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.4266553934
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1753507351
Short name T915
Test name
Test status
Simulation time 340698815 ps
CPU time 1.21 seconds
Started Jul 27 07:37:27 PM PDT 24
Finished Jul 27 07:37:28 PM PDT 24
Peak memory 207156 kb
Host smart-11f04ce0-537d-45e9-aed5-f1eb40f2e8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17535
07351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1753507351
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3799963590
Short name T1193
Test name
Test status
Simulation time 10204535472 ps
CPU time 22.24 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:50 PM PDT 24
Peak memory 207328 kb
Host smart-e4fde39b-afc6-4804-9ed2-827ab5f448e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37999
63590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3799963590
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.2763175602
Short name T2037
Test name
Test status
Simulation time 1049508948 ps
CPU time 8.68 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:38 PM PDT 24
Peak memory 207316 kb
Host smart-25f544dd-bba9-4f45-8ce0-19a2705d6029
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763175602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.2763175602
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3390738343
Short name T2165
Test name
Test status
Simulation time 402617004 ps
CPU time 1.3 seconds
Started Jul 27 07:37:30 PM PDT 24
Finished Jul 27 07:37:32 PM PDT 24
Peak memory 207068 kb
Host smart-26c91976-8d14-4c7d-8259-3c65fd95694a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33907
38343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3390738343
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.4245984792
Short name T792
Test name
Test status
Simulation time 144623900 ps
CPU time 0.81 seconds
Started Jul 27 07:37:29 PM PDT 24
Finished Jul 27 07:37:30 PM PDT 24
Peak memory 207032 kb
Host smart-42948117-773d-435a-b30c-441626051d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42459
84792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.4245984792
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1226653449
Short name T836
Test name
Test status
Simulation time 46790745 ps
CPU time 0.7 seconds
Started Jul 27 07:37:27 PM PDT 24
Finished Jul 27 07:37:28 PM PDT 24
Peak memory 207088 kb
Host smart-bcbb3d49-47da-4cd7-b6b9-ad23aa0dc390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12266
53449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1226653449
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2136017174
Short name T1983
Test name
Test status
Simulation time 1053650198 ps
CPU time 2.6 seconds
Started Jul 27 07:37:32 PM PDT 24
Finished Jul 27 07:37:34 PM PDT 24
Peak memory 207304 kb
Host smart-5fa343f7-f872-466a-97af-a6cdd5276589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21360
17174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2136017174
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.1723718568
Short name T2779
Test name
Test status
Simulation time 196211619 ps
CPU time 2.49 seconds
Started Jul 27 07:37:31 PM PDT 24
Finished Jul 27 07:37:33 PM PDT 24
Peak memory 207348 kb
Host smart-f872bad0-85b4-490f-b580-5d59d17462de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17237
18568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.1723718568
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3289149705
Short name T1754
Test name
Test status
Simulation time 211338373 ps
CPU time 0.99 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:29 PM PDT 24
Peak memory 207116 kb
Host smart-44a9df92-b211-419b-868a-1e55fce03b0b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3289149705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3289149705
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1055031169
Short name T2814
Test name
Test status
Simulation time 140693823 ps
CPU time 0.86 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:29 PM PDT 24
Peak memory 207088 kb
Host smart-7e9ec3ea-bb00-484d-a82d-d0fc03539304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10550
31169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1055031169
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2572517554
Short name T2177
Test name
Test status
Simulation time 242556810 ps
CPU time 1.03 seconds
Started Jul 27 07:37:28 PM PDT 24
Finished Jul 27 07:37:30 PM PDT 24
Peak memory 207348 kb
Host smart-df1a48f7-cd92-4eee-84f6-3b836524a736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25725
17554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2572517554
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.2607005903
Short name T1523
Test name
Test status
Simulation time 6094898836 ps
CPU time 46.49 seconds
Started Jul 27 07:37:30 PM PDT 24
Finished Jul 27 07:38:16 PM PDT 24
Peak memory 217224 kb
Host smart-1f2e58d7-2b90-4726-9ff5-56cdc1e6f710
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2607005903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.2607005903
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.132254048
Short name T1304
Test name
Test status
Simulation time 7000991165 ps
CPU time 48.24 seconds
Started Jul 27 07:37:34 PM PDT 24
Finished Jul 27 07:38:22 PM PDT 24
Peak memory 207432 kb
Host smart-cd121ee0-aee8-4a19-b6fa-4ac7f8a771ec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=132254048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.132254048
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3001455902
Short name T2813
Test name
Test status
Simulation time 230928158 ps
CPU time 0.97 seconds
Started Jul 27 07:37:37 PM PDT 24
Finished Jul 27 07:37:38 PM PDT 24
Peak memory 207060 kb
Host smart-06ae4388-b3bc-46d5-a78f-87e0a4337fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30014
55902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3001455902
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3422005362
Short name T2729
Test name
Test status
Simulation time 23347593811 ps
CPU time 29.3 seconds
Started Jul 27 07:37:33 PM PDT 24
Finished Jul 27 07:38:02 PM PDT 24
Peak memory 207176 kb
Host smart-bebb34bf-e986-4f2a-8ed4-feb8f1e93356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34220
05362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3422005362
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1900282905
Short name T348
Test name
Test status
Simulation time 3353028970 ps
CPU time 5.54 seconds
Started Jul 27 07:37:38 PM PDT 24
Finished Jul 27 07:37:43 PM PDT 24
Peak memory 207412 kb
Host smart-436be844-65fd-4647-be65-9f6ee6ed3822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19002
82905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1900282905
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.2873600052
Short name T1063
Test name
Test status
Simulation time 5076681470 ps
CPU time 141.98 seconds
Started Jul 27 07:37:35 PM PDT 24
Finished Jul 27 07:39:57 PM PDT 24
Peak memory 215560 kb
Host smart-a1a6cb35-e79c-4722-b2b3-4f2a650a2823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28736
00052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.2873600052
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1704336302
Short name T994
Test name
Test status
Simulation time 5575580177 ps
CPU time 168.67 seconds
Started Jul 27 07:37:32 PM PDT 24
Finished Jul 27 07:40:21 PM PDT 24
Peak memory 215632 kb
Host smart-3398ff01-37ac-4863-b056-3d53189d26d0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1704336302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1704336302
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.152977938
Short name T2753
Test name
Test status
Simulation time 255750945 ps
CPU time 1.04 seconds
Started Jul 27 07:37:39 PM PDT 24
Finished Jul 27 07:37:40 PM PDT 24
Peak memory 207120 kb
Host smart-a98bb04e-68f4-48ea-92ed-5686a0773011
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=152977938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.152977938
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1329966217
Short name T1240
Test name
Test status
Simulation time 195687019 ps
CPU time 0.95 seconds
Started Jul 27 07:37:33 PM PDT 24
Finished Jul 27 07:37:34 PM PDT 24
Peak memory 207016 kb
Host smart-bd408f51-72d3-4f82-a01e-1697c4751791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13299
66217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1329966217
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.3796576740
Short name T1544
Test name
Test status
Simulation time 5532404486 ps
CPU time 43.58 seconds
Started Jul 27 07:37:39 PM PDT 24
Finished Jul 27 07:38:22 PM PDT 24
Peak memory 217168 kb
Host smart-d3e42fe8-8091-40d6-93bc-5f3b1d90cd3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37965
76740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.3796576740
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1375408168
Short name T1992
Test name
Test status
Simulation time 5000350064 ps
CPU time 148.42 seconds
Started Jul 27 07:37:37 PM PDT 24
Finished Jul 27 07:40:06 PM PDT 24
Peak memory 215528 kb
Host smart-27907b58-67a2-4fb6-b2f7-0911d214419e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1375408168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1375408168
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3756483024
Short name T374
Test name
Test status
Simulation time 160388061 ps
CPU time 0.85 seconds
Started Jul 27 07:37:34 PM PDT 24
Finished Jul 27 07:37:35 PM PDT 24
Peak memory 207164 kb
Host smart-2c9d15e1-fe53-405d-b553-657d081292b5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3756483024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3756483024
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2944731623
Short name T2612
Test name
Test status
Simulation time 164399669 ps
CPU time 0.83 seconds
Started Jul 27 07:37:39 PM PDT 24
Finished Jul 27 07:37:39 PM PDT 24
Peak memory 207100 kb
Host smart-5e72e49f-2f0d-4efa-ba75-99ee185d5bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29447
31623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2944731623
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1923973877
Short name T763
Test name
Test status
Simulation time 225406324 ps
CPU time 0.89 seconds
Started Jul 27 07:37:38 PM PDT 24
Finished Jul 27 07:37:39 PM PDT 24
Peak memory 207108 kb
Host smart-dae841b0-7c57-4491-92b5-b221fe568dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19239
73877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1923973877
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.701456713
Short name T2400
Test name
Test status
Simulation time 198507376 ps
CPU time 0.9 seconds
Started Jul 27 07:37:31 PM PDT 24
Finished Jul 27 07:37:32 PM PDT 24
Peak memory 207136 kb
Host smart-cc8086f5-72a3-4159-9ba4-8f6a5f54ddd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70145
6713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.701456713
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2734480156
Short name T2802
Test name
Test status
Simulation time 181185432 ps
CPU time 0.89 seconds
Started Jul 27 07:37:37 PM PDT 24
Finished Jul 27 07:37:38 PM PDT 24
Peak memory 207148 kb
Host smart-53e6ed16-2bda-4640-8603-5d52c59b434c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27344
80156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2734480156
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1179876111
Short name T2034
Test name
Test status
Simulation time 169493854 ps
CPU time 0.89 seconds
Started Jul 27 07:37:37 PM PDT 24
Finished Jul 27 07:37:38 PM PDT 24
Peak memory 207064 kb
Host smart-124b6973-a9f7-4afa-9c1e-ceedbf1cc71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11798
76111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1179876111
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.2004275140
Short name T77
Test name
Test status
Simulation time 268123538 ps
CPU time 1.12 seconds
Started Jul 27 07:37:34 PM PDT 24
Finished Jul 27 07:37:35 PM PDT 24
Peak memory 207036 kb
Host smart-1cc1e897-5a23-4a18-b030-cba94b4a0eee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2004275140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.2004275140
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1874423330
Short name T1871
Test name
Test status
Simulation time 144788148 ps
CPU time 0.87 seconds
Started Jul 27 07:37:36 PM PDT 24
Finished Jul 27 07:37:37 PM PDT 24
Peak memory 206992 kb
Host smart-c20a46a5-511f-43de-a036-bc03060c16f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18744
23330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1874423330
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1890500077
Short name T2835
Test name
Test status
Simulation time 36438714 ps
CPU time 0.81 seconds
Started Jul 27 07:37:34 PM PDT 24
Finished Jul 27 07:37:35 PM PDT 24
Peak memory 207080 kb
Host smart-660fa8dd-e4b0-4136-8b68-c9472575e6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18905
00077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1890500077
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1838570084
Short name T257
Test name
Test status
Simulation time 6471662783 ps
CPU time 17.59 seconds
Started Jul 27 07:37:37 PM PDT 24
Finished Jul 27 07:37:55 PM PDT 24
Peak memory 215556 kb
Host smart-68751f43-5f25-4661-960c-8942c4ab18c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18385
70084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1838570084
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2053712843
Short name T316
Test name
Test status
Simulation time 198661231 ps
CPU time 0.96 seconds
Started Jul 27 07:37:39 PM PDT 24
Finished Jul 27 07:37:40 PM PDT 24
Peak memory 207144 kb
Host smart-a7f05e74-41e6-484b-b0b5-aebefed11438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20537
12843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2053712843
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3585403453
Short name T2627
Test name
Test status
Simulation time 184957852 ps
CPU time 0.89 seconds
Started Jul 27 07:37:34 PM PDT 24
Finished Jul 27 07:37:35 PM PDT 24
Peak memory 207092 kb
Host smart-b24fd835-9871-4adb-9496-6bbaa1397e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35854
03453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3585403453
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1050452796
Short name T2329
Test name
Test status
Simulation time 242770003 ps
CPU time 1.06 seconds
Started Jul 27 07:37:35 PM PDT 24
Finished Jul 27 07:37:36 PM PDT 24
Peak memory 207100 kb
Host smart-3a1e9e7c-4397-4885-9f7f-89c6751afd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10504
52796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1050452796
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1241187744
Short name T2678
Test name
Test status
Simulation time 164920010 ps
CPU time 0.88 seconds
Started Jul 27 07:37:37 PM PDT 24
Finished Jul 27 07:37:38 PM PDT 24
Peak memory 207148 kb
Host smart-abda90bb-d679-4028-a308-165f80640662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12411
87744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1241187744
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3638028219
Short name T1702
Test name
Test status
Simulation time 168457398 ps
CPU time 0.84 seconds
Started Jul 27 07:37:37 PM PDT 24
Finished Jul 27 07:37:38 PM PDT 24
Peak memory 207124 kb
Host smart-2725f3af-339a-47a4-9385-2d62dce627e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36380
28219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3638028219
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3389592911
Short name T2098
Test name
Test status
Simulation time 164792656 ps
CPU time 0.83 seconds
Started Jul 27 07:37:37 PM PDT 24
Finished Jul 27 07:37:38 PM PDT 24
Peak memory 207132 kb
Host smart-536e9528-27a4-41db-82c8-cad9447d7da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33895
92911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3389592911
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2280446908
Short name T1726
Test name
Test status
Simulation time 152044483 ps
CPU time 0.86 seconds
Started Jul 27 07:37:32 PM PDT 24
Finished Jul 27 07:37:33 PM PDT 24
Peak memory 207092 kb
Host smart-152d272d-cfa5-475d-be07-410f062ddd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22804
46908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2280446908
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.171658469
Short name T28
Test name
Test status
Simulation time 226950042 ps
CPU time 1.06 seconds
Started Jul 27 07:37:36 PM PDT 24
Finished Jul 27 07:37:37 PM PDT 24
Peak memory 207144 kb
Host smart-907900dd-e016-4f3e-9375-c3f648e5687a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17165
8469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.171658469
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.2555634819
Short name T2254
Test name
Test status
Simulation time 3446018081 ps
CPU time 106.36 seconds
Started Jul 27 07:37:37 PM PDT 24
Finished Jul 27 07:39:24 PM PDT 24
Peak memory 215560 kb
Host smart-d02d501e-0378-4784-b841-f72dc55d8646
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2555634819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.2555634819
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.777375144
Short name T2022
Test name
Test status
Simulation time 165452257 ps
CPU time 0.86 seconds
Started Jul 27 07:37:33 PM PDT 24
Finished Jul 27 07:37:34 PM PDT 24
Peak memory 206928 kb
Host smart-31cc2e9f-7407-4a37-89e2-2affe328fe4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77737
5144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.777375144
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1673178451
Short name T489
Test name
Test status
Simulation time 142495755 ps
CPU time 0.83 seconds
Started Jul 27 07:37:33 PM PDT 24
Finished Jul 27 07:37:34 PM PDT 24
Peak memory 207108 kb
Host smart-9ea534bb-834c-4727-abb1-d0b0e6be7303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16731
78451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1673178451
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3798375477
Short name T723
Test name
Test status
Simulation time 558518235 ps
CPU time 1.51 seconds
Started Jul 27 07:37:44 PM PDT 24
Finished Jul 27 07:37:46 PM PDT 24
Peak memory 207104 kb
Host smart-7e291322-4caf-4ffd-abeb-d719c553ad1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37983
75477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3798375477
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.591397180
Short name T398
Test name
Test status
Simulation time 3618619712 ps
CPU time 26.93 seconds
Started Jul 27 07:37:36 PM PDT 24
Finished Jul 27 07:38:03 PM PDT 24
Peak memory 207248 kb
Host smart-7e42b59f-78e2-4fbd-b585-e24e94d63274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59139
7180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.591397180
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.96599545
Short name T892
Test name
Test status
Simulation time 1549792837 ps
CPU time 35.76 seconds
Started Jul 27 07:37:32 PM PDT 24
Finished Jul 27 07:38:07 PM PDT 24
Peak memory 207312 kb
Host smart-dc1a0ab5-c3eb-4718-a9f1-35641feccc01
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96599545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_host_
handshake.96599545
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.2106989720
Short name T2785
Test name
Test status
Simulation time 55584333 ps
CPU time 0.68 seconds
Started Jul 27 07:37:54 PM PDT 24
Finished Jul 27 07:37:55 PM PDT 24
Peak memory 207228 kb
Host smart-19451c61-879e-455a-abf7-763d4de34456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2106989720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.2106989720
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3089488729
Short name T852
Test name
Test status
Simulation time 3853633205 ps
CPU time 5.47 seconds
Started Jul 27 07:37:40 PM PDT 24
Finished Jul 27 07:37:45 PM PDT 24
Peak memory 207572 kb
Host smart-1e101c00-ab08-4149-8573-05702633e6d2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089488729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.3089488729
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.406474631
Short name T662
Test name
Test status
Simulation time 13355083400 ps
CPU time 16.2 seconds
Started Jul 27 07:37:40 PM PDT 24
Finished Jul 27 07:37:56 PM PDT 24
Peak memory 207300 kb
Host smart-8a7227ec-9d72-4658-95bc-29743ab764fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=406474631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.406474631
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2784321687
Short name T231
Test name
Test status
Simulation time 23489984830 ps
CPU time 30.43 seconds
Started Jul 27 07:37:38 PM PDT 24
Finished Jul 27 07:38:09 PM PDT 24
Peak memory 207368 kb
Host smart-9a64f884-c3d9-424f-bd2a-24275011b805
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784321687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_resume.2784321687
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.378014335
Short name T1345
Test name
Test status
Simulation time 171286665 ps
CPU time 0.88 seconds
Started Jul 27 07:37:39 PM PDT 24
Finished Jul 27 07:37:40 PM PDT 24
Peak memory 207104 kb
Host smart-8f48828f-b61f-4fb9-9369-e38cd7e69988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37801
4335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.378014335
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.2624026359
Short name T1560
Test name
Test status
Simulation time 163716840 ps
CPU time 0.91 seconds
Started Jul 27 07:37:45 PM PDT 24
Finished Jul 27 07:37:46 PM PDT 24
Peak memory 207112 kb
Host smart-07dde42b-17cc-4fca-92b2-aa778c083ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26240
26359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.2624026359
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.4200035691
Short name T1938
Test name
Test status
Simulation time 308030038 ps
CPU time 1.33 seconds
Started Jul 27 07:37:39 PM PDT 24
Finished Jul 27 07:37:40 PM PDT 24
Peak memory 207140 kb
Host smart-c7d88d1e-d96f-4c4b-98b4-0d89ca76cb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42000
35691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.4200035691
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.393015572
Short name T1229
Test name
Test status
Simulation time 1297163819 ps
CPU time 3.24 seconds
Started Jul 27 07:37:38 PM PDT 24
Finished Jul 27 07:37:41 PM PDT 24
Peak memory 207304 kb
Host smart-92cfa15f-0ad2-45d5-9ce3-31f511beb416
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=393015572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.393015572
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2405412504
Short name T1608
Test name
Test status
Simulation time 15744202882 ps
CPU time 35.5 seconds
Started Jul 27 07:37:42 PM PDT 24
Finished Jul 27 07:38:17 PM PDT 24
Peak memory 207388 kb
Host smart-bb155048-7dd4-4b84-8893-385beea945db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24054
12504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2405412504
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.2768113679
Short name T2263
Test name
Test status
Simulation time 189297904 ps
CPU time 0.88 seconds
Started Jul 27 07:37:38 PM PDT 24
Finished Jul 27 07:37:39 PM PDT 24
Peak memory 207096 kb
Host smart-6cccd0c5-d869-4bfa-9955-398af09bced3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768113679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.2768113679
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.2422822238
Short name T902
Test name
Test status
Simulation time 346065563 ps
CPU time 1.27 seconds
Started Jul 27 07:37:39 PM PDT 24
Finished Jul 27 07:37:41 PM PDT 24
Peak memory 207108 kb
Host smart-1d1db8b1-f73f-4d87-869d-93b51fe249ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24228
22238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.2422822238
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.228252020
Short name T794
Test name
Test status
Simulation time 156767779 ps
CPU time 0.85 seconds
Started Jul 27 07:37:41 PM PDT 24
Finished Jul 27 07:37:41 PM PDT 24
Peak memory 207104 kb
Host smart-7d629f4b-f91e-41d8-b06d-07d140708cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22825
2020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.228252020
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2609395706
Short name T1263
Test name
Test status
Simulation time 30055543 ps
CPU time 0.69 seconds
Started Jul 27 07:37:40 PM PDT 24
Finished Jul 27 07:37:41 PM PDT 24
Peak memory 206992 kb
Host smart-de04ad63-8c87-4358-a30f-32fdcb539eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26093
95706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2609395706
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.382955251
Short name T1219
Test name
Test status
Simulation time 891599359 ps
CPU time 2.45 seconds
Started Jul 27 07:37:42 PM PDT 24
Finished Jul 27 07:37:45 PM PDT 24
Peak memory 207372 kb
Host smart-98e8ecd7-8d0c-4611-b904-099ddcb7df14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38295
5251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.382955251
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1954871818
Short name T549
Test name
Test status
Simulation time 192845387 ps
CPU time 2.31 seconds
Started Jul 27 07:37:40 PM PDT 24
Finished Jul 27 07:37:42 PM PDT 24
Peak memory 207260 kb
Host smart-52583458-b473-41b2-9433-bf7de8bff297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19548
71818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1954871818
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2879325924
Short name T1486
Test name
Test status
Simulation time 161804849 ps
CPU time 0.93 seconds
Started Jul 27 07:37:39 PM PDT 24
Finished Jul 27 07:37:41 PM PDT 24
Peak memory 207116 kb
Host smart-fdb5dac9-dbba-47f7-a97a-cf80101a832d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2879325924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2879325924
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.1281883382
Short name T1957
Test name
Test status
Simulation time 166605364 ps
CPU time 0.87 seconds
Started Jul 27 07:37:38 PM PDT 24
Finished Jul 27 07:37:39 PM PDT 24
Peak memory 206980 kb
Host smart-4bd1bcbd-14b4-49d6-8dd0-6a89669395fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12818
83382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1281883382
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3717001287
Short name T2805
Test name
Test status
Simulation time 239475691 ps
CPU time 1.02 seconds
Started Jul 27 07:37:39 PM PDT 24
Finished Jul 27 07:37:40 PM PDT 24
Peak memory 207096 kb
Host smart-373687a5-0555-46f1-a2a4-f1c6c674c5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37170
01287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3717001287
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.2647537490
Short name T1389
Test name
Test status
Simulation time 6780722798 ps
CPU time 62.97 seconds
Started Jul 27 07:37:39 PM PDT 24
Finished Jul 27 07:38:42 PM PDT 24
Peak memory 216784 kb
Host smart-5172d656-64f1-4ccc-9ec3-4f92970ed07e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2647537490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.2647537490
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.3651462498
Short name T867
Test name
Test status
Simulation time 7849435538 ps
CPU time 50.85 seconds
Started Jul 27 07:37:39 PM PDT 24
Finished Jul 27 07:38:30 PM PDT 24
Peak memory 207320 kb
Host smart-e6da48a8-49b2-45bf-a21f-2e8e06dbc354
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3651462498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.3651462498
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.656988387
Short name T1694
Test name
Test status
Simulation time 23359023680 ps
CPU time 33.43 seconds
Started Jul 27 07:37:39 PM PDT 24
Finished Jul 27 07:38:12 PM PDT 24
Peak memory 207316 kb
Host smart-6a16334e-28e2-4cc3-9bd6-b5dae081b0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65698
8387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.656988387
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.80142696
Short name T1335
Test name
Test status
Simulation time 3256773372 ps
CPU time 5.06 seconds
Started Jul 27 07:37:47 PM PDT 24
Finished Jul 27 07:37:53 PM PDT 24
Peak memory 207364 kb
Host smart-7e25a0e9-fa51-44d2-bc12-c3cada2c87a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80142
696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.80142696
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.1688339319
Short name T744
Test name
Test status
Simulation time 8156137211 ps
CPU time 58.59 seconds
Started Jul 27 07:37:49 PM PDT 24
Finished Jul 27 07:38:47 PM PDT 24
Peak memory 217612 kb
Host smart-abd260c0-5a8b-4c1a-93d6-e01e5639c113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16883
39319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.1688339319
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1676497392
Short name T1731
Test name
Test status
Simulation time 4301055150 ps
CPU time 43.99 seconds
Started Jul 27 07:37:49 PM PDT 24
Finished Jul 27 07:38:33 PM PDT 24
Peak memory 207304 kb
Host smart-8150a0a2-b6f4-4333-b651-1cb35ae7178d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1676497392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1676497392
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3130098690
Short name T1210
Test name
Test status
Simulation time 253400412 ps
CPU time 0.98 seconds
Started Jul 27 07:37:51 PM PDT 24
Finished Jul 27 07:37:52 PM PDT 24
Peak memory 207152 kb
Host smart-3123b6d8-9600-4810-8bc4-adf457c34591
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3130098690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3130098690
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1903459586
Short name T2137
Test name
Test status
Simulation time 185945182 ps
CPU time 0.94 seconds
Started Jul 27 07:37:48 PM PDT 24
Finished Jul 27 07:37:49 PM PDT 24
Peak memory 207060 kb
Host smart-5c3bf04f-a7f7-49be-bf79-c827b4bea56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19034
59586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1903459586
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.298413308
Short name T2655
Test name
Test status
Simulation time 6652533560 ps
CPU time 191.53 seconds
Started Jul 27 07:37:49 PM PDT 24
Finished Jul 27 07:41:00 PM PDT 24
Peak memory 215504 kb
Host smart-05ab795c-37ae-4b23-877b-738bde3e3f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29841
3308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.298413308
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1485665061
Short name T800
Test name
Test status
Simulation time 7209397547 ps
CPU time 216.7 seconds
Started Jul 27 07:37:46 PM PDT 24
Finished Jul 27 07:41:23 PM PDT 24
Peak memory 215584 kb
Host smart-b610e62d-40fa-4e8d-9b2f-97b8fd3d064f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1485665061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1485665061
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.4189248333
Short name T1810
Test name
Test status
Simulation time 159914936 ps
CPU time 0.9 seconds
Started Jul 27 07:37:49 PM PDT 24
Finished Jul 27 07:37:50 PM PDT 24
Peak memory 207096 kb
Host smart-e0b090d1-226f-40d6-8c75-392466ea1dc1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4189248333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.4189248333
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2100417109
Short name T1396
Test name
Test status
Simulation time 143834842 ps
CPU time 0.81 seconds
Started Jul 27 07:37:46 PM PDT 24
Finished Jul 27 07:37:47 PM PDT 24
Peak memory 207104 kb
Host smart-7db81ca1-20b6-4ce9-bc58-0704d77d2aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21004
17109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2100417109
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1560389161
Short name T116
Test name
Test status
Simulation time 214900347 ps
CPU time 1 seconds
Started Jul 27 07:37:47 PM PDT 24
Finished Jul 27 07:37:48 PM PDT 24
Peak memory 207208 kb
Host smart-3dff3443-f3d5-4b42-918c-e3d5a185cfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15603
89161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1560389161
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1148781459
Short name T2620
Test name
Test status
Simulation time 148152704 ps
CPU time 0.86 seconds
Started Jul 27 07:37:48 PM PDT 24
Finished Jul 27 07:37:49 PM PDT 24
Peak memory 207096 kb
Host smart-9a7dc9e2-bb12-475e-96f5-b211a89d39d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11487
81459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1148781459
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2778924160
Short name T1811
Test name
Test status
Simulation time 191307084 ps
CPU time 0.83 seconds
Started Jul 27 07:37:48 PM PDT 24
Finished Jul 27 07:37:49 PM PDT 24
Peak memory 207128 kb
Host smart-9424849c-3993-4ba2-a3ca-fbe55e74e767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27789
24160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2778924160
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3728791692
Short name T2259
Test name
Test status
Simulation time 185795741 ps
CPU time 0.9 seconds
Started Jul 27 07:37:49 PM PDT 24
Finished Jul 27 07:37:50 PM PDT 24
Peak memory 207140 kb
Host smart-1703b4d3-64e4-47a7-af1e-da7fa345ea2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37287
91692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3728791692
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1340055477
Short name T814
Test name
Test status
Simulation time 158948290 ps
CPU time 0.88 seconds
Started Jul 27 07:37:46 PM PDT 24
Finished Jul 27 07:37:47 PM PDT 24
Peak memory 207104 kb
Host smart-b12fb8ed-6d44-4c75-90ae-bc7ed78db815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13400
55477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1340055477
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.1528225043
Short name T460
Test name
Test status
Simulation time 268600039 ps
CPU time 1.08 seconds
Started Jul 27 07:37:48 PM PDT 24
Finished Jul 27 07:37:49 PM PDT 24
Peak memory 207136 kb
Host smart-967feef2-d2a1-441a-b1d9-c6cf92b333f5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1528225043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.1528225043
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.557128309
Short name T939
Test name
Test status
Simulation time 219404975 ps
CPU time 0.89 seconds
Started Jul 27 07:37:55 PM PDT 24
Finished Jul 27 07:37:56 PM PDT 24
Peak memory 207132 kb
Host smart-0671efce-55fa-4d57-b468-e4bc3422b5c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55712
8309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.557128309
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2172165954
Short name T2528
Test name
Test status
Simulation time 89267221 ps
CPU time 0.74 seconds
Started Jul 27 07:37:55 PM PDT 24
Finished Jul 27 07:37:56 PM PDT 24
Peak memory 207092 kb
Host smart-8d9ed52f-a007-4c26-82d3-4a29590db2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21721
65954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2172165954
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3343235427
Short name T339
Test name
Test status
Simulation time 13230304367 ps
CPU time 38.43 seconds
Started Jul 27 07:37:48 PM PDT 24
Finished Jul 27 07:38:26 PM PDT 24
Peak memory 219608 kb
Host smart-d97b9df2-2492-40f0-9662-e7c2ccd16146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33432
35427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3343235427
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.705641032
Short name T2172
Test name
Test status
Simulation time 207389897 ps
CPU time 0.89 seconds
Started Jul 27 07:37:48 PM PDT 24
Finished Jul 27 07:37:49 PM PDT 24
Peak memory 207112 kb
Host smart-eabb6361-bc42-459a-9424-d8c519a966de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70564
1032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.705641032
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2300947485
Short name T2335
Test name
Test status
Simulation time 177349688 ps
CPU time 0.88 seconds
Started Jul 27 07:37:48 PM PDT 24
Finished Jul 27 07:37:49 PM PDT 24
Peak memory 207112 kb
Host smart-ca0c779b-5236-4a54-9754-8db528c9ef49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23009
47485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2300947485
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2165142005
Short name T1888
Test name
Test status
Simulation time 196676199 ps
CPU time 0.92 seconds
Started Jul 27 07:37:47 PM PDT 24
Finished Jul 27 07:37:48 PM PDT 24
Peak memory 207112 kb
Host smart-2da74d27-1065-4bac-9562-c0c83037a71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21651
42005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2165142005
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.3830832007
Short name T2273
Test name
Test status
Simulation time 225320995 ps
CPU time 0.99 seconds
Started Jul 27 07:37:47 PM PDT 24
Finished Jul 27 07:37:48 PM PDT 24
Peak memory 207024 kb
Host smart-da23ac04-26ab-4e51-b831-3d6b9c3392a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38308
32007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.3830832007
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1461953496
Short name T342
Test name
Test status
Simulation time 142009515 ps
CPU time 0.83 seconds
Started Jul 27 07:37:49 PM PDT 24
Finished Jul 27 07:37:50 PM PDT 24
Peak memory 207136 kb
Host smart-7e8c9c00-80c5-4d0f-a68d-b4204290f2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14619
53496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1461953496
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2208672185
Short name T2600
Test name
Test status
Simulation time 151228672 ps
CPU time 0.85 seconds
Started Jul 27 07:37:51 PM PDT 24
Finished Jul 27 07:37:52 PM PDT 24
Peak memory 207100 kb
Host smart-8b7c6ab2-170a-44df-a4e4-ebc4c4f76981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22086
72185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2208672185
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2482424292
Short name T1762
Test name
Test status
Simulation time 153319672 ps
CPU time 0.85 seconds
Started Jul 27 07:37:47 PM PDT 24
Finished Jul 27 07:37:48 PM PDT 24
Peak memory 207104 kb
Host smart-4adaa906-89fe-4f22-ad2d-9762b4809ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24824
24292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2482424292
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3979651982
Short name T1667
Test name
Test status
Simulation time 227883016 ps
CPU time 0.98 seconds
Started Jul 27 07:37:49 PM PDT 24
Finished Jul 27 07:37:50 PM PDT 24
Peak memory 207096 kb
Host smart-32f591ea-466b-4fbc-b7fe-9f5c6f25ba4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39796
51982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3979651982
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.167929708
Short name T732
Test name
Test status
Simulation time 4011189962 ps
CPU time 113.55 seconds
Started Jul 27 07:37:50 PM PDT 24
Finished Jul 27 07:39:44 PM PDT 24
Peak memory 215560 kb
Host smart-345ca5fb-7fe9-49e0-8c35-cfa2e53149ba
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=167929708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.167929708
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2281249481
Short name T551
Test name
Test status
Simulation time 164992469 ps
CPU time 0.87 seconds
Started Jul 27 07:37:50 PM PDT 24
Finished Jul 27 07:37:51 PM PDT 24
Peak memory 207108 kb
Host smart-6d81e822-4747-4ab6-9e29-68c0aacb87b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22812
49481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2281249481
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2328730836
Short name T2537
Test name
Test status
Simulation time 181334309 ps
CPU time 0.9 seconds
Started Jul 27 07:37:50 PM PDT 24
Finished Jul 27 07:37:51 PM PDT 24
Peak memory 207096 kb
Host smart-6728f65e-55cd-4848-bc42-213e1000f1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23287
30836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2328730836
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.2292436555
Short name T2582
Test name
Test status
Simulation time 865593023 ps
CPU time 2.22 seconds
Started Jul 27 07:37:55 PM PDT 24
Finished Jul 27 07:37:57 PM PDT 24
Peak memory 207336 kb
Host smart-980e9f01-4d04-4866-a8c2-e2a50a61f03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22924
36555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.2292436555
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.3437798720
Short name T1784
Test name
Test status
Simulation time 4714897053 ps
CPU time 135.55 seconds
Started Jul 27 07:37:54 PM PDT 24
Finished Jul 27 07:40:10 PM PDT 24
Peak memory 215608 kb
Host smart-b4574653-31c2-491c-bd4b-c3f4751c64d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34377
98720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.3437798720
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.1298500059
Short name T2754
Test name
Test status
Simulation time 4952774183 ps
CPU time 34.19 seconds
Started Jul 27 07:37:41 PM PDT 24
Finished Jul 27 07:38:15 PM PDT 24
Peak memory 207388 kb
Host smart-e7170dcf-3416-4b4e-a628-fba19db8ef74
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298500059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_hos
t_handshake.1298500059
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.2432014897
Short name T645
Test name
Test status
Simulation time 40794918 ps
CPU time 0.71 seconds
Started Jul 27 07:38:08 PM PDT 24
Finished Jul 27 07:38:09 PM PDT 24
Peak memory 207180 kb
Host smart-977cb7f6-e687-4dbd-b545-78a5c90f2f78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2432014897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.2432014897
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.1190992271
Short name T2561
Test name
Test status
Simulation time 4409004633 ps
CPU time 6.11 seconds
Started Jul 27 07:37:54 PM PDT 24
Finished Jul 27 07:38:01 PM PDT 24
Peak memory 207328 kb
Host smart-0257657a-154a-4f20-a433-5a4cf92b4b14
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190992271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_disconnect.1190992271
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2135075770
Short name T2285
Test name
Test status
Simulation time 13326879328 ps
CPU time 19.23 seconds
Started Jul 27 07:38:02 PM PDT 24
Finished Jul 27 07:38:21 PM PDT 24
Peak memory 207412 kb
Host smart-2b1b62ee-a795-4818-bff3-5e8cc62f2e48
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135075770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2135075770
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.4054682690
Short name T2223
Test name
Test status
Simulation time 23423670283 ps
CPU time 31.18 seconds
Started Jul 27 07:37:58 PM PDT 24
Finished Jul 27 07:38:29 PM PDT 24
Peak memory 207328 kb
Host smart-9fdd01a5-1f22-4d91-a9ea-56c70aec6ece
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054682690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.4054682690
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.33229140
Short name T1101
Test name
Test status
Simulation time 156070729 ps
CPU time 0.88 seconds
Started Jul 27 07:37:54 PM PDT 24
Finished Jul 27 07:37:55 PM PDT 24
Peak memory 207100 kb
Host smart-f3c2c78f-8f42-4427-b753-13df65b6bf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33229
140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.33229140
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3971271680
Short name T1047
Test name
Test status
Simulation time 143033666 ps
CPU time 0.87 seconds
Started Jul 27 07:37:55 PM PDT 24
Finished Jul 27 07:37:56 PM PDT 24
Peak memory 207060 kb
Host smart-72b1dfed-5157-4a1e-ae0e-41b6aceff798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39712
71680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3971271680
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.227365703
Short name T2065
Test name
Test status
Simulation time 395070605 ps
CPU time 1.4 seconds
Started Jul 27 07:37:58 PM PDT 24
Finished Jul 27 07:37:59 PM PDT 24
Peak memory 207068 kb
Host smart-868b89a8-0dcc-4fa4-b410-1bc998b05dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22736
5703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.227365703
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.604360780
Short name T1507
Test name
Test status
Simulation time 347699831 ps
CPU time 1.09 seconds
Started Jul 27 07:37:54 PM PDT 24
Finished Jul 27 07:37:55 PM PDT 24
Peak memory 207168 kb
Host smart-230c1650-8fbf-44e4-9a23-fae84c516a20
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=604360780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.604360780
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.153274118
Short name T1203
Test name
Test status
Simulation time 5692635366 ps
CPU time 37.32 seconds
Started Jul 27 07:37:55 PM PDT 24
Finished Jul 27 07:38:33 PM PDT 24
Peak memory 207396 kb
Host smart-55b75e2b-ace1-4f56-85ca-50dbd5ba332f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153274118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.153274118
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.422557920
Short name T166
Test name
Test status
Simulation time 379709519 ps
CPU time 1.34 seconds
Started Jul 27 07:37:53 PM PDT 24
Finished Jul 27 07:37:54 PM PDT 24
Peak memory 207108 kb
Host smart-a9980cd6-f3a5-40d8-84a7-4dfcf98625c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42255
7920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.422557920
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3418855023
Short name T554
Test name
Test status
Simulation time 184141123 ps
CPU time 0.86 seconds
Started Jul 27 07:37:55 PM PDT 24
Finished Jul 27 07:37:56 PM PDT 24
Peak memory 207092 kb
Host smart-2a1e1985-212c-4cee-a3a6-035268a1e8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34188
55023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3418855023
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.923245403
Short name T912
Test name
Test status
Simulation time 34474484 ps
CPU time 0.73 seconds
Started Jul 27 07:38:02 PM PDT 24
Finished Jul 27 07:38:03 PM PDT 24
Peak memory 207108 kb
Host smart-076c2abb-2bac-4214-8472-870ebba54c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92324
5403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.923245403
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.1693334015
Short name T1014
Test name
Test status
Simulation time 890456148 ps
CPU time 2.55 seconds
Started Jul 27 07:37:52 PM PDT 24
Finished Jul 27 07:37:55 PM PDT 24
Peak memory 207192 kb
Host smart-336f1a94-acd7-4ee3-8bcf-23eca1b33ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16933
34015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.1693334015
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1545533134
Short name T1065
Test name
Test status
Simulation time 195238325 ps
CPU time 1.96 seconds
Started Jul 27 07:37:52 PM PDT 24
Finished Jul 27 07:37:54 PM PDT 24
Peak memory 207268 kb
Host smart-3578b462-76d4-49d3-b08a-33a7cc727ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15455
33134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1545533134
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.1802434518
Short name T2132
Test name
Test status
Simulation time 162623537 ps
CPU time 0.95 seconds
Started Jul 27 07:38:02 PM PDT 24
Finished Jul 27 07:38:03 PM PDT 24
Peak memory 207152 kb
Host smart-90a90d3e-ff83-45c8-a7be-9f36817af009
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1802434518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.1802434518
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3723767222
Short name T2134
Test name
Test status
Simulation time 148319657 ps
CPU time 0.87 seconds
Started Jul 27 07:37:53 PM PDT 24
Finished Jul 27 07:37:53 PM PDT 24
Peak memory 207104 kb
Host smart-9f839c21-e29a-49b1-bae0-a339781b4f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37237
67222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3723767222
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3261972492
Short name T2610
Test name
Test status
Simulation time 223177271 ps
CPU time 1.05 seconds
Started Jul 27 07:37:56 PM PDT 24
Finished Jul 27 07:37:57 PM PDT 24
Peak memory 207112 kb
Host smart-26f8c992-818c-4043-87d0-4c4d77558845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32619
72492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3261972492
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.3288128412
Short name T1003
Test name
Test status
Simulation time 9188302780 ps
CPU time 270.73 seconds
Started Jul 27 07:37:55 PM PDT 24
Finished Jul 27 07:42:25 PM PDT 24
Peak memory 215612 kb
Host smart-fa07d66f-365c-476b-84b3-08114d9f990d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3288128412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.3288128412
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.4113815939
Short name T1849
Test name
Test status
Simulation time 10047143029 ps
CPU time 70.04 seconds
Started Jul 27 07:37:52 PM PDT 24
Finished Jul 27 07:39:02 PM PDT 24
Peak memory 207360 kb
Host smart-3497d19d-c3b4-4a30-a85b-e0680caa3271
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4113815939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.4113815939
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2463605517
Short name T1470
Test name
Test status
Simulation time 159653842 ps
CPU time 0.89 seconds
Started Jul 27 07:37:53 PM PDT 24
Finished Jul 27 07:37:54 PM PDT 24
Peak memory 207100 kb
Host smart-14e882c2-9628-4316-894c-dd1f81ee9a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24636
05517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2463605517
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.79179711
Short name T1056
Test name
Test status
Simulation time 23324697437 ps
CPU time 29.68 seconds
Started Jul 27 07:38:02 PM PDT 24
Finished Jul 27 07:38:32 PM PDT 24
Peak memory 207308 kb
Host smart-c97ffbdd-50cb-4a48-a069-10a3f1b838e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79179
711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.79179711
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3690926303
Short name T1738
Test name
Test status
Simulation time 3305414737 ps
CPU time 4.88 seconds
Started Jul 27 07:37:53 PM PDT 24
Finished Jul 27 07:37:58 PM PDT 24
Peak memory 207380 kb
Host smart-8b68e2f4-b40f-4d98-bafa-8794a94d1a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36909
26303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3690926303
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.1353541763
Short name T509
Test name
Test status
Simulation time 4523818339 ps
CPU time 32.78 seconds
Started Jul 27 07:37:53 PM PDT 24
Finished Jul 27 07:38:26 PM PDT 24
Peak memory 218244 kb
Host smart-415a2b78-576a-41cb-97c8-3c6419770ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13535
41763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.1353541763
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.3209939320
Short name T539
Test name
Test status
Simulation time 3506669088 ps
CPU time 101.9 seconds
Started Jul 27 07:37:56 PM PDT 24
Finished Jul 27 07:39:37 PM PDT 24
Peak memory 215608 kb
Host smart-d4f90adf-5ff1-480b-8965-e6f99e1f1bda
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3209939320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.3209939320
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.173257945
Short name T1504
Test name
Test status
Simulation time 260746595 ps
CPU time 1.04 seconds
Started Jul 27 07:37:59 PM PDT 24
Finished Jul 27 07:38:00 PM PDT 24
Peak memory 207144 kb
Host smart-0c173cb1-de3e-4240-92df-e16ef953b5ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=173257945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.173257945
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.874024344
Short name T2270
Test name
Test status
Simulation time 200490680 ps
CPU time 0.96 seconds
Started Jul 27 07:38:00 PM PDT 24
Finished Jul 27 07:38:01 PM PDT 24
Peak memory 207168 kb
Host smart-db6d1674-0fa6-412c-900e-2c1136b0017c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87402
4344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.874024344
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.4184613829
Short name T1036
Test name
Test status
Simulation time 5724613484 ps
CPU time 168.73 seconds
Started Jul 27 07:37:55 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 215544 kb
Host smart-dd6cad01-bf73-46e3-8161-2ba9a5e9256b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41846
13829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.4184613829
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.405925313
Short name T2752
Test name
Test status
Simulation time 3409551557 ps
CPU time 92.23 seconds
Started Jul 27 07:38:11 PM PDT 24
Finished Jul 27 07:39:43 PM PDT 24
Peak memory 215620 kb
Host smart-37fbe4ad-50cb-4985-bc95-ae19d12510b0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=405925313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.405925313
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.1348944638
Short name T1252
Test name
Test status
Simulation time 151844781 ps
CPU time 0.82 seconds
Started Jul 27 07:38:10 PM PDT 24
Finished Jul 27 07:38:11 PM PDT 24
Peak memory 207136 kb
Host smart-6fa3f6e4-3cf1-48fe-a1e4-ff006333b861
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1348944638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.1348944638
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3062077090
Short name T1850
Test name
Test status
Simulation time 188388087 ps
CPU time 0.91 seconds
Started Jul 27 07:38:03 PM PDT 24
Finished Jul 27 07:38:04 PM PDT 24
Peak memory 207168 kb
Host smart-eb7de82d-4924-408d-a3fd-a6a9c4674beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30620
77090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3062077090
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.380483577
Short name T857
Test name
Test status
Simulation time 197096303 ps
CPU time 0.99 seconds
Started Jul 27 07:38:02 PM PDT 24
Finished Jul 27 07:38:03 PM PDT 24
Peak memory 207144 kb
Host smart-d105c4ac-9025-488e-a5cc-f22800ee6d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38048
3577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.380483577
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.4063525372
Short name T2662
Test name
Test status
Simulation time 151668634 ps
CPU time 0.88 seconds
Started Jul 27 07:37:58 PM PDT 24
Finished Jul 27 07:37:59 PM PDT 24
Peak memory 207220 kb
Host smart-013ac55b-8eb6-4895-a071-ab48d8b0ee2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40635
25372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.4063525372
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2421152309
Short name T1900
Test name
Test status
Simulation time 169542037 ps
CPU time 0.82 seconds
Started Jul 27 07:37:59 PM PDT 24
Finished Jul 27 07:37:59 PM PDT 24
Peak memory 207108 kb
Host smart-7ead14c4-129e-4b2a-8be8-57f89e13f477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24211
52309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2421152309
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1813247739
Short name T1862
Test name
Test status
Simulation time 150741194 ps
CPU time 0.85 seconds
Started Jul 27 07:38:00 PM PDT 24
Finished Jul 27 07:38:01 PM PDT 24
Peak memory 207064 kb
Host smart-ee4b7433-1c27-496f-9291-ee603d5a79f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18132
47739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1813247739
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.3823854789
Short name T1380
Test name
Test status
Simulation time 235796470 ps
CPU time 1.02 seconds
Started Jul 27 07:38:00 PM PDT 24
Finished Jul 27 07:38:02 PM PDT 24
Peak memory 207220 kb
Host smart-58fe4d1d-4094-4622-8828-3df569f38ef4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3823854789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.3823854789
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.2537862974
Short name T1197
Test name
Test status
Simulation time 151841362 ps
CPU time 0.85 seconds
Started Jul 27 07:38:00 PM PDT 24
Finished Jul 27 07:38:01 PM PDT 24
Peak memory 207056 kb
Host smart-8c4d9eff-8196-47df-baf5-32e1641c96b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25378
62974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.2537862974
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.4158790530
Short name T1484
Test name
Test status
Simulation time 95218687 ps
CPU time 0.74 seconds
Started Jul 27 07:38:02 PM PDT 24
Finished Jul 27 07:38:03 PM PDT 24
Peak memory 207112 kb
Host smart-ddca90ca-08e4-479d-9e19-96077c932439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41587
90530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.4158790530
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1871040210
Short name T1880
Test name
Test status
Simulation time 6647587219 ps
CPU time 17.31 seconds
Started Jul 27 07:38:00 PM PDT 24
Finished Jul 27 07:38:18 PM PDT 24
Peak memory 215572 kb
Host smart-4ed2efd7-1e31-443c-91d7-11b77bc13342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18710
40210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1871040210
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.945628715
Short name T2086
Test name
Test status
Simulation time 178039797 ps
CPU time 0.92 seconds
Started Jul 27 07:38:00 PM PDT 24
Finished Jul 27 07:38:01 PM PDT 24
Peak memory 207088 kb
Host smart-8e3532fd-1907-48cb-8c67-7b6e7a69cd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94562
8715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.945628715
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.4208290477
Short name T2388
Test name
Test status
Simulation time 211443303 ps
CPU time 1 seconds
Started Jul 27 07:38:03 PM PDT 24
Finished Jul 27 07:38:04 PM PDT 24
Peak memory 207064 kb
Host smart-7cb928ab-46a6-4b17-b9ec-d667d740315b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42082
90477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.4208290477
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3241889648
Short name T1207
Test name
Test status
Simulation time 173540499 ps
CPU time 0.89 seconds
Started Jul 27 07:38:11 PM PDT 24
Finished Jul 27 07:38:12 PM PDT 24
Peak memory 207124 kb
Host smart-c0e5e18c-4594-4f70-b5ff-a6e38d801247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32418
89648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3241889648
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.1235344585
Short name T97
Test name
Test status
Simulation time 155846274 ps
CPU time 0.86 seconds
Started Jul 27 07:38:11 PM PDT 24
Finished Jul 27 07:38:12 PM PDT 24
Peak memory 207128 kb
Host smart-ccea71b9-e96a-4840-8a84-f5c6599ccb45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12353
44585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.1235344585
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1799283591
Short name T1676
Test name
Test status
Simulation time 171527468 ps
CPU time 0.87 seconds
Started Jul 27 07:37:59 PM PDT 24
Finished Jul 27 07:38:00 PM PDT 24
Peak memory 207104 kb
Host smart-d147517a-8bb3-4444-b517-8435c2e79c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17992
83591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1799283591
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.293813230
Short name T1148
Test name
Test status
Simulation time 203414745 ps
CPU time 0.87 seconds
Started Jul 27 07:37:59 PM PDT 24
Finished Jul 27 07:38:00 PM PDT 24
Peak memory 207060 kb
Host smart-0f5af193-5914-4d7e-afac-0b8bcc57d7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29381
3230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.293813230
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1427757771
Short name T403
Test name
Test status
Simulation time 214897655 ps
CPU time 1 seconds
Started Jul 27 07:38:11 PM PDT 24
Finished Jul 27 07:38:13 PM PDT 24
Peak memory 207120 kb
Host smart-00f3ea82-044a-4d0b-acff-e9ac9a24621d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14277
57771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1427757771
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3172507911
Short name T1156
Test name
Test status
Simulation time 5512304356 ps
CPU time 42.23 seconds
Started Jul 27 07:38:03 PM PDT 24
Finished Jul 27 07:38:45 PM PDT 24
Peak memory 215612 kb
Host smart-ab1f56f5-1d27-489a-9ced-f71aca2ebd40
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3172507911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3172507911
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2581874595
Short name T1216
Test name
Test status
Simulation time 203819597 ps
CPU time 0.99 seconds
Started Jul 27 07:38:11 PM PDT 24
Finished Jul 27 07:38:12 PM PDT 24
Peak memory 207144 kb
Host smart-cd9adf71-7a22-44b7-ba18-d751b2dada9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25818
74595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2581874595
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1965292558
Short name T667
Test name
Test status
Simulation time 158411983 ps
CPU time 0.83 seconds
Started Jul 27 07:37:59 PM PDT 24
Finished Jul 27 07:38:00 PM PDT 24
Peak memory 207068 kb
Host smart-bf5418f0-2674-4df6-8aeb-71d083aeed96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19652
92558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1965292558
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.3266718069
Short name T1914
Test name
Test status
Simulation time 612419646 ps
CPU time 1.7 seconds
Started Jul 27 07:38:10 PM PDT 24
Finished Jul 27 07:38:12 PM PDT 24
Peak memory 207096 kb
Host smart-caa0a2b6-eb4a-4d5d-8041-236a75fe9af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32667
18069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.3266718069
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.4169350673
Short name T2347
Test name
Test status
Simulation time 3998978710 ps
CPU time 31.44 seconds
Started Jul 27 07:38:03 PM PDT 24
Finished Jul 27 07:38:35 PM PDT 24
Peak memory 217088 kb
Host smart-cf03f557-d521-49b9-9458-740e79308f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41693
50673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.4169350673
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.298435053
Short name T359
Test name
Test status
Simulation time 4287669999 ps
CPU time 26.46 seconds
Started Jul 27 07:37:58 PM PDT 24
Finished Jul 27 07:38:24 PM PDT 24
Peak memory 207372 kb
Host smart-855c0be2-d611-4f03-9ee9-746c7b91b43d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298435053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_host
_handshake.298435053
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.3099823984
Short name T1264
Test name
Test status
Simulation time 62549437 ps
CPU time 0.68 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:38:15 PM PDT 24
Peak memory 207108 kb
Host smart-9c903d46-af61-4926-afdf-7bd41b893ecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3099823984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.3099823984
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.528901275
Short name T2436
Test name
Test status
Simulation time 3978873068 ps
CPU time 5.92 seconds
Started Jul 27 07:38:06 PM PDT 24
Finished Jul 27 07:38:12 PM PDT 24
Peak memory 207328 kb
Host smart-c8833bb5-88a6-415e-bebc-66cd39aa6449
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528901275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ao
n_wake_disconnect.528901275
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.2333074427
Short name T825
Test name
Test status
Simulation time 13454974518 ps
CPU time 15.8 seconds
Started Jul 27 07:38:05 PM PDT 24
Finished Jul 27 07:38:21 PM PDT 24
Peak memory 207400 kb
Host smart-d33e2d47-2de6-417c-9442-c0d6778a72d6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333074427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.2333074427
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.177148829
Short name T1695
Test name
Test status
Simulation time 23343608567 ps
CPU time 31.05 seconds
Started Jul 27 07:38:06 PM PDT 24
Finished Jul 27 07:38:37 PM PDT 24
Peak memory 207300 kb
Host smart-f3934141-0f5b-40af-ae4c-b4675020d5a1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177148829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ao
n_wake_resume.177148829
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3110282124
Short name T2201
Test name
Test status
Simulation time 188279224 ps
CPU time 0.94 seconds
Started Jul 27 07:38:08 PM PDT 24
Finished Jul 27 07:38:09 PM PDT 24
Peak memory 207156 kb
Host smart-3d06abe6-6bb5-41e6-ad50-315d37b5c371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31102
82124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3110282124
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.3882560240
Short name T872
Test name
Test status
Simulation time 180979751 ps
CPU time 0.85 seconds
Started Jul 27 07:38:08 PM PDT 24
Finished Jul 27 07:38:08 PM PDT 24
Peak memory 207064 kb
Host smart-d619b38c-8d6c-4ef3-b4fe-5cb6f7de4253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38825
60240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.3882560240
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.2374040601
Short name T96
Test name
Test status
Simulation time 459360647 ps
CPU time 1.51 seconds
Started Jul 27 07:38:07 PM PDT 24
Finished Jul 27 07:38:09 PM PDT 24
Peak memory 207060 kb
Host smart-6a185f8b-95f5-4e2b-9e64-61430face7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23740
40601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.2374040601
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.81922144
Short name T588
Test name
Test status
Simulation time 1447014733 ps
CPU time 3.38 seconds
Started Jul 27 07:38:07 PM PDT 24
Finished Jul 27 07:38:11 PM PDT 24
Peak memory 207276 kb
Host smart-80f98620-fd59-46ea-aa72-f1f10a090446
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=81922144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.81922144
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.4202344833
Short name T343
Test name
Test status
Simulation time 12968504850 ps
CPU time 28.18 seconds
Started Jul 27 07:38:07 PM PDT 24
Finished Jul 27 07:38:35 PM PDT 24
Peak memory 207352 kb
Host smart-d94bea89-6b00-473a-8983-2182b1560218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42023
44833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.4202344833
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.3039263823
Short name T1551
Test name
Test status
Simulation time 156155723 ps
CPU time 0.93 seconds
Started Jul 27 07:38:06 PM PDT 24
Finished Jul 27 07:38:07 PM PDT 24
Peak memory 207132 kb
Host smart-e0f8f7f1-4b6f-41b6-9ba7-97a2149a09a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039263823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.3039263823
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.2473756878
Short name T1587
Test name
Test status
Simulation time 551214201 ps
CPU time 1.62 seconds
Started Jul 27 07:38:08 PM PDT 24
Finished Jul 27 07:38:10 PM PDT 24
Peak memory 207056 kb
Host smart-e3361493-16f7-4e87-bf52-dd0f0f268b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24737
56878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.2473756878
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.842465206
Short name T932
Test name
Test status
Simulation time 159599776 ps
CPU time 0.84 seconds
Started Jul 27 07:38:07 PM PDT 24
Finished Jul 27 07:38:08 PM PDT 24
Peak memory 207064 kb
Host smart-ad3ca796-4b97-4e8e-ab10-27214fee7272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84246
5206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.842465206
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.3506350506
Short name T2762
Test name
Test status
Simulation time 44316013 ps
CPU time 0.71 seconds
Started Jul 27 07:38:06 PM PDT 24
Finished Jul 27 07:38:07 PM PDT 24
Peak memory 207296 kb
Host smart-3e442614-a983-494e-ab78-2947023c5516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35063
50506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3506350506
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.702511281
Short name T459
Test name
Test status
Simulation time 840780542 ps
CPU time 2.19 seconds
Started Jul 27 07:38:06 PM PDT 24
Finished Jul 27 07:38:08 PM PDT 24
Peak memory 207324 kb
Host smart-a54fc0aa-c3c1-49ab-b516-5e1b9e9df15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70251
1281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.702511281
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.49248339
Short name T2120
Test name
Test status
Simulation time 206913742 ps
CPU time 2.53 seconds
Started Jul 27 07:38:05 PM PDT 24
Finished Jul 27 07:38:07 PM PDT 24
Peak memory 207292 kb
Host smart-f2db9c99-f759-4c25-b53a-7c99c96dab3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49248
339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.49248339
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1435769812
Short name T560
Test name
Test status
Simulation time 233283213 ps
CPU time 1.15 seconds
Started Jul 27 07:38:05 PM PDT 24
Finished Jul 27 07:38:06 PM PDT 24
Peak memory 215508 kb
Host smart-f9bc3071-7809-4671-a419-205c6c3baa64
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1435769812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1435769812
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.4292969129
Short name T778
Test name
Test status
Simulation time 145510134 ps
CPU time 0.85 seconds
Started Jul 27 07:38:07 PM PDT 24
Finished Jul 27 07:38:08 PM PDT 24
Peak memory 207032 kb
Host smart-58058a5e-09c8-4bbb-bf4a-eb520b0bfe3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42929
69129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.4292969129
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1001016619
Short name T2749
Test name
Test status
Simulation time 273075963 ps
CPU time 1.03 seconds
Started Jul 27 07:38:04 PM PDT 24
Finished Jul 27 07:38:05 PM PDT 24
Peak memory 207104 kb
Host smart-6fd8c2f3-1f9f-4530-b453-14baccf5a211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10010
16619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1001016619
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.1033643887
Short name T2798
Test name
Test status
Simulation time 10051062719 ps
CPU time 75.29 seconds
Started Jul 27 07:38:09 PM PDT 24
Finished Jul 27 07:39:24 PM PDT 24
Peak memory 216716 kb
Host smart-70eccbfc-e3d1-41c9-9531-98d84aa0c3e6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1033643887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.1033643887
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.3347413153
Short name T2255
Test name
Test status
Simulation time 9150032672 ps
CPU time 61.11 seconds
Started Jul 27 07:38:09 PM PDT 24
Finished Jul 27 07:39:10 PM PDT 24
Peak memory 207316 kb
Host smart-a93f9313-e2ec-40f0-b183-88dc805ec872
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3347413153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.3347413153
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.2515767723
Short name T1679
Test name
Test status
Simulation time 219335858 ps
CPU time 0.92 seconds
Started Jul 27 07:38:04 PM PDT 24
Finished Jul 27 07:38:05 PM PDT 24
Peak memory 207120 kb
Host smart-65d011dd-ad59-412a-bc7e-041942a99fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25157
67723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.2515767723
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.1398490241
Short name T2039
Test name
Test status
Simulation time 23328600654 ps
CPU time 28.35 seconds
Started Jul 27 07:38:06 PM PDT 24
Finished Jul 27 07:38:34 PM PDT 24
Peak memory 207372 kb
Host smart-d2fa35b5-5b38-4ed4-859c-5e596ef447f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13984
90241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.1398490241
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.724428228
Short name T2296
Test name
Test status
Simulation time 3306190349 ps
CPU time 5.1 seconds
Started Jul 27 07:38:06 PM PDT 24
Finished Jul 27 07:38:11 PM PDT 24
Peak memory 207372 kb
Host smart-fe3bf766-dfde-4fc6-ade0-b6468173ee45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72442
8228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.724428228
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.823833714
Short name T2831
Test name
Test status
Simulation time 7506823919 ps
CPU time 210.84 seconds
Started Jul 27 07:38:04 PM PDT 24
Finished Jul 27 07:41:35 PM PDT 24
Peak memory 215552 kb
Host smart-7a004ead-f4b2-4db1-b204-3b1b73964454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82383
3714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.823833714
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.77168684
Short name T2304
Test name
Test status
Simulation time 7781561108 ps
CPU time 222.6 seconds
Started Jul 27 07:38:07 PM PDT 24
Finished Jul 27 07:41:49 PM PDT 24
Peak memory 215628 kb
Host smart-87ff50c3-31c7-4e56-b16b-a5d97e4bc963
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=77168684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.77168684
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.2189151311
Short name T390
Test name
Test status
Simulation time 266010134 ps
CPU time 1.02 seconds
Started Jul 27 07:38:07 PM PDT 24
Finished Jul 27 07:38:08 PM PDT 24
Peak memory 207084 kb
Host smart-5f521709-ca79-4eb1-8f54-43fe973132ea
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2189151311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.2189151311
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2184304385
Short name T425
Test name
Test status
Simulation time 193205435 ps
CPU time 0.93 seconds
Started Jul 27 07:38:07 PM PDT 24
Finished Jul 27 07:38:08 PM PDT 24
Peak memory 207120 kb
Host smart-41741432-facf-4763-97a4-c6c14d23e271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21843
04385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2184304385
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2593453121
Short name T574
Test name
Test status
Simulation time 6681757687 ps
CPU time 200.76 seconds
Started Jul 27 07:38:07 PM PDT 24
Finished Jul 27 07:41:28 PM PDT 24
Peak memory 215580 kb
Host smart-3fbbc0b2-f8fc-4126-9ac1-6a4511a0e6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25934
53121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2593453121
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1845788496
Short name T2613
Test name
Test status
Simulation time 7857503469 ps
CPU time 223.94 seconds
Started Jul 27 07:38:07 PM PDT 24
Finished Jul 27 07:41:52 PM PDT 24
Peak memory 215532 kb
Host smart-e40f7bd0-4d79-4955-8da4-e92bbaad1697
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1845788496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1845788496
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.266372181
Short name T1617
Test name
Test status
Simulation time 187598362 ps
CPU time 0.88 seconds
Started Jul 27 07:38:08 PM PDT 24
Finished Jul 27 07:38:09 PM PDT 24
Peak memory 207332 kb
Host smart-b942cb87-0c34-460d-a088-016dff89c237
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=266372181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.266372181
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.890602916
Short name T2386
Test name
Test status
Simulation time 168830658 ps
CPU time 0.91 seconds
Started Jul 27 07:38:08 PM PDT 24
Finished Jul 27 07:38:09 PM PDT 24
Peak memory 207160 kb
Host smart-f80f4684-332d-44f0-9598-1859aea139f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89060
2916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.890602916
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.465871822
Short name T1969
Test name
Test status
Simulation time 193584602 ps
CPU time 0.94 seconds
Started Jul 27 07:38:05 PM PDT 24
Finished Jul 27 07:38:06 PM PDT 24
Peak memory 207120 kb
Host smart-67277de3-2c5a-4d74-946c-c478617a2c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46587
1822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.465871822
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.256282446
Short name T1979
Test name
Test status
Simulation time 188969831 ps
CPU time 0.93 seconds
Started Jul 27 07:38:09 PM PDT 24
Finished Jul 27 07:38:10 PM PDT 24
Peak memory 207260 kb
Host smart-95d5e4b3-9043-493a-af54-34b8f26a9008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25628
2446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.256282446
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2737644481
Short name T418
Test name
Test status
Simulation time 170235723 ps
CPU time 0.84 seconds
Started Jul 27 07:38:10 PM PDT 24
Finished Jul 27 07:38:11 PM PDT 24
Peak memory 207096 kb
Host smart-892fe9a8-82bc-4824-b0e4-cd7ed31fe850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27376
44481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2737644481
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.833469699
Short name T1354
Test name
Test status
Simulation time 200136617 ps
CPU time 0.94 seconds
Started Jul 27 07:38:07 PM PDT 24
Finished Jul 27 07:38:08 PM PDT 24
Peak memory 207088 kb
Host smart-f71adad3-8fe4-45ee-aab7-69d6db846e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83346
9699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.833469699
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3654080774
Short name T1789
Test name
Test status
Simulation time 154574592 ps
CPU time 0.88 seconds
Started Jul 27 07:38:06 PM PDT 24
Finished Jul 27 07:38:07 PM PDT 24
Peak memory 207064 kb
Host smart-25202ce8-3a75-467b-97cc-850671e47023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36540
80774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3654080774
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.2697462515
Short name T328
Test name
Test status
Simulation time 210603152 ps
CPU time 1.01 seconds
Started Jul 27 07:38:06 PM PDT 24
Finished Jul 27 07:38:07 PM PDT 24
Peak memory 207048 kb
Host smart-4d3696e4-2181-4b1c-9aaa-2b10249abe94
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2697462515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.2697462515
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3934353434
Short name T676
Test name
Test status
Simulation time 154799796 ps
CPU time 0.83 seconds
Started Jul 27 07:38:05 PM PDT 24
Finished Jul 27 07:38:06 PM PDT 24
Peak memory 207164 kb
Host smart-2af1e8f8-4af7-4660-8ecd-16ee127d59fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39343
53434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3934353434
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.45639722
Short name T2515
Test name
Test status
Simulation time 56685417 ps
CPU time 0.73 seconds
Started Jul 27 07:38:06 PM PDT 24
Finished Jul 27 07:38:07 PM PDT 24
Peak memory 207100 kb
Host smart-a0101947-d34a-4829-8b9c-7ce1a77059db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45639
722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.45639722
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.991231348
Short name T256
Test name
Test status
Simulation time 17535623379 ps
CPU time 41.32 seconds
Started Jul 27 07:38:11 PM PDT 24
Finished Jul 27 07:38:53 PM PDT 24
Peak memory 215644 kb
Host smart-088a1544-096f-423c-9458-7dd00678e83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99123
1348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.991231348
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.4089717458
Short name T805
Test name
Test status
Simulation time 209456506 ps
CPU time 0.97 seconds
Started Jul 27 07:38:06 PM PDT 24
Finished Jul 27 07:38:07 PM PDT 24
Peak memory 207032 kb
Host smart-07810f32-ad67-4b29-babf-7a1919d6b9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40897
17458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.4089717458
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1594603846
Short name T357
Test name
Test status
Simulation time 183510429 ps
CPU time 0.91 seconds
Started Jul 27 07:38:13 PM PDT 24
Finished Jul 27 07:38:14 PM PDT 24
Peak memory 207148 kb
Host smart-4e067e44-ba47-46cf-a9d2-c33f82c5241c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15946
03846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1594603846
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.2319105045
Short name T2352
Test name
Test status
Simulation time 195472705 ps
CPU time 0.89 seconds
Started Jul 27 07:38:12 PM PDT 24
Finished Jul 27 07:38:13 PM PDT 24
Peak memory 207072 kb
Host smart-2546571a-6118-4513-8a04-d4d9e42c22f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23191
05045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.2319105045
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.3968837542
Short name T591
Test name
Test status
Simulation time 160793807 ps
CPU time 0.91 seconds
Started Jul 27 07:38:12 PM PDT 24
Finished Jul 27 07:38:13 PM PDT 24
Peak memory 207088 kb
Host smart-2b951b5e-34df-49c7-93de-f46db91a4e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39688
37542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.3968837542
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.460326396
Short name T2104
Test name
Test status
Simulation time 172076296 ps
CPU time 0.84 seconds
Started Jul 27 07:38:13 PM PDT 24
Finished Jul 27 07:38:14 PM PDT 24
Peak memory 207032 kb
Host smart-6e50bfff-c7c6-4c9c-8725-1f5ced40fdcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46032
6396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.460326396
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3422898692
Short name T1685
Test name
Test status
Simulation time 151034842 ps
CPU time 0.87 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:38:15 PM PDT 24
Peak memory 207104 kb
Host smart-13efdb27-8d62-4769-89d3-516bab6e1795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34228
98692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3422898692
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2711534256
Short name T40
Test name
Test status
Simulation time 151271121 ps
CPU time 0.84 seconds
Started Jul 27 07:38:12 PM PDT 24
Finished Jul 27 07:38:13 PM PDT 24
Peak memory 207120 kb
Host smart-f2bab026-24a0-4e5f-949e-f9eb987daad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27115
34256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2711534256
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3553093356
Short name T1846
Test name
Test status
Simulation time 216262920 ps
CPU time 0.96 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:38:15 PM PDT 24
Peak memory 207108 kb
Host smart-9f16247d-85e0-4d1b-9b5b-1e90bfc37df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35530
93356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3553093356
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3150299182
Short name T982
Test name
Test status
Simulation time 5929700879 ps
CPU time 47.22 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:39:01 PM PDT 24
Peak memory 216892 kb
Host smart-bf157834-1f00-4aa6-82ea-c9d75cb49dd1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3150299182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3150299182
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1094229626
Short name T1937
Test name
Test status
Simulation time 166060897 ps
CPU time 0.9 seconds
Started Jul 27 07:38:11 PM PDT 24
Finished Jul 27 07:38:12 PM PDT 24
Peak memory 207116 kb
Host smart-0a703b04-889f-44cc-9bc6-b0be3bfffc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10942
29626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1094229626
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.4264273311
Short name T856
Test name
Test status
Simulation time 179893388 ps
CPU time 0.87 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:38:15 PM PDT 24
Peak memory 207088 kb
Host smart-5a655710-3f9b-4d24-9eb2-b517e83f0745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42642
73311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.4264273311
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.1910752883
Short name T1547
Test name
Test status
Simulation time 1201524179 ps
CPU time 2.83 seconds
Started Jul 27 07:38:12 PM PDT 24
Finished Jul 27 07:38:15 PM PDT 24
Peak memory 207308 kb
Host smart-5e83e916-31e3-4570-bdc1-567d36d8859e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19107
52883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.1910752883
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1734857843
Short name T2781
Test name
Test status
Simulation time 4393771582 ps
CPU time 128.16 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:40:23 PM PDT 24
Peak memory 215492 kb
Host smart-6ed1536e-9f93-4a61-b958-5cde55955deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17348
57843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1734857843
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.553677630
Short name T1076
Test name
Test status
Simulation time 1009143715 ps
CPU time 23.77 seconds
Started Jul 27 07:38:04 PM PDT 24
Finished Jul 27 07:38:28 PM PDT 24
Peak memory 207312 kb
Host smart-89e6738f-d935-4b38-95fc-bd3ac9b90a85
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553677630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_host
_handshake.553677630
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.211429275
Short name T2368
Test name
Test status
Simulation time 43133543 ps
CPU time 0.66 seconds
Started Jul 27 07:34:05 PM PDT 24
Finished Jul 27 07:34:06 PM PDT 24
Peak memory 207180 kb
Host smart-c4597ded-4a72-4573-b401-01bf7f222756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=211429275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.211429275
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1566815053
Short name T441
Test name
Test status
Simulation time 3612934833 ps
CPU time 5.67 seconds
Started Jul 27 07:33:44 PM PDT 24
Finished Jul 27 07:33:50 PM PDT 24
Peak memory 207380 kb
Host smart-a0ce1c73-e218-46f8-b90e-5398609dea4e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566815053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.1566815053
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1513972130
Short name T818
Test name
Test status
Simulation time 13342734024 ps
CPU time 15.8 seconds
Started Jul 27 07:33:44 PM PDT 24
Finished Jul 27 07:34:00 PM PDT 24
Peak memory 207404 kb
Host smart-f7eafd29-0293-4115-ad0d-118d40905595
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513972130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1513972130
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.2690980764
Short name T1283
Test name
Test status
Simulation time 23402567001 ps
CPU time 28.61 seconds
Started Jul 27 07:33:45 PM PDT 24
Finished Jul 27 07:34:14 PM PDT 24
Peak memory 207264 kb
Host smart-2923863b-14c6-4a93-9a5e-b9ff701724ed
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690980764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.2690980764
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1314976147
Short name T385
Test name
Test status
Simulation time 164720742 ps
CPU time 0.88 seconds
Started Jul 27 07:33:44 PM PDT 24
Finished Jul 27 07:33:45 PM PDT 24
Peak memory 207084 kb
Host smart-e4fb0ff8-4c4b-4001-abc9-80bbc13094d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13149
76147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1314976147
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2476869344
Short name T104
Test name
Test status
Simulation time 204469095 ps
CPU time 0.95 seconds
Started Jul 27 07:33:44 PM PDT 24
Finished Jul 27 07:33:45 PM PDT 24
Peak memory 207036 kb
Host smart-9b4e068d-6d76-47a9-8506-7b195df858c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24768
69344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2476869344
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.4115768898
Short name T704
Test name
Test status
Simulation time 149296005 ps
CPU time 0.84 seconds
Started Jul 27 07:33:44 PM PDT 24
Finished Jul 27 07:33:45 PM PDT 24
Peak memory 207056 kb
Host smart-a08f158f-1416-4326-9c74-967614b7582e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41157
68898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.4115768898
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.573768700
Short name T2489
Test name
Test status
Simulation time 329837732 ps
CPU time 1.33 seconds
Started Jul 27 07:33:47 PM PDT 24
Finished Jul 27 07:33:48 PM PDT 24
Peak memory 207144 kb
Host smart-e182207c-3ed9-403d-9d65-98628a1a452e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57376
8700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.573768700
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.1647552583
Short name T1338
Test name
Test status
Simulation time 660940702 ps
CPU time 1.99 seconds
Started Jul 27 07:33:44 PM PDT 24
Finished Jul 27 07:33:46 PM PDT 24
Peak memory 207104 kb
Host smart-dd0158c0-7385-409a-89c0-ca5223581ec4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1647552583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.1647552583
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.2639558992
Short name T1481
Test name
Test status
Simulation time 18178519120 ps
CPU time 40.95 seconds
Started Jul 27 07:33:44 PM PDT 24
Finished Jul 27 07:34:25 PM PDT 24
Peak memory 207360 kb
Host smart-277198ad-f077-40ae-b0c3-5e281a07612c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26395
58992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.2639558992
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.1834199426
Short name T2742
Test name
Test status
Simulation time 4818107381 ps
CPU time 42.15 seconds
Started Jul 27 07:33:43 PM PDT 24
Finished Jul 27 07:34:25 PM PDT 24
Peak memory 207380 kb
Host smart-23abc62e-3d04-4342-9a5f-3c95d509877e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834199426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.1834199426
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.814946186
Short name T2246
Test name
Test status
Simulation time 420427921 ps
CPU time 1.46 seconds
Started Jul 27 07:33:51 PM PDT 24
Finished Jul 27 07:33:53 PM PDT 24
Peak memory 207076 kb
Host smart-96ecfdc0-ac3e-4bfd-8423-696dbb436bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81494
6186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.814946186
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.3841040987
Short name T963
Test name
Test status
Simulation time 163177139 ps
CPU time 0.88 seconds
Started Jul 27 07:33:51 PM PDT 24
Finished Jul 27 07:33:52 PM PDT 24
Peak memory 207108 kb
Host smart-06ca1db9-6e95-445a-a89a-1eec7dd40a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38410
40987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.3841040987
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2215908926
Short name T949
Test name
Test status
Simulation time 57930848 ps
CPU time 0.69 seconds
Started Jul 27 07:33:50 PM PDT 24
Finished Jul 27 07:33:50 PM PDT 24
Peak memory 207072 kb
Host smart-e8dd2278-8cd8-473d-af8b-e7000ca70e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22159
08926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2215908926
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.2769800697
Short name T776
Test name
Test status
Simulation time 991097907 ps
CPU time 2.63 seconds
Started Jul 27 07:33:51 PM PDT 24
Finished Jul 27 07:33:54 PM PDT 24
Peak memory 207364 kb
Host smart-c35f8a76-ee7d-42ef-bf24-45aacd4afc52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27698
00697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2769800697
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.3075289626
Short name T386
Test name
Test status
Simulation time 199143068 ps
CPU time 2.28 seconds
Started Jul 27 07:33:51 PM PDT 24
Finished Jul 27 07:33:53 PM PDT 24
Peak memory 207316 kb
Host smart-99cc2e4a-c9a2-4e16-bd46-61b6553d6a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30752
89626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.3075289626
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.3320926431
Short name T2218
Test name
Test status
Simulation time 106188297825 ps
CPU time 155.3 seconds
Started Jul 27 07:33:53 PM PDT 24
Finished Jul 27 07:36:29 PM PDT 24
Peak memory 207456 kb
Host smart-8e23e9fc-14b9-4919-be5c-1327111bece4
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3320926431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.3320926431
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.4155739810
Short name T1659
Test name
Test status
Simulation time 89273492589 ps
CPU time 154.96 seconds
Started Jul 27 07:33:51 PM PDT 24
Finished Jul 27 07:36:26 PM PDT 24
Peak memory 207344 kb
Host smart-4e23644c-8ff2-4074-a958-692b88241cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155739810 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.4155739810
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.993991127
Short name T1588
Test name
Test status
Simulation time 107122936207 ps
CPU time 176.73 seconds
Started Jul 27 07:33:50 PM PDT 24
Finished Jul 27 07:36:47 PM PDT 24
Peak memory 207372 kb
Host smart-0b137192-8630-4ebf-ba0e-f7d4937501da
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=993991127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.993991127
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.582778662
Short name T307
Test name
Test status
Simulation time 118097913853 ps
CPU time 213.78 seconds
Started Jul 27 07:33:50 PM PDT 24
Finished Jul 27 07:37:24 PM PDT 24
Peak memory 207448 kb
Host smart-0889302f-0e0b-4eb3-a615-f6a72a54b6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582778662 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.582778662
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.859546961
Short name T1235
Test name
Test status
Simulation time 106106505900 ps
CPU time 178.12 seconds
Started Jul 27 07:33:51 PM PDT 24
Finished Jul 27 07:36:49 PM PDT 24
Peak memory 207284 kb
Host smart-28d715b9-d3c8-4731-aeac-416108159221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85954
6961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.859546961
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.540536989
Short name T1947
Test name
Test status
Simulation time 230835917 ps
CPU time 1.2 seconds
Started Jul 27 07:33:50 PM PDT 24
Finished Jul 27 07:33:51 PM PDT 24
Peak memory 215488 kb
Host smart-7f9f2c7d-793a-43d9-b8fe-d83f4fb0fd06
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=540536989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.540536989
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.4138616731
Short name T2321
Test name
Test status
Simulation time 136950534 ps
CPU time 0.78 seconds
Started Jul 27 07:33:50 PM PDT 24
Finished Jul 27 07:33:51 PM PDT 24
Peak memory 207056 kb
Host smart-06dfb894-3831-47f4-923b-c9c2cde7c79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41386
16731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.4138616731
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.4212243916
Short name T1079
Test name
Test status
Simulation time 229544516 ps
CPU time 1.01 seconds
Started Jul 27 07:33:49 PM PDT 24
Finished Jul 27 07:33:51 PM PDT 24
Peak memory 207128 kb
Host smart-a2fb3956-067d-4c5c-9136-57c85ca99290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42122
43916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.4212243916
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.3461014187
Short name T2237
Test name
Test status
Simulation time 10019729253 ps
CPU time 305.91 seconds
Started Jul 27 07:33:52 PM PDT 24
Finished Jul 27 07:38:58 PM PDT 24
Peak memory 215628 kb
Host smart-4a29677c-1204-43cf-9ef9-bee804d45777
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3461014187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.3461014187
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.2650184404
Short name T392
Test name
Test status
Simulation time 5112465242 ps
CPU time 37.5 seconds
Started Jul 27 07:33:53 PM PDT 24
Finished Jul 27 07:34:30 PM PDT 24
Peak memory 207324 kb
Host smart-cea4d0f0-6443-47c5-a37e-efd02f802a98
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2650184404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.2650184404
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1580513732
Short name T879
Test name
Test status
Simulation time 171025023 ps
CPU time 0.88 seconds
Started Jul 27 07:33:49 PM PDT 24
Finished Jul 27 07:33:50 PM PDT 24
Peak memory 207132 kb
Host smart-795c659b-be1d-43cb-aba3-aa8d4bcbbd16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15805
13732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1580513732
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.3732305643
Short name T1630
Test name
Test status
Simulation time 23388810162 ps
CPU time 27.48 seconds
Started Jul 27 07:33:50 PM PDT 24
Finished Jul 27 07:34:17 PM PDT 24
Peak memory 207332 kb
Host smart-a44fad74-daa2-4aa4-9df9-b429b24c203a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37323
05643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.3732305643
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3847251962
Short name T2351
Test name
Test status
Simulation time 3280447668 ps
CPU time 4.84 seconds
Started Jul 27 07:33:52 PM PDT 24
Finished Jul 27 07:33:57 PM PDT 24
Peak memory 207320 kb
Host smart-f127fba2-38ee-4484-b95b-5979f25e481d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38472
51962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3847251962
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2709946964
Short name T839
Test name
Test status
Simulation time 7117057073 ps
CPU time 52.54 seconds
Started Jul 27 07:33:50 PM PDT 24
Finished Jul 27 07:34:43 PM PDT 24
Peak memory 217380 kb
Host smart-5a2c97a3-32ec-4ce9-a3f1-e08411cc492a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27099
46964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2709946964
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.1072455702
Short name T727
Test name
Test status
Simulation time 4553262382 ps
CPU time 133.01 seconds
Started Jul 27 07:33:53 PM PDT 24
Finished Jul 27 07:36:06 PM PDT 24
Peak memory 223456 kb
Host smart-d278964e-c48b-440a-8148-db9adb5df895
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1072455702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.1072455702
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.3265561828
Short name T599
Test name
Test status
Simulation time 261706572 ps
CPU time 1.08 seconds
Started Jul 27 07:33:54 PM PDT 24
Finished Jul 27 07:33:56 PM PDT 24
Peak memory 207140 kb
Host smart-b08aacb4-2cbe-4d92-af64-69eb68436f0e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3265561828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.3265561828
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.517758255
Short name T1527
Test name
Test status
Simulation time 194292233 ps
CPU time 0.93 seconds
Started Jul 27 07:33:53 PM PDT 24
Finished Jul 27 07:33:54 PM PDT 24
Peak memory 207108 kb
Host smart-13193e86-d442-4db5-a43b-fb2626d76ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51775
8255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.517758255
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1826811397
Short name T391
Test name
Test status
Simulation time 4055313121 ps
CPU time 33.8 seconds
Started Jul 27 07:33:51 PM PDT 24
Finished Jul 27 07:34:25 PM PDT 24
Peak memory 216716 kb
Host smart-a68f21fc-e0cd-44d3-8625-52af427a46dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18268
11397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1826811397
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.2518251224
Short name T931
Test name
Test status
Simulation time 3543289899 ps
CPU time 27.94 seconds
Started Jul 27 07:33:57 PM PDT 24
Finished Jul 27 07:34:25 PM PDT 24
Peak memory 216852 kb
Host smart-08799ac6-8073-41f2-be84-bb865657901f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2518251224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.2518251224
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1738362239
Short name T2265
Test name
Test status
Simulation time 155667868 ps
CPU time 0.84 seconds
Started Jul 27 07:33:58 PM PDT 24
Finished Jul 27 07:33:59 PM PDT 24
Peak memory 207100 kb
Host smart-5a05ee47-3ca2-440a-93f0-5c9e0175a108
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1738362239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1738362239
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2411686240
Short name T1689
Test name
Test status
Simulation time 155535026 ps
CPU time 0.85 seconds
Started Jul 27 07:33:57 PM PDT 24
Finished Jul 27 07:33:58 PM PDT 24
Peak memory 207196 kb
Host smart-2a963962-6770-4d85-a83c-835299054b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24116
86240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2411686240
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1522364251
Short name T128
Test name
Test status
Simulation time 195965836 ps
CPU time 0.89 seconds
Started Jul 27 07:33:56 PM PDT 24
Finished Jul 27 07:33:57 PM PDT 24
Peak memory 207032 kb
Host smart-fd84c216-a475-4760-a814-7f1fe7537a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15223
64251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1522364251
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1473923732
Short name T1960
Test name
Test status
Simulation time 193320597 ps
CPU time 0.93 seconds
Started Jul 27 07:33:58 PM PDT 24
Finished Jul 27 07:33:59 PM PDT 24
Peak memory 207348 kb
Host smart-b82506b0-d1c0-459d-9673-b163091806ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14739
23732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1473923732
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1114978110
Short name T1457
Test name
Test status
Simulation time 176151227 ps
CPU time 0.94 seconds
Started Jul 27 07:33:55 PM PDT 24
Finished Jul 27 07:33:56 PM PDT 24
Peak memory 207028 kb
Host smart-3d686430-6566-48a9-93e3-52ff3c64d097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11149
78110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1114978110
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3651934335
Short name T1424
Test name
Test status
Simulation time 160202424 ps
CPU time 0.84 seconds
Started Jul 27 07:33:57 PM PDT 24
Finished Jul 27 07:33:58 PM PDT 24
Peak memory 207324 kb
Host smart-33ce17fe-dd4f-4d80-9ef3-e025199e35d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36519
34335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3651934335
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.3229803337
Short name T2701
Test name
Test status
Simulation time 225595111 ps
CPU time 0.97 seconds
Started Jul 27 07:34:01 PM PDT 24
Finished Jul 27 07:34:02 PM PDT 24
Peak memory 207156 kb
Host smart-686d08f2-2afb-434d-b050-55aa40b1021a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3229803337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.3229803337
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.4046085202
Short name T2313
Test name
Test status
Simulation time 232052000 ps
CPU time 0.99 seconds
Started Jul 27 07:33:56 PM PDT 24
Finished Jul 27 07:33:57 PM PDT 24
Peak memory 207112 kb
Host smart-4bd580e9-3492-4d47-b791-27088009546e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40460
85202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.4046085202
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1678624757
Short name T1897
Test name
Test status
Simulation time 219183050 ps
CPU time 0.89 seconds
Started Jul 27 07:33:59 PM PDT 24
Finished Jul 27 07:34:00 PM PDT 24
Peak memory 207032 kb
Host smart-fb74069e-fd95-45b3-b66b-b673c3b6062b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16786
24757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1678624757
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2063021203
Short name T2061
Test name
Test status
Simulation time 49996245 ps
CPU time 0.73 seconds
Started Jul 27 07:33:59 PM PDT 24
Finished Jul 27 07:34:00 PM PDT 24
Peak memory 207108 kb
Host smart-557b93ca-b4c8-4f50-9549-ebb0ec1de510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20630
21203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2063021203
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3936407954
Short name T280
Test name
Test status
Simulation time 14500129746 ps
CPU time 39.15 seconds
Started Jul 27 07:34:03 PM PDT 24
Finished Jul 27 07:34:42 PM PDT 24
Peak memory 215580 kb
Host smart-cc933467-9277-4d7f-bd5f-5213e83bde00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39364
07954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3936407954
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3728560930
Short name T2765
Test name
Test status
Simulation time 165812958 ps
CPU time 0.89 seconds
Started Jul 27 07:34:07 PM PDT 24
Finished Jul 27 07:34:08 PM PDT 24
Peak memory 207140 kb
Host smart-03cdcdc9-31ee-4a30-8cce-ff87dbf1f095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37285
60930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3728560930
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1597419038
Short name T1631
Test name
Test status
Simulation time 169265878 ps
CPU time 0.9 seconds
Started Jul 27 07:34:04 PM PDT 24
Finished Jul 27 07:34:05 PM PDT 24
Peak memory 207116 kb
Host smart-c24affdb-e842-44b6-a4c3-0bb03a6caeb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15974
19038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1597419038
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3354640549
Short name T811
Test name
Test status
Simulation time 11444535592 ps
CPU time 214.51 seconds
Started Jul 27 07:34:04 PM PDT 24
Finished Jul 27 07:37:39 PM PDT 24
Peak memory 215604 kb
Host smart-9485d5cf-f1b1-4a14-b015-c0226250cb07
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354640549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3354640549
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1942384572
Short name T2553
Test name
Test status
Simulation time 8194660722 ps
CPU time 143.98 seconds
Started Jul 27 07:34:05 PM PDT 24
Finished Jul 27 07:36:29 PM PDT 24
Peak memory 215596 kb
Host smart-3ce11c9f-107f-45c7-9072-0e97cebe0101
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1942384572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1942384572
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2847778463
Short name T913
Test name
Test status
Simulation time 15262981454 ps
CPU time 360.57 seconds
Started Jul 27 07:34:03 PM PDT 24
Finished Jul 27 07:40:04 PM PDT 24
Peak memory 215636 kb
Host smart-13e2647e-cddb-4950-aa0a-27dedd04a368
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847778463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2847778463
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.291305918
Short name T1514
Test name
Test status
Simulation time 185468791 ps
CPU time 0.91 seconds
Started Jul 27 07:34:02 PM PDT 24
Finished Jul 27 07:34:03 PM PDT 24
Peak memory 207092 kb
Host smart-8b122493-05f2-481e-b6c9-27df70756207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29130
5918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.291305918
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.209478753
Short name T2581
Test name
Test status
Simulation time 182176890 ps
CPU time 0.88 seconds
Started Jul 27 07:34:05 PM PDT 24
Finished Jul 27 07:34:06 PM PDT 24
Peak memory 207144 kb
Host smart-1c911cd2-df4c-45b3-9435-9ecbfb732e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20947
8753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.209478753
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1469223952
Short name T65
Test name
Test status
Simulation time 153158775 ps
CPU time 0.86 seconds
Started Jul 27 07:34:02 PM PDT 24
Finished Jul 27 07:34:03 PM PDT 24
Peak memory 207160 kb
Host smart-b28c19af-0843-43d3-a23d-9b9c6d20b6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14692
23952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1469223952
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1335448971
Short name T2096
Test name
Test status
Simulation time 161205978 ps
CPU time 0.85 seconds
Started Jul 27 07:34:05 PM PDT 24
Finished Jul 27 07:34:06 PM PDT 24
Peak memory 207124 kb
Host smart-f0de270a-c5e1-4fa4-a3cc-dadc49dce445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13354
48971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1335448971
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1021928261
Short name T204
Test name
Test status
Simulation time 883867945 ps
CPU time 1.76 seconds
Started Jul 27 07:34:05 PM PDT 24
Finished Jul 27 07:34:07 PM PDT 24
Peak memory 224020 kb
Host smart-d69b0b40-6b90-4853-8451-2d1510919c9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1021928261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1021928261
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.3723340870
Short name T47
Test name
Test status
Simulation time 404967704 ps
CPU time 1.4 seconds
Started Jul 27 07:34:05 PM PDT 24
Finished Jul 27 07:34:06 PM PDT 24
Peak memory 207108 kb
Host smart-d2019286-cd64-4caf-976c-525c3504f6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37233
40870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3723340870
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.2837808778
Short name T184
Test name
Test status
Simulation time 214273713 ps
CPU time 0.95 seconds
Started Jul 27 07:34:04 PM PDT 24
Finished Jul 27 07:34:05 PM PDT 24
Peak memory 207144 kb
Host smart-5ae13519-0c6f-426e-87e9-8e8c9871148d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28378
08778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.2837808778
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2680232760
Short name T2669
Test name
Test status
Simulation time 153911393 ps
CPU time 0.83 seconds
Started Jul 27 07:34:03 PM PDT 24
Finished Jul 27 07:34:04 PM PDT 24
Peak memory 207092 kb
Host smart-c553649c-6b03-4b56-a176-a69d8a9d1b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26802
32760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2680232760
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.1887240152
Short name T2663
Test name
Test status
Simulation time 159467104 ps
CPU time 0.85 seconds
Started Jul 27 07:34:03 PM PDT 24
Finished Jul 27 07:34:04 PM PDT 24
Peak memory 207144 kb
Host smart-7de876c9-5ac4-4991-9dbf-655b2f0e700a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18872
40152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.1887240152
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3976797244
Short name T625
Test name
Test status
Simulation time 227125800 ps
CPU time 1.06 seconds
Started Jul 27 07:34:05 PM PDT 24
Finished Jul 27 07:34:06 PM PDT 24
Peak memory 207112 kb
Host smart-5f01b95b-7c4e-4464-ac66-c9695be86a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39767
97244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3976797244
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1776745019
Short name T2591
Test name
Test status
Simulation time 6081306010 ps
CPU time 59.49 seconds
Started Jul 27 07:34:02 PM PDT 24
Finished Jul 27 07:35:02 PM PDT 24
Peak memory 215624 kb
Host smart-dd42c8f9-0396-43be-b2f0-feec5a8e6e05
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1776745019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1776745019
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1164415219
Short name T2467
Test name
Test status
Simulation time 169169881 ps
CPU time 0.92 seconds
Started Jul 27 07:34:04 PM PDT 24
Finished Jul 27 07:34:05 PM PDT 24
Peak memory 207152 kb
Host smart-377f7066-de1c-46d7-ab2a-82af5b526e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11644
15219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1164415219
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1310707474
Short name T799
Test name
Test status
Simulation time 171633239 ps
CPU time 0.89 seconds
Started Jul 27 07:34:08 PM PDT 24
Finished Jul 27 07:34:09 PM PDT 24
Peak memory 207136 kb
Host smart-87c65089-8920-46c6-ac9e-b93afbb91354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13107
07474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1310707474
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.3879862744
Short name T2117
Test name
Test status
Simulation time 780095883 ps
CPU time 2.01 seconds
Started Jul 27 07:34:05 PM PDT 24
Finished Jul 27 07:34:07 PM PDT 24
Peak memory 207088 kb
Host smart-61afe1e1-70e9-4d21-8601-4237c233b00c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38798
62744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.3879862744
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2810120501
Short name T1545
Test name
Test status
Simulation time 5390963848 ps
CPU time 39.56 seconds
Started Jul 27 07:34:05 PM PDT 24
Finished Jul 27 07:34:45 PM PDT 24
Peak memory 207364 kb
Host smart-05328b73-c3da-48c5-932a-1af7794c2124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28101
20501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2810120501
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.2923978449
Short name T1698
Test name
Test status
Simulation time 1555030244 ps
CPU time 36.19 seconds
Started Jul 27 07:33:52 PM PDT 24
Finished Jul 27 07:34:28 PM PDT 24
Peak memory 207276 kb
Host smart-c2305b32-8759-45cc-941f-dba789b70345
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923978449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host
_handshake.2923978449
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.203472032
Short name T196
Test name
Test status
Simulation time 33924983 ps
CPU time 0.66 seconds
Started Jul 27 07:38:28 PM PDT 24
Finished Jul 27 07:38:29 PM PDT 24
Peak memory 207132 kb
Host smart-5e35ee13-767a-45ed-88a1-d9df78cfc2fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=203472032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.203472032
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2683842192
Short name T1609
Test name
Test status
Simulation time 4079106741 ps
CPU time 5.66 seconds
Started Jul 27 07:38:16 PM PDT 24
Finished Jul 27 07:38:22 PM PDT 24
Peak memory 207408 kb
Host smart-e270a931-0dd7-4610-b683-c653929e4486
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683842192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_disconnect.2683842192
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1800558518
Short name T1445
Test name
Test status
Simulation time 13396858015 ps
CPU time 15.86 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:38:30 PM PDT 24
Peak memory 207376 kb
Host smart-a29435b6-bc2a-4a50-bf23-aaf3f12ce2fd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800558518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1800558518
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.786526057
Short name T2343
Test name
Test status
Simulation time 23354294520 ps
CPU time 30.31 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:38:44 PM PDT 24
Peak memory 207388 kb
Host smart-518144c9-3c9f-4e15-8be3-2c7730dca6bc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786526057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_ao
n_wake_resume.786526057
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1392833640
Short name T2047
Test name
Test status
Simulation time 143192485 ps
CPU time 0.84 seconds
Started Jul 27 07:38:13 PM PDT 24
Finished Jul 27 07:38:14 PM PDT 24
Peak memory 207132 kb
Host smart-80f71caf-bd58-45da-bef5-0c4a8439426a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13928
33640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1392833640
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.3082576479
Short name T63
Test name
Test status
Simulation time 167071573 ps
CPU time 0.86 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:38:15 PM PDT 24
Peak memory 207108 kb
Host smart-9d019172-94c4-46f6-b929-c049aa4f7685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30825
76479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3082576479
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2780952183
Short name T1407
Test name
Test status
Simulation time 377972670 ps
CPU time 1.32 seconds
Started Jul 27 07:38:13 PM PDT 24
Finished Jul 27 07:38:14 PM PDT 24
Peak memory 207104 kb
Host smart-87e5e6fd-45c3-45b9-8016-c90f38dd68ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27809
52183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2780952183
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2482101280
Short name T777
Test name
Test status
Simulation time 560356267 ps
CPU time 1.65 seconds
Started Jul 27 07:38:13 PM PDT 24
Finished Jul 27 07:38:15 PM PDT 24
Peak memory 207072 kb
Host smart-aa5d3798-8b5b-4f39-9678-8e4b5167d834
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2482101280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2482101280
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.2534148821
Short name T2801
Test name
Test status
Simulation time 1259921820 ps
CPU time 30.46 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:38:45 PM PDT 24
Peak memory 207336 kb
Host smart-200bfd5c-91bc-44df-8ab1-fa438fdf723b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534148821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.2534148821
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3177061736
Short name T2836
Test name
Test status
Simulation time 480121208 ps
CPU time 1.45 seconds
Started Jul 27 07:38:13 PM PDT 24
Finished Jul 27 07:38:14 PM PDT 24
Peak memory 206976 kb
Host smart-2ac1e212-5c28-47e8-8a79-75c2bea4acd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31770
61736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3177061736
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.3193509582
Short name T1488
Test name
Test status
Simulation time 137450885 ps
CPU time 0.79 seconds
Started Jul 27 07:38:12 PM PDT 24
Finished Jul 27 07:38:13 PM PDT 24
Peak memory 207080 kb
Host smart-6a028d4d-5d3f-4195-abd3-f804bfe08166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31935
09582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.3193509582
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3038332899
Short name T1269
Test name
Test status
Simulation time 35334328 ps
CPU time 0.71 seconds
Started Jul 27 07:38:12 PM PDT 24
Finished Jul 27 07:38:13 PM PDT 24
Peak memory 207068 kb
Host smart-50f0c7b8-75f8-4d31-8958-60eee102df01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30383
32899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3038332899
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.1150909276
Short name T619
Test name
Test status
Simulation time 936542007 ps
CPU time 2.56 seconds
Started Jul 27 07:38:17 PM PDT 24
Finished Jul 27 07:38:19 PM PDT 24
Peak memory 207340 kb
Host smart-3aab6cbd-160b-40a1-87d8-a1ef64b3c909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11509
09276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.1150909276
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2131062498
Short name T412
Test name
Test status
Simulation time 294961260 ps
CPU time 2.27 seconds
Started Jul 27 07:38:15 PM PDT 24
Finished Jul 27 07:38:17 PM PDT 24
Peak memory 207360 kb
Host smart-1c94965c-c148-428c-b87b-97b23028a19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21310
62498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2131062498
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1625146815
Short name T2794
Test name
Test status
Simulation time 183416279 ps
CPU time 0.9 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:38:15 PM PDT 24
Peak memory 207144 kb
Host smart-2e84aff0-91de-4028-8bef-784ae65390c6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1625146815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1625146815
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2445934480
Short name T2511
Test name
Test status
Simulation time 143979746 ps
CPU time 0.79 seconds
Started Jul 27 07:38:12 PM PDT 24
Finished Jul 27 07:38:13 PM PDT 24
Peak memory 207072 kb
Host smart-0c42f039-f934-4ef2-a190-fae59dce1432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24459
34480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2445934480
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.965807641
Short name T2690
Test name
Test status
Simulation time 238998749 ps
CPU time 0.97 seconds
Started Jul 27 07:38:12 PM PDT 24
Finished Jul 27 07:38:13 PM PDT 24
Peak memory 206988 kb
Host smart-a089033a-113d-4c6a-b698-643d244822ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96580
7641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.965807641
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.2059362963
Short name T476
Test name
Test status
Simulation time 9397716783 ps
CPU time 68.64 seconds
Started Jul 27 07:38:10 PM PDT 24
Finished Jul 27 07:39:19 PM PDT 24
Peak memory 216840 kb
Host smart-84fac7df-3c94-40d6-8f8c-38703c837823
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2059362963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2059362963
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.2730212427
Short name T937
Test name
Test status
Simulation time 9995097695 ps
CPU time 130.52 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:40:25 PM PDT 24
Peak memory 207408 kb
Host smart-b1eecd0e-a801-4dc9-a49c-9c160c45a1f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2730212427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.2730212427
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.2906335822
Short name T1729
Test name
Test status
Simulation time 202055332 ps
CPU time 0.96 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:38:15 PM PDT 24
Peak memory 207136 kb
Host smart-6ff75f2d-d722-4f00-95e5-dab5e4768710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29063
35822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.2906335822
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.852253583
Short name T1982
Test name
Test status
Simulation time 23285905383 ps
CPU time 28.51 seconds
Started Jul 27 07:38:13 PM PDT 24
Finished Jul 27 07:38:42 PM PDT 24
Peak memory 207340 kb
Host smart-6f24ee57-4b17-4113-9f9e-e5a1dda44b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85225
3583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.852253583
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.1115361004
Short name T333
Test name
Test status
Simulation time 3362923718 ps
CPU time 4.8 seconds
Started Jul 27 07:38:13 PM PDT 24
Finished Jul 27 07:38:18 PM PDT 24
Peak memory 207272 kb
Host smart-03f8e64c-a132-493b-9c1b-cd88b4832b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11153
61004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1115361004
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.3935835638
Short name T1404
Test name
Test status
Simulation time 6655821206 ps
CPU time 59.86 seconds
Started Jul 27 07:38:17 PM PDT 24
Finished Jul 27 07:39:17 PM PDT 24
Peak memory 217236 kb
Host smart-d0ba646e-65c9-4ff7-afad-fab918b4d5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39358
35638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.3935835638
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2389719391
Short name T1988
Test name
Test status
Simulation time 6388806732 ps
CPU time 65.9 seconds
Started Jul 27 07:38:17 PM PDT 24
Finished Jul 27 07:39:23 PM PDT 24
Peak memory 207408 kb
Host smart-782b4018-509f-41be-bbf2-78370360f9c6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2389719391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2389719391
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2983455649
Short name T890
Test name
Test status
Simulation time 243951326 ps
CPU time 1.05 seconds
Started Jul 27 07:38:19 PM PDT 24
Finished Jul 27 07:38:20 PM PDT 24
Peak memory 207172 kb
Host smart-905408f7-3741-4011-986f-57fa75d7c78d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2983455649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2983455649
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1497802109
Short name T1287
Test name
Test status
Simulation time 195706198 ps
CPU time 0.96 seconds
Started Jul 27 07:38:16 PM PDT 24
Finished Jul 27 07:38:17 PM PDT 24
Peak memory 207140 kb
Host smart-12610fb5-b7af-4d6b-814b-fcf6f3a6d774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14978
02109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1497802109
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3795533496
Short name T2674
Test name
Test status
Simulation time 3956745199 ps
CPU time 31.52 seconds
Started Jul 27 07:38:20 PM PDT 24
Finished Jul 27 07:38:51 PM PDT 24
Peak memory 217168 kb
Host smart-192dde00-58ad-486d-997a-84e6fe990756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37955
33496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3795533496
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.3648813975
Short name T2232
Test name
Test status
Simulation time 4425858463 ps
CPU time 126.21 seconds
Started Jul 27 07:38:17 PM PDT 24
Finished Jul 27 07:40:23 PM PDT 24
Peak memory 215588 kb
Host smart-ab392b20-d933-496d-b5ad-988a830a35d9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3648813975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.3648813975
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.169920698
Short name T652
Test name
Test status
Simulation time 168240058 ps
CPU time 0.86 seconds
Started Jul 27 07:38:18 PM PDT 24
Finished Jul 27 07:38:19 PM PDT 24
Peak memory 207136 kb
Host smart-702104e9-431d-4664-94de-76b20a092043
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=169920698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.169920698
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1004648851
Short name T2247
Test name
Test status
Simulation time 139607369 ps
CPU time 0.82 seconds
Started Jul 27 07:38:20 PM PDT 24
Finished Jul 27 07:38:21 PM PDT 24
Peak memory 207120 kb
Host smart-ae997326-39f4-46bc-8e93-cd2223962aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10046
48851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1004648851
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3683552679
Short name T1023
Test name
Test status
Simulation time 179463336 ps
CPU time 0.92 seconds
Started Jul 27 07:38:21 PM PDT 24
Finished Jul 27 07:38:22 PM PDT 24
Peak memory 207156 kb
Host smart-c959d03a-908b-47bb-a8c9-d3d6ab45ba2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36835
52679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3683552679
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.405259817
Short name T926
Test name
Test status
Simulation time 177773257 ps
CPU time 0.87 seconds
Started Jul 27 07:38:17 PM PDT 24
Finished Jul 27 07:38:18 PM PDT 24
Peak memory 207036 kb
Host smart-43a010aa-6bde-4540-96e1-07e92b059399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40525
9817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.405259817
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3690106819
Short name T372
Test name
Test status
Simulation time 156296643 ps
CPU time 0.92 seconds
Started Jul 27 07:38:24 PM PDT 24
Finished Jul 27 07:38:25 PM PDT 24
Peak memory 207136 kb
Host smart-6752b2a7-694c-4d5a-9ca7-c3bd8d47c480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36901
06819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3690106819
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2533220930
Short name T1364
Test name
Test status
Simulation time 161450200 ps
CPU time 0.89 seconds
Started Jul 27 07:38:25 PM PDT 24
Finished Jul 27 07:38:26 PM PDT 24
Peak memory 207144 kb
Host smart-819f0a2e-a41f-4ce5-9a25-8cb2808df6ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25332
20930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2533220930
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2619480949
Short name T740
Test name
Test status
Simulation time 282811785 ps
CPU time 1.1 seconds
Started Jul 27 07:38:17 PM PDT 24
Finished Jul 27 07:38:18 PM PDT 24
Peak memory 207104 kb
Host smart-f4c9ba30-7d81-45d6-84ed-1a9f5d0a71df
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2619480949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2619480949
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.4074992877
Short name T635
Test name
Test status
Simulation time 197181137 ps
CPU time 0.89 seconds
Started Jul 27 07:38:17 PM PDT 24
Finished Jul 27 07:38:18 PM PDT 24
Peak memory 207072 kb
Host smart-6349bf3d-69a8-42d6-8ba0-2e34675d5f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40749
92877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.4074992877
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2138639203
Short name T1536
Test name
Test status
Simulation time 36785641 ps
CPU time 0.73 seconds
Started Jul 27 07:38:19 PM PDT 24
Finished Jul 27 07:38:20 PM PDT 24
Peak memory 207056 kb
Host smart-96602130-2394-44fe-a368-a34c2b867ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21386
39203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2138639203
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.2182548489
Short name T1980
Test name
Test status
Simulation time 13613396134 ps
CPU time 34.49 seconds
Started Jul 27 07:38:17 PM PDT 24
Finished Jul 27 07:38:51 PM PDT 24
Peak memory 215576 kb
Host smart-59e1c4ec-5852-4cd7-92f7-57719f6dcf0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21825
48489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.2182548489
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2301958021
Short name T1494
Test name
Test status
Simulation time 179009869 ps
CPU time 0.91 seconds
Started Jul 27 07:38:19 PM PDT 24
Finished Jul 27 07:38:20 PM PDT 24
Peak memory 207124 kb
Host smart-6d3a0578-73b7-450a-aa54-8c6f5011979a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23019
58021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2301958021
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2485560629
Short name T1339
Test name
Test status
Simulation time 222835169 ps
CPU time 0.95 seconds
Started Jul 27 07:38:18 PM PDT 24
Finished Jul 27 07:38:19 PM PDT 24
Peak memory 207188 kb
Host smart-75da799b-d9bf-4015-b9e3-d9e891432ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24855
60629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2485560629
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.770694131
Short name T1165
Test name
Test status
Simulation time 179464115 ps
CPU time 0.89 seconds
Started Jul 27 07:38:17 PM PDT 24
Finished Jul 27 07:38:18 PM PDT 24
Peak memory 207136 kb
Host smart-92cf2c89-c237-48ad-8c5f-4c4f1b89e48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77069
4131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.770694131
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.233841360
Short name T1110
Test name
Test status
Simulation time 147274085 ps
CPU time 0.82 seconds
Started Jul 27 07:38:18 PM PDT 24
Finished Jul 27 07:38:19 PM PDT 24
Peak memory 207112 kb
Host smart-828c1089-6444-4da6-a00e-250d3584bd5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23384
1360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.233841360
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.267137160
Short name T2440
Test name
Test status
Simulation time 178175942 ps
CPU time 0.82 seconds
Started Jul 27 07:38:16 PM PDT 24
Finished Jul 27 07:38:16 PM PDT 24
Peak memory 207088 kb
Host smart-c94f5947-60bb-4fd5-b9d6-a40f3f33d1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26713
7160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.267137160
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.548546991
Short name T2371
Test name
Test status
Simulation time 150117876 ps
CPU time 0.86 seconds
Started Jul 27 07:38:16 PM PDT 24
Finished Jul 27 07:38:17 PM PDT 24
Peak memory 207096 kb
Host smart-92422277-e868-4ae2-ba3f-eccb6c1d08aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54854
6991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.548546991
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3377450580
Short name T739
Test name
Test status
Simulation time 205306133 ps
CPU time 0.94 seconds
Started Jul 27 07:38:19 PM PDT 24
Finished Jul 27 07:38:20 PM PDT 24
Peak memory 207108 kb
Host smart-deccaa70-d54a-448f-ad74-d75256771cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33774
50580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3377450580
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1649339910
Short name T2395
Test name
Test status
Simulation time 6847377045 ps
CPU time 71.01 seconds
Started Jul 27 07:38:27 PM PDT 24
Finished Jul 27 07:39:39 PM PDT 24
Peak memory 216940 kb
Host smart-8367a395-aa89-4c6c-b67e-ac1d0f708053
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1649339910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1649339910
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2510730904
Short name T294
Test name
Test status
Simulation time 166641070 ps
CPU time 0.85 seconds
Started Jul 27 07:38:23 PM PDT 24
Finished Jul 27 07:38:24 PM PDT 24
Peak memory 207092 kb
Host smart-96e434b7-c818-4e2d-b234-23297296fd76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25107
30904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2510730904
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3048887021
Short name T988
Test name
Test status
Simulation time 217204567 ps
CPU time 0.92 seconds
Started Jul 27 07:38:22 PM PDT 24
Finished Jul 27 07:38:23 PM PDT 24
Peak memory 207072 kb
Host smart-700fca98-72c4-4c71-a290-4c2392525609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30488
87021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3048887021
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.1441965020
Short name T366
Test name
Test status
Simulation time 437606348 ps
CPU time 1.39 seconds
Started Jul 27 07:38:26 PM PDT 24
Finished Jul 27 07:38:28 PM PDT 24
Peak memory 207108 kb
Host smart-e3252ee1-ef22-4a95-b730-4281fc3aa360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14419
65020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.1441965020
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.2900989906
Short name T1099
Test name
Test status
Simulation time 6281703106 ps
CPU time 186.85 seconds
Started Jul 27 07:38:26 PM PDT 24
Finished Jul 27 07:41:33 PM PDT 24
Peak memory 215580 kb
Host smart-fc0b6343-478f-4ffc-885b-129153aec808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29009
89906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2900989906
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.1180916483
Short name T2601
Test name
Test status
Simulation time 5009310203 ps
CPU time 33.06 seconds
Started Jul 27 07:38:14 PM PDT 24
Finished Jul 27 07:38:47 PM PDT 24
Peak memory 207344 kb
Host smart-921680c6-5782-4eff-8d01-37e90f4e658b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180916483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.1180916483
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.234145152
Short name T1427
Test name
Test status
Simulation time 52424592 ps
CPU time 0.67 seconds
Started Jul 27 07:38:36 PM PDT 24
Finished Jul 27 07:38:37 PM PDT 24
Peak memory 207064 kb
Host smart-058956ae-eae4-44ac-be83-9722fbdda9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=234145152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.234145152
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3343353929
Short name T514
Test name
Test status
Simulation time 3867515666 ps
CPU time 5.63 seconds
Started Jul 27 07:38:24 PM PDT 24
Finished Jul 27 07:38:29 PM PDT 24
Peak memory 207428 kb
Host smart-a1ccbc35-7e1f-4dca-a6bc-b0b01a66702e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343353929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.3343353929
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.402403295
Short name T2571
Test name
Test status
Simulation time 13332796336 ps
CPU time 16.48 seconds
Started Jul 27 07:38:27 PM PDT 24
Finished Jul 27 07:38:43 PM PDT 24
Peak memory 207400 kb
Host smart-3ad20eed-0d3e-4f61-82eb-871a576a62c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=402403295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.402403295
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.811509932
Short name T433
Test name
Test status
Simulation time 23382594902 ps
CPU time 28.51 seconds
Started Jul 27 07:38:29 PM PDT 24
Finished Jul 27 07:38:58 PM PDT 24
Peak memory 207384 kb
Host smart-1b7dd660-3d28-4969-9152-0a9650bea8a2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811509932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_ao
n_wake_resume.811509932
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3173341292
Short name T2691
Test name
Test status
Simulation time 183596769 ps
CPU time 0.97 seconds
Started Jul 27 07:38:24 PM PDT 24
Finished Jul 27 07:38:25 PM PDT 24
Peak memory 207088 kb
Host smart-33227d7b-e6d3-43fa-804d-4b611fb90c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31733
41292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3173341292
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.703360464
Short name T2417
Test name
Test status
Simulation time 168183645 ps
CPU time 0.86 seconds
Started Jul 27 07:38:26 PM PDT 24
Finished Jul 27 07:38:27 PM PDT 24
Peak memory 207132 kb
Host smart-e8137fa7-6de5-47ea-b595-1ac06f2dfa34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70336
0464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.703360464
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1844117996
Short name T2679
Test name
Test status
Simulation time 363962680 ps
CPU time 1.3 seconds
Started Jul 27 07:38:26 PM PDT 24
Finished Jul 27 07:38:28 PM PDT 24
Peak memory 207156 kb
Host smart-3c74dcc8-bf5b-4cc9-b014-e951d8519c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18441
17996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1844117996
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.725220737
Short name T2479
Test name
Test status
Simulation time 1446225504 ps
CPU time 3.84 seconds
Started Jul 27 07:38:22 PM PDT 24
Finished Jul 27 07:38:26 PM PDT 24
Peak memory 207376 kb
Host smart-0a6bf4b7-1542-4f72-97b5-354268b17ea4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=725220737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.725220737
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.776509664
Short name T1881
Test name
Test status
Simulation time 2444632574 ps
CPU time 21.94 seconds
Started Jul 27 07:38:23 PM PDT 24
Finished Jul 27 07:38:45 PM PDT 24
Peak memory 207392 kb
Host smart-a61167e8-ea45-407e-b708-d68b35473c15
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776509664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.776509664
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.2511163564
Short name T1705
Test name
Test status
Simulation time 421094730 ps
CPU time 1.4 seconds
Started Jul 27 07:38:24 PM PDT 24
Finished Jul 27 07:38:26 PM PDT 24
Peak memory 207076 kb
Host smart-4c586042-d504-4a21-a7d7-b54f025945fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25111
63564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.2511163564
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.2963226574
Short name T2275
Test name
Test status
Simulation time 150320043 ps
CPU time 0.83 seconds
Started Jul 27 07:38:25 PM PDT 24
Finished Jul 27 07:38:26 PM PDT 24
Peak memory 207072 kb
Host smart-dbc96b97-b635-442e-af6e-0ff934a69233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29632
26574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.2963226574
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1081108470
Short name T487
Test name
Test status
Simulation time 38957291 ps
CPU time 0.73 seconds
Started Jul 27 07:38:25 PM PDT 24
Finished Jul 27 07:38:26 PM PDT 24
Peak memory 207184 kb
Host smart-f311f38c-fb3e-42ae-a1f7-8a6151e5a1d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811
08470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1081108470
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1231643258
Short name T946
Test name
Test status
Simulation time 917526943 ps
CPU time 2.56 seconds
Started Jul 27 07:38:25 PM PDT 24
Finished Jul 27 07:38:28 PM PDT 24
Peak memory 207320 kb
Host smart-118b3a17-af66-4536-8953-6c2bde72be41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12316
43258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1231643258
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.462428434
Short name T1189
Test name
Test status
Simulation time 239480787 ps
CPU time 1.42 seconds
Started Jul 27 07:38:26 PM PDT 24
Finished Jul 27 07:38:28 PM PDT 24
Peak memory 207296 kb
Host smart-18c3fa07-52a2-420a-887e-327d4085e809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46242
8434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.462428434
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.4099228084
Short name T2848
Test name
Test status
Simulation time 212214370 ps
CPU time 1.12 seconds
Started Jul 27 07:38:25 PM PDT 24
Finished Jul 27 07:38:27 PM PDT 24
Peak memory 215548 kb
Host smart-50f86604-b348-49b8-8214-3d2be3a2d520
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4099228084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.4099228084
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3349861642
Short name T1419
Test name
Test status
Simulation time 137839792 ps
CPU time 0.83 seconds
Started Jul 27 07:38:25 PM PDT 24
Finished Jul 27 07:38:26 PM PDT 24
Peak memory 207108 kb
Host smart-e73e7577-11ff-4736-bd6e-1edf70524367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33498
61642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3349861642
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3269213508
Short name T2823
Test name
Test status
Simulation time 286292032 ps
CPU time 1.01 seconds
Started Jul 27 07:38:25 PM PDT 24
Finished Jul 27 07:38:26 PM PDT 24
Peak memory 207112 kb
Host smart-09c7a5d9-9b27-44fc-af48-dfb4230d1ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32692
13508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3269213508
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.2122730893
Short name T1591
Test name
Test status
Simulation time 5672533394 ps
CPU time 54.3 seconds
Started Jul 27 07:38:25 PM PDT 24
Finished Jul 27 07:39:20 PM PDT 24
Peak memory 217004 kb
Host smart-afdb9746-6087-47c1-94db-99fb5814dd87
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2122730893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.2122730893
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.492483191
Short name T2730
Test name
Test status
Simulation time 7610194882 ps
CPU time 87.78 seconds
Started Jul 27 07:38:24 PM PDT 24
Finished Jul 27 07:39:52 PM PDT 24
Peak memory 207336 kb
Host smart-63369ac2-2ec6-44ed-bb80-759f466c5d3c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=492483191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.492483191
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.557330936
Short name T642
Test name
Test status
Simulation time 201341935 ps
CPU time 0.96 seconds
Started Jul 27 07:38:22 PM PDT 24
Finished Jul 27 07:38:23 PM PDT 24
Peak memory 207020 kb
Host smart-871fd28b-d680-4494-b4de-b5f9143e9c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55733
0936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.557330936
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.3915982754
Short name T832
Test name
Test status
Simulation time 23355168427 ps
CPU time 29.33 seconds
Started Jul 27 07:38:24 PM PDT 24
Finished Jul 27 07:38:53 PM PDT 24
Peak memory 207356 kb
Host smart-a15a46cc-774c-4f70-8162-b5c73c6f93b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39159
82754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.3915982754
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.2424278784
Short name T1242
Test name
Test status
Simulation time 3393043857 ps
CPU time 4.82 seconds
Started Jul 27 07:38:32 PM PDT 24
Finished Jul 27 07:38:37 PM PDT 24
Peak memory 207320 kb
Host smart-5ef2830c-ebfc-4253-b20a-c2fc22fe2999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24242
78784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.2424278784
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1947203245
Short name T2741
Test name
Test status
Simulation time 5887849279 ps
CPU time 162.17 seconds
Started Jul 27 07:38:30 PM PDT 24
Finished Jul 27 07:41:13 PM PDT 24
Peak memory 215588 kb
Host smart-c0fb04d1-f7d2-4201-adc0-47254558cc01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19472
03245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1947203245
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.1375612002
Short name T622
Test name
Test status
Simulation time 2847322770 ps
CPU time 20.94 seconds
Started Jul 27 07:38:30 PM PDT 24
Finished Jul 27 07:38:51 PM PDT 24
Peak memory 217028 kb
Host smart-e811a2c2-e2ca-4ac9-93cc-9e8b3ccb2584
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1375612002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.1375612002
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3668559217
Short name T951
Test name
Test status
Simulation time 276595924 ps
CPU time 0.99 seconds
Started Jul 27 07:38:31 PM PDT 24
Finished Jul 27 07:38:32 PM PDT 24
Peak memory 207096 kb
Host smart-379141fd-73fa-4fb8-905c-d2db8345c176
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3668559217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3668559217
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3788154303
Short name T2219
Test name
Test status
Simulation time 196975267 ps
CPU time 0.94 seconds
Started Jul 27 07:38:31 PM PDT 24
Finished Jul 27 07:38:32 PM PDT 24
Peak memory 207156 kb
Host smart-a8b91a70-3f63-42e2-a499-3e85d2163a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37881
54303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3788154303
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.2369151599
Short name T2715
Test name
Test status
Simulation time 5256672829 ps
CPU time 149.21 seconds
Started Jul 27 07:38:29 PM PDT 24
Finished Jul 27 07:40:58 PM PDT 24
Peak memory 215572 kb
Host smart-fc1b481d-7a96-48ba-8aab-0db5392bfed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23691
51599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.2369151599
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.4249580966
Short name T1315
Test name
Test status
Simulation time 4336049124 ps
CPU time 33.64 seconds
Started Jul 27 07:38:33 PM PDT 24
Finished Jul 27 07:39:06 PM PDT 24
Peak memory 207488 kb
Host smart-ed070d36-0fd2-4449-acee-5c7583a25312
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4249580966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.4249580966
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.532199578
Short name T1869
Test name
Test status
Simulation time 159834803 ps
CPU time 0.8 seconds
Started Jul 27 07:38:29 PM PDT 24
Finished Jul 27 07:38:30 PM PDT 24
Peak memory 207156 kb
Host smart-a6ae0111-3154-4e23-8b35-284bc7d38287
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=532199578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.532199578
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1095029495
Short name T682
Test name
Test status
Simulation time 150369146 ps
CPU time 0.83 seconds
Started Jul 27 07:38:30 PM PDT 24
Finished Jul 27 07:38:31 PM PDT 24
Peak memory 207196 kb
Host smart-aa3bba79-b3e3-4e6c-9fb8-87d59fa1070c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10950
29495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1095029495
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3054678079
Short name T2181
Test name
Test status
Simulation time 286269438 ps
CPU time 1.1 seconds
Started Jul 27 07:38:30 PM PDT 24
Finished Jul 27 07:38:32 PM PDT 24
Peak memory 207048 kb
Host smart-44a298db-bf3f-46d4-a8c8-002b4e6d9628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30546
78079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3054678079
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.948022243
Short name T2019
Test name
Test status
Simulation time 192686895 ps
CPU time 0.91 seconds
Started Jul 27 07:38:29 PM PDT 24
Finished Jul 27 07:38:30 PM PDT 24
Peak memory 207016 kb
Host smart-8ea10aab-97a9-4697-ac0c-fc16f82fceca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94802
2243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.948022243
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3866550469
Short name T352
Test name
Test status
Simulation time 155201437 ps
CPU time 0.88 seconds
Started Jul 27 07:38:31 PM PDT 24
Finished Jul 27 07:38:32 PM PDT 24
Peak memory 207056 kb
Host smart-9731e7e8-3ef9-48f2-8a64-1a429eed4811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38665
50469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3866550469
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3913583188
Short name T1643
Test name
Test status
Simulation time 179209238 ps
CPU time 0.94 seconds
Started Jul 27 07:38:30 PM PDT 24
Finished Jul 27 07:38:31 PM PDT 24
Peak memory 207140 kb
Host smart-f6dca084-ea81-479c-b861-e60e6f484bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39135
83188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3913583188
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1808125804
Short name T183
Test name
Test status
Simulation time 160003784 ps
CPU time 0.9 seconds
Started Jul 27 07:38:30 PM PDT 24
Finished Jul 27 07:38:31 PM PDT 24
Peak memory 207100 kb
Host smart-66de703a-c71f-45f5-a5a0-86c42896eb74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18081
25804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1808125804
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.2186397626
Short name T2292
Test name
Test status
Simulation time 258107777 ps
CPU time 1.1 seconds
Started Jul 27 07:38:32 PM PDT 24
Finished Jul 27 07:38:34 PM PDT 24
Peak memory 207136 kb
Host smart-366b25c3-08f8-4f5d-a1ee-e8215c9968dc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2186397626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2186397626
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.926430650
Short name T865
Test name
Test status
Simulation time 160632287 ps
CPU time 0.83 seconds
Started Jul 27 07:38:32 PM PDT 24
Finished Jul 27 07:38:33 PM PDT 24
Peak memory 207108 kb
Host smart-2e42a390-729f-4d23-8f79-1f5c29643738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92643
0650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.926430650
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.85841344
Short name T31
Test name
Test status
Simulation time 49185865 ps
CPU time 0.68 seconds
Started Jul 27 07:38:28 PM PDT 24
Finished Jul 27 07:38:29 PM PDT 24
Peak memory 207104 kb
Host smart-da390cd1-2736-4c76-bf33-bf7e9f18bf8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85841
344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.85841344
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2122933261
Short name T2706
Test name
Test status
Simulation time 17995357632 ps
CPU time 45.48 seconds
Started Jul 27 07:38:30 PM PDT 24
Finished Jul 27 07:39:16 PM PDT 24
Peak memory 215528 kb
Host smart-cc5de3d1-20cc-4c91-a176-b67345871a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21229
33261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2122933261
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3559092214
Short name T2082
Test name
Test status
Simulation time 177898555 ps
CPU time 0.92 seconds
Started Jul 27 07:38:30 PM PDT 24
Finished Jul 27 07:38:32 PM PDT 24
Peak memory 207112 kb
Host smart-9b95b3d2-3bd7-4f15-86e7-84580ed6e30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35590
92214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3559092214
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2212278533
Short name T2079
Test name
Test status
Simulation time 234976200 ps
CPU time 1 seconds
Started Jul 27 07:38:31 PM PDT 24
Finished Jul 27 07:38:32 PM PDT 24
Peak memory 207076 kb
Host smart-435a7f02-da04-4e64-9009-0abf4bf93bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22122
78533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2212278533
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.3497529763
Short name T2716
Test name
Test status
Simulation time 234904378 ps
CPU time 0.99 seconds
Started Jul 27 07:38:30 PM PDT 24
Finished Jul 27 07:38:31 PM PDT 24
Peak memory 207136 kb
Host smart-3a5f8850-6c3a-4d63-b75a-87f50ecd5bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34975
29763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.3497529763
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.653324437
Short name T2619
Test name
Test status
Simulation time 187002274 ps
CPU time 0.96 seconds
Started Jul 27 07:38:30 PM PDT 24
Finished Jul 27 07:38:31 PM PDT 24
Peak memory 207208 kb
Host smart-5484f50f-2898-4745-937b-878751b39a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65332
4437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.653324437
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2225678840
Short name T1554
Test name
Test status
Simulation time 179834320 ps
CPU time 0.86 seconds
Started Jul 27 07:38:32 PM PDT 24
Finished Jul 27 07:38:33 PM PDT 24
Peak memory 207108 kb
Host smart-7f6bfb22-6097-43a9-b361-890d03997211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22256
78840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2225678840
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2470280356
Short name T1847
Test name
Test status
Simulation time 161649954 ps
CPU time 0.91 seconds
Started Jul 27 07:38:31 PM PDT 24
Finished Jul 27 07:38:32 PM PDT 24
Peak memory 207104 kb
Host smart-341186b8-b539-466a-a297-66f6014fb533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24702
80356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2470280356
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.256122178
Short name T1370
Test name
Test status
Simulation time 160636746 ps
CPU time 0.85 seconds
Started Jul 27 07:38:31 PM PDT 24
Finished Jul 27 07:38:32 PM PDT 24
Peak memory 207100 kb
Host smart-d716388a-7d18-41a1-a440-f26fc0dc74d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25612
2178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.256122178
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1803440889
Short name T1348
Test name
Test status
Simulation time 241464238 ps
CPU time 1.09 seconds
Started Jul 27 07:38:31 PM PDT 24
Finished Jul 27 07:38:33 PM PDT 24
Peak memory 207100 kb
Host smart-aac4288d-e970-44e3-87fd-15a330ad402f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18034
40889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1803440889
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3024475692
Short name T515
Test name
Test status
Simulation time 3228625921 ps
CPU time 24.58 seconds
Started Jul 27 07:38:30 PM PDT 24
Finished Jul 27 07:38:55 PM PDT 24
Peak memory 215576 kb
Host smart-00955d66-359b-4511-8103-323586dffa89
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3024475692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3024475692
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1464095106
Short name T2514
Test name
Test status
Simulation time 181787979 ps
CPU time 0.88 seconds
Started Jul 27 07:38:32 PM PDT 24
Finished Jul 27 07:38:33 PM PDT 24
Peak memory 207116 kb
Host smart-6afe6a9e-342c-438e-ad29-bf4d39afbaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14640
95106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1464095106
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.392591083
Short name T2563
Test name
Test status
Simulation time 194169819 ps
CPU time 0.93 seconds
Started Jul 27 07:38:31 PM PDT 24
Finished Jul 27 07:38:32 PM PDT 24
Peak memory 207080 kb
Host smart-151133a0-d88c-47ed-92b8-8038b51e7c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39259
1083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.392591083
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.1175544690
Short name T1827
Test name
Test status
Simulation time 1200731755 ps
CPU time 2.95 seconds
Started Jul 27 07:38:45 PM PDT 24
Finished Jul 27 07:38:49 PM PDT 24
Peak memory 207360 kb
Host smart-7e857615-2f31-46de-882f-2ea774ac0068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11755
44690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.1175544690
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.3149635954
Short name T1473
Test name
Test status
Simulation time 6451391591 ps
CPU time 69.83 seconds
Started Jul 27 07:38:31 PM PDT 24
Finished Jul 27 07:39:41 PM PDT 24
Peak memory 207416 kb
Host smart-93e796fb-bf57-4ecd-940e-84c4e7825cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31496
35954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.3149635954
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.2445081272
Short name T1783
Test name
Test status
Simulation time 2007772799 ps
CPU time 17.16 seconds
Started Jul 27 07:38:26 PM PDT 24
Finished Jul 27 07:38:44 PM PDT 24
Peak memory 207276 kb
Host smart-5303c6ac-5699-48b8-baf7-bbe541fc3a83
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445081272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.2445081272
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.1243064761
Short name T1775
Test name
Test status
Simulation time 58005570 ps
CPU time 0.7 seconds
Started Jul 27 07:38:43 PM PDT 24
Finished Jul 27 07:38:44 PM PDT 24
Peak memory 207140 kb
Host smart-89addecb-05d5-4666-b3a5-3eb6032fb1f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1243064761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1243064761
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.811413111
Short name T12
Test name
Test status
Simulation time 3510579545 ps
CPU time 5.54 seconds
Started Jul 27 07:38:35 PM PDT 24
Finished Jul 27 07:38:41 PM PDT 24
Peak memory 207328 kb
Host smart-65657d96-6d25-48e3-a3f5-3dc62f73d933
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811413111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ao
n_wake_disconnect.811413111
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.231973938
Short name T232
Test name
Test status
Simulation time 13488078162 ps
CPU time 15.3 seconds
Started Jul 27 07:38:36 PM PDT 24
Finished Jul 27 07:38:52 PM PDT 24
Peak memory 207336 kb
Host smart-2d705686-faec-4336-aee1-653854ddc835
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=231973938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.231973938
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.558925417
Short name T2295
Test name
Test status
Simulation time 23299358115 ps
CPU time 27.36 seconds
Started Jul 27 07:38:37 PM PDT 24
Finished Jul 27 07:39:05 PM PDT 24
Peak memory 207476 kb
Host smart-02717b21-9272-4ebd-9db1-d8ec63f808ce
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558925417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ao
n_wake_resume.558925417
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.796946753
Short name T2638
Test name
Test status
Simulation time 152618910 ps
CPU time 0.87 seconds
Started Jul 27 07:38:36 PM PDT 24
Finished Jul 27 07:38:37 PM PDT 24
Peak memory 207104 kb
Host smart-c4a1f4fd-ff92-4aee-956e-337164d988ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79694
6753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.796946753
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2768965262
Short name T1459
Test name
Test status
Simulation time 166627121 ps
CPU time 0.92 seconds
Started Jul 27 07:38:35 PM PDT 24
Finished Jul 27 07:38:36 PM PDT 24
Peak memory 207116 kb
Host smart-afe673c7-3922-4a63-a903-b65a2999c246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27689
65262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2768965262
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.2870730266
Short name T618
Test name
Test status
Simulation time 303798982 ps
CPU time 1.16 seconds
Started Jul 27 07:38:35 PM PDT 24
Finished Jul 27 07:38:36 PM PDT 24
Peak memory 207120 kb
Host smart-6444a075-cff2-49d7-82b2-e3eecb155b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28707
30266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.2870730266
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.4203446920
Short name T1735
Test name
Test status
Simulation time 419636574 ps
CPU time 1.32 seconds
Started Jul 27 07:38:38 PM PDT 24
Finished Jul 27 07:38:40 PM PDT 24
Peak memory 207100 kb
Host smart-97650b00-3af9-44b7-9300-13ca270b993e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4203446920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.4203446920
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.3247200273
Short name T2048
Test name
Test status
Simulation time 7955437368 ps
CPU time 18.17 seconds
Started Jul 27 07:38:41 PM PDT 24
Finished Jul 27 07:38:59 PM PDT 24
Peak memory 207452 kb
Host smart-70808cf3-f0cc-48cf-97f4-d1baca556584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32472
00273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.3247200273
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.2398466374
Short name T2024
Test name
Test status
Simulation time 732129102 ps
CPU time 15.35 seconds
Started Jul 27 07:38:39 PM PDT 24
Finished Jul 27 07:38:54 PM PDT 24
Peak memory 207380 kb
Host smart-c6c36efd-9eb5-4185-a02d-7ca88785af6b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398466374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.2398466374
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.3939314749
Short name T290
Test name
Test status
Simulation time 502924601 ps
CPU time 1.59 seconds
Started Jul 27 07:38:40 PM PDT 24
Finished Jul 27 07:38:42 PM PDT 24
Peak memory 207164 kb
Host smart-8f78994a-f6b4-48bc-b67e-0573e00c1b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39393
14749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.3939314749
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1870288889
Short name T2475
Test name
Test status
Simulation time 137938393 ps
CPU time 0.85 seconds
Started Jul 27 07:38:37 PM PDT 24
Finished Jul 27 07:38:38 PM PDT 24
Peak memory 207056 kb
Host smart-7307267d-a386-45a7-9d64-57cb58fa3b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18702
88889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1870288889
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1782386451
Short name T1769
Test name
Test status
Simulation time 55770916 ps
CPU time 0.74 seconds
Started Jul 27 07:38:45 PM PDT 24
Finished Jul 27 07:38:46 PM PDT 24
Peak memory 207108 kb
Host smart-025ab9b5-afbd-4559-a14d-8bb27a4206a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17823
86451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1782386451
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1218868179
Short name T224
Test name
Test status
Simulation time 929639847 ps
CPU time 2.49 seconds
Started Jul 27 07:38:36 PM PDT 24
Finished Jul 27 07:38:38 PM PDT 24
Peak memory 207180 kb
Host smart-67b3469e-79f2-48ae-aa61-17d0521c6afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12188
68179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1218868179
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.4167191385
Short name T2180
Test name
Test status
Simulation time 185669286 ps
CPU time 2.25 seconds
Started Jul 27 07:38:37 PM PDT 24
Finished Jul 27 07:38:40 PM PDT 24
Peak memory 207344 kb
Host smart-a3037bf1-9fd8-4a12-bc98-9feeccba4d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41671
91385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.4167191385
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.230422845
Short name T355
Test name
Test status
Simulation time 239697842 ps
CPU time 1.1 seconds
Started Jul 27 07:38:38 PM PDT 24
Finished Jul 27 07:38:39 PM PDT 24
Peak memory 215532 kb
Host smart-14b73d1e-0dfd-42ce-88f5-80dd490eda06
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=230422845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.230422845
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.22634815
Short name T2586
Test name
Test status
Simulation time 202033672 ps
CPU time 0.89 seconds
Started Jul 27 07:38:36 PM PDT 24
Finished Jul 27 07:38:37 PM PDT 24
Peak memory 207060 kb
Host smart-bdfde788-c966-4a3b-a5eb-34f8c35763d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22634
815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.22634815
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1090942839
Short name T2389
Test name
Test status
Simulation time 216865402 ps
CPU time 0.99 seconds
Started Jul 27 07:38:46 PM PDT 24
Finished Jul 27 07:38:47 PM PDT 24
Peak memory 207144 kb
Host smart-35074306-1e75-43fa-b59a-e9fbb0b55445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10909
42839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1090942839
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.2061369633
Short name T1280
Test name
Test status
Simulation time 8403802194 ps
CPU time 246.63 seconds
Started Jul 27 07:38:38 PM PDT 24
Finished Jul 27 07:42:44 PM PDT 24
Peak memory 215552 kb
Host smart-90b3db99-6c71-48b5-a1c6-0e34a707083d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2061369633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.2061369633
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.459492423
Short name T2092
Test name
Test status
Simulation time 10357628161 ps
CPU time 72.66 seconds
Started Jul 27 07:38:37 PM PDT 24
Finished Jul 27 07:39:49 PM PDT 24
Peak memory 207300 kb
Host smart-66d4936a-35bc-42b1-89e2-252ca07f0095
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=459492423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.459492423
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.1177306951
Short name T2727
Test name
Test status
Simulation time 169193577 ps
CPU time 0.91 seconds
Started Jul 27 07:38:45 PM PDT 24
Finished Jul 27 07:38:46 PM PDT 24
Peak memory 207140 kb
Host smart-7ea4fdd0-2b59-4371-8553-d512bd27f11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11773
06951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.1177306951
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.2155846734
Short name T1853
Test name
Test status
Simulation time 23284471847 ps
CPU time 31.05 seconds
Started Jul 27 07:38:36 PM PDT 24
Finished Jul 27 07:39:07 PM PDT 24
Peak memory 207576 kb
Host smart-e05f3eb6-0cbd-47d2-8757-49f24ac18d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21558
46734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.2155846734
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1463982140
Short name T686
Test name
Test status
Simulation time 3337320242 ps
CPU time 4.89 seconds
Started Jul 27 07:38:41 PM PDT 24
Finished Jul 27 07:38:46 PM PDT 24
Peak memory 207380 kb
Host smart-c3b8ffcc-10fa-4b1d-b2b2-3c150fc0ae24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14639
82140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1463982140
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.2242457526
Short name T1672
Test name
Test status
Simulation time 5684858583 ps
CPU time 55.14 seconds
Started Jul 27 07:38:38 PM PDT 24
Finished Jul 27 07:39:33 PM PDT 24
Peak memory 217596 kb
Host smart-e9ae42a3-b5c4-45b1-b45c-6a4c5782549d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22424
57526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.2242457526
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.421398703
Short name T1334
Test name
Test status
Simulation time 6090515941 ps
CPU time 183.68 seconds
Started Jul 27 07:38:36 PM PDT 24
Finished Jul 27 07:41:40 PM PDT 24
Peak memory 215532 kb
Host smart-94ecd7ea-0a09-4a6c-8397-201928233ebe
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=421398703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.421398703
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.1656199426
Short name T1567
Test name
Test status
Simulation time 243831693 ps
CPU time 0.99 seconds
Started Jul 27 07:38:45 PM PDT 24
Finished Jul 27 07:38:47 PM PDT 24
Peak memory 207144 kb
Host smart-bbde4b2b-e846-4045-9b3c-fa3999a0eb07
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1656199426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1656199426
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3847616181
Short name T2241
Test name
Test status
Simulation time 188532811 ps
CPU time 0.93 seconds
Started Jul 27 07:38:42 PM PDT 24
Finished Jul 27 07:38:43 PM PDT 24
Peak memory 207120 kb
Host smart-8b6e3bdb-23a6-49f3-9d6e-a32ed5a3a92d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38476
16181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3847616181
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3645503629
Short name T2623
Test name
Test status
Simulation time 3912482723 ps
CPU time 37.65 seconds
Started Jul 27 07:38:41 PM PDT 24
Finished Jul 27 07:39:19 PM PDT 24
Peak memory 216940 kb
Host smart-8ae7aba5-71c6-4b99-9c57-2352a056cc4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36455
03629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3645503629
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.3515091825
Short name T1521
Test name
Test status
Simulation time 4734782589 ps
CPU time 133.81 seconds
Started Jul 27 07:38:41 PM PDT 24
Finished Jul 27 07:40:55 PM PDT 24
Peak memory 215584 kb
Host smart-4da031ae-4bb1-4c97-9b4b-1fc243449ace
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3515091825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3515091825
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.301527899
Short name T2230
Test name
Test status
Simulation time 161534376 ps
CPU time 0.9 seconds
Started Jul 27 07:38:42 PM PDT 24
Finished Jul 27 07:38:44 PM PDT 24
Peak memory 207100 kb
Host smart-a4b8c33f-42ef-4b2a-92a2-a3d04b9368f3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=301527899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.301527899
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3556695395
Short name T2562
Test name
Test status
Simulation time 142385233 ps
CPU time 0.84 seconds
Started Jul 27 07:38:42 PM PDT 24
Finished Jul 27 07:38:43 PM PDT 24
Peak memory 207136 kb
Host smart-d2237787-2be8-4785-b18c-64d346131452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35566
95395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3556695395
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.4201026569
Short name T2190
Test name
Test status
Simulation time 170758709 ps
CPU time 0.91 seconds
Started Jul 27 07:38:44 PM PDT 24
Finished Jul 27 07:38:46 PM PDT 24
Peak memory 207052 kb
Host smart-703c8f32-2686-46c4-8f6b-7f8378152cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42010
26569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.4201026569
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.2990713080
Short name T1123
Test name
Test status
Simulation time 186819219 ps
CPU time 0.9 seconds
Started Jul 27 07:38:42 PM PDT 24
Finished Jul 27 07:38:44 PM PDT 24
Peak memory 207060 kb
Host smart-28f0dfc1-fe45-4613-b276-64bb28c2ac42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29907
13080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2990713080
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.895438167
Short name T1084
Test name
Test status
Simulation time 187337464 ps
CPU time 0.89 seconds
Started Jul 27 07:38:42 PM PDT 24
Finished Jul 27 07:38:43 PM PDT 24
Peak memory 207068 kb
Host smart-867bbe08-4179-4a28-9bdd-0f1e225399a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89543
8167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.895438167
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.4238771031
Short name T1566
Test name
Test status
Simulation time 191797504 ps
CPU time 0.91 seconds
Started Jul 27 07:38:42 PM PDT 24
Finished Jul 27 07:38:44 PM PDT 24
Peak memory 207100 kb
Host smart-a1f6618c-66bd-48e0-845b-0caada9fed71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42387
71031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.4238771031
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3509030386
Short name T1532
Test name
Test status
Simulation time 157379618 ps
CPU time 0.84 seconds
Started Jul 27 07:38:44 PM PDT 24
Finished Jul 27 07:38:45 PM PDT 24
Peak memory 207156 kb
Host smart-2ca508eb-7ffd-47fd-aaf0-f5c1298626b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35090
30386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3509030386
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.2936270131
Short name T470
Test name
Test status
Simulation time 241710855 ps
CPU time 1.01 seconds
Started Jul 27 07:38:42 PM PDT 24
Finished Jul 27 07:38:44 PM PDT 24
Peak memory 207104 kb
Host smart-ad3926cc-aa5a-450e-ba67-abe09774ac57
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2936270131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.2936270131
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2972885333
Short name T19
Test name
Test status
Simulation time 149298122 ps
CPU time 0.81 seconds
Started Jul 27 07:38:43 PM PDT 24
Finished Jul 27 07:38:44 PM PDT 24
Peak memory 207032 kb
Host smart-013a33a6-82a8-485a-99f7-9f4eac0d1830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29728
85333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2972885333
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.838780069
Short name T1669
Test name
Test status
Simulation time 36473069 ps
CPU time 0.69 seconds
Started Jul 27 07:38:48 PM PDT 24
Finished Jul 27 07:38:49 PM PDT 24
Peak memory 207108 kb
Host smart-c5f3f3d1-f242-4c86-9c9b-491497f9c14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83878
0069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.838780069
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2482319167
Short name T277
Test name
Test status
Simulation time 6058006501 ps
CPU time 15.05 seconds
Started Jul 27 07:38:42 PM PDT 24
Finished Jul 27 07:38:57 PM PDT 24
Peak memory 223704 kb
Host smart-161bdade-81af-4551-8274-01cd7835c54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24823
19167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2482319167
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3494019488
Short name T2822
Test name
Test status
Simulation time 175833075 ps
CPU time 0.88 seconds
Started Jul 27 07:38:42 PM PDT 24
Finished Jul 27 07:38:42 PM PDT 24
Peak memory 207012 kb
Host smart-d9547c83-d23d-4413-9f59-5da32d75e2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34940
19488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3494019488
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3314693736
Short name T2433
Test name
Test status
Simulation time 177233154 ps
CPU time 0.91 seconds
Started Jul 27 07:38:43 PM PDT 24
Finished Jul 27 07:38:44 PM PDT 24
Peak memory 207128 kb
Host smart-ded2d0e2-bed3-431f-bdf0-e979a332d385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33146
93736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3314693736
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2089841014
Short name T1136
Test name
Test status
Simulation time 262780983 ps
CPU time 1.03 seconds
Started Jul 27 07:38:40 PM PDT 24
Finished Jul 27 07:38:41 PM PDT 24
Peak memory 207024 kb
Host smart-289f7efc-bbb8-42f9-bb62-92417de51698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898
41014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2089841014
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3818747176
Short name T2844
Test name
Test status
Simulation time 188078479 ps
CPU time 0.88 seconds
Started Jul 27 07:38:42 PM PDT 24
Finished Jul 27 07:38:44 PM PDT 24
Peak memory 207096 kb
Host smart-b9f33c4a-fe57-40b1-8096-4b96148464f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38187
47176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3818747176
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1900581797
Short name T2113
Test name
Test status
Simulation time 172870515 ps
CPU time 0.89 seconds
Started Jul 27 07:38:41 PM PDT 24
Finished Jul 27 07:38:42 PM PDT 24
Peak memory 207136 kb
Host smart-aba62e20-69e7-4f1c-b05a-6a1b90839a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19005
81797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1900581797
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.763097471
Short name T1205
Test name
Test status
Simulation time 151131142 ps
CPU time 0.9 seconds
Started Jul 27 07:38:43 PM PDT 24
Finished Jul 27 07:38:44 PM PDT 24
Peak memory 207040 kb
Host smart-cdfc8e3e-f0ed-43b0-b427-869a631c74d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76309
7471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.763097471
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.473485197
Short name T21
Test name
Test status
Simulation time 148822313 ps
CPU time 0.84 seconds
Started Jul 27 07:38:42 PM PDT 24
Finished Jul 27 07:38:43 PM PDT 24
Peak memory 207072 kb
Host smart-cbc0aa36-bb88-4455-baec-3bfdf6cd123b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47348
5197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.473485197
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2059553463
Short name T1899
Test name
Test status
Simulation time 263602293 ps
CPU time 1.08 seconds
Started Jul 27 07:38:42 PM PDT 24
Finished Jul 27 07:38:43 PM PDT 24
Peak memory 207328 kb
Host smart-29402688-9042-42e1-bd4f-ad8a6dd762b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20595
53463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2059553463
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.578010945
Short name T1764
Test name
Test status
Simulation time 5016851870 ps
CPU time 51.52 seconds
Started Jul 27 07:38:46 PM PDT 24
Finished Jul 27 07:39:38 PM PDT 24
Peak memory 217100 kb
Host smart-7ebd448d-504c-4a07-935f-78aa8a5bbd1b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=578010945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.578010945
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3689357039
Short name T2422
Test name
Test status
Simulation time 174291864 ps
CPU time 0.92 seconds
Started Jul 27 07:38:44 PM PDT 24
Finished Jul 27 07:38:45 PM PDT 24
Peak memory 207140 kb
Host smart-1994b9d6-9785-48fa-b977-ee85de8a6a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36893
57039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3689357039
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.1239815838
Short name T1001
Test name
Test status
Simulation time 223510397 ps
CPU time 0.94 seconds
Started Jul 27 07:38:43 PM PDT 24
Finished Jul 27 07:38:44 PM PDT 24
Peak memory 207136 kb
Host smart-1d4750e6-dba9-430b-83e3-a6109160878c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12398
15838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1239815838
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.4159007705
Short name T1159
Test name
Test status
Simulation time 331642026 ps
CPU time 1.21 seconds
Started Jul 27 07:38:43 PM PDT 24
Finished Jul 27 07:38:45 PM PDT 24
Peak memory 207004 kb
Host smart-d4b55a76-21ce-455c-a9cf-95c4322d75ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41590
07705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.4159007705
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.121932653
Short name T859
Test name
Test status
Simulation time 7441837902 ps
CPU time 220.72 seconds
Started Jul 27 07:38:41 PM PDT 24
Finished Jul 27 07:42:21 PM PDT 24
Peak memory 215592 kb
Host smart-6aa841e3-3036-44dd-991b-6444a1d6f8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12193
2653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.121932653
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.4059762377
Short name T1519
Test name
Test status
Simulation time 757408253 ps
CPU time 15.58 seconds
Started Jul 27 07:38:41 PM PDT 24
Finished Jul 27 07:38:56 PM PDT 24
Peak memory 207360 kb
Host smart-10e24d7b-da8f-4cbf-a811-384d09016a3b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059762377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.4059762377
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.1078212907
Short name T896
Test name
Test status
Simulation time 72517291 ps
CPU time 0.68 seconds
Started Jul 27 07:38:56 PM PDT 24
Finished Jul 27 07:38:56 PM PDT 24
Peak memory 207104 kb
Host smart-559af0b3-17ba-44a1-a33d-80b1308ac0b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1078212907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.1078212907
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.1565980472
Short name T1760
Test name
Test status
Simulation time 3483415246 ps
CPU time 5.03 seconds
Started Jul 27 07:38:45 PM PDT 24
Finished Jul 27 07:38:51 PM PDT 24
Peak memory 207428 kb
Host smart-38cb3cab-a29b-4cec-aecc-1afd1bbbf2f8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565980472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.1565980472
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.191056091
Short name T1152
Test name
Test status
Simulation time 13423621579 ps
CPU time 15.9 seconds
Started Jul 27 07:38:41 PM PDT 24
Finished Jul 27 07:38:57 PM PDT 24
Peak memory 207404 kb
Host smart-9de675f2-7700-4d77-9f32-d0e502f82ecd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=191056091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.191056091
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3471440169
Short name T1894
Test name
Test status
Simulation time 23365549002 ps
CPU time 29.89 seconds
Started Jul 27 07:38:51 PM PDT 24
Finished Jul 27 07:39:22 PM PDT 24
Peak memory 207388 kb
Host smart-ee303c4e-0660-4243-a916-448d56445495
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471440169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.3471440169
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1061170552
Short name T1596
Test name
Test status
Simulation time 179319614 ps
CPU time 0.95 seconds
Started Jul 27 07:38:49 PM PDT 24
Finished Jul 27 07:38:50 PM PDT 24
Peak memory 207208 kb
Host smart-37aea37d-5479-473a-bb0a-823c48685a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10611
70552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1061170552
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3024926333
Short name T673
Test name
Test status
Simulation time 147226726 ps
CPU time 0.86 seconds
Started Jul 27 07:38:49 PM PDT 24
Finished Jul 27 07:38:50 PM PDT 24
Peak memory 207092 kb
Host smart-fff16c07-c6f5-4d96-9a3f-15b65626e2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30249
26333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3024926333
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.54929394
Short name T1715
Test name
Test status
Simulation time 373008442 ps
CPU time 1.42 seconds
Started Jul 27 07:38:53 PM PDT 24
Finished Jul 27 07:38:55 PM PDT 24
Peak memory 207104 kb
Host smart-f382e7bf-424b-4064-8952-e5c071649902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54929
394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.54929394
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.901400818
Short name T2468
Test name
Test status
Simulation time 878030879 ps
CPU time 2.25 seconds
Started Jul 27 07:38:51 PM PDT 24
Finished Jul 27 07:38:54 PM PDT 24
Peak memory 207324 kb
Host smart-1cbcd414-bfa8-4add-adc2-a8d5d5f31037
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=901400818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.901400818
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.3794475379
Short name T2486
Test name
Test status
Simulation time 9785170467 ps
CPU time 22.65 seconds
Started Jul 27 07:38:50 PM PDT 24
Finished Jul 27 07:39:13 PM PDT 24
Peak memory 207336 kb
Host smart-14d0ac1f-f07c-4bbb-bd02-4d97f78c2bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37944
75379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.3794475379
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.3321340324
Short name T1487
Test name
Test status
Simulation time 1098896925 ps
CPU time 26.17 seconds
Started Jul 27 07:38:50 PM PDT 24
Finished Jul 27 07:39:16 PM PDT 24
Peak memory 207376 kb
Host smart-e2b7db84-6147-4c84-ae5a-1ea9ae9cf71a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321340324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.3321340324
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2935055785
Short name T2229
Test name
Test status
Simulation time 484467826 ps
CPU time 1.55 seconds
Started Jul 27 07:38:53 PM PDT 24
Finished Jul 27 07:38:54 PM PDT 24
Peak memory 207072 kb
Host smart-aca700b3-475e-496e-a43d-9e9d82a6ff8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29350
55785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2935055785
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.454470820
Short name T1510
Test name
Test status
Simulation time 193979296 ps
CPU time 0.83 seconds
Started Jul 27 07:38:48 PM PDT 24
Finished Jul 27 07:38:49 PM PDT 24
Peak memory 207084 kb
Host smart-7b2cb7a5-2c82-46cc-aa45-c0060083f12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45447
0820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.454470820
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2531653822
Short name T2089
Test name
Test status
Simulation time 109613357 ps
CPU time 0.75 seconds
Started Jul 27 07:38:52 PM PDT 24
Finished Jul 27 07:38:53 PM PDT 24
Peak memory 206972 kb
Host smart-03f9b4b1-229b-494b-ac72-8b61556b0f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25316
53822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2531653822
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.3700017566
Short name T480
Test name
Test status
Simulation time 865213425 ps
CPU time 2.27 seconds
Started Jul 27 07:39:03 PM PDT 24
Finished Jul 27 07:39:05 PM PDT 24
Peak memory 207368 kb
Host smart-a93c49dd-911b-4022-b66a-d85f15045fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37000
17566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.3700017566
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2062248912
Short name T1638
Test name
Test status
Simulation time 159719329 ps
CPU time 1.29 seconds
Started Jul 27 07:38:50 PM PDT 24
Finished Jul 27 07:38:51 PM PDT 24
Peak memory 207260 kb
Host smart-9e565ec1-dea5-4ae3-a981-bd6a43953d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20622
48912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2062248912
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1692086695
Short name T2030
Test name
Test status
Simulation time 180226086 ps
CPU time 0.96 seconds
Started Jul 27 07:38:51 PM PDT 24
Finished Jul 27 07:38:52 PM PDT 24
Peak memory 207284 kb
Host smart-9a810e3e-82cb-46aa-a3c7-ed2a03bc8ab9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1692086695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1692086695
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1305329912
Short name T1755
Test name
Test status
Simulation time 147696529 ps
CPU time 0.83 seconds
Started Jul 27 07:38:49 PM PDT 24
Finished Jul 27 07:38:50 PM PDT 24
Peak memory 207096 kb
Host smart-de3620cd-7c79-4914-b92c-5a312d9da65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13053
29912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1305329912
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2825707949
Short name T2044
Test name
Test status
Simulation time 237665376 ps
CPU time 0.99 seconds
Started Jul 27 07:39:03 PM PDT 24
Finished Jul 27 07:39:04 PM PDT 24
Peak memory 207128 kb
Host smart-97469025-bbff-40b5-ba9a-7659b0204a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28257
07949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2825707949
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.3801032805
Short name T1160
Test name
Test status
Simulation time 10209952299 ps
CPU time 77.47 seconds
Started Jul 27 07:38:50 PM PDT 24
Finished Jul 27 07:40:08 PM PDT 24
Peak memory 215564 kb
Host smart-42631eca-d20c-4acb-9428-6ce232545393
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3801032805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3801032805
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.2981030911
Short name T742
Test name
Test status
Simulation time 13060164247 ps
CPU time 93.13 seconds
Started Jul 27 07:38:55 PM PDT 24
Finished Jul 27 07:40:28 PM PDT 24
Peak memory 207348 kb
Host smart-06585e03-6feb-4431-8e46-0346918873f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2981030911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.2981030911
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.2387517178
Short name T2403
Test name
Test status
Simulation time 220602606 ps
CPU time 0.93 seconds
Started Jul 27 07:38:53 PM PDT 24
Finished Jul 27 07:38:54 PM PDT 24
Peak memory 207192 kb
Host smart-b95f7c5d-362d-47a7-9ead-6a9deaf0860b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23875
17178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.2387517178
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.223621753
Short name T369
Test name
Test status
Simulation time 23358850510 ps
CPU time 27.91 seconds
Started Jul 27 07:38:52 PM PDT 24
Finished Jul 27 07:39:20 PM PDT 24
Peak memory 207380 kb
Host smart-a0b9b02d-bc5c-4536-a0af-514c755207fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22362
1753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.223621753
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1176537981
Short name T2789
Test name
Test status
Simulation time 3371542526 ps
CPU time 5.06 seconds
Started Jul 27 07:38:53 PM PDT 24
Finished Jul 27 07:38:58 PM PDT 24
Peak memory 207456 kb
Host smart-8860c0c0-7694-4c86-8f36-fb8f8b6907b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11765
37981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1176537981
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3786432168
Short name T335
Test name
Test status
Simulation time 8815994661 ps
CPU time 90.26 seconds
Started Jul 27 07:38:51 PM PDT 24
Finished Jul 27 07:40:21 PM PDT 24
Peak memory 217756 kb
Host smart-05b64a3c-f143-44f9-83c0-f5cee06ee058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37864
32168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3786432168
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.3287645856
Short name T2242
Test name
Test status
Simulation time 5215632470 ps
CPU time 43.74 seconds
Started Jul 27 07:38:50 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 215556 kb
Host smart-c5699c70-2fc4-4ce7-b209-17605140930d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3287645856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.3287645856
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3289688090
Short name T2519
Test name
Test status
Simulation time 326219583 ps
CPU time 1.18 seconds
Started Jul 27 07:39:03 PM PDT 24
Finished Jul 27 07:39:04 PM PDT 24
Peak memory 207136 kb
Host smart-7d2cae9b-ca03-43bf-a06a-a18528ff4ad3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3289688090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3289688090
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.894259198
Short name T1268
Test name
Test status
Simulation time 191471110 ps
CPU time 0.91 seconds
Started Jul 27 07:38:50 PM PDT 24
Finished Jul 27 07:38:51 PM PDT 24
Peak memory 207104 kb
Host smart-38ebf619-36c7-4289-b4ea-0c60a4b6eece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89425
9198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.894259198
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.3368331157
Short name T2718
Test name
Test status
Simulation time 3262688203 ps
CPU time 23.58 seconds
Started Jul 27 07:38:53 PM PDT 24
Finished Jul 27 07:39:17 PM PDT 24
Peak memory 217020 kb
Host smart-d1bba9be-9875-4613-b171-38f102166dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33683
31157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.3368331157
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.1069240604
Short name T1016
Test name
Test status
Simulation time 7966772422 ps
CPU time 63.95 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:40:06 PM PDT 24
Peak memory 207348 kb
Host smart-a0a8177c-2a37-4adb-b3db-2e578d8814a5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1069240604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.1069240604
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.2094434948
Short name T2268
Test name
Test status
Simulation time 182279274 ps
CPU time 0.88 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:39:03 PM PDT 24
Peak memory 207136 kb
Host smart-f6d24880-366b-4528-9588-264a96122ba1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2094434948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2094434948
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.755872989
Short name T1707
Test name
Test status
Simulation time 170244921 ps
CPU time 0.85 seconds
Started Jul 27 07:38:51 PM PDT 24
Finished Jul 27 07:38:52 PM PDT 24
Peak memory 207332 kb
Host smart-648b601b-fc7c-4126-b358-f315e2c50f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75587
2989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.755872989
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.763323249
Short name T2452
Test name
Test status
Simulation time 210835584 ps
CPU time 0.96 seconds
Started Jul 27 07:38:51 PM PDT 24
Finished Jul 27 07:38:52 PM PDT 24
Peak memory 207112 kb
Host smart-62229ca8-bc25-4c68-9ec5-05cb64935635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76332
3249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.763323249
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3804959166
Short name T2768
Test name
Test status
Simulation time 199630592 ps
CPU time 0.94 seconds
Started Jul 27 07:38:50 PM PDT 24
Finished Jul 27 07:38:52 PM PDT 24
Peak memory 207092 kb
Host smart-4407df10-8184-4236-8509-e8d3ac325872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38049
59166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3804959166
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2183613956
Short name T2429
Test name
Test status
Simulation time 180604853 ps
CPU time 0.98 seconds
Started Jul 27 07:38:52 PM PDT 24
Finished Jul 27 07:38:53 PM PDT 24
Peak memory 207064 kb
Host smart-854b62de-3281-4954-8dc3-0dd7a7c2ae00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21836
13956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2183613956
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2566696745
Short name T750
Test name
Test status
Simulation time 168075069 ps
CPU time 0.86 seconds
Started Jul 27 07:38:49 PM PDT 24
Finished Jul 27 07:38:50 PM PDT 24
Peak memory 206992 kb
Host smart-4a0b1434-3772-4531-9172-a706fd2477ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25666
96745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2566696745
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1964400906
Short name T178
Test name
Test status
Simulation time 150740011 ps
CPU time 0.85 seconds
Started Jul 27 07:38:50 PM PDT 24
Finished Jul 27 07:38:51 PM PDT 24
Peak memory 207100 kb
Host smart-6aa79edb-0d2b-418e-bb52-4a92fe81d173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19644
00906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1964400906
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.3559138082
Short name T2634
Test name
Test status
Simulation time 271446194 ps
CPU time 1.03 seconds
Started Jul 27 07:38:50 PM PDT 24
Finished Jul 27 07:38:51 PM PDT 24
Peak memory 207136 kb
Host smart-98c0c06a-9eff-4de6-850d-e4acd1e113f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3559138082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.3559138082
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.999919407
Short name T596
Test name
Test status
Simulation time 146507855 ps
CPU time 0.91 seconds
Started Jul 27 07:38:51 PM PDT 24
Finished Jul 27 07:38:52 PM PDT 24
Peak memory 207132 kb
Host smart-24109635-7671-4319-bb31-f1cd9d6eab55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99991
9407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.999919407
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1430368040
Short name T1288
Test name
Test status
Simulation time 47303034 ps
CPU time 0.7 seconds
Started Jul 27 07:38:53 PM PDT 24
Finished Jul 27 07:38:54 PM PDT 24
Peak memory 207204 kb
Host smart-2bb85e84-d24a-4260-834c-32bec17be16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14303
68040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1430368040
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3593665259
Short name T278
Test name
Test status
Simulation time 5855324251 ps
CPU time 15.97 seconds
Started Jul 27 07:39:03 PM PDT 24
Finished Jul 27 07:39:19 PM PDT 24
Peak memory 215664 kb
Host smart-cc16c897-07a3-4f6f-a46a-323148fad005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35936
65259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3593665259
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1172989371
Short name T1169
Test name
Test status
Simulation time 170646317 ps
CPU time 0.89 seconds
Started Jul 27 07:38:49 PM PDT 24
Finished Jul 27 07:38:51 PM PDT 24
Peak memory 207112 kb
Host smart-ea21b6e5-45bd-41fe-bdaf-9e1e7aa3da1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11729
89371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1172989371
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.737069884
Short name T16
Test name
Test status
Simulation time 206034279 ps
CPU time 0.99 seconds
Started Jul 27 07:39:03 PM PDT 24
Finished Jul 27 07:39:04 PM PDT 24
Peak memory 207108 kb
Host smart-cdfa1c57-3da6-45ab-9c5c-ad9fad8df295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73706
9884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.737069884
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.483751912
Short name T2171
Test name
Test status
Simulation time 152679807 ps
CPU time 0.86 seconds
Started Jul 27 07:38:50 PM PDT 24
Finished Jul 27 07:38:51 PM PDT 24
Peak memory 207140 kb
Host smart-60321706-2b77-4431-a923-1b3cc9a8c197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48375
1912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.483751912
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.1531514490
Short name T1272
Test name
Test status
Simulation time 212277730 ps
CPU time 0.97 seconds
Started Jul 27 07:38:50 PM PDT 24
Finished Jul 27 07:38:52 PM PDT 24
Peak memory 207220 kb
Host smart-5277ae3b-e9eb-4fd7-8790-672beb249fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15315
14490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.1531514490
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2881111460
Short name T1285
Test name
Test status
Simulation time 163408360 ps
CPU time 0.84 seconds
Started Jul 27 07:38:52 PM PDT 24
Finished Jul 27 07:38:53 PM PDT 24
Peak memory 207032 kb
Host smart-da8773c4-8287-4250-996b-d7139662080f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28811
11460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2881111460
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2075527181
Short name T2437
Test name
Test status
Simulation time 208153589 ps
CPU time 0.92 seconds
Started Jul 27 07:38:50 PM PDT 24
Finished Jul 27 07:38:51 PM PDT 24
Peak memory 207040 kb
Host smart-1d78e916-d1cf-465b-9c23-274cb9471dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20755
27181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2075527181
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.78134493
Short name T684
Test name
Test status
Simulation time 150472932 ps
CPU time 0.82 seconds
Started Jul 27 07:38:58 PM PDT 24
Finished Jul 27 07:38:59 PM PDT 24
Peak memory 207140 kb
Host smart-9bbb87bf-cbca-4aaa-b455-0e205d79b061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78134
493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.78134493
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1305689847
Short name T2013
Test name
Test status
Simulation time 216638498 ps
CPU time 0.98 seconds
Started Jul 27 07:38:55 PM PDT 24
Finished Jul 27 07:38:56 PM PDT 24
Peak memory 207140 kb
Host smart-e0c32598-b1c5-470e-b4c7-d8620a2787c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13056
89847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1305689847
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2310626381
Short name T1086
Test name
Test status
Simulation time 174558034 ps
CPU time 0.9 seconds
Started Jul 27 07:38:56 PM PDT 24
Finished Jul 27 07:38:57 PM PDT 24
Peak memory 207140 kb
Host smart-01c915d0-2a11-4a6e-afa7-bf0ee56d1ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23106
26381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2310626381
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3189421071
Short name T590
Test name
Test status
Simulation time 163764718 ps
CPU time 0.89 seconds
Started Jul 27 07:38:59 PM PDT 24
Finished Jul 27 07:39:00 PM PDT 24
Peak memory 207144 kb
Host smart-651a0604-a424-404e-804a-51ac6ac5abc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31894
21071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3189421071
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.3388559347
Short name T1305
Test name
Test status
Simulation time 191544928 ps
CPU time 1.04 seconds
Started Jul 27 07:38:58 PM PDT 24
Finished Jul 27 07:38:59 PM PDT 24
Peak memory 207104 kb
Host smart-1af2eba6-58a0-48c5-b5af-a1e867b20076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33885
59347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.3388559347
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.4149988058
Short name T2211
Test name
Test status
Simulation time 4518337469 ps
CPU time 46.42 seconds
Started Jul 27 07:39:01 PM PDT 24
Finished Jul 27 07:39:48 PM PDT 24
Peak memory 216668 kb
Host smart-c6eb414d-6f9d-4145-a90c-3e7715273e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41499
88058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.4149988058
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.2703932317
Short name T2040
Test name
Test status
Simulation time 717498676 ps
CPU time 15.54 seconds
Started Jul 27 07:38:51 PM PDT 24
Finished Jul 27 07:39:07 PM PDT 24
Peak memory 207324 kb
Host smart-10776c42-a520-428b-9532-43d6023567d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703932317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.2703932317
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.3697176875
Short name T2856
Test name
Test status
Simulation time 77439649 ps
CPU time 0.71 seconds
Started Jul 27 07:39:03 PM PDT 24
Finished Jul 27 07:39:04 PM PDT 24
Peak memory 207136 kb
Host smart-85a4a0a3-8eb5-4299-a36e-47e163ea304b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3697176875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.3697176875
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.865521306
Short name T438
Test name
Test status
Simulation time 4410930517 ps
CPU time 7.18 seconds
Started Jul 27 07:39:00 PM PDT 24
Finished Jul 27 07:39:07 PM PDT 24
Peak memory 207364 kb
Host smart-19169efa-b1a4-43c1-9655-7eefa81ed72a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865521306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ao
n_wake_disconnect.865521306
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.3007173063
Short name T2244
Test name
Test status
Simulation time 13379487850 ps
CPU time 14.63 seconds
Started Jul 27 07:39:00 PM PDT 24
Finished Jul 27 07:39:14 PM PDT 24
Peak memory 207360 kb
Host smart-56bd2a63-fdcd-4e66-961b-e6516310c5fd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007173063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.3007173063
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.3313901454
Short name T2116
Test name
Test status
Simulation time 23318613958 ps
CPU time 28.76 seconds
Started Jul 27 07:38:59 PM PDT 24
Finished Jul 27 07:39:28 PM PDT 24
Peak memory 207384 kb
Host smart-bcd8304d-ece3-404a-90f4-89a459217e08
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313901454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.3313901454
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1619666980
Short name T2038
Test name
Test status
Simulation time 230171093 ps
CPU time 0.94 seconds
Started Jul 27 07:38:55 PM PDT 24
Finished Jul 27 07:38:56 PM PDT 24
Peak memory 207092 kb
Host smart-40b4e18d-2d4c-4a53-84cd-a708c00a0f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16196
66980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1619666980
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.2204720106
Short name T1987
Test name
Test status
Simulation time 146079631 ps
CPU time 0.82 seconds
Started Jul 27 07:39:00 PM PDT 24
Finished Jul 27 07:39:01 PM PDT 24
Peak memory 207080 kb
Host smart-5bcf8c53-2497-4ea2-9d4c-78cc403c4c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22047
20106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.2204720106
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1198776700
Short name T796
Test name
Test status
Simulation time 254128649 ps
CPU time 1.04 seconds
Started Jul 27 07:38:57 PM PDT 24
Finished Jul 27 07:38:58 PM PDT 24
Peak memory 207108 kb
Host smart-690948f7-205b-4621-a15f-83d732fa9a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11987
76700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1198776700
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3835230820
Short name T2630
Test name
Test status
Simulation time 793112462 ps
CPU time 2.03 seconds
Started Jul 27 07:38:56 PM PDT 24
Finished Jul 27 07:38:58 PM PDT 24
Peak memory 207092 kb
Host smart-72475503-2152-44fa-b3fd-ad1cb8f88af6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3835230820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3835230820
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.1439418182
Short name T2127
Test name
Test status
Simulation time 14691912575 ps
CPU time 29.38 seconds
Started Jul 27 07:38:59 PM PDT 24
Finished Jul 27 07:39:28 PM PDT 24
Peak memory 207400 kb
Host smart-4f3930c5-fd4b-466e-93f0-14ce361771cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14394
18182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.1439418182
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.168534477
Short name T2279
Test name
Test status
Simulation time 1702704921 ps
CPU time 39.61 seconds
Started Jul 27 07:38:57 PM PDT 24
Finished Jul 27 07:39:37 PM PDT 24
Peak memory 207264 kb
Host smart-724fe757-a6b8-4037-a107-0123365c6751
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168534477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.168534477
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.2122835923
Short name T1634
Test name
Test status
Simulation time 413533588 ps
CPU time 1.41 seconds
Started Jul 27 07:39:03 PM PDT 24
Finished Jul 27 07:39:04 PM PDT 24
Peak memory 207092 kb
Host smart-b1296582-731a-4e46-a479-1fcd9c21aa53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21228
35923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.2122835923
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3015705501
Short name T2280
Test name
Test status
Simulation time 139908649 ps
CPU time 0.82 seconds
Started Jul 27 07:38:57 PM PDT 24
Finished Jul 27 07:38:58 PM PDT 24
Peak memory 207176 kb
Host smart-a015840d-d795-4a7c-8582-e00aa6be48ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30157
05501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3015705501
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.845867271
Short name T1281
Test name
Test status
Simulation time 52306378 ps
CPU time 0.71 seconds
Started Jul 27 07:38:55 PM PDT 24
Finished Jul 27 07:38:56 PM PDT 24
Peak memory 207060 kb
Host smart-52e2747a-b7c1-43b9-aa3b-1c3f38e1e88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84586
7271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.845867271
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1537970001
Short name T1186
Test name
Test status
Simulation time 933855734 ps
CPU time 2.59 seconds
Started Jul 27 07:38:58 PM PDT 24
Finished Jul 27 07:39:01 PM PDT 24
Peak memory 207428 kb
Host smart-28374659-0ea4-4c53-a450-ac010be111de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15379
70001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1537970001
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.4102243754
Short name T1111
Test name
Test status
Simulation time 332791353 ps
CPU time 2.34 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:39:05 PM PDT 24
Peak memory 207276 kb
Host smart-620c3fa5-bf2f-472f-94b7-b6de0796de0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41022
43754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.4102243754
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.415437066
Short name T2838
Test name
Test status
Simulation time 220831680 ps
CPU time 0.97 seconds
Started Jul 27 07:39:00 PM PDT 24
Finished Jul 27 07:39:01 PM PDT 24
Peak memory 207272 kb
Host smart-05c6b02f-251a-460d-87da-433f0e36e991
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=415437066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.415437066
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3056017593
Short name T1303
Test name
Test status
Simulation time 164623234 ps
CPU time 0.87 seconds
Started Jul 27 07:38:56 PM PDT 24
Finished Jul 27 07:38:57 PM PDT 24
Peak memory 207032 kb
Host smart-0b1f3589-3ee1-4dff-ae6b-01dac4d71b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30560
17593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3056017593
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2987045761
Short name T908
Test name
Test status
Simulation time 290372732 ps
CPU time 1.02 seconds
Started Jul 27 07:38:59 PM PDT 24
Finished Jul 27 07:39:00 PM PDT 24
Peak memory 207100 kb
Host smart-c2253ca3-277f-43b3-b433-29be99f530f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29870
45761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2987045761
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.2857123141
Short name T592
Test name
Test status
Simulation time 7503357771 ps
CPU time 219.43 seconds
Started Jul 27 07:39:00 PM PDT 24
Finished Jul 27 07:42:40 PM PDT 24
Peak memory 215544 kb
Host smart-fd0919a5-5749-4667-8298-a0a72ca9fa13
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2857123141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.2857123141
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.1548783078
Short name T1559
Test name
Test status
Simulation time 9652767644 ps
CPU time 73.14 seconds
Started Jul 27 07:38:58 PM PDT 24
Finished Jul 27 07:40:11 PM PDT 24
Peak memory 207352 kb
Host smart-dce5e134-618d-4312-813a-3d153079eb9f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1548783078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.1548783078
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3072046213
Short name T1744
Test name
Test status
Simulation time 222799871 ps
CPU time 0.99 seconds
Started Jul 27 07:38:59 PM PDT 24
Finished Jul 27 07:39:00 PM PDT 24
Peak memory 207112 kb
Host smart-12d95c01-1d3a-48a9-9920-1f96cd6bfaba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30720
46213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3072046213
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.4098133352
Short name T2560
Test name
Test status
Simulation time 23348003537 ps
CPU time 29.11 seconds
Started Jul 27 07:38:57 PM PDT 24
Finished Jul 27 07:39:26 PM PDT 24
Peak memory 207340 kb
Host smart-21345b9b-c9bf-42fd-8a33-bf0c387bb87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40981
33352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.4098133352
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.712269658
Short name T1363
Test name
Test status
Simulation time 3332112243 ps
CPU time 5.99 seconds
Started Jul 27 07:38:57 PM PDT 24
Finished Jul 27 07:39:03 PM PDT 24
Peak memory 207384 kb
Host smart-af202001-58f8-4660-b749-7b63cbdc90d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71226
9658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.712269658
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.3007843837
Short name T2418
Test name
Test status
Simulation time 6273332368 ps
CPU time 184.98 seconds
Started Jul 27 07:38:59 PM PDT 24
Finished Jul 27 07:42:04 PM PDT 24
Peak memory 215616 kb
Host smart-df6c2812-3d4f-481a-bb7c-e86fc1aba99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30078
43837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.3007843837
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.1597097667
Short name T1668
Test name
Test status
Simulation time 4001408490 ps
CPU time 115.13 seconds
Started Jul 27 07:39:00 PM PDT 24
Finished Jul 27 07:40:55 PM PDT 24
Peak memory 215568 kb
Host smart-1e56099a-fa01-42e3-a01a-87a84a4be6cf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1597097667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.1597097667
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.711070385
Short name T384
Test name
Test status
Simulation time 266832758 ps
CPU time 1.04 seconds
Started Jul 27 07:38:58 PM PDT 24
Finished Jul 27 07:38:59 PM PDT 24
Peak memory 207140 kb
Host smart-00e35f8b-034c-4dd5-a410-549cacef5a48
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=711070385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.711070385
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2669460423
Short name T479
Test name
Test status
Simulation time 196847516 ps
CPU time 0.98 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:39:03 PM PDT 24
Peak memory 207144 kb
Host smart-fb0fdd01-733c-48b8-a132-7ab8996bd4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26694
60423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2669460423
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.967977777
Short name T1674
Test name
Test status
Simulation time 5950994472 ps
CPU time 169.56 seconds
Started Jul 27 07:39:03 PM PDT 24
Finished Jul 27 07:41:53 PM PDT 24
Peak memory 215520 kb
Host smart-982d724f-51e2-43c8-ad09-afbae59874a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96797
7777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.967977777
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3991830678
Short name T2046
Test name
Test status
Simulation time 7540726342 ps
CPU time 220.88 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:42:43 PM PDT 24
Peak memory 215548 kb
Host smart-8b3a7e6d-2cde-4385-8094-c6be9788bf5a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3991830678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3991830678
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3546489902
Short name T1741
Test name
Test status
Simulation time 149807294 ps
CPU time 0.82 seconds
Started Jul 27 07:39:04 PM PDT 24
Finished Jul 27 07:39:05 PM PDT 24
Peak memory 207152 kb
Host smart-a3ef7536-9795-458e-a56e-18b086d18ce9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3546489902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3546489902
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3880913545
Short name T2233
Test name
Test status
Simulation time 171036062 ps
CPU time 0.86 seconds
Started Jul 27 07:39:06 PM PDT 24
Finished Jul 27 07:39:07 PM PDT 24
Peak memory 207136 kb
Host smart-2253ca88-cc77-439c-8154-67ffeb2928d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809
13545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3880913545
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.533569849
Short name T127
Test name
Test status
Simulation time 190660609 ps
CPU time 0.93 seconds
Started Jul 27 07:39:01 PM PDT 24
Finished Jul 27 07:39:02 PM PDT 24
Peak memory 207148 kb
Host smart-d9c3ae2e-44ef-4c73-9be0-134738ce1f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53356
9849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.533569849
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.40192063
Short name T675
Test name
Test status
Simulation time 207484942 ps
CPU time 0.94 seconds
Started Jul 27 07:39:01 PM PDT 24
Finished Jul 27 07:39:02 PM PDT 24
Peak memory 207104 kb
Host smart-fe3ec15f-dcf9-4e50-8c37-137d8755185e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40192
063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.40192063
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1218896016
Short name T2114
Test name
Test status
Simulation time 196110253 ps
CPU time 0.9 seconds
Started Jul 27 07:39:03 PM PDT 24
Finished Jul 27 07:39:04 PM PDT 24
Peak memory 207128 kb
Host smart-2dbdd388-3992-48b6-8b9c-feda0a8862e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12188
96016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1218896016
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1425004101
Short name T2714
Test name
Test status
Simulation time 189217012 ps
CPU time 0.91 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:39:03 PM PDT 24
Peak memory 207140 kb
Host smart-f663d76a-30bf-433f-964b-f23493e34162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14250
04101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1425004101
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.4165133149
Short name T640
Test name
Test status
Simulation time 157890115 ps
CPU time 0.84 seconds
Started Jul 27 07:39:04 PM PDT 24
Finished Jul 27 07:39:05 PM PDT 24
Peak memory 207128 kb
Host smart-359c05ea-0cae-4124-aa35-6ed3291da6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41651
33149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.4165133149
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.153677844
Short name T1355
Test name
Test status
Simulation time 174129263 ps
CPU time 0.96 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:39:03 PM PDT 24
Peak memory 207148 kb
Host smart-ce3c4e44-e26c-461b-9a78-a538fed8f1ba
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=153677844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.153677844
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.812797128
Short name T2018
Test name
Test status
Simulation time 171255866 ps
CPU time 0.84 seconds
Started Jul 27 07:39:00 PM PDT 24
Finished Jul 27 07:39:01 PM PDT 24
Peak memory 207132 kb
Host smart-a4e8c2c9-9d68-44d0-94b1-b8586238bcdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81279
7128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.812797128
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1928178891
Short name T25
Test name
Test status
Simulation time 118566051 ps
CPU time 0.8 seconds
Started Jul 27 07:39:05 PM PDT 24
Finished Jul 27 07:39:06 PM PDT 24
Peak memory 207108 kb
Host smart-26c178f7-fee3-41cc-b5d1-b68fe56e7e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19281
78891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1928178891
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2487002532
Short name T254
Test name
Test status
Simulation time 6949551545 ps
CPU time 16.55 seconds
Started Jul 27 07:39:03 PM PDT 24
Finished Jul 27 07:39:20 PM PDT 24
Peak memory 215612 kb
Host smart-dad25e74-93f4-4347-aed3-83c2d712207e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24870
02532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2487002532
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3126616231
Short name T2771
Test name
Test status
Simulation time 188722510 ps
CPU time 0.96 seconds
Started Jul 27 07:39:03 PM PDT 24
Finished Jul 27 07:39:04 PM PDT 24
Peak memory 207220 kb
Host smart-ae45ae74-4e38-486c-bf0d-7109bd69b1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31266
16231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3126616231
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1547768501
Short name T1736
Test name
Test status
Simulation time 176741894 ps
CPU time 0.86 seconds
Started Jul 27 07:39:04 PM PDT 24
Finished Jul 27 07:39:05 PM PDT 24
Peak memory 207148 kb
Host smart-6b28c335-10a9-4bfb-81f6-eb36dec892bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15477
68501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1547768501
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3461136350
Short name T537
Test name
Test status
Simulation time 184761877 ps
CPU time 0.9 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:39:03 PM PDT 24
Peak memory 207140 kb
Host smart-fef27a0e-b253-4c46-8646-61c00a386740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34611
36350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3461136350
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.4022693009
Short name T553
Test name
Test status
Simulation time 213761977 ps
CPU time 0.92 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:39:03 PM PDT 24
Peak memory 207108 kb
Host smart-ccd13562-cd85-4626-a219-a02920973c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40226
93009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.4022693009
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.2208730545
Short name T958
Test name
Test status
Simulation time 148828319 ps
CPU time 0.91 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:39:03 PM PDT 24
Peak memory 207068 kb
Host smart-6b30d580-ff02-4ad9-a250-6d6525161b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22087
30545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.2208730545
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.4077857112
Short name T1453
Test name
Test status
Simulation time 155270362 ps
CPU time 0.87 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:39:03 PM PDT 24
Peak memory 207064 kb
Host smart-ea4ef5e6-b57d-44ae-a3c5-3d0c41bbab45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40778
57112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.4077857112
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2225608243
Short name T414
Test name
Test status
Simulation time 177064900 ps
CPU time 0.91 seconds
Started Jul 27 07:39:01 PM PDT 24
Finished Jul 27 07:39:02 PM PDT 24
Peak memory 207144 kb
Host smart-f78b5253-3b69-47b2-98ee-00b67008ea1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22256
08243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2225608243
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1408537879
Short name T1730
Test name
Test status
Simulation time 197455764 ps
CPU time 0.99 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:39:03 PM PDT 24
Peak memory 207068 kb
Host smart-b67d79b0-318d-4d78-821c-e3122cc28d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14085
37879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1408537879
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.4057777636
Short name T917
Test name
Test status
Simulation time 4520526708 ps
CPU time 46.51 seconds
Started Jul 27 07:39:05 PM PDT 24
Finished Jul 27 07:39:51 PM PDT 24
Peak memory 217236 kb
Host smart-3a5c65ac-8441-4b10-8020-940f3af3faca
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4057777636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.4057777636
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.4254937989
Short name T2651
Test name
Test status
Simulation time 199414644 ps
CPU time 0.94 seconds
Started Jul 27 07:39:06 PM PDT 24
Finished Jul 27 07:39:07 PM PDT 24
Peak memory 207132 kb
Host smart-af39d153-f354-4557-bc51-8477d1e8b546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42549
37989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.4254937989
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.625024716
Short name T2207
Test name
Test status
Simulation time 150043307 ps
CPU time 0.86 seconds
Started Jul 27 07:39:03 PM PDT 24
Finished Jul 27 07:39:04 PM PDT 24
Peak memory 207108 kb
Host smart-29b0f567-2efb-4cd5-9b96-83d2273124cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62502
4716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.625024716
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1547917756
Short name T941
Test name
Test status
Simulation time 736747447 ps
CPU time 2.16 seconds
Started Jul 27 07:39:04 PM PDT 24
Finished Jul 27 07:39:06 PM PDT 24
Peak memory 207060 kb
Host smart-4a9dd2e3-06b2-4275-aa76-60cf64f1a52f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15479
17756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1547917756
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.3151467166
Short name T2107
Test name
Test status
Simulation time 4386543861 ps
CPU time 43.87 seconds
Started Jul 27 07:39:04 PM PDT 24
Finished Jul 27 07:39:48 PM PDT 24
Peak memory 216856 kb
Host smart-0ba1e0a9-12aa-425a-8b43-7418e70b9a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31514
67166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3151467166
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.524906927
Short name T2402
Test name
Test status
Simulation time 1338549461 ps
CPU time 9.28 seconds
Started Jul 27 07:38:56 PM PDT 24
Finished Jul 27 07:39:06 PM PDT 24
Peak memory 207272 kb
Host smart-f3f30531-90b8-4a42-b3ce-68eeaf5cd7de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524906927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_host
_handshake.524906927
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.221969037
Short name T924
Test name
Test status
Simulation time 80702094 ps
CPU time 0.72 seconds
Started Jul 27 07:39:22 PM PDT 24
Finished Jul 27 07:39:22 PM PDT 24
Peak memory 207128 kb
Host smart-9d4c0180-bba0-4883-a3e0-023fade227df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=221969037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.221969037
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1403262474
Short name T469
Test name
Test status
Simulation time 3948643522 ps
CPU time 5.76 seconds
Started Jul 27 07:39:08 PM PDT 24
Finished Jul 27 07:39:13 PM PDT 24
Peak memory 207364 kb
Host smart-897ed48a-c03f-41e5-a19a-d9737efd364c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403262474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.1403262474
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.519498529
Short name T961
Test name
Test status
Simulation time 23404573717 ps
CPU time 28.69 seconds
Started Jul 27 07:39:01 PM PDT 24
Finished Jul 27 07:39:30 PM PDT 24
Peak memory 207372 kb
Host smart-e3b726e2-9ef2-4ac6-9f3f-8d7f6a165aeb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519498529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_ao
n_wake_resume.519498529
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.625276523
Short name T710
Test name
Test status
Simulation time 236843470 ps
CPU time 0.99 seconds
Started Jul 27 07:39:04 PM PDT 24
Finished Jul 27 07:39:05 PM PDT 24
Peak memory 207124 kb
Host smart-8b20244b-614c-43aa-80aa-1cc3bdf2a95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62527
6523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.625276523
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.776818598
Short name T2445
Test name
Test status
Simulation time 159196934 ps
CPU time 0.85 seconds
Started Jul 27 07:39:02 PM PDT 24
Finished Jul 27 07:39:03 PM PDT 24
Peak memory 207080 kb
Host smart-71ae3279-c39d-41ca-b5b6-0e768d3fd4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77681
8598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.776818598
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.202369436
Short name T2751
Test name
Test status
Simulation time 198766666 ps
CPU time 0.96 seconds
Started Jul 27 07:39:08 PM PDT 24
Finished Jul 27 07:39:09 PM PDT 24
Peak memory 207132 kb
Host smart-9746e03a-c2bc-4e68-a606-eb9bafefe72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20236
9436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.202369436
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1489196817
Short name T646
Test name
Test status
Simulation time 1047277723 ps
CPU time 2.6 seconds
Started Jul 27 07:39:06 PM PDT 24
Finished Jul 27 07:39:09 PM PDT 24
Peak memory 207264 kb
Host smart-480cf15b-d4d7-43fd-83c4-d91e0f6fc386
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1489196817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1489196817
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.619719325
Short name T1653
Test name
Test status
Simulation time 17394626015 ps
CPU time 36.79 seconds
Started Jul 27 07:39:12 PM PDT 24
Finished Jul 27 07:39:49 PM PDT 24
Peak memory 207348 kb
Host smart-28fd1231-c6de-40f2-8d2d-c3acbeced841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61971
9325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.619719325
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.1816976848
Short name T2539
Test name
Test status
Simulation time 1612496475 ps
CPU time 38.78 seconds
Started Jul 27 07:39:10 PM PDT 24
Finished Jul 27 07:39:48 PM PDT 24
Peak memory 207284 kb
Host smart-70e159ba-c93b-421d-aaa7-1b43641aa75f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816976848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.1816976848
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.1896902278
Short name T766
Test name
Test status
Simulation time 367162562 ps
CPU time 1.29 seconds
Started Jul 27 07:39:08 PM PDT 24
Finished Jul 27 07:39:09 PM PDT 24
Peak memory 207108 kb
Host smart-ea5d2e88-4b81-4d2f-9d99-8c93dceba8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18969
02278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.1896902278
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.4028823379
Short name T1440
Test name
Test status
Simulation time 137069348 ps
CPU time 0.8 seconds
Started Jul 27 07:39:10 PM PDT 24
Finished Jul 27 07:39:11 PM PDT 24
Peak memory 207112 kb
Host smart-41edb7d1-1f57-4105-a243-12891979bf0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40288
23379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.4028823379
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3508867620
Short name T2746
Test name
Test status
Simulation time 48273525 ps
CPU time 0.72 seconds
Started Jul 27 07:39:09 PM PDT 24
Finished Jul 27 07:39:10 PM PDT 24
Peak memory 207104 kb
Host smart-04e56f4f-555a-4ec1-9af7-4689cd638ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35088
67620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3508867620
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1057925099
Short name T507
Test name
Test status
Simulation time 773385981 ps
CPU time 2.42 seconds
Started Jul 27 07:39:09 PM PDT 24
Finished Jul 27 07:39:11 PM PDT 24
Peak memory 207372 kb
Host smart-0688a949-b1b9-4156-9b64-28ffdb0d7fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10579
25099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1057925099
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.528884438
Short name T2428
Test name
Test status
Simulation time 191768581 ps
CPU time 2.13 seconds
Started Jul 27 07:39:06 PM PDT 24
Finished Jul 27 07:39:09 PM PDT 24
Peak memory 207316 kb
Host smart-2052db34-6859-4b55-9e6b-a93bf0237f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52888
4438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.528884438
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2337286263
Short name T2226
Test name
Test status
Simulation time 210552680 ps
CPU time 1.1 seconds
Started Jul 27 07:39:09 PM PDT 24
Finished Jul 27 07:39:10 PM PDT 24
Peak memory 207236 kb
Host smart-fcaf6a25-edb7-4c15-8712-91f65e842b8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2337286263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2337286263
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2651779196
Short name T368
Test name
Test status
Simulation time 152274216 ps
CPU time 0.83 seconds
Started Jul 27 07:39:07 PM PDT 24
Finished Jul 27 07:39:08 PM PDT 24
Peak memory 207164 kb
Host smart-b40231be-b49a-440e-b2d5-3add91539061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26517
79196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2651779196
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.567424005
Short name T1277
Test name
Test status
Simulation time 224472977 ps
CPU time 0.96 seconds
Started Jul 27 07:39:08 PM PDT 24
Finished Jul 27 07:39:09 PM PDT 24
Peak memory 207116 kb
Host smart-37b6d812-9843-4431-83c7-2742a4228b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56742
4005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.567424005
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.2149361088
Short name T1375
Test name
Test status
Simulation time 9589354471 ps
CPU time 74.2 seconds
Started Jul 27 07:39:10 PM PDT 24
Finished Jul 27 07:40:25 PM PDT 24
Peak memory 215492 kb
Host smart-018ce743-b028-49e9-a47e-f1cc98ae9d0d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2149361088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.2149361088
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.2088150159
Short name T2193
Test name
Test status
Simulation time 14242148891 ps
CPU time 111.47 seconds
Started Jul 27 07:39:09 PM PDT 24
Finished Jul 27 07:41:01 PM PDT 24
Peak memory 207380 kb
Host smart-02ac34c9-990f-4fca-9dd6-b9c920078967
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2088150159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.2088150159
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.4160231096
Short name T1092
Test name
Test status
Simulation time 206431244 ps
CPU time 0.98 seconds
Started Jul 27 07:39:12 PM PDT 24
Finished Jul 27 07:39:13 PM PDT 24
Peak memory 207108 kb
Host smart-736497fa-2f2e-4d0f-ac34-b851224f581f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41602
31096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.4160231096
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.3066582454
Short name T464
Test name
Test status
Simulation time 23276513411 ps
CPU time 34.19 seconds
Started Jul 27 07:39:10 PM PDT 24
Finished Jul 27 07:39:45 PM PDT 24
Peak memory 207344 kb
Host smart-b452d014-cd80-4d42-aa32-f06ebaf99018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30665
82454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.3066582454
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.4234904363
Short name T2185
Test name
Test status
Simulation time 3326594596 ps
CPU time 4.8 seconds
Started Jul 27 07:39:10 PM PDT 24
Finished Jul 27 07:39:15 PM PDT 24
Peak memory 207328 kb
Host smart-fb257fed-43a2-4c97-882e-c3654b3e7c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42349
04363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.4234904363
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.2044502545
Short name T2027
Test name
Test status
Simulation time 8663371544 ps
CPU time 243.09 seconds
Started Jul 27 07:39:08 PM PDT 24
Finished Jul 27 07:43:11 PM PDT 24
Peak memory 215472 kb
Host smart-04493e86-0137-48d9-89a7-08d8d487f53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20445
02545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.2044502545
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3872636895
Short name T457
Test name
Test status
Simulation time 4961208651 ps
CPU time 50.88 seconds
Started Jul 27 07:39:10 PM PDT 24
Finished Jul 27 07:40:00 PM PDT 24
Peak memory 207344 kb
Host smart-2e47c3ac-502d-4840-bfa1-3fb869f3fc96
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3872636895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3872636895
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3285752393
Short name T2090
Test name
Test status
Simulation time 283393357 ps
CPU time 1.02 seconds
Started Jul 27 07:39:10 PM PDT 24
Finished Jul 27 07:39:11 PM PDT 24
Peak memory 207092 kb
Host smart-27334c8e-e9ae-49bf-b77f-488c23e26fad
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3285752393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3285752393
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2526058717
Short name T930
Test name
Test status
Simulation time 195030551 ps
CPU time 0.94 seconds
Started Jul 27 07:39:09 PM PDT 24
Finished Jul 27 07:39:10 PM PDT 24
Peak memory 207064 kb
Host smart-fcee957a-452d-470f-bb74-c190042e2f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25260
58717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2526058717
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.190996151
Short name T828
Test name
Test status
Simulation time 3605730413 ps
CPU time 38.25 seconds
Started Jul 27 07:39:10 PM PDT 24
Finished Jul 27 07:39:49 PM PDT 24
Peak memory 216948 kb
Host smart-b0a2d9ea-b8fc-4c0e-87fd-4e9d99d21959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19099
6151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.190996151
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1530488404
Short name T492
Test name
Test status
Simulation time 5263843871 ps
CPU time 156.16 seconds
Started Jul 27 07:39:10 PM PDT 24
Finished Jul 27 07:41:46 PM PDT 24
Peak memory 215504 kb
Host smart-8d2fee90-38fc-4e5a-af62-c225ee24538d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1530488404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1530488404
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2578853866
Short name T2463
Test name
Test status
Simulation time 145420189 ps
CPU time 0.88 seconds
Started Jul 27 07:39:11 PM PDT 24
Finished Jul 27 07:39:12 PM PDT 24
Peak memory 207084 kb
Host smart-4e91a66b-24cb-485a-bfe4-630d7568e813
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2578853866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2578853866
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3252588265
Short name T736
Test name
Test status
Simulation time 208017432 ps
CPU time 0.92 seconds
Started Jul 27 07:39:08 PM PDT 24
Finished Jul 27 07:39:09 PM PDT 24
Peak memory 207084 kb
Host smart-f11c2096-2158-4a80-b99b-9b8d5c9dc631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32525
88265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3252588265
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.677381991
Short name T145
Test name
Test status
Simulation time 230742029 ps
CPU time 1.05 seconds
Started Jul 27 07:39:15 PM PDT 24
Finished Jul 27 07:39:16 PM PDT 24
Peak memory 207140 kb
Host smart-f22b7b0d-4c60-4137-a063-7849a5aff4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67738
1991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.677381991
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.3829889454
Short name T1367
Test name
Test status
Simulation time 168607866 ps
CPU time 0.87 seconds
Started Jul 27 07:39:16 PM PDT 24
Finished Jul 27 07:39:17 PM PDT 24
Peak memory 207088 kb
Host smart-340ee642-a556-4e4c-9483-95604bde0321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38298
89454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3829889454
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.25030728
Short name T1539
Test name
Test status
Simulation time 214634129 ps
CPU time 0.9 seconds
Started Jul 27 07:39:15 PM PDT 24
Finished Jul 27 07:39:16 PM PDT 24
Peak memory 207140 kb
Host smart-62625965-cdd5-44d8-9539-5458262ce122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25030
728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.25030728
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2773433046
Short name T2526
Test name
Test status
Simulation time 200920987 ps
CPU time 0.94 seconds
Started Jul 27 07:39:14 PM PDT 24
Finished Jul 27 07:39:15 PM PDT 24
Peak memory 207024 kb
Host smart-c6498409-b977-4ca4-8449-0b6ffc999f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27734
33046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2773433046
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2189668440
Short name T718
Test name
Test status
Simulation time 162262520 ps
CPU time 0.91 seconds
Started Jul 27 07:39:15 PM PDT 24
Finished Jul 27 07:39:16 PM PDT 24
Peak memory 207108 kb
Host smart-e9aa059e-eeca-4708-a9a4-699e544f37fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21896
68440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2189668440
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.3266398542
Short name T2602
Test name
Test status
Simulation time 232302048 ps
CPU time 1.09 seconds
Started Jul 27 07:39:14 PM PDT 24
Finished Jul 27 07:39:15 PM PDT 24
Peak memory 207100 kb
Host smart-08f9858d-bb6e-4ede-b553-b7b9020f8179
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3266398542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.3266398542
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2516933635
Short name T1614
Test name
Test status
Simulation time 173062002 ps
CPU time 0.85 seconds
Started Jul 27 07:39:14 PM PDT 24
Finished Jul 27 07:39:15 PM PDT 24
Peak memory 207124 kb
Host smart-777ce910-9b23-441b-8d0d-f170165c87f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25169
33635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2516933635
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2621619542
Short name T2381
Test name
Test status
Simulation time 32620479 ps
CPU time 0.68 seconds
Started Jul 27 07:39:16 PM PDT 24
Finished Jul 27 07:39:17 PM PDT 24
Peak memory 207036 kb
Host smart-a903661d-d7c6-4a63-9899-c00b0c494354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26216
19542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2621619542
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.856446955
Short name T1415
Test name
Test status
Simulation time 19972798242 ps
CPU time 52.82 seconds
Started Jul 27 07:39:16 PM PDT 24
Finished Jul 27 07:40:09 PM PDT 24
Peak memory 215724 kb
Host smart-72db5575-4e42-4679-9efc-30655d6bbfc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85644
6955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.856446955
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1099397933
Short name T1854
Test name
Test status
Simulation time 189569854 ps
CPU time 0.9 seconds
Started Jul 27 07:39:14 PM PDT 24
Finished Jul 27 07:39:15 PM PDT 24
Peak memory 207024 kb
Host smart-0e7c4a73-566f-4285-aa53-bb77fb6ead5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10993
97933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1099397933
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3624576733
Short name T349
Test name
Test status
Simulation time 196241867 ps
CPU time 0.98 seconds
Started Jul 27 07:39:13 PM PDT 24
Finished Jul 27 07:39:14 PM PDT 24
Peak memory 207112 kb
Host smart-e32efc61-d24e-4805-bb82-11faa570679b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36245
76733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3624576733
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.4055807878
Short name T1009
Test name
Test status
Simulation time 248432009 ps
CPU time 0.97 seconds
Started Jul 27 07:39:16 PM PDT 24
Finished Jul 27 07:39:17 PM PDT 24
Peak memory 207100 kb
Host smart-51e6bb96-bb3b-48a6-9ae7-3eca8d5a2434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40558
07878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.4055807878
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.4012576002
Short name T864
Test name
Test status
Simulation time 156371241 ps
CPU time 0.86 seconds
Started Jul 27 07:39:14 PM PDT 24
Finished Jul 27 07:39:15 PM PDT 24
Peak memory 207116 kb
Host smart-b196bb2d-51cb-4742-9700-e34d7420420b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40125
76002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.4012576002
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1791347381
Short name T2747
Test name
Test status
Simulation time 159540264 ps
CPU time 0.87 seconds
Started Jul 27 07:39:14 PM PDT 24
Finished Jul 27 07:39:15 PM PDT 24
Peak memory 207092 kb
Host smart-89350b5a-74c6-47d5-8bfc-a9f5ff1a35e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17913
47381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1791347381
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1708205321
Short name T579
Test name
Test status
Simulation time 220154950 ps
CPU time 0.9 seconds
Started Jul 27 07:39:14 PM PDT 24
Finished Jul 27 07:39:15 PM PDT 24
Peak memory 207080 kb
Host smart-fac1c5fc-0caf-4e90-807b-2358e3d1438d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17082
05321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1708205321
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3062367373
Short name T486
Test name
Test status
Simulation time 172056076 ps
CPU time 0.87 seconds
Started Jul 27 07:39:16 PM PDT 24
Finished Jul 27 07:39:17 PM PDT 24
Peak memory 207072 kb
Host smart-4df2adfa-7d2e-40e1-ad31-3ac737e119c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30623
67373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3062367373
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1660129413
Short name T2380
Test name
Test status
Simulation time 192689174 ps
CPU time 0.97 seconds
Started Jul 27 07:39:14 PM PDT 24
Finished Jul 27 07:39:15 PM PDT 24
Peak memory 206992 kb
Host smart-c96a21a2-227a-4fa4-a22b-5123462757ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16601
29413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1660129413
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.19817120
Short name T586
Test name
Test status
Simulation time 5771298302 ps
CPU time 177.51 seconds
Started Jul 27 07:39:14 PM PDT 24
Finished Jul 27 07:42:12 PM PDT 24
Peak memory 215604 kb
Host smart-c36c353a-6198-415f-9aaf-f5d5f63cbd48
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=19817120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.19817120
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2535480308
Short name T1585
Test name
Test status
Simulation time 193762603 ps
CPU time 0.94 seconds
Started Jul 27 07:39:14 PM PDT 24
Finished Jul 27 07:39:15 PM PDT 24
Peak memory 207068 kb
Host smart-da15fd0d-7d7f-48e5-9700-354eac29fb92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25354
80308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2535480308
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2076485137
Short name T1406
Test name
Test status
Simulation time 156586628 ps
CPU time 0.84 seconds
Started Jul 27 07:39:14 PM PDT 24
Finished Jul 27 07:39:15 PM PDT 24
Peak memory 207096 kb
Host smart-24bcacc5-bc4d-4f82-92ab-b1c80de05e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20764
85137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2076485137
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.715240332
Short name T227
Test name
Test status
Simulation time 793487942 ps
CPU time 2.23 seconds
Started Jul 27 07:39:16 PM PDT 24
Finished Jul 27 07:39:18 PM PDT 24
Peak memory 207072 kb
Host smart-3f4653f0-b21b-4635-97df-9f5e1bf8cb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71524
0332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.715240332
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.2629521174
Short name T175
Test name
Test status
Simulation time 5764567694 ps
CPU time 55.23 seconds
Started Jul 27 07:39:15 PM PDT 24
Finished Jul 27 07:40:11 PM PDT 24
Peak memory 216784 kb
Host smart-adb0d166-7f33-4052-bc99-fd0f274f9063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26295
21174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.2629521174
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.4097374153
Short name T1787
Test name
Test status
Simulation time 2984871232 ps
CPU time 19.25 seconds
Started Jul 27 07:39:09 PM PDT 24
Finished Jul 27 07:39:28 PM PDT 24
Peak memory 207432 kb
Host smart-00af7ab7-bf1a-4471-847e-7f1df45a8af0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097374153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.4097374153
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.1040003063
Short name T822
Test name
Test status
Simulation time 50239760 ps
CPU time 0.67 seconds
Started Jul 27 07:39:26 PM PDT 24
Finished Jul 27 07:39:27 PM PDT 24
Peak memory 207080 kb
Host smart-722a27b8-0026-4f13-a0f3-5b200a194c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1040003063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.1040003063
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2464523
Short name T1250
Test name
Test status
Simulation time 4120761187 ps
CPU time 6.1 seconds
Started Jul 27 07:39:22 PM PDT 24
Finished Jul 27 07:39:28 PM PDT 24
Peak memory 207380 kb
Host smart-575b7e2b-a591-4a62-92ba-5affc7bf6f65
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us
bdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_
wake_disconnect.2464523
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.602480770
Short name T1423
Test name
Test status
Simulation time 13398580652 ps
CPU time 16 seconds
Started Jul 27 07:39:21 PM PDT 24
Finished Jul 27 07:39:37 PM PDT 24
Peak memory 207360 kb
Host smart-4fb9d630-adb4-4d11-81c4-46b795cb9038
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=602480770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.602480770
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2694530257
Short name T2217
Test name
Test status
Simulation time 23394673778 ps
CPU time 27.26 seconds
Started Jul 27 07:39:20 PM PDT 24
Finished Jul 27 07:39:47 PM PDT 24
Peak memory 207356 kb
Host smart-a4a4df00-8c5d-4ce8-bcd5-91369dd07eff
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694530257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.2694530257
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1617472339
Short name T2665
Test name
Test status
Simulation time 155493634 ps
CPU time 0.86 seconds
Started Jul 27 07:39:26 PM PDT 24
Finished Jul 27 07:39:27 PM PDT 24
Peak memory 207132 kb
Host smart-959eaa2f-d8a6-49fc-b80f-ebdb9881a604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16174
72339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1617472339
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.4071402928
Short name T2817
Test name
Test status
Simulation time 194851809 ps
CPU time 0.91 seconds
Started Jul 27 07:39:21 PM PDT 24
Finished Jul 27 07:39:22 PM PDT 24
Peak memory 207048 kb
Host smart-217360c7-2a59-4da4-9b38-7a6cc718f84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40714
02928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.4071402928
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.1924649693
Short name T2369
Test name
Test status
Simulation time 351435545 ps
CPU time 1.42 seconds
Started Jul 27 07:39:23 PM PDT 24
Finished Jul 27 07:39:24 PM PDT 24
Peak memory 207068 kb
Host smart-5de88011-94ab-4b21-ba96-f6a43b2cd8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19246
49693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.1924649693
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3117108442
Short name T1940
Test name
Test status
Simulation time 512731536 ps
CPU time 1.46 seconds
Started Jul 27 07:39:22 PM PDT 24
Finished Jul 27 07:39:24 PM PDT 24
Peak memory 207140 kb
Host smart-0005fcc8-d19c-4ff4-94dd-35e22389efe2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3117108442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3117108442
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.3424191040
Short name T1723
Test name
Test status
Simulation time 15470495222 ps
CPU time 35.71 seconds
Started Jul 27 07:39:20 PM PDT 24
Finished Jul 27 07:39:56 PM PDT 24
Peak memory 207392 kb
Host smart-1628338f-c400-4835-91a1-cfc0df4985b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34241
91040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3424191040
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.301813651
Short name T2119
Test name
Test status
Simulation time 1105426360 ps
CPU time 9.57 seconds
Started Jul 27 07:39:19 PM PDT 24
Finished Jul 27 07:39:29 PM PDT 24
Peak memory 207360 kb
Host smart-e5bb877b-8d24-4f6a-a5a8-2e667e222deb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301813651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.301813651
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.954957254
Short name T2083
Test name
Test status
Simulation time 473106076 ps
CPU time 1.47 seconds
Started Jul 27 07:39:20 PM PDT 24
Finished Jul 27 07:39:22 PM PDT 24
Peak memory 207052 kb
Host smart-63ee8178-e9b9-4e64-834d-a41f31d537f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95495
7254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.954957254
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.1076243282
Short name T2110
Test name
Test status
Simulation time 138953810 ps
CPU time 0.81 seconds
Started Jul 27 07:39:19 PM PDT 24
Finished Jul 27 07:39:20 PM PDT 24
Peak memory 207064 kb
Host smart-0808accf-2672-4fc7-a54f-0868107764e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10762
43282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.1076243282
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.2240113198
Short name T2450
Test name
Test status
Simulation time 105014417 ps
CPU time 0.82 seconds
Started Jul 27 07:39:22 PM PDT 24
Finished Jul 27 07:39:23 PM PDT 24
Peak memory 206996 kb
Host smart-776e6e9c-f592-412f-97bf-c7c1bc54a1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22401
13198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2240113198
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3036194679
Short name T725
Test name
Test status
Simulation time 863599291 ps
CPU time 2.19 seconds
Started Jul 27 07:39:24 PM PDT 24
Finished Jul 27 07:39:26 PM PDT 24
Peak memory 207440 kb
Host smart-1c2dfa3c-b036-43f2-8cd8-00bab6f07a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30361
94679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3036194679
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1556932558
Short name T2337
Test name
Test status
Simulation time 149837758 ps
CPU time 1.26 seconds
Started Jul 27 07:39:19 PM PDT 24
Finished Jul 27 07:39:20 PM PDT 24
Peak memory 207220 kb
Host smart-316e536f-7860-426e-8f29-7a6743608202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15569
32558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1556932558
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3013579848
Short name T1005
Test name
Test status
Simulation time 158825634 ps
CPU time 0.86 seconds
Started Jul 27 07:39:21 PM PDT 24
Finished Jul 27 07:39:22 PM PDT 24
Peak memory 207116 kb
Host smart-ba270907-76fd-49de-a6c2-497051308698
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3013579848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3013579848
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.253214578
Short name T1163
Test name
Test status
Simulation time 140168090 ps
CPU time 0.88 seconds
Started Jul 27 07:39:26 PM PDT 24
Finished Jul 27 07:39:26 PM PDT 24
Peak memory 207100 kb
Host smart-79d8ae14-6170-4517-9a16-709d00060fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25321
4578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.253214578
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1588258049
Short name T806
Test name
Test status
Simulation time 176687430 ps
CPU time 0.97 seconds
Started Jul 27 07:39:19 PM PDT 24
Finished Jul 27 07:39:20 PM PDT 24
Peak memory 207064 kb
Host smart-c4eaa681-c4d1-44b9-a4c5-f672bda395ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15882
58049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1588258049
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.4068301785
Short name T2618
Test name
Test status
Simulation time 5363151560 ps
CPU time 158.16 seconds
Started Jul 27 07:39:23 PM PDT 24
Finished Jul 27 07:42:01 PM PDT 24
Peak memory 215572 kb
Host smart-0ed3f3f1-3186-4725-95ab-7dae1c1a41bf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4068301785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.4068301785
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1542579559
Short name T1241
Test name
Test status
Simulation time 187670175 ps
CPU time 0.88 seconds
Started Jul 27 07:39:18 PM PDT 24
Finished Jul 27 07:39:19 PM PDT 24
Peak memory 207012 kb
Host smart-a2f7795d-8ece-4941-9685-c3affefb7340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15425
79559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1542579559
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3618743841
Short name T35
Test name
Test status
Simulation time 23351225691 ps
CPU time 27.53 seconds
Started Jul 27 07:39:27 PM PDT 24
Finished Jul 27 07:39:55 PM PDT 24
Peak memory 207376 kb
Host smart-2bf0428d-697e-4733-b6d6-b5aa161de615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36187
43841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3618743841
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2622768494
Short name T331
Test name
Test status
Simulation time 3322894478 ps
CPU time 5.13 seconds
Started Jul 27 07:39:24 PM PDT 24
Finished Jul 27 07:39:29 PM PDT 24
Peak memory 207456 kb
Host smart-f0357f05-551e-4a86-b1f2-6a31444b93cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26227
68494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2622768494
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.237188807
Short name T2397
Test name
Test status
Simulation time 4960211988 ps
CPU time 38.06 seconds
Started Jul 27 07:39:20 PM PDT 24
Finished Jul 27 07:39:58 PM PDT 24
Peak memory 223776 kb
Host smart-f648a9e2-e965-4a1e-9da0-13faee50ead4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23718
8807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.237188807
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.174672462
Short name T627
Test name
Test status
Simulation time 4833462714 ps
CPU time 38.76 seconds
Started Jul 27 07:39:21 PM PDT 24
Finished Jul 27 07:40:00 PM PDT 24
Peak memory 215624 kb
Host smart-929311e4-84ab-4bd9-a4a0-c77fb71f03b6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=174672462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.174672462
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1486214209
Short name T695
Test name
Test status
Simulation time 248503939 ps
CPU time 1.05 seconds
Started Jul 27 07:39:20 PM PDT 24
Finished Jul 27 07:39:21 PM PDT 24
Peak memory 207084 kb
Host smart-901c4afc-822b-4be7-b38b-b8f38a952553
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1486214209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1486214209
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.668343407
Short name T2264
Test name
Test status
Simulation time 181158724 ps
CPU time 0.89 seconds
Started Jul 27 07:39:24 PM PDT 24
Finished Jul 27 07:39:25 PM PDT 24
Peak memory 207064 kb
Host smart-bd52e098-681d-4ce4-a46b-e1e44d3845ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66834
3407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.668343407
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.4194364517
Short name T1558
Test name
Test status
Simulation time 5802244291 ps
CPU time 54.53 seconds
Started Jul 27 07:39:19 PM PDT 24
Finished Jul 27 07:40:14 PM PDT 24
Peak memory 215564 kb
Host smart-0d48c9c9-08eb-4911-8b4f-f4f754f7ae6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41943
64517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.4194364517
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.3727668494
Short name T1861
Test name
Test status
Simulation time 4006006469 ps
CPU time 40.4 seconds
Started Jul 27 07:39:21 PM PDT 24
Finished Jul 27 07:40:01 PM PDT 24
Peak memory 216884 kb
Host smart-910f0ef9-0448-45aa-9bfe-8c61be079212
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3727668494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.3727668494
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.1032927839
Short name T605
Test name
Test status
Simulation time 195998309 ps
CPU time 0.89 seconds
Started Jul 27 07:39:22 PM PDT 24
Finished Jul 27 07:39:23 PM PDT 24
Peak memory 207084 kb
Host smart-cfe39ff0-bc7c-4bef-8e65-b628bf3fb9be
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1032927839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.1032927839
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2096708630
Short name T2495
Test name
Test status
Simulation time 143205093 ps
CPU time 0.91 seconds
Started Jul 27 07:39:20 PM PDT 24
Finished Jul 27 07:39:21 PM PDT 24
Peak memory 207332 kb
Host smart-055e0432-c021-4100-b576-fd9d73496639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20967
08630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2096708630
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.1078236790
Short name T1496
Test name
Test status
Simulation time 185456497 ps
CPU time 0.92 seconds
Started Jul 27 07:39:21 PM PDT 24
Finished Jul 27 07:39:22 PM PDT 24
Peak memory 207136 kb
Host smart-5e0758f1-cb9c-4850-9b89-96315ccc618a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10782
36790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1078236790
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.399184422
Short name T847
Test name
Test status
Simulation time 217682880 ps
CPU time 0.95 seconds
Started Jul 27 07:39:22 PM PDT 24
Finished Jul 27 07:39:23 PM PDT 24
Peak memory 207032 kb
Host smart-6cb65894-ea2e-4ffe-97c3-01cbf78f0072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39918
4422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.399184422
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1912122699
Short name T1500
Test name
Test status
Simulation time 180570327 ps
CPU time 0.91 seconds
Started Jul 27 07:39:29 PM PDT 24
Finished Jul 27 07:39:30 PM PDT 24
Peak memory 207072 kb
Host smart-5bb66960-2be0-44c7-8e66-8efa9c38aab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19121
22699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1912122699
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3502855538
Short name T1806
Test name
Test status
Simulation time 181770781 ps
CPU time 0.87 seconds
Started Jul 27 07:39:25 PM PDT 24
Finished Jul 27 07:39:26 PM PDT 24
Peak memory 207092 kb
Host smart-855a5ee0-7d79-45dd-9d91-63d26005c0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35028
55538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3502855538
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1604457073
Short name T505
Test name
Test status
Simulation time 200870536 ps
CPU time 1.02 seconds
Started Jul 27 07:39:27 PM PDT 24
Finished Jul 27 07:39:28 PM PDT 24
Peak memory 207136 kb
Host smart-79d1eafd-ab56-4ac3-ab15-3324687ed8db
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1604457073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1604457073
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.3928266979
Short name T987
Test name
Test status
Simulation time 208001345 ps
CPU time 0.85 seconds
Started Jul 27 07:39:25 PM PDT 24
Finished Jul 27 07:39:26 PM PDT 24
Peak memory 207104 kb
Host smart-6aec76be-6e40-4d98-9438-b1f53ffee8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39282
66979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.3928266979
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2914381709
Short name T1249
Test name
Test status
Simulation time 32923897 ps
CPU time 0.72 seconds
Started Jul 27 07:39:26 PM PDT 24
Finished Jul 27 07:39:27 PM PDT 24
Peak memory 207104 kb
Host smart-303840d7-9b14-4f93-84e5-ccfcb85b9d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29143
81709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2914381709
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1168349135
Short name T2732
Test name
Test status
Simulation time 8380223625 ps
CPU time 24.23 seconds
Started Jul 27 07:39:26 PM PDT 24
Finished Jul 27 07:39:51 PM PDT 24
Peak memory 215768 kb
Host smart-42c2bca2-fdce-42e3-b795-6b24342b309b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11683
49135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1168349135
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1095333167
Short name T1788
Test name
Test status
Simulation time 174604129 ps
CPU time 0.89 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:39:35 PM PDT 24
Peak memory 207164 kb
Host smart-3b24a3ed-5d85-4145-b07a-baba9ccdcbcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10953
33167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1095333167
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.861424845
Short name T1261
Test name
Test status
Simulation time 282033036 ps
CPU time 1.04 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 207040 kb
Host smart-4e27c3bc-0ba2-4d61-bbda-52cf2907ae77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86142
4845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.861424845
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1492768088
Short name T1164
Test name
Test status
Simulation time 222606850 ps
CPU time 0.96 seconds
Started Jul 27 07:39:29 PM PDT 24
Finished Jul 27 07:39:30 PM PDT 24
Peak memory 207064 kb
Host smart-53ff410f-ac0a-4510-8097-d523181af903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14927
68088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1492768088
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.4251732227
Short name T1701
Test name
Test status
Simulation time 181613610 ps
CPU time 0.93 seconds
Started Jul 27 07:39:34 PM PDT 24
Finished Jul 27 07:39:35 PM PDT 24
Peak memory 207108 kb
Host smart-4ab16b8e-68bd-46a9-8910-761ae8511970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42517
32227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.4251732227
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3820989478
Short name T2780
Test name
Test status
Simulation time 169753315 ps
CPU time 0.86 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 207080 kb
Host smart-b347796f-9930-4fda-96e4-4d2599d7b7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38209
89478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3820989478
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.4272160120
Short name T2178
Test name
Test status
Simulation time 153158533 ps
CPU time 0.81 seconds
Started Jul 27 07:39:34 PM PDT 24
Finished Jul 27 07:39:35 PM PDT 24
Peak memory 207132 kb
Host smart-9a7bf81c-4c75-43c7-a295-454a7ee6d8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42721
60120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.4272160120
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2396991392
Short name T1259
Test name
Test status
Simulation time 151141796 ps
CPU time 0.81 seconds
Started Jul 27 07:39:26 PM PDT 24
Finished Jul 27 07:39:27 PM PDT 24
Peak memory 207100 kb
Host smart-6f7192e2-93ae-4113-9d6c-2db5a6dccefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23969
91392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2396991392
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.50757874
Short name T2282
Test name
Test status
Simulation time 211118776 ps
CPU time 0.98 seconds
Started Jul 27 07:39:25 PM PDT 24
Finished Jul 27 07:39:26 PM PDT 24
Peak memory 207108 kb
Host smart-ab3b91b1-1085-4f56-8f28-d98742343cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50757
874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.50757874
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.4248726795
Short name T2328
Test name
Test status
Simulation time 3738615381 ps
CPU time 36.12 seconds
Started Jul 27 07:39:25 PM PDT 24
Finished Jul 27 07:40:01 PM PDT 24
Peak memory 215624 kb
Host smart-365a5343-d789-4d17-a6e2-2a8018954640
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4248726795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.4248726795
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.3349788875
Short name T1697
Test name
Test status
Simulation time 152130857 ps
CPU time 0.84 seconds
Started Jul 27 07:39:31 PM PDT 24
Finished Jul 27 07:39:32 PM PDT 24
Peak memory 207104 kb
Host smart-ae8322e1-9c5d-4f59-b362-9a4e90bc6b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33497
88875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3349788875
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1290085799
Short name T1898
Test name
Test status
Simulation time 178467997 ps
CPU time 0.93 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 207108 kb
Host smart-9df5e3b0-937e-4a90-8c32-f2037dc04e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12900
85799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1290085799
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.2778033477
Short name T757
Test name
Test status
Simulation time 388681113 ps
CPU time 1.28 seconds
Started Jul 27 07:39:32 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 207104 kb
Host smart-a91164bf-f9dd-4411-8c7a-08a15635c17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27780
33477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.2778033477
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2799687743
Short name T1572
Test name
Test status
Simulation time 5472563792 ps
CPU time 41.59 seconds
Started Jul 27 07:39:25 PM PDT 24
Finished Jul 27 07:40:07 PM PDT 24
Peak memory 207272 kb
Host smart-b8c57150-26c9-4c83-befa-b43261f62ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27996
87743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2799687743
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.639787686
Short name T666
Test name
Test status
Simulation time 2890340089 ps
CPU time 25.37 seconds
Started Jul 27 07:39:21 PM PDT 24
Finished Jul 27 07:39:47 PM PDT 24
Peak memory 207296 kb
Host smart-ecb96127-fc80-4737-b05a-4b98192cdd0b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639787686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_host
_handshake.639787686
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3867479615
Short name T1374
Test name
Test status
Simulation time 37987492 ps
CPU time 0.63 seconds
Started Jul 27 07:39:37 PM PDT 24
Finished Jul 27 07:39:38 PM PDT 24
Peak memory 207136 kb
Host smart-46bc1885-bc8b-4b62-a57f-b21da34e343b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3867479615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3867479615
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.912519548
Short name T2812
Test name
Test status
Simulation time 3695071308 ps
CPU time 5.68 seconds
Started Jul 27 07:39:27 PM PDT 24
Finished Jul 27 07:39:33 PM PDT 24
Peak memory 207428 kb
Host smart-c43190c0-8170-4250-9729-ad595fa74054
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912519548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_ao
n_wake_disconnect.912519548
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2667910503
Short name T648
Test name
Test status
Simulation time 13374432100 ps
CPU time 14.84 seconds
Started Jul 27 07:39:28 PM PDT 24
Finished Jul 27 07:39:43 PM PDT 24
Peak memory 207468 kb
Host smart-aa17fa85-3c8d-4d65-a5a8-445b94f0d60c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667910503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2667910503
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3312549816
Short name T2299
Test name
Test status
Simulation time 23326040635 ps
CPU time 27.12 seconds
Started Jul 27 07:39:26 PM PDT 24
Finished Jul 27 07:39:54 PM PDT 24
Peak memory 207424 kb
Host smart-708c14f4-4ebb-44dd-9dac-2c8af000c43a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312549816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.3312549816
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.294296519
Short name T1501
Test name
Test status
Simulation time 155558400 ps
CPU time 0.84 seconds
Started Jul 27 07:39:29 PM PDT 24
Finished Jul 27 07:39:30 PM PDT 24
Peak memory 207136 kb
Host smart-8c18564d-da4c-4022-8f9a-ca35890f52d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29429
6519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.294296519
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.3664515812
Short name T2205
Test name
Test status
Simulation time 230460928 ps
CPU time 0.96 seconds
Started Jul 27 07:39:27 PM PDT 24
Finished Jul 27 07:39:28 PM PDT 24
Peak memory 207116 kb
Host smart-16e60717-7912-4e76-bee7-1ce4d1f20822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36645
15812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.3664515812
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.3041159262
Short name T2461
Test name
Test status
Simulation time 559736353 ps
CPU time 1.77 seconds
Started Jul 27 07:39:27 PM PDT 24
Finished Jul 27 07:39:29 PM PDT 24
Peak memory 207068 kb
Host smart-cc96717d-fa25-4e21-969a-937b7d40c2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30411
59262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.3041159262
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.197471601
Short name T1083
Test name
Test status
Simulation time 452111369 ps
CPU time 1.42 seconds
Started Jul 27 07:39:26 PM PDT 24
Finished Jul 27 07:39:28 PM PDT 24
Peak memory 207132 kb
Host smart-81395933-defa-4b5c-ae63-6f077614dfce
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=197471601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.197471601
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.4205372522
Short name T2658
Test name
Test status
Simulation time 17392494175 ps
CPU time 34.81 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:40:08 PM PDT 24
Peak memory 207388 kb
Host smart-53c0835e-5997-4144-bc5b-b6d607aa418c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42053
72522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.4205372522
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.2399000117
Short name T1485
Test name
Test status
Simulation time 1520863998 ps
CPU time 37.24 seconds
Started Jul 27 07:39:27 PM PDT 24
Finished Jul 27 07:40:05 PM PDT 24
Peak memory 207320 kb
Host smart-c9dad3c5-5bd6-449b-9f92-35f6789712e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399000117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.2399000117
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1339086566
Short name T332
Test name
Test status
Simulation time 350590596 ps
CPU time 1.29 seconds
Started Jul 27 07:39:29 PM PDT 24
Finished Jul 27 07:39:31 PM PDT 24
Peak memory 207108 kb
Host smart-9f67a523-b2bb-4491-aff3-10a1e74bf11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13390
86566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1339086566
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.72748991
Short name T802
Test name
Test status
Simulation time 158224275 ps
CPU time 0.83 seconds
Started Jul 27 07:39:34 PM PDT 24
Finished Jul 27 07:39:35 PM PDT 24
Peak memory 207128 kb
Host smart-f9f5bcb3-5bd7-47af-91f8-e37f32506d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72748
991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.72748991
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.3785937328
Short name T2357
Test name
Test status
Simulation time 33093075 ps
CPU time 0.71 seconds
Started Jul 27 07:39:34 PM PDT 24
Finished Jul 27 07:39:35 PM PDT 24
Peak memory 207120 kb
Host smart-e1475aa3-ac85-45d7-9264-028da32323e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37859
37328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3785937328
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3789281216
Short name T1010
Test name
Test status
Simulation time 930354799 ps
CPU time 2.35 seconds
Started Jul 27 07:39:26 PM PDT 24
Finished Jul 27 07:39:29 PM PDT 24
Peak memory 207368 kb
Host smart-f9cc55dc-ec7b-4972-8543-52f11e0b045c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37892
81216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3789281216
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.344517768
Short name T499
Test name
Test status
Simulation time 204336875 ps
CPU time 2.06 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:39:36 PM PDT 24
Peak memory 207288 kb
Host smart-ad455291-9ab3-4d48-bcd6-056caa673c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34451
7768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.344517768
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.3571007781
Short name T362
Test name
Test status
Simulation time 167728268 ps
CPU time 0.91 seconds
Started Jul 27 07:39:36 PM PDT 24
Finished Jul 27 07:39:37 PM PDT 24
Peak memory 207132 kb
Host smart-b1132c74-baa5-4f0d-a988-a5dad911e860
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3571007781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3571007781
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1026519845
Short name T1388
Test name
Test status
Simulation time 166352948 ps
CPU time 0.87 seconds
Started Jul 27 07:39:32 PM PDT 24
Finished Jul 27 07:39:33 PM PDT 24
Peak memory 207068 kb
Host smart-6fa4d955-6c13-4899-be74-08d8174538d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10265
19845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1026519845
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.4039120706
Short name T2161
Test name
Test status
Simulation time 250123352 ps
CPU time 1.1 seconds
Started Jul 27 07:39:32 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 207064 kb
Host smart-24e6b87b-503c-4d27-bc7d-27fbd194495e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40391
20706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.4039120706
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.1747085280
Short name T2505
Test name
Test status
Simulation time 8790220049 ps
CPU time 271.29 seconds
Started Jul 27 07:39:34 PM PDT 24
Finished Jul 27 07:44:05 PM PDT 24
Peak memory 215628 kb
Host smart-3a436b7a-7214-455b-9c33-391781a0b0f2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1747085280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.1747085280
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.276645912
Short name T1113
Test name
Test status
Simulation time 6285849373 ps
CPU time 82.44 seconds
Started Jul 27 07:39:31 PM PDT 24
Finished Jul 27 07:40:53 PM PDT 24
Peak memory 207324 kb
Host smart-e556baaa-eb94-47da-8ec6-e416e2899398
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=276645912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.276645912
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2705463340
Short name T2153
Test name
Test status
Simulation time 223168167 ps
CPU time 0.99 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 207128 kb
Host smart-713a2366-a75a-4321-bde7-d22ab03598c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27054
63340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2705463340
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.2956042665
Short name T2598
Test name
Test status
Simulation time 23324322998 ps
CPU time 31.82 seconds
Started Jul 27 07:39:30 PM PDT 24
Finished Jul 27 07:40:02 PM PDT 24
Peak memory 207312 kb
Host smart-b4a64072-c02d-400a-99d5-1c342fc6c540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29560
42665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.2956042665
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2787737609
Short name T1859
Test name
Test status
Simulation time 3366667592 ps
CPU time 5.3 seconds
Started Jul 27 07:39:30 PM PDT 24
Finished Jul 27 07:39:36 PM PDT 24
Peak memory 207336 kb
Host smart-62562f94-5995-4ae6-9d1f-5411919c72d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27877
37609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2787737609
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3804170698
Short name T609
Test name
Test status
Simulation time 7535337060 ps
CPU time 71.12 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:40:45 PM PDT 24
Peak memory 217500 kb
Host smart-46ad1b3e-234e-47c6-a486-7addbd5bfe04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38041
70698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3804170698
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.1268596226
Short name T2158
Test name
Test status
Simulation time 6601717748 ps
CPU time 45.1 seconds
Started Jul 27 07:39:34 PM PDT 24
Finished Jul 27 07:40:19 PM PDT 24
Peak memory 207372 kb
Host smart-e9a2fecb-45bf-4588-8a7a-9cbea3b5f979
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1268596226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.1268596226
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1527439443
Short name T884
Test name
Test status
Simulation time 258181773 ps
CPU time 0.96 seconds
Started Jul 27 07:39:30 PM PDT 24
Finished Jul 27 07:39:31 PM PDT 24
Peak memory 207172 kb
Host smart-a84c8d6b-5dd3-4cab-add1-24c25226ee0c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1527439443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1527439443
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2217066240
Short name T724
Test name
Test status
Simulation time 187486473 ps
CPU time 0.98 seconds
Started Jul 27 07:39:32 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 207152 kb
Host smart-fc4054e2-18bf-4702-94f4-878a9b56e79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22170
66240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2217066240
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.4044443210
Short name T2653
Test name
Test status
Simulation time 5574791617 ps
CPU time 165.28 seconds
Started Jul 27 07:39:30 PM PDT 24
Finished Jul 27 07:42:15 PM PDT 24
Peak memory 215608 kb
Host smart-c67663d2-e69a-4026-a4c8-5d9d0636294d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40444
43210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.4044443210
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.2847214579
Short name T2839
Test name
Test status
Simulation time 5667969865 ps
CPU time 59.46 seconds
Started Jul 27 07:39:32 PM PDT 24
Finished Jul 27 07:40:31 PM PDT 24
Peak memory 207424 kb
Host smart-4d0bb321-f0bd-4bcc-aa8b-1598db4e18fb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2847214579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.2847214579
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3337650249
Short name T2783
Test name
Test status
Simulation time 151904936 ps
CPU time 0.85 seconds
Started Jul 27 07:39:32 PM PDT 24
Finished Jul 27 07:39:33 PM PDT 24
Peak memory 207024 kb
Host smart-9091b390-72c0-4bd7-97cf-22310fb45c43
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3337650249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3337650249
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.9601647
Short name T1172
Test name
Test status
Simulation time 140388708 ps
CPU time 0.9 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 207124 kb
Host smart-2e9b661c-7623-4678-989d-d4222450f7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96016
47 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.9601647
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.806493407
Short name T129
Test name
Test status
Simulation time 265553707 ps
CPU time 1.07 seconds
Started Jul 27 07:39:32 PM PDT 24
Finished Jul 27 07:39:33 PM PDT 24
Peak memory 207140 kb
Host smart-35f1f739-7c34-4be1-8a00-c0b847f5d461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80649
3407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.806493407
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.754584680
Short name T1868
Test name
Test status
Simulation time 151670598 ps
CPU time 0.87 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 207112 kb
Host smart-e544daf7-31f0-45d6-a52e-ac0cd1251331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75458
4680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.754584680
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2885943271
Short name T1385
Test name
Test status
Simulation time 173084284 ps
CPU time 0.9 seconds
Started Jul 27 07:39:31 PM PDT 24
Finished Jul 27 07:39:32 PM PDT 24
Peak memory 207164 kb
Host smart-7a9dda5b-4291-40b5-aead-390e1c427526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28859
43271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2885943271
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.158825420
Short name T1433
Test name
Test status
Simulation time 177961775 ps
CPU time 0.88 seconds
Started Jul 27 07:39:32 PM PDT 24
Finished Jul 27 07:39:33 PM PDT 24
Peak memory 207092 kb
Host smart-0c2fb1c2-a133-4e73-b20f-eae4ac379f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15882
5420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.158825420
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.4170576354
Short name T1474
Test name
Test status
Simulation time 180004871 ps
CPU time 0.93 seconds
Started Jul 27 07:39:34 PM PDT 24
Finished Jul 27 07:39:35 PM PDT 24
Peak memory 207220 kb
Host smart-b561c788-d6fa-4855-b8d1-c6e8568cd0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41705
76354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.4170576354
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3732120364
Short name T2493
Test name
Test status
Simulation time 207328119 ps
CPU time 0.97 seconds
Started Jul 27 07:39:32 PM PDT 24
Finished Jul 27 07:39:33 PM PDT 24
Peak memory 207132 kb
Host smart-f453821b-5120-4977-a086-00de597e5749
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3732120364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3732120364
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.309445579
Short name T2182
Test name
Test status
Simulation time 170646498 ps
CPU time 0.87 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 207104 kb
Host smart-9707c144-3db1-49b9-af32-0c37d7fa63bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30944
5579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.309445579
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3125453943
Short name T954
Test name
Test status
Simulation time 62193366 ps
CPU time 0.74 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 207076 kb
Host smart-8a66927f-e9ca-483f-b671-d6776131c271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31254
53943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3125453943
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3581369992
Short name T253
Test name
Test status
Simulation time 15889702706 ps
CPU time 36.43 seconds
Started Jul 27 07:39:32 PM PDT 24
Finished Jul 27 07:40:08 PM PDT 24
Peak memory 215608 kb
Host smart-d46cba0e-b0b3-4f36-abd7-c143559a1d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35813
69992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3581369992
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.111679327
Short name T1752
Test name
Test status
Simulation time 179481123 ps
CPU time 0.95 seconds
Started Jul 27 07:39:31 PM PDT 24
Finished Jul 27 07:39:32 PM PDT 24
Peak memory 207064 kb
Host smart-961fd55f-9bb5-4067-806f-6eeb52cb60d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11167
9327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.111679327
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1195572419
Short name T1373
Test name
Test status
Simulation time 222593343 ps
CPU time 0.96 seconds
Started Jul 27 07:39:33 PM PDT 24
Finished Jul 27 07:39:34 PM PDT 24
Peak memory 206988 kb
Host smart-5522a176-fd10-4de9-8e6c-7c4db1e2ee88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11955
72419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1195572419
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.938895806
Short name T2051
Test name
Test status
Simulation time 194764925 ps
CPU time 0.91 seconds
Started Jul 27 07:39:32 PM PDT 24
Finished Jul 27 07:39:33 PM PDT 24
Peak memory 207092 kb
Host smart-90453eee-5803-4c89-b9b6-dd18941e8323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93889
5806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.938895806
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.47863971
Short name T1998
Test name
Test status
Simulation time 180267116 ps
CPU time 0.92 seconds
Started Jul 27 07:39:39 PM PDT 24
Finished Jul 27 07:39:40 PM PDT 24
Peak memory 207112 kb
Host smart-71886971-ab7d-43b0-a28e-55331f2196dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47863
971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.47863971
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3547163187
Short name T615
Test name
Test status
Simulation time 183036994 ps
CPU time 0.86 seconds
Started Jul 27 07:39:39 PM PDT 24
Finished Jul 27 07:39:40 PM PDT 24
Peak memory 207144 kb
Host smart-236437e3-ef50-408b-a889-22b2dd370e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35471
63187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3547163187
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1105294468
Short name T2509
Test name
Test status
Simulation time 150478326 ps
CPU time 0.83 seconds
Started Jul 27 07:39:38 PM PDT 24
Finished Jul 27 07:39:38 PM PDT 24
Peak memory 207076 kb
Host smart-a97320ce-fab2-412a-a47c-6accc0b9a76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11052
94468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1105294468
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2836868754
Short name T741
Test name
Test status
Simulation time 151206232 ps
CPU time 0.87 seconds
Started Jul 27 07:39:36 PM PDT 24
Finished Jul 27 07:39:37 PM PDT 24
Peak memory 207096 kb
Host smart-82a24670-b83a-440a-8408-e114db4252f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28368
68754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2836868754
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2157227225
Short name T1050
Test name
Test status
Simulation time 236277170 ps
CPU time 1.03 seconds
Started Jul 27 07:39:38 PM PDT 24
Finished Jul 27 07:39:39 PM PDT 24
Peak memory 207104 kb
Host smart-519a6dc5-f575-412a-9264-2de736287dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21572
27225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2157227225
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.403687274
Short name T2387
Test name
Test status
Simulation time 6108918749 ps
CPU time 186.47 seconds
Started Jul 27 07:39:38 PM PDT 24
Finished Jul 27 07:42:44 PM PDT 24
Peak memory 215604 kb
Host smart-1b46998f-15b9-4457-88a9-66538d88ccf1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=403687274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.403687274
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3326865345
Short name T594
Test name
Test status
Simulation time 152749520 ps
CPU time 0.8 seconds
Started Jul 27 07:39:38 PM PDT 24
Finished Jul 27 07:39:39 PM PDT 24
Peak memory 207144 kb
Host smart-0f1c340f-c3bf-4b13-8ac7-6a9d73b8135a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33268
65345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3326865345
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2661070681
Short name T898
Test name
Test status
Simulation time 189802531 ps
CPU time 0.91 seconds
Started Jul 27 07:39:37 PM PDT 24
Finished Jul 27 07:39:38 PM PDT 24
Peak memory 207144 kb
Host smart-3ccb938b-9a71-4c04-ad22-3c389e48bec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26610
70681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2661070681
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.4138763166
Short name T1780
Test name
Test status
Simulation time 1085370541 ps
CPU time 2.62 seconds
Started Jul 27 07:39:38 PM PDT 24
Finished Jul 27 07:39:41 PM PDT 24
Peak memory 207316 kb
Host smart-6c47063d-717f-4715-8b5d-4b4d4c7b77e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41387
63166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.4138763166
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1683773247
Short name T660
Test name
Test status
Simulation time 6904929847 ps
CPU time 197.32 seconds
Started Jul 27 07:39:42 PM PDT 24
Finished Jul 27 07:42:59 PM PDT 24
Peak memory 215616 kb
Host smart-1a14e439-3e00-4329-876d-104e64ba77de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16837
73247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1683773247
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.2536717254
Short name T781
Test name
Test status
Simulation time 1316488699 ps
CPU time 30.76 seconds
Started Jul 27 07:39:27 PM PDT 24
Finished Jul 27 07:39:58 PM PDT 24
Peak memory 207328 kb
Host smart-1b4f8619-b3a2-42e3-8df7-2e9fce381bd3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536717254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.2536717254
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.3457212498
Short name T2769
Test name
Test status
Simulation time 41706523 ps
CPU time 0.68 seconds
Started Jul 27 07:39:51 PM PDT 24
Finished Jul 27 07:39:52 PM PDT 24
Peak memory 207104 kb
Host smart-47ae1caf-3b7c-47dd-9841-ef4c1aa974c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3457212498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.3457212498
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1474695694
Short name T2258
Test name
Test status
Simulation time 3717540658 ps
CPU time 5.69 seconds
Started Jul 27 07:39:39 PM PDT 24
Finished Jul 27 07:39:44 PM PDT 24
Peak memory 207344 kb
Host smart-ba5cb68a-0233-46fd-94ae-76330beb8a5d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474695694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.1474695694
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.2487405174
Short name T793
Test name
Test status
Simulation time 13331925348 ps
CPU time 14.7 seconds
Started Jul 27 07:39:38 PM PDT 24
Finished Jul 27 07:39:53 PM PDT 24
Peak memory 207404 kb
Host smart-b4dbb23a-ff06-4bf8-9c98-80cb016174ad
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487405174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.2487405174
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.561856591
Short name T198
Test name
Test status
Simulation time 23364445126 ps
CPU time 26.76 seconds
Started Jul 27 07:39:45 PM PDT 24
Finished Jul 27 07:40:12 PM PDT 24
Peak memory 207380 kb
Host smart-7d37417c-2db4-46ba-bf29-fd93c6d7b316
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561856591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_ao
n_wake_resume.561856591
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3771858392
Short name T411
Test name
Test status
Simulation time 175618562 ps
CPU time 0.92 seconds
Started Jul 27 07:39:39 PM PDT 24
Finished Jul 27 07:39:40 PM PDT 24
Peak memory 207144 kb
Host smart-8dd4f4a6-76a3-4b0b-9a5b-175d78ad4e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37718
58392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3771858392
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.899992001
Short name T1325
Test name
Test status
Simulation time 164525867 ps
CPU time 0.89 seconds
Started Jul 27 07:39:37 PM PDT 24
Finished Jul 27 07:39:39 PM PDT 24
Peak memory 207104 kb
Host smart-4d4197f3-77a7-48fb-b204-0b781c576f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89999
2001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.899992001
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.702997852
Short name T1184
Test name
Test status
Simulation time 373744297 ps
CPU time 1.35 seconds
Started Jul 27 07:39:38 PM PDT 24
Finished Jul 27 07:39:39 PM PDT 24
Peak memory 207120 kb
Host smart-b38b2218-cdcb-46af-9009-c89b5f4ce18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70299
7852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.702997852
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1945959449
Short name T2191
Test name
Test status
Simulation time 1261281950 ps
CPU time 3.1 seconds
Started Jul 27 07:39:39 PM PDT 24
Finished Jul 27 07:39:42 PM PDT 24
Peak memory 207336 kb
Host smart-04bc9a26-04db-4690-ac4e-886135d6394f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1945959449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1945959449
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.2476449472
Short name T336
Test name
Test status
Simulation time 12788147583 ps
CPU time 29.86 seconds
Started Jul 27 07:39:39 PM PDT 24
Finished Jul 27 07:40:09 PM PDT 24
Peak memory 207360 kb
Host smart-16e9d446-7af9-422f-aa36-4a4153564472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24764
49472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.2476449472
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.689534858
Short name T1848
Test name
Test status
Simulation time 2858980509 ps
CPU time 19.15 seconds
Started Jul 27 07:39:38 PM PDT 24
Finished Jul 27 07:39:57 PM PDT 24
Peak memory 207376 kb
Host smart-ff548b85-4a57-4b8a-9487-8cd95779c59b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689534858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.689534858
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.1750654300
Short name T1248
Test name
Test status
Simulation time 365848210 ps
CPU time 1.32 seconds
Started Jul 27 07:39:45 PM PDT 24
Finished Jul 27 07:39:46 PM PDT 24
Peak memory 207088 kb
Host smart-84656804-7eb3-4c06-8e08-1cd649db1b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17506
54300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.1750654300
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3903620351
Short name T439
Test name
Test status
Simulation time 147346426 ps
CPU time 0.8 seconds
Started Jul 27 07:39:37 PM PDT 24
Finished Jul 27 07:39:38 PM PDT 24
Peak memory 207188 kb
Host smart-4f72861f-88e7-4967-ac39-d94cf82d668b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39036
20351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3903620351
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.1130832047
Short name T1349
Test name
Test status
Simulation time 32592104 ps
CPU time 0.71 seconds
Started Jul 27 07:39:41 PM PDT 24
Finished Jul 27 07:39:42 PM PDT 24
Peak memory 207108 kb
Host smart-78d64106-a982-4173-96f9-919c74151bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11308
32047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1130832047
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.3131189944
Short name T1737
Test name
Test status
Simulation time 1000897840 ps
CPU time 2.53 seconds
Started Jul 27 07:39:36 PM PDT 24
Finished Jul 27 07:39:39 PM PDT 24
Peak memory 207372 kb
Host smart-5cdee75c-ce87-44df-a647-c242b4fc105d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31311
89944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.3131189944
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1651852371
Short name T1499
Test name
Test status
Simulation time 237307797 ps
CPU time 1.43 seconds
Started Jul 27 07:39:39 PM PDT 24
Finished Jul 27 07:39:40 PM PDT 24
Peak memory 207300 kb
Host smart-bcbaaf32-8934-44a4-af52-f8385d571b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16518
52371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1651852371
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2532280864
Short name T2031
Test name
Test status
Simulation time 214395291 ps
CPU time 0.99 seconds
Started Jul 27 07:39:39 PM PDT 24
Finished Jul 27 07:39:41 PM PDT 24
Peak memory 207332 kb
Host smart-95ba60db-0e24-47a9-b924-b3142a4902e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2532280864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2532280864
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.514902543
Short name T17
Test name
Test status
Simulation time 140468392 ps
CPU time 0.84 seconds
Started Jul 27 07:39:41 PM PDT 24
Finished Jul 27 07:39:42 PM PDT 24
Peak memory 207100 kb
Host smart-695e248b-820a-4016-a0f5-3eee97d845b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51490
2543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.514902543
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2554198302
Short name T2455
Test name
Test status
Simulation time 199257437 ps
CPU time 1.01 seconds
Started Jul 27 07:39:37 PM PDT 24
Finished Jul 27 07:39:39 PM PDT 24
Peak memory 207080 kb
Host smart-cc75a7e8-8606-4273-a723-662ae5597c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25541
98302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2554198302
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.1855603204
Short name T1625
Test name
Test status
Simulation time 6805619791 ps
CPU time 56.36 seconds
Started Jul 27 07:39:39 PM PDT 24
Finished Jul 27 07:40:35 PM PDT 24
Peak memory 215648 kb
Host smart-e471c6e4-c6f6-4e3d-9d45-93df22858d1b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1855603204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.1855603204
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.1446185330
Short name T692
Test name
Test status
Simulation time 4792918611 ps
CPU time 56.68 seconds
Started Jul 27 07:39:38 PM PDT 24
Finished Jul 27 07:40:35 PM PDT 24
Peak memory 207416 kb
Host smart-0fa9c00b-8127-4d96-bf9a-dd0564cc6177
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1446185330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.1446185330
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.139095152
Short name T791
Test name
Test status
Simulation time 230507842 ps
CPU time 1.01 seconds
Started Jul 27 07:39:38 PM PDT 24
Finished Jul 27 07:39:40 PM PDT 24
Peak memory 207100 kb
Host smart-2890a644-ccf6-47a1-bf6d-f90728ff0385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13909
5152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.139095152
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.1651654862
Short name T1442
Test name
Test status
Simulation time 23412888347 ps
CPU time 27.98 seconds
Started Jul 27 07:39:45 PM PDT 24
Finished Jul 27 07:40:13 PM PDT 24
Peak memory 207372 kb
Host smart-94ad4fda-8efd-4d11-b569-4a9e023c5710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16516
54862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.1651654862
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.2818430595
Short name T1413
Test name
Test status
Simulation time 3336501402 ps
CPU time 5.03 seconds
Started Jul 27 07:39:37 PM PDT 24
Finished Jul 27 07:39:43 PM PDT 24
Peak memory 207320 kb
Host smart-b9387e5b-5825-4aed-9f5a-579aa86e1402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28184
30595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2818430595
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.4071581643
Short name T2271
Test name
Test status
Simulation time 6793287829 ps
CPU time 191.05 seconds
Started Jul 27 07:39:38 PM PDT 24
Finished Jul 27 07:42:50 PM PDT 24
Peak memory 215648 kb
Host smart-1a2bf568-f864-4c56-86b0-d3607562997d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40715
81643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.4071581643
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3245001358
Short name T2066
Test name
Test status
Simulation time 5798317134 ps
CPU time 42.94 seconds
Started Jul 27 07:39:39 PM PDT 24
Finished Jul 27 07:40:22 PM PDT 24
Peak memory 207392 kb
Host smart-5dcac0f6-f41d-416e-9fa8-d79234228028
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3245001358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3245001358
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.383120913
Short name T1986
Test name
Test status
Simulation time 274099558 ps
CPU time 1.03 seconds
Started Jul 27 07:39:39 PM PDT 24
Finished Jul 27 07:39:41 PM PDT 24
Peak memory 207104 kb
Host smart-d5379cca-ff70-46b0-99f1-eb91318029a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=383120913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.383120913
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2896478758
Short name T1043
Test name
Test status
Simulation time 184234470 ps
CPU time 0.89 seconds
Started Jul 27 07:39:39 PM PDT 24
Finished Jul 27 07:39:40 PM PDT 24
Peak memory 207164 kb
Host smart-9840f32b-2221-481a-98bc-7e79383c5bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28964
78758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2896478758
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2871396973
Short name T535
Test name
Test status
Simulation time 3128712566 ps
CPU time 87.79 seconds
Started Jul 27 07:39:46 PM PDT 24
Finished Jul 27 07:41:14 PM PDT 24
Peak memory 215684 kb
Host smart-0846cd73-eb19-49cf-b4d2-a1a60b600f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28713
96973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2871396973
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.3197177236
Short name T2534
Test name
Test status
Simulation time 3998434628 ps
CPU time 30.82 seconds
Started Jul 27 07:39:45 PM PDT 24
Finished Jul 27 07:40:16 PM PDT 24
Peak memory 207372 kb
Host smart-7fea02c0-86cc-4113-bc98-8fdce605ebae
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3197177236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.3197177236
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.687728953
Short name T2585
Test name
Test status
Simulation time 173266262 ps
CPU time 0.92 seconds
Started Jul 27 07:39:47 PM PDT 24
Finished Jul 27 07:39:48 PM PDT 24
Peak memory 207332 kb
Host smart-6740d567-378a-4bd9-809c-00265a3b6b64
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=687728953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.687728953
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2325223008
Short name T626
Test name
Test status
Simulation time 218571346 ps
CPU time 0.94 seconds
Started Jul 27 07:39:46 PM PDT 24
Finished Jul 27 07:39:47 PM PDT 24
Peak memory 207124 kb
Host smart-0481da63-47e1-49ad-8d52-b87727b12ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23252
23008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2325223008
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3112899519
Short name T135
Test name
Test status
Simulation time 186172549 ps
CPU time 0.93 seconds
Started Jul 27 07:39:46 PM PDT 24
Finished Jul 27 07:39:47 PM PDT 24
Peak memory 207164 kb
Host smart-93593867-4f4b-4c65-b116-f8c392d71310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31128
99519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3112899519
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.726755927
Short name T1594
Test name
Test status
Simulation time 217149189 ps
CPU time 0.91 seconds
Started Jul 27 07:39:45 PM PDT 24
Finished Jul 27 07:39:46 PM PDT 24
Peak memory 206988 kb
Host smart-b78dee1e-a935-4f1b-8264-7e11883c521e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72675
5927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.726755927
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3868618910
Short name T996
Test name
Test status
Simulation time 178448150 ps
CPU time 0.88 seconds
Started Jul 27 07:39:42 PM PDT 24
Finished Jul 27 07:39:43 PM PDT 24
Peak memory 207036 kb
Host smart-9602df39-f377-4e34-b421-901996ea522a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38686
18910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3868618910
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1215989466
Short name T1128
Test name
Test status
Simulation time 151509451 ps
CPU time 0.86 seconds
Started Jul 27 07:39:45 PM PDT 24
Finished Jul 27 07:39:46 PM PDT 24
Peak memory 207100 kb
Host smart-561dc23b-a3ea-471f-8d87-2f18fcf38a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12159
89466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1215989466
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3101997577
Short name T2109
Test name
Test status
Simulation time 144825277 ps
CPU time 0.88 seconds
Started Jul 27 07:39:44 PM PDT 24
Finished Jul 27 07:39:45 PM PDT 24
Peak memory 207076 kb
Host smart-b38c66fc-faf7-4ce0-a532-85bbbf2723e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31019
97577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3101997577
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.422738169
Short name T1915
Test name
Test status
Simulation time 214018180 ps
CPU time 1.03 seconds
Started Jul 27 07:39:46 PM PDT 24
Finished Jul 27 07:39:47 PM PDT 24
Peak memory 207112 kb
Host smart-262dd63d-c70e-4479-affd-43e411874190
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=422738169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.422738169
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2463272044
Short name T1476
Test name
Test status
Simulation time 136454747 ps
CPU time 0.82 seconds
Started Jul 27 07:39:46 PM PDT 24
Finished Jul 27 07:39:47 PM PDT 24
Peak memory 207100 kb
Host smart-28e0bb9c-5b2e-45a8-a6f3-7ba64fd0522c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24632
72044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2463272044
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2094850305
Short name T977
Test name
Test status
Simulation time 55113825 ps
CPU time 0.74 seconds
Started Jul 27 07:39:43 PM PDT 24
Finished Jul 27 07:39:44 PM PDT 24
Peak memory 207064 kb
Host smart-4a142f8d-f3e2-4301-b463-ee0f829fe4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20948
50305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2094850305
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.863108337
Short name T1425
Test name
Test status
Simulation time 6684103787 ps
CPU time 17.19 seconds
Started Jul 27 07:39:44 PM PDT 24
Finished Jul 27 07:40:01 PM PDT 24
Peak memory 215572 kb
Host smart-915e4535-4ba6-4333-8c2b-09a4ed8a14e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86310
8337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.863108337
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1862977488
Short name T225
Test name
Test status
Simulation time 166771035 ps
CPU time 0.84 seconds
Started Jul 27 07:39:44 PM PDT 24
Finished Jul 27 07:39:45 PM PDT 24
Peak memory 207032 kb
Host smart-3b9df872-98d5-4641-ac7c-a022a4918c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18629
77488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1862977488
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2356311938
Short name T538
Test name
Test status
Simulation time 191282038 ps
CPU time 0.94 seconds
Started Jul 27 07:39:47 PM PDT 24
Finished Jul 27 07:39:48 PM PDT 24
Peak memory 207220 kb
Host smart-65b6918b-bc73-4468-ba90-6895ef71abd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23563
11938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2356311938
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.1552635833
Short name T1187
Test name
Test status
Simulation time 169469713 ps
CPU time 0.88 seconds
Started Jul 27 07:39:45 PM PDT 24
Finished Jul 27 07:39:46 PM PDT 24
Peak memory 207124 kb
Host smart-950d4729-2c98-4d2d-9648-53e4b3a19eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15526
35833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1552635833
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3394556496
Short name T606
Test name
Test status
Simulation time 179477567 ps
CPU time 0.96 seconds
Started Jul 27 07:39:46 PM PDT 24
Finished Jul 27 07:39:47 PM PDT 24
Peak memory 207064 kb
Host smart-eb7123e6-bc17-4574-ac8b-71b65ddd1e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33945
56496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3394556496
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.1052481422
Short name T66
Test name
Test status
Simulation time 186023517 ps
CPU time 0.88 seconds
Started Jul 27 07:39:45 PM PDT 24
Finished Jul 27 07:39:46 PM PDT 24
Peak memory 207136 kb
Host smart-0849416a-020a-4d37-a736-2385c6b99643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10524
81422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.1052481422
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1640550248
Short name T2764
Test name
Test status
Simulation time 148528131 ps
CPU time 0.82 seconds
Started Jul 27 07:39:46 PM PDT 24
Finished Jul 27 07:39:46 PM PDT 24
Peak memory 207096 kb
Host smart-4511e7de-dbd5-42d4-bffd-c3b783121f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16405
50248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1640550248
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3958240320
Short name T728
Test name
Test status
Simulation time 170797127 ps
CPU time 0.86 seconds
Started Jul 27 07:39:46 PM PDT 24
Finished Jul 27 07:39:47 PM PDT 24
Peak memory 207352 kb
Host smart-a6ae7608-0b98-46a5-bfb7-9177e666ce33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39582
40320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3958240320
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3166478577
Short name T379
Test name
Test status
Simulation time 251508910 ps
CPU time 1.03 seconds
Started Jul 27 07:39:45 PM PDT 24
Finished Jul 27 07:39:46 PM PDT 24
Peak memory 207112 kb
Host smart-a67962a8-a1a6-4446-b6ad-810c9508b77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31664
78577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3166478577
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.2838427636
Short name T1137
Test name
Test status
Simulation time 5906067690 ps
CPU time 45.35 seconds
Started Jul 27 07:39:47 PM PDT 24
Finished Jul 27 07:40:32 PM PDT 24
Peak memory 216760 kb
Host smart-9d29bf0a-22e0-434c-81ed-fc50da51bd21
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2838427636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.2838427636
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.307213696
Short name T1299
Test name
Test status
Simulation time 259906049 ps
CPU time 0.95 seconds
Started Jul 27 07:39:45 PM PDT 24
Finished Jul 27 07:39:46 PM PDT 24
Peak memory 207192 kb
Host smart-c700081e-98ec-41cb-815a-699519ed7d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30721
3696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.307213696
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3998762472
Short name T2289
Test name
Test status
Simulation time 204835314 ps
CPU time 0.94 seconds
Started Jul 27 07:39:50 PM PDT 24
Finished Jul 27 07:39:51 PM PDT 24
Peak memory 207108 kb
Host smart-c32c6c4b-78f9-4704-be4b-32b4578d1500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39987
62472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3998762472
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.2222148083
Short name T20
Test name
Test status
Simulation time 956674838 ps
CPU time 2.31 seconds
Started Jul 27 07:39:45 PM PDT 24
Finished Jul 27 07:39:47 PM PDT 24
Peak memory 207344 kb
Host smart-205f1d20-bfe5-48a1-b398-d56ec85ff8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22221
48083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.2222148083
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.1694176448
Short name T1756
Test name
Test status
Simulation time 4129812517 ps
CPU time 33.84 seconds
Started Jul 27 07:39:43 PM PDT 24
Finished Jul 27 07:40:17 PM PDT 24
Peak memory 207236 kb
Host smart-20d09ab8-9eed-4067-8f5b-3ccc9d4bb89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16941
76448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.1694176448
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.1801925655
Short name T957
Test name
Test status
Simulation time 2472069399 ps
CPU time 23.66 seconds
Started Jul 27 07:39:37 PM PDT 24
Finished Jul 27 07:40:00 PM PDT 24
Peak memory 207368 kb
Host smart-e4db14f9-51a1-425a-8384-0fb7f9a5d79f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801925655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.1801925655
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.867940237
Short name T193
Test name
Test status
Simulation time 34871173 ps
CPU time 0.67 seconds
Started Jul 27 07:40:00 PM PDT 24
Finished Jul 27 07:40:01 PM PDT 24
Peak memory 207108 kb
Host smart-f72e344b-b96e-4351-a6f1-9f8789876d55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=867940237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.867940237
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.2017114920
Short name T934
Test name
Test status
Simulation time 4274770263 ps
CPU time 6.04 seconds
Started Jul 27 07:39:53 PM PDT 24
Finished Jul 27 07:39:59 PM PDT 24
Peak memory 207380 kb
Host smart-46649b5d-0768-4517-b803-0ddcccc9ad80
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017114920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_disconnect.2017114920
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2346980905
Short name T807
Test name
Test status
Simulation time 13387463318 ps
CPU time 19.67 seconds
Started Jul 27 07:40:02 PM PDT 24
Finished Jul 27 07:40:22 PM PDT 24
Peak memory 207288 kb
Host smart-a6306de1-f6dc-41f2-b6c7-e88fb6379ae0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346980905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2346980905
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.4190719204
Short name T783
Test name
Test status
Simulation time 23427735683 ps
CPU time 28.92 seconds
Started Jul 27 07:39:52 PM PDT 24
Finished Jul 27 07:40:21 PM PDT 24
Peak memory 207356 kb
Host smart-dfd87403-4d25-44af-b30f-070666b8a86c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190719204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_resume.4190719204
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3073582285
Short name T595
Test name
Test status
Simulation time 182411089 ps
CPU time 0.9 seconds
Started Jul 27 07:39:53 PM PDT 24
Finished Jul 27 07:39:54 PM PDT 24
Peak memory 207132 kb
Host smart-925fd585-ad8d-479e-99c4-dedbfc16e7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30735
82285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3073582285
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.389129685
Short name T1343
Test name
Test status
Simulation time 145554930 ps
CPU time 0.86 seconds
Started Jul 27 07:39:50 PM PDT 24
Finished Jul 27 07:39:51 PM PDT 24
Peak memory 207040 kb
Host smart-53fcb82c-7716-4173-b125-34b495489d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38912
9685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.389129685
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.418331422
Short name T803
Test name
Test status
Simulation time 264046887 ps
CPU time 1.16 seconds
Started Jul 27 07:39:51 PM PDT 24
Finished Jul 27 07:39:53 PM PDT 24
Peak memory 207108 kb
Host smart-2b183df9-04ff-4217-9488-4beaf9a72e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41833
1422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.418331422
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3930804901
Short name T683
Test name
Test status
Simulation time 391182589 ps
CPU time 1.17 seconds
Started Jul 27 07:39:55 PM PDT 24
Finished Jul 27 07:39:56 PM PDT 24
Peak memory 207260 kb
Host smart-5101baa5-f8fb-40a6-8ff0-6e382495e384
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3930804901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3930804901
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3773991425
Short name T1779
Test name
Test status
Simulation time 8033761945 ps
CPU time 18.17 seconds
Started Jul 27 07:39:50 PM PDT 24
Finished Jul 27 07:40:09 PM PDT 24
Peak memory 207348 kb
Host smart-36464fe0-cd33-4e6f-a783-9a7abd079853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37739
91425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3773991425
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.2401434512
Short name T1772
Test name
Test status
Simulation time 546836916 ps
CPU time 8.52 seconds
Started Jul 27 07:39:52 PM PDT 24
Finished Jul 27 07:40:00 PM PDT 24
Peak memory 207260 kb
Host smart-a175b760-e643-4d45-8a58-dd8fd64d084d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401434512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.2401434512
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.4266642308
Short name T1541
Test name
Test status
Simulation time 499540874 ps
CPU time 1.56 seconds
Started Jul 27 07:39:51 PM PDT 24
Finished Jul 27 07:39:53 PM PDT 24
Peak memory 206960 kb
Host smart-d0c8d92b-ea31-4871-84de-1ae6b9f251be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42666
42308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.4266642308
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2248562035
Short name T2740
Test name
Test status
Simulation time 146065032 ps
CPU time 0.84 seconds
Started Jul 27 07:39:49 PM PDT 24
Finished Jul 27 07:39:51 PM PDT 24
Peak memory 206984 kb
Host smart-5049b670-0f98-4fe7-b3f1-b5e3d618909c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22485
62035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2248562035
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3643413904
Short name T1613
Test name
Test status
Simulation time 48739350 ps
CPU time 0.83 seconds
Started Jul 27 07:40:02 PM PDT 24
Finished Jul 27 07:40:03 PM PDT 24
Peak memory 206984 kb
Host smart-259b07a6-7584-4a45-8d8a-82481f081c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36434
13904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3643413904
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.681937125
Short name T1628
Test name
Test status
Simulation time 842078899 ps
CPU time 2.39 seconds
Started Jul 27 07:39:52 PM PDT 24
Finished Jul 27 07:39:55 PM PDT 24
Peak memory 207372 kb
Host smart-b2b12447-9fd8-492e-8de6-fbad754c73ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68193
7125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.681937125
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3097243311
Short name T613
Test name
Test status
Simulation time 184376474 ps
CPU time 2.43 seconds
Started Jul 27 07:39:50 PM PDT 24
Finished Jul 27 07:39:53 PM PDT 24
Peak memory 207228 kb
Host smart-b1167405-981b-4452-9137-dc36b6636084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30972
43311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3097243311
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1966131345
Short name T2167
Test name
Test status
Simulation time 203365960 ps
CPU time 1.01 seconds
Started Jul 27 07:39:53 PM PDT 24
Finished Jul 27 07:39:54 PM PDT 24
Peak memory 207256 kb
Host smart-64feccc2-17b4-437e-bb23-224aae82cd3e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1966131345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1966131345
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1371656270
Short name T1369
Test name
Test status
Simulation time 138140663 ps
CPU time 0.93 seconds
Started Jul 27 07:40:02 PM PDT 24
Finished Jul 27 07:40:03 PM PDT 24
Peak memory 206996 kb
Host smart-520a978a-f6cd-4924-aef9-320707013025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13716
56270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1371656270
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2564259844
Short name T1739
Test name
Test status
Simulation time 184845075 ps
CPU time 0.94 seconds
Started Jul 27 07:39:51 PM PDT 24
Finished Jul 27 07:39:52 PM PDT 24
Peak memory 207196 kb
Host smart-2d2426dc-436d-4bb4-b83e-b166b8a5ecb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25642
59844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2564259844
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.3423090386
Short name T1441
Test name
Test status
Simulation time 8841194696 ps
CPU time 93.54 seconds
Started Jul 27 07:39:51 PM PDT 24
Finished Jul 27 07:41:25 PM PDT 24
Peak memory 216920 kb
Host smart-8de650f0-8686-4b3a-819e-8093ebce10e6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3423090386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.3423090386
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.1570333404
Short name T1816
Test name
Test status
Simulation time 9215879681 ps
CPU time 67.07 seconds
Started Jul 27 07:39:52 PM PDT 24
Finished Jul 27 07:40:59 PM PDT 24
Peak memory 207332 kb
Host smart-21a1709d-b655-424d-9945-e58ebbedc02f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1570333404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.1570333404
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.3235564336
Short name T962
Test name
Test status
Simulation time 224924199 ps
CPU time 0.93 seconds
Started Jul 27 07:39:52 PM PDT 24
Finished Jul 27 07:39:53 PM PDT 24
Peak memory 207116 kb
Host smart-b4f9d7cc-d38a-4682-bbfc-b0863e369ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32355
64336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.3235564336
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1039968175
Short name T1917
Test name
Test status
Simulation time 23338788255 ps
CPU time 29.04 seconds
Started Jul 27 07:39:50 PM PDT 24
Finished Jul 27 07:40:20 PM PDT 24
Peak memory 207272 kb
Host smart-d6082cdc-b180-455f-9e62-713d3789bf41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10399
68175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1039968175
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.809100658
Short name T720
Test name
Test status
Simulation time 3297523098 ps
CPU time 4.85 seconds
Started Jul 27 07:39:55 PM PDT 24
Finished Jul 27 07:40:00 PM PDT 24
Peak memory 207492 kb
Host smart-f24561b2-9223-45e4-9570-08d869c0ecd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80910
0658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.809100658
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.917080079
Short name T1270
Test name
Test status
Simulation time 5287417467 ps
CPU time 39.81 seconds
Started Jul 27 07:39:50 PM PDT 24
Finished Jul 27 07:40:30 PM PDT 24
Peak memory 217564 kb
Host smart-755a49f2-633e-4e9a-985c-32857c093d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91708
0079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.917080079
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.1295572700
Short name T1430
Test name
Test status
Simulation time 4183884302 ps
CPU time 125.02 seconds
Started Jul 27 07:39:52 PM PDT 24
Finished Jul 27 07:41:57 PM PDT 24
Peak memory 215508 kb
Host smart-55207d11-fdd0-4a4b-b6ee-51966038afaa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1295572700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.1295572700
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.192407578
Short name T877
Test name
Test status
Simulation time 237978959 ps
CPU time 1.02 seconds
Started Jul 27 07:39:52 PM PDT 24
Finished Jul 27 07:39:53 PM PDT 24
Peak memory 207140 kb
Host smart-6c222779-6333-4d67-8ceb-7b9f1306e7b0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=192407578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.192407578
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1238930099
Short name T1105
Test name
Test status
Simulation time 188914664 ps
CPU time 0.91 seconds
Started Jul 27 07:39:53 PM PDT 24
Finished Jul 27 07:39:54 PM PDT 24
Peak memory 207092 kb
Host smart-46cb9aa4-de05-4bee-875d-3d8005524374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12389
30099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1238930099
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.1124692215
Short name T512
Test name
Test status
Simulation time 4558483929 ps
CPU time 46.48 seconds
Started Jul 27 07:39:52 PM PDT 24
Finished Jul 27 07:40:39 PM PDT 24
Peak memory 216900 kb
Host smart-82e3b9b6-c3ba-47f8-9f12-316a70cd66bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11246
92215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.1124692215
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.1363193609
Short name T2538
Test name
Test status
Simulation time 5180271615 ps
CPU time 51.09 seconds
Started Jul 27 07:39:55 PM PDT 24
Finished Jul 27 07:40:47 PM PDT 24
Peak memory 216996 kb
Host smart-7dbdeb68-d2ad-461c-8272-aa6e8d1fb20e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1363193609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.1363193609
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.375909293
Short name T2565
Test name
Test status
Simulation time 164865161 ps
CPU time 0.92 seconds
Started Jul 27 07:39:51 PM PDT 24
Finished Jul 27 07:39:52 PM PDT 24
Peak memory 207120 kb
Host smart-6a6b35d6-59c7-4b85-a66f-21727758987e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=375909293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.375909293
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.262118650
Short name T1913
Test name
Test status
Simulation time 149387056 ps
CPU time 0.91 seconds
Started Jul 27 07:40:02 PM PDT 24
Finished Jul 27 07:40:03 PM PDT 24
Peak memory 207016 kb
Host smart-3bf8317c-df48-4c4c-b981-9121a2feeeb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26211
8650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.262118650
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3710691616
Short name T2227
Test name
Test status
Simulation time 206964043 ps
CPU time 0.97 seconds
Started Jul 27 07:39:53 PM PDT 24
Finished Jul 27 07:39:54 PM PDT 24
Peak memory 207084 kb
Host smart-67b54849-5772-45f7-9524-913b4e1ed2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37106
91616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3710691616
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.392978281
Short name T1290
Test name
Test status
Simulation time 225885057 ps
CPU time 0.93 seconds
Started Jul 27 07:39:53 PM PDT 24
Finished Jul 27 07:39:54 PM PDT 24
Peak memory 207136 kb
Host smart-20989dbf-b14c-4e43-a898-688b025fbdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39297
8281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.392978281
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.665293451
Short name T786
Test name
Test status
Simulation time 170475380 ps
CPU time 0.88 seconds
Started Jul 27 07:39:58 PM PDT 24
Finished Jul 27 07:39:59 PM PDT 24
Peak memory 207076 kb
Host smart-a2bbafaf-b25b-436e-8b56-03cbddb01a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66529
3451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.665293451
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.114553274
Short name T1173
Test name
Test status
Simulation time 176866643 ps
CPU time 0.89 seconds
Started Jul 27 07:40:00 PM PDT 24
Finished Jul 27 07:40:01 PM PDT 24
Peak memory 207140 kb
Host smart-a2d366d0-6a73-4e34-8e02-b4ecc823c7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11455
3274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.114553274
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.791070480
Short name T1162
Test name
Test status
Simulation time 182919452 ps
CPU time 0.95 seconds
Started Jul 27 07:40:02 PM PDT 24
Finished Jul 27 07:40:03 PM PDT 24
Peak memory 207068 kb
Host smart-d1bd23a7-b0fd-40e1-86df-1040d58d74ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79107
0480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.791070480
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1243108303
Short name T874
Test name
Test status
Simulation time 236013096 ps
CPU time 0.98 seconds
Started Jul 27 07:39:59 PM PDT 24
Finished Jul 27 07:40:00 PM PDT 24
Peak memory 207136 kb
Host smart-1901798a-4e47-4e9d-b06f-0c056a7cdd05
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1243108303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1243108303
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3410659860
Short name T1254
Test name
Test status
Simulation time 143663096 ps
CPU time 0.84 seconds
Started Jul 27 07:40:00 PM PDT 24
Finished Jul 27 07:40:01 PM PDT 24
Peak memory 207084 kb
Host smart-2e85512d-dad3-4bdd-a039-700f12ea2193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34106
59860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3410659860
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2621182414
Short name T2670
Test name
Test status
Simulation time 73494310 ps
CPU time 0.75 seconds
Started Jul 27 07:40:03 PM PDT 24
Finished Jul 27 07:40:04 PM PDT 24
Peak memory 207056 kb
Host smart-053e94c7-bb6d-4408-88db-e3cf8aec0ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26211
82414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2621182414
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2015198147
Short name T2719
Test name
Test status
Simulation time 20575033857 ps
CPU time 53.16 seconds
Started Jul 27 07:40:01 PM PDT 24
Finished Jul 27 07:40:54 PM PDT 24
Peak memory 215600 kb
Host smart-7f350378-d2eb-449a-b8f0-417516f23851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20151
98147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2015198147
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.801239653
Short name T950
Test name
Test status
Simulation time 195498218 ps
CPU time 1.02 seconds
Started Jul 27 07:40:03 PM PDT 24
Finished Jul 27 07:40:04 PM PDT 24
Peak memory 207092 kb
Host smart-a184d103-e628-4345-95a5-fc9381599e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80123
9653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.801239653
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.4039934870
Short name T2622
Test name
Test status
Simulation time 180924146 ps
CPU time 0.98 seconds
Started Jul 27 07:40:00 PM PDT 24
Finished Jul 27 07:40:01 PM PDT 24
Peak memory 207116 kb
Host smart-309d52d5-d0c5-4948-804d-4b01442a9e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40399
34870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.4039934870
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.4676686
Short name T557
Test name
Test status
Simulation time 235832247 ps
CPU time 1.04 seconds
Started Jul 27 07:40:01 PM PDT 24
Finished Jul 27 07:40:02 PM PDT 24
Peak memory 207140 kb
Host smart-eefc3061-5555-49db-bb39-eb64e1cd6cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46766
86 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.4676686
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.3233885716
Short name T1188
Test name
Test status
Simulation time 173584211 ps
CPU time 0.89 seconds
Started Jul 27 07:40:03 PM PDT 24
Finished Jul 27 07:40:04 PM PDT 24
Peak memory 207200 kb
Host smart-4f9e6aaa-339f-4f91-b655-b51f70e2c98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32338
85716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3233885716
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.74028518
Short name T975
Test name
Test status
Simulation time 162172481 ps
CPU time 0.87 seconds
Started Jul 27 07:40:00 PM PDT 24
Finished Jul 27 07:40:01 PM PDT 24
Peak memory 207120 kb
Host smart-91ab2c64-255b-434a-9b5c-1466cf2d8dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74028
518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.74028518
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.62461217
Short name T2225
Test name
Test status
Simulation time 246230681 ps
CPU time 0.98 seconds
Started Jul 27 07:40:03 PM PDT 24
Finished Jul 27 07:40:04 PM PDT 24
Peak memory 207160 kb
Host smart-98644a7a-648a-4207-9a92-adfc49acd7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62461
217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.62461217
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1209023736
Short name T2017
Test name
Test status
Simulation time 167211422 ps
CPU time 0.83 seconds
Started Jul 27 07:40:03 PM PDT 24
Finished Jul 27 07:40:04 PM PDT 24
Peak memory 207208 kb
Host smart-eb564936-0107-4a5d-9246-1129af6299a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12090
23736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1209023736
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3304085002
Short name T1956
Test name
Test status
Simulation time 200369038 ps
CPU time 0.99 seconds
Started Jul 27 07:40:03 PM PDT 24
Finished Jul 27 07:40:04 PM PDT 24
Peak memory 207128 kb
Host smart-9b2d742e-3b67-4d26-8760-75f1e0f27e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33040
85002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3304085002
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3253120050
Short name T897
Test name
Test status
Simulation time 4322380840 ps
CPU time 125.27 seconds
Started Jul 27 07:40:02 PM PDT 24
Finished Jul 27 07:42:08 PM PDT 24
Peak memory 215608 kb
Host smart-b32837d7-c0f9-47de-a3ab-9aef1a2a053f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3253120050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3253120050
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2828298924
Short name T870
Test name
Test status
Simulation time 171539725 ps
CPU time 0.94 seconds
Started Jul 27 07:40:02 PM PDT 24
Finished Jul 27 07:40:03 PM PDT 24
Peak memory 207092 kb
Host smart-53122064-13b9-4b69-b69b-098965a0715f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28282
98924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2828298924
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2469725595
Short name T581
Test name
Test status
Simulation time 185788211 ps
CPU time 0.91 seconds
Started Jul 27 07:40:00 PM PDT 24
Finished Jul 27 07:40:01 PM PDT 24
Peak memory 207112 kb
Host smart-9296d15a-9e90-4458-a88a-458c387632cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24697
25595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2469725595
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.1893022804
Short name T1763
Test name
Test status
Simulation time 451558700 ps
CPU time 1.45 seconds
Started Jul 27 07:40:00 PM PDT 24
Finished Jul 27 07:40:02 PM PDT 24
Peak memory 207096 kb
Host smart-ba47a48d-66bb-4ade-bebd-db706544e7d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18930
22804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1893022804
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3459630876
Short name T1421
Test name
Test status
Simulation time 3021390597 ps
CPU time 22.57 seconds
Started Jul 27 07:40:03 PM PDT 24
Finished Jul 27 07:40:25 PM PDT 24
Peak memory 216728 kb
Host smart-1d84e1be-3a5a-4deb-b3d8-92a32c96959c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34596
30876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3459630876
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.716359539
Short name T1530
Test name
Test status
Simulation time 1118477217 ps
CPU time 9.34 seconds
Started Jul 27 07:39:50 PM PDT 24
Finished Jul 27 07:40:00 PM PDT 24
Peak memory 207340 kb
Host smart-ea2340db-7b46-456f-b32c-ac5bc0c357f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716359539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_host
_handshake.716359539
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.2922071301
Short name T1681
Test name
Test status
Simulation time 101223110 ps
CPU time 0.73 seconds
Started Jul 27 07:34:28 PM PDT 24
Finished Jul 27 07:34:28 PM PDT 24
Peak memory 207228 kb
Host smart-8ca6c6ac-5eda-4b57-8705-45523f6e43ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2922071301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2922071301
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3335643979
Short name T2088
Test name
Test status
Simulation time 4453398981 ps
CPU time 7.18 seconds
Started Jul 27 07:34:15 PM PDT 24
Finished Jul 27 07:34:23 PM PDT 24
Peak memory 207428 kb
Host smart-12d164e3-26df-4877-a267-a10e814c763b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335643979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.3335643979
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.2073497300
Short name T1390
Test name
Test status
Simulation time 13386074581 ps
CPU time 15.86 seconds
Started Jul 27 07:34:12 PM PDT 24
Finished Jul 27 07:34:28 PM PDT 24
Peak memory 207412 kb
Host smart-4c76b6ab-4ed7-4772-a98d-e6f16796e7f4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073497300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.2073497300
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.2525532695
Short name T2365
Test name
Test status
Simulation time 23299807975 ps
CPU time 29.72 seconds
Started Jul 27 07:34:11 PM PDT 24
Finished Jul 27 07:34:41 PM PDT 24
Peak memory 207364 kb
Host smart-a1326083-9c62-4f19-8a0c-644e60fda03d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525532695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.2525532695
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.4197058133
Short name T2787
Test name
Test status
Simulation time 192925091 ps
CPU time 0.95 seconds
Started Jul 27 07:34:10 PM PDT 24
Finished Jul 27 07:34:11 PM PDT 24
Peak memory 207104 kb
Host smart-0778f8e4-be69-4b77-af7e-3f441b118406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41970
58133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.4197058133
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.2404553273
Short name T51
Test name
Test status
Simulation time 146183844 ps
CPU time 0.87 seconds
Started Jul 27 07:34:11 PM PDT 24
Finished Jul 27 07:34:12 PM PDT 24
Peak memory 207092 kb
Host smart-2a9f0a31-24c2-40d1-8654-551a763f9b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24045
53273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2404553273
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.3223983466
Short name T55
Test name
Test status
Simulation time 139662474 ps
CPU time 0.88 seconds
Started Jul 27 07:34:12 PM PDT 24
Finished Jul 27 07:34:12 PM PDT 24
Peak memory 207100 kb
Host smart-43717f3c-ad33-48ec-918d-de2242843d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32239
83466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.3223983466
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.836751441
Short name T2660
Test name
Test status
Simulation time 149382155 ps
CPU time 0.84 seconds
Started Jul 27 07:34:11 PM PDT 24
Finished Jul 27 07:34:12 PM PDT 24
Peak memory 207188 kb
Host smart-d83129e2-81b4-4bb5-a3be-143f4c812223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83675
1441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.836751441
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.1201623337
Short name T388
Test name
Test status
Simulation time 187549560 ps
CPU time 0.96 seconds
Started Jul 27 07:34:09 PM PDT 24
Finished Jul 27 07:34:10 PM PDT 24
Peak memory 207104 kb
Host smart-5fe81f8a-2940-4be0-8a05-a79d1d7839a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12016
23337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.1201623337
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.2116740778
Short name T2432
Test name
Test status
Simulation time 1028623710 ps
CPU time 2.63 seconds
Started Jul 27 07:34:12 PM PDT 24
Finished Jul 27 07:34:15 PM PDT 24
Peak memory 207292 kb
Host smart-4c4dd6c4-ea24-4c30-9507-9c8728faf668
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2116740778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.2116740778
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.2095959341
Short name T189
Test name
Test status
Simulation time 11713360195 ps
CPU time 26.9 seconds
Started Jul 27 07:34:10 PM PDT 24
Finished Jul 27 07:34:37 PM PDT 24
Peak memory 207396 kb
Host smart-6740468e-52af-4875-9ba3-29bd87c8ca2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20959
59341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.2095959341
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.1987235253
Short name T1878
Test name
Test status
Simulation time 1041780665 ps
CPU time 22.35 seconds
Started Jul 27 07:34:10 PM PDT 24
Finished Jul 27 07:34:33 PM PDT 24
Peak memory 207332 kb
Host smart-6c28ce69-0b42-444b-a331-c822e1f9062f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987235253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.1987235253
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.2897969617
Short name T2825
Test name
Test status
Simulation time 426109119 ps
CPU time 1.53 seconds
Started Jul 27 07:34:10 PM PDT 24
Finished Jul 27 07:34:11 PM PDT 24
Peak memory 207036 kb
Host smart-754b1271-33d6-4342-b758-36a559922cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28979
69617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.2897969617
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.311539982
Short name T761
Test name
Test status
Simulation time 193608386 ps
CPU time 0.89 seconds
Started Jul 27 07:34:10 PM PDT 24
Finished Jul 27 07:34:11 PM PDT 24
Peak memory 207092 kb
Host smart-7651d4ec-7a88-4dd1-aaef-58d610b6c820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31153
9982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.311539982
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.81037296
Short name T2272
Test name
Test status
Simulation time 56481334 ps
CPU time 0.74 seconds
Started Jul 27 07:34:12 PM PDT 24
Finished Jul 27 07:34:13 PM PDT 24
Peak memory 207084 kb
Host smart-bfbd62b3-7962-4db7-b762-1c5d036fc514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81037
296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.81037296
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3365364574
Short name T458
Test name
Test status
Simulation time 837490375 ps
CPU time 2.29 seconds
Started Jul 27 07:34:15 PM PDT 24
Finished Jul 27 07:34:18 PM PDT 24
Peak memory 207356 kb
Host smart-bb9cfb76-cedd-4c10-888c-932ca3251b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33653
64574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3365364574
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.4120435596
Short name T1843
Test name
Test status
Simulation time 153407714 ps
CPU time 1.24 seconds
Started Jul 27 07:34:15 PM PDT 24
Finished Jul 27 07:34:16 PM PDT 24
Peak memory 207396 kb
Host smart-bb4e4470-d586-4c7f-a917-d60f0d74c89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41204
35596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.4120435596
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.1924871180
Short name T300
Test name
Test status
Simulation time 93187929363 ps
CPU time 136.91 seconds
Started Jul 27 07:34:16 PM PDT 24
Finished Jul 27 07:36:33 PM PDT 24
Peak memory 207288 kb
Host smart-72de8d23-318d-4be0-82a6-9f6114f2ad4d
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1924871180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.1924871180
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.480878507
Short name T1578
Test name
Test status
Simulation time 106215378880 ps
CPU time 180.16 seconds
Started Jul 27 07:34:16 PM PDT 24
Finished Jul 27 07:37:16 PM PDT 24
Peak memory 207272 kb
Host smart-551e4b8c-b09c-4293-8a16-8e6fa537be64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480878507 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.480878507
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.3757836023
Short name T1200
Test name
Test status
Simulation time 88137943831 ps
CPU time 144 seconds
Started Jul 27 07:34:15 PM PDT 24
Finished Jul 27 07:36:40 PM PDT 24
Peak memory 207352 kb
Host smart-ccb30250-9954-4b3e-bc95-fe30c0235c42
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3757836023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.3757836023
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.3998496649
Short name T468
Test name
Test status
Simulation time 92242010444 ps
CPU time 149.86 seconds
Started Jul 27 07:34:09 PM PDT 24
Finished Jul 27 07:36:39 PM PDT 24
Peak memory 207304 kb
Host smart-82f56152-750b-4df6-89f3-f6524e27beaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998496649 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.3998496649
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.2227113753
Short name T2162
Test name
Test status
Simulation time 114192579333 ps
CPU time 186.45 seconds
Started Jul 27 07:34:17 PM PDT 24
Finished Jul 27 07:37:24 PM PDT 24
Peak memory 207300 kb
Host smart-a67a97d1-b912-4e15-a730-958f1627ea81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22271
13753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.2227113753
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1389112787
Short name T1931
Test name
Test status
Simulation time 216582978 ps
CPU time 1.11 seconds
Started Jul 27 07:34:17 PM PDT 24
Finished Jul 27 07:34:18 PM PDT 24
Peak memory 207256 kb
Host smart-43904f69-a41e-48d2-a3e8-14d7c963881b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1389112787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1389112787
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1067365087
Short name T532
Test name
Test status
Simulation time 148227345 ps
CPU time 0.88 seconds
Started Jul 27 07:34:19 PM PDT 24
Finished Jul 27 07:34:20 PM PDT 24
Peak memory 207092 kb
Host smart-8deadbe4-11ca-4302-8b44-e6b8dff7e567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10673
65087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1067365087
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2735418210
Short name T2336
Test name
Test status
Simulation time 244504612 ps
CPU time 0.95 seconds
Started Jul 27 07:34:13 PM PDT 24
Finished Jul 27 07:34:14 PM PDT 24
Peak memory 207088 kb
Host smart-d39114cd-db76-4b11-a630-4ee634bc5714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27354
18210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2735418210
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.3293479361
Short name T703
Test name
Test status
Simulation time 9155886218 ps
CPU time 73.78 seconds
Started Jul 27 07:34:16 PM PDT 24
Finished Jul 27 07:35:30 PM PDT 24
Peak memory 207384 kb
Host smart-79eb3752-6c69-4928-bc4e-cb208eb7ca04
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3293479361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3293479361
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.3079028519
Short name T1580
Test name
Test status
Simulation time 7547771057 ps
CPU time 54.96 seconds
Started Jul 27 07:34:14 PM PDT 24
Finished Jul 27 07:35:09 PM PDT 24
Peak memory 207332 kb
Host smart-41146322-c2d4-4794-9528-3e5fecfc765f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3079028519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.3079028519
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3087676452
Short name T1312
Test name
Test status
Simulation time 236559561 ps
CPU time 0.95 seconds
Started Jul 27 07:34:15 PM PDT 24
Finished Jul 27 07:34:16 PM PDT 24
Peak memory 207080 kb
Host smart-99ef0098-57da-458d-bf2e-66672be3c002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30876
76452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3087676452
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.588817847
Short name T1007
Test name
Test status
Simulation time 23293865877 ps
CPU time 28.11 seconds
Started Jul 27 07:34:14 PM PDT 24
Finished Jul 27 07:34:42 PM PDT 24
Peak memory 207340 kb
Host smart-68a5498f-f147-4bac-b8d9-64d8beb9460d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58881
7847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.588817847
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1028625991
Short name T2552
Test name
Test status
Simulation time 3261535297 ps
CPU time 4.61 seconds
Started Jul 27 07:34:17 PM PDT 24
Finished Jul 27 07:34:22 PM PDT 24
Peak memory 207320 kb
Host smart-2ce8d24e-9a41-461e-b171-8b7e31a619bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10286
25991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1028625991
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.4213783409
Short name T2566
Test name
Test status
Simulation time 6696190254 ps
CPU time 202.35 seconds
Started Jul 27 07:34:17 PM PDT 24
Finished Jul 27 07:37:40 PM PDT 24
Peak memory 215496 kb
Host smart-09d91bac-a49f-49d1-9b9e-f1ac17e23312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42137
83409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.4213783409
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1154989852
Short name T1565
Test name
Test status
Simulation time 5919058420 ps
CPU time 169.24 seconds
Started Jul 27 07:34:16 PM PDT 24
Finished Jul 27 07:37:05 PM PDT 24
Peak memory 215520 kb
Host smart-7eec2f71-52aa-46bc-9625-3a1aea9c0516
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1154989852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1154989852
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.667446239
Short name T1851
Test name
Test status
Simulation time 257708685 ps
CPU time 0.96 seconds
Started Jul 27 07:34:13 PM PDT 24
Finished Jul 27 07:34:14 PM PDT 24
Peak memory 207096 kb
Host smart-27f7fb20-396e-4dc8-b266-b794116cfdfd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=667446239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.667446239
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3412001494
Short name T734
Test name
Test status
Simulation time 242550951 ps
CPU time 1.01 seconds
Started Jul 27 07:34:15 PM PDT 24
Finished Jul 27 07:34:16 PM PDT 24
Peak memory 207092 kb
Host smart-b033c2aa-1ba7-4e42-ba21-47e3d2403741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34120
01494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3412001494
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.4069225394
Short name T2862
Test name
Test status
Simulation time 6493996365 ps
CPU time 196.63 seconds
Started Jul 27 07:34:24 PM PDT 24
Finished Jul 27 07:37:40 PM PDT 24
Peak memory 215552 kb
Host smart-ee3f7447-3699-4239-bda4-404fe12281bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40692
25394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.4069225394
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.1122487659
Short name T1204
Test name
Test status
Simulation time 7359046401 ps
CPU time 58.59 seconds
Started Jul 27 07:34:22 PM PDT 24
Finished Jul 27 07:35:20 PM PDT 24
Peak memory 207440 kb
Host smart-453ece13-5c96-40ee-b44d-7a63c971cfa2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1122487659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.1122487659
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.2425042594
Short name T1196
Test name
Test status
Simulation time 157348605 ps
CPU time 0.86 seconds
Started Jul 27 07:34:23 PM PDT 24
Finished Jul 27 07:34:24 PM PDT 24
Peak memory 207156 kb
Host smart-72dd50d4-bf60-4f6a-ab68-33ad409dbfc5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2425042594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.2425042594
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.963334694
Short name T2130
Test name
Test status
Simulation time 154349967 ps
CPU time 0.83 seconds
Started Jul 27 07:34:24 PM PDT 24
Finished Jul 27 07:34:25 PM PDT 24
Peak memory 207100 kb
Host smart-11e8d405-3b41-48c1-baf1-2698b4e20488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96333
4694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.963334694
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3261177081
Short name T1678
Test name
Test status
Simulation time 193347748 ps
CPU time 0.89 seconds
Started Jul 27 07:34:23 PM PDT 24
Finished Jul 27 07:34:24 PM PDT 24
Peak memory 207100 kb
Host smart-d478046e-9973-4fdd-98bf-32c6ec2c577f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32611
77081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3261177081
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.1945009664
Short name T2605
Test name
Test status
Simulation time 164324430 ps
CPU time 0.87 seconds
Started Jul 27 07:34:25 PM PDT 24
Finished Jul 27 07:34:26 PM PDT 24
Peak memory 207132 kb
Host smart-55dd72c2-9e0f-4110-beba-5887a891b2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19450
09664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.1945009664
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1953376698
Short name T472
Test name
Test status
Simulation time 173162074 ps
CPU time 0.84 seconds
Started Jul 27 07:34:22 PM PDT 24
Finished Jul 27 07:34:23 PM PDT 24
Peak memory 207072 kb
Host smart-bc10c257-272b-46ee-b85d-acd422e8af1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19533
76698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1953376698
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1269419630
Short name T2854
Test name
Test status
Simulation time 165266208 ps
CPU time 0.89 seconds
Started Jul 27 07:34:32 PM PDT 24
Finished Jul 27 07:34:33 PM PDT 24
Peak memory 207184 kb
Host smart-68a6d9b4-af91-4c18-9007-8158455d1f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12694
19630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1269419630
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.23304301
Short name T1118
Test name
Test status
Simulation time 197711920 ps
CPU time 1.01 seconds
Started Jul 27 07:34:27 PM PDT 24
Finished Jul 27 07:34:28 PM PDT 24
Peak memory 207148 kb
Host smart-342da261-5b52-4ee0-bb3f-c3b385450356
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=23304301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.23304301
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.175297555
Short name T455
Test name
Test status
Simulation time 240487570 ps
CPU time 1.06 seconds
Started Jul 27 07:34:23 PM PDT 24
Finished Jul 27 07:34:24 PM PDT 24
Peak memory 207112 kb
Host smart-a670eb74-6eed-4e5c-adc3-d84fec826e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17529
7555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.175297555
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2417822255
Short name T2449
Test name
Test status
Simulation time 137265424 ps
CPU time 0.83 seconds
Started Jul 27 07:34:23 PM PDT 24
Finished Jul 27 07:34:24 PM PDT 24
Peak memory 207104 kb
Host smart-1c92000b-df74-4efc-87c8-9a05aed577ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24178
22255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2417822255
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3745192513
Short name T2070
Test name
Test status
Simulation time 35095730 ps
CPU time 0.69 seconds
Started Jul 27 07:34:22 PM PDT 24
Finished Jul 27 07:34:23 PM PDT 24
Peak memory 207156 kb
Host smart-663502d1-77d6-44f1-a568-5e8d01379847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37451
92513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3745192513
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.987307787
Short name T2095
Test name
Test status
Simulation time 21283345942 ps
CPU time 57.08 seconds
Started Jul 27 07:34:23 PM PDT 24
Finished Jul 27 07:35:20 PM PDT 24
Peak memory 215576 kb
Host smart-cece94d5-c20e-4f7d-9164-190756648dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98730
7787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.987307787
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.3118022743
Short name T2202
Test name
Test status
Simulation time 239521421 ps
CPU time 0.96 seconds
Started Jul 27 07:34:24 PM PDT 24
Finished Jul 27 07:34:25 PM PDT 24
Peak memory 207124 kb
Host smart-43d3d912-f38f-406f-b76c-84392c823d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31180
22743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3118022743
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2483903785
Short name T1378
Test name
Test status
Simulation time 161065446 ps
CPU time 0.84 seconds
Started Jul 27 07:34:26 PM PDT 24
Finished Jul 27 07:34:27 PM PDT 24
Peak memory 207100 kb
Host smart-3beb3356-8b84-47e4-bf57-3a1866dc01b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24839
03785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2483903785
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.716675234
Short name T580
Test name
Test status
Simulation time 7115764222 ps
CPU time 116.84 seconds
Started Jul 27 07:34:23 PM PDT 24
Finished Jul 27 07:36:21 PM PDT 24
Peak memory 215596 kb
Host smart-e08bcf92-7c42-4597-9fd6-86bae21831a4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=716675234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.716675234
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.3791790288
Short name T167
Test name
Test status
Simulation time 12868319015 ps
CPU time 73.78 seconds
Started Jul 27 07:34:25 PM PDT 24
Finished Jul 27 07:35:38 PM PDT 24
Peak memory 215588 kb
Host smart-c2a9ae40-08ba-49ac-849d-539ebddce1ef
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3791790288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.3791790288
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.181095341
Short name T976
Test name
Test status
Simulation time 7055609504 ps
CPU time 34.46 seconds
Started Jul 27 07:34:25 PM PDT 24
Finished Jul 27 07:35:00 PM PDT 24
Peak memory 223748 kb
Host smart-b4687ddf-f633-4b2d-a8c5-d1cf5421e95f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=181095341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.181095341
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.4092556043
Short name T2426
Test name
Test status
Simulation time 239500150 ps
CPU time 0.98 seconds
Started Jul 27 07:34:28 PM PDT 24
Finished Jul 27 07:34:29 PM PDT 24
Peak memory 207132 kb
Host smart-df057d14-df64-4b49-b6bf-eaf54edba430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40925
56043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.4092556043
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.165754330
Short name T701
Test name
Test status
Simulation time 173810304 ps
CPU time 0.93 seconds
Started Jul 27 07:34:24 PM PDT 24
Finished Jul 27 07:34:25 PM PDT 24
Peak memory 207124 kb
Host smart-9ee8c433-ae3c-4087-9030-b88d7b8d5a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16575
4330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.165754330
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3582747420
Short name T1714
Test name
Test status
Simulation time 142604490 ps
CPU time 0.82 seconds
Started Jul 27 07:34:26 PM PDT 24
Finished Jul 27 07:34:27 PM PDT 24
Peak memory 207056 kb
Host smart-3c9ef149-64fc-4d2d-9473-dd65de6db589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35827
47420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3582747420
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.2399129644
Short name T70
Test name
Test status
Simulation time 151439156 ps
CPU time 0.81 seconds
Started Jul 27 07:34:24 PM PDT 24
Finished Jul 27 07:34:25 PM PDT 24
Peak memory 207096 kb
Host smart-5c32f8ec-e3e4-4e29-b6d3-f88328edf40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23991
29644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.2399129644
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.2159302660
Short name T1708
Test name
Test status
Simulation time 446861105 ps
CPU time 1.38 seconds
Started Jul 27 07:34:24 PM PDT 24
Finished Jul 27 07:34:26 PM PDT 24
Peak memory 207140 kb
Host smart-e612ad70-a303-4b40-a472-854da68bef8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21593
02660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.2159302660
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.1430709844
Short name T169
Test name
Test status
Simulation time 190577576 ps
CPU time 0.91 seconds
Started Jul 27 07:34:27 PM PDT 24
Finished Jul 27 07:34:28 PM PDT 24
Peak memory 207124 kb
Host smart-57a8a7a1-dea7-429e-86ab-c26ffa22151d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14307
09844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.1430709844
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2445175410
Short name T1209
Test name
Test status
Simulation time 147077012 ps
CPU time 0.85 seconds
Started Jul 27 07:34:28 PM PDT 24
Finished Jul 27 07:34:29 PM PDT 24
Peak memory 207088 kb
Host smart-33220901-76c0-460f-a0a1-abfa8d6d84bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24451
75410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2445175410
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.17409151
Short name T1793
Test name
Test status
Simulation time 146137502 ps
CPU time 0.85 seconds
Started Jul 27 07:34:28 PM PDT 24
Finished Jul 27 07:34:30 PM PDT 24
Peak memory 207108 kb
Host smart-8d5705a8-269c-4dc2-a912-4ced76ad77bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17409
151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.17409151
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3519280876
Short name T2717
Test name
Test status
Simulation time 264101821 ps
CPU time 1.12 seconds
Started Jul 27 07:34:31 PM PDT 24
Finished Jul 27 07:34:32 PM PDT 24
Peak memory 207120 kb
Host smart-f11857c0-a433-4ec5-a928-d22f9b383169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35192
80876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3519280876
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3978614495
Short name T1251
Test name
Test status
Simulation time 5258834043 ps
CPU time 52.1 seconds
Started Jul 27 07:34:27 PM PDT 24
Finished Jul 27 07:35:20 PM PDT 24
Peak memory 216868 kb
Host smart-5974850d-4317-41fa-839c-dcf196c228b3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3978614495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3978614495
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3136644271
Short name T1468
Test name
Test status
Simulation time 171651209 ps
CPU time 0.94 seconds
Started Jul 27 07:34:31 PM PDT 24
Finished Jul 27 07:34:32 PM PDT 24
Peak memory 207124 kb
Host smart-8a74a5c1-1d59-44d8-b3be-8ddc1901371b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31366
44271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3136644271
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.980444785
Short name T2294
Test name
Test status
Simulation time 155555616 ps
CPU time 0.86 seconds
Started Jul 27 07:34:28 PM PDT 24
Finished Jul 27 07:34:29 PM PDT 24
Peak memory 207136 kb
Host smart-5baee6ee-3c3b-44fa-8ccd-f69c7cb6fed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98044
4785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.980444785
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.1388996465
Short name T2236
Test name
Test status
Simulation time 623291312 ps
CPU time 1.66 seconds
Started Jul 27 07:34:27 PM PDT 24
Finished Jul 27 07:34:29 PM PDT 24
Peak memory 207032 kb
Host smart-a2448e7b-8597-411e-9d7e-1e21865bebe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13889
96465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.1388996465
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.1813217245
Short name T765
Test name
Test status
Simulation time 7695771708 ps
CPU time 74.65 seconds
Started Jul 27 07:34:26 PM PDT 24
Finished Jul 27 07:35:41 PM PDT 24
Peak memory 207376 kb
Host smart-51f7287d-a37d-409b-ad71-c292574028bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18132
17245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.1813217245
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.2891757389
Short name T1645
Test name
Test status
Simulation time 4963604402 ps
CPU time 31.81 seconds
Started Jul 27 07:34:11 PM PDT 24
Finished Jul 27 07:34:43 PM PDT 24
Peak memory 207384 kb
Host smart-1f4e1909-335e-4969-9c6b-cb9abc0d976d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891757389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.2891757389
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.2422199969
Short name T1907
Test name
Test status
Simulation time 33725401 ps
CPU time 0.65 seconds
Started Jul 27 07:40:11 PM PDT 24
Finished Jul 27 07:40:12 PM PDT 24
Peak memory 207144 kb
Host smart-ac3b13b0-5be5-443a-a69c-ef2371f80bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2422199969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.2422199969
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3361842822
Short name T769
Test name
Test status
Simulation time 3961778278 ps
CPU time 5.57 seconds
Started Jul 27 07:40:01 PM PDT 24
Finished Jul 27 07:40:06 PM PDT 24
Peak memory 207328 kb
Host smart-9ae97cd8-8ec8-4fd9-98a5-296c5ec4bf03
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361842822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.3361842822
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2060075149
Short name T663
Test name
Test status
Simulation time 13488726927 ps
CPU time 15.9 seconds
Started Jul 27 07:40:00 PM PDT 24
Finished Jul 27 07:40:16 PM PDT 24
Peak memory 207596 kb
Host smart-784beb9b-b63e-43a6-ac04-a27dd4e4f39d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060075149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2060075149
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.2639475959
Short name T674
Test name
Test status
Simulation time 23435965208 ps
CPU time 31.7 seconds
Started Jul 27 07:40:00 PM PDT 24
Finished Jul 27 07:40:32 PM PDT 24
Peak memory 207352 kb
Host smart-59ec126c-89e2-480d-92a8-3a5458b65537
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639475959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_resume.2639475959
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1780266328
Short name T1344
Test name
Test status
Simulation time 169039704 ps
CPU time 0.92 seconds
Started Jul 27 07:40:02 PM PDT 24
Finished Jul 27 07:40:03 PM PDT 24
Peak memory 207088 kb
Host smart-e0c82978-b06d-4342-bf09-58764b0660dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17802
66328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1780266328
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.531323575
Short name T2628
Test name
Test status
Simulation time 154589039 ps
CPU time 0.9 seconds
Started Jul 27 07:40:02 PM PDT 24
Finished Jul 27 07:40:03 PM PDT 24
Peak memory 207088 kb
Host smart-83b965fc-b98a-4143-8ce5-8db322154f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53132
3575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.531323575
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3088190722
Short name T2453
Test name
Test status
Simulation time 272365654 ps
CPU time 1.15 seconds
Started Jul 27 07:40:00 PM PDT 24
Finished Jul 27 07:40:02 PM PDT 24
Peak memory 207120 kb
Host smart-262d7087-24a9-45b7-8cc4-393c861f5d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30881
90722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3088190722
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.873178069
Short name T1684
Test name
Test status
Simulation time 551547372 ps
CPU time 1.65 seconds
Started Jul 27 07:39:59 PM PDT 24
Finished Jul 27 07:40:01 PM PDT 24
Peak memory 207088 kb
Host smart-7f0ddb35-83a9-48c6-89e9-a81ca103f335
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=873178069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.873178069
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.4021826731
Short name T2504
Test name
Test status
Simulation time 18968892666 ps
CPU time 39.98 seconds
Started Jul 27 07:40:01 PM PDT 24
Finished Jul 27 07:40:41 PM PDT 24
Peak memory 207324 kb
Host smart-9ea98f10-cc32-46cf-8c21-a8e7d75a58ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40218
26731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.4021826731
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.4076777845
Short name T2091
Test name
Test status
Simulation time 3646763535 ps
CPU time 23.8 seconds
Started Jul 27 07:40:03 PM PDT 24
Finished Jul 27 07:40:27 PM PDT 24
Peak memory 207368 kb
Host smart-0ef37724-b630-4f6c-8695-a615438026df
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076777845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.4076777845
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1763793273
Short name T2248
Test name
Test status
Simulation time 460126187 ps
CPU time 1.52 seconds
Started Jul 27 07:40:05 PM PDT 24
Finished Jul 27 07:40:06 PM PDT 24
Peak memory 207072 kb
Host smart-12805211-4269-486b-b6e2-ad363f9659ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17637
93273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1763793273
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3925183966
Short name T1467
Test name
Test status
Simulation time 142414579 ps
CPU time 0.82 seconds
Started Jul 27 07:40:05 PM PDT 24
Finished Jul 27 07:40:06 PM PDT 24
Peak memory 207040 kb
Host smart-dbe51157-3423-4883-8d3c-17885283fd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39251
83966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3925183966
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.3068334689
Short name T244
Test name
Test status
Simulation time 59799355 ps
CPU time 0.75 seconds
Started Jul 27 07:40:07 PM PDT 24
Finished Jul 27 07:40:07 PM PDT 24
Peak memory 207100 kb
Host smart-eca85db3-2ffb-4cc0-9f94-545c5ed127ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30683
34689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.3068334689
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.2111453749
Short name T1837
Test name
Test status
Simulation time 885732141 ps
CPU time 2.4 seconds
Started Jul 27 07:40:06 PM PDT 24
Finished Jul 27 07:40:09 PM PDT 24
Peak memory 207356 kb
Host smart-0c65314a-522a-41d2-a6e4-5892b48986ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21114
53749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.2111453749
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3930137872
Short name T2302
Test name
Test status
Simulation time 155360523 ps
CPU time 1.56 seconds
Started Jul 27 07:40:07 PM PDT 24
Finished Jul 27 07:40:09 PM PDT 24
Peak memory 207292 kb
Host smart-88582e8f-e841-4acb-8c66-697680177501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39301
37872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3930137872
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3195780515
Short name T1533
Test name
Test status
Simulation time 274498816 ps
CPU time 1.17 seconds
Started Jul 27 07:40:05 PM PDT 24
Finished Jul 27 07:40:07 PM PDT 24
Peak memory 207244 kb
Host smart-9d4454d7-9152-47c8-a85c-d2047e9587cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3195780515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3195780515
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.786758537
Short name T1098
Test name
Test status
Simulation time 145806561 ps
CPU time 0.84 seconds
Started Jul 27 07:40:06 PM PDT 24
Finished Jul 27 07:40:07 PM PDT 24
Peak memory 207172 kb
Host smart-b755d045-3be3-44f2-aea4-bdddd96b54cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78675
8537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.786758537
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1440871131
Short name T1771
Test name
Test status
Simulation time 182239740 ps
CPU time 0.9 seconds
Started Jul 27 07:40:08 PM PDT 24
Finished Jul 27 07:40:09 PM PDT 24
Peak memory 207124 kb
Host smart-353cdf77-e7f1-4d7f-9a29-082bb933e758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14408
71131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1440871131
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.2536133526
Short name T679
Test name
Test status
Simulation time 7776240977 ps
CPU time 224.7 seconds
Started Jul 27 07:40:09 PM PDT 24
Finished Jul 27 07:43:54 PM PDT 24
Peak memory 215604 kb
Host smart-8684128c-bb84-4983-9500-cb96e7aaeb85
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2536133526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.2536133526
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.3484110568
Short name T762
Test name
Test status
Simulation time 6910629812 ps
CPU time 49.45 seconds
Started Jul 27 07:40:08 PM PDT 24
Finished Jul 27 07:40:57 PM PDT 24
Peak memory 207356 kb
Host smart-4a03e1a1-b9f2-4ecf-88f0-dd7803affde1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3484110568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.3484110568
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1334249441
Short name T2144
Test name
Test status
Simulation time 217140203 ps
CPU time 0.91 seconds
Started Jul 27 07:40:09 PM PDT 24
Finished Jul 27 07:40:10 PM PDT 24
Peak memory 207192 kb
Host smart-c4ae24a1-0def-49d1-b97f-0b5babedc1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13342
49441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1334249441
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.2733501860
Short name T399
Test name
Test status
Simulation time 23336106643 ps
CPU time 35.13 seconds
Started Jul 27 07:40:09 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 207360 kb
Host smart-176b0caa-881b-489a-a80f-32935f08b5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27335
01860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.2733501860
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3204713035
Short name T2052
Test name
Test status
Simulation time 3268471543 ps
CPU time 4.91 seconds
Started Jul 27 07:40:08 PM PDT 24
Finished Jul 27 07:40:13 PM PDT 24
Peak memory 207340 kb
Host smart-90ebdf4d-c6e0-4883-95ee-8fd478fb9077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047
13035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3204713035
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.2933653159
Short name T2345
Test name
Test status
Simulation time 5369045416 ps
CPU time 151.09 seconds
Started Jul 27 07:40:07 PM PDT 24
Finished Jul 27 07:42:38 PM PDT 24
Peak memory 215636 kb
Host smart-b5bcfbb4-6e99-4c44-9d72-621743c77cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29336
53159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.2933653159
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1103282884
Short name T1834
Test name
Test status
Simulation time 3168367785 ps
CPU time 23.43 seconds
Started Jul 27 07:40:05 PM PDT 24
Finished Jul 27 07:40:29 PM PDT 24
Peak memory 215552 kb
Host smart-216daede-cb6e-4703-a2a3-4ba738027b3c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1103282884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1103282884
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2643043901
Short name T1535
Test name
Test status
Simulation time 243158605 ps
CPU time 0.97 seconds
Started Jul 27 07:40:05 PM PDT 24
Finished Jul 27 07:40:06 PM PDT 24
Peak memory 207112 kb
Host smart-5bf5609f-3e53-486e-9315-04a0c4584ad5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2643043901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2643043901
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1698318041
Short name T850
Test name
Test status
Simulation time 206579662 ps
CPU time 0.92 seconds
Started Jul 27 07:40:06 PM PDT 24
Finished Jul 27 07:40:07 PM PDT 24
Peak memory 207168 kb
Host smart-a0010b2f-02c9-4e85-9e32-428efeaee218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16983
18041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1698318041
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.1171661456
Short name T705
Test name
Test status
Simulation time 5479434442 ps
CPU time 42.46 seconds
Started Jul 27 07:40:12 PM PDT 24
Finished Jul 27 07:40:54 PM PDT 24
Peak memory 215572 kb
Host smart-7e9a4280-a9bf-48d6-98b5-11ff8115bb36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11716
61456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.1171661456
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.2942911650
Short name T1908
Test name
Test status
Simulation time 5973526809 ps
CPU time 57.85 seconds
Started Jul 27 07:40:09 PM PDT 24
Finished Jul 27 07:41:07 PM PDT 24
Peak memory 207412 kb
Host smart-5bc8381c-9322-4bc3-8c2e-a8d89c7699de
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2942911650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.2942911650
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.2014611180
Short name T406
Test name
Test status
Simulation time 150971922 ps
CPU time 0.82 seconds
Started Jul 27 07:40:06 PM PDT 24
Finished Jul 27 07:40:06 PM PDT 24
Peak memory 207124 kb
Host smart-4faa616d-4fac-4817-9510-cb55d3fd5b13
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2014611180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.2014611180
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1497394428
Short name T1838
Test name
Test status
Simulation time 149656109 ps
CPU time 0.85 seconds
Started Jul 27 07:40:10 PM PDT 24
Finished Jul 27 07:40:11 PM PDT 24
Peak memory 207060 kb
Host smart-ad3ba0f5-cb4c-4043-9d34-d982001c5467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14973
94428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1497394428
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3804066432
Short name T506
Test name
Test status
Simulation time 198589391 ps
CPU time 1.01 seconds
Started Jul 27 07:40:08 PM PDT 24
Finished Jul 27 07:40:09 PM PDT 24
Peak memory 207096 kb
Host smart-a4598d36-085d-4c10-8ceb-b61e4522035e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38040
66432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3804066432
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1605108977
Short name T2637
Test name
Test status
Simulation time 155176279 ps
CPU time 0.84 seconds
Started Jul 27 07:40:08 PM PDT 24
Finished Jul 27 07:40:09 PM PDT 24
Peak memory 207132 kb
Host smart-04829ddd-fb90-4512-a48e-bad0a1518558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16051
08977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1605108977
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1772414252
Short name T968
Test name
Test status
Simulation time 218938984 ps
CPU time 0.9 seconds
Started Jul 27 07:40:06 PM PDT 24
Finished Jul 27 07:40:07 PM PDT 24
Peak memory 207032 kb
Host smart-614b7651-0eeb-4f3a-a7f8-27f287c578ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17724
14252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1772414252
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2263140766
Short name T689
Test name
Test status
Simulation time 148650310 ps
CPU time 0.81 seconds
Started Jul 27 07:40:09 PM PDT 24
Finished Jul 27 07:40:10 PM PDT 24
Peak memory 207140 kb
Host smart-d902385a-7cc3-4730-8e78-50fb5918ace2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22631
40766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2263140766
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.3758088954
Short name T419
Test name
Test status
Simulation time 234159720 ps
CPU time 1.02 seconds
Started Jul 27 07:40:05 PM PDT 24
Finished Jul 27 07:40:06 PM PDT 24
Peak memory 207128 kb
Host smart-d5ec253b-1d96-4584-9b68-757e93cc53a3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3758088954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.3758088954
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.165806752
Short name T1030
Test name
Test status
Simulation time 179079129 ps
CPU time 0.91 seconds
Started Jul 27 07:40:07 PM PDT 24
Finished Jul 27 07:40:08 PM PDT 24
Peak memory 207028 kb
Host smart-9ea2b98a-ae6e-40a9-b4d8-59173d170e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16580
6752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.165806752
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2193522307
Short name T1720
Test name
Test status
Simulation time 52741351 ps
CPU time 0.67 seconds
Started Jul 27 07:40:08 PM PDT 24
Finished Jul 27 07:40:09 PM PDT 24
Peak memory 207064 kb
Host smart-a28ab195-fd05-4281-a9e3-8cd1fddbbe42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21935
22307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2193522307
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.767644645
Short name T1821
Test name
Test status
Simulation time 14023504896 ps
CPU time 34.6 seconds
Started Jul 27 07:40:08 PM PDT 24
Finished Jul 27 07:40:42 PM PDT 24
Peak memory 215636 kb
Host smart-41ff0d4c-8fba-412b-9caf-ddcbc89b8b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76764
4645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.767644645
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.325036611
Short name T2427
Test name
Test status
Simulation time 200008652 ps
CPU time 0.95 seconds
Started Jul 27 07:40:17 PM PDT 24
Finished Jul 27 07:40:18 PM PDT 24
Peak memory 207024 kb
Host smart-57ab7f56-1800-4d55-9313-8eaa3135ec15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32503
6611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.325036611
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2830206708
Short name T2077
Test name
Test status
Simulation time 178285095 ps
CPU time 0.89 seconds
Started Jul 27 07:40:10 PM PDT 24
Finished Jul 27 07:40:11 PM PDT 24
Peak memory 207072 kb
Host smart-42fdf24f-3352-46cf-94d4-2f3569810258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28302
06708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2830206708
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.1208334282
Short name T998
Test name
Test status
Simulation time 198629834 ps
CPU time 0.94 seconds
Started Jul 27 07:40:05 PM PDT 24
Finished Jul 27 07:40:06 PM PDT 24
Peak memory 207212 kb
Host smart-74afd04d-150e-4933-a63a-87113a381741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12083
34282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.1208334282
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.2463367631
Short name T2125
Test name
Test status
Simulation time 153360860 ps
CPU time 0.87 seconds
Started Jul 27 07:40:05 PM PDT 24
Finished Jul 27 07:40:06 PM PDT 24
Peak memory 207016 kb
Host smart-edcd6fdb-2b05-44f8-91cf-7045a657ed9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24633
67631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.2463367631
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.4061558821
Short name T714
Test name
Test status
Simulation time 182163945 ps
CPU time 0.86 seconds
Started Jul 27 07:40:06 PM PDT 24
Finished Jul 27 07:40:07 PM PDT 24
Peak memory 207020 kb
Host smart-98a1f274-00e8-4bc6-a99f-6049be8cbc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40615
58821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.4061558821
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.737833886
Short name T1515
Test name
Test status
Simulation time 170617472 ps
CPU time 0.85 seconds
Started Jul 27 07:40:17 PM PDT 24
Finished Jul 27 07:40:18 PM PDT 24
Peak memory 206992 kb
Host smart-4abbda3b-5342-4a94-9715-b5752980064f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73783
3886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.737833886
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.4086809625
Short name T938
Test name
Test status
Simulation time 185072097 ps
CPU time 0.88 seconds
Started Jul 27 07:40:06 PM PDT 24
Finished Jul 27 07:40:07 PM PDT 24
Peak memory 207148 kb
Host smart-bc71ffa6-cb0d-490b-b508-fc13fc13c894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40868
09625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.4086809625
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2559731600
Short name T2635
Test name
Test status
Simulation time 197638118 ps
CPU time 0.98 seconds
Started Jul 27 07:40:09 PM PDT 24
Finished Jul 27 07:40:10 PM PDT 24
Peak memory 207108 kb
Host smart-d800e025-9b36-4ad1-861c-0b719c1b45be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25597
31600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2559731600
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2131928234
Short name T2569
Test name
Test status
Simulation time 5036467635 ps
CPU time 38.32 seconds
Started Jul 27 07:40:12 PM PDT 24
Finished Jul 27 07:40:50 PM PDT 24
Peak memory 217040 kb
Host smart-c6a3879d-9daa-488c-9e86-bf19cac525c4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2131928234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2131928234
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3105456867
Short name T1718
Test name
Test status
Simulation time 177460086 ps
CPU time 0.84 seconds
Started Jul 27 07:40:10 PM PDT 24
Finished Jul 27 07:40:11 PM PDT 24
Peak memory 207120 kb
Host smart-b04d45ed-1a9a-475b-ba9c-2086f1245025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31054
56867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3105456867
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3718390358
Short name T2138
Test name
Test status
Simulation time 160849843 ps
CPU time 0.9 seconds
Started Jul 27 07:40:07 PM PDT 24
Finished Jul 27 07:40:08 PM PDT 24
Peak memory 207120 kb
Host smart-d9a660e3-df58-4c85-811e-c1eadf2122b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37183
90358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3718390358
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.548665749
Short name T2824
Test name
Test status
Simulation time 1425621218 ps
CPU time 3.18 seconds
Started Jul 27 07:40:12 PM PDT 24
Finished Jul 27 07:40:15 PM PDT 24
Peak memory 207288 kb
Host smart-5e65d6f8-f19f-4ea6-a77b-80d078029de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54866
5749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.548665749
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.4001159492
Short name T578
Test name
Test status
Simulation time 4559361426 ps
CPU time 46.39 seconds
Started Jul 27 07:40:09 PM PDT 24
Finished Jul 27 07:40:56 PM PDT 24
Peak memory 216784 kb
Host smart-6f4c1bce-cb05-4974-8ea2-cd24c54abc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40011
59492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.4001159492
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.2898811265
Short name T863
Test name
Test status
Simulation time 1533166001 ps
CPU time 10.13 seconds
Started Jul 27 07:40:08 PM PDT 24
Finished Jul 27 07:40:18 PM PDT 24
Peak memory 207376 kb
Host smart-cf70d9bf-1b96-4d6c-ad09-2fc17a319ea5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898811265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.2898811265
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.1647027570
Short name T2640
Test name
Test status
Simulation time 36858388 ps
CPU time 0.69 seconds
Started Jul 27 07:40:20 PM PDT 24
Finished Jul 27 07:40:21 PM PDT 24
Peak memory 207180 kb
Host smart-104cda29-3e4b-4725-b93f-d4bc03d33b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1647027570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.1647027570
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3810152042
Short name T2464
Test name
Test status
Simulation time 3988861983 ps
CPU time 5.77 seconds
Started Jul 27 07:40:10 PM PDT 24
Finished Jul 27 07:40:15 PM PDT 24
Peak memory 207364 kb
Host smart-538a9908-38b6-4257-99d5-1d408a4bbeec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810152042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.3810152042
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3447752935
Short name T1959
Test name
Test status
Simulation time 13356097192 ps
CPU time 14.68 seconds
Started Jul 27 07:40:09 PM PDT 24
Finished Jul 27 07:40:24 PM PDT 24
Peak memory 207508 kb
Host smart-9626c975-849d-4728-a84d-2ad6667fbba1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447752935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3447752935
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3658838078
Short name T7
Test name
Test status
Simulation time 23344736189 ps
CPU time 33.01 seconds
Started Jul 27 07:40:17 PM PDT 24
Finished Jul 27 07:40:50 PM PDT 24
Peak memory 207276 kb
Host smart-18bd9681-0831-4d54-bab9-13c806f51296
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658838078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.3658838078
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.687641478
Short name T2809
Test name
Test status
Simulation time 183903956 ps
CPU time 0.98 seconds
Started Jul 27 07:40:20 PM PDT 24
Finished Jul 27 07:40:21 PM PDT 24
Peak memory 207132 kb
Host smart-09d338d8-da21-4997-9741-0a283820672e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68764
1478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.687641478
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.3250996157
Short name T2796
Test name
Test status
Simulation time 141192546 ps
CPU time 0.82 seconds
Started Jul 27 07:40:12 PM PDT 24
Finished Jul 27 07:40:13 PM PDT 24
Peak memory 207108 kb
Host smart-5d6d3424-19cb-4182-91b2-e5944e166582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32509
96157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3250996157
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.329544590
Short name T1095
Test name
Test status
Simulation time 208934873 ps
CPU time 0.96 seconds
Started Jul 27 07:40:17 PM PDT 24
Finished Jul 27 07:40:18 PM PDT 24
Peak memory 207092 kb
Host smart-dc032a27-5f79-41ef-846e-58cec104e5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32954
4590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.329544590
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3405306862
Short name T1032
Test name
Test status
Simulation time 868544187 ps
CPU time 2.14 seconds
Started Jul 27 07:40:16 PM PDT 24
Finished Jul 27 07:40:18 PM PDT 24
Peak memory 207316 kb
Host smart-fef8b6b6-0d79-4b71-ba54-ef454cfef85e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3405306862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3405306862
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.2639579616
Short name T1321
Test name
Test status
Simulation time 18152351402 ps
CPU time 40 seconds
Started Jul 27 07:40:10 PM PDT 24
Finished Jul 27 07:40:50 PM PDT 24
Peak memory 207380 kb
Host smart-9406a683-0d5a-43d2-8c9d-ce666b75a074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26395
79616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.2639579616
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.1767148176
Short name T572
Test name
Test status
Simulation time 162431382 ps
CPU time 0.84 seconds
Started Jul 27 07:40:18 PM PDT 24
Finished Jul 27 07:40:19 PM PDT 24
Peak memory 206996 kb
Host smart-52e23ed7-00f7-4a07-b4e2-a77690ccf817
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767148176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.1767148176
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.4149991991
Short name T287
Test name
Test status
Simulation time 453074309 ps
CPU time 1.5 seconds
Started Jul 27 07:40:10 PM PDT 24
Finished Jul 27 07:40:12 PM PDT 24
Peak memory 206976 kb
Host smart-af4a7c86-d18b-4705-b8a1-cf28c662d5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41499
91991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.4149991991
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2666987978
Short name T37
Test name
Test status
Simulation time 135366233 ps
CPU time 0.81 seconds
Started Jul 27 07:40:14 PM PDT 24
Finished Jul 27 07:40:14 PM PDT 24
Peak memory 207056 kb
Host smart-12d1b730-e2ab-468b-be50-8ff225fa474c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26669
87978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2666987978
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3621676550
Short name T568
Test name
Test status
Simulation time 42001290 ps
CPU time 0.68 seconds
Started Jul 27 07:40:12 PM PDT 24
Finished Jul 27 07:40:13 PM PDT 24
Peak memory 207052 kb
Host smart-eaf986e8-27f9-4b8f-89dd-6f91e6a55ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36216
76550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3621676550
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.1036655586
Short name T1006
Test name
Test status
Simulation time 857513167 ps
CPU time 2.23 seconds
Started Jul 27 07:40:12 PM PDT 24
Finished Jul 27 07:40:14 PM PDT 24
Peak memory 207276 kb
Host smart-52d9bcb4-ef5c-4836-a65c-1299734564af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10366
55586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1036655586
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3265300592
Short name T364
Test name
Test status
Simulation time 440535866 ps
CPU time 2.96 seconds
Started Jul 27 07:40:12 PM PDT 24
Finished Jul 27 07:40:15 PM PDT 24
Peak memory 207252 kb
Host smart-bf811687-2cd6-46e3-a082-053f2a154eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32653
00592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3265300592
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2861824250
Short name T2830
Test name
Test status
Simulation time 229783177 ps
CPU time 1.24 seconds
Started Jul 27 07:40:18 PM PDT 24
Finished Jul 27 07:40:19 PM PDT 24
Peak memory 215516 kb
Host smart-4f1e7674-d2a1-4258-b6cb-74cc9c7b53ca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2861824250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2861824250
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3256490081
Short name T493
Test name
Test status
Simulation time 158642619 ps
CPU time 0.84 seconds
Started Jul 27 07:40:13 PM PDT 24
Finished Jul 27 07:40:14 PM PDT 24
Peak memory 207188 kb
Host smart-f4049585-4fcb-4f30-a01a-f8c1a0306f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32564
90081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3256490081
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2398278908
Short name T2541
Test name
Test status
Simulation time 297340474 ps
CPU time 1.13 seconds
Started Jul 27 07:40:10 PM PDT 24
Finished Jul 27 07:40:12 PM PDT 24
Peak memory 207200 kb
Host smart-d5aefa64-280f-45af-abc2-a1232cbc2bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23982
78908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2398278908
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.2351498936
Short name T2067
Test name
Test status
Simulation time 5455213353 ps
CPU time 56.29 seconds
Started Jul 27 07:40:12 PM PDT 24
Finished Jul 27 07:41:09 PM PDT 24
Peak memory 216872 kb
Host smart-77fedbb4-e3fb-4bee-a90a-b1856de5ca75
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2351498936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.2351498936
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.1829761112
Short name T2636
Test name
Test status
Simulation time 8982891482 ps
CPU time 113.27 seconds
Started Jul 27 07:40:13 PM PDT 24
Finished Jul 27 07:42:06 PM PDT 24
Peak memory 207352 kb
Host smart-c00f07a9-a77a-408c-95ce-324bb59e1506
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1829761112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.1829761112
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.4110019691
Short name T1328
Test name
Test status
Simulation time 213131539 ps
CPU time 1.01 seconds
Started Jul 27 07:40:13 PM PDT 24
Finished Jul 27 07:40:14 PM PDT 24
Peak memory 207128 kb
Host smart-2da3c82c-bc4f-47b8-84ac-f9a2d4de1115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41100
19691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.4110019691
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.411350372
Short name T1823
Test name
Test status
Simulation time 23342361271 ps
CPU time 27.21 seconds
Started Jul 27 07:40:12 PM PDT 24
Finished Jul 27 07:40:39 PM PDT 24
Peak memory 207356 kb
Host smart-292f7aa9-194a-4139-abc3-4077119afd6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41135
0372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.411350372
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.955110992
Short name T1366
Test name
Test status
Simulation time 3324729986 ps
CPU time 5.73 seconds
Started Jul 27 07:40:14 PM PDT 24
Finished Jul 27 07:40:20 PM PDT 24
Peak memory 207308 kb
Host smart-2692d3e0-29c0-4a48-97f7-25b52b9442fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95511
0992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.955110992
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2922804277
Short name T2748
Test name
Test status
Simulation time 8192981053 ps
CPU time 229.89 seconds
Started Jul 27 07:40:12 PM PDT 24
Finished Jul 27 07:44:02 PM PDT 24
Peak memory 215536 kb
Host smart-b59c1313-7c36-49d0-9e11-45ee54e2735f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29228
04277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2922804277
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.535109804
Short name T1623
Test name
Test status
Simulation time 7142650089 ps
CPU time 219.62 seconds
Started Jul 27 07:40:17 PM PDT 24
Finished Jul 27 07:43:56 PM PDT 24
Peak memory 215528 kb
Host smart-0145ce01-f6c0-40f7-a42b-369419dfb830
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=535109804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.535109804
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2167643775
Short name T1495
Test name
Test status
Simulation time 246273773 ps
CPU time 1.06 seconds
Started Jul 27 07:40:12 PM PDT 24
Finished Jul 27 07:40:13 PM PDT 24
Peak memory 207156 kb
Host smart-dcd45c91-7f37-413f-a2b1-01d850e87e40
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2167643775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2167643775
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1570799164
Short name T570
Test name
Test status
Simulation time 191719598 ps
CPU time 1.18 seconds
Started Jul 27 07:40:09 PM PDT 24
Finished Jul 27 07:40:11 PM PDT 24
Peak memory 207100 kb
Host smart-1b587a6e-3e78-4f3a-a392-13c92497c65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15707
99164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1570799164
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.584735738
Short name T1654
Test name
Test status
Simulation time 4339521912 ps
CPU time 46.31 seconds
Started Jul 27 07:40:13 PM PDT 24
Finished Jul 27 07:41:00 PM PDT 24
Peak memory 216792 kb
Host smart-2b7bd315-f889-43c2-9682-6a59f16edb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58473
5738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.584735738
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.676017758
Short name T1185
Test name
Test status
Simulation time 3422742550 ps
CPU time 34.65 seconds
Started Jul 27 07:40:20 PM PDT 24
Finished Jul 27 07:40:54 PM PDT 24
Peak memory 217016 kb
Host smart-0bb70bfa-6f92-45ae-b11d-9ff108940552
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=676017758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.676017758
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.94230555
Short name T2512
Test name
Test status
Simulation time 174811714 ps
CPU time 0.9 seconds
Started Jul 27 07:40:13 PM PDT 24
Finished Jul 27 07:40:14 PM PDT 24
Peak memory 207128 kb
Host smart-89ee208d-c57b-4af1-9434-3cfcb0130fc0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=94230555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.94230555
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1050298550
Short name T1332
Test name
Test status
Simulation time 145574012 ps
CPU time 0.83 seconds
Started Jul 27 07:40:13 PM PDT 24
Finished Jul 27 07:40:14 PM PDT 24
Peak memory 207220 kb
Host smart-b0cb9b62-58c2-4c04-ae2d-f8f7c2319d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10502
98550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1050298550
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.661875367
Short name T143
Test name
Test status
Simulation time 207779893 ps
CPU time 0.96 seconds
Started Jul 27 07:40:15 PM PDT 24
Finished Jul 27 07:40:16 PM PDT 24
Peak memory 207120 kb
Host smart-5d467533-fe5c-469a-8197-0b2f84e1d1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66187
5367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.661875367
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.1031222413
Short name T1972
Test name
Test status
Simulation time 175374532 ps
CPU time 0.92 seconds
Started Jul 27 07:40:16 PM PDT 24
Finished Jul 27 07:40:17 PM PDT 24
Peak memory 207092 kb
Host smart-a13f2e97-d659-4b2c-92f7-abded4c56005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10312
22413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.1031222413
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2194132381
Short name T1866
Test name
Test status
Simulation time 187293123 ps
CPU time 0.92 seconds
Started Jul 27 07:40:11 PM PDT 24
Finished Jul 27 07:40:12 PM PDT 24
Peak memory 207100 kb
Host smart-8f5b494b-9a5e-41c4-a2b4-59c171917a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21941
32381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2194132381
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.740683592
Short name T432
Test name
Test status
Simulation time 172844236 ps
CPU time 0.91 seconds
Started Jul 27 07:40:20 PM PDT 24
Finished Jul 27 07:40:21 PM PDT 24
Peak memory 207132 kb
Host smart-b40b7696-c3ee-4beb-9d5b-78d18e3ace39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74068
3592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.740683592
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1165428277
Short name T1809
Test name
Test status
Simulation time 190829644 ps
CPU time 0.88 seconds
Started Jul 27 07:40:14 PM PDT 24
Finished Jul 27 07:40:15 PM PDT 24
Peak memory 207084 kb
Host smart-767aa2d1-3a92-412c-9c1f-8f86a2e4f70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11654
28277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1165428277
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.3066545434
Short name T2055
Test name
Test status
Simulation time 272153156 ps
CPU time 1.09 seconds
Started Jul 27 07:40:18 PM PDT 24
Finished Jul 27 07:40:19 PM PDT 24
Peak memory 207132 kb
Host smart-278e9843-3e93-4cb8-9763-6d7c8b47b3c9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3066545434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.3066545434
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.410867394
Short name T2554
Test name
Test status
Simulation time 137492053 ps
CPU time 0.83 seconds
Started Jul 27 07:40:17 PM PDT 24
Finished Jul 27 07:40:18 PM PDT 24
Peak memory 206984 kb
Host smart-f8d4b65b-b7e5-41ca-aa51-066cdb57eea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41086
7394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.410867394
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.3025707058
Short name T279
Test name
Test status
Simulation time 16203277995 ps
CPU time 39.29 seconds
Started Jul 27 07:40:17 PM PDT 24
Finished Jul 27 07:40:56 PM PDT 24
Peak memory 215500 kb
Host smart-e298e188-eecb-4f9b-977b-402770394274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30257
07058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3025707058
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1495916705
Short name T1360
Test name
Test status
Simulation time 193699750 ps
CPU time 0.98 seconds
Started Jul 27 07:40:17 PM PDT 24
Finished Jul 27 07:40:18 PM PDT 24
Peak memory 207072 kb
Host smart-f0252b6d-aac2-4d7e-9da5-ea2ee3f7c91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14959
16705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1495916705
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.3775663741
Short name T2788
Test name
Test status
Simulation time 288924114 ps
CPU time 1.08 seconds
Started Jul 27 07:40:19 PM PDT 24
Finished Jul 27 07:40:20 PM PDT 24
Peak memory 207112 kb
Host smart-5624bf09-0c1d-4a09-9b35-41fa5eb6c3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37756
63741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3775663741
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.3921903529
Short name T356
Test name
Test status
Simulation time 182831107 ps
CPU time 0.9 seconds
Started Jul 27 07:40:18 PM PDT 24
Finished Jul 27 07:40:19 PM PDT 24
Peak memory 207104 kb
Host smart-4073496e-7658-4262-a3c3-293726fb5ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39219
03529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.3921903529
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.2344154480
Short name T1782
Test name
Test status
Simulation time 191134034 ps
CPU time 0.9 seconds
Started Jul 27 07:40:18 PM PDT 24
Finished Jul 27 07:40:19 PM PDT 24
Peak memory 207104 kb
Host smart-2462c2f0-cefd-4427-bac2-1d98b166f0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23441
54480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.2344154480
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3766296599
Short name T2711
Test name
Test status
Simulation time 198717705 ps
CPU time 0.91 seconds
Started Jul 27 07:40:17 PM PDT 24
Finished Jul 27 07:40:18 PM PDT 24
Peak memory 206988 kb
Host smart-a0244ead-ed47-478d-b47e-f9a90a1a7ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37662
96599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3766296599
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.973735397
Short name T1129
Test name
Test status
Simulation time 218234075 ps
CPU time 0.9 seconds
Started Jul 27 07:40:18 PM PDT 24
Finished Jul 27 07:40:19 PM PDT 24
Peak memory 207072 kb
Host smart-fbcdc335-50b3-483c-a5a6-1ef1eb1db70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97373
5397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.973735397
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4117252521
Short name T671
Test name
Test status
Simulation time 153692784 ps
CPU time 0.83 seconds
Started Jul 27 07:40:22 PM PDT 24
Finished Jul 27 07:40:23 PM PDT 24
Peak memory 207104 kb
Host smart-d4abf779-2af0-444a-bef5-5d751c4dff1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41172
52521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4117252521
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2418945042
Short name T2204
Test name
Test status
Simulation time 178486473 ps
CPU time 0.9 seconds
Started Jul 27 07:40:16 PM PDT 24
Finished Jul 27 07:40:17 PM PDT 24
Peak memory 207016 kb
Host smart-210406d3-822b-426b-8445-32c828ac5bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24189
45042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2418945042
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.2219431937
Short name T526
Test name
Test status
Simulation time 6140897559 ps
CPU time 45.36 seconds
Started Jul 27 07:40:17 PM PDT 24
Finished Jul 27 07:41:03 PM PDT 24
Peak memory 215576 kb
Host smart-68d31c58-1e6f-487a-af31-3cb4e9785ef6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2219431937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.2219431937
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3537227278
Short name T2379
Test name
Test status
Simulation time 172723452 ps
CPU time 0.88 seconds
Started Jul 27 07:40:17 PM PDT 24
Finished Jul 27 07:40:18 PM PDT 24
Peak memory 207164 kb
Host smart-6ff4778e-b12d-42b5-982c-66adc93e3117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35372
27278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3537227278
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2228297488
Short name T1234
Test name
Test status
Simulation time 147118742 ps
CPU time 0.81 seconds
Started Jul 27 07:40:18 PM PDT 24
Finished Jul 27 07:40:19 PM PDT 24
Peak memory 207220 kb
Host smart-fda482ca-53dd-4044-944e-b88f6de50874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22282
97488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2228297488
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2556400621
Short name T2567
Test name
Test status
Simulation time 341985537 ps
CPU time 1.32 seconds
Started Jul 27 07:40:19 PM PDT 24
Finished Jul 27 07:40:21 PM PDT 24
Peak memory 207108 kb
Host smart-749bc731-aea8-4a94-8b4c-4b3ec89583ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25564
00621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2556400621
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1683738597
Short name T2624
Test name
Test status
Simulation time 4660567455 ps
CPU time 46.86 seconds
Started Jul 27 07:40:19 PM PDT 24
Finished Jul 27 07:41:06 PM PDT 24
Peak memory 217056 kb
Host smart-8df29075-1519-4e25-8a54-6bee019d25bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16837
38597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1683738597
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.2076403078
Short name T2506
Test name
Test status
Simulation time 3447536929 ps
CPU time 31.54 seconds
Started Jul 27 07:40:11 PM PDT 24
Finished Jul 27 07:40:42 PM PDT 24
Peak memory 207408 kb
Host smart-96d7c9e3-ed0e-4546-8ea4-d6a146af7f33
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076403078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.2076403078
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.3124059304
Short name T2142
Test name
Test status
Simulation time 41421283 ps
CPU time 0.65 seconds
Started Jul 27 07:40:35 PM PDT 24
Finished Jul 27 07:40:36 PM PDT 24
Peak memory 207160 kb
Host smart-776210b4-f184-432f-835b-fb272c66f823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3124059304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.3124059304
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.106563222
Short name T790
Test name
Test status
Simulation time 4455057255 ps
CPU time 6.18 seconds
Started Jul 27 07:40:18 PM PDT 24
Finished Jul 27 07:40:24 PM PDT 24
Peak memory 207384 kb
Host smart-ad2df1f9-69e4-44c3-8456-fed08d103693
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106563222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_ao
n_wake_disconnect.106563222
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.2988952124
Short name T2684
Test name
Test status
Simulation time 13381786809 ps
CPU time 14.94 seconds
Started Jul 27 07:40:21 PM PDT 24
Finished Jul 27 07:40:36 PM PDT 24
Peak memory 207392 kb
Host smart-9ab284fe-375f-4a3c-af14-0fd224682993
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988952124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2988952124
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1684244332
Short name T2774
Test name
Test status
Simulation time 216971337 ps
CPU time 0.94 seconds
Started Jul 27 07:40:20 PM PDT 24
Finished Jul 27 07:40:21 PM PDT 24
Peak memory 207132 kb
Host smart-d143fe30-18b0-44e2-8407-4c28fd79dacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16842
44332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1684244332
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.3741402640
Short name T2103
Test name
Test status
Simulation time 153134026 ps
CPU time 0.84 seconds
Started Jul 27 07:40:19 PM PDT 24
Finished Jul 27 07:40:20 PM PDT 24
Peak memory 207056 kb
Host smart-d4a409e2-afc4-4ef9-9d0f-99d0e73bdf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37414
02640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.3741402640
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.711431103
Short name T1664
Test name
Test status
Simulation time 573609351 ps
CPU time 1.78 seconds
Started Jul 27 07:40:16 PM PDT 24
Finished Jul 27 07:40:18 PM PDT 24
Peak memory 207140 kb
Host smart-dffdb3dd-6dd0-42c9-887e-8550f3fa1880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71143
1103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.711431103
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_device_address.1019240683
Short name T1885
Test name
Test status
Simulation time 9881931017 ps
CPU time 21.98 seconds
Started Jul 27 07:40:30 PM PDT 24
Finished Jul 27 07:40:52 PM PDT 24
Peak memory 207400 kb
Host smart-b3356abc-9d64-4a27-ae2f-d93c6f5d589b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10192
40683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.1019240683
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.2844697621
Short name T477
Test name
Test status
Simulation time 1074889749 ps
CPU time 9.32 seconds
Started Jul 27 07:40:27 PM PDT 24
Finished Jul 27 07:40:37 PM PDT 24
Peak memory 207304 kb
Host smart-f208654e-16fd-43ab-8f20-c520c064cc5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844697621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.2844697621
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.2518957792
Short name T1420
Test name
Test status
Simulation time 385533595 ps
CPU time 1.43 seconds
Started Jul 27 07:40:27 PM PDT 24
Finished Jul 27 07:40:29 PM PDT 24
Peak memory 207108 kb
Host smart-3ed9f6b5-0142-4a0a-a6bf-5b306555fb56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25189
57792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.2518957792
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.2238311044
Short name T2725
Test name
Test status
Simulation time 142550040 ps
CPU time 0.8 seconds
Started Jul 27 07:40:24 PM PDT 24
Finished Jul 27 07:40:25 PM PDT 24
Peak memory 206984 kb
Host smart-d3f1816c-de92-4365-bb89-3e9bed2ada92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22383
11044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.2238311044
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2976132205
Short name T2850
Test name
Test status
Simulation time 43201717 ps
CPU time 0.7 seconds
Started Jul 27 07:40:25 PM PDT 24
Finished Jul 27 07:40:26 PM PDT 24
Peak memory 207108 kb
Host smart-6f2f9fb3-0252-44bc-8b17-decd5b6fb10b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29761
32205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2976132205
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1516777746
Short name T2477
Test name
Test status
Simulation time 1006450967 ps
CPU time 2.55 seconds
Started Jul 27 07:40:27 PM PDT 24
Finished Jul 27 07:40:30 PM PDT 24
Peak memory 207212 kb
Host smart-92479bf7-e447-4921-bc40-897faa9ac1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15167
77746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1516777746
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1435329727
Short name T916
Test name
Test status
Simulation time 222948491 ps
CPU time 1.65 seconds
Started Jul 27 07:40:27 PM PDT 24
Finished Jul 27 07:40:29 PM PDT 24
Peak memory 207232 kb
Host smart-a52bedf1-70df-4073-b348-028b062bd743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
29727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1435329727
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.93989736
Short name T2340
Test name
Test status
Simulation time 200270100 ps
CPU time 1.09 seconds
Started Jul 27 07:40:28 PM PDT 24
Finished Jul 27 07:40:29 PM PDT 24
Peak memory 207284 kb
Host smart-7991d3d0-e76e-4365-ae2a-9a5a8a27b915
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=93989736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.93989736
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1125481378
Short name T1039
Test name
Test status
Simulation time 167160052 ps
CPU time 0.89 seconds
Started Jul 27 07:40:24 PM PDT 24
Finished Jul 27 07:40:25 PM PDT 24
Peak memory 207188 kb
Host smart-825cac72-98f2-4b98-8ec3-375679797a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11254
81378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1125481378
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2825347273
Short name T604
Test name
Test status
Simulation time 152943181 ps
CPU time 0.84 seconds
Started Jul 27 07:40:24 PM PDT 24
Finished Jul 27 07:40:25 PM PDT 24
Peak memory 207120 kb
Host smart-01dab9ef-ac9f-49bf-84d0-18bba282ae21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28253
47273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2825347273
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.1393085565
Short name T1620
Test name
Test status
Simulation time 7149903114 ps
CPU time 69.81 seconds
Started Jul 27 07:40:24 PM PDT 24
Finished Jul 27 07:41:34 PM PDT 24
Peak memory 216960 kb
Host smart-0ac8f93a-6b34-4fea-a12f-5878b3d4dabb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1393085565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1393085565
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.4276914123
Short name T2819
Test name
Test status
Simulation time 172886342 ps
CPU time 0.91 seconds
Started Jul 27 07:40:24 PM PDT 24
Finished Jul 27 07:40:25 PM PDT 24
Peak memory 207128 kb
Host smart-cda96d36-3ffb-4cf3-aa51-43316a45c5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42769
14123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.4276914123
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.1862445317
Short name T2250
Test name
Test status
Simulation time 23333249060 ps
CPU time 27.33 seconds
Started Jul 27 07:40:24 PM PDT 24
Finished Jul 27 07:40:51 PM PDT 24
Peak memory 207392 kb
Host smart-974ee214-854f-441f-b76b-dd2bc53d3f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18624
45317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.1862445317
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1244186528
Short name T2307
Test name
Test status
Simulation time 3276976585 ps
CPU time 4.6 seconds
Started Jul 27 07:40:28 PM PDT 24
Finished Jul 27 07:40:32 PM PDT 24
Peak memory 207388 kb
Host smart-12046996-276a-4497-ad06-79bde16be789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12441
86528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1244186528
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.2872858371
Short name T709
Test name
Test status
Simulation time 7131041368 ps
CPU time 213.59 seconds
Started Jul 27 07:40:26 PM PDT 24
Finished Jul 27 07:44:00 PM PDT 24
Peak memory 215596 kb
Host smart-91783dc6-0403-41c4-b772-7c972d6efeef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28728
58371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2872858371
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.4053842400
Short name T2733
Test name
Test status
Simulation time 4058633730 ps
CPU time 40.32 seconds
Started Jul 27 07:40:26 PM PDT 24
Finished Jul 27 07:41:06 PM PDT 24
Peak memory 207320 kb
Host smart-c8fc2096-608f-4207-ac5d-8e926d13c8f5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4053842400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.4053842400
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.2152237587
Short name T1725
Test name
Test status
Simulation time 253639725 ps
CPU time 0.98 seconds
Started Jul 27 07:40:25 PM PDT 24
Finished Jul 27 07:40:26 PM PDT 24
Peak memory 207148 kb
Host smart-0a5ca4b5-c31b-4a28-924d-c104f4990a1e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2152237587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.2152237587
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1097259699
Short name T972
Test name
Test status
Simulation time 188943301 ps
CPU time 0.93 seconds
Started Jul 27 07:40:25 PM PDT 24
Finished Jul 27 07:40:26 PM PDT 24
Peak memory 207196 kb
Host smart-8113e615-b597-4361-aad4-a1c883b7bd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10972
59699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1097259699
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.3765774581
Short name T1062
Test name
Test status
Simulation time 4635509345 ps
CPU time 37.03 seconds
Started Jul 27 07:40:27 PM PDT 24
Finished Jul 27 07:41:04 PM PDT 24
Peak memory 217112 kb
Host smart-483a9c7c-6f2a-4ba0-89e9-85158093705f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37657
74581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.3765774581
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1453814633
Short name T2064
Test name
Test status
Simulation time 4825906190 ps
CPU time 138.85 seconds
Started Jul 27 07:40:25 PM PDT 24
Finished Jul 27 07:42:44 PM PDT 24
Peak memory 215760 kb
Host smart-793e34cb-d688-4e94-8ee8-4bcb3a2e253e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1453814633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1453814633
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2809049210
Short name T1925
Test name
Test status
Simulation time 158845547 ps
CPU time 0.83 seconds
Started Jul 27 07:40:26 PM PDT 24
Finished Jul 27 07:40:27 PM PDT 24
Peak memory 207124 kb
Host smart-41e49c0d-9647-4395-a41c-2ad6ca4b25ba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2809049210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2809049210
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.4176911818
Short name T2118
Test name
Test status
Simulation time 141859054 ps
CPU time 0.85 seconds
Started Jul 27 07:40:24 PM PDT 24
Finished Jul 27 07:40:25 PM PDT 24
Peak memory 207072 kb
Host smart-e54eb659-8300-4b70-9470-e76fcc11ca13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41769
11818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.4176911818
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.4270118207
Short name T1813
Test name
Test status
Simulation time 192764513 ps
CPU time 0.92 seconds
Started Jul 27 07:40:27 PM PDT 24
Finished Jul 27 07:40:28 PM PDT 24
Peak memory 207092 kb
Host smart-9b6df445-0b93-445a-9383-b8289407767c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42701
18207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.4270118207
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.4151546990
Short name T1704
Test name
Test status
Simulation time 192331003 ps
CPU time 0.91 seconds
Started Jul 27 07:40:27 PM PDT 24
Finished Jul 27 07:40:28 PM PDT 24
Peak memory 207032 kb
Host smart-6edf6c0e-bf78-4bf8-bf5d-2c41a16419e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41515
46990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.4151546990
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.95025428
Short name T2209
Test name
Test status
Simulation time 187473732 ps
CPU time 0.85 seconds
Started Jul 27 07:40:25 PM PDT 24
Finished Jul 27 07:40:26 PM PDT 24
Peak memory 207132 kb
Host smart-5ff1adf4-aad4-4c9d-89b2-be9a3fafa0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95025
428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.95025428
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1001230426
Short name T1286
Test name
Test status
Simulation time 185961424 ps
CPU time 0.92 seconds
Started Jul 27 07:40:26 PM PDT 24
Finished Jul 27 07:40:27 PM PDT 24
Peak memory 207192 kb
Host smart-f30df075-e5ac-43c1-8679-e830ada35aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10012
30426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1001230426
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1921417973
Short name T187
Test name
Test status
Simulation time 152074662 ps
CPU time 0.82 seconds
Started Jul 27 07:40:26 PM PDT 24
Finished Jul 27 07:40:27 PM PDT 24
Peak memory 207328 kb
Host smart-9a35c40e-eb4a-47ed-b711-4fac05a42a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19214
17973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1921417973
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.4052183292
Short name T1212
Test name
Test status
Simulation time 254403442 ps
CPU time 1.06 seconds
Started Jul 27 07:40:27 PM PDT 24
Finished Jul 27 07:40:28 PM PDT 24
Peak memory 207136 kb
Host smart-5b00a208-c3e9-4fb2-b496-798f5caa5e26
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4052183292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.4052183292
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.894115313
Short name T601
Test name
Test status
Simulation time 162354660 ps
CPU time 0.8 seconds
Started Jul 27 07:40:24 PM PDT 24
Finished Jul 27 07:40:25 PM PDT 24
Peak memory 207132 kb
Host smart-e9b46e18-dd24-4239-a268-426f7f09acd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89411
5313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.894115313
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2685145702
Short name T614
Test name
Test status
Simulation time 76796805 ps
CPU time 0.74 seconds
Started Jul 27 07:40:24 PM PDT 24
Finished Jul 27 07:40:25 PM PDT 24
Peak memory 206980 kb
Host smart-a64262fa-b5a6-4848-8c34-4da13fd3d10a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26851
45702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2685145702
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2591833270
Short name T2354
Test name
Test status
Simulation time 9220510063 ps
CPU time 21.47 seconds
Started Jul 27 07:40:26 PM PDT 24
Finished Jul 27 07:40:48 PM PDT 24
Peak memory 215548 kb
Host smart-fd848b9b-9169-4016-8c74-9da52b89a97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25918
33270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2591833270
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.411294403
Short name T2559
Test name
Test status
Simulation time 191031120 ps
CPU time 0.93 seconds
Started Jul 27 07:40:27 PM PDT 24
Finished Jul 27 07:40:28 PM PDT 24
Peak memory 207112 kb
Host smart-cc18f456-c51f-445f-b6f4-1f3ce0a1d6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41129
4403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.411294403
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2317719047
Short name T2364
Test name
Test status
Simulation time 213429271 ps
CPU time 0.94 seconds
Started Jul 27 07:40:26 PM PDT 24
Finished Jul 27 07:40:27 PM PDT 24
Peak memory 207108 kb
Host smart-2e964a65-b38d-4f90-8d55-f2209f413448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23177
19047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2317719047
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.2552853613
Short name T2238
Test name
Test status
Simulation time 223975930 ps
CPU time 0.94 seconds
Started Jul 27 07:40:27 PM PDT 24
Finished Jul 27 07:40:28 PM PDT 24
Peak memory 207140 kb
Host smart-267a2f9c-cf04-4e16-8dac-225c631aed28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25528
53613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.2552853613
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.861833556
Short name T451
Test name
Test status
Simulation time 188707019 ps
CPU time 0.92 seconds
Started Jul 27 07:40:33 PM PDT 24
Finished Jul 27 07:40:35 PM PDT 24
Peak memory 207108 kb
Host smart-ea1fbc31-1c98-482d-9294-6493ea72ce12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86183
3556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.861833556
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.724500699
Short name T1342
Test name
Test status
Simulation time 166694845 ps
CPU time 0.84 seconds
Started Jul 27 07:40:30 PM PDT 24
Finished Jul 27 07:40:31 PM PDT 24
Peak memory 207120 kb
Host smart-950ce8a4-a1a3-446b-b841-52f3f4ee1065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72450
0699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.724500699
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3029124471
Short name T162
Test name
Test status
Simulation time 197762651 ps
CPU time 0.85 seconds
Started Jul 27 07:40:32 PM PDT 24
Finished Jul 27 07:40:33 PM PDT 24
Peak memory 207100 kb
Host smart-7a2e4170-e15d-431e-b19e-8786745a5337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30291
24471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3029124471
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.4290212197
Short name T746
Test name
Test status
Simulation time 164509168 ps
CPU time 0.84 seconds
Started Jul 27 07:40:31 PM PDT 24
Finished Jul 27 07:40:32 PM PDT 24
Peak memory 207120 kb
Host smart-b21d061d-a18b-48f9-b586-f8c745b616d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42902
12197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.4290212197
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1932451388
Short name T1256
Test name
Test status
Simulation time 239784396 ps
CPU time 1.03 seconds
Started Jul 27 07:40:30 PM PDT 24
Finished Jul 27 07:40:32 PM PDT 24
Peak memory 207132 kb
Host smart-975a8da3-f24e-4d5d-aa72-1452b3b4e6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19324
51388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1932451388
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.4208495641
Short name T478
Test name
Test status
Simulation time 4857113275 ps
CPU time 38.01 seconds
Started Jul 27 07:40:31 PM PDT 24
Finished Jul 27 07:41:09 PM PDT 24
Peak memory 215556 kb
Host smart-c5caedf0-19f7-4f84-ae09-9daea57c9f6b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4208495641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.4208495641
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1132953386
Short name T1383
Test name
Test status
Simulation time 182535997 ps
CPU time 0.86 seconds
Started Jul 27 07:40:32 PM PDT 24
Finished Jul 27 07:40:33 PM PDT 24
Peak memory 207144 kb
Host smart-89bdd979-d7de-407e-99b5-c7640199b223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11329
53386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1132953386
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1773306281
Short name T2517
Test name
Test status
Simulation time 180679253 ps
CPU time 0.88 seconds
Started Jul 27 07:40:32 PM PDT 24
Finished Jul 27 07:40:33 PM PDT 24
Peak memory 207132 kb
Host smart-d036fccf-9937-40b0-8301-35706d16fc0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17733
06281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1773306281
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.359468749
Short name T1640
Test name
Test status
Simulation time 1224127402 ps
CPU time 2.8 seconds
Started Jul 27 07:40:31 PM PDT 24
Finished Jul 27 07:40:34 PM PDT 24
Peak memory 207228 kb
Host smart-36189eb0-952a-4d3a-b999-29429cc8a94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35946
8749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.359468749
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.572925464
Short name T466
Test name
Test status
Simulation time 6647074866 ps
CPU time 193.07 seconds
Started Jul 27 07:40:32 PM PDT 24
Finished Jul 27 07:43:45 PM PDT 24
Peak memory 215540 kb
Host smart-337f5eec-956b-447d-835f-5a0367f412d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57292
5464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.572925464
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.710865004
Short name T1562
Test name
Test status
Simulation time 288629129 ps
CPU time 4.42 seconds
Started Jul 27 07:40:26 PM PDT 24
Finished Jul 27 07:40:30 PM PDT 24
Peak memory 207300 kb
Host smart-a3696cc7-cfbf-4b59-ae70-88774d4d44fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710865004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_host
_handshake.710865004
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.3735692588
Short name T1015
Test name
Test status
Simulation time 45667485 ps
CPU time 0.68 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:40:45 PM PDT 24
Peak memory 207124 kb
Host smart-d020acbd-49ac-4720-bab6-e1db1385a38b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3735692588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3735692588
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2630904028
Short name T2766
Test name
Test status
Simulation time 4056328741 ps
CPU time 5.65 seconds
Started Jul 27 07:40:31 PM PDT 24
Finished Jul 27 07:40:36 PM PDT 24
Peak memory 207384 kb
Host smart-868a00ff-68b2-4d93-994f-6cd6376c1f4f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630904028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_disconnect.2630904028
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.2097599072
Short name T2419
Test name
Test status
Simulation time 13388936390 ps
CPU time 16.26 seconds
Started Jul 27 07:40:29 PM PDT 24
Finished Jul 27 07:40:45 PM PDT 24
Peak memory 207444 kb
Host smart-2924e632-9e67-44ce-a051-13eb74641efe
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097599072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.2097599072
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.757746217
Short name T610
Test name
Test status
Simulation time 23441916543 ps
CPU time 31.77 seconds
Started Jul 27 07:40:35 PM PDT 24
Finished Jul 27 07:41:07 PM PDT 24
Peak memory 207388 kb
Host smart-816de2a0-be26-4cc6-9f15-30cf821ee4da
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757746217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_ao
n_wake_resume.757746217
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.4287648879
Short name T2535
Test name
Test status
Simulation time 151575569 ps
CPU time 0.8 seconds
Started Jul 27 07:40:30 PM PDT 24
Finished Jul 27 07:40:31 PM PDT 24
Peak memory 207144 kb
Host smart-18f7d632-e473-4531-b6f0-aaba5beacd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42876
48879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.4287648879
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3682725038
Short name T824
Test name
Test status
Simulation time 145700521 ps
CPU time 0.87 seconds
Started Jul 27 07:40:33 PM PDT 24
Finished Jul 27 07:40:34 PM PDT 24
Peak memory 207076 kb
Host smart-acef0ed8-cdc9-4100-aac5-61d749fc7e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36827
25038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3682725038
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.277653572
Short name T95
Test name
Test status
Simulation time 198272257 ps
CPU time 0.99 seconds
Started Jul 27 07:40:32 PM PDT 24
Finished Jul 27 07:40:33 PM PDT 24
Peak memory 207076 kb
Host smart-05f37466-8ff1-4718-80ec-d954f97f61c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27765
3572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.277653572
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2525979281
Short name T82
Test name
Test status
Simulation time 1223645342 ps
CPU time 3.05 seconds
Started Jul 27 07:40:32 PM PDT 24
Finished Jul 27 07:40:36 PM PDT 24
Peak memory 207324 kb
Host smart-e75a3646-7b48-4487-9c17-a802f81e5b2e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2525979281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2525979281
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.1262725426
Short name T2072
Test name
Test status
Simulation time 10597470554 ps
CPU time 23.81 seconds
Started Jul 27 07:40:29 PM PDT 24
Finished Jul 27 07:40:53 PM PDT 24
Peak memory 207304 kb
Host smart-f5e3490e-f47d-4e03-a291-c96bdb2b61d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12627
25426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.1262725426
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.2509126067
Short name T381
Test name
Test status
Simulation time 1525568047 ps
CPU time 9.71 seconds
Started Jul 27 07:40:30 PM PDT 24
Finished Jul 27 07:40:40 PM PDT 24
Peak memory 207492 kb
Host smart-5e8f9dd7-306e-4618-b470-332dbe3c7af2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509126067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.2509126067
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.2584906208
Short name T1414
Test name
Test status
Simulation time 488277814 ps
CPU time 1.55 seconds
Started Jul 27 07:40:34 PM PDT 24
Finished Jul 27 07:40:35 PM PDT 24
Peak memory 207160 kb
Host smart-18ebc825-0fc8-4341-a1d8-066581062e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25849
06208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.2584906208
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2496046158
Short name T1781
Test name
Test status
Simulation time 138646610 ps
CPU time 0.85 seconds
Started Jul 27 07:40:32 PM PDT 24
Finished Jul 27 07:40:33 PM PDT 24
Peak memory 207032 kb
Host smart-a3912cbb-b9a4-4e9e-b9f3-bf01e4039bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24960
46158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2496046158
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1801267555
Short name T1070
Test name
Test status
Simulation time 33309909 ps
CPU time 0.69 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:40:43 PM PDT 24
Peak memory 207116 kb
Host smart-26b4773b-561b-477d-bd9f-37bf4126fdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18012
67555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1801267555
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1361453017
Short name T1721
Test name
Test status
Simulation time 917879313 ps
CPU time 2.48 seconds
Started Jul 27 07:40:39 PM PDT 24
Finished Jul 27 07:40:42 PM PDT 24
Peak memory 207336 kb
Host smart-229ed5ce-8e23-4ae4-928d-2244b3df338e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13614
53017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1361453017
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2541403906
Short name T1100
Test name
Test status
Simulation time 203681362 ps
CPU time 2.42 seconds
Started Jul 27 07:40:35 PM PDT 24
Finished Jul 27 07:40:37 PM PDT 24
Peak memory 207228 kb
Host smart-095e6013-8027-4655-b5c3-c46d94bfe6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25414
03906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2541403906
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.1364294701
Short name T928
Test name
Test status
Simulation time 186606183 ps
CPU time 1.03 seconds
Started Jul 27 07:40:42 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 215536 kb
Host smart-8170b677-6a6b-472d-8fa4-cd68ca8a436b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1364294701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.1364294701
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3628229998
Short name T522
Test name
Test status
Simulation time 138032614 ps
CPU time 0.81 seconds
Started Jul 27 07:40:37 PM PDT 24
Finished Jul 27 07:40:38 PM PDT 24
Peak memory 207068 kb
Host smart-fc15c363-9432-4e0b-ad82-8ec32ed8f394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36282
29998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3628229998
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3343341318
Short name T1910
Test name
Test status
Simulation time 181507916 ps
CPU time 0.91 seconds
Started Jul 27 07:40:39 PM PDT 24
Finished Jul 27 07:40:40 PM PDT 24
Peak memory 207076 kb
Host smart-3722ddda-e78c-48f2-ad70-44417443efaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33433
41318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3343341318
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.1999689103
Short name T2310
Test name
Test status
Simulation time 6405216786 ps
CPU time 49.96 seconds
Started Jul 27 07:40:40 PM PDT 24
Finished Jul 27 07:41:30 PM PDT 24
Peak memory 215592 kb
Host smart-7db24ffe-156e-4751-b891-67c3fb710fb5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1999689103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1999689103
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.2492560748
Short name T797
Test name
Test status
Simulation time 4982229005 ps
CPU time 58.95 seconds
Started Jul 27 07:40:37 PM PDT 24
Finished Jul 27 07:41:36 PM PDT 24
Peak memory 207352 kb
Host smart-6758127b-6423-4368-819d-691b9cf142d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2492560748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2492560748
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.1719854469
Short name T577
Test name
Test status
Simulation time 236449547 ps
CPU time 0.99 seconds
Started Jul 27 07:40:36 PM PDT 24
Finished Jul 27 07:40:37 PM PDT 24
Peak memory 207080 kb
Host smart-a9e04c5a-44e2-46b1-8087-f10b76890594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17198
54469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.1719854469
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.2843511715
Short name T199
Test name
Test status
Simulation time 23295266372 ps
CPU time 29.87 seconds
Started Jul 27 07:40:38 PM PDT 24
Finished Jul 27 07:41:08 PM PDT 24
Peak memory 207360 kb
Host smart-b09b0fb5-d3b9-404e-8db7-de45da58fdc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28435
11715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.2843511715
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1698403571
Short name T1126
Test name
Test status
Simulation time 3264675203 ps
CPU time 4.92 seconds
Started Jul 27 07:40:37 PM PDT 24
Finished Jul 27 07:40:42 PM PDT 24
Peak memory 207372 kb
Host smart-d2812e1f-7e0b-4644-95ce-488e0b1f41e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16984
03571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1698403571
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1391029630
Short name T702
Test name
Test status
Simulation time 6393593885 ps
CPU time 178.63 seconds
Started Jul 27 07:40:38 PM PDT 24
Finished Jul 27 07:43:36 PM PDT 24
Peak memory 215520 kb
Host smart-45263fe9-bb9c-46f9-b419-0237f6a5b95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13910
29630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1391029630
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.4146494531
Short name T1033
Test name
Test status
Simulation time 6311948914 ps
CPU time 183.53 seconds
Started Jul 27 07:40:37 PM PDT 24
Finished Jul 27 07:43:41 PM PDT 24
Peak memory 215624 kb
Host smart-e77ae60f-f53c-4707-b101-21e618a8b2cf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4146494531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.4146494531
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.3060912414
Short name T536
Test name
Test status
Simulation time 244999356 ps
CPU time 1.01 seconds
Started Jul 27 07:40:36 PM PDT 24
Finished Jul 27 07:40:38 PM PDT 24
Peak memory 207076 kb
Host smart-95c13fd2-6da3-4d7a-b1e7-c0043d2c6c19
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3060912414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.3060912414
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1669030754
Short name T2676
Test name
Test status
Simulation time 210431718 ps
CPU time 0.95 seconds
Started Jul 27 07:40:36 PM PDT 24
Finished Jul 27 07:40:37 PM PDT 24
Peak memory 207160 kb
Host smart-bb462893-dcae-40a6-aa84-2e6be02a9943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16690
30754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1669030754
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.630854790
Short name T654
Test name
Test status
Simulation time 3964265117 ps
CPU time 29.85 seconds
Started Jul 27 07:40:39 PM PDT 24
Finished Jul 27 07:41:09 PM PDT 24
Peak memory 215512 kb
Host smart-86585a82-4a96-414a-a32c-6b7e75401582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63085
4790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.630854790
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.3458272113
Short name T638
Test name
Test status
Simulation time 7461550061 ps
CPU time 219.02 seconds
Started Jul 27 07:40:36 PM PDT 24
Finished Jul 27 07:44:15 PM PDT 24
Peak memory 215640 kb
Host smart-b6354178-22c3-425d-a0e2-f1347d6f7331
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3458272113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.3458272113
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.4184889625
Short name T846
Test name
Test status
Simulation time 178833228 ps
CPU time 0.87 seconds
Started Jul 27 07:40:36 PM PDT 24
Finished Jul 27 07:40:37 PM PDT 24
Peak memory 207128 kb
Host smart-8f50b987-5d83-46ae-92f0-fafe2a678def
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4184889625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.4184889625
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1440380125
Short name T1951
Test name
Test status
Simulation time 156071848 ps
CPU time 0.9 seconds
Started Jul 27 07:40:41 PM PDT 24
Finished Jul 27 07:40:42 PM PDT 24
Peak memory 207160 kb
Host smart-3efb6349-1e79-44df-9c3c-a9b48e42106a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14403
80125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1440380125
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2728477897
Short name T141
Test name
Test status
Simulation time 288454153 ps
CPU time 1.03 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:40:45 PM PDT 24
Peak memory 207120 kb
Host smart-314d9594-5ad5-458b-9a9b-e51ee0c757da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27284
77897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2728477897
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.3791306440
Short name T1946
Test name
Test status
Simulation time 179729459 ps
CPU time 0.93 seconds
Started Jul 27 07:40:39 PM PDT 24
Finished Jul 27 07:40:40 PM PDT 24
Peak memory 207144 kb
Host smart-f37e10d8-f050-4e3b-a7e1-f7fcc259e6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37913
06440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.3791306440
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.4164660799
Short name T2049
Test name
Test status
Simulation time 177826576 ps
CPU time 0.91 seconds
Started Jul 27 07:40:42 PM PDT 24
Finished Jul 27 07:40:43 PM PDT 24
Peak memory 207144 kb
Host smart-1782917a-2999-4213-9483-3ccca92ec9ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41646
60799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.4164660799
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2589420230
Short name T494
Test name
Test status
Simulation time 169573282 ps
CPU time 0.87 seconds
Started Jul 27 07:40:36 PM PDT 24
Finished Jul 27 07:40:37 PM PDT 24
Peak memory 207124 kb
Host smart-15291f55-ce85-4ee9-b5f5-c8af5d7a0cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25894
20230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2589420230
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.161893391
Short name T181
Test name
Test status
Simulation time 176362113 ps
CPU time 0.95 seconds
Started Jul 27 07:40:36 PM PDT 24
Finished Jul 27 07:40:37 PM PDT 24
Peak memory 207136 kb
Host smart-19762839-b5eb-490d-9dfa-a949fce64fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16189
3391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.161893391
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.724073509
Short name T1607
Test name
Test status
Simulation time 226139174 ps
CPU time 1.09 seconds
Started Jul 27 07:40:37 PM PDT 24
Finished Jul 27 07:40:38 PM PDT 24
Peak memory 207124 kb
Host smart-0c3789b5-cc9e-46f1-81de-2bd2b10a7b14
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=724073509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.724073509
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.962208140
Short name T1970
Test name
Test status
Simulation time 143812042 ps
CPU time 0.83 seconds
Started Jul 27 07:40:42 PM PDT 24
Finished Jul 27 07:40:43 PM PDT 24
Peak memory 207168 kb
Host smart-077e03a5-f7bb-49bd-bce6-5e64d338e4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96220
8140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.962208140
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.239554191
Short name T2420
Test name
Test status
Simulation time 34235044 ps
CPU time 0.69 seconds
Started Jul 27 07:40:37 PM PDT 24
Finished Jul 27 07:40:38 PM PDT 24
Peak memory 207104 kb
Host smart-85dc63d2-d3b2-4235-a4ac-d29693740618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23955
4191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.239554191
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.788051767
Short name T1021
Test name
Test status
Simulation time 15471993722 ps
CPU time 42.92 seconds
Started Jul 27 07:40:39 PM PDT 24
Finished Jul 27 07:41:22 PM PDT 24
Peak memory 215580 kb
Host smart-1e17b5c7-d95e-4f8e-900b-14f0a99b8307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78805
1767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.788051767
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2988286149
Short name T1543
Test name
Test status
Simulation time 167618613 ps
CPU time 0.89 seconds
Started Jul 27 07:40:36 PM PDT 24
Finished Jul 27 07:40:37 PM PDT 24
Peak memory 207124 kb
Host smart-bf0fa964-94d9-47c4-b0ec-f1e353ef82f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29882
86149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2988286149
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1120913301
Short name T1505
Test name
Test status
Simulation time 192556517 ps
CPU time 0.91 seconds
Started Jul 27 07:40:37 PM PDT 24
Finished Jul 27 07:40:38 PM PDT 24
Peak memory 207060 kb
Host smart-4e25f0d0-3012-4b31-a1a0-17120daa4cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11209
13301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1120913301
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2338585702
Short name T2661
Test name
Test status
Simulation time 202477250 ps
CPU time 0.95 seconds
Started Jul 27 07:40:39 PM PDT 24
Finished Jul 27 07:40:40 PM PDT 24
Peak memory 207200 kb
Host smart-8b525b4d-7478-4691-b42f-8ef02555320d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23385
85702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2338585702
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.244400044
Short name T2410
Test name
Test status
Simulation time 169517824 ps
CPU time 0.88 seconds
Started Jul 27 07:40:37 PM PDT 24
Finished Jul 27 07:40:38 PM PDT 24
Peak memory 207128 kb
Host smart-b47167d0-98d1-47f7-8954-d2ae0ce30aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24440
0044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.244400044
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.181635309
Short name T1462
Test name
Test status
Simulation time 161506844 ps
CPU time 0.84 seconds
Started Jul 27 07:40:40 PM PDT 24
Finished Jul 27 07:40:41 PM PDT 24
Peak memory 207164 kb
Host smart-6f0db30e-509e-4338-8932-a891ac7e5070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18163
5309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.181635309
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1460694792
Short name T397
Test name
Test status
Simulation time 162742533 ps
CPU time 0.97 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 207112 kb
Host smart-38e3be06-dcef-4f3c-8beb-0b515f1a1674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14606
94792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1460694792
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2876289189
Short name T905
Test name
Test status
Simulation time 171325049 ps
CPU time 0.83 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 207128 kb
Host smart-ee2a5c0e-0e13-4146-b3d2-f46be7f7bcee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28762
89189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2876289189
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3711700111
Short name T1506
Test name
Test status
Simulation time 225108116 ps
CPU time 1.03 seconds
Started Jul 27 07:40:40 PM PDT 24
Finished Jul 27 07:40:42 PM PDT 24
Peak memory 207188 kb
Host smart-b43c32fa-3174-497e-8f13-8f94fe28d096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37117
00111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3711700111
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.2549126013
Short name T1761
Test name
Test status
Simulation time 5224204185 ps
CPU time 39.83 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:41:24 PM PDT 24
Peak memory 216988 kb
Host smart-6fdcbf73-d6d0-4600-a5fc-256b695f527a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2549126013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.2549126013
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.4209635399
Short name T907
Test name
Test status
Simulation time 177017641 ps
CPU time 0.88 seconds
Started Jul 27 07:40:36 PM PDT 24
Finished Jul 27 07:40:37 PM PDT 24
Peak memory 207200 kb
Host smart-8572a5e4-373a-4a45-9bba-d78cd5f71177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42096
35399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.4209635399
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1068069932
Short name T376
Test name
Test status
Simulation time 215427087 ps
CPU time 0.91 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 207124 kb
Host smart-54db93bf-246b-4814-905e-2ccec044e1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10680
69932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1068069932
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.2880838712
Short name T1966
Test name
Test status
Simulation time 326219585 ps
CPU time 1.24 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 207104 kb
Host smart-8ec24803-6234-49ce-b0b3-ef5d46e751fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28808
38712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.2880838712
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3021846462
Short name T936
Test name
Test status
Simulation time 5615759628 ps
CPU time 44.35 seconds
Started Jul 27 07:40:45 PM PDT 24
Finished Jul 27 07:41:29 PM PDT 24
Peak memory 216872 kb
Host smart-05360065-d5cc-439d-a416-e43aeee2ab46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30218
46462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3021846462
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.4237432624
Short name T1410
Test name
Test status
Simulation time 584487522 ps
CPU time 11.33 seconds
Started Jul 27 07:40:31 PM PDT 24
Finished Jul 27 07:40:43 PM PDT 24
Peak memory 207252 kb
Host smart-6ef30027-1f1f-4e04-871a-eea38dc73e18
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237432624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.4237432624
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3733231116
Short name T2469
Test name
Test status
Simulation time 58757034 ps
CPU time 0.66 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:40:51 PM PDT 24
Peak memory 207048 kb
Host smart-40460c4a-2e47-4e88-85b6-fce5c2275b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3733231116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3733231116
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2805834711
Short name T1926
Test name
Test status
Simulation time 3903061576 ps
CPU time 5.94 seconds
Started Jul 27 07:40:42 PM PDT 24
Finished Jul 27 07:40:48 PM PDT 24
Peak memory 207416 kb
Host smart-4dc34ed9-b566-49fa-b1c4-d409d8a5fce4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805834711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.2805834711
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.1994762101
Short name T2287
Test name
Test status
Simulation time 13373222929 ps
CPU time 17.54 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:41:01 PM PDT 24
Peak memory 207412 kb
Host smart-6acd0ad4-73b8-4ef1-8540-d4de742db9b2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994762101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.1994762101
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.890653487
Short name T1934
Test name
Test status
Simulation time 23468689017 ps
CPU time 27.94 seconds
Started Jul 27 07:40:45 PM PDT 24
Finished Jul 27 07:41:13 PM PDT 24
Peak memory 207416 kb
Host smart-3ed09e03-92d9-4c60-9250-970b0279ba36
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890653487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_ao
n_wake_resume.890653487
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.220141091
Short name T422
Test name
Test status
Simulation time 148315514 ps
CPU time 0.9 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:40:45 PM PDT 24
Peak memory 207016 kb
Host smart-5c5433d7-681d-46a5-bd4e-8e26621c91e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22014
1091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.220141091
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1681305516
Short name T843
Test name
Test status
Simulation time 146811458 ps
CPU time 0.84 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 207108 kb
Host smart-db21438c-c4b8-401a-8b51-f2ea48dca01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16813
05516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1681305516
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.138595425
Short name T474
Test name
Test status
Simulation time 261478291 ps
CPU time 1.11 seconds
Started Jul 27 07:40:41 PM PDT 24
Finished Jul 27 07:40:43 PM PDT 24
Peak memory 207068 kb
Host smart-9ec5d860-61b4-49e0-a82d-33d726c51001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13859
5425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.138595425
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1629513316
Short name T717
Test name
Test status
Simulation time 1399126604 ps
CPU time 3.46 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:40:46 PM PDT 24
Peak memory 207256 kb
Host smart-b3fcedb6-3bac-4ad5-b6ff-9714d9346b49
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1629513316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1629513316
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.4288625124
Short name T2269
Test name
Test status
Simulation time 7030345325 ps
CPU time 14.21 seconds
Started Jul 27 07:40:42 PM PDT 24
Finished Jul 27 07:40:57 PM PDT 24
Peak memory 207208 kb
Host smart-37b27da8-bf91-4a1b-bcaf-d8661392e6ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42886
25124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.4288625124
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.3931309861
Short name T2021
Test name
Test status
Simulation time 739780990 ps
CPU time 15.02 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:40:59 PM PDT 24
Peak memory 207304 kb
Host smart-be221e94-9431-42c0-a217-9da2b2ca51b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931309861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.3931309861
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.744727057
Short name T1038
Test name
Test status
Simulation time 476309943 ps
CPU time 1.64 seconds
Started Jul 27 07:40:45 PM PDT 24
Finished Jul 27 07:40:46 PM PDT 24
Peak memory 207108 kb
Host smart-3bc4c511-9f6a-4967-abab-83c106af93c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74472
7057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.744727057
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2660755084
Short name T885
Test name
Test status
Simulation time 140310120 ps
CPU time 0.82 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 207116 kb
Host smart-737b36ae-2ff5-4874-a097-1158f63788f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26607
55084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2660755084
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1355733365
Short name T2195
Test name
Test status
Simulation time 33138413 ps
CPU time 0.67 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 207108 kb
Host smart-3a4e4597-9028-44d0-9c51-689a5f933d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13557
33365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1355733365
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.2540015662
Short name T1443
Test name
Test status
Simulation time 981605709 ps
CPU time 2.48 seconds
Started Jul 27 07:40:42 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 207204 kb
Host smart-12386a80-4a72-452b-926c-4c4c83dcb76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25400
15662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2540015662
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3438615926
Short name T1858
Test name
Test status
Simulation time 188369721 ps
CPU time 2.1 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:40:46 PM PDT 24
Peak memory 207300 kb
Host smart-182974f2-123a-4784-befb-a53526cdd4d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34386
15926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3438615926
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.954350489
Short name T2773
Test name
Test status
Simulation time 182433977 ps
CPU time 0.97 seconds
Started Jul 27 07:40:46 PM PDT 24
Finished Jul 27 07:40:47 PM PDT 24
Peak memory 207336 kb
Host smart-6ef1c6e9-a5e9-4d70-9338-b9b5915c8bed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=954350489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.954350489
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2147671546
Short name T1336
Test name
Test status
Simulation time 151082511 ps
CPU time 0.83 seconds
Started Jul 27 07:40:41 PM PDT 24
Finished Jul 27 07:40:42 PM PDT 24
Peak memory 207068 kb
Host smart-71fd1da3-9857-4aeb-bb54-eae708a407d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21476
71546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2147671546
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.3219673728
Short name T380
Test name
Test status
Simulation time 179342743 ps
CPU time 0.93 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 207072 kb
Host smart-290da4fe-c7a7-4d61-9af9-3731814f4bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32196
73728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3219673728
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.3236606045
Short name T1386
Test name
Test status
Simulation time 4625311437 ps
CPU time 134.81 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:42:58 PM PDT 24
Peak memory 215624 kb
Host smart-cc1357b0-4a2d-4f80-9087-036ce34faefe
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3236606045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.3236606045
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3792759123
Short name T2099
Test name
Test status
Simulation time 228311090 ps
CPU time 0.98 seconds
Started Jul 27 07:40:41 PM PDT 24
Finished Jul 27 07:40:43 PM PDT 24
Peak memory 207084 kb
Host smart-0cee13eb-7ca7-4579-acac-38689022a9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37927
59123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3792759123
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.3743176786
Short name T2834
Test name
Test status
Simulation time 23340954698 ps
CPU time 27.67 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:41:12 PM PDT 24
Peak memory 207364 kb
Host smart-96fbc037-53ef-40b5-b6db-30793a540485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37431
76786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.3743176786
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2675663063
Short name T1405
Test name
Test status
Simulation time 3282479331 ps
CPU time 4.83 seconds
Started Jul 27 07:40:46 PM PDT 24
Finished Jul 27 07:40:51 PM PDT 24
Peak memory 207372 kb
Host smart-f13af7c4-8dd2-4add-b0e5-157643dddfd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26756
63063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2675663063
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2501131638
Short name T2139
Test name
Test status
Simulation time 9831182869 ps
CPU time 284.99 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:45:29 PM PDT 24
Peak memory 215564 kb
Host smart-d41c4838-3927-4be0-b62c-503f57d79e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25011
31638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2501131638
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3695676750
Short name T2401
Test name
Test status
Simulation time 4845534201 ps
CPU time 146.28 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:43:10 PM PDT 24
Peak memory 215488 kb
Host smart-b799bd57-78bc-4b91-a13b-3824076abf60
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3695676750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3695676750
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.2422332181
Short name T821
Test name
Test status
Simulation time 293362089 ps
CPU time 1.04 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:40:45 PM PDT 24
Peak memory 207088 kb
Host smart-33eac95c-72a5-4e06-8e74-69ddeef2ce4f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2422332181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.2422332181
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2814906363
Short name T435
Test name
Test status
Simulation time 195451710 ps
CPU time 0.97 seconds
Started Jul 27 07:40:42 PM PDT 24
Finished Jul 27 07:40:44 PM PDT 24
Peak memory 207092 kb
Host smart-a63712dc-f1e2-4b95-a58a-170752b17647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28149
06363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2814906363
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.249195874
Short name T1397
Test name
Test status
Simulation time 3429025777 ps
CPU time 24.58 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:41:09 PM PDT 24
Peak memory 217136 kb
Host smart-5a711d41-acae-4f89-b479-07228e30e1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24919
5874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.249195874
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.1212791468
Short name T1412
Test name
Test status
Simulation time 5717188185 ps
CPU time 171.51 seconds
Started Jul 27 07:40:43 PM PDT 24
Finished Jul 27 07:43:35 PM PDT 24
Peak memory 215564 kb
Host smart-56f9c5ca-34c5-44f1-8d00-03a19b817f02
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1212791468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.1212791468
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.2601418135
Short name T971
Test name
Test status
Simulation time 154932101 ps
CPU time 0.9 seconds
Started Jul 27 07:40:45 PM PDT 24
Finished Jul 27 07:40:46 PM PDT 24
Peak memory 207044 kb
Host smart-b5ed9dd0-d8e1-406e-b039-87c2b8e949a9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2601418135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2601418135
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2158601945
Short name T1298
Test name
Test status
Simulation time 143983661 ps
CPU time 0.87 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:40:45 PM PDT 24
Peak memory 207144 kb
Host smart-b6d95fdd-27be-4bc4-8da0-6c6aaf7c6e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21586
01945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2158601945
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2953274292
Short name T139
Test name
Test status
Simulation time 189473702 ps
CPU time 0.9 seconds
Started Jul 27 07:40:42 PM PDT 24
Finished Jul 27 07:40:43 PM PDT 24
Peak memory 207096 kb
Host smart-6b8fa62c-448b-4d05-bd78-9f1f66a5db9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29532
74292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2953274292
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1516192331
Short name T2111
Test name
Test status
Simulation time 146904646 ps
CPU time 0.89 seconds
Started Jul 27 07:40:45 PM PDT 24
Finished Jul 27 07:40:46 PM PDT 24
Peak memory 207108 kb
Host smart-161a61ac-74af-48a1-87e4-621a1ae9c2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15161
92331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1516192331
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.184789227
Short name T1677
Test name
Test status
Simulation time 158707766 ps
CPU time 0.87 seconds
Started Jul 27 07:40:44 PM PDT 24
Finished Jul 27 07:40:45 PM PDT 24
Peak memory 207068 kb
Host smart-edbcbe20-db4b-4679-b288-173e2e45e622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18478
9227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.184789227
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3188200944
Short name T2840
Test name
Test status
Simulation time 179815137 ps
CPU time 0.86 seconds
Started Jul 27 07:40:51 PM PDT 24
Finished Jul 27 07:40:52 PM PDT 24
Peak memory 207096 kb
Host smart-949db773-4299-4d8e-ba17-bfc960e24a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31882
00944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3188200944
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.4062076024
Short name T174
Test name
Test status
Simulation time 192054137 ps
CPU time 0.89 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:40:51 PM PDT 24
Peak memory 207020 kb
Host smart-d92bea88-20bd-4f39-ac55-ee95426f3868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40620
76024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.4062076024
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.2745083092
Short name T2170
Test name
Test status
Simulation time 235238671 ps
CPU time 1.04 seconds
Started Jul 27 07:40:48 PM PDT 24
Finished Jul 27 07:40:50 PM PDT 24
Peak memory 207112 kb
Host smart-b3749bdc-372e-4af2-9ef4-c5838e0679eb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2745083092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.2745083092
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3802498007
Short name T1971
Test name
Test status
Simulation time 146744287 ps
CPU time 0.82 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:40:51 PM PDT 24
Peak memory 207028 kb
Host smart-87caf3c7-5cde-4252-8812-98a6693362c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38024
98007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3802498007
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2300654210
Short name T34
Test name
Test status
Simulation time 36419245 ps
CPU time 0.68 seconds
Started Jul 27 07:40:52 PM PDT 24
Finished Jul 27 07:40:53 PM PDT 24
Peak memory 207092 kb
Host smart-7f9d1518-3dcc-408c-bc70-483f110fe5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23006
54210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2300654210
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3767322615
Short name T690
Test name
Test status
Simulation time 10052312814 ps
CPU time 27.26 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:41:18 PM PDT 24
Peak memory 215568 kb
Host smart-8294e30d-db67-4d7b-9856-44b6db0d01ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37673
22615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3767322615
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2366270981
Short name T2267
Test name
Test status
Simulation time 179569956 ps
CPU time 0.92 seconds
Started Jul 27 07:40:51 PM PDT 24
Finished Jul 27 07:40:52 PM PDT 24
Peak memory 207144 kb
Host smart-d1f1307d-f6dc-4015-b336-3b6db54b7c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23662
70981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2366270981
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2196068983
Short name T2360
Test name
Test status
Simulation time 202932896 ps
CPU time 1.01 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:40:51 PM PDT 24
Peak memory 207140 kb
Host smart-3a406fac-c63c-48ce-8c3e-e4cf7487ea52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21960
68983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2196068983
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.1149620454
Short name T639
Test name
Test status
Simulation time 228293556 ps
CPU time 1 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:40:51 PM PDT 24
Peak memory 207144 kb
Host smart-12a93577-d362-49ae-b298-12d010131314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11496
20454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.1149620454
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2341155986
Short name T1911
Test name
Test status
Simulation time 210231857 ps
CPU time 0.97 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:40:51 PM PDT 24
Peak memory 207200 kb
Host smart-6395e7d6-5e96-4b84-9d86-7f0fd1fbb79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23411
55986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2341155986
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.303236489
Short name T2240
Test name
Test status
Simulation time 143561978 ps
CPU time 0.84 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:40:51 PM PDT 24
Peak memory 207096 kb
Host smart-1fca0377-5018-4ab1-8c15-ca2d884bd732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30323
6489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.303236489
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1109426019
Short name T2346
Test name
Test status
Simulation time 156927203 ps
CPU time 0.83 seconds
Started Jul 27 07:40:49 PM PDT 24
Finished Jul 27 07:40:49 PM PDT 24
Peak memory 206980 kb
Host smart-b4c1842d-f116-443f-9619-e83d268b2894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11094
26019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1109426019
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1106589327
Short name T111
Test name
Test status
Simulation time 153545748 ps
CPU time 0.84 seconds
Started Jul 27 07:40:51 PM PDT 24
Finished Jul 27 07:40:52 PM PDT 24
Peak memory 207084 kb
Host smart-249827b7-f84c-49db-820f-1626a01bb8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11065
89327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1106589327
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.399000346
Short name T2173
Test name
Test status
Simulation time 190933345 ps
CPU time 0.94 seconds
Started Jul 27 07:40:49 PM PDT 24
Finished Jul 27 07:40:50 PM PDT 24
Peak memory 207084 kb
Host smart-d1fed435-ce38-4a38-a7ec-20dc0de1fb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39900
0346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.399000346
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2208719072
Short name T2859
Test name
Test status
Simulation time 6766241254 ps
CPU time 203.85 seconds
Started Jul 27 07:40:53 PM PDT 24
Finished Jul 27 07:44:17 PM PDT 24
Peak memory 215596 kb
Host smart-e9178b9b-ff57-42d8-9e29-415b00765860
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2208719072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2208719072
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.139779019
Short name T2438
Test name
Test status
Simulation time 176556948 ps
CPU time 0.87 seconds
Started Jul 27 07:40:53 PM PDT 24
Finished Jul 27 07:40:54 PM PDT 24
Peak memory 207116 kb
Host smart-f3a296a8-ba2f-403a-88c3-444b1918d0b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13977
9019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.139779019
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.4064239352
Short name T2372
Test name
Test status
Simulation time 178238407 ps
CPU time 0.88 seconds
Started Jul 27 07:40:52 PM PDT 24
Finished Jul 27 07:40:53 PM PDT 24
Peak memory 207096 kb
Host smart-42bfbeb6-2434-46d8-9f37-6867a854e5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40642
39352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.4064239352
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.219635118
Short name T2003
Test name
Test status
Simulation time 555475277 ps
CPU time 1.69 seconds
Started Jul 27 07:40:49 PM PDT 24
Finished Jul 27 07:40:51 PM PDT 24
Peak memory 207084 kb
Host smart-ab9eec67-b566-4c74-9b36-7613b63e449f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21963
5118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.219635118
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1217272420
Short name T2278
Test name
Test status
Simulation time 2970129776 ps
CPU time 83.45 seconds
Started Jul 27 07:40:51 PM PDT 24
Finished Jul 27 07:42:14 PM PDT 24
Peak memory 215692 kb
Host smart-b3999232-eac4-4552-b711-0a3dd87dd719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12172
72420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1217272420
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.1677582897
Short name T1409
Test name
Test status
Simulation time 1573938374 ps
CPU time 9.58 seconds
Started Jul 27 07:40:45 PM PDT 24
Finished Jul 27 07:40:55 PM PDT 24
Peak memory 207296 kb
Host smart-302549dd-0e5c-4312-bb87-15520bc042f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677582897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos
t_handshake.1677582897
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.2824298590
Short name T2094
Test name
Test status
Simulation time 53103153 ps
CPU time 0.71 seconds
Started Jul 27 07:41:02 PM PDT 24
Finished Jul 27 07:41:03 PM PDT 24
Peak memory 207168 kb
Host smart-964650ed-c35f-4eaa-8903-8dc79fe42d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2824298590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.2824298590
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.272548811
Short name T745
Test name
Test status
Simulation time 3836492813 ps
CPU time 5.6 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:40:56 PM PDT 24
Peak memory 207332 kb
Host smart-0838597b-894b-42d0-a00d-f7e2cef49369
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272548811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ao
n_wake_disconnect.272548811
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3893053661
Short name T197
Test name
Test status
Simulation time 13419524139 ps
CPU time 15.87 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:41:05 PM PDT 24
Peak memory 207376 kb
Host smart-0f30d323-6a45-43a9-82ec-514d2c38fa5a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893053661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3893053661
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3862921762
Short name T1573
Test name
Test status
Simulation time 23384524079 ps
CPU time 29.22 seconds
Started Jul 27 07:40:52 PM PDT 24
Finished Jul 27 07:41:21 PM PDT 24
Peak memory 207368 kb
Host smart-5e1fe224-4b05-40a1-8a5d-e09396db4515
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862921762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_resume.3862921762
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3300785808
Short name T1865
Test name
Test status
Simulation time 148456015 ps
CPU time 0.81 seconds
Started Jul 27 07:40:52 PM PDT 24
Finished Jul 27 07:40:53 PM PDT 24
Peak memory 207116 kb
Host smart-0b05072f-6792-4de7-9fb1-cbf4c99f01ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33007
85808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3300785808
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.3817899809
Short name T2214
Test name
Test status
Simulation time 149735545 ps
CPU time 0.91 seconds
Started Jul 27 07:40:52 PM PDT 24
Finished Jul 27 07:40:53 PM PDT 24
Peak memory 207100 kb
Host smart-9e58ad81-ed30-4315-86d1-aef49ae089e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38178
99809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.3817899809
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.355621082
Short name T952
Test name
Test status
Simulation time 275392698 ps
CPU time 1.18 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:40:51 PM PDT 24
Peak memory 207104 kb
Host smart-2c92de7b-a603-43aa-b3b9-a36105710579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35562
1082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.355621082
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3972005775
Short name T1792
Test name
Test status
Simulation time 1106664855 ps
CPU time 2.92 seconds
Started Jul 27 07:40:51 PM PDT 24
Finished Jul 27 07:40:54 PM PDT 24
Peak memory 207280 kb
Host smart-a5882047-1b48-4181-a284-3c5417d60d0e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3972005775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3972005775
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3607589244
Short name T2050
Test name
Test status
Simulation time 6573784775 ps
CPU time 15.96 seconds
Started Jul 27 07:40:51 PM PDT 24
Finished Jul 27 07:41:07 PM PDT 24
Peak memory 207476 kb
Host smart-8d69da9e-a947-4bf1-be11-435ae05a8c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36075
89244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3607589244
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.2323768870
Short name T974
Test name
Test status
Simulation time 823037746 ps
CPU time 18.57 seconds
Started Jul 27 07:40:49 PM PDT 24
Finished Jul 27 07:41:08 PM PDT 24
Peak memory 207320 kb
Host smart-3d9c9a1e-1f76-4c38-a957-b07ca4575f94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323768870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.2323768870
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.2174730112
Short name T1673
Test name
Test status
Simulation time 361467660 ps
CPU time 1.28 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:40:51 PM PDT 24
Peak memory 207108 kb
Host smart-81655942-8d0e-43cd-8be3-ef854846d004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21747
30112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.2174730112
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.2135799476
Short name T1211
Test name
Test status
Simulation time 133881593 ps
CPU time 0.81 seconds
Started Jul 27 07:40:48 PM PDT 24
Finished Jul 27 07:40:49 PM PDT 24
Peak memory 207080 kb
Host smart-9a17bc26-e486-4f66-8aa5-fd7c04c386f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21357
99476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.2135799476
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3846563722
Short name T1237
Test name
Test status
Simulation time 32551924 ps
CPU time 0.73 seconds
Started Jul 27 07:40:57 PM PDT 24
Finished Jul 27 07:40:58 PM PDT 24
Peak memory 206972 kb
Host smart-7c5c3655-4baf-4de9-a3d9-8255b2ba4efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38465
63722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3846563722
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1248775326
Short name T546
Test name
Test status
Simulation time 977242149 ps
CPU time 2.55 seconds
Started Jul 27 07:40:56 PM PDT 24
Finished Jul 27 07:40:59 PM PDT 24
Peak memory 207376 kb
Host smart-3e78116e-65e0-448c-9f5d-0c9c6b8fa09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12487
75326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1248775326
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1067436157
Short name T1867
Test name
Test status
Simulation time 286467231 ps
CPU time 2.09 seconds
Started Jul 27 07:40:56 PM PDT 24
Finished Jul 27 07:40:58 PM PDT 24
Peak memory 207260 kb
Host smart-48c7c267-9aab-40a0-b0ed-3ef5f514252c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10674
36157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1067436157
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.282065420
Short name T733
Test name
Test status
Simulation time 265470825 ps
CPU time 1.15 seconds
Started Jul 27 07:40:58 PM PDT 24
Finished Jul 27 07:40:59 PM PDT 24
Peak memory 207304 kb
Host smart-01131fd2-7f94-4ea7-8d6f-201a04188a68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=282065420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.282065420
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2986555607
Short name T1882
Test name
Test status
Simulation time 142861600 ps
CPU time 0.96 seconds
Started Jul 27 07:41:03 PM PDT 24
Finished Jul 27 07:41:04 PM PDT 24
Peak memory 207108 kb
Host smart-a3743868-04be-4ac5-9fe1-7de2272323e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29865
55607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2986555607
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2521647850
Short name T1221
Test name
Test status
Simulation time 218396740 ps
CPU time 1.01 seconds
Started Jul 27 07:40:58 PM PDT 24
Finished Jul 27 07:41:00 PM PDT 24
Peak memory 207096 kb
Host smart-3a761b0d-3dec-41b2-a7c3-44b66604c53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25216
47850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2521647850
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.1208857275
Short name T481
Test name
Test status
Simulation time 6760220161 ps
CPU time 201.08 seconds
Started Jul 27 07:41:00 PM PDT 24
Finished Jul 27 07:44:21 PM PDT 24
Peak memory 215592 kb
Host smart-0e440abe-b2ea-4581-8346-93cf2feaa08e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1208857275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.1208857275
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.694866087
Short name T483
Test name
Test status
Simulation time 12572526573 ps
CPU time 157.59 seconds
Started Jul 27 07:40:58 PM PDT 24
Finished Jul 27 07:43:35 PM PDT 24
Peak memory 207396 kb
Host smart-0bbd0cb7-9efa-4e5c-b1cf-8cf41e855347
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=694866087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.694866087
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2425948198
Short name T1691
Test name
Test status
Simulation time 221366288 ps
CPU time 0.91 seconds
Started Jul 27 07:40:56 PM PDT 24
Finished Jul 27 07:40:57 PM PDT 24
Peak memory 207144 kb
Host smart-6722da06-0154-4529-a042-370cd8c4a46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24259
48198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2425948198
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.3260389934
Short name T784
Test name
Test status
Simulation time 23304305760 ps
CPU time 31.87 seconds
Started Jul 27 07:40:55 PM PDT 24
Finished Jul 27 07:41:27 PM PDT 24
Peak memory 207380 kb
Host smart-ca8557de-5e19-4809-95e3-fbde15f7cb43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32603
89934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.3260389934
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.114784813
Short name T2750
Test name
Test status
Simulation time 3298700017 ps
CPU time 5.02 seconds
Started Jul 27 07:41:00 PM PDT 24
Finished Jul 27 07:41:05 PM PDT 24
Peak memory 207376 kb
Host smart-1856a948-f866-48ec-86a7-c3f399d88e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11478
4813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.114784813
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.638026727
Short name T868
Test name
Test status
Simulation time 7494919581 ps
CPU time 77.22 seconds
Started Jul 27 07:41:01 PM PDT 24
Finished Jul 27 07:42:18 PM PDT 24
Peak memory 217540 kb
Host smart-8efc57c1-7b98-4e1c-9dfd-cc18f9c007cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63802
6727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.638026727
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2225618396
Short name T1282
Test name
Test status
Simulation time 4657471758 ps
CPU time 35.21 seconds
Started Jul 27 07:40:57 PM PDT 24
Finished Jul 27 07:41:32 PM PDT 24
Peak memory 207284 kb
Host smart-6eec28b1-8bf0-4c69-8834-2ef6f03cc85d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2225618396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2225618396
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2805165680
Short name T2510
Test name
Test status
Simulation time 247844181 ps
CPU time 1.02 seconds
Started Jul 27 07:41:02 PM PDT 24
Finished Jul 27 07:41:04 PM PDT 24
Peak memory 207120 kb
Host smart-e0dde554-1f90-4a9f-a1bb-38e6c11262ad
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2805165680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2805165680
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2632337704
Short name T249
Test name
Test status
Simulation time 199669706 ps
CPU time 1.01 seconds
Started Jul 27 07:40:59 PM PDT 24
Finished Jul 27 07:41:00 PM PDT 24
Peak memory 207160 kb
Host smart-7105606b-e757-4c34-a078-80e9f8212cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26323
37704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2632337704
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.1205967259
Short name T2318
Test name
Test status
Simulation time 4821910284 ps
CPU time 134.26 seconds
Started Jul 27 07:41:03 PM PDT 24
Finished Jul 27 07:43:17 PM PDT 24
Peak memory 215476 kb
Host smart-8288c067-410d-4e17-8e6d-66d677c856c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12059
67259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.1205967259
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.255230251
Short name T1683
Test name
Test status
Simulation time 6375915764 ps
CPU time 61.41 seconds
Started Jul 27 07:41:02 PM PDT 24
Finished Jul 27 07:42:03 PM PDT 24
Peak memory 207640 kb
Host smart-e686fd39-ac7f-4b85-9752-67c84592a309
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=255230251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.255230251
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.2325375328
Short name T2011
Test name
Test status
Simulation time 167999823 ps
CPU time 0.89 seconds
Started Jul 27 07:41:01 PM PDT 24
Finished Jul 27 07:41:02 PM PDT 24
Peak memory 207144 kb
Host smart-1db4427e-bb36-466e-a328-33b5ca435853
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2325375328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.2325375328
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3035920541
Short name T2777
Test name
Test status
Simulation time 147380719 ps
CPU time 0.84 seconds
Started Jul 27 07:40:56 PM PDT 24
Finished Jul 27 07:40:57 PM PDT 24
Peak memory 207088 kb
Host smart-9729511b-8ee9-4c19-b0fa-e72db021d304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30359
20541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3035920541
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3118881959
Short name T119
Test name
Test status
Simulation time 224704917 ps
CPU time 1.05 seconds
Started Jul 27 07:41:02 PM PDT 24
Finished Jul 27 07:41:03 PM PDT 24
Peak memory 207344 kb
Host smart-d61c2f0b-f2b7-461c-9113-93839c4ab083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31188
81959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3118881959
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.4276053231
Short name T1146
Test name
Test status
Simulation time 157455860 ps
CPU time 0.84 seconds
Started Jul 27 07:41:00 PM PDT 24
Finished Jul 27 07:41:01 PM PDT 24
Peak memory 207092 kb
Host smart-a3a1901f-ae25-427b-a961-c6978ad6ecc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42760
53231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.4276053231
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.33973367
Short name T1546
Test name
Test status
Simulation time 202792135 ps
CPU time 0.89 seconds
Started Jul 27 07:40:56 PM PDT 24
Finished Jul 27 07:40:57 PM PDT 24
Peak memory 207072 kb
Host smart-f583a062-7e6e-4e79-a1ac-a87e19ad9272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33973
367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.33973367
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3993655974
Short name T2597
Test name
Test status
Simulation time 181649067 ps
CPU time 0.9 seconds
Started Jul 27 07:40:59 PM PDT 24
Finished Jul 27 07:41:00 PM PDT 24
Peak memory 207032 kb
Host smart-b336f90c-5a6d-4db6-9f3d-f137e7a11a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39936
55974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3993655974
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.40832942
Short name T2305
Test name
Test status
Simulation time 153110147 ps
CPU time 0.85 seconds
Started Jul 27 07:41:03 PM PDT 24
Finished Jul 27 07:41:04 PM PDT 24
Peak memory 207112 kb
Host smart-39b1b36f-92c2-44b9-b947-57a73ccb6fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40832
942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.40832942
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.2350685666
Short name T1812
Test name
Test status
Simulation time 214696423 ps
CPU time 0.97 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:41:05 PM PDT 24
Peak memory 207120 kb
Host smart-b9b9ca14-41b9-475a-bfd7-ae347505458e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2350685666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.2350685666
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2017474831
Short name T1058
Test name
Test status
Simulation time 146435294 ps
CPU time 0.83 seconds
Started Jul 27 07:40:58 PM PDT 24
Finished Jul 27 07:40:58 PM PDT 24
Peak memory 207072 kb
Host smart-ca8cd3df-5cfa-4c36-981e-f2bd7fd21a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20174
74831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2017474831
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3208647556
Short name T2208
Test name
Test status
Simulation time 34661263 ps
CPU time 0.69 seconds
Started Jul 27 07:41:00 PM PDT 24
Finished Jul 27 07:41:01 PM PDT 24
Peak memory 207056 kb
Host smart-28a2b0e0-a79b-4974-ac9e-72e5d1d4334b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32086
47556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3208647556
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.367671580
Short name T255
Test name
Test status
Simulation time 8145027493 ps
CPU time 20.56 seconds
Started Jul 27 07:40:57 PM PDT 24
Finished Jul 27 07:41:17 PM PDT 24
Peak memory 215456 kb
Host smart-0023eb5d-c7a4-479b-bd0d-9f05462c432b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36767
1580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.367671580
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3413824319
Short name T1371
Test name
Test status
Simulation time 176797932 ps
CPU time 0.88 seconds
Started Jul 27 07:40:56 PM PDT 24
Finished Jul 27 07:40:57 PM PDT 24
Peak memory 207132 kb
Host smart-6c3d633b-b9d6-451d-a711-96ec43396023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34138
24319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3413824319
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3061263735
Short name T490
Test name
Test status
Simulation time 214260827 ps
CPU time 0.97 seconds
Started Jul 27 07:41:02 PM PDT 24
Finished Jul 27 07:41:03 PM PDT 24
Peak memory 207100 kb
Host smart-af9895a6-28a0-49af-bbd0-f94394d72bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30612
63735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3061263735
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.3690418493
Short name T2341
Test name
Test status
Simulation time 199830872 ps
CPU time 0.95 seconds
Started Jul 27 07:40:55 PM PDT 24
Finished Jul 27 07:40:56 PM PDT 24
Peak memory 207016 kb
Host smart-863bf3c4-5714-4fe5-a1b7-09dd441a513e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36904
18493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.3690418493
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2050595524
Short name T2485
Test name
Test status
Simulation time 194067592 ps
CPU time 0.89 seconds
Started Jul 27 07:40:59 PM PDT 24
Finished Jul 27 07:41:00 PM PDT 24
Peak memory 207100 kb
Host smart-fe5524fd-eebe-43cc-8bb9-053c5f298ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20505
95524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2050595524
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.796032904
Short name T2210
Test name
Test status
Simulation time 145216637 ps
CPU time 0.91 seconds
Started Jul 27 07:40:58 PM PDT 24
Finished Jul 27 07:40:59 PM PDT 24
Peak memory 207132 kb
Host smart-0f11c443-ac70-4bd5-bf85-10c7c8a54411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79603
2904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.796032904
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2072950179
Short name T2383
Test name
Test status
Simulation time 163895663 ps
CPU time 0.83 seconds
Started Jul 27 07:40:58 PM PDT 24
Finished Jul 27 07:40:59 PM PDT 24
Peak memory 207000 kb
Host smart-39cc0ed6-64fe-46d4-9e16-4e1db35c1bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20729
50179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2072950179
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1859155531
Short name T1008
Test name
Test status
Simulation time 154806241 ps
CPU time 0.82 seconds
Started Jul 27 07:40:55 PM PDT 24
Finished Jul 27 07:40:56 PM PDT 24
Peak memory 207020 kb
Host smart-6807fe09-8451-42a3-9e92-ffc7e4f7db95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18591
55531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1859155531
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.883111100
Short name T630
Test name
Test status
Simulation time 246896088 ps
CPU time 1.07 seconds
Started Jul 27 07:40:57 PM PDT 24
Finished Jul 27 07:40:58 PM PDT 24
Peak memory 207128 kb
Host smart-5060c2d7-5d06-48c2-b8a3-80251eda7776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88311
1100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.883111100
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1969040827
Short name T2698
Test name
Test status
Simulation time 3159401662 ps
CPU time 88.35 seconds
Started Jul 27 07:40:58 PM PDT 24
Finished Jul 27 07:42:26 PM PDT 24
Peak memory 215540 kb
Host smart-7fcd8529-50df-4727-bf1f-80fb83af30cb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1969040827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.1969040827
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3037133844
Short name T2527
Test name
Test status
Simulation time 164158474 ps
CPU time 0.84 seconds
Started Jul 27 07:40:58 PM PDT 24
Finished Jul 27 07:40:59 PM PDT 24
Peak memory 207220 kb
Host smart-03e8019a-03ac-4a57-974a-10f814678b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30371
33844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3037133844
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1223283502
Short name T1215
Test name
Test status
Simulation time 179572195 ps
CPU time 0.91 seconds
Started Jul 27 07:41:02 PM PDT 24
Finished Jul 27 07:41:03 PM PDT 24
Peak memory 207120 kb
Host smart-8169161d-3d16-4819-9924-625767a3ef90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12232
83502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1223283502
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.4031178335
Short name T658
Test name
Test status
Simulation time 1265010976 ps
CPU time 3.16 seconds
Started Jul 27 07:40:58 PM PDT 24
Finished Jul 27 07:41:01 PM PDT 24
Peak memory 207372 kb
Host smart-86f1331f-cf0b-4495-8a8f-8f1c6a17285c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40311
78335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.4031178335
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2680314323
Short name T462
Test name
Test status
Simulation time 3513698711 ps
CPU time 36.83 seconds
Started Jul 27 07:41:01 PM PDT 24
Finished Jul 27 07:41:38 PM PDT 24
Peak memory 216752 kb
Host smart-eba5e327-2ae6-4993-b13e-be446220928d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26803
14323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2680314323
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.241356664
Short name T2784
Test name
Test status
Simulation time 437880597 ps
CPU time 8.11 seconds
Started Jul 27 07:40:50 PM PDT 24
Finished Jul 27 07:40:59 PM PDT 24
Peak memory 207416 kb
Host smart-b499a319-168a-492f-91ef-1455ace3f02b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241356664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_host
_handshake.241356664
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.292518083
Short name T1989
Test name
Test status
Simulation time 51241340 ps
CPU time 0.67 seconds
Started Jul 27 07:41:19 PM PDT 24
Finished Jul 27 07:41:20 PM PDT 24
Peak memory 207032 kb
Host smart-f55f117b-b3e3-499c-bcbb-9c3d14955cf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=292518083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.292518083
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.1999431091
Short name T1747
Test name
Test status
Simulation time 3949514849 ps
CPU time 6.12 seconds
Started Jul 27 07:40:58 PM PDT 24
Finished Jul 27 07:41:04 PM PDT 24
Peak memory 207340 kb
Host smart-0dcd7ace-ef5a-45fc-a7fa-7a0c0f76f652
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999431091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.1999431091
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.1965975832
Short name T713
Test name
Test status
Simulation time 13351181178 ps
CPU time 19.09 seconds
Started Jul 27 07:40:57 PM PDT 24
Finished Jul 27 07:41:16 PM PDT 24
Peak memory 207332 kb
Host smart-53c6c687-f2e8-41ee-8ed1-948675f9b8f6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965975832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.1965975832
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.1874740547
Short name T1794
Test name
Test status
Simulation time 23320386576 ps
CPU time 33.12 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:41:37 PM PDT 24
Peak memory 207400 kb
Host smart-5042e3bf-d5d3-4060-8371-d749a4886765
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874740547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.1874740547
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1755839305
Short name T1055
Test name
Test status
Simulation time 179857062 ps
CPU time 0.89 seconds
Started Jul 27 07:41:03 PM PDT 24
Finished Jul 27 07:41:04 PM PDT 24
Peak memory 207216 kb
Host smart-337a832f-268b-4faf-ad8e-385d20450fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17558
39305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1755839305
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.902180479
Short name T559
Test name
Test status
Simulation time 149874997 ps
CPU time 0.82 seconds
Started Jul 27 07:41:05 PM PDT 24
Finished Jul 27 07:41:06 PM PDT 24
Peak memory 207104 kb
Host smart-2a308f38-927b-4d75-ae87-f1e5de343029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90218
0479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.902180479
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.2926133952
Short name T628
Test name
Test status
Simulation time 539536490 ps
CPU time 1.67 seconds
Started Jul 27 07:41:06 PM PDT 24
Finished Jul 27 07:41:07 PM PDT 24
Peak memory 207068 kb
Host smart-e27c88fa-1f7b-439b-a7f2-8ae521b738ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29261
33952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.2926133952
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2680980358
Short name T2382
Test name
Test status
Simulation time 1487271419 ps
CPU time 3.41 seconds
Started Jul 27 07:41:03 PM PDT 24
Finished Jul 27 07:41:07 PM PDT 24
Peak memory 207272 kb
Host smart-c991cb9c-8f24-429d-a195-eb7d5b42f17f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2680980358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2680980358
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.8194253
Short name T337
Test name
Test status
Simulation time 21988135388 ps
CPU time 46.96 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:41:51 PM PDT 24
Peak memory 207548 kb
Host smart-5b1c7a9c-8f8b-4a85-be79-68ed2e358cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81942
53 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.8194253
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.2642065861
Short name T1206
Test name
Test status
Simulation time 3778760564 ps
CPU time 24.23 seconds
Started Jul 27 07:41:02 PM PDT 24
Finished Jul 27 07:41:27 PM PDT 24
Peak memory 207436 kb
Host smart-172b5929-5da6-4799-91f3-0c90a3bf5f8a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642065861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.2642065861
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.918507990
Short name T288
Test name
Test status
Simulation time 385727848 ps
CPU time 1.46 seconds
Started Jul 27 07:41:03 PM PDT 24
Finished Jul 27 07:41:05 PM PDT 24
Peak memory 207160 kb
Host smart-2fa29ffd-dcec-4f6c-97e2-f1d90d105658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91850
7990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.918507990
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.4065744059
Short name T1350
Test name
Test status
Simulation time 152025404 ps
CPU time 0.78 seconds
Started Jul 27 07:41:03 PM PDT 24
Finished Jul 27 07:41:04 PM PDT 24
Peak memory 206980 kb
Host smart-bd2d2b59-3ea6-4d92-800a-fc85e89aec9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40657
44059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.4065744059
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.2215492119
Short name T1011
Test name
Test status
Simulation time 45053528 ps
CPU time 0.7 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:41:05 PM PDT 24
Peak memory 207048 kb
Host smart-824017c6-81f6-44ae-aca0-77fa35788975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22154
92119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2215492119
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.4086774859
Short name T2683
Test name
Test status
Simulation time 862446348 ps
CPU time 2.32 seconds
Started Jul 27 07:41:19 PM PDT 24
Finished Jul 27 07:41:22 PM PDT 24
Peak memory 207292 kb
Host smart-a53c2733-9226-4f75-a883-8c00400929fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40867
74859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.4086774859
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3525018902
Short name T1991
Test name
Test status
Simulation time 204953965 ps
CPU time 1.71 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:41:06 PM PDT 24
Peak memory 207324 kb
Host smart-d674e3ef-2e0f-4a2b-b893-f70fa09d3844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35250
18902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3525018902
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3262410859
Short name T2135
Test name
Test status
Simulation time 216892793 ps
CPU time 1.17 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:41:05 PM PDT 24
Peak memory 215552 kb
Host smart-379fdf53-d12d-4d5e-b036-75fd2cbf34da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3262410859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3262410859
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2891460227
Short name T1357
Test name
Test status
Simulation time 139650694 ps
CPU time 0.81 seconds
Started Jul 27 07:41:05 PM PDT 24
Finished Jul 27 07:41:05 PM PDT 24
Peak memory 207092 kb
Host smart-a9a6a5dd-47c2-42c2-9987-1e29358c7a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28914
60227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2891460227
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2895882549
Short name T1141
Test name
Test status
Simulation time 248409664 ps
CPU time 1.03 seconds
Started Jul 27 07:41:01 PM PDT 24
Finished Jul 27 07:41:02 PM PDT 24
Peak memory 207120 kb
Host smart-6d0f8ea0-a129-4719-9470-deb0948a4ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28958
82549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2895882549
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.1759680770
Short name T812
Test name
Test status
Simulation time 7903102186 ps
CPU time 67.14 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:42:11 PM PDT 24
Peak memory 215492 kb
Host smart-e9d3cb00-e09d-49e9-ad60-cb6a90d9b0a0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1759680770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.1759680770
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1113205125
Short name T1953
Test name
Test status
Simulation time 158481392 ps
CPU time 0.85 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:41:05 PM PDT 24
Peak memory 207096 kb
Host smart-b51d40dd-99fe-47c2-b6d9-b3576f9f052f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11132
05125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1113205125
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.2369764945
Short name T2568
Test name
Test status
Simulation time 23318029547 ps
CPU time 30.21 seconds
Started Jul 27 07:41:01 PM PDT 24
Finished Jul 27 07:41:31 PM PDT 24
Peak memory 207256 kb
Host smart-5c022348-fe88-4631-b6f6-05759b90cccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23697
64945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.2369764945
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.112213895
Short name T1434
Test name
Test status
Simulation time 3323092727 ps
CPU time 5.1 seconds
Started Jul 27 07:41:02 PM PDT 24
Finished Jul 27 07:41:07 PM PDT 24
Peak memory 207360 kb
Host smart-6c3bb862-2cca-4a66-aa2e-c0873a3cbafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11221
3895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.112213895
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2188659964
Short name T2149
Test name
Test status
Simulation time 6738337816 ps
CPU time 63.4 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:42:08 PM PDT 24
Peak memory 217472 kb
Host smart-c440bfcd-e624-485d-bc1e-520ed1d35ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21886
59964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2188659964
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3037963446
Short name T1874
Test name
Test status
Simulation time 3845937427 ps
CPU time 38.62 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:41:42 PM PDT 24
Peak memory 215564 kb
Host smart-ff5e7840-0440-4fcc-8cd0-81a4c82ff39d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3037963446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3037963446
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2019812192
Short name T2122
Test name
Test status
Simulation time 265472863 ps
CPU time 1.08 seconds
Started Jul 27 07:41:19 PM PDT 24
Finished Jul 27 07:41:21 PM PDT 24
Peak memory 206960 kb
Host smart-e1a433fa-51ea-459b-9b74-598da4119b9a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2019812192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2019812192
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2154728693
Short name T584
Test name
Test status
Simulation time 231463647 ps
CPU time 1.03 seconds
Started Jul 27 07:41:03 PM PDT 24
Finished Jul 27 07:41:05 PM PDT 24
Peak memory 207116 kb
Host smart-e2208a8a-d280-412d-bc76-462e3cbd622d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21547
28693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2154728693
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.2700557373
Short name T1902
Test name
Test status
Simulation time 4502526025 ps
CPU time 122.36 seconds
Started Jul 27 07:41:14 PM PDT 24
Finished Jul 27 07:43:17 PM PDT 24
Peak memory 215616 kb
Host smart-457fec2f-86b0-4766-95b1-78d0e33c51e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27005
57373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.2700557373
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.4207613506
Short name T1295
Test name
Test status
Simulation time 6424448198 ps
CPU time 47.99 seconds
Started Jul 27 07:41:03 PM PDT 24
Finished Jul 27 07:41:51 PM PDT 24
Peak memory 207392 kb
Host smart-905e698f-068b-427a-be21-05f03125be92
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4207613506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.4207613506
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.3413830553
Short name T473
Test name
Test status
Simulation time 223798286 ps
CPU time 0.91 seconds
Started Jul 27 07:41:19 PM PDT 24
Finished Jul 27 07:41:20 PM PDT 24
Peak memory 207136 kb
Host smart-f88b526b-1767-4c77-b950-65265fc6f59c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3413830553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.3413830553
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.803402636
Short name T527
Test name
Test status
Simulation time 141964868 ps
CPU time 0.82 seconds
Started Jul 27 07:41:07 PM PDT 24
Finished Jul 27 07:41:08 PM PDT 24
Peak memory 207100 kb
Host smart-16470f78-ffcb-42bd-8f4c-457ff2f6ad7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80340
2636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.803402636
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.633488405
Short name T117
Test name
Test status
Simulation time 166961429 ps
CPU time 0.94 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:41:05 PM PDT 24
Peak memory 207140 kb
Host smart-8553438f-65fc-46ff-af3a-909a6b7711bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63348
8405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.633488405
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3121587617
Short name T696
Test name
Test status
Simulation time 229925270 ps
CPU time 0.95 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:41:05 PM PDT 24
Peak memory 207100 kb
Host smart-daf23ea4-296e-4529-9067-360d250fb311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31215
87617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3121587617
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1120774026
Short name T354
Test name
Test status
Simulation time 215039477 ps
CPU time 0.95 seconds
Started Jul 27 07:41:08 PM PDT 24
Finished Jul 27 07:41:09 PM PDT 24
Peak memory 207060 kb
Host smart-999b5f7d-96d9-4123-9d8c-ebebbab7bb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11207
74026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1120774026
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1948961366
Short name T541
Test name
Test status
Simulation time 214434800 ps
CPU time 0.93 seconds
Started Jul 27 07:41:02 PM PDT 24
Finished Jul 27 07:41:03 PM PDT 24
Peak memory 207028 kb
Host smart-36adbe08-01fd-40ba-b1f5-3243493558bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19489
61366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1948961366
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1909648204
Short name T685
Test name
Test status
Simulation time 222864124 ps
CPU time 0.93 seconds
Started Jul 27 07:41:03 PM PDT 24
Finished Jul 27 07:41:04 PM PDT 24
Peak memory 207196 kb
Host smart-88d1a3b5-c4f5-42d4-8f3d-9a3abd70c9c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19096
48204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1909648204
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.2541639981
Short name T2543
Test name
Test status
Simulation time 210430872 ps
CPU time 0.97 seconds
Started Jul 27 07:41:02 PM PDT 24
Finished Jul 27 07:41:04 PM PDT 24
Peak memory 207108 kb
Host smart-eb586c8a-3123-49d3-ad83-35e08832464d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2541639981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.2541639981
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3099366090
Short name T1418
Test name
Test status
Simulation time 152772869 ps
CPU time 0.89 seconds
Started Jul 27 07:41:13 PM PDT 24
Finished Jul 27 07:41:14 PM PDT 24
Peak memory 207132 kb
Host smart-c73e3a9e-c1e3-4dab-8714-edc7d92d405d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30993
66090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3099366090
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.4255059955
Short name T1309
Test name
Test status
Simulation time 40538797 ps
CPU time 0.69 seconds
Started Jul 27 07:41:08 PM PDT 24
Finished Jul 27 07:41:09 PM PDT 24
Peak memory 207096 kb
Host smart-4a41e18d-d6fd-41a5-8814-6cb3c5054d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42550
59955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.4255059955
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3490517478
Short name T1182
Test name
Test status
Simulation time 19608184916 ps
CPU time 50.22 seconds
Started Jul 27 07:41:11 PM PDT 24
Finished Jul 27 07:42:01 PM PDT 24
Peak memory 215620 kb
Host smart-1e17b065-d568-44a0-bd80-a033ae44a910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34905
17478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3490517478
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2752504031
Short name T1223
Test name
Test status
Simulation time 192953121 ps
CPU time 0.96 seconds
Started Jul 27 07:41:11 PM PDT 24
Finished Jul 27 07:41:12 PM PDT 24
Peak memory 207208 kb
Host smart-928c8fa2-a123-4d7f-92b8-7cfb4328ea86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27525
04031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2752504031
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1747902423
Short name T2439
Test name
Test status
Simulation time 242587995 ps
CPU time 1.02 seconds
Started Jul 27 07:41:07 PM PDT 24
Finished Jul 27 07:41:08 PM PDT 24
Peak memory 207136 kb
Host smart-b6328517-f147-4727-9aa6-036d0e84fc93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17479
02423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1747902423
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.1743280888
Short name T1022
Test name
Test status
Simulation time 218479844 ps
CPU time 0.92 seconds
Started Jul 27 07:41:07 PM PDT 24
Finished Jul 27 07:41:08 PM PDT 24
Peak memory 207120 kb
Host smart-f4a74f47-624c-49b4-9fe7-d62894d36f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17432
80888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.1743280888
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.234577843
Short name T1230
Test name
Test status
Simulation time 182451937 ps
CPU time 0.93 seconds
Started Jul 27 07:41:08 PM PDT 24
Finished Jul 27 07:41:10 PM PDT 24
Peak memory 207072 kb
Host smart-888c0f5b-5ca4-4c0a-9b27-e020d52da018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23457
7843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.234577843
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.882537020
Short name T1887
Test name
Test status
Simulation time 176115225 ps
CPU time 0.87 seconds
Started Jul 27 07:41:08 PM PDT 24
Finished Jul 27 07:41:09 PM PDT 24
Peak memory 207120 kb
Host smart-21761d15-915f-4730-9114-b2036b2de182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88253
7020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.882537020
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.731765038
Short name T1842
Test name
Test status
Simulation time 203933156 ps
CPU time 0.96 seconds
Started Jul 27 07:41:10 PM PDT 24
Finished Jul 27 07:41:11 PM PDT 24
Peak memory 206864 kb
Host smart-646f8695-7eac-4432-a338-d59442b3d358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73176
5038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.731765038
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1997516350
Short name T446
Test name
Test status
Simulation time 183237634 ps
CPU time 0.87 seconds
Started Jul 27 07:41:09 PM PDT 24
Finished Jul 27 07:41:10 PM PDT 24
Peak memory 207112 kb
Host smart-9211d2a9-a80c-49ad-8c27-dc40f60016d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19975
16350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1997516350
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.953610949
Short name T2393
Test name
Test status
Simulation time 200689227 ps
CPU time 0.95 seconds
Started Jul 27 07:41:10 PM PDT 24
Finished Jul 27 07:41:11 PM PDT 24
Peak memory 207136 kb
Host smart-053bb64c-2d9b-46fa-9464-7d413aade4c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95361
0949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.953610949
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.1428705230
Short name T1795
Test name
Test status
Simulation time 5867214977 ps
CPU time 46.55 seconds
Started Jul 27 07:41:10 PM PDT 24
Finished Jul 27 07:41:56 PM PDT 24
Peak memory 217076 kb
Host smart-6bb1add8-4a6d-4bc8-a685-fbdbb12c0176
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1428705230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.1428705230
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3465664668
Short name T2845
Test name
Test status
Simulation time 176957796 ps
CPU time 0.89 seconds
Started Jul 27 07:41:10 PM PDT 24
Finished Jul 27 07:41:11 PM PDT 24
Peak memory 207144 kb
Host smart-cb67c3cf-854f-4576-9a78-dc2271f50f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34656
64668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3465664668
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.1822907291
Short name T1650
Test name
Test status
Simulation time 167837732 ps
CPU time 0.87 seconds
Started Jul 27 07:41:09 PM PDT 24
Finished Jul 27 07:41:10 PM PDT 24
Peak memory 207108 kb
Host smart-b26ef317-8030-4c44-b152-8f149e29f0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18229
07291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1822907291
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.4056209628
Short name T1801
Test name
Test status
Simulation time 1076026357 ps
CPU time 2.59 seconds
Started Jul 27 07:41:19 PM PDT 24
Finished Jul 27 07:41:22 PM PDT 24
Peak memory 207356 kb
Host smart-921702fa-6e91-4064-a911-edd12663f443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40562
09628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.4056209628
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1521315638
Short name T1239
Test name
Test status
Simulation time 4456866007 ps
CPU time 44.83 seconds
Started Jul 27 07:41:19 PM PDT 24
Finished Jul 27 07:42:04 PM PDT 24
Peak memory 215512 kb
Host smart-41d266c8-6dec-4d29-b601-85b1ccacc849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15213
15638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1521315638
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.2669183453
Short name T2035
Test name
Test status
Simulation time 1311893337 ps
CPU time 30.64 seconds
Started Jul 27 07:41:04 PM PDT 24
Finished Jul 27 07:41:35 PM PDT 24
Peak memory 207328 kb
Host smart-7686cd91-74ac-4313-a96a-f407e8a3eade
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669183453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.2669183453
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.605600412
Short name T1026
Test name
Test status
Simulation time 33705342 ps
CPU time 0.66 seconds
Started Jul 27 07:41:25 PM PDT 24
Finished Jul 27 07:41:26 PM PDT 24
Peak memory 207116 kb
Host smart-a8d394ca-589d-4ab3-b90e-dd02c552368a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=605600412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.605600412
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3111305540
Short name T2466
Test name
Test status
Simulation time 4320319482 ps
CPU time 6.03 seconds
Started Jul 27 07:41:08 PM PDT 24
Finished Jul 27 07:41:14 PM PDT 24
Peak memory 207308 kb
Host smart-9b7c16ae-f9a4-41b5-b999-3421c084a91d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111305540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.3111305540
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.1868464115
Short name T2131
Test name
Test status
Simulation time 13334235391 ps
CPU time 16.66 seconds
Started Jul 27 07:41:07 PM PDT 24
Finished Jul 27 07:41:24 PM PDT 24
Peak memory 207404 kb
Host smart-d96e30e2-1ded-47a6-bdc4-8b05efb12207
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868464115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.1868464115
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.331306340
Short name T2557
Test name
Test status
Simulation time 23318842462 ps
CPU time 33.81 seconds
Started Jul 27 07:41:09 PM PDT 24
Finished Jul 27 07:41:43 PM PDT 24
Peak memory 207296 kb
Host smart-6c20e396-ec81-43be-8e1d-adcd301cecd6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331306340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ao
n_wake_resume.331306340
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2796543187
Short name T495
Test name
Test status
Simulation time 155234105 ps
CPU time 0.81 seconds
Started Jul 27 07:41:09 PM PDT 24
Finished Jul 27 07:41:10 PM PDT 24
Peak memory 207116 kb
Host smart-48dda53d-6f33-43aa-bdf3-ff8d1062de50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27965
43187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2796543187
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.473721536
Short name T1713
Test name
Test status
Simulation time 170643090 ps
CPU time 0.86 seconds
Started Jul 27 07:41:08 PM PDT 24
Finished Jul 27 07:41:09 PM PDT 24
Peak memory 207080 kb
Host smart-95acc383-2daa-4ddf-afb6-716c5976ba02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47372
1536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.473721536
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2239080427
Short name T1478
Test name
Test status
Simulation time 405497796 ps
CPU time 1.45 seconds
Started Jul 27 07:41:11 PM PDT 24
Finished Jul 27 07:41:13 PM PDT 24
Peak memory 207152 kb
Host smart-5e62c517-550c-4332-853d-820531d33ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22390
80427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2239080427
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.1290823781
Short name T956
Test name
Test status
Simulation time 1096446031 ps
CPU time 2.9 seconds
Started Jul 27 07:41:08 PM PDT 24
Finished Jul 27 07:41:12 PM PDT 24
Peak memory 207264 kb
Host smart-24ddb1c4-d83f-4bd3-be87-b4a575635207
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1290823781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.1290823781
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.433515284
Short name T341
Test name
Test status
Simulation time 10583801274 ps
CPU time 25.05 seconds
Started Jul 27 07:41:09 PM PDT 24
Finished Jul 27 07:41:34 PM PDT 24
Peak memory 207260 kb
Host smart-6390e133-9af6-41c3-a577-689dfe59272c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43351
5284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.433515284
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.3652637066
Short name T89
Test name
Test status
Simulation time 1304676414 ps
CPU time 30.67 seconds
Started Jul 27 07:41:10 PM PDT 24
Finished Jul 27 07:41:41 PM PDT 24
Peak memory 207380 kb
Host smart-3430e9d8-043c-4c75-90cb-6a0243eebfbc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652637066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.3652637066
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2267379074
Short name T1924
Test name
Test status
Simulation time 145445005 ps
CPU time 0.85 seconds
Started Jul 27 07:41:16 PM PDT 24
Finished Jul 27 07:41:17 PM PDT 24
Peak memory 207040 kb
Host smart-a4bd967a-deed-4301-b13e-83bfda62fcd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22673
79074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2267379074
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.1425674957
Short name T361
Test name
Test status
Simulation time 69027521 ps
CPU time 0.74 seconds
Started Jul 27 07:41:15 PM PDT 24
Finished Jul 27 07:41:16 PM PDT 24
Peak memory 207036 kb
Host smart-be1055de-baed-4f58-9b5a-b6d79ad41975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14256
74957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1425674957
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.1251552566
Short name T2252
Test name
Test status
Simulation time 903722435 ps
CPU time 2.36 seconds
Started Jul 27 07:41:15 PM PDT 24
Finished Jul 27 07:41:17 PM PDT 24
Peak memory 207352 kb
Host smart-97867e85-f95c-48af-a029-cbd35367d52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12515
52566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.1251552566
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2720507389
Short name T681
Test name
Test status
Simulation time 203354166 ps
CPU time 1.64 seconds
Started Jul 27 07:41:16 PM PDT 24
Finished Jul 27 07:41:18 PM PDT 24
Peak memory 207280 kb
Host smart-74f58638-064e-4515-bdcd-e8b5e5fcc128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27205
07389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2720507389
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2208548020
Short name T1155
Test name
Test status
Simulation time 187989678 ps
CPU time 1.01 seconds
Started Jul 27 07:41:19 PM PDT 24
Finished Jul 27 07:41:20 PM PDT 24
Peak memory 207324 kb
Host smart-8be9695e-98b2-45a4-ac93-bbb3b706b3e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2208548020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2208548020
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1529502596
Short name T1841
Test name
Test status
Simulation time 159052166 ps
CPU time 0.87 seconds
Started Jul 27 07:41:19 PM PDT 24
Finished Jul 27 07:41:21 PM PDT 24
Peak memory 207080 kb
Host smart-3704067e-79e2-4a4e-a94b-fbeac6e7dadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15295
02596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1529502596
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3993207829
Short name T2488
Test name
Test status
Simulation time 169634336 ps
CPU time 0.88 seconds
Started Jul 27 07:41:16 PM PDT 24
Finished Jul 27 07:41:17 PM PDT 24
Peak memory 207132 kb
Host smart-219ebc6f-f217-4c41-aa46-f938ade1aeb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39932
07829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3993207829
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.2055852306
Short name T83
Test name
Test status
Simulation time 9862338442 ps
CPU time 76.89 seconds
Started Jul 27 07:41:15 PM PDT 24
Finished Jul 27 07:42:32 PM PDT 24
Peak memory 216668 kb
Host smart-2aaaf5cb-46de-4e4f-9a44-f699c9a9893a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2055852306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.2055852306
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.148726934
Short name T2462
Test name
Test status
Simulation time 6524068694 ps
CPU time 42.29 seconds
Started Jul 27 07:41:18 PM PDT 24
Finished Jul 27 07:42:00 PM PDT 24
Peak memory 207396 kb
Host smart-90562e8a-e629-4453-b16d-e672fca50a7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=148726934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.148726934
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.587398835
Short name T1950
Test name
Test status
Simulation time 280369218 ps
CPU time 1.16 seconds
Started Jul 27 07:41:17 PM PDT 24
Finished Jul 27 07:41:18 PM PDT 24
Peak memory 207328 kb
Host smart-a9860547-beb6-4d75-9106-97733530c2fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58739
8835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.587398835
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.1863054866
Short name T1663
Test name
Test status
Simulation time 23351094066 ps
CPU time 30.84 seconds
Started Jul 27 07:41:17 PM PDT 24
Finished Jul 27 07:41:48 PM PDT 24
Peak memory 207372 kb
Host smart-80d4353b-eb6a-4b5d-976d-41afa98df8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18630
54866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1863054866
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.697885216
Short name T1179
Test name
Test status
Simulation time 3316708844 ps
CPU time 4.96 seconds
Started Jul 27 07:41:17 PM PDT 24
Finished Jul 27 07:41:23 PM PDT 24
Peak memory 207364 kb
Host smart-37aca0f7-e5bb-4641-a591-2b6ce25ca49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69788
5216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.697885216
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.3701389566
Short name T1743
Test name
Test status
Simulation time 5444473501 ps
CPU time 161.62 seconds
Started Jul 27 07:41:16 PM PDT 24
Finished Jul 27 07:43:58 PM PDT 24
Peak memory 215588 kb
Host smart-e4008adb-7f97-46b7-931a-75c42dfa7a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37013
89566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.3701389566
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.1145478535
Short name T1511
Test name
Test status
Simulation time 6019564012 ps
CPU time 178.93 seconds
Started Jul 27 07:41:14 PM PDT 24
Finished Jul 27 07:44:13 PM PDT 24
Peak memory 215580 kb
Host smart-757f8835-5a92-47c1-9b2b-58e2e2a1337c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1145478535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.1145478535
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.2036345581
Short name T2542
Test name
Test status
Simulation time 253579193 ps
CPU time 0.99 seconds
Started Jul 27 07:41:17 PM PDT 24
Finished Jul 27 07:41:18 PM PDT 24
Peak memory 207168 kb
Host smart-6d025bdd-4dbf-4fa1-99cc-206d1945dc11
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2036345581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.2036345581
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.142185758
Short name T1893
Test name
Test status
Simulation time 204003768 ps
CPU time 0.92 seconds
Started Jul 27 07:41:16 PM PDT 24
Finished Jul 27 07:41:18 PM PDT 24
Peak memory 207124 kb
Host smart-20032e88-619e-4209-9ab0-c76447ee4aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14218
5758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.142185758
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.3775124838
Short name T2000
Test name
Test status
Simulation time 6510447402 ps
CPU time 49.39 seconds
Started Jul 27 07:41:20 PM PDT 24
Finished Jul 27 07:42:10 PM PDT 24
Peak memory 217148 kb
Host smart-0af64bd5-7a46-4ca3-90bf-9c3c767e7874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37751
24838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.3775124838
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.3320015313
Short name T1964
Test name
Test status
Simulation time 3216000176 ps
CPU time 24.5 seconds
Started Jul 27 07:41:18 PM PDT 24
Finished Jul 27 07:41:43 PM PDT 24
Peak memory 215620 kb
Host smart-8d0262db-8e3d-4c61-a716-991f27720b5e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3320015313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.3320015313
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1368531749
Short name T1538
Test name
Test status
Simulation time 163381112 ps
CPU time 0.89 seconds
Started Jul 27 07:41:17 PM PDT 24
Finished Jul 27 07:41:18 PM PDT 24
Peak memory 207164 kb
Host smart-a2db05fc-6eec-4b12-9120-01d2e1610049
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1368531749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1368531749
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3277159218
Short name T1508
Test name
Test status
Simulation time 243801653 ps
CPU time 0.92 seconds
Started Jul 27 07:41:16 PM PDT 24
Finished Jul 27 07:41:17 PM PDT 24
Peak memory 207092 kb
Host smart-fb7638d7-b446-44b0-9603-0917d05776e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32771
59218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3277159218
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2078509104
Short name T148
Test name
Test status
Simulation time 173104858 ps
CPU time 0.87 seconds
Started Jul 27 07:41:16 PM PDT 24
Finished Jul 27 07:41:17 PM PDT 24
Peak memory 207136 kb
Host smart-ccfe8c53-5b61-4583-8b6a-dfd9c8ea5d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20785
09104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2078509104
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.149624987
Short name T2855
Test name
Test status
Simulation time 157329745 ps
CPU time 0.82 seconds
Started Jul 27 07:41:15 PM PDT 24
Finished Jul 27 07:41:16 PM PDT 24
Peak memory 207108 kb
Host smart-94a0a9d7-cde1-422b-881d-16853c15254f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14962
4987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.149624987
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.699129169
Short name T2589
Test name
Test status
Simulation time 210843058 ps
CPU time 0.92 seconds
Started Jul 27 07:41:16 PM PDT 24
Finished Jul 27 07:41:17 PM PDT 24
Peak memory 207100 kb
Host smart-72397304-4b3f-4724-a06c-245b0fdc05fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69912
9169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.699129169
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3113556406
Short name T237
Test name
Test status
Simulation time 169496858 ps
CPU time 0.87 seconds
Started Jul 27 07:41:16 PM PDT 24
Finished Jul 27 07:41:17 PM PDT 24
Peak memory 207100 kb
Host smart-3078830c-c559-49ee-93d8-a700d81daa82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31135
56406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3113556406
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1784640471
Short name T1082
Test name
Test status
Simulation time 153098475 ps
CPU time 0.84 seconds
Started Jul 27 07:41:17 PM PDT 24
Finished Jul 27 07:41:18 PM PDT 24
Peak memory 207120 kb
Host smart-68e6bb2e-71f0-4e3c-8827-10bf9c7c68b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17846
40471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1784640471
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.4094537413
Short name T1796
Test name
Test status
Simulation time 229356645 ps
CPU time 1.01 seconds
Started Jul 27 07:41:16 PM PDT 24
Finished Jul 27 07:41:17 PM PDT 24
Peak memory 207100 kb
Host smart-99ed7957-e9c0-4f00-8825-38ad2461c1b7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4094537413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.4094537413
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1829198400
Short name T1825
Test name
Test status
Simulation time 154196904 ps
CPU time 0.84 seconds
Started Jul 27 07:41:15 PM PDT 24
Finished Jul 27 07:41:16 PM PDT 24
Peak memory 207068 kb
Host smart-83a52212-c304-4381-bbbf-9232cda1f1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18291
98400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1829198400
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3176582902
Short name T347
Test name
Test status
Simulation time 20406940471 ps
CPU time 56.08 seconds
Started Jul 27 07:41:15 PM PDT 24
Finished Jul 27 07:42:12 PM PDT 24
Peak memory 215620 kb
Host smart-97f2e3f7-a523-44d4-9561-ece58717b917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31765
82902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3176582902
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2527909002
Short name T1857
Test name
Test status
Simulation time 188693973 ps
CPU time 0.92 seconds
Started Jul 27 07:41:16 PM PDT 24
Finished Jul 27 07:41:17 PM PDT 24
Peak memory 207120 kb
Host smart-8d2e37f9-7348-4b3d-adb3-090d1387ec6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25279
09002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2527909002
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.655906692
Short name T2253
Test name
Test status
Simulation time 204911631 ps
CPU time 0.95 seconds
Started Jul 27 07:41:21 PM PDT 24
Finished Jul 27 07:41:23 PM PDT 24
Peak memory 207096 kb
Host smart-ddd71288-e564-4db9-9cf1-b56943138b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65590
6692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.655906692
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1686464767
Short name T2648
Test name
Test status
Simulation time 197772132 ps
CPU time 0.95 seconds
Started Jul 27 07:41:21 PM PDT 24
Finished Jul 27 07:41:22 PM PDT 24
Peak memory 207092 kb
Host smart-f9d66539-ffb1-496d-b2af-6feb492c5804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16864
64767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1686464767
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3660755652
Short name T1245
Test name
Test status
Simulation time 200562749 ps
CPU time 0.89 seconds
Started Jul 27 07:41:21 PM PDT 24
Finished Jul 27 07:41:22 PM PDT 24
Peak memory 207124 kb
Host smart-97637b44-17ee-4b26-b2f0-a413118c6531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36607
55652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3660755652
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2549925529
Short name T2853
Test name
Test status
Simulation time 186312231 ps
CPU time 0.89 seconds
Started Jul 27 07:41:26 PM PDT 24
Finished Jul 27 07:41:27 PM PDT 24
Peak memory 207112 kb
Host smart-96bac655-be68-46b6-9f86-4044f490e289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25499
25529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2549925529
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2944607622
Short name T1293
Test name
Test status
Simulation time 162806520 ps
CPU time 0.82 seconds
Started Jul 27 07:41:19 PM PDT 24
Finished Jul 27 07:41:20 PM PDT 24
Peak memory 207064 kb
Host smart-4fa25ff2-bbe0-4703-a520-1020d7ba4197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29446
07622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2944607622
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3781972655
Short name T2405
Test name
Test status
Simulation time 171593784 ps
CPU time 0.89 seconds
Started Jul 27 07:41:22 PM PDT 24
Finished Jul 27 07:41:23 PM PDT 24
Peak memory 207064 kb
Host smart-4cd4cbc8-6377-4dd6-84aa-03e7ede8440c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37819
72655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3781972655
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1182526107
Short name T2391
Test name
Test status
Simulation time 234875023 ps
CPU time 0.98 seconds
Started Jul 27 07:41:22 PM PDT 24
Finished Jul 27 07:41:23 PM PDT 24
Peak memory 207068 kb
Host smart-2f9d2ea3-cafb-40ed-bed2-39a270dc630a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11825
26107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1182526107
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.906890020
Short name T151
Test name
Test status
Simulation time 5005718813 ps
CPU time 39.9 seconds
Started Jul 27 07:41:23 PM PDT 24
Finished Jul 27 07:42:03 PM PDT 24
Peak memory 215580 kb
Host smart-9860db7c-a3ad-433e-afe0-93eaf9238919
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=906890020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.906890020
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2919450547
Short name T2404
Test name
Test status
Simulation time 166274591 ps
CPU time 0.84 seconds
Started Jul 27 07:41:23 PM PDT 24
Finished Jul 27 07:41:24 PM PDT 24
Peak memory 207116 kb
Host smart-dcd47ca3-e8e7-4925-b878-58057355ccc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29194
50547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2919450547
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1362715137
Short name T561
Test name
Test status
Simulation time 197006443 ps
CPU time 0.93 seconds
Started Jul 27 07:41:23 PM PDT 24
Finished Jul 27 07:41:24 PM PDT 24
Peak memory 207072 kb
Host smart-75ac0d37-77c5-4f36-ba79-56aacd5f282d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13627
15137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1362715137
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.464891355
Short name T2821
Test name
Test status
Simulation time 1097816659 ps
CPU time 2.6 seconds
Started Jul 27 07:41:26 PM PDT 24
Finished Jul 27 07:41:29 PM PDT 24
Peak memory 207300 kb
Host smart-cd6fd0ef-a2ed-40f3-a2d6-f8b66793039e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46489
1355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.464891355
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3111023504
Short name T1526
Test name
Test status
Simulation time 4080600434 ps
CPU time 123.99 seconds
Started Jul 27 07:41:23 PM PDT 24
Finished Jul 27 07:43:27 PM PDT 24
Peak memory 215544 kb
Host smart-ecb99a66-c1ae-43f5-844b-9569f85da859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31110
23504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3111023504
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.2104114794
Short name T53
Test name
Test status
Simulation time 1124928785 ps
CPU time 24.94 seconds
Started Jul 27 07:41:11 PM PDT 24
Finished Jul 27 07:41:36 PM PDT 24
Peak memory 207308 kb
Host smart-52a06399-0b2c-40c9-b9b2-9b9a273779d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104114794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_hos
t_handshake.2104114794
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.3438353479
Short name T1978
Test name
Test status
Simulation time 41728842 ps
CPU time 0.67 seconds
Started Jul 27 07:41:31 PM PDT 24
Finished Jul 27 07:41:32 PM PDT 24
Peak memory 207184 kb
Host smart-aaadad1f-7923-4ea9-9390-07be15399723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3438353479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.3438353479
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.3050658080
Short name T2524
Test name
Test status
Simulation time 4264791091 ps
CPU time 6.26 seconds
Started Jul 27 07:41:20 PM PDT 24
Finished Jul 27 07:41:27 PM PDT 24
Peak memory 207376 kb
Host smart-d3a7cabc-ced8-408e-af10-2c364272ba37
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050658080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.3050658080
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1336258954
Short name T1864
Test name
Test status
Simulation time 13394536016 ps
CPU time 16.29 seconds
Started Jul 27 07:41:22 PM PDT 24
Finished Jul 27 07:41:38 PM PDT 24
Peak memory 207332 kb
Host smart-7a37aa42-dca5-4dee-9b5c-e1c52aa7b178
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336258954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1336258954
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.2855313787
Short name T1353
Test name
Test status
Simulation time 23470974603 ps
CPU time 28.78 seconds
Started Jul 27 07:41:24 PM PDT 24
Finished Jul 27 07:41:53 PM PDT 24
Peak memory 207388 kb
Host smart-1a17027c-c451-4d3d-8f44-8b3153b01f00
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855313787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_resume.2855313787
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3726954403
Short name T1431
Test name
Test status
Simulation time 163863820 ps
CPU time 0.83 seconds
Started Jul 27 07:41:25 PM PDT 24
Finished Jul 27 07:41:26 PM PDT 24
Peak memory 207084 kb
Host smart-2d3787cb-8be4-46c0-97c2-8cece80f3f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37269
54403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3726954403
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2211433908
Short name T1214
Test name
Test status
Simulation time 141477311 ps
CPU time 0.86 seconds
Started Jul 27 07:41:24 PM PDT 24
Finished Jul 27 07:41:25 PM PDT 24
Peak memory 207040 kb
Host smart-9eb2adb7-d09c-4ea8-a11b-06c2180ee897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22114
33908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2211433908
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.1693479303
Short name T706
Test name
Test status
Simulation time 314010366 ps
CPU time 1.29 seconds
Started Jul 27 07:41:23 PM PDT 24
Finished Jul 27 07:41:25 PM PDT 24
Peak memory 207068 kb
Host smart-fd5b2029-12c4-47b3-a359-c40eb9f54dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16934
79303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.1693479303
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.977045158
Short name T338
Test name
Test status
Simulation time 841709095 ps
CPU time 2.28 seconds
Started Jul 27 07:41:23 PM PDT 24
Finished Jul 27 07:41:25 PM PDT 24
Peak memory 207356 kb
Host smart-97d0cd0f-a937-4680-ab12-4afcf1f788f1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=977045158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.977045158
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.301421875
Short name T1722
Test name
Test status
Simulation time 19278568857 ps
CPU time 43.85 seconds
Started Jul 27 07:41:24 PM PDT 24
Finished Jul 27 07:42:08 PM PDT 24
Peak memory 207484 kb
Host smart-850a997e-e321-463b-99e7-ca7463c3637d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30142
1875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.301421875
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.2543289405
Short name T1027
Test name
Test status
Simulation time 695879537 ps
CPU time 15.44 seconds
Started Jul 27 07:41:21 PM PDT 24
Finished Jul 27 07:41:36 PM PDT 24
Peak memory 207288 kb
Host smart-cd7e6a53-cac3-4094-b53b-76fca39d079d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543289405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.2543289405
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.511824916
Short name T289
Test name
Test status
Simulation time 421861024 ps
CPU time 1.36 seconds
Started Jul 27 07:41:25 PM PDT 24
Finished Jul 27 07:41:26 PM PDT 24
Peak memory 207096 kb
Host smart-bf0631c4-9849-4628-9d0c-b2f585db71f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51182
4916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.511824916
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3968195938
Short name T1727
Test name
Test status
Simulation time 146894505 ps
CPU time 0.83 seconds
Started Jul 27 07:41:21 PM PDT 24
Finished Jul 27 07:41:22 PM PDT 24
Peak memory 207108 kb
Host smart-9c6fc113-4148-408a-8679-43d9bddfc678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39681
95938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3968195938
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.2782366486
Short name T878
Test name
Test status
Simulation time 40469913 ps
CPU time 0.69 seconds
Started Jul 27 07:41:23 PM PDT 24
Finished Jul 27 07:41:24 PM PDT 24
Peak memory 207024 kb
Host smart-51be513c-b8e0-4a63-848d-1b5d61a311ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27823
66486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2782366486
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2386196044
Short name T1472
Test name
Test status
Simulation time 997837217 ps
CPU time 2.81 seconds
Started Jul 27 07:41:25 PM PDT 24
Finished Jul 27 07:41:28 PM PDT 24
Peak memory 207392 kb
Host smart-958f9e35-2f9e-4647-92d0-6b48cf3e8236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23861
96044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2386196044
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3910154446
Short name T749
Test name
Test status
Simulation time 373588553 ps
CPU time 2.67 seconds
Started Jul 27 07:41:23 PM PDT 24
Finished Jul 27 07:41:26 PM PDT 24
Peak memory 207264 kb
Host smart-c8b7c245-74f9-4486-b0ae-14000d8725c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39101
54446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3910154446
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.421802590
Short name T1912
Test name
Test status
Simulation time 239882423 ps
CPU time 1.3 seconds
Started Jul 27 07:41:21 PM PDT 24
Finished Jul 27 07:41:23 PM PDT 24
Peak memory 215528 kb
Host smart-a22fcc4d-72c8-4999-8746-ab67abcd6563
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=421802590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.421802590
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2360521277
Short name T1802
Test name
Test status
Simulation time 142510607 ps
CPU time 0.83 seconds
Started Jul 27 07:41:22 PM PDT 24
Finished Jul 27 07:41:23 PM PDT 24
Peak memory 206980 kb
Host smart-eb82d745-56e1-4249-a91f-847e13dde846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23605
21277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2360521277
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.102164118
Short name T1593
Test name
Test status
Simulation time 163046656 ps
CPU time 0.94 seconds
Started Jul 27 07:41:27 PM PDT 24
Finished Jul 27 07:41:28 PM PDT 24
Peak memory 207144 kb
Host smart-5ab7a689-faf1-4fc8-836a-896f41541f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10216
4118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.102164118
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.3066770305
Short name T979
Test name
Test status
Simulation time 7493717151 ps
CPU time 221.88 seconds
Started Jul 27 07:41:22 PM PDT 24
Finished Jul 27 07:45:05 PM PDT 24
Peak memory 215608 kb
Host smart-7e0dccbb-fec0-4f21-89bf-e2bf22adb409
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3066770305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.3066770305
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.2946705193
Short name T1553
Test name
Test status
Simulation time 7151623737 ps
CPU time 81.62 seconds
Started Jul 27 07:41:23 PM PDT 24
Finished Jul 27 07:42:45 PM PDT 24
Peak memory 207348 kb
Host smart-838dde6c-def7-42b5-a956-c394fc8297b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2946705193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.2946705193
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.859827356
Short name T1117
Test name
Test status
Simulation time 267171687 ps
CPU time 0.98 seconds
Started Jul 27 07:41:22 PM PDT 24
Finished Jul 27 07:41:24 PM PDT 24
Peak memory 207100 kb
Host smart-0479c487-db87-415f-9023-fd423ffbef83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85982
7356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.859827356
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.3565315131
Short name T1577
Test name
Test status
Simulation time 23281214176 ps
CPU time 30 seconds
Started Jul 27 07:41:25 PM PDT 24
Finished Jul 27 07:41:55 PM PDT 24
Peak memory 207428 kb
Host smart-07cb8565-ad00-4464-a573-1f22b49e88e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35653
15131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.3565315131
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.553710949
Short name T1072
Test name
Test status
Simulation time 3325961793 ps
CPU time 5.04 seconds
Started Jul 27 07:41:23 PM PDT 24
Finished Jul 27 07:41:28 PM PDT 24
Peak memory 207356 kb
Host smart-693aa3b5-7b31-4fa5-bf27-a54499f3e1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55371
0949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.553710949
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.2123374271
Short name T1798
Test name
Test status
Simulation time 6391602881 ps
CPU time 53.92 seconds
Started Jul 27 07:41:25 PM PDT 24
Finished Jul 27 07:42:19 PM PDT 24
Peak memory 217516 kb
Host smart-b40d6106-9d69-457d-a3a7-34631a3afb4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21233
74271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2123374271
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2207101659
Short name T2816
Test name
Test status
Simulation time 5879244932 ps
CPU time 173.78 seconds
Started Jul 27 07:41:25 PM PDT 24
Finished Jul 27 07:44:19 PM PDT 24
Peak memory 215580 kb
Host smart-8a752576-02e5-434f-92f0-4105fef358bd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2207101659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2207101659
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.922972022
Short name T463
Test name
Test status
Simulation time 302017771 ps
CPU time 1.05 seconds
Started Jul 27 07:41:24 PM PDT 24
Finished Jul 27 07:41:25 PM PDT 24
Peak memory 207172 kb
Host smart-f1fe0ae5-26d9-4446-9187-2dfebde822b0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=922972022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.922972022
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.4257550516
Short name T2757
Test name
Test status
Simulation time 184615751 ps
CPU time 0.95 seconds
Started Jul 27 07:41:23 PM PDT 24
Finished Jul 27 07:41:24 PM PDT 24
Peak memory 207196 kb
Host smart-f86556be-2fec-448c-bc03-5d9bb7de262e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42575
50516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.4257550516
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.84256792
Short name T1078
Test name
Test status
Simulation time 4293120340 ps
CPU time 43.13 seconds
Started Jul 27 07:41:22 PM PDT 24
Finished Jul 27 07:42:06 PM PDT 24
Peak memory 216856 kb
Host smart-a672baf3-e71f-4601-b66a-b0d8b985a708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84256
792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.84256792
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2298430268
Short name T1537
Test name
Test status
Simulation time 4347773891 ps
CPU time 123.63 seconds
Started Jul 27 07:41:32 PM PDT 24
Finished Jul 27 07:43:36 PM PDT 24
Peak memory 215572 kb
Host smart-6789ede5-0981-4175-bf54-aeb742965afd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2298430268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2298430268
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.3764329510
Short name T2522
Test name
Test status
Simulation time 227598470 ps
CPU time 0.94 seconds
Started Jul 27 07:41:32 PM PDT 24
Finished Jul 27 07:41:33 PM PDT 24
Peak memory 207132 kb
Host smart-328f3e7e-e178-40c6-a272-2046277bb07d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3764329510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.3764329510
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3852398848
Short name T2545
Test name
Test status
Simulation time 169526361 ps
CPU time 0.83 seconds
Started Jul 27 07:41:31 PM PDT 24
Finished Jul 27 07:41:32 PM PDT 24
Peak memory 207120 kb
Host smart-abf3f306-eab5-425e-999d-2159ad8857d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38523
98848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3852398848
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.59163180
Short name T1670
Test name
Test status
Simulation time 203335651 ps
CPU time 0.94 seconds
Started Jul 27 07:41:36 PM PDT 24
Finished Jul 27 07:41:37 PM PDT 24
Peak memory 207140 kb
Host smart-380b276d-2f87-4ba9-bee1-b1e6668ff72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59163
180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.59163180
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2562276952
Short name T820
Test name
Test status
Simulation time 173385688 ps
CPU time 0.89 seconds
Started Jul 27 07:41:37 PM PDT 24
Finished Jul 27 07:41:38 PM PDT 24
Peak memory 207140 kb
Host smart-82ac391a-89ce-4499-b80b-c1927a6b6797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25622
76952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2562276952
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.4046057097
Short name T798
Test name
Test status
Simulation time 174415377 ps
CPU time 0.88 seconds
Started Jul 27 07:41:36 PM PDT 24
Finished Jul 27 07:41:37 PM PDT 24
Peak memory 207136 kb
Host smart-48423e03-5c67-46c6-b974-b60ce33ec95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40460
57097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.4046057097
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1707466710
Short name T849
Test name
Test status
Simulation time 173126943 ps
CPU time 0.91 seconds
Started Jul 27 07:41:33 PM PDT 24
Finished Jul 27 07:41:34 PM PDT 24
Peak memory 207144 kb
Host smart-100e4e6b-6ba7-4794-a14d-4dbacdf81d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17074
66710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1707466710
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3940538108
Short name T108
Test name
Test status
Simulation time 151794263 ps
CPU time 0.85 seconds
Started Jul 27 07:41:33 PM PDT 24
Finished Jul 27 07:41:34 PM PDT 24
Peak memory 207140 kb
Host smart-06e54168-e304-499b-b83d-6b39668e3296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39405
38108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3940538108
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.464115379
Short name T442
Test name
Test status
Simulation time 199386291 ps
CPU time 0.95 seconds
Started Jul 27 07:41:33 PM PDT 24
Finished Jul 27 07:41:34 PM PDT 24
Peak memory 207136 kb
Host smart-72b162d9-fcc2-4c06-9b52-8eb5aeaeec50
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=464115379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.464115379
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1712920302
Short name T2085
Test name
Test status
Simulation time 145209091 ps
CPU time 0.82 seconds
Started Jul 27 07:41:30 PM PDT 24
Finished Jul 27 07:41:31 PM PDT 24
Peak memory 207120 kb
Host smart-b53d3eb4-7227-4c80-9c2a-7b1748a4a8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17129
20302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1712920302
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2512480710
Short name T2471
Test name
Test status
Simulation time 33242387 ps
CPU time 0.68 seconds
Started Jul 27 07:41:34 PM PDT 24
Finished Jul 27 07:41:35 PM PDT 24
Peak memory 207164 kb
Host smart-b60a56b9-2caa-42cc-ad0d-b915af773a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25124
80710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2512480710
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1647606786
Short name T1260
Test name
Test status
Simulation time 13944999838 ps
CPU time 35.58 seconds
Started Jul 27 07:41:32 PM PDT 24
Finished Jul 27 07:42:08 PM PDT 24
Peak memory 215508 kb
Host smart-6b6aab3d-9e54-4c49-92b0-ea07c0baed8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16476
06786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1647606786
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.2357508310
Short name T2735
Test name
Test status
Simulation time 163902654 ps
CPU time 0.89 seconds
Started Jul 27 07:41:32 PM PDT 24
Finished Jul 27 07:41:33 PM PDT 24
Peak memory 207144 kb
Host smart-185eed8b-7bf2-4c55-8d47-329ca1cf9769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23575
08310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2357508310
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.185061095
Short name T2459
Test name
Test status
Simulation time 263170224 ps
CPU time 0.99 seconds
Started Jul 27 07:41:36 PM PDT 24
Finished Jul 27 07:41:37 PM PDT 24
Peak memory 207136 kb
Host smart-74ab7f05-efcd-42cf-bcc7-b3d9048f5942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18506
1095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.185061095
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.3871279892
Short name T1965
Test name
Test status
Simulation time 203368757 ps
CPU time 0.93 seconds
Started Jul 27 07:41:33 PM PDT 24
Finished Jul 27 07:41:34 PM PDT 24
Peak memory 207100 kb
Host smart-b790655a-a1f3-4c1b-adfc-f0524e2aa7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38712
79892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.3871279892
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.1718417202
Short name T772
Test name
Test status
Simulation time 176613694 ps
CPU time 0.86 seconds
Started Jul 27 07:41:31 PM PDT 24
Finished Jul 27 07:41:32 PM PDT 24
Peak memory 207016 kb
Host smart-0f740a7b-1dff-4394-8aad-0ee4e68f6fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17184
17202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1718417202
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3920844068
Short name T488
Test name
Test status
Simulation time 169182774 ps
CPU time 0.87 seconds
Started Jul 27 07:41:36 PM PDT 24
Finished Jul 27 07:41:37 PM PDT 24
Peak memory 207212 kb
Host smart-eec69a24-68b5-4917-9244-ab7bf9ad8820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39208
44068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3920844068
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3006507059
Short name T2029
Test name
Test status
Simulation time 156017687 ps
CPU time 0.82 seconds
Started Jul 27 07:41:31 PM PDT 24
Finished Jul 27 07:41:32 PM PDT 24
Peak memory 207048 kb
Host smart-fceccc48-0294-41c5-a97a-9b1ce343bc80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30065
07059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3006507059
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.4022493650
Short name T2406
Test name
Test status
Simulation time 178058418 ps
CPU time 0.9 seconds
Started Jul 27 07:41:35 PM PDT 24
Finished Jul 27 07:41:36 PM PDT 24
Peak memory 207148 kb
Host smart-39ad1573-79ec-4854-a738-d9772fedf22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40224
93650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.4022493650
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.49393463
Short name T558
Test name
Test status
Simulation time 266659599 ps
CPU time 1.12 seconds
Started Jul 27 07:41:34 PM PDT 24
Finished Jul 27 07:41:35 PM PDT 24
Peak memory 207128 kb
Host smart-9688201d-c186-4cb9-b883-ca402f719a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49393
463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.49393463
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.1956264291
Short name T1839
Test name
Test status
Simulation time 3834457156 ps
CPU time 38.29 seconds
Started Jul 27 07:41:31 PM PDT 24
Finished Jul 27 07:42:09 PM PDT 24
Peak memory 215624 kb
Host smart-14f7104b-0424-4764-887b-868ae7c1a7e6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1956264291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.1956264291
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3068092937
Short name T2435
Test name
Test status
Simulation time 240718078 ps
CPU time 0.97 seconds
Started Jul 27 07:41:38 PM PDT 24
Finished Jul 27 07:41:39 PM PDT 24
Peak memory 207120 kb
Host smart-7ad31524-a05a-4a2d-853b-e84b2fc0a193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30680
92937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3068092937
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1688488758
Short name T780
Test name
Test status
Simulation time 166684917 ps
CPU time 0.86 seconds
Started Jul 27 07:41:32 PM PDT 24
Finished Jul 27 07:41:33 PM PDT 24
Peak memory 207100 kb
Host smart-2adf37b5-4384-4350-927b-e31e958d22f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16884
88758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1688488758
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.3800420873
Short name T1395
Test name
Test status
Simulation time 807267740 ps
CPU time 2.34 seconds
Started Jul 27 07:41:31 PM PDT 24
Finished Jul 27 07:41:33 PM PDT 24
Peak memory 207240 kb
Host smart-960e1ab1-dad4-4d44-aec2-f8a7a860807b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38004
20873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.3800420873
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.2700529306
Short name T1916
Test name
Test status
Simulation time 3669202727 ps
CPU time 105.03 seconds
Started Jul 27 07:41:38 PM PDT 24
Finished Jul 27 07:43:23 PM PDT 24
Peak memory 215496 kb
Host smart-eb295530-82da-49de-84fd-290f48b8d0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27005
29306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2700529306
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.657045519
Short name T1017
Test name
Test status
Simulation time 4361862518 ps
CPU time 29.65 seconds
Started Jul 27 07:41:22 PM PDT 24
Finished Jul 27 07:41:51 PM PDT 24
Peak memory 207320 kb
Host smart-b03c9d0c-6545-4e23-a99a-73bf3410e449
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657045519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_host
_handshake.657045519
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1904579135
Short name T194
Test name
Test status
Simulation time 43138804 ps
CPU time 0.69 seconds
Started Jul 27 07:41:53 PM PDT 24
Finished Jul 27 07:41:54 PM PDT 24
Peak memory 207152 kb
Host smart-51d751ca-a40a-49bf-8f31-84026dabfa2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1904579135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1904579135
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1271172874
Short name T722
Test name
Test status
Simulation time 3610286400 ps
CPU time 5.5 seconds
Started Jul 27 07:41:34 PM PDT 24
Finished Jul 27 07:41:40 PM PDT 24
Peak memory 207352 kb
Host smart-a738ac6f-d5ec-4c75-b46b-002c08b45b01
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271172874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.1271172874
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1579789321
Short name T2154
Test name
Test status
Simulation time 13356921730 ps
CPU time 15 seconds
Started Jul 27 07:41:33 PM PDT 24
Finished Jul 27 07:41:48 PM PDT 24
Peak memory 207412 kb
Host smart-62870266-ff11-41a1-b1c9-cd5bd750978a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579789321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1579789321
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.2490262423
Short name T2025
Test name
Test status
Simulation time 23287292900 ps
CPU time 28.22 seconds
Started Jul 27 07:41:36 PM PDT 24
Finished Jul 27 07:42:04 PM PDT 24
Peak memory 207360 kb
Host smart-32ce27ba-9b0b-420d-bd06-b7418d30ea6f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490262423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.2490262423
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3773571192
Short name T100
Test name
Test status
Simulation time 184554028 ps
CPU time 0.88 seconds
Started Jul 27 07:41:33 PM PDT 24
Finished Jul 27 07:41:34 PM PDT 24
Peak memory 206988 kb
Host smart-84c30554-053b-4c87-9d59-e96066287861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37735
71192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3773571192
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.2916801863
Short name T1150
Test name
Test status
Simulation time 144137217 ps
CPU time 0.82 seconds
Started Jul 27 07:41:33 PM PDT 24
Finished Jul 27 07:41:34 PM PDT 24
Peak memory 207072 kb
Host smart-f49204cc-faab-4119-817f-2960c00eb5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29168
01863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2916801863
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1928570333
Short name T716
Test name
Test status
Simulation time 196499453 ps
CPU time 1.01 seconds
Started Jul 27 07:41:37 PM PDT 24
Finished Jul 27 07:41:38 PM PDT 24
Peak memory 207104 kb
Host smart-abf30549-b870-4305-9677-80b5c3f61afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19285
70333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1928570333
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.438645327
Short name T1923
Test name
Test status
Simulation time 342158386 ps
CPU time 1.26 seconds
Started Jul 27 07:41:33 PM PDT 24
Finished Jul 27 07:41:34 PM PDT 24
Peak memory 207128 kb
Host smart-11f92abf-adb2-41f0-a613-d47b6b41e837
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=438645327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.438645327
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2938933212
Short name T1311
Test name
Test status
Simulation time 21330877646 ps
CPU time 45.37 seconds
Started Jul 27 07:41:33 PM PDT 24
Finished Jul 27 07:42:18 PM PDT 24
Peak memory 207268 kb
Host smart-6ce1fa52-7ffb-4553-a76d-f8f95f7964d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29389
33212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2938933212
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.2551567965
Short name T2224
Test name
Test status
Simulation time 2256311466 ps
CPU time 13.71 seconds
Started Jul 27 07:41:31 PM PDT 24
Finished Jul 27 07:41:45 PM PDT 24
Peak memory 207376 kb
Host smart-5c46b8d9-9278-40ed-a1b8-d7564eb393fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551567965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.2551567965
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.4170239893
Short name T2851
Test name
Test status
Simulation time 423071086 ps
CPU time 1.45 seconds
Started Jul 27 07:41:34 PM PDT 24
Finished Jul 27 07:41:36 PM PDT 24
Peak memory 207084 kb
Host smart-ba7e2dbb-d188-468f-84bf-a57ad87ad427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41702
39893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.4170239893
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2639913652
Short name T2664
Test name
Test status
Simulation time 167747811 ps
CPU time 0.78 seconds
Started Jul 27 07:41:38 PM PDT 24
Finished Jul 27 07:41:39 PM PDT 24
Peak memory 207080 kb
Host smart-9f1b6c2c-7ca3-4a7e-80f5-42a41fa42a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26399
13652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2639913652
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.1625241966
Short name T1660
Test name
Test status
Simulation time 74057040 ps
CPU time 0.74 seconds
Started Jul 27 07:41:36 PM PDT 24
Finished Jul 27 07:41:37 PM PDT 24
Peak memory 207072 kb
Host smart-cc1a87c8-06a5-40a3-82e8-3f0c86b4ecd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16252
41966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1625241966
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.181931175
Short name T2546
Test name
Test status
Simulation time 1026324732 ps
CPU time 2.62 seconds
Started Jul 27 07:41:38 PM PDT 24
Finished Jul 27 07:41:41 PM PDT 24
Peak memory 207336 kb
Host smart-b90a47cc-61a9-42f2-aaaa-77ef801e3652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18193
1175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.181931175
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3509452394
Short name T1981
Test name
Test status
Simulation time 309086970 ps
CPU time 2.09 seconds
Started Jul 27 07:41:33 PM PDT 24
Finished Jul 27 07:41:36 PM PDT 24
Peak memory 207348 kb
Host smart-fa235932-6832-4139-98ed-8e426e629700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35094
52394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3509452394
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1913213517
Short name T1477
Test name
Test status
Simulation time 183207002 ps
CPU time 0.98 seconds
Started Jul 27 07:41:38 PM PDT 24
Finished Jul 27 07:41:39 PM PDT 24
Peak memory 215476 kb
Host smart-4a78e25c-17c2-44a6-bfee-5851c4085b07
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1913213517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1913213517
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.408608339
Short name T2852
Test name
Test status
Simulation time 139602264 ps
CPU time 0.82 seconds
Started Jul 27 07:41:37 PM PDT 24
Finished Jul 27 07:41:38 PM PDT 24
Peak memory 207052 kb
Host smart-f1f3e10f-5638-4a43-b61e-a85d2c284d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40860
8339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.408608339
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3435962387
Short name T1568
Test name
Test status
Simulation time 214325259 ps
CPU time 0.96 seconds
Started Jul 27 07:41:37 PM PDT 24
Finished Jul 27 07:41:39 PM PDT 24
Peak memory 207104 kb
Host smart-ae918a1a-4af7-46d6-9a36-768d1a8d3c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34359
62387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3435962387
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.4153808260
Short name T84
Test name
Test status
Simulation time 6144516557 ps
CPU time 180.18 seconds
Started Jul 27 07:41:39 PM PDT 24
Finished Jul 27 07:44:40 PM PDT 24
Peak memory 215528 kb
Host smart-5fdd4afb-99cc-4bd9-a972-818de0355d5a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4153808260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.4153808260
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.628566430
Short name T2704
Test name
Test status
Simulation time 5508094947 ps
CPU time 38.06 seconds
Started Jul 27 07:41:41 PM PDT 24
Finished Jul 27 07:42:19 PM PDT 24
Peak memory 207340 kb
Host smart-41fd54c2-53be-460f-a765-6bf15a8ea58b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=628566430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.628566430
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.3249411309
Short name T2234
Test name
Test status
Simulation time 233786580 ps
CPU time 0.95 seconds
Started Jul 27 07:41:40 PM PDT 24
Finished Jul 27 07:41:41 PM PDT 24
Peak memory 207132 kb
Host smart-ac00e3ec-7fce-4bda-a983-7ac7c8eff26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32494
11309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.3249411309
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.713577320
Short name T1717
Test name
Test status
Simulation time 23314609388 ps
CPU time 27.35 seconds
Started Jul 27 07:41:39 PM PDT 24
Finished Jul 27 07:42:07 PM PDT 24
Peak memory 207316 kb
Host smart-27fd4275-d311-4610-a5d2-685af6fda688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71357
7320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.713577320
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.421357893
Short name T556
Test name
Test status
Simulation time 3315053195 ps
CPU time 5.43 seconds
Started Jul 27 07:41:37 PM PDT 24
Finished Jul 27 07:41:43 PM PDT 24
Peak memory 207360 kb
Host smart-e55a0901-1363-4d2a-b1c4-88e5dc9edf0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42135
7893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.421357893
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.3600372239
Short name T612
Test name
Test status
Simulation time 5295983440 ps
CPU time 40.18 seconds
Started Jul 27 07:41:38 PM PDT 24
Finished Jul 27 07:42:19 PM PDT 24
Peak memory 217528 kb
Host smart-46751893-91dc-4ea2-9a21-16afab5fbbb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36003
72239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.3600372239
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.2821296505
Short name T2216
Test name
Test status
Simulation time 6979785238 ps
CPU time 210.26 seconds
Started Jul 27 07:41:39 PM PDT 24
Finished Jul 27 07:45:09 PM PDT 24
Peak memory 215644 kb
Host smart-dd9ea770-07c0-4af5-8de7-0caebad9505e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2821296505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2821296505
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.3276170342
Short name T2570
Test name
Test status
Simulation time 249864611 ps
CPU time 0.97 seconds
Started Jul 27 07:41:42 PM PDT 24
Finished Jul 27 07:41:43 PM PDT 24
Peak memory 207024 kb
Host smart-c0d7d0ca-177f-404a-8d5f-7e8fde5b5776
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3276170342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.3276170342
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1950181325
Short name T429
Test name
Test status
Simulation time 191998089 ps
CPU time 0.9 seconds
Started Jul 27 07:41:37 PM PDT 24
Finished Jul 27 07:41:38 PM PDT 24
Peak memory 206564 kb
Host smart-b916ffc6-f593-4529-81ee-aec1bc41d544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19501
81325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1950181325
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.2465166053
Short name T2078
Test name
Test status
Simulation time 6015208021 ps
CPU time 60.14 seconds
Started Jul 27 07:41:40 PM PDT 24
Finished Jul 27 07:42:41 PM PDT 24
Peak memory 215596 kb
Host smart-f67ae88c-429d-4bbe-b027-079afe78a469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24651
66053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.2465166053
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.95240907
Short name T2093
Test name
Test status
Simulation time 3262737089 ps
CPU time 32.22 seconds
Started Jul 27 07:41:36 PM PDT 24
Finished Jul 27 07:42:09 PM PDT 24
Peak memory 215496 kb
Host smart-fe7268ba-fa3c-4f4c-b7d3-f14e7d4365ad
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=95240907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.95240907
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.463526586
Short name T2408
Test name
Test status
Simulation time 156939992 ps
CPU time 0.85 seconds
Started Jul 27 07:41:41 PM PDT 24
Finished Jul 27 07:41:42 PM PDT 24
Peak memory 207128 kb
Host smart-31969500-8c63-4562-a420-0d39baf93be1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=463526586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.463526586
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1583451529
Short name T2516
Test name
Test status
Simulation time 150429271 ps
CPU time 0.85 seconds
Started Jul 27 07:41:42 PM PDT 24
Finished Jul 27 07:41:43 PM PDT 24
Peak memory 207004 kb
Host smart-17cfa5dc-2514-47d9-a941-82844b90de00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15834
51529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1583451529
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3861085561
Short name T121
Test name
Test status
Simulation time 155091470 ps
CPU time 0.84 seconds
Started Jul 27 07:41:37 PM PDT 24
Finished Jul 27 07:41:38 PM PDT 24
Peak memory 207116 kb
Host smart-ebab1832-1062-4f51-b8b2-da483bbebbf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38610
85561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3861085561
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1657631997
Short name T1191
Test name
Test status
Simulation time 173236393 ps
CPU time 0.88 seconds
Started Jul 27 07:41:36 PM PDT 24
Finished Jul 27 07:41:37 PM PDT 24
Peak memory 207344 kb
Host smart-b0a0ee33-d039-4698-bd1c-62bd743ebc34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16576
31997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1657631997
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.4131819489
Short name T1833
Test name
Test status
Simulation time 166390571 ps
CPU time 0.85 seconds
Started Jul 27 07:41:39 PM PDT 24
Finished Jul 27 07:41:40 PM PDT 24
Peak memory 207084 kb
Host smart-b799f580-e55c-4f5f-9330-10502accc68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41318
19489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.4131819489
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.401156118
Short name T707
Test name
Test status
Simulation time 162105572 ps
CPU time 0.85 seconds
Started Jul 27 07:41:34 PM PDT 24
Finished Jul 27 07:41:35 PM PDT 24
Peak memory 207124 kb
Host smart-94055196-152d-492f-a21c-c3334efe020c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40115
6118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.401156118
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1498819877
Short name T2384
Test name
Test status
Simulation time 196396891 ps
CPU time 0.93 seconds
Started Jul 27 07:41:38 PM PDT 24
Finished Jul 27 07:41:39 PM PDT 24
Peak memory 207136 kb
Host smart-f5c13d9b-ef3c-41ea-9367-5bc106983af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14988
19877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1498819877
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3760682630
Short name T1114
Test name
Test status
Simulation time 220701823 ps
CPU time 0.98 seconds
Started Jul 27 07:41:38 PM PDT 24
Finished Jul 27 07:41:39 PM PDT 24
Peak memory 207088 kb
Host smart-ab91669e-af12-4efa-bad2-1679f44977c5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3760682630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3760682630
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2826035363
Short name T2574
Test name
Test status
Simulation time 143799785 ps
CPU time 0.89 seconds
Started Jul 27 07:41:39 PM PDT 24
Finished Jul 27 07:41:40 PM PDT 24
Peak memory 207068 kb
Host smart-e443fff6-f5dc-46f9-922a-026381fd0338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28260
35363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2826035363
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1580519314
Short name T1116
Test name
Test status
Simulation time 34859921 ps
CPU time 0.67 seconds
Started Jul 27 07:41:39 PM PDT 24
Finished Jul 27 07:41:40 PM PDT 24
Peak memory 207052 kb
Host smart-f2e56570-2cbd-4d79-86b9-7b3174144e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15805
19314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1580519314
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.495208635
Short name T2584
Test name
Test status
Simulation time 187755724 ps
CPU time 1 seconds
Started Jul 27 07:41:40 PM PDT 24
Finished Jul 27 07:41:41 PM PDT 24
Peak memory 207088 kb
Host smart-be63c252-6b5f-4118-9858-b2c9bc42fc1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49520
8635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.495208635
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1634008682
Short name T2291
Test name
Test status
Simulation time 206225919 ps
CPU time 0.96 seconds
Started Jul 27 07:41:39 PM PDT 24
Finished Jul 27 07:41:40 PM PDT 24
Peak memory 207032 kb
Host smart-28d10e47-f263-42c1-85dd-8325910d1595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16340
08682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1634008682
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.541436845
Short name T353
Test name
Test status
Simulation time 213341978 ps
CPU time 0.93 seconds
Started Jul 27 07:41:38 PM PDT 24
Finished Jul 27 07:41:39 PM PDT 24
Peak memory 207088 kb
Host smart-4bc79ebe-81fe-4e78-b3f6-009d0d969758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54143
6845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.541436845
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.3935408667
Short name T1734
Test name
Test status
Simulation time 189753164 ps
CPU time 0.99 seconds
Started Jul 27 07:41:38 PM PDT 24
Finished Jul 27 07:41:39 PM PDT 24
Peak memory 207072 kb
Host smart-22660cd8-e867-4490-a7e8-2833faf5c440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39354
08667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.3935408667
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.4021376921
Short name T78
Test name
Test status
Simulation time 150537462 ps
CPU time 0.83 seconds
Started Jul 27 07:41:39 PM PDT 24
Finished Jul 27 07:41:40 PM PDT 24
Peak memory 207056 kb
Host smart-cc947d37-ce72-4569-8f86-276f1c4ff41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40213
76921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.4021376921
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.4290911638
Short name T1922
Test name
Test status
Simulation time 160281635 ps
CPU time 0.88 seconds
Started Jul 27 07:41:42 PM PDT 24
Finished Jul 27 07:41:43 PM PDT 24
Peak memory 206980 kb
Host smart-e4d9e8fb-aa97-403c-9dfb-98292ca13f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42909
11638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.4290911638
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1355426888
Short name T2421
Test name
Test status
Simulation time 167200535 ps
CPU time 0.88 seconds
Started Jul 27 07:41:46 PM PDT 24
Finished Jul 27 07:41:47 PM PDT 24
Peak memory 207068 kb
Host smart-e01b6cdc-2d34-4610-af27-943bbc2d1aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13554
26888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1355426888
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.324290354
Short name T1085
Test name
Test status
Simulation time 211148331 ps
CPU time 1.05 seconds
Started Jul 27 07:41:44 PM PDT 24
Finished Jul 27 07:41:46 PM PDT 24
Peak memory 207108 kb
Host smart-f0b7e4fe-90cb-4120-9894-106136b55813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32429
0354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.324290354
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.2044669498
Short name T2654
Test name
Test status
Simulation time 6233115456 ps
CPU time 64.06 seconds
Started Jul 27 07:41:46 PM PDT 24
Finished Jul 27 07:42:50 PM PDT 24
Peak memory 215532 kb
Host smart-dd29b5ff-f44e-4eb1-8a11-9414f1712273
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2044669498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.2044669498
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.4993932
Short name T2148
Test name
Test status
Simulation time 180226744 ps
CPU time 0.9 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:41:55 PM PDT 24
Peak memory 207160 kb
Host smart-634ac4f8-41b2-48e6-a456-0e0b1826d48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49939
32 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.4993932
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2080647340
Short name T826
Test name
Test status
Simulation time 166765453 ps
CPU time 0.85 seconds
Started Jul 27 07:41:45 PM PDT 24
Finished Jul 27 07:41:46 PM PDT 24
Peak memory 207136 kb
Host smart-e375c59c-0889-43be-a2f1-1a7d262afd60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20806
47340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2080647340
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.4255554766
Short name T1337
Test name
Test status
Simulation time 1000613170 ps
CPU time 2.34 seconds
Started Jul 27 07:41:48 PM PDT 24
Finished Jul 27 07:41:50 PM PDT 24
Peak memory 207240 kb
Host smart-05d61eb4-9a9a-4dd2-a138-ea151ca5be27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42555
54766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.4255554766
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.484389668
Short name T423
Test name
Test status
Simulation time 6136325450 ps
CPU time 179.72 seconds
Started Jul 27 07:41:44 PM PDT 24
Finished Jul 27 07:44:44 PM PDT 24
Peak memory 215580 kb
Host smart-3aad9f9d-135e-4665-857b-e2ef33fbe747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48438
9668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.484389668
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.825577905
Short name T891
Test name
Test status
Simulation time 1134157841 ps
CPU time 25.41 seconds
Started Jul 27 07:41:30 PM PDT 24
Finished Jul 27 07:41:55 PM PDT 24
Peak memory 207252 kb
Host smart-5c17d1c3-51fd-419d-acb0-3e9f7d1cb256
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825577905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_host
_handshake.825577905
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.3442038992
Short name T1540
Test name
Test status
Simulation time 81710389 ps
CPU time 0.75 seconds
Started Jul 27 07:34:47 PM PDT 24
Finished Jul 27 07:34:48 PM PDT 24
Peak memory 207180 kb
Host smart-91de37a2-7d64-48ae-9c27-3b95661dbcec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3442038992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3442038992
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.974465041
Short name T815
Test name
Test status
Simulation time 3955307795 ps
CPU time 6.65 seconds
Started Jul 27 07:34:31 PM PDT 24
Finished Jul 27 07:34:38 PM PDT 24
Peak memory 207344 kb
Host smart-b28f8cca-3d13-487a-83fe-97d7fa6a43ab
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974465041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon
_wake_disconnect.974465041
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.3375490902
Short name T1379
Test name
Test status
Simulation time 13384653998 ps
CPU time 15.44 seconds
Started Jul 27 07:34:32 PM PDT 24
Finished Jul 27 07:34:47 PM PDT 24
Peak memory 207420 kb
Host smart-ad0ead78-f530-403d-92fb-30ef870974e4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375490902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.3375490902
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3089646769
Short name T633
Test name
Test status
Simulation time 23391039621 ps
CPU time 32.86 seconds
Started Jul 27 07:34:31 PM PDT 24
Finished Jul 27 07:35:04 PM PDT 24
Peak memory 207368 kb
Host smart-de60554e-c060-4ff2-ba2e-028fed6b6be2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089646769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.3089646769
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1334548584
Short name T2487
Test name
Test status
Simulation time 174932566 ps
CPU time 0.87 seconds
Started Jul 27 07:34:32 PM PDT 24
Finished Jul 27 07:34:33 PM PDT 24
Peak memory 207144 kb
Host smart-ad607978-2654-4d38-9568-b0480efe914f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13345
48584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1334548584
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.2461118248
Short name T43
Test name
Test status
Simulation time 156813678 ps
CPU time 0.84 seconds
Started Jul 27 07:34:31 PM PDT 24
Finished Jul 27 07:34:32 PM PDT 24
Peak memory 207088 kb
Host smart-43cb1da9-51ca-4a5c-a919-dfd7fe19135a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24611
18248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.2461118248
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2585643913
Short name T57
Test name
Test status
Simulation time 138053083 ps
CPU time 0.81 seconds
Started Jul 27 07:34:30 PM PDT 24
Finished Jul 27 07:34:30 PM PDT 24
Peak memory 207036 kb
Host smart-db29b7ac-7fbe-4e7a-a68b-94b538bfceb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25856
43913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2585643913
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.1655848970
Short name T986
Test name
Test status
Simulation time 161253773 ps
CPU time 0.83 seconds
Started Jul 27 07:34:31 PM PDT 24
Finished Jul 27 07:34:32 PM PDT 24
Peak memory 207108 kb
Host smart-3655e4c5-ad1d-4105-883c-0e9af60ee51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16558
48970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.1655848970
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2480628859
Short name T2481
Test name
Test status
Simulation time 257458547 ps
CPU time 1.13 seconds
Started Jul 27 07:34:34 PM PDT 24
Finished Jul 27 07:34:35 PM PDT 24
Peak memory 207108 kb
Host smart-797e9e50-6d1b-4922-8657-c67ef65e1724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24806
28859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2480628859
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.188084717
Short name T2595
Test name
Test status
Simulation time 1478077391 ps
CPU time 3.36 seconds
Started Jul 27 07:34:34 PM PDT 24
Finished Jul 27 07:34:37 PM PDT 24
Peak memory 207336 kb
Host smart-12e4d332-0826-4b40-9fc8-0bb4dcc627a3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=188084717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.188084717
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.3329519053
Short name T190
Test name
Test status
Simulation time 22215133115 ps
CPU time 42.94 seconds
Started Jul 27 07:34:31 PM PDT 24
Finished Jul 27 07:35:14 PM PDT 24
Peak memory 207280 kb
Host smart-28c2f920-1b87-4ab9-970a-3e24cd8f301c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33295
19053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3329519053
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.515635002
Short name T2521
Test name
Test status
Simulation time 622812068 ps
CPU time 11.53 seconds
Started Jul 27 07:34:34 PM PDT 24
Finished Jul 27 07:34:46 PM PDT 24
Peak memory 207224 kb
Host smart-dc4d5732-555d-4feb-ace9-7b32b22be36e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515635002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.515635002
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.3209545740
Short name T1518
Test name
Test status
Simulation time 354829042 ps
CPU time 1.29 seconds
Started Jul 27 07:34:33 PM PDT 24
Finished Jul 27 07:34:35 PM PDT 24
Peak memory 207036 kb
Host smart-0c2e34ef-6abb-463b-994e-bde61420f462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32095
45740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.3209545740
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.845331503
Short name T751
Test name
Test status
Simulation time 158782281 ps
CPU time 0.84 seconds
Started Jul 27 07:34:46 PM PDT 24
Finished Jul 27 07:34:47 PM PDT 24
Peak memory 207092 kb
Host smart-f32edbc5-af1e-4d4c-8535-d578b48b5c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84533
1503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.845331503
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.78781857
Short name T404
Test name
Test status
Simulation time 33108729 ps
CPU time 0.68 seconds
Started Jul 27 07:34:33 PM PDT 24
Finished Jul 27 07:34:34 PM PDT 24
Peak memory 207032 kb
Host smart-972cf70f-7b86-4c4a-b681-02c567a9a406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78781
857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.78781857
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.578669914
Short name T1351
Test name
Test status
Simulation time 945808046 ps
CPU time 2.61 seconds
Started Jul 27 07:34:33 PM PDT 24
Finished Jul 27 07:34:36 PM PDT 24
Peak memory 207296 kb
Host smart-88f3855e-e8a3-4abd-aa8b-3d7c23d1220e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57866
9914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.578669914
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.781028781
Short name T1225
Test name
Test status
Simulation time 188555530 ps
CPU time 2.06 seconds
Started Jul 27 07:34:32 PM PDT 24
Finished Jul 27 07:34:34 PM PDT 24
Peak memory 207352 kb
Host smart-eebae73c-c717-4b27-a591-cf10fba5deca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78102
8781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.781028781
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.3075864535
Short name T1300
Test name
Test status
Simulation time 93180585589 ps
CPU time 141.84 seconds
Started Jul 27 07:34:34 PM PDT 24
Finished Jul 27 07:36:56 PM PDT 24
Peak memory 207284 kb
Host smart-60fdd1aa-7b46-4148-87d9-2ca99b069e1f
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3075864535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.3075864535
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.1301173334
Short name T302
Test name
Test status
Simulation time 86314498229 ps
CPU time 137.15 seconds
Started Jul 27 07:34:34 PM PDT 24
Finished Jul 27 07:36:51 PM PDT 24
Peak memory 207568 kb
Host smart-630b5da2-15df-406f-96d9-794d07bf5fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301173334 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.1301173334
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.4180560939
Short name T2366
Test name
Test status
Simulation time 117140018617 ps
CPU time 203.71 seconds
Started Jul 27 07:34:34 PM PDT 24
Finished Jul 27 07:37:58 PM PDT 24
Peak memory 207560 kb
Host smart-fc89b114-02ba-4be1-89d4-4874540e62e7
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4180560939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.4180560939
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.3231151565
Short name T491
Test name
Test status
Simulation time 88166709099 ps
CPU time 145.27 seconds
Started Jul 27 07:34:35 PM PDT 24
Finished Jul 27 07:37:01 PM PDT 24
Peak memory 207368 kb
Host smart-3f46353d-b05b-4ce1-bfde-a4d5e2e9a6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231151565 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.3231151565
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.4088028593
Short name T301
Test name
Test status
Simulation time 85150573919 ps
CPU time 135.63 seconds
Started Jul 27 07:34:47 PM PDT 24
Finished Jul 27 07:37:03 PM PDT 24
Peak memory 207392 kb
Host smart-bddb132e-811d-45a3-92ad-159f6c3dc00c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40880
28593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.4088028593
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1628588834
Short name T960
Test name
Test status
Simulation time 227227166 ps
CPU time 1.18 seconds
Started Jul 27 07:34:32 PM PDT 24
Finished Jul 27 07:34:33 PM PDT 24
Peak memory 207284 kb
Host smart-8dfc3c61-ded0-4ec5-804c-adc2b055591c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1628588834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1628588834
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.926961392
Short name T1856
Test name
Test status
Simulation time 143305222 ps
CPU time 0.86 seconds
Started Jul 27 07:34:38 PM PDT 24
Finished Jul 27 07:34:39 PM PDT 24
Peak memory 207112 kb
Host smart-65bdc398-7e7f-4a16-bfd3-0f21719b0eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92696
1392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.926961392
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1212776273
Short name T2189
Test name
Test status
Simulation time 190732167 ps
CPU time 0.96 seconds
Started Jul 27 07:34:35 PM PDT 24
Finished Jul 27 07:34:36 PM PDT 24
Peak memory 207016 kb
Host smart-ef83a0c0-9d8c-41ce-bec1-cc14995adf4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12127
76273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1212776273
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.565247285
Short name T2100
Test name
Test status
Simulation time 5980035117 ps
CPU time 57.99 seconds
Started Jul 27 07:34:34 PM PDT 24
Finished Jul 27 07:35:32 PM PDT 24
Peak memory 215572 kb
Host smart-6b854c1d-8202-4f6e-9635-0e7bf307a609
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=565247285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.565247285
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.3156745277
Short name T2583
Test name
Test status
Simulation time 4572847827 ps
CPU time 29.26 seconds
Started Jul 27 07:34:38 PM PDT 24
Finished Jul 27 07:35:08 PM PDT 24
Peak memory 207360 kb
Host smart-abc08aed-a3cf-4c3c-ba5c-470935f1e143
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3156745277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.3156745277
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.849626822
Short name T1996
Test name
Test status
Simulation time 253473985 ps
CPU time 1 seconds
Started Jul 27 07:34:35 PM PDT 24
Finished Jul 27 07:34:36 PM PDT 24
Peak memory 207128 kb
Host smart-d06f2870-4f6d-48b5-969e-85257cc7b82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84962
6822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.849626822
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.3935654497
Short name T1845
Test name
Test status
Simulation time 23333421704 ps
CPU time 30.76 seconds
Started Jul 27 07:34:36 PM PDT 24
Finished Jul 27 07:35:07 PM PDT 24
Peak memory 207412 kb
Host smart-d46c5eb2-ff8d-423d-b6cc-617a4f149b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39356
54497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.3935654497
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.1692708393
Short name T1995
Test name
Test status
Simulation time 3340577333 ps
CPU time 5.03 seconds
Started Jul 27 07:34:40 PM PDT 24
Finished Jul 27 07:34:45 PM PDT 24
Peak memory 207352 kb
Host smart-8be5eee7-6076-4dc0-bce9-c591c6e324a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16927
08393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1692708393
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3926155694
Short name T919
Test name
Test status
Simulation time 6286462834 ps
CPU time 61.38 seconds
Started Jul 27 07:34:46 PM PDT 24
Finished Jul 27 07:35:47 PM PDT 24
Peak memory 217380 kb
Host smart-af9b1f66-3153-4ccb-b8dd-c16ee5c8481a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39261
55694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3926155694
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2581570090
Short name T1257
Test name
Test status
Simulation time 4368698315 ps
CPU time 129.67 seconds
Started Jul 27 07:34:46 PM PDT 24
Finished Jul 27 07:36:56 PM PDT 24
Peak memory 215576 kb
Host smart-497fac18-db1a-449c-9f35-e5f00dd50e33
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2581570090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2581570090
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.2955415139
Short name T1483
Test name
Test status
Simulation time 257460446 ps
CPU time 1.03 seconds
Started Jul 27 07:34:46 PM PDT 24
Finished Jul 27 07:34:47 PM PDT 24
Peak memory 207136 kb
Host smart-998ad1da-e8b5-4b0f-8186-12f8a906b673
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2955415139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.2955415139
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.4045304775
Short name T276
Test name
Test status
Simulation time 185424451 ps
CPU time 0.92 seconds
Started Jul 27 07:34:39 PM PDT 24
Finished Jul 27 07:34:40 PM PDT 24
Peak memory 207164 kb
Host smart-79f697ac-bae6-47b9-af90-784083f7f4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40453
04775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.4045304775
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2473625440
Short name T485
Test name
Test status
Simulation time 4186922252 ps
CPU time 43.15 seconds
Started Jul 27 07:34:43 PM PDT 24
Finished Jul 27 07:35:27 PM PDT 24
Peak memory 217212 kb
Host smart-94b40ff6-783a-48c9-ab9d-3b4ffb3bc7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24736
25440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2473625440
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.1920668084
Short name T2828
Test name
Test status
Simulation time 6952310934 ps
CPU time 212.09 seconds
Started Jul 27 07:34:47 PM PDT 24
Finished Jul 27 07:38:19 PM PDT 24
Peak memory 215544 kb
Host smart-a4c07061-02e1-40e6-b3ac-8819aea29ea2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1920668084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.1920668084
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.2249794855
Short name T329
Test name
Test status
Simulation time 164989942 ps
CPU time 0.86 seconds
Started Jul 27 07:34:39 PM PDT 24
Finished Jul 27 07:34:40 PM PDT 24
Peak memory 207076 kb
Host smart-a23570ce-961d-4363-9223-25d0b107877d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2249794855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.2249794855
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3999865278
Short name T2362
Test name
Test status
Simulation time 161448825 ps
CPU time 0.87 seconds
Started Jul 27 07:34:39 PM PDT 24
Finished Jul 27 07:34:40 PM PDT 24
Peak memory 207104 kb
Host smart-c4edb07d-13cf-42ca-aae6-3ee822fbf891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39998
65278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3999865278
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.332172419
Short name T137
Test name
Test status
Simulation time 205344872 ps
CPU time 0.92 seconds
Started Jul 27 07:34:39 PM PDT 24
Finished Jul 27 07:34:40 PM PDT 24
Peak memory 207136 kb
Host smart-18db4fd0-38f4-497e-afa8-e4e60cea90a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33217
2419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.332172419
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.253697135
Short name T2231
Test name
Test status
Simulation time 141473219 ps
CPU time 0.81 seconds
Started Jul 27 07:34:38 PM PDT 24
Finished Jul 27 07:34:39 PM PDT 24
Peak memory 207092 kb
Host smart-cef367f9-2894-4a20-b387-239019f738b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25369
7135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.253697135
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.658563029
Short name T1647
Test name
Test status
Simulation time 182843156 ps
CPU time 0.87 seconds
Started Jul 27 07:34:41 PM PDT 24
Finished Jul 27 07:34:42 PM PDT 24
Peak memory 207128 kb
Host smart-08bd79e5-75fa-4332-a237-df841ebb3e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65856
3029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.658563029
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2537180402
Short name T22
Test name
Test status
Simulation time 150018590 ps
CPU time 0.88 seconds
Started Jul 27 07:34:42 PM PDT 24
Finished Jul 27 07:34:43 PM PDT 24
Peak memory 207164 kb
Host smart-21ff21d8-69f1-4f32-a1d0-0103c6ba1938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25371
80402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2537180402
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2535281622
Short name T2188
Test name
Test status
Simulation time 158786999 ps
CPU time 0.93 seconds
Started Jul 27 07:34:40 PM PDT 24
Finished Jul 27 07:34:41 PM PDT 24
Peak memory 207200 kb
Host smart-8b38ef10-e629-438a-ae62-29b25bbb8054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25352
81622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2535281622
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.4235901005
Short name T1041
Test name
Test status
Simulation time 228393226 ps
CPU time 0.99 seconds
Started Jul 27 07:34:46 PM PDT 24
Finished Jul 27 07:34:47 PM PDT 24
Peak memory 207132 kb
Host smart-5787e474-1cea-4023-81e9-b8979d14020b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4235901005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.4235901005
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2837476321
Short name T668
Test name
Test status
Simulation time 239275799 ps
CPU time 1.03 seconds
Started Jul 27 07:34:42 PM PDT 24
Finished Jul 27 07:34:44 PM PDT 24
Peak memory 207220 kb
Host smart-18fa11bb-33bf-4400-9d78-7e5140efcef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28374
76321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2837476321
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2195111385
Short name T440
Test name
Test status
Simulation time 185581128 ps
CPU time 0.85 seconds
Started Jul 27 07:34:40 PM PDT 24
Finished Jul 27 07:34:41 PM PDT 24
Peak memory 207104 kb
Host smart-ae6b689e-129a-404a-883e-f96e03a66f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21951
11385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2195111385
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.90554892
Short name T2004
Test name
Test status
Simulation time 58963336 ps
CPU time 0.7 seconds
Started Jul 27 07:34:50 PM PDT 24
Finished Jul 27 07:34:51 PM PDT 24
Peak memory 207064 kb
Host smart-12e8346b-c259-4415-ab43-7ea3efb88f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90554
892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.90554892
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.644199503
Short name T258
Test name
Test status
Simulation time 8976354190 ps
CPU time 21.9 seconds
Started Jul 27 07:34:40 PM PDT 24
Finished Jul 27 07:35:02 PM PDT 24
Peak memory 220316 kb
Host smart-1ffcb505-0aac-46c1-8b89-a42e2c397a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64419
9503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.644199503
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3422239189
Short name T2549
Test name
Test status
Simulation time 187837087 ps
CPU time 0.87 seconds
Started Jul 27 07:34:40 PM PDT 24
Finished Jul 27 07:34:41 PM PDT 24
Peak memory 207140 kb
Host smart-300da335-d8a1-4929-9ed4-1e6a3cdfdaf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34222
39189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3422239189
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2932368393
Short name T1306
Test name
Test status
Simulation time 246854592 ps
CPU time 1.08 seconds
Started Jul 27 07:34:42 PM PDT 24
Finished Jul 27 07:34:44 PM PDT 24
Peak memory 207132 kb
Host smart-9e59d035-08f8-42a2-907d-250025c3794b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29323
68393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2932368393
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2156136623
Short name T2841
Test name
Test status
Simulation time 13786684744 ps
CPU time 385.35 seconds
Started Jul 27 07:34:49 PM PDT 24
Finished Jul 27 07:41:15 PM PDT 24
Peak memory 215512 kb
Host smart-535cd1a7-f6bd-4076-a698-2dc2b06947fd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2156136623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2156136623
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.989905251
Short name T1555
Test name
Test status
Simulation time 17634267310 ps
CPU time 407.86 seconds
Started Jul 27 07:34:48 PM PDT 24
Finished Jul 27 07:41:36 PM PDT 24
Peak memory 215588 kb
Host smart-60a17804-c609-4a7b-9a37-49d20109901c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=989905251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.989905251
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1683376101
Short name T330
Test name
Test status
Simulation time 237211286 ps
CPU time 1.01 seconds
Started Jul 27 07:34:49 PM PDT 24
Finished Jul 27 07:34:50 PM PDT 24
Peak memory 207124 kb
Host smart-6bf162da-d8b9-4011-92a0-ec3a89787a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16833
76101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1683376101
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1169921158
Short name T2129
Test name
Test status
Simulation time 234947361 ps
CPU time 0.94 seconds
Started Jul 27 07:34:49 PM PDT 24
Finished Jul 27 07:34:50 PM PDT 24
Peak memory 207096 kb
Host smart-5ab46f49-dcc2-43a2-989f-e21031439030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11699
21158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1169921158
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.792382876
Short name T801
Test name
Test status
Simulation time 136427286 ps
CPU time 0.8 seconds
Started Jul 27 07:34:48 PM PDT 24
Finished Jul 27 07:34:49 PM PDT 24
Peak memory 207000 kb
Host smart-304afb10-4ad5-4cec-9715-d69d3826128d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79238
2876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.792382876
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.1765465400
Short name T71
Test name
Test status
Simulation time 151426215 ps
CPU time 0.84 seconds
Started Jul 27 07:34:48 PM PDT 24
Finished Jul 27 07:34:49 PM PDT 24
Peak memory 207116 kb
Host smart-cbcb527c-273b-46c6-b6a9-285dc9ccf723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17654
65400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.1765465400
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2120308736
Short name T218
Test name
Test status
Simulation time 1012922188 ps
CPU time 1.76 seconds
Started Jul 27 07:34:49 PM PDT 24
Finished Jul 27 07:34:51 PM PDT 24
Peak memory 223920 kb
Host smart-4008e063-8225-4804-89d5-f4498feca253
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2120308736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2120308736
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.2077562642
Short name T49
Test name
Test status
Simulation time 383636750 ps
CPU time 1.48 seconds
Started Jul 27 07:34:47 PM PDT 24
Finished Jul 27 07:34:49 PM PDT 24
Peak memory 207080 kb
Host smart-7e317978-e108-47ee-a458-a12c953ac89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20775
62642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.2077562642
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.2192210772
Short name T2033
Test name
Test status
Simulation time 205736778 ps
CPU time 0.96 seconds
Started Jul 27 07:34:47 PM PDT 24
Finished Jul 27 07:34:48 PM PDT 24
Peak memory 207128 kb
Host smart-4d1b94aa-0bc1-436c-9aca-c932e7de6c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21922
10772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.2192210772
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.136383863
Short name T835
Test name
Test status
Simulation time 155981166 ps
CPU time 0.86 seconds
Started Jul 27 07:34:45 PM PDT 24
Finished Jul 27 07:34:46 PM PDT 24
Peak memory 207068 kb
Host smart-b416491e-e5bf-41b5-9769-166eb6afbfed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13638
3863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.136383863
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3613157914
Short name T2416
Test name
Test status
Simulation time 157310754 ps
CPU time 0.86 seconds
Started Jul 27 07:34:46 PM PDT 24
Finished Jul 27 07:34:47 PM PDT 24
Peak memory 207072 kb
Host smart-8c54b236-9f10-46f5-bc5b-57e6ce10d6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36131
57914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3613157914
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.4164465852
Short name T829
Test name
Test status
Simulation time 226474824 ps
CPU time 1.08 seconds
Started Jul 27 07:34:49 PM PDT 24
Finished Jul 27 07:34:51 PM PDT 24
Peak memory 207140 kb
Host smart-5f61a486-3745-4f1a-be11-7718eb6d4e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41644
65852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.4164465852
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1083419183
Short name T1323
Test name
Test status
Simulation time 4978825609 ps
CPU time 36.36 seconds
Started Jul 27 07:34:48 PM PDT 24
Finished Jul 27 07:35:24 PM PDT 24
Peak memory 216932 kb
Host smart-4b963281-a036-4e64-83bc-a87dce7320fc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1083419183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1083419183
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.4062964999
Short name T1138
Test name
Test status
Simulation time 167670789 ps
CPU time 0.96 seconds
Started Jul 27 07:34:49 PM PDT 24
Finished Jul 27 07:34:50 PM PDT 24
Peak memory 207124 kb
Host smart-145c23b9-ad1f-471e-bc4f-25eac844d73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40629
64999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.4062964999
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2363209280
Short name T2763
Test name
Test status
Simulation time 184369516 ps
CPU time 0.91 seconds
Started Jul 27 07:34:45 PM PDT 24
Finished Jul 27 07:34:46 PM PDT 24
Peak memory 207088 kb
Host smart-a50be162-b6d4-41f5-a8db-9059c7ac85c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23632
09280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2363209280
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.3734681322
Short name T1786
Test name
Test status
Simulation time 263115987 ps
CPU time 1.12 seconds
Started Jul 27 07:34:49 PM PDT 24
Finished Jul 27 07:34:50 PM PDT 24
Peak memory 207096 kb
Host smart-13c5907c-094f-4c90-b97f-099d64e0ad29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37346
81322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.3734681322
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.3387260526
Short name T1317
Test name
Test status
Simulation time 5358336595 ps
CPU time 39.01 seconds
Started Jul 27 07:34:50 PM PDT 24
Finished Jul 27 07:35:29 PM PDT 24
Peak memory 217044 kb
Host smart-8ec99e1e-1f37-4dde-804d-645b3e692fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33872
60526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.3387260526
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.633114250
Short name T69
Test name
Test status
Simulation time 15145487280 ps
CPU time 153.38 seconds
Started Jul 27 07:34:49 PM PDT 24
Finished Jul 27 07:37:22 PM PDT 24
Peak memory 217396 kb
Host smart-added6a9-bb36-4653-8469-231427cabc6d
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633114250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.633114250
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.3072213416
Short name T1976
Test name
Test status
Simulation time 1163797116 ps
CPU time 9.4 seconds
Started Jul 27 07:34:33 PM PDT 24
Finished Jul 27 07:34:43 PM PDT 24
Peak memory 207368 kb
Host smart-321c782b-4b5b-4928-ae28-1969e7bebcf1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072213416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.3072213416
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.2689388280
Short name T2608
Test name
Test status
Simulation time 46870661 ps
CPU time 0.69 seconds
Started Jul 27 07:41:58 PM PDT 24
Finished Jul 27 07:41:59 PM PDT 24
Peak memory 207096 kb
Host smart-f8bb39e2-754b-4034-b2c6-5f214ac569d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2689388280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.2689388280
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.4106481422
Short name T1048
Test name
Test status
Simulation time 4220196693 ps
CPU time 5.96 seconds
Started Jul 27 07:41:44 PM PDT 24
Finished Jul 27 07:41:51 PM PDT 24
Peak memory 207360 kb
Host smart-132c93ff-08d6-4d67-bf95-b21972bb0fcd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106481422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.4106481422
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2887584509
Short name T15
Test name
Test status
Simulation time 13411964568 ps
CPU time 14.49 seconds
Started Jul 27 07:41:44 PM PDT 24
Finished Jul 27 07:41:59 PM PDT 24
Peak memory 207408 kb
Host smart-8e093d69-39d1-4f08-b06b-963eb552a144
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887584509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2887584509
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3328091735
Short name T2626
Test name
Test status
Simulation time 23383316260 ps
CPU time 29.99 seconds
Started Jul 27 07:41:48 PM PDT 24
Finished Jul 27 07:42:18 PM PDT 24
Peak memory 207324 kb
Host smart-2354e49a-a7f3-47d1-a0a8-7dea8d6bb69d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328091735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.3328091735
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.239429284
Short name T1071
Test name
Test status
Simulation time 195739504 ps
CPU time 0.89 seconds
Started Jul 27 07:41:44 PM PDT 24
Finished Jul 27 07:41:45 PM PDT 24
Peak memory 206992 kb
Host smart-c7c61643-4263-47c8-aace-1079f2d6c83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23942
9284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.239429284
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.4144844530
Short name T1817
Test name
Test status
Simulation time 184253367 ps
CPU time 0.91 seconds
Started Jul 27 07:41:44 PM PDT 24
Finished Jul 27 07:41:46 PM PDT 24
Peak memory 207040 kb
Host smart-3f12bd28-b7f6-4591-8014-d677fe5fb91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41448
44530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.4144844530
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2257857779
Short name T1773
Test name
Test status
Simulation time 293055763 ps
CPU time 1.16 seconds
Started Jul 27 07:41:45 PM PDT 24
Finished Jul 27 07:41:46 PM PDT 24
Peak memory 207148 kb
Host smart-4d9ae73d-f1b4-4988-8196-17208eec7098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22578
57779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2257857779
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.3090711883
Short name T2625
Test name
Test status
Simulation time 902687840 ps
CPU time 2.44 seconds
Started Jul 27 07:41:44 PM PDT 24
Finished Jul 27 07:41:46 PM PDT 24
Peak memory 207312 kb
Host smart-8e34f3be-d745-4e02-970b-ebdc29310333
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3090711883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.3090711883
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1496543482
Short name T911
Test name
Test status
Simulation time 11578982674 ps
CPU time 25.29 seconds
Started Jul 27 07:41:45 PM PDT 24
Finished Jul 27 07:42:11 PM PDT 24
Peak memory 207352 kb
Host smart-f0da7f3b-dc17-4edc-99b7-78fb278b5de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14965
43482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1496543482
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.2570047524
Short name T449
Test name
Test status
Simulation time 5711002732 ps
CPU time 36.82 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:42:31 PM PDT 24
Peak memory 207020 kb
Host smart-c74b543a-2c6f-4e73-a233-0747485fd164
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570047524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.2570047524
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2407188074
Short name T1800
Test name
Test status
Simulation time 387454052 ps
CPU time 1.33 seconds
Started Jul 27 07:41:45 PM PDT 24
Finished Jul 27 07:41:46 PM PDT 24
Peak memory 207100 kb
Host smart-ea64be73-e6b2-4347-8801-df07f21f9ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24071
88074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2407188074
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2371562988
Short name T2222
Test name
Test status
Simulation time 208040084 ps
CPU time 0.9 seconds
Started Jul 27 07:41:45 PM PDT 24
Finished Jul 27 07:41:46 PM PDT 24
Peak memory 207076 kb
Host smart-f8d90a92-1fe2-4683-85d0-195675fd5b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23715
62988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2371562988
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.1724844469
Short name T655
Test name
Test status
Simulation time 91477555 ps
CPU time 0.74 seconds
Started Jul 27 07:41:45 PM PDT 24
Finished Jul 27 07:41:46 PM PDT 24
Peak memory 207156 kb
Host smart-cbd78930-ca0b-428f-abbb-44cb09ea4feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
44469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1724844469
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.1899965635
Short name T1384
Test name
Test status
Simulation time 986785574 ps
CPU time 2.47 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:41:57 PM PDT 24
Peak memory 206912 kb
Host smart-8ef9aa6f-955a-4b82-8797-04cf9012be50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18999
65635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.1899965635
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2389427640
Short name T2413
Test name
Test status
Simulation time 314340982 ps
CPU time 2.73 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:41:57 PM PDT 24
Peak memory 207248 kb
Host smart-c469e863-55e0-4c57-aac6-e9f09a5304dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23894
27640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2389427640
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.679493176
Short name T862
Test name
Test status
Simulation time 255173440 ps
CPU time 1.21 seconds
Started Jul 27 07:41:45 PM PDT 24
Finished Jul 27 07:41:46 PM PDT 24
Peak memory 215528 kb
Host smart-0c2bdd0f-00c8-4eda-bedb-1ef0f0aff622
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=679493176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.679493176
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.4231104381
Short name T1053
Test name
Test status
Simulation time 151291300 ps
CPU time 0.83 seconds
Started Jul 27 07:41:46 PM PDT 24
Finished Jul 27 07:41:47 PM PDT 24
Peak memory 207100 kb
Host smart-e7189cc0-4105-4755-a203-230fb4cd5acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42311
04381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.4231104381
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3062094932
Short name T417
Test name
Test status
Simulation time 232991432 ps
CPU time 1.03 seconds
Started Jul 27 07:41:45 PM PDT 24
Finished Jul 27 07:41:47 PM PDT 24
Peak memory 207100 kb
Host smart-74318313-efff-4de2-a8eb-1a8add28f034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30620
94932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3062094932
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.1207134745
Short name T1831
Test name
Test status
Simulation time 8055938125 ps
CPU time 225.4 seconds
Started Jul 27 07:41:46 PM PDT 24
Finished Jul 27 07:45:32 PM PDT 24
Peak memory 215516 kb
Host smart-f8d68a08-d0ce-41f1-a16a-701a8a0887e6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1207134745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.1207134745
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.2259128717
Short name T953
Test name
Test status
Simulation time 3932925980 ps
CPU time 24.53 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:42:18 PM PDT 24
Peak memory 207332 kb
Host smart-e3205bde-910e-4525-9b4b-df8ad8800804
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2259128717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.2259128717
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.368110273
Short name T1840
Test name
Test status
Simulation time 222729991 ps
CPU time 1 seconds
Started Jul 27 07:41:46 PM PDT 24
Finished Jul 27 07:41:47 PM PDT 24
Peak memory 207108 kb
Host smart-6cfe45c9-328e-4819-9445-f52a8ec2ac69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36811
0273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.368110273
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1703415155
Short name T2480
Test name
Test status
Simulation time 23292440106 ps
CPU time 31.57 seconds
Started Jul 27 07:41:50 PM PDT 24
Finished Jul 27 07:42:21 PM PDT 24
Peak memory 207380 kb
Host smart-7f39083a-a679-482e-90df-725386e1176a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17034
15155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1703415155
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.1347352294
Short name T2454
Test name
Test status
Simulation time 3283006427 ps
CPU time 5.04 seconds
Started Jul 27 07:41:45 PM PDT 24
Finished Jul 27 07:41:51 PM PDT 24
Peak memory 207392 kb
Host smart-ff6635de-0c6e-4e07-ba17-e001bba2c279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13473
52294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.1347352294
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.2629263574
Short name T1803
Test name
Test status
Simulation time 10094881283 ps
CPU time 99.24 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:43:34 PM PDT 24
Peak memory 217492 kb
Host smart-745c0610-ba25-497f-bd1f-069c0a909a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26292
63574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.2629263574
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.3821063902
Short name T163
Test name
Test status
Simulation time 3092493420 ps
CPU time 24.54 seconds
Started Jul 27 07:41:45 PM PDT 24
Finished Jul 27 07:42:10 PM PDT 24
Peak memory 217108 kb
Host smart-28a653c1-4a59-4d9a-80fd-ce9e3c448257
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3821063902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.3821063902
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.3179158514
Short name T2332
Test name
Test status
Simulation time 241171272 ps
CPU time 1.04 seconds
Started Jul 27 07:41:53 PM PDT 24
Finished Jul 27 07:41:54 PM PDT 24
Peak memory 207108 kb
Host smart-a6bded72-15da-4be0-8fb1-d5e1a66f2eb4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3179158514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.3179158514
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.10451480
Short name T1135
Test name
Test status
Simulation time 209701528 ps
CPU time 0.94 seconds
Started Jul 27 07:41:48 PM PDT 24
Finished Jul 27 07:41:49 PM PDT 24
Peak memory 207108 kb
Host smart-c7616db0-e87c-4418-851c-6b18a89fb6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10451
480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.10451480
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1676834349
Short name T921
Test name
Test status
Simulation time 5778446015 ps
CPU time 44.64 seconds
Started Jul 27 07:41:47 PM PDT 24
Finished Jul 27 07:42:31 PM PDT 24
Peak memory 215604 kb
Host smart-7ce6c0ef-260b-4598-b181-d9e44dc9614e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16768
34349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1676834349
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1950344123
Short name T1489
Test name
Test status
Simulation time 5140249393 ps
CPU time 40.73 seconds
Started Jul 27 07:41:50 PM PDT 24
Finished Jul 27 07:42:31 PM PDT 24
Peak memory 217044 kb
Host smart-449cf9f5-b4bf-4b0f-804b-a6e5d7450265
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1950344123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1950344123
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.1018048425
Short name T1157
Test name
Test status
Simulation time 166754417 ps
CPU time 0.86 seconds
Started Jul 27 07:41:53 PM PDT 24
Finished Jul 27 07:41:54 PM PDT 24
Peak memory 207108 kb
Host smart-f9834845-7cdb-4c33-8587-cd7012f57ab9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1018048425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.1018048425
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2228637524
Short name T1595
Test name
Test status
Simulation time 148533114 ps
CPU time 0.83 seconds
Started Jul 27 07:41:47 PM PDT 24
Finished Jul 27 07:41:48 PM PDT 24
Peak memory 207104 kb
Host smart-2ce873fb-5806-47f3-8871-6d3ee35a152b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22286
37524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2228637524
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1996179483
Short name T132
Test name
Test status
Simulation time 207169630 ps
CPU time 1.01 seconds
Started Jul 27 07:41:50 PM PDT 24
Finished Jul 27 07:41:51 PM PDT 24
Peak memory 207164 kb
Host smart-ae170f2f-6ce0-45c4-97ae-d17184926bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19961
79483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1996179483
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.2658633545
Short name T641
Test name
Test status
Simulation time 148335347 ps
CPU time 0.82 seconds
Started Jul 27 07:41:47 PM PDT 24
Finished Jul 27 07:41:48 PM PDT 24
Peak memory 207100 kb
Host smart-6a730aa9-b3a9-4830-be96-50c93dbb3dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26586
33545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2658633545
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1849653724
Short name T2659
Test name
Test status
Simulation time 163372328 ps
CPU time 0.9 seconds
Started Jul 27 07:41:53 PM PDT 24
Finished Jul 27 07:41:54 PM PDT 24
Peak memory 207148 kb
Host smart-b5934bef-7a95-4f7d-8547-cb95ab240cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18496
53724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1849653724
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1487027281
Short name T922
Test name
Test status
Simulation time 187732963 ps
CPU time 0.94 seconds
Started Jul 27 07:41:46 PM PDT 24
Finished Jul 27 07:41:47 PM PDT 24
Peak memory 207072 kb
Host smart-23a645e7-5aa6-49bf-862d-ca904deabc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14870
27281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1487027281
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1406227796
Short name T173
Test name
Test status
Simulation time 159917507 ps
CPU time 0.89 seconds
Started Jul 27 07:41:52 PM PDT 24
Finished Jul 27 07:41:53 PM PDT 24
Peak memory 207128 kb
Host smart-6fc2861d-f487-41d5-8b84-6206c1e57053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14062
27796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1406227796
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.2967901575
Short name T775
Test name
Test status
Simulation time 200798670 ps
CPU time 0.97 seconds
Started Jul 27 07:41:46 PM PDT 24
Finished Jul 27 07:41:47 PM PDT 24
Peak memory 207132 kb
Host smart-bdb84dd4-518d-4590-99e4-4571dffdd42b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2967901575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.2967901575
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1052700440
Short name T1166
Test name
Test status
Simulation time 158730767 ps
CPU time 0.88 seconds
Started Jul 27 07:41:52 PM PDT 24
Finished Jul 27 07:41:53 PM PDT 24
Peak memory 207092 kb
Host smart-068bf255-fbc3-45ab-9f04-c8ac25e2f1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10527
00440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1052700440
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1115003406
Short name T1061
Test name
Test status
Simulation time 49604529 ps
CPU time 0.7 seconds
Started Jul 27 07:41:47 PM PDT 24
Finished Jul 27 07:41:48 PM PDT 24
Peak memory 207064 kb
Host smart-5a9294f3-316e-4f6a-b8f3-3d49a9720429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11150
03406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1115003406
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.18737059
Short name T251
Test name
Test status
Simulation time 13817715585 ps
CPU time 33.27 seconds
Started Jul 27 07:41:52 PM PDT 24
Finished Jul 27 07:42:26 PM PDT 24
Peak memory 215556 kb
Host smart-5f374b5f-2847-4d99-a2da-ee3303d181f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18737
059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.18737059
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3379459554
Short name T1077
Test name
Test status
Simulation time 160681204 ps
CPU time 0.85 seconds
Started Jul 27 07:41:50 PM PDT 24
Finished Jul 27 07:41:51 PM PDT 24
Peak memory 207108 kb
Host smart-35162ec8-d299-436b-aa25-243cb30a1544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33794
59554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3379459554
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1485597596
Short name T2442
Test name
Test status
Simulation time 255304813 ps
CPU time 1.07 seconds
Started Jul 27 07:41:53 PM PDT 24
Finished Jul 27 07:41:54 PM PDT 24
Peak memory 207072 kb
Host smart-4b3d27cb-eac0-4ba6-8009-2c3d9466e2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14855
97596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1485597596
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.3739548137
Short name T1314
Test name
Test status
Simulation time 233043548 ps
CPU time 0.94 seconds
Started Jul 27 07:41:53 PM PDT 24
Finished Jul 27 07:41:54 PM PDT 24
Peak memory 207096 kb
Host smart-e31da947-5b8c-4951-8298-19cf7eeb73ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37395
48137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.3739548137
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1186215434
Short name T1604
Test name
Test status
Simulation time 166117650 ps
CPU time 0.85 seconds
Started Jul 27 07:41:45 PM PDT 24
Finished Jul 27 07:41:46 PM PDT 24
Peak memory 207140 kb
Host smart-105976e9-a463-4bec-bf7e-52b1b7150513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11862
15434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1186215434
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.3348054823
Short name T2448
Test name
Test status
Simulation time 139426555 ps
CPU time 0.79 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:41:55 PM PDT 24
Peak memory 207084 kb
Host smart-ac83bb1d-43fd-4c50-a19d-429401d39d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33480
54823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.3348054823
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1613263654
Short name T90
Test name
Test status
Simulation time 153464337 ps
CPU time 0.84 seconds
Started Jul 27 07:41:55 PM PDT 24
Finished Jul 27 07:41:56 PM PDT 24
Peak memory 207132 kb
Host smart-8799a82a-a7ca-4e02-acc5-df9ad897357b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16132
63654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1613263654
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1261133641
Short name T2145
Test name
Test status
Simulation time 156264354 ps
CPU time 0.84 seconds
Started Jul 27 07:41:47 PM PDT 24
Finished Jul 27 07:41:48 PM PDT 24
Peak memory 207196 kb
Host smart-6e2e1fe6-7e82-4819-918c-b9e1b68ab75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12611
33641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1261133641
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3564558417
Short name T1333
Test name
Test status
Simulation time 234891298 ps
CPU time 1.07 seconds
Started Jul 27 07:41:53 PM PDT 24
Finished Jul 27 07:41:54 PM PDT 24
Peak memory 207160 kb
Host smart-2efaa22b-dda8-46b0-8316-ec122eeaae06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35645
58417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3564558417
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.126417703
Short name T910
Test name
Test status
Simulation time 5443820793 ps
CPU time 155.6 seconds
Started Jul 27 07:41:53 PM PDT 24
Finished Jul 27 07:44:29 PM PDT 24
Peak memory 215580 kb
Host smart-bc562264-7f86-4a3c-b5b4-9ee1061ac809
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=126417703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.126417703
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.648438159
Short name T2075
Test name
Test status
Simulation time 175406836 ps
CPU time 0.92 seconds
Started Jul 27 07:41:53 PM PDT 24
Finished Jul 27 07:41:54 PM PDT 24
Peak memory 207164 kb
Host smart-a16febd0-ed7a-4c06-8771-85765152fca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64843
8159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.648438159
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1100967771
Short name T995
Test name
Test status
Simulation time 183152975 ps
CPU time 0.9 seconds
Started Jul 27 07:41:55 PM PDT 24
Finished Jul 27 07:41:56 PM PDT 24
Peak memory 206988 kb
Host smart-696271c5-7f7d-4a7f-910d-d8f6bd66ed4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11009
67771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1100967771
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.166575481
Short name T1590
Test name
Test status
Simulation time 844715711 ps
CPU time 2.25 seconds
Started Jul 27 07:42:03 PM PDT 24
Finished Jul 27 07:42:05 PM PDT 24
Peak memory 207328 kb
Host smart-074e00ea-9b34-40a7-81fd-a3fdb284a829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16657
5481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.166575481
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.4055355506
Short name T447
Test name
Test status
Simulation time 6504431642 ps
CPU time 195.61 seconds
Started Jul 27 07:41:56 PM PDT 24
Finished Jul 27 07:45:12 PM PDT 24
Peak memory 215616 kb
Host smart-80d61a29-87d0-460b-ab49-aa446ceb8c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40553
55506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.4055355506
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.1849942468
Short name T1826
Test name
Test status
Simulation time 355663110 ps
CPU time 4.77 seconds
Started Jul 27 07:41:43 PM PDT 24
Finished Jul 27 07:41:48 PM PDT 24
Peak memory 207300 kb
Host smart-872f9f31-ad26-484b-9dd5-ab2ffb4acdab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849942468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.1849942468
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1654450288
Short name T2695
Test name
Test status
Simulation time 35577100 ps
CPU time 0.65 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:08 PM PDT 24
Peak memory 207164 kb
Host smart-10f470b6-2157-497f-981a-a33cf7e6c541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1654450288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1654450288
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2523464357
Short name T2457
Test name
Test status
Simulation time 3539078856 ps
CPU time 5.19 seconds
Started Jul 27 07:42:03 PM PDT 24
Finished Jul 27 07:42:09 PM PDT 24
Peak memory 207396 kb
Host smart-3649dcc1-e152-42f1-bb1f-c23e1ac53615
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523464357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.2523464357
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.4135702564
Short name T2350
Test name
Test status
Simulation time 13476034554 ps
CPU time 15.94 seconds
Started Jul 27 07:42:05 PM PDT 24
Finished Jul 27 07:42:21 PM PDT 24
Peak memory 207412 kb
Host smart-7ec88af3-2072-490d-8aa5-3e5675543a63
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135702564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.4135702564
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3325584500
Short name T779
Test name
Test status
Simulation time 23404201162 ps
CPU time 28.46 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:42:23 PM PDT 24
Peak memory 207380 kb
Host smart-f8880b6d-918b-4d00-9a43-edcc36da0e15
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325584500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.3325584500
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1781794507
Short name T603
Test name
Test status
Simulation time 149918731 ps
CPU time 0.82 seconds
Started Jul 27 07:41:55 PM PDT 24
Finished Jul 27 07:41:56 PM PDT 24
Peak memory 207112 kb
Host smart-14007eb6-5a07-43ad-a45d-d0d7f1b71208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17817
94507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1781794507
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.3077097619
Short name T2629
Test name
Test status
Simulation time 153488168 ps
CPU time 0.86 seconds
Started Jul 27 07:42:04 PM PDT 24
Finished Jul 27 07:42:05 PM PDT 24
Peak memory 207092 kb
Host smart-51604b24-6706-48f9-b069-f807bb9440fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30770
97619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.3077097619
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2705082755
Short name T530
Test name
Test status
Simulation time 471166889 ps
CPU time 1.62 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:41:56 PM PDT 24
Peak memory 207332 kb
Host smart-f408c2f8-7794-4af9-9252-7466ed087c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27050
82755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2705082755
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.202376019
Short name T1512
Test name
Test status
Simulation time 1196574844 ps
CPU time 3 seconds
Started Jul 27 07:41:57 PM PDT 24
Finished Jul 27 07:42:00 PM PDT 24
Peak memory 207468 kb
Host smart-afab30cd-8bee-483e-a74c-e7e970df5aa1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=202376019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.202376019
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.2629795324
Short name T1045
Test name
Test status
Simulation time 22357626104 ps
CPU time 51.39 seconds
Started Jul 27 07:41:53 PM PDT 24
Finished Jul 27 07:42:45 PM PDT 24
Peak memory 207408 kb
Host smart-7c437884-6b3a-4ff4-9711-cd352a7e191e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26297
95324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2629795324
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.4133952155
Short name T830
Test name
Test status
Simulation time 7056832865 ps
CPU time 47.51 seconds
Started Jul 27 07:41:57 PM PDT 24
Finished Jul 27 07:42:44 PM PDT 24
Peak memory 207328 kb
Host smart-59fb405d-44c6-49f3-b603-4eb180fe06c6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133952155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.4133952155
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.1506625667
Short name T1307
Test name
Test status
Simulation time 362251437 ps
CPU time 1.37 seconds
Started Jul 27 07:41:57 PM PDT 24
Finished Jul 27 07:41:59 PM PDT 24
Peak memory 207160 kb
Host smart-07bdb482-095b-4f00-a46d-e22c964e5f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15066
25667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.1506625667
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.712017665
Short name T2215
Test name
Test status
Simulation time 171288558 ps
CPU time 0.86 seconds
Started Jul 27 07:42:05 PM PDT 24
Finished Jul 27 07:42:06 PM PDT 24
Peak memory 207112 kb
Host smart-b6a7cd5f-0f3d-45e1-9f3e-495fe45c8233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71201
7665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.712017665
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.2917786277
Short name T1372
Test name
Test status
Simulation time 39138359 ps
CPU time 0.68 seconds
Started Jul 27 07:41:57 PM PDT 24
Finished Jul 27 07:41:58 PM PDT 24
Peak memory 207036 kb
Host smart-ceb54873-0980-4a6a-85fe-d303380cad06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29177
86277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2917786277
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.71454036
Short name T2743
Test name
Test status
Simulation time 852484532 ps
CPU time 2.38 seconds
Started Jul 27 07:42:04 PM PDT 24
Finished Jul 27 07:42:06 PM PDT 24
Peak memory 207372 kb
Host smart-b962ec5a-2d2e-4f99-b7fe-0dbcb1af5c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71454
036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.71454036
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1874353287
Short name T2832
Test name
Test status
Simulation time 334268190 ps
CPU time 2.27 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:41:57 PM PDT 24
Peak memory 207280 kb
Host smart-bb6be06a-4801-48c6-8ca4-1846cda878b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18743
53287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1874353287
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.4204558708
Short name T91
Test name
Test status
Simulation time 198708104 ps
CPU time 1.01 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:41:55 PM PDT 24
Peak memory 207404 kb
Host smart-3c03cfd6-577f-4952-85f7-b39bafeaa071
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4204558708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.4204558708
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2118577562
Short name T1233
Test name
Test status
Simulation time 177800596 ps
CPU time 0.88 seconds
Started Jul 27 07:42:01 PM PDT 24
Finished Jul 27 07:42:02 PM PDT 24
Peak memory 207080 kb
Host smart-e907961b-b177-4288-b702-d7f51101a22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21185
77562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2118577562
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3788430968
Short name T1870
Test name
Test status
Simulation time 242403934 ps
CPU time 1.05 seconds
Started Jul 27 07:42:05 PM PDT 24
Finished Jul 27 07:42:06 PM PDT 24
Peak memory 207148 kb
Host smart-701d8d8a-0798-4624-8cfd-4d57468a21f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37884
30968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3788430968
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.2688216892
Short name T2476
Test name
Test status
Simulation time 6216272252 ps
CPU time 63.57 seconds
Started Jul 27 07:41:55 PM PDT 24
Finished Jul 27 07:42:59 PM PDT 24
Peak memory 216668 kb
Host smart-28b9136c-f09f-46f4-ac36-47c3393764da
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2688216892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.2688216892
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.2414947842
Short name T1400
Test name
Test status
Simulation time 11353085006 ps
CPU time 79.5 seconds
Started Jul 27 07:41:59 PM PDT 24
Finished Jul 27 07:43:19 PM PDT 24
Peak memory 207372 kb
Host smart-ef3a8eef-2bbf-4777-90ad-c4a80b9d603d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2414947842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.2414947842
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2031882543
Short name T1626
Test name
Test status
Simulation time 186832964 ps
CPU time 0.88 seconds
Started Jul 27 07:42:04 PM PDT 24
Finished Jul 27 07:42:05 PM PDT 24
Peak memory 207124 kb
Host smart-b9775951-3778-4d59-a690-c46cb6ca6326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20318
82543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2031882543
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.1805032032
Short name T2036
Test name
Test status
Simulation time 23353465752 ps
CPU time 27.6 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:42:22 PM PDT 24
Peak memory 207344 kb
Host smart-a8a8e1cc-b569-4382-9cd6-121b8781f1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18050
32032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.1805032032
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.3956972767
Short name T1262
Test name
Test status
Simulation time 3290459359 ps
CPU time 4.73 seconds
Started Jul 27 07:41:59 PM PDT 24
Finished Jul 27 07:42:04 PM PDT 24
Peak memory 207348 kb
Host smart-80846634-33ac-4df7-b0f7-4429bcfe6ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39569
72767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.3956972767
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.1026622544
Short name T1402
Test name
Test status
Simulation time 9107923532 ps
CPU time 86.74 seconds
Started Jul 27 07:42:05 PM PDT 24
Finished Jul 27 07:43:32 PM PDT 24
Peak memory 217620 kb
Host smart-cf0e4f3f-831b-46cf-967f-0879cde26af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10266
22544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.1026622544
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.85168323
Short name T2192
Test name
Test status
Simulation time 4523180974 ps
CPU time 127.78 seconds
Started Jul 27 07:41:54 PM PDT 24
Finished Jul 27 07:44:02 PM PDT 24
Peak memory 215616 kb
Host smart-5df53a0d-7bbb-4818-92bd-784a773507d6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=85168323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.85168323
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1790780174
Short name T1319
Test name
Test status
Simulation time 242108040 ps
CPU time 1 seconds
Started Jul 27 07:41:58 PM PDT 24
Finished Jul 27 07:41:59 PM PDT 24
Peak memory 207084 kb
Host smart-88ddd033-50b4-468e-be55-3afb27783f8b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1790780174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1790780174
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2897087927
Short name T2760
Test name
Test status
Simulation time 182021207 ps
CPU time 0.97 seconds
Started Jul 27 07:41:55 PM PDT 24
Finished Jul 27 07:41:56 PM PDT 24
Peak memory 207084 kb
Host smart-45400466-5bfc-4165-90ed-2b8fded3df08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28970
87927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2897087927
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.2845174811
Short name T1576
Test name
Test status
Simulation time 4248364476 ps
CPU time 31.89 seconds
Started Jul 27 07:41:57 PM PDT 24
Finished Jul 27 07:42:29 PM PDT 24
Peak memory 215476 kb
Host smart-a1f4ac6d-21ad-44ec-b564-b78526ece5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28451
74811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.2845174811
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.3176225573
Short name T161
Test name
Test status
Simulation time 3221465502 ps
CPU time 93.81 seconds
Started Jul 27 07:42:05 PM PDT 24
Finished Jul 27 07:43:39 PM PDT 24
Peak memory 215624 kb
Host smart-dbac520f-1b1f-4d2a-ac32-797e254530c6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3176225573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.3176225573
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.4186879120
Short name T2580
Test name
Test status
Simulation time 176403114 ps
CPU time 0.89 seconds
Started Jul 27 07:41:56 PM PDT 24
Finished Jul 27 07:41:57 PM PDT 24
Peak memory 207112 kb
Host smart-82ecf616-a02a-404c-9864-a44686e19284
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4186879120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.4186879120
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.414766865
Short name T582
Test name
Test status
Simulation time 169407062 ps
CPU time 0.93 seconds
Started Jul 27 07:41:58 PM PDT 24
Finished Jul 27 07:41:59 PM PDT 24
Peak memory 207124 kb
Host smart-12f4e483-2ca1-41cc-9f1f-838dc43bdf8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41476
6865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.414766865
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1329972404
Short name T140
Test name
Test status
Simulation time 202427910 ps
CPU time 0.98 seconds
Started Jul 27 07:41:57 PM PDT 24
Finished Jul 27 07:41:58 PM PDT 24
Peak memory 207128 kb
Host smart-571f5c59-27c6-4db4-9bad-497e16e8bf1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13299
72404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1329972404
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1132003029
Short name T1961
Test name
Test status
Simulation time 193473809 ps
CPU time 0.91 seconds
Started Jul 27 07:42:08 PM PDT 24
Finished Jul 27 07:42:09 PM PDT 24
Peak memory 207096 kb
Host smart-f0c788a0-c04d-4a4a-a89e-230d1af24f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11320
03029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1132003029
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2142416088
Short name T2317
Test name
Test status
Simulation time 156190322 ps
CPU time 0.86 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:08 PM PDT 24
Peak memory 207208 kb
Host smart-feb6528c-3bf7-4043-a614-ac64196440cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21424
16088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2142416088
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2226917997
Short name T1944
Test name
Test status
Simulation time 179745146 ps
CPU time 0.91 seconds
Started Jul 27 07:42:09 PM PDT 24
Finished Jul 27 07:42:10 PM PDT 24
Peak memory 207108 kb
Host smart-360b6203-9e46-4beb-bdbd-014f22c12180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22269
17997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2226917997
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.547743889
Short name T1750
Test name
Test status
Simulation time 267493976 ps
CPU time 1.03 seconds
Started Jul 27 07:42:12 PM PDT 24
Finished Jul 27 07:42:13 PM PDT 24
Peak memory 207096 kb
Host smart-6c3079b5-9410-4b03-9898-3a0237f33a17
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=547743889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.547743889
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.4103706726
Short name T893
Test name
Test status
Simulation time 147292899 ps
CPU time 0.88 seconds
Started Jul 27 07:42:10 PM PDT 24
Finished Jul 27 07:42:11 PM PDT 24
Peak memory 207056 kb
Host smart-2ea212b1-868d-4e06-9dbd-26ceaa5987d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41037
06726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.4103706726
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2248088364
Short name T935
Test name
Test status
Simulation time 38630732 ps
CPU time 0.68 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:07 PM PDT 24
Peak memory 207036 kb
Host smart-ac1b8b8d-9153-498d-bbeb-990837aa83d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22480
88364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2248088364
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3811838048
Short name T1031
Test name
Test status
Simulation time 19394931902 ps
CPU time 48.24 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:43:03 PM PDT 24
Peak memory 215696 kb
Host smart-9db9124d-058f-4d62-a9d6-0073d92e5bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38118
38048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3811838048
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1151610722
Short name T317
Test name
Test status
Simulation time 175622920 ps
CPU time 0.96 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:08 PM PDT 24
Peak memory 207064 kb
Host smart-3fd8d9b9-b2b3-4f88-a29a-a13c7a8e8cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11516
10722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1151610722
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.4085139411
Short name T2377
Test name
Test status
Simulation time 210665321 ps
CPU time 0.91 seconds
Started Jul 27 07:42:14 PM PDT 24
Finished Jul 27 07:42:15 PM PDT 24
Peak memory 207116 kb
Host smart-07a97df0-1857-4c36-b3e7-829889dd0e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40851
39411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.4085139411
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1585814884
Short name T611
Test name
Test status
Simulation time 209142691 ps
CPU time 0.91 seconds
Started Jul 27 07:42:14 PM PDT 24
Finished Jul 27 07:42:15 PM PDT 24
Peak memory 207124 kb
Host smart-d3d069f5-4170-43f2-8106-5e1303cae071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15858
14884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1585814884
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.2032067539
Short name T2578
Test name
Test status
Simulation time 167721616 ps
CPU time 0.89 seconds
Started Jul 27 07:42:06 PM PDT 24
Finished Jul 27 07:42:07 PM PDT 24
Peak memory 207136 kb
Host smart-828b9545-12af-40eb-8b93-040ac44ac446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20320
67539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.2032067539
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.4144472980
Short name T1876
Test name
Test status
Simulation time 178438601 ps
CPU time 0.87 seconds
Started Jul 27 07:42:10 PM PDT 24
Finished Jul 27 07:42:11 PM PDT 24
Peak memory 207108 kb
Host smart-b51da709-d47d-48cc-9fa5-5b47d34f76d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41444
72980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.4144472980
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.206415148
Short name T519
Test name
Test status
Simulation time 169439843 ps
CPU time 0.84 seconds
Started Jul 27 07:42:08 PM PDT 24
Finished Jul 27 07:42:09 PM PDT 24
Peak memory 207064 kb
Host smart-ee4114c5-47be-4886-8268-dbe839375cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20641
5148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.206415148
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.823557282
Short name T875
Test name
Test status
Simulation time 223499452 ps
CPU time 0.93 seconds
Started Jul 27 07:42:14 PM PDT 24
Finished Jul 27 07:42:15 PM PDT 24
Peak memory 207256 kb
Host smart-d9cf9d7e-9811-4ace-bdca-04130c131b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82355
7282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.823557282
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.943219174
Short name T1140
Test name
Test status
Simulation time 239896436 ps
CPU time 1.03 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:08 PM PDT 24
Peak memory 207080 kb
Host smart-38b3bda1-b41f-4c78-b82b-a75edf07cc9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94321
9174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.943219174
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2260524066
Short name T1042
Test name
Test status
Simulation time 5930594483 ps
CPU time 46.75 seconds
Started Jul 27 07:42:08 PM PDT 24
Finished Jul 27 07:42:54 PM PDT 24
Peak memory 217080 kb
Host smart-da33ec11-b965-4fb6-a65a-fc2f5cc44654
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2260524066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2260524066
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2796069115
Short name T1583
Test name
Test status
Simulation time 143019432 ps
CPU time 0.8 seconds
Started Jul 27 07:42:04 PM PDT 24
Finished Jul 27 07:42:05 PM PDT 24
Peak memory 207144 kb
Host smart-8dd64c96-55e0-46cf-b09a-f13fa8aa8d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27960
69115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2796069115
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3945745089
Short name T1096
Test name
Test status
Simulation time 200706820 ps
CPU time 0.91 seconds
Started Jul 27 07:42:06 PM PDT 24
Finished Jul 27 07:42:07 PM PDT 24
Peak memory 207136 kb
Host smart-25493a11-73ab-451c-bd25-0673db81f8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39457
45089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3945745089
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.652528130
Short name T2133
Test name
Test status
Simulation time 507994164 ps
CPU time 1.52 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:09 PM PDT 24
Peak memory 207112 kb
Host smart-abe84036-12c9-43d8-8ff9-3b00fa345e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65252
8130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.652528130
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.1501279600
Short name T1774
Test name
Test status
Simulation time 4350411294 ps
CPU time 126.78 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:44:13 PM PDT 24
Peak memory 215492 kb
Host smart-bc41dc29-c0df-4f0a-81d2-a9e5d4f2b37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15012
79600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.1501279600
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.1733399721
Short name T691
Test name
Test status
Simulation time 1566104181 ps
CPU time 38.53 seconds
Started Jul 27 07:41:55 PM PDT 24
Finished Jul 27 07:42:34 PM PDT 24
Peak memory 207288 kb
Host smart-4bef1cf7-eb6e-47c3-bf46-60440b46cbbe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733399721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.1733399721
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.4102810255
Short name T1455
Test name
Test status
Simulation time 46922246 ps
CPU time 0.69 seconds
Started Jul 27 07:42:18 PM PDT 24
Finished Jul 27 07:42:18 PM PDT 24
Peak memory 207104 kb
Host smart-0da786be-3186-46f6-a969-7059dc6b6dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4102810255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.4102810255
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2873938162
Short name T1232
Test name
Test status
Simulation time 4110600402 ps
CPU time 6.14 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:13 PM PDT 24
Peak memory 207348 kb
Host smart-1e4f9a2f-5b6c-497d-b487-20c372e30a88
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873938162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.2873938162
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3575401043
Short name T208
Test name
Test status
Simulation time 13369312941 ps
CPU time 19.38 seconds
Started Jul 27 07:42:05 PM PDT 24
Finished Jul 27 07:42:25 PM PDT 24
Peak memory 207376 kb
Host smart-44bc2c36-685d-420a-84f6-d561ea8775a9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575401043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3575401043
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1088393184
Short name T2023
Test name
Test status
Simulation time 23351649370 ps
CPU time 27.11 seconds
Started Jul 27 07:42:05 PM PDT 24
Finished Jul 27 07:42:32 PM PDT 24
Peak memory 207320 kb
Host smart-c2791af2-e0af-4538-9bd3-23b35bb12fc7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088393184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.1088393184
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3819557334
Short name T521
Test name
Test status
Simulation time 146372954 ps
CPU time 0.81 seconds
Started Jul 27 07:42:12 PM PDT 24
Finished Jul 27 07:42:13 PM PDT 24
Peak memory 207088 kb
Host smart-85bdfdd4-70ad-4bcb-a996-a2836f5351b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38195
57334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3819557334
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.2785465570
Short name T1973
Test name
Test status
Simulation time 173950262 ps
CPU time 0.87 seconds
Started Jul 27 07:42:13 PM PDT 24
Finished Jul 27 07:42:14 PM PDT 24
Peak memory 207208 kb
Host smart-bf7f47cb-3e69-408c-978f-d9fab5a17e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27854
65570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.2785465570
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.2112062470
Short name T2123
Test name
Test status
Simulation time 473055739 ps
CPU time 1.51 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:08 PM PDT 24
Peak memory 207156 kb
Host smart-c6882830-54f6-46c0-9aa9-7eab372d9af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21120
62470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.2112062470
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.603306010
Short name T1852
Test name
Test status
Simulation time 1030802475 ps
CPU time 2.53 seconds
Started Jul 27 07:42:13 PM PDT 24
Finished Jul 27 07:42:16 PM PDT 24
Peak memory 207336 kb
Host smart-6ee1c0e5-69e0-47e2-9fea-f976b016aacb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=603306010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.603306010
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.2117555467
Short name T861
Test name
Test status
Simulation time 15110789735 ps
CPU time 32.73 seconds
Started Jul 27 07:42:12 PM PDT 24
Finished Jul 27 07:42:45 PM PDT 24
Peak memory 207352 kb
Host smart-83fba3c9-7a96-40d0-95a7-499b164df7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21175
55467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.2117555467
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.2467321410
Short name T1133
Test name
Test status
Simulation time 6420975165 ps
CPU time 40.34 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:47 PM PDT 24
Peak memory 207332 kb
Host smart-1cd28bc6-1ce7-4282-833a-360ebd115b67
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467321410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.2467321410
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3129619317
Short name T1491
Test name
Test status
Simulation time 463728443 ps
CPU time 1.43 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:08 PM PDT 24
Peak memory 206988 kb
Host smart-86aafd37-28f2-49b7-9904-e82812184c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31296
19317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3129619317
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3825582108
Short name T2827
Test name
Test status
Simulation time 146209974 ps
CPU time 0.85 seconds
Started Jul 27 07:42:11 PM PDT 24
Finished Jul 27 07:42:12 PM PDT 24
Peak memory 207080 kb
Host smart-6d5a4414-0750-4bf0-820f-a1e83cd81cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38255
82108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3825582108
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.3562884878
Short name T102
Test name
Test status
Simulation time 37567490 ps
CPU time 0.76 seconds
Started Jul 27 07:42:06 PM PDT 24
Finished Jul 27 07:42:07 PM PDT 24
Peak memory 207160 kb
Host smart-29da14db-1e39-4607-945f-8fcf9accaf37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35628
84878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3562884878
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.4198424722
Short name T2166
Test name
Test status
Simulation time 960260217 ps
CPU time 2.61 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:10 PM PDT 24
Peak memory 207324 kb
Host smart-6ce6ca3f-4346-4238-bc2d-3a880484802a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41984
24722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.4198424722
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3611530045
Short name T1497
Test name
Test status
Simulation time 247898450 ps
CPU time 1.6 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:09 PM PDT 24
Peak memory 207280 kb
Host smart-b4aa66f0-647a-4cb9-a3ec-ae35664c19f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36115
30045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3611530045
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1368583797
Short name T575
Test name
Test status
Simulation time 191957144 ps
CPU time 0.97 seconds
Started Jul 27 07:42:08 PM PDT 24
Finished Jul 27 07:42:09 PM PDT 24
Peak memory 207300 kb
Host smart-04a1e3d7-8663-48b6-9ccc-f76f6f25ea84
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1368583797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1368583797
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3325474748
Short name T1190
Test name
Test status
Simulation time 172044047 ps
CPU time 0.84 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:08 PM PDT 24
Peak memory 207056 kb
Host smart-7d7f05d1-39e5-497a-b0c5-7ef865c0e620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33254
74748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3325474748
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2029216542
Short name T513
Test name
Test status
Simulation time 235512489 ps
CPU time 0.97 seconds
Started Jul 27 07:42:06 PM PDT 24
Finished Jul 27 07:42:07 PM PDT 24
Peak memory 207144 kb
Host smart-48372fe9-9471-4f07-aedd-d792ec95ae88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20292
16542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2029216542
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.4116564818
Short name T753
Test name
Test status
Simulation time 6658113827 ps
CPU time 49.62 seconds
Started Jul 27 07:42:13 PM PDT 24
Finished Jul 27 07:43:03 PM PDT 24
Peak memory 217228 kb
Host smart-278814d1-4bc4-4fbe-9bca-7564b133916e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4116564818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.4116564818
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.2069772818
Short name T743
Test name
Test status
Simulation time 190636466 ps
CPU time 1 seconds
Started Jul 27 07:42:07 PM PDT 24
Finished Jul 27 07:42:08 PM PDT 24
Peak memory 207108 kb
Host smart-a6778a04-d50e-4476-ba56-683c04a6b6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20697
72818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2069772818
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.3716395366
Short name T2312
Test name
Test status
Simulation time 23324518725 ps
CPU time 31.33 seconds
Started Jul 27 07:42:10 PM PDT 24
Finished Jul 27 07:42:41 PM PDT 24
Peak memory 207292 kb
Host smart-452046ab-0944-4bd9-aa6a-5d9cd948fa2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37163
95366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.3716395366
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.867025737
Short name T2184
Test name
Test status
Simulation time 3387639322 ps
CPU time 5.65 seconds
Started Jul 27 07:42:12 PM PDT 24
Finished Jul 27 07:42:18 PM PDT 24
Peak memory 207256 kb
Host smart-02f94c90-1e0c-4b4e-b23a-c95c5cc3cd62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86702
5737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.867025737
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.248773644
Short name T2136
Test name
Test status
Simulation time 5712957754 ps
CPU time 52.24 seconds
Started Jul 27 07:42:08 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 218396 kb
Host smart-85562c9b-a0b6-4091-87b6-0f1ae29a6121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24877
3644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.248773644
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3226100754
Short name T1025
Test name
Test status
Simulation time 5130999900 ps
CPU time 37.14 seconds
Started Jul 27 07:42:12 PM PDT 24
Finished Jul 27 07:42:49 PM PDT 24
Peak memory 217036 kb
Host smart-974b3717-4f2d-491a-880b-f7f8db89c533
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3226100754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3226100754
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2161833111
Short name T1592
Test name
Test status
Simulation time 252591701 ps
CPU time 1.05 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:17 PM PDT 24
Peak memory 207260 kb
Host smart-ed9018b0-77e8-4571-b3d0-815cad8879d9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2161833111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2161833111
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1463767895
Short name T659
Test name
Test status
Simulation time 192335155 ps
CPU time 0.93 seconds
Started Jul 27 07:42:30 PM PDT 24
Finished Jul 27 07:42:31 PM PDT 24
Peak memory 207016 kb
Host smart-a8bf7dd2-1643-4f60-b2e2-a24dfcb2c2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14637
67895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1463767895
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.1335714826
Short name T644
Test name
Test status
Simulation time 5218730450 ps
CPU time 50.44 seconds
Started Jul 27 07:42:16 PM PDT 24
Finished Jul 27 07:43:06 PM PDT 24
Peak memory 217040 kb
Host smart-48be8180-861e-43ad-9a4d-01bcdfdf53ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13357
14826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.1335714826
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.341362864
Short name T1469
Test name
Test status
Simulation time 3691427078 ps
CPU time 102.02 seconds
Started Jul 27 07:42:13 PM PDT 24
Finished Jul 27 07:43:55 PM PDT 24
Peak memory 223556 kb
Host smart-28dbfd48-3117-4cca-8088-596619d994da
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=341362864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.341362864
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.1114631292
Short name T413
Test name
Test status
Simulation time 159971329 ps
CPU time 0.84 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:16 PM PDT 24
Peak memory 207100 kb
Host smart-a3c2d2ff-ab5c-47c2-b7e1-e9ea5ede9a16
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1114631292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.1114631292
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1685424990
Short name T1149
Test name
Test status
Simulation time 226039386 ps
CPU time 0.95 seconds
Started Jul 27 07:42:14 PM PDT 24
Finished Jul 27 07:42:15 PM PDT 24
Peak memory 207084 kb
Host smart-f7b94add-4009-41bf-b5b8-9aec6f562048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16854
24990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1685424990
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.409409008
Short name T138
Test name
Test status
Simulation time 185890207 ps
CPU time 0.95 seconds
Started Jul 27 07:42:30 PM PDT 24
Finished Jul 27 07:42:31 PM PDT 24
Peak memory 206948 kb
Host smart-cbeb1cf5-78cc-48a3-bf90-faa4739e7aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40940
9008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.409409008
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.3669224877
Short name T113
Test name
Test status
Simulation time 174473716 ps
CPU time 0.87 seconds
Started Jul 27 07:42:13 PM PDT 24
Finished Jul 27 07:42:14 PM PDT 24
Peak memory 207068 kb
Host smart-ba665ada-b1c7-4ba5-9f27-2caa7f2cba17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36692
24877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.3669224877
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2354390082
Short name T1943
Test name
Test status
Simulation time 184880087 ps
CPU time 0.85 seconds
Started Jul 27 07:42:18 PM PDT 24
Finished Jul 27 07:42:19 PM PDT 24
Peak memory 207164 kb
Host smart-76a7631f-5fb0-4adf-8e5f-9154e1d347eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23543
90082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2354390082
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2318119597
Short name T993
Test name
Test status
Simulation time 172233355 ps
CPU time 0.84 seconds
Started Jul 27 07:42:14 PM PDT 24
Finished Jul 27 07:42:15 PM PDT 24
Peak memory 207108 kb
Host smart-bcc17a32-7875-411d-bb65-0fa389e70372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23181
19597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2318119597
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3111200658
Short name T2508
Test name
Test status
Simulation time 197041443 ps
CPU time 0.94 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:16 PM PDT 24
Peak memory 207220 kb
Host smart-93078481-0fe5-40fc-a313-af263d5e5099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31112
00658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3111200658
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.2483212959
Short name T421
Test name
Test status
Simulation time 229111499 ps
CPU time 1.08 seconds
Started Jul 27 07:42:13 PM PDT 24
Finished Jul 27 07:42:14 PM PDT 24
Peak memory 207328 kb
Host smart-4d5d4d80-073f-48f4-8604-22e149052a30
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2483212959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.2483212959
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.720546463
Short name T504
Test name
Test status
Simulation time 215486555 ps
CPU time 0.91 seconds
Started Jul 27 07:42:16 PM PDT 24
Finished Jul 27 07:42:17 PM PDT 24
Peak memory 207164 kb
Host smart-9b4f3abf-0815-4987-b968-d7cf820fd8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72054
6463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.720546463
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1269853186
Short name T2611
Test name
Test status
Simulation time 68070423 ps
CPU time 0.74 seconds
Started Jul 27 07:42:14 PM PDT 24
Finished Jul 27 07:42:15 PM PDT 24
Peak memory 207172 kb
Host smart-f82c4749-7bc2-499f-b926-6b96ab5fa59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12698
53186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1269853186
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3640692348
Short name T252
Test name
Test status
Simulation time 20939690827 ps
CPU time 60.69 seconds
Started Jul 27 07:42:30 PM PDT 24
Finished Jul 27 07:43:31 PM PDT 24
Peak memory 215528 kb
Host smart-a9879fc6-bfff-4801-b517-505061f5c311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36406
92348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3640692348
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.524795877
Short name T669
Test name
Test status
Simulation time 190440184 ps
CPU time 0.92 seconds
Started Jul 27 07:42:17 PM PDT 24
Finished Jul 27 07:42:18 PM PDT 24
Peak memory 207108 kb
Host smart-2c80da9a-caf1-4eb8-8a5f-6a88a9f6f4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52479
5877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.524795877
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3356734428
Short name T1161
Test name
Test status
Simulation time 177169094 ps
CPU time 0.98 seconds
Started Jul 27 07:42:12 PM PDT 24
Finished Jul 27 07:42:13 PM PDT 24
Peak memory 207104 kb
Host smart-7e26cf79-5893-4b2e-85d3-48e22c7bab52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33567
34428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3356734428
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2477990097
Short name T1361
Test name
Test status
Simulation time 174767701 ps
CPU time 0.9 seconds
Started Jul 27 07:42:14 PM PDT 24
Finished Jul 27 07:42:15 PM PDT 24
Peak memory 207136 kb
Host smart-679e1b71-10aa-4c37-b82c-9ecffcc497a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24779
90097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2477990097
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.556567462
Short name T1069
Test name
Test status
Simulation time 155302185 ps
CPU time 0.8 seconds
Started Jul 27 07:42:14 PM PDT 24
Finished Jul 27 07:42:15 PM PDT 24
Peak memory 207112 kb
Host smart-2ed1028a-455b-4a32-a0a0-14fbf48ab99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55656
7462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.556567462
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2451880460
Short name T1080
Test name
Test status
Simulation time 177800903 ps
CPU time 0.91 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:16 PM PDT 24
Peak memory 207096 kb
Host smart-2d7479a3-de20-46fc-8667-92f86307e87c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24518
80460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2451880460
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2910490292
Short name T860
Test name
Test status
Simulation time 156017042 ps
CPU time 0.88 seconds
Started Jul 27 07:42:18 PM PDT 24
Finished Jul 27 07:42:19 PM PDT 24
Peak memory 207080 kb
Host smart-4cfe9b65-b4b9-409c-87a1-7424ce6d95ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29104
90292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2910490292
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3464413640
Short name T1622
Test name
Test status
Simulation time 152749299 ps
CPU time 0.88 seconds
Started Jul 27 07:42:14 PM PDT 24
Finished Jul 27 07:42:15 PM PDT 24
Peak memory 207104 kb
Host smart-fe7cd2d9-dc95-437d-b2e8-83e01a1d1de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34644
13640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3464413640
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3285553886
Short name T1089
Test name
Test status
Simulation time 249518827 ps
CPU time 1.08 seconds
Started Jul 27 07:42:18 PM PDT 24
Finished Jul 27 07:42:19 PM PDT 24
Peak memory 207112 kb
Host smart-8cb2d262-5cc8-4941-9b7e-d6bbdf0af97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32855
53886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3285553886
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1717809248
Short name T1408
Test name
Test status
Simulation time 4311028426 ps
CPU time 131.5 seconds
Started Jul 27 07:42:14 PM PDT 24
Finished Jul 27 07:44:25 PM PDT 24
Peak memory 215544 kb
Host smart-753c3da4-de84-4f14-92d5-e900e0b6799d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1717809248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1717809248
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3964755694
Short name T1392
Test name
Test status
Simulation time 159232961 ps
CPU time 0.83 seconds
Started Jul 27 07:42:14 PM PDT 24
Finished Jul 27 07:42:15 PM PDT 24
Peak memory 207084 kb
Host smart-7878ec68-5208-450e-b43c-bef580b2fd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39647
55694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3964755694
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.771955163
Short name T1561
Test name
Test status
Simulation time 205508133 ps
CPU time 0.92 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:16 PM PDT 24
Peak memory 207008 kb
Host smart-f7f75d98-d844-4b6a-b906-3e4a2e245089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77195
5163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.771955163
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.3189207882
Short name T848
Test name
Test status
Simulation time 574826086 ps
CPU time 1.75 seconds
Started Jul 27 07:42:13 PM PDT 24
Finished Jul 27 07:42:14 PM PDT 24
Peak memory 207084 kb
Host smart-e5dd6429-07e8-4d01-8fbd-847212e72793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31892
07882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.3189207882
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.1986336463
Short name T715
Test name
Test status
Simulation time 4693206011 ps
CPU time 47.93 seconds
Started Jul 27 07:42:13 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 207316 kb
Host smart-a296c0cc-23a4-47d0-a06d-90978e9c1501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19863
36463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1986336463
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.1669199411
Short name T2790
Test name
Test status
Simulation time 1466742850 ps
CPU time 33.21 seconds
Started Jul 27 07:42:06 PM PDT 24
Finished Jul 27 07:42:40 PM PDT 24
Peak memory 207296 kb
Host smart-9154a182-b6c8-47c8-a868-9493676ef490
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669199411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.1669199411
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.960135581
Short name T1529
Test name
Test status
Simulation time 43396170 ps
CPU time 0.67 seconds
Started Jul 27 07:42:23 PM PDT 24
Finished Jul 27 07:42:24 PM PDT 24
Peak memory 207120 kb
Host smart-b4ec76fa-4426-4be7-bfa0-364658fbf036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=960135581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.960135581
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3143949781
Short name T1997
Test name
Test status
Simulation time 3734939395 ps
CPU time 5.27 seconds
Started Jul 27 07:42:12 PM PDT 24
Finished Jul 27 07:42:17 PM PDT 24
Peak memory 207380 kb
Host smart-900b7147-513f-4554-a249-c6dbfbb6d8d9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143949781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.3143949781
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.3144055525
Short name T901
Test name
Test status
Simulation time 13327072394 ps
CPU time 14.9 seconds
Started Jul 27 07:42:30 PM PDT 24
Finished Jul 27 07:42:45 PM PDT 24
Peak memory 207288 kb
Host smart-3f610a9e-e9c2-4061-a00f-d6d708f0ebfa
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144055525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.3144055525
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3719569692
Short name T942
Test name
Test status
Simulation time 23361859215 ps
CPU time 28.02 seconds
Started Jul 27 07:42:14 PM PDT 24
Finished Jul 27 07:42:42 PM PDT 24
Peak memory 207424 kb
Host smart-7e1ab69e-0688-408f-aed8-190b5ebd156c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719569692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.3719569692
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3289264239
Short name T2396
Test name
Test status
Simulation time 155317834 ps
CPU time 0.85 seconds
Started Jul 27 07:42:30 PM PDT 24
Finished Jul 27 07:42:31 PM PDT 24
Peak memory 207040 kb
Host smart-5c126f7e-87d5-403b-919b-84971b47b512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32892
64239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3289264239
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.3247761342
Short name T2155
Test name
Test status
Simulation time 154912160 ps
CPU time 0.82 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:16 PM PDT 24
Peak memory 207112 kb
Host smart-415b2f9b-62bf-487f-9497-71a919412e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32477
61342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.3247761342
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.3766736946
Short name T2398
Test name
Test status
Simulation time 351818192 ps
CPU time 1.34 seconds
Started Jul 27 07:42:17 PM PDT 24
Finished Jul 27 07:42:18 PM PDT 24
Peak memory 207108 kb
Host smart-5a8ea4cf-f564-400a-b887-d1376f8f8dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37667
36946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.3766736946
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.249211093
Short name T2826
Test name
Test status
Simulation time 669649055 ps
CPU time 1.87 seconds
Started Jul 27 07:42:16 PM PDT 24
Finished Jul 27 07:42:18 PM PDT 24
Peak memory 207136 kb
Host smart-91ed7d14-3cd3-4e7f-814a-cfa83e38f6a1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=249211093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.249211093
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3960511794
Short name T2592
Test name
Test status
Simulation time 6274456419 ps
CPU time 16.05 seconds
Started Jul 27 07:42:17 PM PDT 24
Finished Jul 27 07:42:34 PM PDT 24
Peak memory 207184 kb
Host smart-336b4f15-b2a6-4494-8a52-a8ede6a99d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39605
11794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3960511794
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.1004937983
Short name T2146
Test name
Test status
Simulation time 853990508 ps
CPU time 19.32 seconds
Started Jul 27 07:42:17 PM PDT 24
Finished Jul 27 07:42:36 PM PDT 24
Peak memory 207328 kb
Host smart-1cefd89e-31b4-417d-bdc0-585ed77caf3f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004937983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.1004937983
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.121454533
Short name T873
Test name
Test status
Simulation time 382733929 ps
CPU time 1.44 seconds
Started Jul 27 07:42:17 PM PDT 24
Finished Jul 27 07:42:19 PM PDT 24
Peak memory 206880 kb
Host smart-0e0a5483-209b-4d8c-8e85-e646162b3bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12145
4533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.121454533
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.648516206
Short name T985
Test name
Test status
Simulation time 178188342 ps
CPU time 0.9 seconds
Started Jul 27 07:42:16 PM PDT 24
Finished Jul 27 07:42:17 PM PDT 24
Peak memory 207164 kb
Host smart-f740861c-b0b2-4e05-9fd7-5def6f2e7bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64851
6206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.648516206
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1392186838
Short name T735
Test name
Test status
Simulation time 49520319 ps
CPU time 0.72 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:15 PM PDT 24
Peak memory 207064 kb
Host smart-3991968f-86ab-48c3-83f4-74374f392e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13921
86838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1392186838
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.134573132
Short name T1238
Test name
Test status
Simulation time 987465266 ps
CPU time 2.62 seconds
Started Jul 27 07:42:18 PM PDT 24
Finished Jul 27 07:42:21 PM PDT 24
Peak memory 207328 kb
Host smart-b50a5ab1-e3a5-419c-8811-865d1009442e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13457
3132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.134573132
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3373132430
Short name T903
Test name
Test status
Simulation time 165909498 ps
CPU time 1.31 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:17 PM PDT 24
Peak memory 207300 kb
Host smart-ea1c4e13-6161-4704-9225-345f84262198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33731
32430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3373132430
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2345118829
Short name T1124
Test name
Test status
Simulation time 191264371 ps
CPU time 1.02 seconds
Started Jul 27 07:42:16 PM PDT 24
Finished Jul 27 07:42:17 PM PDT 24
Peak memory 207276 kb
Host smart-5da60de8-22f9-4813-81ae-19dcabc89d21
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2345118829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2345118829
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2603920207
Short name T1824
Test name
Test status
Simulation time 152604993 ps
CPU time 0.81 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:16 PM PDT 24
Peak memory 207104 kb
Host smart-fa0b6880-3f1f-466e-8088-e10836e67789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26039
20207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2603920207
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.4243028409
Short name T616
Test name
Test status
Simulation time 192444283 ps
CPU time 1 seconds
Started Jul 27 07:42:26 PM PDT 24
Finished Jul 27 07:42:27 PM PDT 24
Peak memory 207072 kb
Host smart-0abb25d7-e544-4ef5-86d3-23a2e1212d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42430
28409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.4243028409
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.90370200
Short name T1557
Test name
Test status
Simulation time 8385678127 ps
CPU time 84.75 seconds
Started Jul 27 07:42:30 PM PDT 24
Finished Jul 27 07:43:55 PM PDT 24
Peak memory 216964 kb
Host smart-c6024b00-733e-42c9-ba7b-65eff6d3d6f9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=90370200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.90370200
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.3535803600
Short name T1401
Test name
Test status
Simulation time 6640513806 ps
CPU time 49.57 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:43:04 PM PDT 24
Peak memory 207348 kb
Host smart-df40ccd6-cf53-44e3-bc34-ea77ec745ce0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3535803600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.3535803600
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.629759759
Short name T787
Test name
Test status
Simulation time 234046982 ps
CPU time 1.02 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:16 PM PDT 24
Peak memory 207220 kb
Host smart-274e8295-3095-449f-8e98-891bf40f5a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62975
9759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.629759759
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.3406591428
Short name T2069
Test name
Test status
Simulation time 23310156655 ps
CPU time 29.94 seconds
Started Jul 27 07:42:26 PM PDT 24
Finished Jul 27 07:42:56 PM PDT 24
Peak memory 207320 kb
Host smart-b9232fe4-9e8f-4f30-9fd1-e35eef1b92c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34065
91428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.3406591428
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.2255559131
Short name T2689
Test name
Test status
Simulation time 3350700592 ps
CPU time 4.91 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:20 PM PDT 24
Peak memory 207280 kb
Host smart-de708140-332c-48e1-b63d-fa0d950d1f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22555
59131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.2255559131
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.1183593976
Short name T1289
Test name
Test status
Simulation time 9000086160 ps
CPU time 267.32 seconds
Started Jul 27 07:42:16 PM PDT 24
Finished Jul 27 07:46:44 PM PDT 24
Peak memory 215628 kb
Host smart-f450aedc-1082-40f1-a101-0039612f8927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11835
93976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.1183593976
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.1726163186
Short name T698
Test name
Test status
Simulation time 5783993440 ps
CPU time 58.03 seconds
Started Jul 27 07:42:26 PM PDT 24
Finished Jul 27 07:43:24 PM PDT 24
Peak memory 207320 kb
Host smart-a725d00d-1008-4d8d-b21c-ddec2da9c6c6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1726163186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.1726163186
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.218822302
Short name T1863
Test name
Test status
Simulation time 243994583 ps
CPU time 0.96 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:16 PM PDT 24
Peak memory 207016 kb
Host smart-c728335c-0857-4f11-a76e-6ce8470557a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=218822302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.218822302
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2051079216
Short name T2235
Test name
Test status
Simulation time 192883911 ps
CPU time 1.01 seconds
Started Jul 27 07:42:15 PM PDT 24
Finished Jul 27 07:42:17 PM PDT 24
Peak memory 207136 kb
Host smart-4196c7a7-e720-4921-8cd7-c78930e705bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20510
79216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2051079216
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.33886730
Short name T882
Test name
Test status
Simulation time 3291598111 ps
CPU time 24.35 seconds
Started Jul 27 07:42:17 PM PDT 24
Finished Jul 27 07:42:41 PM PDT 24
Peak memory 215580 kb
Host smart-b943860d-5a8a-40c2-93b0-739d8971bdb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33886
730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.33886730
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3847598528
Short name T1589
Test name
Test status
Simulation time 5790414086 ps
CPU time 44.05 seconds
Started Jul 27 07:42:30 PM PDT 24
Finished Jul 27 07:43:14 PM PDT 24
Peak memory 216764 kb
Host smart-8b24bc93-db00-495b-a7f1-5653343f3eff
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3847598528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3847598528
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2882355396
Short name T1570
Test name
Test status
Simulation time 163863611 ps
CPU time 0.94 seconds
Started Jul 27 07:42:17 PM PDT 24
Finished Jul 27 07:42:18 PM PDT 24
Peak memory 207168 kb
Host smart-da72913c-6da6-432e-9417-439ed0f4c2f5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2882355396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2882355396
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1027095768
Short name T2474
Test name
Test status
Simulation time 150077924 ps
CPU time 0.85 seconds
Started Jul 27 07:42:30 PM PDT 24
Finished Jul 27 07:42:31 PM PDT 24
Peak memory 207016 kb
Host smart-0235d997-4db5-4541-9be7-7994d24a1572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10270
95768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1027095768
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1224240073
Short name T1804
Test name
Test status
Simulation time 213808584 ps
CPU time 1.03 seconds
Started Jul 27 07:42:25 PM PDT 24
Finished Jul 27 07:42:26 PM PDT 24
Peak memory 207092 kb
Host smart-8710b794-7a27-4510-afe8-9eee46bed962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12242
40073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1224240073
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.463944253
Short name T2009
Test name
Test status
Simulation time 165095474 ps
CPU time 0.95 seconds
Started Jul 27 07:42:16 PM PDT 24
Finished Jul 27 07:42:17 PM PDT 24
Peak memory 207128 kb
Host smart-33c435a2-7548-4d4b-8c53-13b99a022d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46394
4253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.463944253
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2653281456
Short name T1648
Test name
Test status
Simulation time 163279049 ps
CPU time 0.91 seconds
Started Jul 27 07:42:23 PM PDT 24
Finished Jul 27 07:42:24 PM PDT 24
Peak memory 207128 kb
Host smart-0f1ccfd7-d369-4f95-ace5-a8453cf299f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26532
81456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2653281456
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1603529263
Short name T881
Test name
Test status
Simulation time 185387647 ps
CPU time 0.91 seconds
Started Jul 27 07:42:36 PM PDT 24
Finished Jul 27 07:42:37 PM PDT 24
Peak memory 207072 kb
Host smart-5568ac72-f5ef-4c2b-b1f6-2b85d18fde8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16035
29263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1603529263
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.327225502
Short name T2200
Test name
Test status
Simulation time 153359977 ps
CPU time 0.89 seconds
Started Jul 27 07:42:24 PM PDT 24
Finished Jul 27 07:42:25 PM PDT 24
Peak memory 207132 kb
Host smart-0e958a32-05fb-495b-8f00-5073f44f2535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32722
5502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.327225502
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.2551100862
Short name T621
Test name
Test status
Simulation time 253784487 ps
CPU time 1.03 seconds
Started Jul 27 07:42:20 PM PDT 24
Finished Jul 27 07:42:21 PM PDT 24
Peak memory 206988 kb
Host smart-112b99df-0b44-4e2c-ac41-993152e3be1a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2551100862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.2551100862
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.235055554
Short name T1174
Test name
Test status
Simulation time 153613278 ps
CPU time 0.84 seconds
Started Jul 27 07:42:24 PM PDT 24
Finished Jul 27 07:42:25 PM PDT 24
Peak memory 207128 kb
Host smart-9d410f17-4d12-4618-85f9-21f834045616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23505
5554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.235055554
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2034323352
Short name T1176
Test name
Test status
Simulation time 49826827 ps
CPU time 0.69 seconds
Started Jul 27 07:42:22 PM PDT 24
Finished Jul 27 07:42:23 PM PDT 24
Peak memory 207080 kb
Host smart-8ce9e9de-932c-4679-b7f9-af74617f215e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20343
23352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2034323352
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2732501975
Short name T1326
Test name
Test status
Simulation time 15068735286 ps
CPU time 38.07 seconds
Started Jul 27 07:42:21 PM PDT 24
Finished Jul 27 07:42:59 PM PDT 24
Peak memory 215568 kb
Host smart-4e85524e-c1ae-44b3-a116-15756e7cca02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27325
01975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2732501975
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.983932782
Short name T1548
Test name
Test status
Simulation time 166768370 ps
CPU time 0.89 seconds
Started Jul 27 07:42:25 PM PDT 24
Finished Jul 27 07:42:26 PM PDT 24
Peak memory 207012 kb
Host smart-3788b1ba-0a50-4093-ab53-51927fef4dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98393
2782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.983932782
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2267184813
Short name T2806
Test name
Test status
Simulation time 213658665 ps
CPU time 0.98 seconds
Started Jul 27 07:42:22 PM PDT 24
Finished Jul 27 07:42:23 PM PDT 24
Peak memory 207144 kb
Host smart-501c429f-d164-4629-86f7-6af54501dca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22671
84813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2267184813
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.2156319777
Short name T1271
Test name
Test status
Simulation time 227748123 ps
CPU time 1.01 seconds
Started Jul 27 07:42:23 PM PDT 24
Finished Jul 27 07:42:24 PM PDT 24
Peak memory 207196 kb
Host smart-c0d5dafb-0d71-4a7d-8ab3-5cea9719b092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21563
19777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.2156319777
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.900468883
Short name T1655
Test name
Test status
Simulation time 171005033 ps
CPU time 0.86 seconds
Started Jul 27 07:42:37 PM PDT 24
Finished Jul 27 07:42:38 PM PDT 24
Peak memory 206968 kb
Host smart-af4c59d5-42f1-4141-b09b-66e50741d3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90046
8883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.900468883
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3217746082
Short name T2020
Test name
Test status
Simulation time 161630838 ps
CPU time 0.87 seconds
Started Jul 27 07:42:24 PM PDT 24
Finished Jul 27 07:42:25 PM PDT 24
Peak memory 207132 kb
Host smart-41229251-12c5-453c-9d27-a6d8028eb4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32177
46082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3217746082
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3633074326
Short name T855
Test name
Test status
Simulation time 178751227 ps
CPU time 0.88 seconds
Started Jul 27 07:42:23 PM PDT 24
Finished Jul 27 07:42:24 PM PDT 24
Peak memory 207088 kb
Host smart-ab40f5e7-37b0-44d7-b308-e4e83e1a0a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36330
74326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3633074326
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.8650550
Short name T431
Test name
Test status
Simulation time 188472562 ps
CPU time 0.9 seconds
Started Jul 27 07:42:21 PM PDT 24
Finished Jul 27 07:42:22 PM PDT 24
Peak memory 207084 kb
Host smart-bc0ccfb4-e101-4697-8704-cbbf32f8e1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86505
50 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.8650550
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.148743035
Short name T2513
Test name
Test status
Simulation time 208367733 ps
CPU time 1.03 seconds
Started Jul 27 07:42:21 PM PDT 24
Finished Jul 27 07:42:22 PM PDT 24
Peak memory 207072 kb
Host smart-e3455ef3-b5ea-490e-97a9-8724b8f63622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14874
3035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.148743035
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.2768327132
Short name T1417
Test name
Test status
Simulation time 4793871331 ps
CPU time 132.05 seconds
Started Jul 27 07:42:22 PM PDT 24
Finished Jul 27 07:44:34 PM PDT 24
Peak memory 215580 kb
Host smart-5dac6296-58cb-49db-95db-e4a068846dd3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2768327132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.2768327132
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.996771959
Short name T571
Test name
Test status
Simulation time 207552581 ps
CPU time 0.94 seconds
Started Jul 27 07:42:22 PM PDT 24
Finished Jul 27 07:42:23 PM PDT 24
Peak memory 207136 kb
Host smart-9542178d-4cda-4904-a9a7-c2ae455d4cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99677
1959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.996771959
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2756924086
Short name T534
Test name
Test status
Simulation time 159630957 ps
CPU time 0.85 seconds
Started Jul 27 07:42:22 PM PDT 24
Finished Jul 27 07:42:23 PM PDT 24
Peak memory 207124 kb
Host smart-f1dccc54-7bec-45f8-8c5c-295c65c6c325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27569
24086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2756924086
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.1736190855
Short name T1327
Test name
Test status
Simulation time 1363047171 ps
CPU time 3.27 seconds
Started Jul 27 07:42:25 PM PDT 24
Finished Jul 27 07:42:28 PM PDT 24
Peak memory 207300 kb
Host smart-49d60734-93cb-410b-a33c-08373c90016d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17361
90855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.1736190855
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3683644003
Short name T2431
Test name
Test status
Simulation time 5913919961 ps
CPU time 176.73 seconds
Started Jul 27 07:42:37 PM PDT 24
Finished Jul 27 07:45:34 PM PDT 24
Peak memory 215532 kb
Host smart-8fd75059-8850-42f5-b886-705ac0296a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36836
44003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3683644003
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.4197346709
Short name T358
Test name
Test status
Simulation time 5627636378 ps
CPU time 37.15 seconds
Started Jul 27 07:42:30 PM PDT 24
Finished Jul 27 07:43:07 PM PDT 24
Peak memory 207256 kb
Host smart-699914c3-934e-400e-834b-657554388d6f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197346709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.4197346709
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.1948634941
Short name T2041
Test name
Test status
Simulation time 39189462 ps
CPU time 0.64 seconds
Started Jul 27 07:42:29 PM PDT 24
Finished Jul 27 07:42:30 PM PDT 24
Peak memory 207148 kb
Host smart-d2c88c00-f595-4ea7-aba9-0c4469b9b866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1948634941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.1948634941
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.4056722391
Short name T2555
Test name
Test status
Simulation time 3490570533 ps
CPU time 5.51 seconds
Started Jul 27 07:42:24 PM PDT 24
Finished Jul 27 07:42:29 PM PDT 24
Peak memory 207328 kb
Host smart-25ddc12e-7902-45d1-a5a5-5508e70aeb98
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056722391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.4056722391
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.3181624361
Short name T760
Test name
Test status
Simulation time 13368262821 ps
CPU time 19.3 seconds
Started Jul 27 07:42:36 PM PDT 24
Finished Jul 27 07:42:56 PM PDT 24
Peak memory 207336 kb
Host smart-477e28b3-7d5f-464c-977f-c5e18c0242d5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181624361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3181624361
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.786424187
Short name T2482
Test name
Test status
Simulation time 23358561960 ps
CPU time 28.02 seconds
Started Jul 27 07:42:25 PM PDT 24
Finished Jul 27 07:42:53 PM PDT 24
Peak memory 207364 kb
Host smart-6fc78ad0-213c-4d1f-ae89-42c1a028ea65
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786424187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_ao
n_wake_resume.786424187
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2452141733
Short name T1243
Test name
Test status
Simulation time 166358196 ps
CPU time 0.94 seconds
Started Jul 27 07:42:25 PM PDT 24
Finished Jul 27 07:42:26 PM PDT 24
Peak memory 207148 kb
Host smart-76cc943b-8c84-4ebd-a475-cdd4839a2f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24521
41733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2452141733
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3061674582
Short name T2759
Test name
Test status
Simulation time 153462504 ps
CPU time 0.86 seconds
Started Jul 27 07:42:26 PM PDT 24
Finished Jul 27 07:42:27 PM PDT 24
Peak memory 207040 kb
Host smart-dc4920a1-c535-403d-9373-30be3b2e1422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30616
74582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3061674582
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.2317924886
Short name T876
Test name
Test status
Simulation time 317237582 ps
CPU time 1.25 seconds
Started Jul 27 07:42:25 PM PDT 24
Finished Jul 27 07:42:27 PM PDT 24
Peak memory 207008 kb
Host smart-2d3eb423-4525-4fc9-9624-7a5ad9176a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23179
24886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.2317924886
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2155485806
Short name T2045
Test name
Test status
Simulation time 489212680 ps
CPU time 1.52 seconds
Started Jul 27 07:42:24 PM PDT 24
Finished Jul 27 07:42:26 PM PDT 24
Peak memory 207084 kb
Host smart-5264afc7-2cc9-42be-bdfc-c737577f096a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2155485806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2155485806
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.3579848548
Short name T1275
Test name
Test status
Simulation time 3837903357 ps
CPU time 34.92 seconds
Started Jul 27 07:42:25 PM PDT 24
Finished Jul 27 07:43:00 PM PDT 24
Peak memory 207328 kb
Host smart-dcbb1b64-6cc3-468e-8ad6-90434607ab31
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579848548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.3579848548
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.173551911
Short name T2776
Test name
Test status
Simulation time 402030584 ps
CPU time 1.44 seconds
Started Jul 27 07:42:22 PM PDT 24
Finished Jul 27 07:42:24 PM PDT 24
Peak memory 207080 kb
Host smart-c153f315-47f7-482d-8be1-a4af3af0549a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17355
1911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.173551911
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.2188405111
Short name T2642
Test name
Test status
Simulation time 141954945 ps
CPU time 0.92 seconds
Started Jul 27 07:42:22 PM PDT 24
Finished Jul 27 07:42:23 PM PDT 24
Peak memory 207072 kb
Host smart-9ce32581-67eb-4f59-a08c-aec3f75f1ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21884
05111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.2188405111
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2696291935
Short name T1466
Test name
Test status
Simulation time 72842419 ps
CPU time 0.74 seconds
Started Jul 27 07:42:26 PM PDT 24
Finished Jul 27 07:42:27 PM PDT 24
Peak memory 207036 kb
Host smart-b9cae267-993c-4d44-9fa1-47a128596b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26962
91935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2696291935
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.3043463210
Short name T1639
Test name
Test status
Simulation time 952238183 ps
CPU time 2.4 seconds
Started Jul 27 07:42:37 PM PDT 24
Finished Jul 27 07:42:39 PM PDT 24
Peak memory 207164 kb
Host smart-282044d9-ab9b-4df4-98d4-54acfff29140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30434
63210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.3043463210
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.4140781772
Short name T944
Test name
Test status
Simulation time 171642439 ps
CPU time 1.75 seconds
Started Jul 27 07:42:24 PM PDT 24
Finished Jul 27 07:42:25 PM PDT 24
Peak memory 207240 kb
Host smart-1c7c0915-0333-4c5b-ad79-a761787ef435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41407
81772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.4140781772
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2665176054
Short name T2590
Test name
Test status
Simulation time 233401243 ps
CPU time 1.01 seconds
Started Jul 27 07:42:25 PM PDT 24
Finished Jul 27 07:42:26 PM PDT 24
Peak memory 215472 kb
Host smart-1c896910-1bea-4d68-80ac-8ff1018f6853
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2665176054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2665176054
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3892079311
Short name T2327
Test name
Test status
Simulation time 152149637 ps
CPU time 0.83 seconds
Started Jul 27 07:42:25 PM PDT 24
Finished Jul 27 07:42:26 PM PDT 24
Peak memory 207112 kb
Host smart-4f9b1968-2bb5-474b-aee3-e1bdced8c2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38920
79311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3892079311
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.110922659
Short name T1601
Test name
Test status
Simulation time 231476685 ps
CPU time 1.05 seconds
Started Jul 27 07:42:23 PM PDT 24
Finished Jul 27 07:42:24 PM PDT 24
Peak memory 207084 kb
Host smart-377560d1-baf2-4496-ba22-b5a106fa5aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11092
2659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.110922659
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.3392686228
Short name T2558
Test name
Test status
Simulation time 7491064413 ps
CPU time 220.14 seconds
Started Jul 27 07:42:25 PM PDT 24
Finished Jul 27 07:46:05 PM PDT 24
Peak memory 215468 kb
Host smart-37519b73-2b5c-4ea3-a75d-1bf8a389d7ee
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3392686228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.3392686228
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.996091747
Short name T918
Test name
Test status
Simulation time 178913301 ps
CPU time 0.94 seconds
Started Jul 27 07:42:27 PM PDT 24
Finished Jul 27 07:42:28 PM PDT 24
Peak memory 207068 kb
Host smart-ae7494dc-f268-4781-898f-d47df6fb4f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99609
1747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.996091747
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.631623006
Short name T2187
Test name
Test status
Simulation time 23339788845 ps
CPU time 29.81 seconds
Started Jul 27 07:42:37 PM PDT 24
Finished Jul 27 07:43:07 PM PDT 24
Peak memory 207296 kb
Host smart-840f2638-9ad1-4e4a-a9f7-00395ed0d414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63162
3006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.631623006
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2976377129
Short name T1985
Test name
Test status
Simulation time 3315027125 ps
CPU time 4.82 seconds
Started Jul 27 07:42:22 PM PDT 24
Finished Jul 27 07:42:27 PM PDT 24
Peak memory 207356 kb
Host smart-276de256-febc-408d-8eda-785e0e96ef5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29763
77129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2976377129
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.591338728
Short name T2298
Test name
Test status
Simulation time 7357765789 ps
CPU time 71.44 seconds
Started Jul 27 07:42:30 PM PDT 24
Finished Jul 27 07:43:42 PM PDT 24
Peak memory 223792 kb
Host smart-4a0cbef7-3c94-43d0-a5c5-879d4242d017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59133
8728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.591338728
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3824975726
Short name T389
Test name
Test status
Simulation time 6866662259 ps
CPU time 51.27 seconds
Started Jul 27 07:42:28 PM PDT 24
Finished Jul 27 07:43:19 PM PDT 24
Peak memory 207384 kb
Host smart-a3d21a35-c867-451b-a5eb-c455c984f059
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3824975726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3824975726
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.243250166
Short name T1034
Test name
Test status
Simulation time 267054690 ps
CPU time 0.99 seconds
Started Jul 27 07:42:34 PM PDT 24
Finished Jul 27 07:42:35 PM PDT 24
Peak memory 207052 kb
Host smart-6da9cfa7-849f-4b7a-a99b-54e691d60b83
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=243250166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.243250166
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3496491452
Short name T1493
Test name
Test status
Simulation time 185945106 ps
CPU time 0.92 seconds
Started Jul 27 07:42:31 PM PDT 24
Finished Jul 27 07:42:32 PM PDT 24
Peak memory 207100 kb
Host smart-95bb5c0c-ec84-4c4d-901a-30a468e4c70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34964
91452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3496491452
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3646204675
Short name T1301
Test name
Test status
Simulation time 5268565879 ps
CPU time 53.94 seconds
Started Jul 27 07:42:31 PM PDT 24
Finished Jul 27 07:43:25 PM PDT 24
Peak memory 215584 kb
Host smart-920f48cf-957a-4b63-bb5e-1a659a0bfe2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36462
04675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3646204675
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.331954812
Short name T1267
Test name
Test status
Simulation time 7474538549 ps
CPU time 227.1 seconds
Started Jul 27 07:42:33 PM PDT 24
Finished Jul 27 07:46:21 PM PDT 24
Peak memory 215532 kb
Host smart-c156c1c0-9392-4e4f-9e94-bec0d9ef3fde
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=331954812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.331954812
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.3311398228
Short name T525
Test name
Test status
Simulation time 155745884 ps
CPU time 0.88 seconds
Started Jul 27 07:42:30 PM PDT 24
Finished Jul 27 07:42:31 PM PDT 24
Peak memory 207164 kb
Host smart-296b280f-f17c-4476-893b-995aebd18812
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3311398228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.3311398228
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2099861660
Short name T2616
Test name
Test status
Simulation time 145150120 ps
CPU time 0.84 seconds
Started Jul 27 07:42:29 PM PDT 24
Finished Jul 27 07:42:30 PM PDT 24
Peak memory 207164 kb
Host smart-37e78c2e-1614-484e-b041-6e085e0f11a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20998
61660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2099861660
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2324807402
Short name T125
Test name
Test status
Simulation time 207025966 ps
CPU time 0.99 seconds
Started Jul 27 07:42:34 PM PDT 24
Finished Jul 27 07:42:35 PM PDT 24
Peak memory 207048 kb
Host smart-cce89bf1-8da5-4717-80c6-59998ff828da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23248
07402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2324807402
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3906021556
Short name T2697
Test name
Test status
Simulation time 180749346 ps
CPU time 0.94 seconds
Started Jul 27 07:42:28 PM PDT 24
Finished Jul 27 07:42:29 PM PDT 24
Peak memory 207064 kb
Host smart-e9bbed4c-9ac0-4553-b5c0-ae7c189425a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39060
21556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3906021556
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3386739448
Short name T1358
Test name
Test status
Simulation time 165740672 ps
CPU time 0.92 seconds
Started Jul 27 07:42:27 PM PDT 24
Finished Jul 27 07:42:28 PM PDT 24
Peak memory 207164 kb
Host smart-d6ab1946-dd9e-4df4-992b-9d3cd0b12e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33867
39448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3386739448
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1222226077
Short name T293
Test name
Test status
Simulation time 154765527 ps
CPU time 0.82 seconds
Started Jul 27 07:42:39 PM PDT 24
Finished Jul 27 07:42:40 PM PDT 24
Peak memory 207136 kb
Host smart-739683f5-9449-46c0-9309-49d30db1a4ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12222
26077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1222226077
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3330240196
Short name T895
Test name
Test status
Simulation time 159881848 ps
CPU time 0.84 seconds
Started Jul 27 07:42:38 PM PDT 24
Finished Jul 27 07:42:39 PM PDT 24
Peak memory 207128 kb
Host smart-52086413-ea62-4ead-9018-529b61e02060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33302
40196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3330240196
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.2623600515
Short name T2261
Test name
Test status
Simulation time 233228055 ps
CPU time 1.03 seconds
Started Jul 27 07:42:37 PM PDT 24
Finished Jul 27 07:42:39 PM PDT 24
Peak memory 207156 kb
Host smart-dd4f0652-2759-46e9-b5e9-d01c9c7541f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2623600515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.2623600515
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1940010164
Short name T837
Test name
Test status
Simulation time 154767306 ps
CPU time 0.85 seconds
Started Jul 27 07:42:32 PM PDT 24
Finished Jul 27 07:42:33 PM PDT 24
Peak memory 207132 kb
Host smart-3c4181ec-200e-4e17-8f0a-dc1ad0948841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19400
10164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1940010164
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.553476148
Short name T1635
Test name
Test status
Simulation time 48284024 ps
CPU time 0.72 seconds
Started Jul 27 07:42:28 PM PDT 24
Finished Jul 27 07:42:29 PM PDT 24
Peak memory 207028 kb
Host smart-6b668d82-761a-4ef6-82cd-3b7cfe2b60d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55347
6148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.553476148
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2163902919
Short name T1742
Test name
Test status
Simulation time 7353836569 ps
CPU time 17.38 seconds
Started Jul 27 07:42:37 PM PDT 24
Finished Jul 27 07:42:55 PM PDT 24
Peak memory 219772 kb
Host smart-48289af6-28ab-4c7f-a9aa-cc7d797a33c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21639
02919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2163902919
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1716379890
Short name T1952
Test name
Test status
Simulation time 186369572 ps
CPU time 0.94 seconds
Started Jul 27 07:42:27 PM PDT 24
Finished Jul 27 07:42:28 PM PDT 24
Peak memory 207016 kb
Host smart-dd203667-dd8b-4808-baf4-c1957a9684a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17163
79890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1716379890
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2864498860
Short name T894
Test name
Test status
Simulation time 214411353 ps
CPU time 0.98 seconds
Started Jul 27 07:42:31 PM PDT 24
Finished Jul 27 07:42:32 PM PDT 24
Peak memory 207088 kb
Host smart-16ea3bfd-fd8d-4346-9b80-8a3bae218db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28644
98860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2864498860
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.297408374
Short name T2645
Test name
Test status
Simulation time 173033979 ps
CPU time 0.89 seconds
Started Jul 27 07:42:32 PM PDT 24
Finished Jul 27 07:42:34 PM PDT 24
Peak memory 207096 kb
Host smart-cace305b-3915-4d9a-a6d8-352cb1baf1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29740
8374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.297408374
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3507736140
Short name T1963
Test name
Test status
Simulation time 170971598 ps
CPU time 0.9 seconds
Started Jul 27 07:42:28 PM PDT 24
Finished Jul 27 07:42:29 PM PDT 24
Peak memory 207200 kb
Host smart-291004c7-45fe-4842-91a7-1afcf6d09d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35077
36140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3507736140
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.657529162
Short name T67
Test name
Test status
Simulation time 155738669 ps
CPU time 0.84 seconds
Started Jul 27 07:42:32 PM PDT 24
Finished Jul 27 07:42:33 PM PDT 24
Peak memory 207076 kb
Host smart-559790de-321d-4c9c-bc78-f8ad0d546672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65752
9162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.657529162
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2763807366
Short name T764
Test name
Test status
Simulation time 159583570 ps
CPU time 0.88 seconds
Started Jul 27 07:42:33 PM PDT 24
Finished Jul 27 07:42:34 PM PDT 24
Peak memory 207064 kb
Host smart-a0d96c39-a583-414e-8fae-0413ab5d7177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27638
07366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2763807366
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2145002768
Short name T1102
Test name
Test status
Simulation time 181242192 ps
CPU time 0.86 seconds
Started Jul 27 07:42:34 PM PDT 24
Finished Jul 27 07:42:35 PM PDT 24
Peak memory 207092 kb
Host smart-5dee6b1e-5a2e-4f0c-a7b7-ff0b26aef479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21450
02768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2145002768
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.622852767
Short name T1458
Test name
Test status
Simulation time 264843422 ps
CPU time 1.13 seconds
Started Jul 27 07:42:32 PM PDT 24
Finished Jul 27 07:42:34 PM PDT 24
Peak memory 207096 kb
Host smart-063a51a2-85dc-469b-b246-c8e4dc8e3d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62285
2767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.622852767
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.622710455
Short name T587
Test name
Test status
Simulation time 3796012939 ps
CPU time 37.69 seconds
Started Jul 27 07:42:29 PM PDT 24
Finished Jul 27 07:43:07 PM PDT 24
Peak memory 215816 kb
Host smart-e2c0dc41-732a-4413-8359-7127916d4cb7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=622710455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.622710455
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1178571157
Short name T2507
Test name
Test status
Simulation time 207754163 ps
CPU time 0.9 seconds
Started Jul 27 07:42:32 PM PDT 24
Finished Jul 27 07:42:33 PM PDT 24
Peak memory 207164 kb
Host smart-81582899-ebe7-4e6e-973e-809edc3386b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11785
71157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1178571157
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.659453462
Short name T583
Test name
Test status
Simulation time 163193337 ps
CPU time 0.88 seconds
Started Jul 27 07:42:27 PM PDT 24
Finished Jul 27 07:42:28 PM PDT 24
Peak memory 207128 kb
Host smart-2f06a2ba-74ea-4853-86a6-7c4d016aefff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65945
3462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.659453462
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2077987786
Short name T661
Test name
Test status
Simulation time 649434162 ps
CPU time 1.84 seconds
Started Jul 27 07:42:31 PM PDT 24
Finished Jul 27 07:42:33 PM PDT 24
Peak memory 207088 kb
Host smart-fd32ce9f-29b2-4293-9107-81d5fdaa6fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20779
87786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2077987786
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.1274711092
Short name T2775
Test name
Test status
Simulation time 5236261118 ps
CPU time 158.15 seconds
Started Jul 27 07:42:29 PM PDT 24
Finished Jul 27 07:45:07 PM PDT 24
Peak memory 215580 kb
Host smart-d48b2c63-abf4-4352-bd1a-89061116fb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12747
11092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1274711092
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.913522681
Short name T589
Test name
Test status
Simulation time 1173983266 ps
CPU time 25.76 seconds
Started Jul 27 07:42:25 PM PDT 24
Finished Jul 27 07:42:51 PM PDT 24
Peak memory 207328 kb
Host smart-61269def-c871-474b-ba71-734d3bb6f9ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913522681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_host
_handshake.913522681
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.3424436203
Short name T2080
Test name
Test status
Simulation time 59032573 ps
CPU time 0.7 seconds
Started Jul 27 07:42:50 PM PDT 24
Finished Jul 27 07:42:50 PM PDT 24
Peak memory 207140 kb
Host smart-b5d09741-6d33-4d85-a25b-d549664b14d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3424436203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3424436203
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.2142105789
Short name T2451
Test name
Test status
Simulation time 4053814723 ps
CPU time 6.79 seconds
Started Jul 27 07:42:33 PM PDT 24
Finished Jul 27 07:42:40 PM PDT 24
Peak memory 207368 kb
Host smart-b19d1e08-6a95-4bdf-85e1-caaca609db1b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142105789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.2142105789
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.378307558
Short name T2239
Test name
Test status
Simulation time 13404794573 ps
CPU time 16.37 seconds
Started Jul 27 07:42:31 PM PDT 24
Finished Jul 27 07:42:47 PM PDT 24
Peak memory 207392 kb
Host smart-3f8f8771-20bf-44a4-9fee-16d0520ab84e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=378307558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.378307558
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1060284592
Short name T1228
Test name
Test status
Simulation time 23380500753 ps
CPU time 32.43 seconds
Started Jul 27 07:42:38 PM PDT 24
Finished Jul 27 07:43:10 PM PDT 24
Peak memory 207388 kb
Host smart-a4a95895-647b-4438-abcb-7a56123c5c23
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060284592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.1060284592
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.963580457
Short name T1368
Test name
Test status
Simulation time 151597938 ps
CPU time 0.84 seconds
Started Jul 27 07:42:28 PM PDT 24
Finished Jul 27 07:42:29 PM PDT 24
Peak memory 207032 kb
Host smart-096ecb5b-cb31-4ac6-adb1-f86f55489bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96358
0457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.963580457
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3784331688
Short name T1426
Test name
Test status
Simulation time 145509896 ps
CPU time 0.82 seconds
Started Jul 27 07:42:27 PM PDT 24
Finished Jul 27 07:42:28 PM PDT 24
Peak memory 207176 kb
Host smart-9fec18a6-c2a3-4e2f-8214-5755f6c38a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37843
31688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3784331688
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.3439687521
Short name T2671
Test name
Test status
Simulation time 347091157 ps
CPU time 1.38 seconds
Started Jul 27 07:42:36 PM PDT 24
Finished Jul 27 07:42:38 PM PDT 24
Peak memory 207068 kb
Host smart-ee2951d4-de31-4715-9b82-3622ff92dadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34396
87521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.3439687521
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.380328554
Short name T1703
Test name
Test status
Simulation time 1289320933 ps
CPU time 3.28 seconds
Started Jul 27 07:42:41 PM PDT 24
Finished Jul 27 07:42:44 PM PDT 24
Peak memory 207312 kb
Host smart-08a303b3-e1cb-42fe-ab99-65fc7eafd3ca
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=380328554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.380328554
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.3202257482
Short name T296
Test name
Test status
Simulation time 21731040020 ps
CPU time 50.15 seconds
Started Jul 27 07:42:41 PM PDT 24
Finished Jul 27 07:43:31 PM PDT 24
Peak memory 207328 kb
Host smart-48ca9fc1-c9fc-4090-b1ad-dc276b61b2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32022
57482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.3202257482
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.1154188872
Short name T416
Test name
Test status
Simulation time 635227820 ps
CPU time 5.37 seconds
Started Jul 27 07:42:38 PM PDT 24
Finished Jul 27 07:42:44 PM PDT 24
Peak memory 207336 kb
Host smart-62866b26-d45f-4163-9032-15c37427dd49
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154188872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.1154188872
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.890023159
Short name T833
Test name
Test status
Simulation time 425072810 ps
CPU time 1.48 seconds
Started Jul 27 07:42:39 PM PDT 24
Finished Jul 27 07:42:41 PM PDT 24
Peak memory 207064 kb
Host smart-081d4501-ca97-4abc-a35b-c5aa6f070d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89002
3159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.890023159
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.4037376698
Short name T220
Test name
Test status
Simulation time 151511761 ps
CPU time 0.84 seconds
Started Jul 27 07:42:37 PM PDT 24
Finished Jul 27 07:42:38 PM PDT 24
Peak memory 207104 kb
Host smart-aef01f87-68c0-48af-b5eb-a86d06309b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373
76698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.4037376698
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.3150845985
Short name T1090
Test name
Test status
Simulation time 36878221 ps
CPU time 0.69 seconds
Started Jul 27 07:42:39 PM PDT 24
Finished Jul 27 07:42:40 PM PDT 24
Peak memory 207292 kb
Host smart-0049aaca-d087-4430-aca0-d55f35d37291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31508
45985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3150845985
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1241106929
Short name T1873
Test name
Test status
Simulation time 962277709 ps
CPU time 2.65 seconds
Started Jul 27 07:42:42 PM PDT 24
Finished Jul 27 07:42:44 PM PDT 24
Peak memory 207404 kb
Host smart-0896aefe-872f-41c2-a7e5-fcca71b1f7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12411
06929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1241106929
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.31929429
Short name T192
Test name
Test status
Simulation time 233112581 ps
CPU time 1.84 seconds
Started Jul 27 07:42:37 PM PDT 24
Finished Jul 27 07:42:39 PM PDT 24
Peak memory 207280 kb
Host smart-8e7a3281-3251-4c87-af5b-42f408a9d6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31929
429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.31929429
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.4199102707
Short name T2596
Test name
Test status
Simulation time 249292019 ps
CPU time 1.19 seconds
Started Jul 27 07:42:36 PM PDT 24
Finished Jul 27 07:42:37 PM PDT 24
Peak memory 215516 kb
Host smart-27834be6-805e-44a5-b6e5-78f38d53c3bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4199102707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.4199102707
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3226323644
Short name T1728
Test name
Test status
Simulation time 141972589 ps
CPU time 0.8 seconds
Started Jul 27 07:42:36 PM PDT 24
Finished Jul 27 07:42:37 PM PDT 24
Peak memory 207072 kb
Host smart-fc53fdee-5cf5-44cf-b94d-1e671b6092bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32263
23644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3226323644
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.902488726
Short name T1073
Test name
Test status
Simulation time 196351869 ps
CPU time 0.94 seconds
Started Jul 27 07:42:40 PM PDT 24
Finished Jul 27 07:42:41 PM PDT 24
Peak memory 207132 kb
Host smart-2a84454a-31dc-46dd-aac7-703391fffc97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90248
8726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.902488726
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.407831156
Short name T482
Test name
Test status
Simulation time 9626841713 ps
CPU time 74.06 seconds
Started Jul 27 07:42:38 PM PDT 24
Finished Jul 27 07:43:52 PM PDT 24
Peak memory 217080 kb
Host smart-c52a74b7-c686-4f13-bc87-7921c2343ecc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=407831156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.407831156
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.3253721679
Short name T774
Test name
Test status
Simulation time 5872202984 ps
CPU time 68.16 seconds
Started Jul 27 07:42:36 PM PDT 24
Finished Jul 27 07:43:44 PM PDT 24
Peak memory 207380 kb
Host smart-c9c7a125-26b0-46b5-a0e6-24280651b438
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3253721679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.3253721679
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1811782240
Short name T1217
Test name
Test status
Simulation time 200448359 ps
CPU time 0.93 seconds
Started Jul 27 07:42:39 PM PDT 24
Finished Jul 27 07:42:40 PM PDT 24
Peak memory 207100 kb
Host smart-eb2a5707-9063-4ad8-8060-6af6ae4f4c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18117
82240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1811782240
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2050474857
Short name T943
Test name
Test status
Simulation time 23325124391 ps
CPU time 28.06 seconds
Started Jul 27 07:42:39 PM PDT 24
Finished Jul 27 07:43:08 PM PDT 24
Peak memory 207568 kb
Host smart-3ae09ff9-f6f4-4a64-bb5e-32977368ed3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20504
74857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2050474857
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3815260891
Short name T503
Test name
Test status
Simulation time 3341991820 ps
CPU time 5.04 seconds
Started Jul 27 07:42:37 PM PDT 24
Finished Jul 27 07:42:42 PM PDT 24
Peak memory 207312 kb
Host smart-1b160c7a-55a5-4ce8-9318-9c30d840ebc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38152
60891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3815260891
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.1985649506
Short name T1482
Test name
Test status
Simulation time 7424445027 ps
CPU time 224.23 seconds
Started Jul 27 07:42:36 PM PDT 24
Finished Jul 27 07:46:20 PM PDT 24
Peak memory 215624 kb
Host smart-65d8cdd5-f392-45b7-b284-edcb886ce6ae
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1985649506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.1985649506
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.795416336
Short name T730
Test name
Test status
Simulation time 237814523 ps
CPU time 0.96 seconds
Started Jul 27 07:42:38 PM PDT 24
Finished Jul 27 07:42:39 PM PDT 24
Peak memory 207024 kb
Host smart-d764c557-64ad-4e66-912b-2e565213c3ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=795416336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.795416336
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1008637732
Short name T636
Test name
Test status
Simulation time 190832524 ps
CPU time 0.99 seconds
Started Jul 27 07:42:41 PM PDT 24
Finished Jul 27 07:42:42 PM PDT 24
Peak memory 207100 kb
Host smart-59979ed6-5693-4991-b7ff-7a2fbad73820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10086
37732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1008637732
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.594470846
Short name T2309
Test name
Test status
Simulation time 5988041706 ps
CPU time 61.03 seconds
Started Jul 27 07:42:42 PM PDT 24
Finished Jul 27 07:43:44 PM PDT 24
Peak memory 215628 kb
Host smart-61b75549-481c-46dd-881b-a61b9cfd975a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59447
0846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.594470846
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.2336130786
Short name T2243
Test name
Test status
Simulation time 5499919021 ps
CPU time 46.06 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:43:33 PM PDT 24
Peak memory 207368 kb
Host smart-70ca004c-0c46-4ac9-af1d-a14b0139ee16
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2336130786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.2336130786
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3161774651
Short name T1227
Test name
Test status
Simulation time 154849264 ps
CPU time 0.82 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:42:48 PM PDT 24
Peak memory 207128 kb
Host smart-866b5618-f4ee-4c64-b649-ec5d6bc9d125
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3161774651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3161774651
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2432256552
Short name T2334
Test name
Test status
Simulation time 147179862 ps
CPU time 0.85 seconds
Started Jul 27 07:42:48 PM PDT 24
Finished Jul 27 07:42:49 PM PDT 24
Peak memory 207160 kb
Host smart-40b9ad92-2c10-4301-8d3d-0f78525c6b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24322
56552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2432256552
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3024286565
Short name T122
Test name
Test status
Simulation time 211204754 ps
CPU time 0.99 seconds
Started Jul 27 07:42:48 PM PDT 24
Finished Jul 27 07:42:49 PM PDT 24
Peak memory 207136 kb
Host smart-2d9df9a9-c8f3-495f-913d-9a6541140691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30242
86565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3024286565
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.2440890701
Short name T841
Test name
Test status
Simulation time 256088525 ps
CPU time 0.98 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:42:49 PM PDT 24
Peak memory 207100 kb
Host smart-8f25a596-2228-4004-94e8-af94c9d0ad04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24408
90701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.2440890701
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.92827691
Short name T969
Test name
Test status
Simulation time 156007731 ps
CPU time 0.87 seconds
Started Jul 27 07:42:49 PM PDT 24
Finished Jul 27 07:42:50 PM PDT 24
Peak memory 207216 kb
Host smart-d970594e-0c53-442f-a910-b092440066c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92827
691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.92827691
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.267980484
Short name T511
Test name
Test status
Simulation time 181457134 ps
CPU time 0.91 seconds
Started Jul 27 07:42:46 PM PDT 24
Finished Jul 27 07:42:47 PM PDT 24
Peak memory 207096 kb
Host smart-b5a5f358-8b5b-4c71-b70b-c26bc9c0e279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26798
0484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.267980484
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2593483282
Short name T755
Test name
Test status
Simulation time 156637252 ps
CPU time 0.88 seconds
Started Jul 27 07:42:52 PM PDT 24
Finished Jul 27 07:42:53 PM PDT 24
Peak memory 207072 kb
Host smart-eff88c6f-26c9-4141-b3ff-fedcab6ebe7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25934
83282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2593483282
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.823780083
Short name T643
Test name
Test status
Simulation time 225390913 ps
CPU time 0.98 seconds
Started Jul 27 07:42:46 PM PDT 24
Finished Jul 27 07:42:48 PM PDT 24
Peak memory 207096 kb
Host smart-3c8039e8-5eee-4905-aea8-17ecfd54be87
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=823780083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.823780083
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3381353260
Short name T980
Test name
Test status
Simulation time 149080630 ps
CPU time 0.82 seconds
Started Jul 27 07:42:46 PM PDT 24
Finished Jul 27 07:42:47 PM PDT 24
Peak memory 207128 kb
Host smart-20442e8e-db00-4dee-8324-883a86c56875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33813
53260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3381353260
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.926513103
Short name T1103
Test name
Test status
Simulation time 52583049 ps
CPU time 0.74 seconds
Started Jul 27 07:42:50 PM PDT 24
Finished Jul 27 07:42:51 PM PDT 24
Peak memory 207080 kb
Host smart-7018192c-fcdd-4a5b-95f2-42bc142294d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92651
3103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.926513103
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3852597830
Short name T809
Test name
Test status
Simulation time 7084526007 ps
CPU time 16.71 seconds
Started Jul 27 07:42:46 PM PDT 24
Finished Jul 27 07:43:03 PM PDT 24
Peak memory 215584 kb
Host smart-7a4f80d7-6d90-4656-a39d-23bcdcd6e977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38525
97830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3852597830
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2781681610
Short name T1860
Test name
Test status
Simulation time 150242241 ps
CPU time 0.86 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:42:48 PM PDT 24
Peak memory 207132 kb
Host smart-acf6a064-1974-4cfb-a0af-10c9fec26f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27816
81610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2781681610
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.887762480
Short name T1091
Test name
Test status
Simulation time 241345972 ps
CPU time 0.93 seconds
Started Jul 27 07:42:49 PM PDT 24
Finished Jul 27 07:42:50 PM PDT 24
Peak memory 207348 kb
Host smart-3a283892-8135-4333-965a-58f121629c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88776
2480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.887762480
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.1513466660
Short name T2283
Test name
Test status
Simulation time 199249003 ps
CPU time 0.98 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:42:48 PM PDT 24
Peak memory 207136 kb
Host smart-4549f818-c2bd-4b3d-a2cf-c9f8f954b5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15134
66660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.1513466660
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.4021638041
Short name T1919
Test name
Test status
Simulation time 184482085 ps
CPU time 0.9 seconds
Started Jul 27 07:42:50 PM PDT 24
Finished Jul 27 07:42:51 PM PDT 24
Peak memory 207100 kb
Host smart-706275fc-f43a-4b9b-af29-527821772f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40216
38041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.4021638041
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.1181177927
Short name T2257
Test name
Test status
Simulation time 145971756 ps
CPU time 0.87 seconds
Started Jul 27 07:42:50 PM PDT 24
Finished Jul 27 07:42:51 PM PDT 24
Peak memory 207100 kb
Host smart-1447cd9a-134a-4335-ae67-32d7e0124c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11811
77927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.1181177927
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3519779649
Short name T2443
Test name
Test status
Simulation time 153074621 ps
CPU time 0.88 seconds
Started Jul 27 07:42:50 PM PDT 24
Finished Jul 27 07:42:51 PM PDT 24
Peak memory 206956 kb
Host smart-8a227a7d-a411-4b82-bc03-ddab2497cee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35197
79649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3519779649
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3210981704
Short name T2358
Test name
Test status
Simulation time 161402375 ps
CPU time 0.86 seconds
Started Jul 27 07:42:48 PM PDT 24
Finished Jul 27 07:42:49 PM PDT 24
Peak memory 207112 kb
Host smart-d613dd2a-8737-4dbc-b4ea-7303301ef1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32109
81704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3210981704
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2748770948
Short name T1797
Test name
Test status
Simulation time 242233337 ps
CPU time 1.07 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:42:48 PM PDT 24
Peak memory 207092 kb
Host smart-9141e6a0-64a7-4846-98a2-9f47403d3093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27487
70948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2748770948
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3049466607
Short name T678
Test name
Test status
Simulation time 3340207699 ps
CPU time 27.98 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:43:15 PM PDT 24
Peak memory 217140 kb
Host smart-9820cdf8-b2bc-43b2-8d23-2a775d96ca33
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3049466607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3049466607
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3638396795
Short name T816
Test name
Test status
Simulation time 181217219 ps
CPU time 0.86 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:42:49 PM PDT 24
Peak memory 207088 kb
Host smart-6a75ea47-619c-4311-8328-8b49793de931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36383
96795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3638396795
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.2545615889
Short name T2617
Test name
Test status
Simulation time 220081920 ps
CPU time 0.96 seconds
Started Jul 27 07:42:48 PM PDT 24
Finished Jul 27 07:42:49 PM PDT 24
Peak memory 207100 kb
Host smart-15ea505c-65dd-45a1-98df-9c3ccbc90d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25456
15889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2545615889
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.1386891426
Short name T497
Test name
Test status
Simulation time 278666729 ps
CPU time 1.07 seconds
Started Jul 27 07:42:50 PM PDT 24
Finished Jul 27 07:42:51 PM PDT 24
Peak memory 207168 kb
Host smart-5cd41070-5e9e-477f-b742-9990d76ca0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13868
91426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.1386891426
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.3432112137
Short name T2738
Test name
Test status
Simulation time 6940006113 ps
CPU time 53.82 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:43:41 PM PDT 24
Peak memory 207384 kb
Host smart-9f6b2fa8-a30e-4109-b22f-6559ff7997af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34321
12137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.3432112137
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.1243827526
Short name T52
Test name
Test status
Simulation time 3020825890 ps
CPU time 27.67 seconds
Started Jul 27 07:42:37 PM PDT 24
Finished Jul 27 07:43:05 PM PDT 24
Peak memory 207308 kb
Host smart-ec027418-ce55-4980-91d3-fab0eca3a8ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243827526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_hos
t_handshake.1243827526
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.4111987865
Short name T1446
Test name
Test status
Simulation time 44725298 ps
CPU time 0.71 seconds
Started Jul 27 07:43:02 PM PDT 24
Finished Jul 27 07:43:03 PM PDT 24
Peak memory 207144 kb
Host smart-f6daa605-f359-409c-9bf0-7cc2d4a4a48b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4111987865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.4111987865
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.219461256
Short name T2121
Test name
Test status
Simulation time 3903749040 ps
CPU time 6.54 seconds
Started Jul 27 07:42:46 PM PDT 24
Finished Jul 27 07:42:53 PM PDT 24
Peak memory 207288 kb
Host smart-12a3755d-83a4-4459-9578-1df83a926804
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219461256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_ao
n_wake_disconnect.219461256
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1801856623
Short name T2502
Test name
Test status
Simulation time 13501117284 ps
CPU time 17.73 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:43:05 PM PDT 24
Peak memory 207408 kb
Host smart-071ca431-8ce3-416a-a5bb-77a111ec7619
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801856623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1801856623
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.1051354590
Short name T14
Test name
Test status
Simulation time 23332411626 ps
CPU time 27.64 seconds
Started Jul 27 07:42:48 PM PDT 24
Finished Jul 27 07:43:16 PM PDT 24
Peak memory 207372 kb
Host smart-a0b93dcd-b0fa-4a6a-bec9-85d366c175b1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051354590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.1051354590
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2685837115
Short name T475
Test name
Test status
Simulation time 190153051 ps
CPU time 1.02 seconds
Started Jul 27 07:42:46 PM PDT 24
Finished Jul 27 07:42:47 PM PDT 24
Peak memory 207116 kb
Host smart-a5651799-498f-498e-afa6-5308db363409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26858
37115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2685837115
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3419372143
Short name T699
Test name
Test status
Simulation time 152962255 ps
CPU time 0.89 seconds
Started Jul 27 07:42:48 PM PDT 24
Finished Jul 27 07:42:49 PM PDT 24
Peak memory 207048 kb
Host smart-bef401f8-e8eb-49df-a001-a93662099087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34193
72143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3419372143
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.1396979749
Short name T2682
Test name
Test status
Simulation time 322090050 ps
CPU time 1.28 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:42:48 PM PDT 24
Peak memory 207104 kb
Host smart-90b4f01a-477c-4b2a-aa12-f13bf5216b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13969
79749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.1396979749
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.4226129465
Short name T2415
Test name
Test status
Simulation time 321160128 ps
CPU time 1.15 seconds
Started Jul 27 07:42:48 PM PDT 24
Finished Jul 27 07:42:49 PM PDT 24
Peak memory 207100 kb
Host smart-c7260614-3fc9-4e70-b6f9-e33bb0d27594
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4226129465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.4226129465
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.1154252437
Short name T2646
Test name
Test status
Simulation time 15529121172 ps
CPU time 30.59 seconds
Started Jul 27 07:42:48 PM PDT 24
Finished Jul 27 07:43:19 PM PDT 24
Peak memory 207208 kb
Host smart-61df0d6b-f840-4afc-9a64-e1ed0ed65e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11542
52437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.1154252437
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.3211266732
Short name T2213
Test name
Test status
Simulation time 143135713 ps
CPU time 0.87 seconds
Started Jul 27 07:42:48 PM PDT 24
Finished Jul 27 07:42:49 PM PDT 24
Peak memory 207060 kb
Host smart-932afee9-9c5a-484b-8b34-f176bda3502d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211266732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.3211266732
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.2861879403
Short name T2322
Test name
Test status
Simulation time 398391895 ps
CPU time 1.43 seconds
Started Jul 27 07:42:48 PM PDT 24
Finished Jul 27 07:42:49 PM PDT 24
Peak memory 207080 kb
Host smart-b86a66f3-18e5-49a1-ad04-8b1d195596db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28618
79403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.2861879403
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.3558068550
Short name T1097
Test name
Test status
Simulation time 143839066 ps
CPU time 0.86 seconds
Started Jul 27 07:42:50 PM PDT 24
Finished Jul 27 07:42:51 PM PDT 24
Peak memory 207164 kb
Host smart-d41edcf0-52e5-4fce-9c20-c3268632776a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35580
68550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.3558068550
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2993841378
Short name T529
Test name
Test status
Simulation time 54096637 ps
CPU time 0.76 seconds
Started Jul 27 07:42:49 PM PDT 24
Finished Jul 27 07:42:50 PM PDT 24
Peak memory 207044 kb
Host smart-04074dc1-1951-4f20-a7be-aa3f9ad1a61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29938
41378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2993841378
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3014896970
Short name T2068
Test name
Test status
Simulation time 696900949 ps
CPU time 1.99 seconds
Started Jul 27 07:42:48 PM PDT 24
Finished Jul 27 07:42:50 PM PDT 24
Peak memory 207248 kb
Host smart-2311ae1d-8b65-4912-bf7d-20489dde5dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30148
96970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3014896970
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2065443485
Short name T2160
Test name
Test status
Simulation time 314647695 ps
CPU time 2.49 seconds
Started Jul 27 07:42:46 PM PDT 24
Finished Jul 27 07:42:49 PM PDT 24
Peak memory 207240 kb
Host smart-d5dfd665-d1cd-4305-bba6-5ccebe112886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20654
43485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2065443485
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3594957742
Short name T804
Test name
Test status
Simulation time 196827540 ps
CPU time 1.04 seconds
Started Jul 27 07:42:52 PM PDT 24
Finished Jul 27 07:42:53 PM PDT 24
Peak memory 207260 kb
Host smart-a03ebfc3-e151-41c0-ac36-41c575712a11
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3594957742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3594957742
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3332406794
Short name T2444
Test name
Test status
Simulation time 161531760 ps
CPU time 0.84 seconds
Started Jul 27 07:42:52 PM PDT 24
Finished Jul 27 07:42:53 PM PDT 24
Peak memory 207040 kb
Host smart-7b1ab366-ecb2-4635-bcf3-5046b014a0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33324
06794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3332406794
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.644568067
Short name T565
Test name
Test status
Simulation time 204456203 ps
CPU time 0.97 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:42:48 PM PDT 24
Peak memory 207124 kb
Host smart-4ecdc9fc-0df4-45c7-9c4f-a64a20ec4594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64456
8067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.644568067
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.772867796
Short name T2314
Test name
Test status
Simulation time 4874262674 ps
CPU time 36.96 seconds
Started Jul 27 07:42:50 PM PDT 24
Finished Jul 27 07:43:28 PM PDT 24
Peak memory 215512 kb
Host smart-2e1c324b-d3e9-4603-8250-f1e9d0b68f84
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=772867796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.772867796
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.261970491
Short name T2042
Test name
Test status
Simulation time 8972018269 ps
CPU time 56.54 seconds
Started Jul 27 07:42:46 PM PDT 24
Finished Jul 27 07:43:43 PM PDT 24
Peak memory 207340 kb
Host smart-3da0a253-46ba-4b34-a152-e123f1d28981
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=261970491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.261970491
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1648675855
Short name T408
Test name
Test status
Simulation time 263389136 ps
CPU time 0.99 seconds
Started Jul 27 07:42:46 PM PDT 24
Finished Jul 27 07:42:47 PM PDT 24
Peak memory 207072 kb
Host smart-056e890f-ac80-4e26-b11c-b214ce6575be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16486
75855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1648675855
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.3748503417
Short name T1391
Test name
Test status
Simulation time 23374286301 ps
CPU time 31.98 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:43:20 PM PDT 24
Peak memory 207376 kb
Host smart-b87bbc81-91fa-4953-86c9-194bd819bda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37485
03417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.3748503417
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2952890177
Short name T670
Test name
Test status
Simulation time 3293069605 ps
CPU time 5.21 seconds
Started Jul 27 07:42:48 PM PDT 24
Finished Jul 27 07:42:53 PM PDT 24
Peak memory 207316 kb
Host smart-7ff65e0e-698b-4dfc-b0cb-c61d7edd528e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29528
90177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2952890177
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.3970130621
Short name T158
Test name
Test status
Simulation time 5479542391 ps
CPU time 44.15 seconds
Started Jul 27 07:42:56 PM PDT 24
Finished Jul 27 07:43:40 PM PDT 24
Peak memory 216908 kb
Host smart-a1fc28db-e47d-46ce-a6b9-1bb4df086297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39701
30621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.3970130621
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.448272999
Short name T1571
Test name
Test status
Simulation time 4781588200 ps
CPU time 41.32 seconds
Started Jul 27 07:42:58 PM PDT 24
Finished Jul 27 07:43:39 PM PDT 24
Peak memory 217172 kb
Host smart-d69b92d2-b1f0-4ec4-8c3f-b9b2eb1bf679
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=448272999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.448272999
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.2933810142
Short name T2650
Test name
Test status
Simulation time 286816146 ps
CPU time 1.01 seconds
Started Jul 27 07:43:00 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 207120 kb
Host smart-7941716c-79ef-48c9-844d-05523c4b8b37
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2933810142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.2933810142
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1400537562
Short name T687
Test name
Test status
Simulation time 199187744 ps
CPU time 0.94 seconds
Started Jul 27 07:42:57 PM PDT 24
Finished Jul 27 07:42:58 PM PDT 24
Peak memory 207036 kb
Host smart-87d44d51-d34b-49cf-bdc7-01870d15b9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14005
37562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1400537562
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.1320248805
Short name T1799
Test name
Test status
Simulation time 4771574290 ps
CPU time 35.12 seconds
Started Jul 27 07:43:02 PM PDT 24
Finished Jul 27 07:43:37 PM PDT 24
Peak memory 216848 kb
Host smart-9ec6dc4f-1779-40c5-9d16-5d315d63c0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13202
48805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.1320248805
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.3665333748
Short name T179
Test name
Test status
Simulation time 8080360003 ps
CPU time 237.39 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:46:57 PM PDT 24
Peak memory 215484 kb
Host smart-105da0f6-1960-43dc-9584-f3215e07d91b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3665333748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.3665333748
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.3975371742
Short name T1765
Test name
Test status
Simulation time 167196166 ps
CPU time 0.9 seconds
Started Jul 27 07:43:01 PM PDT 24
Finished Jul 27 07:43:02 PM PDT 24
Peak memory 207116 kb
Host smart-66cd366a-ccec-4971-8470-35ffb3a86f80
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3975371742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.3975371742
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2474532958
Short name T617
Test name
Test status
Simulation time 151131520 ps
CPU time 0.89 seconds
Started Jul 27 07:43:02 PM PDT 24
Finished Jul 27 07:43:03 PM PDT 24
Peak memory 207064 kb
Host smart-17f307f5-1e60-4ef3-bb6c-6f30e810444d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24745
32958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2474532958
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1628131712
Short name T1451
Test name
Test status
Simulation time 217371914 ps
CPU time 1.02 seconds
Started Jul 27 07:43:01 PM PDT 24
Finished Jul 27 07:43:02 PM PDT 24
Peak memory 207216 kb
Host smart-fe4bfe1b-70d7-4c83-ad88-54f378ed848b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16281
31712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1628131712
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.711280887
Short name T1828
Test name
Test status
Simulation time 189651739 ps
CPU time 0.88 seconds
Started Jul 27 07:42:58 PM PDT 24
Finished Jul 27 07:42:59 PM PDT 24
Peak memory 207136 kb
Host smart-a96442f9-9c26-4655-9298-ae94959a7852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71128
0887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.711280887
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2301059691
Short name T1746
Test name
Test status
Simulation time 168243279 ps
CPU time 0.86 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:00 PM PDT 24
Peak memory 207160 kb
Host smart-ca1bf499-5bb9-4034-adab-52ba946e8471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23010
59691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2301059691
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3393846047
Short name T887
Test name
Test status
Simulation time 232944014 ps
CPU time 0.92 seconds
Started Jul 27 07:43:05 PM PDT 24
Finished Jul 27 07:43:06 PM PDT 24
Peak memory 207112 kb
Host smart-7b9557b0-d483-4885-9912-b67ab134b18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33938
46047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3393846047
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2559306045
Short name T2097
Test name
Test status
Simulation time 151979195 ps
CPU time 0.79 seconds
Started Jul 27 07:42:58 PM PDT 24
Finished Jul 27 07:42:59 PM PDT 24
Peak memory 207140 kb
Host smart-47aabba9-1885-4104-8307-5d4eacbb055c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25593
06045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2559306045
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3507041645
Short name T1436
Test name
Test status
Simulation time 206553597 ps
CPU time 0.96 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:00 PM PDT 24
Peak memory 207084 kb
Host smart-5e48d1e7-162f-41d8-bf09-ca4f568e1ae7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3507041645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3507041645
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.4130710926
Short name T1266
Test name
Test status
Simulation time 144892671 ps
CPU time 0.79 seconds
Started Jul 27 07:42:56 PM PDT 24
Finished Jul 27 07:42:57 PM PDT 24
Peak memory 207128 kb
Host smart-8bd7825c-5be6-4d39-8061-aeba6bab5a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41307
10926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.4130710926
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.623229071
Short name T24
Test name
Test status
Simulation time 48405362 ps
CPU time 0.7 seconds
Started Jul 27 07:42:57 PM PDT 24
Finished Jul 27 07:42:58 PM PDT 24
Peak memory 207040 kb
Host smart-d2441d68-3e7b-4ce7-90ab-384fd86f3569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62322
9071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.623229071
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3161724249
Short name T973
Test name
Test status
Simulation time 22639859583 ps
CPU time 61.77 seconds
Started Jul 27 07:43:04 PM PDT 24
Finished Jul 27 07:44:06 PM PDT 24
Peak memory 223836 kb
Host smart-77626dc8-58a9-4f51-91f9-cde7f4c71264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31617
24249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3161724249
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3296896101
Short name T737
Test name
Test status
Simulation time 211509376 ps
CPU time 0.9 seconds
Started Jul 27 07:43:01 PM PDT 24
Finished Jul 27 07:43:02 PM PDT 24
Peak memory 207104 kb
Host smart-6a22f9cd-0aa0-4e73-8d62-a7c8e8199b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32968
96101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3296896101
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.937952667
Short name T827
Test name
Test status
Simulation time 263518513 ps
CPU time 1.02 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 207076 kb
Host smart-ef7fe09c-d6a1-4932-9cfe-20575273530b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93795
2667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.937952667
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.2473509342
Short name T365
Test name
Test status
Simulation time 229850757 ps
CPU time 0.93 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:00 PM PDT 24
Peak memory 207200 kb
Host smart-42eadf68-822f-4a71-8ab4-8a6071c30dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24735
09342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.2473509342
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.223268568
Short name T1181
Test name
Test status
Simulation time 183508640 ps
CPU time 0.91 seconds
Started Jul 27 07:42:58 PM PDT 24
Finished Jul 27 07:42:59 PM PDT 24
Peak memory 207096 kb
Host smart-a285ac7d-d815-4f0f-b048-c500fd2a7f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22326
8568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.223268568
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.1433152038
Short name T1757
Test name
Test status
Simulation time 159390957 ps
CPU time 0.84 seconds
Started Jul 27 07:43:00 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 207128 kb
Host smart-b2a67828-1075-4bf5-af3f-634ed3945dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14331
52038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1433152038
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.42093336
Short name T1059
Test name
Test status
Simulation time 176420728 ps
CPU time 0.99 seconds
Started Jul 27 07:43:00 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 207100 kb
Host smart-69549067-adb3-4238-8edc-406d199d65db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42093
336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.42093336
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3530759125
Short name T1904
Test name
Test status
Simulation time 154913152 ps
CPU time 0.89 seconds
Started Jul 27 07:42:57 PM PDT 24
Finished Jul 27 07:42:58 PM PDT 24
Peak memory 207028 kb
Host smart-91653417-2a3f-4119-a2a4-0043aa99754e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35307
59125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3530759125
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.890623027
Short name T1279
Test name
Test status
Simulation time 258821347 ps
CPU time 0.96 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:00 PM PDT 24
Peak memory 207060 kb
Host smart-5b2f2718-22f7-41fd-947a-ba06f3678a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89062
3027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.890623027
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.3039307672
Short name T1665
Test name
Test status
Simulation time 4484553853 ps
CPU time 35.49 seconds
Started Jul 27 07:42:58 PM PDT 24
Finished Jul 27 07:43:34 PM PDT 24
Peak memory 215256 kb
Host smart-c12a4c3f-7f46-462c-9e28-96b164556269
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3039307672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.3039307672
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.560345113
Short name T1
Test name
Test status
Simulation time 233166996 ps
CPU time 0.95 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:00 PM PDT 24
Peak memory 207108 kb
Host smart-024d8963-93c8-4d4e-8e63-73c88626471d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56034
5113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.560345113
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.847127108
Short name T2157
Test name
Test status
Simulation time 171457109 ps
CPU time 0.89 seconds
Started Jul 27 07:43:00 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 207120 kb
Host smart-342fccc1-f1b8-48ea-a6ad-38b05c189acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84712
7108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.847127108
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.3811831076
Short name T2737
Test name
Test status
Simulation time 705473930 ps
CPU time 1.91 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 206960 kb
Host smart-9d0d7637-063d-44b8-b179-f29e2e9d733c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38118
31076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.3811831076
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.1770705284
Short name T496
Test name
Test status
Simulation time 3246365740 ps
CPU time 34.49 seconds
Started Jul 27 07:42:57 PM PDT 24
Finished Jul 27 07:43:32 PM PDT 24
Peak memory 216880 kb
Host smart-e0cb2139-ee0d-44be-84b0-d0b442c433a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17707
05284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.1770705284
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.1309051926
Short name T623
Test name
Test status
Simulation time 1126750775 ps
CPU time 9.52 seconds
Started Jul 27 07:42:47 PM PDT 24
Finished Jul 27 07:42:57 PM PDT 24
Peak memory 207348 kb
Host smart-b5716b4c-0eb1-4053-9430-3aad285c8eb8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309051926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos
t_handshake.1309051926
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.1106684508
Short name T1636
Test name
Test status
Simulation time 76895229 ps
CPU time 0.71 seconds
Started Jul 27 07:43:09 PM PDT 24
Finished Jul 27 07:43:10 PM PDT 24
Peak memory 207208 kb
Host smart-698c88ad-7c56-4966-b2d4-e2819528e37b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1106684508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.1106684508
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.412176797
Short name T2245
Test name
Test status
Simulation time 4175834513 ps
CPU time 6.03 seconds
Started Jul 27 07:42:58 PM PDT 24
Finished Jul 27 07:43:04 PM PDT 24
Peak memory 207344 kb
Host smart-e8720793-c065-4e56-ab4b-6b14ecd29d85
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412176797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_ao
n_wake_disconnect.412176797
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3450389203
Short name T1308
Test name
Test status
Simulation time 13426421230 ps
CPU time 18.29 seconds
Started Jul 27 07:43:00 PM PDT 24
Finished Jul 27 07:43:18 PM PDT 24
Peak memory 207392 kb
Host smart-9297b509-fccd-4ed1-87cb-b4d7ae201f6d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450389203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3450389203
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.3900379814
Short name T2102
Test name
Test status
Simulation time 23367864191 ps
CPU time 31.95 seconds
Started Jul 27 07:43:05 PM PDT 24
Finished Jul 27 07:43:37 PM PDT 24
Peak memory 207368 kb
Host smart-b0de1743-0e73-4ced-8f1e-d006110539af
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900379814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.3900379814
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3871398505
Short name T2599
Test name
Test status
Simulation time 205562781 ps
CPU time 0.93 seconds
Started Jul 27 07:43:01 PM PDT 24
Finished Jul 27 07:43:02 PM PDT 24
Peak memory 207216 kb
Host smart-16df2533-3e69-4f49-aae8-f49c5335d596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38713
98505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3871398505
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.3511369399
Short name T1253
Test name
Test status
Simulation time 151951173 ps
CPU time 0.86 seconds
Started Jul 27 07:43:00 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 207112 kb
Host smart-b6f5f3d5-9d2b-44c3-9796-71f0f6979209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35113
69399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.3511369399
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.3632079061
Short name T2575
Test name
Test status
Simulation time 395885895 ps
CPU time 1.43 seconds
Started Jul 27 07:42:57 PM PDT 24
Finished Jul 27 07:42:59 PM PDT 24
Peak memory 207020 kb
Host smart-bda1052e-3acc-4f49-a909-b3ab64dda838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36320
79061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.3632079061
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3583693285
Short name T1534
Test name
Test status
Simulation time 997618120 ps
CPU time 2.46 seconds
Started Jul 27 07:42:57 PM PDT 24
Finished Jul 27 07:43:00 PM PDT 24
Peak memory 207328 kb
Host smart-2a739073-dd71-4228-9fd1-b9b39a0c4d02
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3583693285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3583693285
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.2818937938
Short name T1629
Test name
Test status
Simulation time 17356093600 ps
CPU time 40.85 seconds
Started Jul 27 07:43:01 PM PDT 24
Finished Jul 27 07:43:42 PM PDT 24
Peak memory 207320 kb
Host smart-36ed55ed-62fe-405f-968c-03f8a6aa69a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28189
37938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.2818937938
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.2629532679
Short name T1600
Test name
Test status
Simulation time 4328222482 ps
CPU time 30.07 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:29 PM PDT 24
Peak memory 207328 kb
Host smart-679bc9ef-4f26-4c3e-969f-d7d890f8da77
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629532679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.2629532679
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.3317313145
Short name T2168
Test name
Test status
Simulation time 398740254 ps
CPU time 1.35 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 206960 kb
Host smart-4d86211d-7d9e-4a13-96dd-10e9177899f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33173
13145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.3317313145
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.1335904697
Short name T2441
Test name
Test status
Simulation time 140118283 ps
CPU time 0.85 seconds
Started Jul 27 07:43:00 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 207108 kb
Host smart-0c1cb4cc-da25-41d3-881e-9261162062bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13359
04697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.1335904697
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3054989221
Short name T484
Test name
Test status
Simulation time 27978661 ps
CPU time 0.69 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:00 PM PDT 24
Peak memory 207080 kb
Host smart-e7e8ea77-1b14-4ce0-8074-e1a3efcea25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30549
89221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3054989221
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1389076887
Short name T2303
Test name
Test status
Simulation time 917164938 ps
CPU time 2.63 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:02 PM PDT 24
Peak memory 207284 kb
Host smart-a6aa512b-fbb7-42b5-9dee-726567690fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13890
76887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1389076887
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3950722187
Short name T731
Test name
Test status
Simulation time 252244956 ps
CPU time 1.95 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 207272 kb
Host smart-851e6876-e78f-4ff3-93a1-df88ebb8c6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39507
22187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3950722187
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3975207250
Short name T1758
Test name
Test status
Simulation time 246571208 ps
CPU time 1.14 seconds
Started Jul 27 07:43:00 PM PDT 24
Finished Jul 27 07:43:01 PM PDT 24
Peak memory 207348 kb
Host smart-151a6cd6-1e65-4039-98fc-6b131f8b23b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3975207250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3975207250
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2330835729
Short name T851
Test name
Test status
Simulation time 165320547 ps
CPU time 0.86 seconds
Started Jul 27 07:43:01 PM PDT 24
Finished Jul 27 07:43:02 PM PDT 24
Peak memory 207084 kb
Host smart-b3b3d1b2-ad8c-4c51-be87-a1876d2897c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23308
35729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2330835729
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2241457239
Short name T1751
Test name
Test status
Simulation time 155447563 ps
CPU time 0.86 seconds
Started Jul 27 07:42:58 PM PDT 24
Finished Jul 27 07:42:59 PM PDT 24
Peak memory 206728 kb
Host smart-3f129a96-6014-44dd-9631-accab58e529b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22414
57239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2241457239
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.2239469670
Short name T649
Test name
Test status
Simulation time 6093974991 ps
CPU time 45.17 seconds
Started Jul 27 07:42:57 PM PDT 24
Finished Jul 27 07:43:43 PM PDT 24
Peak memory 215464 kb
Host smart-26e5387d-b5f2-4a3b-a0c1-edfa76c4b9fe
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2239469670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.2239469670
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.1083866191
Short name T410
Test name
Test status
Simulation time 7162395553 ps
CPU time 50.64 seconds
Started Jul 27 07:43:05 PM PDT 24
Finished Jul 27 07:43:56 PM PDT 24
Peak memory 207352 kb
Host smart-059ef9e7-fcc0-4882-877a-0f30cdfa7258
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1083866191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.1083866191
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.2321441559
Short name T54
Test name
Test status
Simulation time 232389440 ps
CPU time 1 seconds
Started Jul 27 07:43:01 PM PDT 24
Finished Jul 27 07:43:02 PM PDT 24
Peak memory 207132 kb
Host smart-44e869ce-3249-4040-aa05-57e1b4da4fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23214
41559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.2321441559
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.1939116799
Short name T219
Test name
Test status
Simulation time 23280656045 ps
CPU time 28.42 seconds
Started Jul 27 07:43:00 PM PDT 24
Finished Jul 27 07:43:29 PM PDT 24
Peak memory 207372 kb
Host smart-a58463f2-648e-4c67-a174-9607b6bdea87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19391
16799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.1939116799
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.3376671656
Short name T2062
Test name
Test status
Simulation time 3280095209 ps
CPU time 4.59 seconds
Started Jul 27 07:42:58 PM PDT 24
Finished Jul 27 07:43:03 PM PDT 24
Peak memory 207360 kb
Host smart-4e456ad4-4707-4f32-abfb-a1e957d0d51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33766
71656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.3376671656
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3123877375
Short name T719
Test name
Test status
Simulation time 6305235690 ps
CPU time 50.1 seconds
Started Jul 27 07:43:05 PM PDT 24
Finished Jul 27 07:43:55 PM PDT 24
Peak memory 217528 kb
Host smart-44206475-781a-4a95-be0e-900d89d8e6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31238
77375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3123877375
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.3770998162
Short name T1877
Test name
Test status
Simulation time 4324007633 ps
CPU time 130.41 seconds
Started Jul 27 07:43:01 PM PDT 24
Finished Jul 27 07:45:11 PM PDT 24
Peak memory 215624 kb
Host smart-f626043b-c8c2-46ac-8bef-632f0dc3946b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3770998162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.3770998162
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3416528501
Short name T2112
Test name
Test status
Simulation time 274568224 ps
CPU time 1.08 seconds
Started Jul 27 07:43:01 PM PDT 24
Finished Jul 27 07:43:03 PM PDT 24
Peak memory 207168 kb
Host smart-2aa9a49d-dc3e-4ef5-bd78-db5e6ca44dd9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3416528501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3416528501
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2259179188
Short name T2342
Test name
Test status
Simulation time 187981281 ps
CPU time 0.92 seconds
Started Jul 27 07:43:04 PM PDT 24
Finished Jul 27 07:43:05 PM PDT 24
Peak memory 207216 kb
Host smart-090f91d0-ee71-4f5d-8b69-aff4b4384b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22591
79188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2259179188
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.4085784157
Short name T2594
Test name
Test status
Simulation time 5238600630 ps
CPU time 154.4 seconds
Started Jul 27 07:43:02 PM PDT 24
Finished Jul 27 07:45:36 PM PDT 24
Peak memory 215664 kb
Host smart-bec28aa0-3211-4328-83d2-c83286f08daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40857
84157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.4085784157
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.2604486358
Short name T984
Test name
Test status
Simulation time 5251054232 ps
CPU time 156.82 seconds
Started Jul 27 07:43:04 PM PDT 24
Finished Jul 27 07:45:41 PM PDT 24
Peak memory 215588 kb
Host smart-c4d8d340-4784-454a-af99-831d22b6fe73
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2604486358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.2604486358
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.1885922789
Short name T2829
Test name
Test status
Simulation time 176405747 ps
CPU time 0.94 seconds
Started Jul 27 07:43:03 PM PDT 24
Finished Jul 27 07:43:04 PM PDT 24
Peak memory 206512 kb
Host smart-e4b5f5e0-a13c-4aa1-929e-fe6a861c821f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1885922789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.1885922789
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2874549621
Short name T729
Test name
Test status
Simulation time 144386644 ps
CPU time 0.86 seconds
Started Jul 27 07:43:02 PM PDT 24
Finished Jul 27 07:43:03 PM PDT 24
Peak memory 207196 kb
Host smart-5bf03c47-2f72-49a2-b9e1-1931efc7a88c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28745
49621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2874549621
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3855168881
Short name T2043
Test name
Test status
Simulation time 180060989 ps
CPU time 0.89 seconds
Started Jul 27 07:43:04 PM PDT 24
Finished Jul 27 07:43:05 PM PDT 24
Peak memory 207208 kb
Host smart-867bee8b-a82e-4749-82e5-e90cf52ebc73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38551
68881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3855168881
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1256414806
Short name T789
Test name
Test status
Simulation time 165350133 ps
CPU time 0.89 seconds
Started Jul 27 07:43:01 PM PDT 24
Finished Jul 27 07:43:02 PM PDT 24
Peak memory 207184 kb
Host smart-304ecb9c-fcd2-4f8b-a7cd-f3def68081e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12564
14806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1256414806
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.4279444108
Short name T2376
Test name
Test status
Simulation time 186917709 ps
CPU time 0.9 seconds
Started Jul 27 07:43:11 PM PDT 24
Finished Jul 27 07:43:12 PM PDT 24
Peak memory 207088 kb
Host smart-f3192d6e-8907-4684-8171-aa6749d7da2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42794
44108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.4279444108
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.768935813
Short name T1575
Test name
Test status
Simulation time 164841253 ps
CPU time 0.83 seconds
Started Jul 27 07:43:05 PM PDT 24
Finished Jul 27 07:43:06 PM PDT 24
Peak memory 207108 kb
Host smart-49ab421b-a97b-49d7-8929-aa628940c70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76893
5813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.768935813
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.2383609159
Short name T631
Test name
Test status
Simulation time 238004323 ps
CPU time 0.98 seconds
Started Jul 27 07:43:06 PM PDT 24
Finished Jul 27 07:43:07 PM PDT 24
Peak memory 207136 kb
Host smart-711ff0f5-76ac-4107-9588-baa53fe64c4d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2383609159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.2383609159
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3389446716
Short name T2141
Test name
Test status
Simulation time 178968124 ps
CPU time 0.87 seconds
Started Jul 27 07:43:15 PM PDT 24
Finished Jul 27 07:43:16 PM PDT 24
Peak memory 207068 kb
Host smart-87a85861-0b42-4942-989e-704ea36d9918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33894
46716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3389446716
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2945207289
Short name T2058
Test name
Test status
Simulation time 64642659 ps
CPU time 0.7 seconds
Started Jul 27 07:43:09 PM PDT 24
Finished Jul 27 07:43:10 PM PDT 24
Peak memory 207032 kb
Host smart-d4446750-e972-45b2-9b34-90f354513b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29452
07289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2945207289
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.509312149
Short name T2147
Test name
Test status
Simulation time 14815748667 ps
CPU time 38.27 seconds
Started Jul 27 07:43:10 PM PDT 24
Finished Jul 27 07:43:49 PM PDT 24
Peak memory 215592 kb
Host smart-19a82859-ce64-4dca-bfdc-4f0f40dd43a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50931
2149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.509312149
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3143284891
Short name T1686
Test name
Test status
Simulation time 180868902 ps
CPU time 0.88 seconds
Started Jul 27 07:43:08 PM PDT 24
Finished Jul 27 07:43:09 PM PDT 24
Peak memory 207120 kb
Host smart-e7022f0f-46f4-499f-a6fc-e3c1e1018c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31432
84891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3143284891
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2890172779
Short name T1696
Test name
Test status
Simulation time 173269251 ps
CPU time 0.86 seconds
Started Jul 27 07:43:10 PM PDT 24
Finished Jul 27 07:43:11 PM PDT 24
Peak memory 206964 kb
Host smart-2e5387b4-088c-4c03-aea7-008cb78b2315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28901
72779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2890172779
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.993203920
Short name T1028
Test name
Test status
Simulation time 209382224 ps
CPU time 0.98 seconds
Started Jul 27 07:43:12 PM PDT 24
Finished Jul 27 07:43:13 PM PDT 24
Peak memory 207108 kb
Host smart-0f24f173-fbf0-4d41-b5fd-9bec8e69499f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99320
3920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.993203920
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1334890950
Short name T904
Test name
Test status
Simulation time 206755912 ps
CPU time 1.01 seconds
Started Jul 27 07:43:10 PM PDT 24
Finished Jul 27 07:43:12 PM PDT 24
Peak memory 207064 kb
Host smart-51b672eb-0889-477e-b011-e47a8af09b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13348
90950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1334890950
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.4196545409
Short name T853
Test name
Test status
Simulation time 196024708 ps
CPU time 0.93 seconds
Started Jul 27 07:43:11 PM PDT 24
Finished Jul 27 07:43:12 PM PDT 24
Peak memory 205988 kb
Host smart-0ba324e8-b970-4ae7-a0a5-f4c68c4b9002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41965
45409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.4196545409
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2214677395
Short name T542
Test name
Test status
Simulation time 184196836 ps
CPU time 0.87 seconds
Started Jul 27 07:43:12 PM PDT 24
Finished Jul 27 07:43:13 PM PDT 24
Peak memory 206756 kb
Host smart-ee3fa151-724a-4e08-8acf-cdc070d53ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22146
77395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2214677395
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.4287599594
Short name T2164
Test name
Test status
Simulation time 187596759 ps
CPU time 0.85 seconds
Started Jul 27 07:43:13 PM PDT 24
Finished Jul 27 07:43:14 PM PDT 24
Peak memory 207116 kb
Host smart-dbd6dadb-597c-4042-b49b-b674e8f5ca90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42875
99594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.4287599594
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.2539484756
Short name T1603
Test name
Test status
Simulation time 3820507368 ps
CPU time 105.76 seconds
Started Jul 27 07:43:05 PM PDT 24
Finished Jul 27 07:44:51 PM PDT 24
Peak memory 215536 kb
Host smart-923a099e-eb1f-44ef-85ee-12630a9a2410
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2539484756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.2539484756
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.240884567
Short name T2228
Test name
Test status
Simulation time 214709222 ps
CPU time 0.88 seconds
Started Jul 27 07:43:06 PM PDT 24
Finished Jul 27 07:43:07 PM PDT 24
Peak memory 207052 kb
Host smart-2db0c3bb-678c-4e56-b86f-150d10916b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24088
4567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.240884567
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3551706817
Short name T103
Test name
Test status
Simulation time 173769987 ps
CPU time 0.86 seconds
Started Jul 27 07:43:13 PM PDT 24
Finished Jul 27 07:43:14 PM PDT 24
Peak memory 207136 kb
Host smart-b0fa5c36-16ac-4488-b69b-fa936e0adb5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35517
06817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3551706817
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.541054996
Short name T2572
Test name
Test status
Simulation time 388920407 ps
CPU time 1.33 seconds
Started Jul 27 07:43:07 PM PDT 24
Finished Jul 27 07:43:09 PM PDT 24
Peak memory 207052 kb
Host smart-3b3de736-0e7e-481d-b48d-542d9d0e94eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54105
4996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.541054996
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.3256816345
Short name T344
Test name
Test status
Simulation time 4531569058 ps
CPU time 134.7 seconds
Started Jul 27 07:43:15 PM PDT 24
Finished Jul 27 07:45:30 PM PDT 24
Peak memory 215540 kb
Host smart-4d9c2919-7563-4f9a-bd74-3f6577cec7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32568
16345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.3256816345
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.3045522792
Short name T1884
Test name
Test status
Simulation time 3437937068 ps
CPU time 31.44 seconds
Started Jul 27 07:42:59 PM PDT 24
Finished Jul 27 07:43:31 PM PDT 24
Peak memory 207424 kb
Host smart-49579de9-05d7-47b5-9e48-484906801c3d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045522792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos
t_handshake.3045522792
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.3549391842
Short name T2693
Test name
Test status
Simulation time 66595226 ps
CPU time 0.67 seconds
Started Jul 27 07:43:18 PM PDT 24
Finished Jul 27 07:43:19 PM PDT 24
Peak memory 207152 kb
Host smart-0023a372-a48e-4b8a-ac51-05cfb0355783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3549391842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3549391842
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.4240500400
Short name T842
Test name
Test status
Simulation time 3751279503 ps
CPU time 5.63 seconds
Started Jul 27 07:43:07 PM PDT 24
Finished Jul 27 07:43:12 PM PDT 24
Peak memory 207312 kb
Host smart-71f579fd-1e1a-408b-80b9-2df404463233
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240500400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.4240500400
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.3588044300
Short name T2006
Test name
Test status
Simulation time 13351671784 ps
CPU time 16.02 seconds
Started Jul 27 07:43:13 PM PDT 24
Finished Jul 27 07:43:29 PM PDT 24
Peak memory 207376 kb
Host smart-b67ce437-d77e-4005-b49a-5dce792d8d77
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588044300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3588044300
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3678180855
Short name T1954
Test name
Test status
Simulation time 23324245747 ps
CPU time 30.5 seconds
Started Jul 27 07:43:09 PM PDT 24
Finished Jul 27 07:43:40 PM PDT 24
Peak memory 207364 kb
Host smart-3f2231e3-2ad1-4fe1-966c-b0ad1bbfd803
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678180855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_resume.3678180855
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1175673819
Short name T2348
Test name
Test status
Simulation time 157631222 ps
CPU time 0.88 seconds
Started Jul 27 07:43:06 PM PDT 24
Finished Jul 27 07:43:07 PM PDT 24
Peak memory 207204 kb
Host smart-1ac1f227-8106-4d92-9c81-da565a771367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11756
73819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1175673819
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.243869530
Short name T545
Test name
Test status
Simulation time 149059517 ps
CPU time 0.88 seconds
Started Jul 27 07:43:10 PM PDT 24
Finished Jul 27 07:43:11 PM PDT 24
Peak memory 207040 kb
Host smart-11337134-b477-4658-ba50-9110efcc50cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24386
9530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.243869530
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.3364093218
Short name T2007
Test name
Test status
Simulation time 511497556 ps
CPU time 1.9 seconds
Started Jul 27 07:43:08 PM PDT 24
Finished Jul 27 07:43:10 PM PDT 24
Peak memory 207156 kb
Host smart-9e77563d-f63b-4813-82e4-337a3d380645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33640
93218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.3364093218
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2452074894
Short name T81
Test name
Test status
Simulation time 613822011 ps
CPU time 1.82 seconds
Started Jul 27 07:43:15 PM PDT 24
Finished Jul 27 07:43:17 PM PDT 24
Peak memory 207124 kb
Host smart-c7aa822b-89a4-4fc4-9ad1-2437d76f2273
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2452074894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2452074894
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.3561228300
Short name T1579
Test name
Test status
Simulation time 13420431119 ps
CPU time 30 seconds
Started Jul 27 07:43:15 PM PDT 24
Finished Jul 27 07:43:45 PM PDT 24
Peak memory 207388 kb
Host smart-fff6c7a3-402e-46b0-a395-98346d179c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35612
28300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.3561228300
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.3466269869
Short name T400
Test name
Test status
Simulation time 4827604555 ps
CPU time 44.13 seconds
Started Jul 27 07:43:10 PM PDT 24
Finished Jul 27 07:43:54 PM PDT 24
Peak memory 207328 kb
Host smart-0d98cbfb-a4f9-4e71-ab62-ecd0d6e010d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466269869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.3466269869
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.3513812580
Short name T1903
Test name
Test status
Simulation time 505725526 ps
CPU time 1.64 seconds
Started Jul 27 07:43:12 PM PDT 24
Finished Jul 27 07:43:14 PM PDT 24
Peak memory 207108 kb
Host smart-36ac1c02-3e08-4006-9cd1-eacd617eb8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35138
12580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.3513812580
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1373448459
Short name T1682
Test name
Test status
Simulation time 137736451 ps
CPU time 0.83 seconds
Started Jul 27 07:43:12 PM PDT 24
Finished Jul 27 07:43:13 PM PDT 24
Peak memory 207040 kb
Host smart-03247139-2af7-4341-afe9-74b98f28275c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13734
48459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1373448459
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1096230885
Short name T1313
Test name
Test status
Simulation time 35990537 ps
CPU time 0.69 seconds
Started Jul 27 07:43:11 PM PDT 24
Finished Jul 27 07:43:12 PM PDT 24
Peak memory 207032 kb
Host smart-540b4457-e3f4-4f02-9f6c-552dcb6ef3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10962
30885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1096230885
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.4031113651
Short name T1699
Test name
Test status
Simulation time 851605432 ps
CPU time 2.57 seconds
Started Jul 27 07:43:12 PM PDT 24
Finished Jul 27 07:43:15 PM PDT 24
Peak memory 206992 kb
Host smart-a398e57b-a631-4c48-a6b2-158949580e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40311
13651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.4031113651
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2685412563
Short name T2152
Test name
Test status
Simulation time 189239961 ps
CPU time 2.47 seconds
Started Jul 27 07:43:13 PM PDT 24
Finished Jul 27 07:43:16 PM PDT 24
Peak memory 207340 kb
Host smart-22eaa1ac-e4d7-44f0-9bb5-318218d88cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26854
12563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2685412563
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2759183238
Short name T2220
Test name
Test status
Simulation time 290538509 ps
CPU time 1.33 seconds
Started Jul 27 07:43:08 PM PDT 24
Finished Jul 27 07:43:10 PM PDT 24
Peak memory 207320 kb
Host smart-6a7293f7-0fed-4da9-b050-c989612f01a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2759183238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2759183238
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.4031654535
Short name T92
Test name
Test status
Simulation time 150916045 ps
CPU time 0.86 seconds
Started Jul 27 07:43:10 PM PDT 24
Finished Jul 27 07:43:11 PM PDT 24
Peak memory 207028 kb
Host smart-09789173-ada9-4233-ad20-aa1bb4e32b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40316
54535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.4031654535
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3356536480
Short name T1574
Test name
Test status
Simulation time 184651523 ps
CPU time 0.93 seconds
Started Jul 27 07:43:08 PM PDT 24
Finished Jul 27 07:43:09 PM PDT 24
Peak memory 207100 kb
Host smart-a350b1ef-3363-449a-8d76-d5c1206a1b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33565
36480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3356536480
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.1369007298
Short name T1955
Test name
Test status
Simulation time 9879260121 ps
CPU time 101.99 seconds
Started Jul 27 07:43:09 PM PDT 24
Finished Jul 27 07:44:51 PM PDT 24
Peak memory 216924 kb
Host smart-dff9f630-3a3e-4281-8b7e-25142cac0d1f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1369007298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.1369007298
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2038670178
Short name T1712
Test name
Test status
Simulation time 195377678 ps
CPU time 0.92 seconds
Started Jul 27 07:43:06 PM PDT 24
Finished Jul 27 07:43:07 PM PDT 24
Peak memory 207192 kb
Host smart-3750994b-c5d4-4d7b-9a70-c1365eb61962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20386
70178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2038670178
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3975778558
Short name T1975
Test name
Test status
Simulation time 23289131816 ps
CPU time 26.59 seconds
Started Jul 27 07:43:14 PM PDT 24
Finished Jul 27 07:43:41 PM PDT 24
Peak memory 207360 kb
Host smart-56447d19-fe38-45b4-abeb-52ed44f55812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39757
78558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3975778558
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3332145586
Short name T2394
Test name
Test status
Simulation time 3326944523 ps
CPU time 4.72 seconds
Started Jul 27 07:43:13 PM PDT 24
Finished Jul 27 07:43:18 PM PDT 24
Peak memory 207364 kb
Host smart-ce8a87de-d9b6-472f-b208-6d4d2c585e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33321
45586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3332145586
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.2412658953
Short name T334
Test name
Test status
Simulation time 7596064456 ps
CPU time 74.32 seconds
Started Jul 27 07:43:07 PM PDT 24
Finished Jul 27 07:44:21 PM PDT 24
Peak memory 223716 kb
Host smart-da3c7b68-0f11-490c-a1e0-75814afb1771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24126
58953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.2412658953
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.1044566482
Short name T768
Test name
Test status
Simulation time 4674681704 ps
CPU time 36.32 seconds
Started Jul 27 07:43:13 PM PDT 24
Finished Jul 27 07:43:49 PM PDT 24
Peak memory 207448 kb
Host smart-91fd68f6-d53d-465f-b6c8-9e0559710a0a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1044566482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.1044566482
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3544667825
Short name T1231
Test name
Test status
Simulation time 246058857 ps
CPU time 1.01 seconds
Started Jul 27 07:43:12 PM PDT 24
Finished Jul 27 07:43:13 PM PDT 24
Peak memory 207160 kb
Host smart-ae768b92-a79c-480b-b4fd-e01f1e4996ce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3544667825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3544667825
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1331121030
Short name T2076
Test name
Test status
Simulation time 249397141 ps
CPU time 1.05 seconds
Started Jul 27 07:43:07 PM PDT 24
Finished Jul 27 07:43:08 PM PDT 24
Peak memory 207164 kb
Host smart-f9b3b22d-7b5c-48aa-9fb6-ff6ddfb01cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13311
21030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1331121030
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3144156772
Short name T1581
Test name
Test status
Simulation time 6005318235 ps
CPU time 46.09 seconds
Started Jul 27 07:43:13 PM PDT 24
Finished Jul 27 07:43:59 PM PDT 24
Peak memory 216696 kb
Host smart-883efa6c-3109-4858-b137-453332f15f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31441
56772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3144156772
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2804927726
Short name T1949
Test name
Test status
Simulation time 3790032481 ps
CPU time 38.8 seconds
Started Jul 27 07:43:09 PM PDT 24
Finished Jul 27 07:43:48 PM PDT 24
Peak memory 215556 kb
Host smart-053dc38c-74dd-4c09-a7ee-6d879d015c49
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2804927726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2804927726
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.1408231295
Short name T1130
Test name
Test status
Simulation time 169953636 ps
CPU time 0.9 seconds
Started Jul 27 07:43:09 PM PDT 24
Finished Jul 27 07:43:10 PM PDT 24
Peak memory 207172 kb
Host smart-9042c0ae-b234-4471-8381-d49cd0011c00
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1408231295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.1408231295
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1089485079
Short name T1359
Test name
Test status
Simulation time 142047017 ps
CPU time 0.87 seconds
Started Jul 27 07:43:09 PM PDT 24
Finished Jul 27 07:43:10 PM PDT 24
Peak memory 207100 kb
Host smart-1c1b5323-1872-49cc-8465-543769578245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
85079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1089485079
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1730184013
Short name T123
Test name
Test status
Simulation time 194820981 ps
CPU time 0.94 seconds
Started Jul 27 07:43:11 PM PDT 24
Finished Jul 27 07:43:12 PM PDT 24
Peak memory 205972 kb
Host smart-9d6be009-59e4-45e8-8392-8a58ab334b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17301
84013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1730184013
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.1107277797
Short name T1814
Test name
Test status
Simulation time 150196464 ps
CPU time 0.87 seconds
Started Jul 27 07:43:09 PM PDT 24
Finished Jul 27 07:43:10 PM PDT 24
Peak memory 207064 kb
Host smart-f7b3d85f-e1b5-467f-b1b7-013c078cd756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11072
77797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.1107277797
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3671258768
Short name T1584
Test name
Test status
Simulation time 184933882 ps
CPU time 0.88 seconds
Started Jul 27 07:43:13 PM PDT 24
Finished Jul 27 07:43:14 PM PDT 24
Peak memory 207108 kb
Host smart-c081d283-93ea-46cb-b93f-a7c2a7ff380b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36712
58768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3671258768
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1068988863
Short name T2696
Test name
Test status
Simulation time 152563840 ps
CPU time 0.83 seconds
Started Jul 27 07:43:10 PM PDT 24
Finished Jul 27 07:43:11 PM PDT 24
Peak memory 206992 kb
Host smart-1b9994df-b527-493f-9cdc-7d903ad876b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10689
88863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1068988863
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2449786738
Short name T1318
Test name
Test status
Simulation time 159210134 ps
CPU time 0.88 seconds
Started Jul 27 07:43:10 PM PDT 24
Finished Jul 27 07:43:11 PM PDT 24
Peak memory 207060 kb
Host smart-ecbe17a9-193f-46bd-8596-51cc96ec22b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24497
86738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2449786738
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.892497745
Short name T1456
Test name
Test status
Simulation time 218135342 ps
CPU time 0.99 seconds
Started Jul 27 07:43:10 PM PDT 24
Finished Jul 27 07:43:11 PM PDT 24
Peak memory 207036 kb
Host smart-183e4918-0218-4fff-bcb2-7c0b3d02433e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=892497745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.892497745
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3506009330
Short name T2712
Test name
Test status
Simulation time 146538340 ps
CPU time 0.82 seconds
Started Jul 27 07:43:13 PM PDT 24
Finished Jul 27 07:43:14 PM PDT 24
Peak memory 207104 kb
Host smart-819ebd71-1b57-454a-ae7c-a0d6468c572b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35060
09330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3506009330
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1872289226
Short name T1064
Test name
Test status
Simulation time 62182239 ps
CPU time 0.73 seconds
Started Jul 27 07:43:16 PM PDT 24
Finished Jul 27 07:43:17 PM PDT 24
Peak memory 207084 kb
Host smart-55a9800e-a45f-4fc3-9112-1ea91e32b485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18722
89226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1872289226
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1407897018
Short name T2367
Test name
Test status
Simulation time 13372658314 ps
CPU time 33.82 seconds
Started Jul 27 07:43:17 PM PDT 24
Finished Jul 27 07:43:50 PM PDT 24
Peak memory 220284 kb
Host smart-d7f1ef41-cead-481a-89e0-ebaaab6358ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14078
97018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1407897018
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3831685987
Short name T1310
Test name
Test status
Simulation time 187330715 ps
CPU time 0.89 seconds
Started Jul 27 07:43:16 PM PDT 24
Finished Jul 27 07:43:17 PM PDT 24
Peak memory 207140 kb
Host smart-091ae37c-3f86-40c6-900e-08e7cadff962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38316
85987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3831685987
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3571021194
Short name T795
Test name
Test status
Simulation time 207317084 ps
CPU time 0.92 seconds
Started Jul 27 07:43:25 PM PDT 24
Finished Jul 27 07:43:26 PM PDT 24
Peak memory 207076 kb
Host smart-8ddbfb50-0a70-47d7-abc4-8d0c7f775648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35710
21194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3571021194
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2743607064
Short name T883
Test name
Test status
Simulation time 180776164 ps
CPU time 0.89 seconds
Started Jul 27 07:43:18 PM PDT 24
Finished Jul 27 07:43:19 PM PDT 24
Peak memory 207160 kb
Host smart-863563bb-3205-42a6-bebc-67d533a78dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27436
07064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2743607064
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.2203117549
Short name T1278
Test name
Test status
Simulation time 191505950 ps
CPU time 1.02 seconds
Started Jul 27 07:43:19 PM PDT 24
Finished Jul 27 07:43:21 PM PDT 24
Peak memory 207100 kb
Host smart-60b85d94-7d23-4d9e-8d8a-556b6dd184d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22031
17549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2203117549
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2131381738
Short name T1822
Test name
Test status
Simulation time 183232212 ps
CPU time 0.87 seconds
Started Jul 27 07:43:14 PM PDT 24
Finished Jul 27 07:43:15 PM PDT 24
Peak memory 207124 kb
Host smart-90fe396a-5b50-43f1-b923-4cf181c3a8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21313
81738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2131381738
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.551095579
Short name T1815
Test name
Test status
Simulation time 188027277 ps
CPU time 0.89 seconds
Started Jul 27 07:43:22 PM PDT 24
Finished Jul 27 07:43:23 PM PDT 24
Peak memory 206988 kb
Host smart-7de08ba1-ed7c-4e7e-89cb-ffc9c25eb218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55109
5579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.551095579
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.4025863339
Short name T2815
Test name
Test status
Simulation time 183749910 ps
CPU time 0.88 seconds
Started Jul 27 07:43:16 PM PDT 24
Finished Jul 27 07:43:17 PM PDT 24
Peak memory 207068 kb
Host smart-e335538c-f841-49b6-b27e-293c4b104893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40258
63339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.4025863339
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1189687629
Short name T99
Test name
Test status
Simulation time 220159084 ps
CPU time 1.03 seconds
Started Jul 27 07:43:20 PM PDT 24
Finished Jul 27 07:43:21 PM PDT 24
Peak memory 207132 kb
Host smart-03f5901d-8256-427d-ad8e-b7496add3aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11896
87629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1189687629
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.1801779470
Short name T2604
Test name
Test status
Simulation time 4866823004 ps
CPU time 49.23 seconds
Started Jul 27 07:43:22 PM PDT 24
Finished Jul 27 07:44:11 PM PDT 24
Peak memory 215448 kb
Host smart-f3eb51c8-e71d-4c5f-883c-718df630d780
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1801779470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.1801779470
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1683664706
Short name T2756
Test name
Test status
Simulation time 171493928 ps
CPU time 0.94 seconds
Started Jul 27 07:43:20 PM PDT 24
Finished Jul 27 07:43:21 PM PDT 24
Peak memory 207116 kb
Host smart-3b400e1c-703b-4ccc-9b0f-e1db11990f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16836
64706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1683664706
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.3241045521
Short name T2349
Test name
Test status
Simulation time 205432464 ps
CPU time 0.99 seconds
Started Jul 27 07:43:25 PM PDT 24
Finished Jul 27 07:43:26 PM PDT 24
Peak memory 207072 kb
Host smart-fbd75863-4c05-4af8-8c70-fad18bb27d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32410
45521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3241045521
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.2253210281
Short name T29
Test name
Test status
Simulation time 804709075 ps
CPU time 2.04 seconds
Started Jul 27 07:43:18 PM PDT 24
Finished Jul 27 07:43:20 PM PDT 24
Peak memory 207048 kb
Host smart-f6b76edd-97e3-4578-a3d0-d81adaa03775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22532
10281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.2253210281
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3808610663
Short name T1920
Test name
Test status
Simulation time 4075648344 ps
CPU time 118 seconds
Started Jul 27 07:43:21 PM PDT 24
Finished Jul 27 07:45:19 PM PDT 24
Peak memory 215628 kb
Host smart-d6b2a9fe-2413-4d1c-9fc6-830946a5135a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38086
10663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3808610663
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.980742014
Short name T528
Test name
Test status
Simulation time 221934795 ps
CPU time 0.91 seconds
Started Jul 27 07:43:09 PM PDT 24
Finished Jul 27 07:43:10 PM PDT 24
Peak memory 207108 kb
Host smart-88391ca3-3fe4-42c7-be05-3d96aeb7ea81
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980742014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_host
_handshake.980742014
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.4097526459
Short name T2525
Test name
Test status
Simulation time 38240959 ps
CPU time 0.67 seconds
Started Jul 27 07:43:27 PM PDT 24
Finished Jul 27 07:43:28 PM PDT 24
Peak memory 207108 kb
Host smart-3b86a3ce-7597-4b1a-906e-8f895f636d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4097526459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.4097526459
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1946218427
Short name T1121
Test name
Test status
Simulation time 3711493441 ps
CPU time 6.12 seconds
Started Jul 27 07:43:18 PM PDT 24
Finished Jul 27 07:43:24 PM PDT 24
Peak memory 207388 kb
Host smart-1e6a54ae-7de2-4c59-b04d-aa1b820edb6e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946218427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_disconnect.1946218427
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2274326968
Short name T1448
Test name
Test status
Simulation time 13377453268 ps
CPU time 15.79 seconds
Started Jul 27 07:43:20 PM PDT 24
Finished Jul 27 07:43:36 PM PDT 24
Peak memory 207400 kb
Host smart-b835a5fb-85ec-46f3-8f64-7475cbcb094a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274326968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2274326968
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1841068216
Short name T1637
Test name
Test status
Simulation time 23363273409 ps
CPU time 30.63 seconds
Started Jul 27 07:43:17 PM PDT 24
Finished Jul 27 07:43:48 PM PDT 24
Peak memory 207348 kb
Host smart-ce08f3e2-988b-4eef-9026-8af72b935ebd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841068216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.1841068216
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3117699896
Short name T360
Test name
Test status
Simulation time 214383969 ps
CPU time 0.92 seconds
Started Jul 27 07:43:17 PM PDT 24
Finished Jul 27 07:43:18 PM PDT 24
Peak memory 207104 kb
Host smart-858d2a1c-3df0-4bbc-bc0a-d01ad7e00891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31176
99896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3117699896
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.152536757
Short name T64
Test name
Test status
Simulation time 212816535 ps
CPU time 0.9 seconds
Started Jul 27 07:43:19 PM PDT 24
Finished Jul 27 07:43:20 PM PDT 24
Peak memory 207064 kb
Host smart-27cc547d-cb88-4b86-b504-f83b729ed981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15253
6757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.152536757
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.901599056
Short name T2668
Test name
Test status
Simulation time 475608686 ps
CPU time 1.61 seconds
Started Jul 27 07:43:16 PM PDT 24
Finished Jul 27 07:43:18 PM PDT 24
Peak memory 207136 kb
Host smart-efef580c-8b69-499d-89ee-e470a39368a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90159
9056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.901599056
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.652246077
Short name T2577
Test name
Test status
Simulation time 930876036 ps
CPU time 2.85 seconds
Started Jul 27 07:43:21 PM PDT 24
Finished Jul 27 07:43:24 PM PDT 24
Peak memory 207228 kb
Host smart-fc0df17e-08e7-4d32-9715-99b31ed4b606
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=652246077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.652246077
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.117356636
Short name T2174
Test name
Test status
Simulation time 656167360 ps
CPU time 4.92 seconds
Started Jul 27 07:43:16 PM PDT 24
Finished Jul 27 07:43:21 PM PDT 24
Peak memory 207328 kb
Host smart-d35b7622-9360-48fc-8834-3d0d9af5bb7c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117356636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.117356636
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1910022765
Short name T1883
Test name
Test status
Simulation time 402057767 ps
CPU time 1.28 seconds
Started Jul 27 07:43:13 PM PDT 24
Finished Jul 27 07:43:15 PM PDT 24
Peak memory 207068 kb
Host smart-c7ddda33-37ac-470c-9665-0b405f485855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19100
22765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1910022765
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3541428580
Short name T375
Test name
Test status
Simulation time 161549717 ps
CPU time 0.86 seconds
Started Jul 27 07:43:20 PM PDT 24
Finished Jul 27 07:43:21 PM PDT 24
Peak memory 207064 kb
Host smart-fd102b46-cd7d-4915-8cc1-1b0817afb8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35414
28580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3541428580
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2565380326
Short name T1297
Test name
Test status
Simulation time 58449565 ps
CPU time 0.72 seconds
Started Jul 27 07:43:20 PM PDT 24
Finished Jul 27 07:43:21 PM PDT 24
Peak memory 207064 kb
Host smart-954713e9-9f38-48c4-b4fd-ac0610a71fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25653
80326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2565380326
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3419807578
Short name T1671
Test name
Test status
Simulation time 971822166 ps
CPU time 2.43 seconds
Started Jul 27 07:43:22 PM PDT 24
Finished Jul 27 07:43:24 PM PDT 24
Peak memory 207284 kb
Host smart-0a49b2d8-8785-41b9-b90a-2f2b6f1c8add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34198
07578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3419807578
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2957255083
Short name T1224
Test name
Test status
Simulation time 196432394 ps
CPU time 2.01 seconds
Started Jul 27 07:43:15 PM PDT 24
Finished Jul 27 07:43:17 PM PDT 24
Peak memory 207236 kb
Host smart-799cc9f4-5917-4095-99af-72ea9da1cb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29572
55083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2957255083
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.4290660251
Short name T1621
Test name
Test status
Simulation time 210483105 ps
CPU time 1.13 seconds
Started Jul 27 07:43:15 PM PDT 24
Finished Jul 27 07:43:16 PM PDT 24
Peak memory 215520 kb
Host smart-1b8f92e0-3787-4b31-a77b-509e8ab83a41
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4290660251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.4290660251
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1897545285
Short name T2484
Test name
Test status
Simulation time 144993971 ps
CPU time 0.89 seconds
Started Jul 27 07:43:16 PM PDT 24
Finished Jul 27 07:43:17 PM PDT 24
Peak memory 207316 kb
Host smart-8ada7f3e-a01f-41fc-b4e8-1056813af78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18975
45285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1897545285
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3039583980
Short name T222
Test name
Test status
Simulation time 216522415 ps
CPU time 0.98 seconds
Started Jul 27 07:43:15 PM PDT 24
Finished Jul 27 07:43:16 PM PDT 24
Peak memory 207016 kb
Host smart-eb1dfe1f-d6d3-4ad8-bafa-94972acf2d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30395
83980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3039583980
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.3366250148
Short name T1656
Test name
Test status
Simulation time 5912117507 ps
CPU time 46.35 seconds
Started Jul 27 07:43:15 PM PDT 24
Finished Jul 27 07:44:01 PM PDT 24
Peak memory 217148 kb
Host smart-653354e5-8b07-47ee-97de-fa5fbeabbfbc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3366250148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.3366250148
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.424484877
Short name T1142
Test name
Test status
Simulation time 242339623 ps
CPU time 1.03 seconds
Started Jul 27 07:43:25 PM PDT 24
Finished Jul 27 07:43:26 PM PDT 24
Peak memory 207072 kb
Host smart-ad75a9f6-f3aa-4a53-a6db-18041c6545fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42448
4877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.424484877
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.300934366
Short name T1139
Test name
Test status
Simulation time 23278426240 ps
CPU time 31.82 seconds
Started Jul 27 07:43:18 PM PDT 24
Finished Jul 27 07:43:50 PM PDT 24
Peak memory 207332 kb
Host smart-d5115d34-d60f-4bda-8deb-d72a6b1377d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30093
4366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.300934366
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.2403442395
Short name T992
Test name
Test status
Simulation time 3329630418 ps
CPU time 5.19 seconds
Started Jul 27 07:43:18 PM PDT 24
Finished Jul 27 07:43:23 PM PDT 24
Peak memory 207344 kb
Host smart-25858fec-c413-4998-a3a8-465581c69982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24034
42395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.2403442395
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.473434340
Short name T2330
Test name
Test status
Simulation time 4853944658 ps
CPU time 135.01 seconds
Started Jul 27 07:43:24 PM PDT 24
Finished Jul 27 07:45:39 PM PDT 24
Peak memory 215580 kb
Host smart-1e65cac3-0af0-4f13-8caf-01c5133da4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47343
4340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.473434340
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.2343268118
Short name T576
Test name
Test status
Simulation time 4824583944 ps
CPU time 39.58 seconds
Started Jul 27 07:43:27 PM PDT 24
Finished Jul 27 07:44:07 PM PDT 24
Peak memory 207380 kb
Host smart-bf79d0d3-286a-47ab-b590-7f94f7b93e46
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2343268118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.2343268118
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2914015835
Short name T1662
Test name
Test status
Simulation time 243136719 ps
CPU time 1.04 seconds
Started Jul 27 07:43:27 PM PDT 24
Finished Jul 27 07:43:28 PM PDT 24
Peak memory 207120 kb
Host smart-519043a5-fffc-420b-b14e-cbedb5c70fc3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2914015835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2914015835
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.459000894
Short name T1700
Test name
Test status
Simulation time 184992748 ps
CPU time 0.94 seconds
Started Jul 27 07:43:28 PM PDT 24
Finished Jul 27 07:43:29 PM PDT 24
Peak memory 207148 kb
Host smart-23656d86-e916-4a7c-b9b4-4bf143b6aa34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45900
0894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.459000894
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1135585007
Short name T2373
Test name
Test status
Simulation time 3790411272 ps
CPU time 31.72 seconds
Started Jul 27 07:43:26 PM PDT 24
Finished Jul 27 07:43:58 PM PDT 24
Peak memory 217228 kb
Host smart-651c253e-ee12-4d28-a1ee-efe6acda750c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11355
85007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1135585007
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.2431072372
Short name T164
Test name
Test status
Simulation time 5251098242 ps
CPU time 154.09 seconds
Started Jul 27 07:43:28 PM PDT 24
Finished Jul 27 07:46:02 PM PDT 24
Peak memory 215572 kb
Host smart-044a7d57-a6ed-4a23-b243-4227ebdbf966
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2431072372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.2431072372
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1960361946
Short name T1855
Test name
Test status
Simulation time 158069701 ps
CPU time 0.88 seconds
Started Jul 27 07:43:27 PM PDT 24
Finished Jul 27 07:43:28 PM PDT 24
Peak memory 207128 kb
Host smart-9803297b-c92b-4101-8855-cdb4a70e6200
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1960361946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1960361946
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2482074367
Short name T708
Test name
Test status
Simulation time 180906777 ps
CPU time 0.84 seconds
Started Jul 27 07:43:24 PM PDT 24
Finished Jul 27 07:43:24 PM PDT 24
Peak memory 207116 kb
Host smart-b6f98f08-e98f-4624-bb86-99571f3c52df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24820
74367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2482074367
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.976806578
Short name T120
Test name
Test status
Simulation time 218743903 ps
CPU time 0.98 seconds
Started Jul 27 07:43:28 PM PDT 24
Finished Jul 27 07:43:29 PM PDT 24
Peak memory 207136 kb
Host smart-f39937b9-9f72-41f2-8f6e-4cdd68a83000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97680
6578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.976806578
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.4240138815
Short name T1067
Test name
Test status
Simulation time 170332630 ps
CPU time 0.91 seconds
Started Jul 27 07:43:25 PM PDT 24
Finished Jul 27 07:43:26 PM PDT 24
Peak memory 207224 kb
Host smart-01e3a4ae-4e97-48e6-96c5-1f4eb7ee725e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42401
38815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.4240138815
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.654524091
Short name T909
Test name
Test status
Simulation time 196289806 ps
CPU time 0.96 seconds
Started Jul 27 07:43:29 PM PDT 24
Finished Jul 27 07:43:30 PM PDT 24
Peak memory 207100 kb
Host smart-78dce1ed-dc08-4888-b1c3-220cc3bef01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65452
4091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.654524091
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1221900302
Short name T2728
Test name
Test status
Simulation time 200861789 ps
CPU time 0.9 seconds
Started Jul 27 07:43:28 PM PDT 24
Finished Jul 27 07:43:29 PM PDT 24
Peak memory 207124 kb
Host smart-d177ca42-7659-4d4a-b88f-032fc1d9f5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12219
00302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1221900302
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.230460851
Short name T182
Test name
Test status
Simulation time 155845883 ps
CPU time 0.85 seconds
Started Jul 27 07:43:24 PM PDT 24
Finished Jul 27 07:43:25 PM PDT 24
Peak memory 207020 kb
Host smart-16996b06-4fb0-4ac9-bf66-d090da4e617e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23046
0851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.230460851
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.1697422187
Short name T1618
Test name
Test status
Simulation time 191943191 ps
CPU time 0.98 seconds
Started Jul 27 07:43:29 PM PDT 24
Finished Jul 27 07:43:31 PM PDT 24
Peak memory 207068 kb
Host smart-a5ec3ddc-1287-46af-81c2-f2fedecb2200
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1697422187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1697422187
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3647613916
Short name T2564
Test name
Test status
Simulation time 147791563 ps
CPU time 0.81 seconds
Started Jul 27 07:43:28 PM PDT 24
Finished Jul 27 07:43:29 PM PDT 24
Peak memory 207032 kb
Host smart-dfccc05a-90d0-43d9-9764-2ceca2a81627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36476
13916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3647613916
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1085431177
Short name T2633
Test name
Test status
Simulation time 53184922 ps
CPU time 0.73 seconds
Started Jul 27 07:43:27 PM PDT 24
Finished Jul 27 07:43:28 PM PDT 24
Peak memory 207064 kb
Host smart-a0dc0b99-7c21-4ed8-adb4-f82e0f3226d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10854
31177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1085431177
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.4189107706
Short name T1652
Test name
Test status
Simulation time 14818448360 ps
CPU time 36.49 seconds
Started Jul 27 07:43:25 PM PDT 24
Finished Jul 27 07:44:02 PM PDT 24
Peak memory 215480 kb
Host smart-43cc1752-be31-4504-ace5-3f2e0fadaf5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41891
07706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.4189107706
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2234735982
Short name T925
Test name
Test status
Simulation time 182246080 ps
CPU time 0.87 seconds
Started Jul 27 07:43:26 PM PDT 24
Finished Jul 27 07:43:27 PM PDT 24
Peak memory 207148 kb
Host smart-390a669f-4f64-4c06-b791-41e48016563f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22347
35982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2234735982
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1323650625
Short name T2721
Test name
Test status
Simulation time 165390979 ps
CPU time 0.89 seconds
Started Jul 27 07:43:24 PM PDT 24
Finished Jul 27 07:43:25 PM PDT 24
Peak memory 207092 kb
Host smart-924aa8e8-98a1-4552-8687-6ae7c0959f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13236
50625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1323650625
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.414977279
Short name T2576
Test name
Test status
Simulation time 263769322 ps
CPU time 1.06 seconds
Started Jul 27 07:43:29 PM PDT 24
Finished Jul 27 07:43:30 PM PDT 24
Peak memory 207156 kb
Host smart-8b62e12c-f60d-4fd1-866c-ed6b8aa0d576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41497
7279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.414977279
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.827493859
Short name T2276
Test name
Test status
Simulation time 148088711 ps
CPU time 0.85 seconds
Started Jul 27 07:43:25 PM PDT 24
Finished Jul 27 07:43:26 PM PDT 24
Peak memory 207100 kb
Host smart-ef3bbed9-6f44-4c2e-87a5-bad0ce754feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82749
3859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.827493859
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2406228433
Short name T2087
Test name
Test status
Simulation time 198746871 ps
CPU time 0.93 seconds
Started Jul 27 07:43:24 PM PDT 24
Finished Jul 27 07:43:25 PM PDT 24
Peak memory 207128 kb
Host smart-1eb4d841-425d-4075-b4ae-0322fd7bce8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24062
28433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2406228433
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1025526164
Short name T2324
Test name
Test status
Simulation time 211124590 ps
CPU time 0.91 seconds
Started Jul 27 07:43:27 PM PDT 24
Finished Jul 27 07:43:28 PM PDT 24
Peak memory 207040 kb
Host smart-67d58370-7276-4199-9673-bbb86eb03c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10255
26164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1025526164
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1743892922
Short name T1432
Test name
Test status
Simulation time 150350818 ps
CPU time 0.84 seconds
Started Jul 27 07:43:25 PM PDT 24
Finished Jul 27 07:43:26 PM PDT 24
Peak memory 207140 kb
Host smart-51d68177-bb8c-4d44-8700-5a5110b44aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17438
92922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1743892922
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2256936113
Short name T1284
Test name
Test status
Simulation time 214482817 ps
CPU time 1.07 seconds
Started Jul 27 07:43:29 PM PDT 24
Finished Jul 27 07:43:30 PM PDT 24
Peak memory 207100 kb
Host smart-b7dbef11-bf11-4ef3-b42e-adefa6d6c09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22569
36113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2256936113
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.385871606
Short name T1346
Test name
Test status
Simulation time 5788013021 ps
CPU time 42.99 seconds
Started Jul 27 07:43:27 PM PDT 24
Finished Jul 27 07:44:10 PM PDT 24
Peak memory 215544 kb
Host smart-e8a5586c-ecc9-4223-bb5e-c2d898f3d0eb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=385871606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.385871606
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1220558110
Short name T1035
Test name
Test status
Simulation time 148085227 ps
CPU time 0.82 seconds
Started Jul 27 07:43:28 PM PDT 24
Finished Jul 27 07:43:29 PM PDT 24
Peak memory 207144 kb
Host smart-e4dc3626-5481-46c1-af86-1169f1e6c3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12205
58110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1220558110
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1598925993
Short name T2529
Test name
Test status
Simulation time 167874767 ps
CPU time 0.93 seconds
Started Jul 27 07:43:27 PM PDT 24
Finished Jul 27 07:43:28 PM PDT 24
Peak memory 207128 kb
Host smart-f4622a5c-4d8d-4fa2-be8b-dbf3c55a6d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15989
25993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1598925993
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.3246349619
Short name T1641
Test name
Test status
Simulation time 860825970 ps
CPU time 2.13 seconds
Started Jul 27 07:43:24 PM PDT 24
Finished Jul 27 07:43:26 PM PDT 24
Peak memory 207352 kb
Host smart-6d1790e8-cfe9-48f3-94c1-16b86bea23d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32463
49619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.3246349619
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.11807064
Short name T2008
Test name
Test status
Simulation time 3884616610 ps
CPU time 29.14 seconds
Started Jul 27 07:43:28 PM PDT 24
Finished Jul 27 07:43:57 PM PDT 24
Peak memory 207312 kb
Host smart-92449097-35ec-4b4f-b669-2f77a7e90650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11807
064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.11807064
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.2211356431
Short name T1680
Test name
Test status
Simulation time 501725172 ps
CPU time 8.2 seconds
Started Jul 27 07:43:18 PM PDT 24
Finished Jul 27 07:43:26 PM PDT 24
Peak memory 207336 kb
Host smart-b9a32310-11b4-41b8-9b3b-3e15f048ac06
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211356431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.2211356431
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.2444827705
Short name T970
Test name
Test status
Simulation time 46856296 ps
CPU time 0.74 seconds
Started Jul 27 07:35:04 PM PDT 24
Finished Jul 27 07:35:05 PM PDT 24
Peak memory 207144 kb
Host smart-8cd0d644-f10b-4a77-bebf-bae766065eb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2444827705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2444827705
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.704778964
Short name T1060
Test name
Test status
Simulation time 4211036828 ps
CPU time 6 seconds
Started Jul 27 07:34:48 PM PDT 24
Finished Jul 27 07:34:54 PM PDT 24
Peak memory 207364 kb
Host smart-c695c786-54be-4a51-99f3-49c635e32b99
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704778964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon
_wake_disconnect.704778964
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3643932705
Short name T933
Test name
Test status
Simulation time 13353975873 ps
CPU time 15.07 seconds
Started Jul 27 07:34:51 PM PDT 24
Finished Jul 27 07:35:07 PM PDT 24
Peak memory 207348 kb
Host smart-210e8097-59da-47b1-a3ce-81008c1288fe
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643932705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3643932705
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2803591927
Short name T2556
Test name
Test status
Simulation time 23338370298 ps
CPU time 26.51 seconds
Started Jul 27 07:34:55 PM PDT 24
Finished Jul 27 07:35:22 PM PDT 24
Peak memory 207288 kb
Host smart-ed3f3161-7c65-4bc4-9236-022865ae5eda
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803591927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.2803591927
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2854375245
Short name T2551
Test name
Test status
Simulation time 235714732 ps
CPU time 0.96 seconds
Started Jul 27 07:34:51 PM PDT 24
Finished Jul 27 07:34:52 PM PDT 24
Peak memory 207144 kb
Host smart-ed5a760c-d736-48a1-ba9e-feb0e94b670a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28543
75245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2854375245
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.1028187865
Short name T563
Test name
Test status
Simulation time 149485377 ps
CPU time 0.85 seconds
Started Jul 27 07:34:52 PM PDT 24
Finished Jul 27 07:34:53 PM PDT 24
Peak memory 207036 kb
Host smart-31304782-12ca-4235-a599-b7e5a7317c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10281
87865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.1028187865
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.1162595733
Short name T405
Test name
Test status
Simulation time 430920631 ps
CPU time 1.48 seconds
Started Jul 27 07:34:56 PM PDT 24
Finished Jul 27 07:34:57 PM PDT 24
Peak memory 207028 kb
Host smart-f5870292-c531-4fc4-ac78-5867aea20e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11625
95733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.1162595733
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.4110386196
Short name T2810
Test name
Test status
Simulation time 709712077 ps
CPU time 1.83 seconds
Started Jul 27 07:34:56 PM PDT 24
Finished Jul 27 07:34:58 PM PDT 24
Peak memory 207060 kb
Host smart-0f9271de-3814-4f5f-b64f-2ac45e48984b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4110386196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.4110386196
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3694921271
Short name T2028
Test name
Test status
Simulation time 14984102207 ps
CPU time 33.81 seconds
Started Jul 27 07:34:52 PM PDT 24
Finished Jul 27 07:35:26 PM PDT 24
Peak memory 207352 kb
Host smart-e4f7bee2-af73-43f9-8884-530ae6c692cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36949
21271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3694921271
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.3707249183
Short name T2842
Test name
Test status
Simulation time 2323367813 ps
CPU time 14.56 seconds
Started Jul 27 07:34:55 PM PDT 24
Finished Jul 27 07:35:09 PM PDT 24
Peak memory 207252 kb
Host smart-c99ecbc6-9be5-48be-91f9-8fe1708cfe1d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707249183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.3707249183
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.644004949
Short name T1387
Test name
Test status
Simulation time 336311419 ps
CPU time 1.22 seconds
Started Jul 27 07:34:57 PM PDT 24
Finished Jul 27 07:34:58 PM PDT 24
Peak memory 207060 kb
Host smart-5a85378e-edd6-49fa-8546-81fdd0016741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64400
4949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.644004949
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2415346338
Short name T1909
Test name
Test status
Simulation time 223046916 ps
CPU time 0.86 seconds
Started Jul 27 07:34:52 PM PDT 24
Finished Jul 27 07:34:53 PM PDT 24
Peak memory 207040 kb
Host smart-f0f17553-e0fd-4085-9e8e-4fc9ae746f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24153
46338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2415346338
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2269662178
Short name T759
Test name
Test status
Simulation time 85807137 ps
CPU time 0.74 seconds
Started Jul 27 07:34:55 PM PDT 24
Finished Jul 27 07:34:56 PM PDT 24
Peak memory 207056 kb
Host smart-a542dd9f-c01b-4b27-9545-16cdeaee7d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22696
62178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2269662178
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.663487609
Short name T680
Test name
Test status
Simulation time 927840618 ps
CPU time 2.5 seconds
Started Jul 27 07:34:56 PM PDT 24
Finished Jul 27 07:34:59 PM PDT 24
Peak memory 207340 kb
Host smart-642e3bbd-6df8-4567-8b9f-395e9f977480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66348
7609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.663487609
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.149044693
Short name T1693
Test name
Test status
Simulation time 331939082 ps
CPU time 2.42 seconds
Started Jul 27 07:34:52 PM PDT 24
Finished Jul 27 07:34:54 PM PDT 24
Peak memory 207296 kb
Host smart-67eb3ace-0dd5-4cd4-94c6-57aad5511a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14904
4693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.149044693
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3966792591
Short name T712
Test name
Test status
Simulation time 156938782 ps
CPU time 0.83 seconds
Started Jul 27 07:34:52 PM PDT 24
Finished Jul 27 07:34:53 PM PDT 24
Peak memory 207128 kb
Host smart-46b2736b-ed6f-49d3-b907-a9b66f8038fc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3966792591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3966792591
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3154937435
Short name T1394
Test name
Test status
Simulation time 148135703 ps
CPU time 0.83 seconds
Started Jul 27 07:34:52 PM PDT 24
Finished Jul 27 07:34:53 PM PDT 24
Peak memory 207080 kb
Host smart-3c545eb6-e4d4-4222-8749-ba88f6235bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31549
37435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3154937435
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3046887856
Short name T2667
Test name
Test status
Simulation time 211796079 ps
CPU time 0.99 seconds
Started Jul 27 07:34:55 PM PDT 24
Finished Jul 27 07:34:57 PM PDT 24
Peak memory 207140 kb
Host smart-24b051f8-41a4-4e42-9f7c-ea39af6a8a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30468
87856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3046887856
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.2764795318
Short name T624
Test name
Test status
Simulation time 6021685867 ps
CPU time 48.87 seconds
Started Jul 27 07:34:52 PM PDT 24
Finished Jul 27 07:35:41 PM PDT 24
Peak memory 215496 kb
Host smart-658c6553-26f4-444f-9549-9ca716ad55c8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2764795318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.2764795318
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.3625838513
Short name T2001
Test name
Test status
Simulation time 7582707614 ps
CPU time 48.67 seconds
Started Jul 27 07:34:52 PM PDT 24
Finished Jul 27 07:35:41 PM PDT 24
Peak memory 207356 kb
Host smart-e0d5f1ad-e4f1-43ab-bdba-483e3ca03dc3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3625838513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.3625838513
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1744762861
Short name T2675
Test name
Test status
Simulation time 171877031 ps
CPU time 0.85 seconds
Started Jul 27 07:34:51 PM PDT 24
Finished Jul 27 07:34:52 PM PDT 24
Peak memory 207124 kb
Host smart-62ec1fbc-bd3b-4c37-9b56-28514192eee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17447
62861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1744762861
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.2623084896
Short name T1524
Test name
Test status
Simulation time 23352494761 ps
CPU time 28.6 seconds
Started Jul 27 07:34:56 PM PDT 24
Finished Jul 27 07:35:25 PM PDT 24
Peak memory 207384 kb
Host smart-6ee4a431-59a2-4bb1-a4d3-7321954d2780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26230
84896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.2623084896
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.3807730805
Short name T2199
Test name
Test status
Simulation time 3315064812 ps
CPU time 5.25 seconds
Started Jul 27 07:35:03 PM PDT 24
Finished Jul 27 07:35:08 PM PDT 24
Peak memory 207372 kb
Host smart-74452a32-c598-4c43-b259-cb7a53925b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38077
30805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.3807730805
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3403602790
Short name T2818
Test name
Test status
Simulation time 8841918716 ps
CPU time 253.38 seconds
Started Jul 27 07:35:01 PM PDT 24
Finished Jul 27 07:39:14 PM PDT 24
Peak memory 215668 kb
Host smart-24e6acbc-c696-4c95-b7cc-be04b2347ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34036
02790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3403602790
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.853797006
Short name T226
Test name
Test status
Simulation time 7108441182 ps
CPU time 52 seconds
Started Jul 27 07:34:58 PM PDT 24
Finished Jul 27 07:35:51 PM PDT 24
Peak memory 207448 kb
Host smart-e8062898-cc17-4a79-a02c-7ba478000d86
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=853797006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.853797006
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.318944854
Short name T387
Test name
Test status
Simulation time 243034206 ps
CPU time 1.05 seconds
Started Jul 27 07:34:59 PM PDT 24
Finished Jul 27 07:35:00 PM PDT 24
Peak memory 207140 kb
Host smart-5d38a58a-3f1c-4168-a0cc-18281554b80d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=318944854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.318944854
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1735836418
Short name T2156
Test name
Test status
Simulation time 232849933 ps
CPU time 0.98 seconds
Started Jul 27 07:34:59 PM PDT 24
Finished Jul 27 07:35:00 PM PDT 24
Peak memory 207136 kb
Host smart-ec7751dd-2226-437a-8fe4-3fb625341e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17358
36418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1735836418
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1902796653
Short name T1439
Test name
Test status
Simulation time 6362902404 ps
CPU time 61.39 seconds
Started Jul 27 07:34:58 PM PDT 24
Finished Jul 27 07:36:00 PM PDT 24
Peak memory 216988 kb
Host smart-12d6c404-0d03-47ee-b0b1-427eaec71a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19027
96653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1902796653
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.1347839529
Short name T810
Test name
Test status
Simulation time 2809843721 ps
CPU time 28.09 seconds
Started Jul 27 07:35:00 PM PDT 24
Finished Jul 27 07:35:29 PM PDT 24
Peak memory 215584 kb
Host smart-672d547f-3061-46b8-9a6c-ee4479316fdc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1347839529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.1347839529
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.2793996164
Short name T1690
Test name
Test status
Simulation time 152004592 ps
CPU time 0.83 seconds
Started Jul 27 07:34:56 PM PDT 24
Finished Jul 27 07:34:57 PM PDT 24
Peak memory 207132 kb
Host smart-d33bef65-7fc2-4bab-9710-4182a8331036
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2793996164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.2793996164
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.347198058
Short name T1265
Test name
Test status
Simulation time 178663598 ps
CPU time 0.89 seconds
Started Jul 27 07:35:01 PM PDT 24
Finished Jul 27 07:35:01 PM PDT 24
Peak memory 207124 kb
Host smart-3bf8ad4d-2fa4-49c1-aa3e-ca07a1cf536c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34719
8058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.347198058
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3721918892
Short name T147
Test name
Test status
Simulation time 185618268 ps
CPU time 0.87 seconds
Started Jul 27 07:34:58 PM PDT 24
Finished Jul 27 07:34:59 PM PDT 24
Peak memory 207124 kb
Host smart-57491c24-9cb9-44e7-8391-99216047d377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37219
18892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3721918892
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.4240934241
Short name T1167
Test name
Test status
Simulation time 194832131 ps
CPU time 0.87 seconds
Started Jul 27 07:35:00 PM PDT 24
Finished Jul 27 07:35:01 PM PDT 24
Peak memory 207136 kb
Host smart-59aa3b0e-15ff-4825-9928-5990516b6f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42409
34241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.4240934241
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.570264665
Short name T1178
Test name
Test status
Simulation time 162960395 ps
CPU time 0.85 seconds
Started Jul 27 07:34:57 PM PDT 24
Finished Jul 27 07:34:58 PM PDT 24
Peak memory 207120 kb
Host smart-03dc68b8-ac9e-4171-adbd-08cd56b9a309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57026
4665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.570264665
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2919820119
Short name T1517
Test name
Test status
Simulation time 187516850 ps
CPU time 0.89 seconds
Started Jul 27 07:34:57 PM PDT 24
Finished Jul 27 07:34:58 PM PDT 24
Peak memory 207108 kb
Host smart-0648580b-25c1-4e0f-9dea-b85c1afaac61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29198
20119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2919820119
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1517369704
Short name T1226
Test name
Test status
Simulation time 156099044 ps
CPU time 0.89 seconds
Started Jul 27 07:34:59 PM PDT 24
Finished Jul 27 07:35:00 PM PDT 24
Peak memory 207120 kb
Host smart-66689604-0422-4805-8100-4d99ebfe683f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15173
69704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1517369704
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.4100952347
Short name T2056
Test name
Test status
Simulation time 218178728 ps
CPU time 1.02 seconds
Started Jul 27 07:34:57 PM PDT 24
Finished Jul 27 07:34:58 PM PDT 24
Peak memory 207100 kb
Host smart-d494bc08-a25e-4606-aab7-0084fffd2f17
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4100952347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.4100952347
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3635556372
Short name T1132
Test name
Test status
Simulation time 148732930 ps
CPU time 0.83 seconds
Started Jul 27 07:35:03 PM PDT 24
Finished Jul 27 07:35:04 PM PDT 24
Peak memory 207084 kb
Host smart-26e69da1-eafc-4448-8273-2d9d34ae9ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36355
56372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3635556372
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.179933596
Short name T2032
Test name
Test status
Simulation time 37037747 ps
CPU time 0.7 seconds
Started Jul 27 07:35:00 PM PDT 24
Finished Jul 27 07:35:01 PM PDT 24
Peak memory 207064 kb
Host smart-e769d57f-92bd-4955-8c47-3a247681b5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17993
3596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.179933596
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.494644062
Short name T2744
Test name
Test status
Simulation time 14920407032 ps
CPU time 38.12 seconds
Started Jul 27 07:35:00 PM PDT 24
Finished Jul 27 07:35:39 PM PDT 24
Peak memory 215576 kb
Host smart-b0f16fe7-c66f-43a6-ad2a-1d5e361b5ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49464
4062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.494644062
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.247103727
Short name T1984
Test name
Test status
Simulation time 218008050 ps
CPU time 0.98 seconds
Started Jul 27 07:34:58 PM PDT 24
Finished Jul 27 07:34:59 PM PDT 24
Peak memory 207096 kb
Host smart-7d424349-f5ca-4c8d-9667-7729bb5ebf23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24710
3727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.247103727
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.4116782354
Short name T1153
Test name
Test status
Simulation time 259365756 ps
CPU time 1.07 seconds
Started Jul 27 07:34:58 PM PDT 24
Finished Jul 27 07:34:59 PM PDT 24
Peak memory 207076 kb
Host smart-7fcf954d-1cb5-4b35-b7f4-2ed35a0d1394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41167
82354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.4116782354
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1306329110
Short name T552
Test name
Test status
Simulation time 8321895145 ps
CPU time 155.35 seconds
Started Jul 27 07:34:59 PM PDT 24
Finished Jul 27 07:37:35 PM PDT 24
Peak memory 215580 kb
Host smart-9161ef99-dc1f-41c5-a7e8-19f1bf2f9086
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306329110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1306329110
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.4250302915
Short name T345
Test name
Test status
Simulation time 11106457281 ps
CPU time 80.78 seconds
Started Jul 27 07:34:57 PM PDT 24
Finished Jul 27 07:36:18 PM PDT 24
Peak memory 218200 kb
Host smart-c0bd04e7-fbcd-4bb1-968b-8cd1b5ffdadd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4250302915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.4250302915
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3481444772
Short name T520
Test name
Test status
Simulation time 11418459667 ps
CPU time 64.46 seconds
Started Jul 27 07:34:56 PM PDT 24
Finished Jul 27 07:36:01 PM PDT 24
Peak memory 217748 kb
Host smart-12bd7bb6-b573-4495-b4f6-f97278eb0e47
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481444772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3481444772
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.1494412654
Short name T1502
Test name
Test status
Simulation time 220244136 ps
CPU time 0.95 seconds
Started Jul 27 07:35:00 PM PDT 24
Finished Jul 27 07:35:01 PM PDT 24
Peak memory 207192 kb
Host smart-1ed63b5e-2857-4dc8-b3a4-256b47f30e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14944
12654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.1494412654
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1360633132
Short name T2639
Test name
Test status
Simulation time 234000216 ps
CPU time 1.01 seconds
Started Jul 27 07:34:58 PM PDT 24
Finished Jul 27 07:34:59 PM PDT 24
Peak memory 207072 kb
Host smart-71915e1c-b25d-4277-8168-1afb1887af93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13606
33132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1360633132
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2822592527
Short name T2699
Test name
Test status
Simulation time 210856701 ps
CPU time 0.93 seconds
Started Jul 27 07:35:00 PM PDT 24
Finished Jul 27 07:35:01 PM PDT 24
Peak memory 207120 kb
Host smart-bf78fc29-54cb-4627-bfeb-f53dcc382c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28225
92527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2822592527
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.310902466
Short name T817
Test name
Test status
Simulation time 164396401 ps
CPU time 0.88 seconds
Started Jul 27 07:34:57 PM PDT 24
Finished Jul 27 07:34:58 PM PDT 24
Peak memory 207100 kb
Host smart-4728955c-9fc3-4690-b98d-618071c68067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31090
2466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.310902466
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.441648555
Short name T2631
Test name
Test status
Simulation time 148423133 ps
CPU time 0.87 seconds
Started Jul 27 07:35:01 PM PDT 24
Finished Jul 27 07:35:02 PM PDT 24
Peak memory 207140 kb
Host smart-22bd1664-9eda-4225-85a0-16c4eac8f93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44164
8555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.441648555
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.353352795
Short name T2470
Test name
Test status
Simulation time 262670149 ps
CPU time 1.07 seconds
Started Jul 27 07:35:03 PM PDT 24
Finished Jul 27 07:35:04 PM PDT 24
Peak memory 207124 kb
Host smart-d278c871-2033-40dd-a8e1-32495a389486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35335
2795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.353352795
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.3363421429
Short name T415
Test name
Test status
Simulation time 4499229182 ps
CPU time 135.9 seconds
Started Jul 27 07:35:00 PM PDT 24
Finished Jul 27 07:37:16 PM PDT 24
Peak memory 215536 kb
Host smart-309f80de-e719-4adf-bab8-6250d14620fe
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3363421429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.3363421429
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1263376061
Short name T1599
Test name
Test status
Simulation time 183371308 ps
CPU time 0.95 seconds
Started Jul 27 07:35:03 PM PDT 24
Finished Jul 27 07:35:04 PM PDT 24
Peak memory 207112 kb
Host smart-b8af60e2-5a3d-4b0d-9675-f6255f69a3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12633
76061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1263376061
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1760130826
Short name T1642
Test name
Test status
Simulation time 182147818 ps
CPU time 1 seconds
Started Jul 27 07:35:04 PM PDT 24
Finished Jul 27 07:35:05 PM PDT 24
Peak memory 207092 kb
Host smart-248bff21-3238-40cd-8522-82bcf04fe028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17601
30826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1760130826
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.1003294786
Short name T1154
Test name
Test status
Simulation time 509015571 ps
CPU time 1.48 seconds
Started Jul 27 07:35:04 PM PDT 24
Finished Jul 27 07:35:05 PM PDT 24
Peak memory 207088 kb
Host smart-d2e76834-a74c-4d3c-ba3c-c2a51b9ae48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10032
94786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.1003294786
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2162388579
Short name T711
Test name
Test status
Simulation time 5151561689 ps
CPU time 37.83 seconds
Started Jul 27 07:35:02 PM PDT 24
Finished Jul 27 07:35:40 PM PDT 24
Peak memory 215548 kb
Host smart-c9addbc3-9c89-4caf-80f6-0037a78a336e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21623
88579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2162388579
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.1308603584
Short name T2621
Test name
Test status
Simulation time 885396322 ps
CPU time 5.67 seconds
Started Jul 27 07:34:52 PM PDT 24
Finished Jul 27 07:34:58 PM PDT 24
Peak memory 207364 kb
Host smart-b66e5dd6-210b-4919-a244-48fcc0dd9d88
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308603584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.1308603584
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.468670903
Short name T1661
Test name
Test status
Simulation time 32339001 ps
CPU time 0.69 seconds
Started Jul 27 07:35:17 PM PDT 24
Finished Jul 27 07:35:17 PM PDT 24
Peak memory 207232 kb
Host smart-25bfc321-22b2-44bb-8eaf-bad3030d69e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=468670903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.468670903
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.2095449231
Short name T2115
Test name
Test status
Simulation time 3547266777 ps
CPU time 5.95 seconds
Started Jul 27 07:35:05 PM PDT 24
Finished Jul 27 07:35:11 PM PDT 24
Peak memory 207368 kb
Host smart-bd2b1b5f-8eb4-4186-8098-cf6ac8a9aa31
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095449231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.2095449231
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.1332864222
Short name T2795
Test name
Test status
Simulation time 13381334703 ps
CPU time 15.94 seconds
Started Jul 27 07:35:05 PM PDT 24
Finished Jul 27 07:35:21 PM PDT 24
Peak memory 207404 kb
Host smart-b54dc9bb-2b98-42c0-ab0a-ee09690e53bb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332864222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.1332864222
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.1600563013
Short name T965
Test name
Test status
Simulation time 23375404738 ps
CPU time 30.72 seconds
Started Jul 27 07:35:03 PM PDT 24
Finished Jul 27 07:35:34 PM PDT 24
Peak memory 207424 kb
Host smart-b0a2fecd-f928-491c-850b-7d7e697e5907
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600563013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.1600563013
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3772979984
Short name T2074
Test name
Test status
Simulation time 179831330 ps
CPU time 0.9 seconds
Started Jul 27 07:35:04 PM PDT 24
Finished Jul 27 07:35:05 PM PDT 24
Peak memory 207076 kb
Host smart-859fc9e3-0045-45b8-b81f-06b92c044f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37729
79984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3772979984
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.3841472352
Short name T2791
Test name
Test status
Simulation time 157872853 ps
CPU time 0.86 seconds
Started Jul 27 07:35:13 PM PDT 24
Finished Jul 27 07:35:14 PM PDT 24
Peak memory 207228 kb
Host smart-9a55054e-a20a-435b-a190-75164cea65b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38414
72352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.3841472352
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.732267885
Short name T1766
Test name
Test status
Simulation time 311485760 ps
CPU time 1.18 seconds
Started Jul 27 07:35:05 PM PDT 24
Finished Jul 27 07:35:06 PM PDT 24
Peak memory 207192 kb
Host smart-70106d9b-fbce-43ae-9f9a-30a8f97bfea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73226
7885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.732267885
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3246749811
Short name T888
Test name
Test status
Simulation time 961384135 ps
CPU time 2.69 seconds
Started Jul 27 07:35:03 PM PDT 24
Finished Jul 27 07:35:06 PM PDT 24
Peak memory 207392 kb
Host smart-67f12a8a-e5f0-493e-ba2e-2174465ecc7c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3246749811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3246749811
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.3012253401
Short name T88
Test name
Test status
Simulation time 21379378528 ps
CPU time 43.85 seconds
Started Jul 27 07:35:12 PM PDT 24
Finished Jul 27 07:35:56 PM PDT 24
Peak memory 207324 kb
Host smart-a76ef660-fb9f-4816-975a-3c98a3895524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30122
53401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3012253401
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.3407543657
Short name T1013
Test name
Test status
Simulation time 1002736839 ps
CPU time 22.31 seconds
Started Jul 27 07:35:05 PM PDT 24
Finished Jul 27 07:35:27 PM PDT 24
Peak memory 207228 kb
Host smart-283bb00f-1a3c-4cef-9492-1d0266863033
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407543657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.3407543657
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3752887374
Short name T1891
Test name
Test status
Simulation time 365014152 ps
CPU time 1.23 seconds
Started Jul 27 07:35:03 PM PDT 24
Finished Jul 27 07:35:04 PM PDT 24
Peak memory 207292 kb
Host smart-df21ec35-e5c6-4ff3-94dd-5d73570ae1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37528
87374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3752887374
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2012263158
Short name T36
Test name
Test status
Simulation time 133216315 ps
CPU time 0.8 seconds
Started Jul 27 07:35:03 PM PDT 24
Finished Jul 27 07:35:04 PM PDT 24
Peak memory 207060 kb
Host smart-94a7d276-a6d3-4895-a1cf-49cdb2d7fece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20122
63158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2012263158
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3418294815
Short name T597
Test name
Test status
Simulation time 40887594 ps
CPU time 0.7 seconds
Started Jul 27 07:35:04 PM PDT 24
Finished Jul 27 07:35:05 PM PDT 24
Peak memory 207092 kb
Host smart-822a8fd6-10fb-4d79-aa6a-ab8c6fca4f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34182
94815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3418294815
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1413369444
Short name T1147
Test name
Test status
Simulation time 913287837 ps
CPU time 2.28 seconds
Started Jul 27 07:35:16 PM PDT 24
Finished Jul 27 07:35:18 PM PDT 24
Peak memory 207476 kb
Host smart-eebc269b-be68-47ee-bd2a-a0f26d48ab5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14133
69444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1413369444
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.656940397
Short name T18
Test name
Test status
Simulation time 322162529 ps
CPU time 2.17 seconds
Started Jul 27 07:35:03 PM PDT 24
Finished Jul 27 07:35:05 PM PDT 24
Peak memory 207172 kb
Host smart-b1ffbe5d-2bb5-48e0-9539-8564c2b5d7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65694
0397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.656940397
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.908499708
Short name T1452
Test name
Test status
Simulation time 199244700 ps
CPU time 1 seconds
Started Jul 27 07:35:03 PM PDT 24
Finished Jul 27 07:35:05 PM PDT 24
Peak memory 215524 kb
Host smart-b34c2129-ba8a-4654-8f5f-b70e4b18c68d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=908499708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.908499708
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1095086950
Short name T1740
Test name
Test status
Simulation time 159931090 ps
CPU time 0.85 seconds
Started Jul 27 07:35:11 PM PDT 24
Finished Jul 27 07:35:12 PM PDT 24
Peak memory 207228 kb
Host smart-4b2b3bef-5ca7-4f99-a2a6-71c2d44a03ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10950
86950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1095086950
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.4258204517
Short name T1024
Test name
Test status
Simulation time 193374761 ps
CPU time 0.92 seconds
Started Jul 27 07:35:16 PM PDT 24
Finished Jul 27 07:35:17 PM PDT 24
Peak memory 207256 kb
Host smart-396e771d-ff00-4f6e-af0a-c57e790212fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42582
04517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.4258204517
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.4184853840
Short name T500
Test name
Test status
Simulation time 9959878858 ps
CPU time 76.55 seconds
Started Jul 27 07:35:08 PM PDT 24
Finished Jul 27 07:36:24 PM PDT 24
Peak memory 215652 kb
Host smart-ea9f3900-51a5-4409-97ff-49333beb22dc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4184853840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.4184853840
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.1867142212
Short name T85
Test name
Test status
Simulation time 4340221738 ps
CPU time 45.91 seconds
Started Jul 27 07:35:04 PM PDT 24
Finished Jul 27 07:35:50 PM PDT 24
Peak memory 207316 kb
Host smart-c00fa5eb-d575-43be-be09-aeed9ac5679d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1867142212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.1867142212
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.3431591109
Short name T2447
Test name
Test status
Simulation time 209004499 ps
CPU time 0.96 seconds
Started Jul 27 07:35:12 PM PDT 24
Finished Jul 27 07:35:13 PM PDT 24
Peak memory 207260 kb
Host smart-ca869c7c-1cde-4a9e-97ed-76c43c351629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34315
91109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.3431591109
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.3772472619
Short name T562
Test name
Test status
Simulation time 23332067623 ps
CPU time 30.71 seconds
Started Jul 27 07:35:11 PM PDT 24
Finished Jul 27 07:35:42 PM PDT 24
Peak memory 207248 kb
Host smart-1fa5c850-6197-4317-bc40-7b82d3095d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37724
72619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.3772472619
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3727465133
Short name T1549
Test name
Test status
Simulation time 3335126133 ps
CPU time 5.27 seconds
Started Jul 27 07:35:10 PM PDT 24
Finished Jul 27 07:35:15 PM PDT 24
Peak memory 207368 kb
Host smart-104fff18-ad29-40bd-85d0-1ae85198e532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37274
65133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3727465133
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.2174895158
Short name T540
Test name
Test status
Simulation time 5829281565 ps
CPU time 41.52 seconds
Started Jul 27 07:35:22 PM PDT 24
Finished Jul 27 07:36:04 PM PDT 24
Peak memory 207268 kb
Host smart-a825e568-59c4-4753-85dd-c407d00ca55a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2174895158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.2174895158
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.1146673028
Short name T2550
Test name
Test status
Simulation time 255158005 ps
CPU time 1 seconds
Started Jul 27 07:35:11 PM PDT 24
Finished Jul 27 07:35:12 PM PDT 24
Peak memory 207084 kb
Host smart-7debaf7c-b290-43ea-83fa-a1c2b3b65abc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1146673028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.1146673028
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.4206056868
Short name T2736
Test name
Test status
Simulation time 252710052 ps
CPU time 0.99 seconds
Started Jul 27 07:35:10 PM PDT 24
Finished Jul 27 07:35:11 PM PDT 24
Peak memory 207104 kb
Host smart-553d5af1-cf32-41f6-be0e-fce88bd56f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42060
56868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.4206056868
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2522217314
Short name T2833
Test name
Test status
Simulation time 5033063210 ps
CPU time 150.25 seconds
Started Jul 27 07:35:10 PM PDT 24
Finished Jul 27 07:37:40 PM PDT 24
Peak memory 215524 kb
Host smart-de450faa-5b8f-4e15-96fc-7b81fc067015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25222
17314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2522217314
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.1065380561
Short name T1990
Test name
Test status
Simulation time 4155958956 ps
CPU time 116.2 seconds
Started Jul 27 07:35:12 PM PDT 24
Finished Jul 27 07:37:08 PM PDT 24
Peak memory 215524 kb
Host smart-a67ae0c4-5e0d-464e-92aa-99e0afb5bbd3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1065380561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.1065380561
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.3513401344
Short name T2656
Test name
Test status
Simulation time 177972903 ps
CPU time 0.9 seconds
Started Jul 27 07:35:11 PM PDT 24
Finished Jul 27 07:35:12 PM PDT 24
Peak memory 207024 kb
Host smart-ae3f3446-a09a-4d4d-b4ef-d791544d39ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3513401344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.3513401344
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3688473981
Short name T2163
Test name
Test status
Simulation time 153354706 ps
CPU time 0.88 seconds
Started Jul 27 07:35:10 PM PDT 24
Finished Jul 27 07:35:11 PM PDT 24
Peak memory 207160 kb
Host smart-df2336c7-0a56-4682-ab5d-a828ccbef187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36884
73981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3688473981
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.4056477332
Short name T124
Test name
Test status
Simulation time 214983190 ps
CPU time 0.97 seconds
Started Jul 27 07:35:10 PM PDT 24
Finished Jul 27 07:35:11 PM PDT 24
Peak memory 207144 kb
Host smart-4456fc42-f581-4b08-96e9-6d688c3da5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40564
77332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.4056477332
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1476684035
Short name T2778
Test name
Test status
Simulation time 173074209 ps
CPU time 0.95 seconds
Started Jul 27 07:35:16 PM PDT 24
Finished Jul 27 07:35:17 PM PDT 24
Peak memory 207024 kb
Host smart-60a5dab3-decd-44b2-8c6b-c39fe1067bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14766
84035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1476684035
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1625007927
Short name T2734
Test name
Test status
Simulation time 177526722 ps
CPU time 0.89 seconds
Started Jul 27 07:35:09 PM PDT 24
Finished Jul 27 07:35:10 PM PDT 24
Peak memory 207072 kb
Host smart-1d0a738d-2bb7-454f-aae4-de27a37cd4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16250
07927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1625007927
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2484512082
Short name T981
Test name
Test status
Simulation time 182973756 ps
CPU time 0.9 seconds
Started Jul 27 07:35:08 PM PDT 24
Finished Jul 27 07:35:09 PM PDT 24
Peak memory 207104 kb
Host smart-2197533e-47c7-463b-a52f-47c08416f827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24845
12082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2484512082
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.422787110
Short name T2702
Test name
Test status
Simulation time 168096040 ps
CPU time 0.86 seconds
Started Jul 27 07:35:11 PM PDT 24
Finished Jul 27 07:35:12 PM PDT 24
Peak memory 207192 kb
Host smart-9b0aeb28-a209-4a46-84f6-2c6cc03d8716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42278
7110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.422787110
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.3083090708
Short name T1192
Test name
Test status
Simulation time 239518635 ps
CPU time 1.05 seconds
Started Jul 27 07:35:14 PM PDT 24
Finished Jul 27 07:35:15 PM PDT 24
Peak memory 207156 kb
Host smart-4c9cd616-b939-4b26-b856-1796fe987da9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3083090708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.3083090708
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.762130613
Short name T2198
Test name
Test status
Simulation time 147250971 ps
CPU time 0.86 seconds
Started Jul 27 07:35:10 PM PDT 24
Finished Jul 27 07:35:11 PM PDT 24
Peak memory 207040 kb
Host smart-35c2a3ad-63b9-48e4-b5cb-3a3462edcadd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76213
0613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.762130613
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2023802085
Short name T1324
Test name
Test status
Simulation time 35928115 ps
CPU time 0.7 seconds
Started Jul 27 07:35:11 PM PDT 24
Finished Jul 27 07:35:12 PM PDT 24
Peak memory 207092 kb
Host smart-923914b9-092a-494b-bd3c-0155de4a36de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20238
02085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2023802085
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1830286609
Short name T2491
Test name
Test status
Simulation time 13559784483 ps
CPU time 32.91 seconds
Started Jul 27 07:35:12 PM PDT 24
Finished Jul 27 07:35:45 PM PDT 24
Peak memory 215584 kb
Host smart-f9aafa74-e54d-4192-b027-a263e7f04d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18302
86609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1830286609
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2045587071
Short name T1777
Test name
Test status
Simulation time 160949323 ps
CPU time 0.86 seconds
Started Jul 27 07:35:22 PM PDT 24
Finished Jul 27 07:35:23 PM PDT 24
Peak memory 207024 kb
Host smart-10002d37-5156-4485-8859-2d94087f6e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20455
87071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2045587071
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2610249183
Short name T2579
Test name
Test status
Simulation time 216104268 ps
CPU time 0.95 seconds
Started Jul 27 07:35:23 PM PDT 24
Finished Jul 27 07:35:24 PM PDT 24
Peak memory 207016 kb
Host smart-1c80d2cd-3c30-4c74-8435-2fbc2abfd72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102
49183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2610249183
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3534441420
Short name T2460
Test name
Test status
Simulation time 5676620306 ps
CPU time 38.8 seconds
Started Jul 27 07:35:27 PM PDT 24
Finished Jul 27 07:36:06 PM PDT 24
Peak memory 217380 kb
Host smart-9952f392-63ac-45de-bdd3-c545627d3258
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534441420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3534441420
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2806639845
Short name T176
Test name
Test status
Simulation time 13609045805 ps
CPU time 74.4 seconds
Started Jul 27 07:35:17 PM PDT 24
Finished Jul 27 07:36:31 PM PDT 24
Peak memory 218164 kb
Host smart-d0a8d9c4-df6f-48b7-9c16-98fd18ccdbc1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2806639845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2806639845
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.33726665
Short name T1411
Test name
Test status
Simulation time 19519847756 ps
CPU time 461.97 seconds
Started Jul 27 07:35:15 PM PDT 24
Finished Jul 27 07:42:57 PM PDT 24
Peak memory 215588 kb
Host smart-2c0cdeb7-cae8-45ac-a335-ab9df6c93241
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=33726665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.33726665
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.289939817
Short name T2532
Test name
Test status
Simulation time 244574617 ps
CPU time 0.98 seconds
Started Jul 27 07:35:12 PM PDT 24
Finished Jul 27 07:35:13 PM PDT 24
Peak memory 207108 kb
Host smart-dd85adb2-3905-4bc9-b53b-3ed9d259065d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28993
9817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.289939817
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3674665680
Short name T1002
Test name
Test status
Simulation time 173733048 ps
CPU time 0.96 seconds
Started Jul 27 07:35:16 PM PDT 24
Finished Jul 27 07:35:17 PM PDT 24
Peak memory 207140 kb
Host smart-7c825c04-6dde-428d-9c81-56942e55b6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36746
65680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3674665680
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.655981187
Short name T1692
Test name
Test status
Simulation time 171989973 ps
CPU time 0.85 seconds
Started Jul 27 07:35:20 PM PDT 24
Finished Jul 27 07:35:20 PM PDT 24
Peak memory 207128 kb
Host smart-ce334fa2-173f-4fa3-9b01-6c011a16726c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65598
1187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.655981187
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1871408522
Short name T1180
Test name
Test status
Simulation time 151866108 ps
CPU time 0.83 seconds
Started Jul 27 07:35:25 PM PDT 24
Finished Jul 27 07:35:26 PM PDT 24
Peak memory 206992 kb
Host smart-39a30ff6-5099-4b63-b15d-8dd80bc996da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18714
08522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1871408522
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.4091744257
Short name T275
Test name
Test status
Simulation time 163173713 ps
CPU time 0.89 seconds
Started Jul 27 07:35:18 PM PDT 24
Finished Jul 27 07:35:19 PM PDT 24
Peak memory 207068 kb
Host smart-563d8b9e-86d9-4b60-af6e-29fd87095ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40917
44257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.4091744257
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3971131250
Short name T2124
Test name
Test status
Simulation time 220251848 ps
CPU time 1 seconds
Started Jul 27 07:35:21 PM PDT 24
Finished Jul 27 07:35:23 PM PDT 24
Peak memory 207120 kb
Host smart-b585471f-a447-4ae1-8877-21e31a45c9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39711
31250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3971131250
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1038874823
Short name T1513
Test name
Test status
Simulation time 5810126969 ps
CPU time 48.15 seconds
Started Jul 27 07:35:16 PM PDT 24
Finished Jul 27 07:36:05 PM PDT 24
Peak memory 216980 kb
Host smart-45b94610-c749-4070-9058-65986438fac7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1038874823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1038874823
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2287911120
Short name T677
Test name
Test status
Simulation time 165630048 ps
CPU time 0.82 seconds
Started Jul 27 07:35:16 PM PDT 24
Finished Jul 27 07:35:17 PM PDT 24
Peak memory 207128 kb
Host smart-2046f888-8663-491c-8767-6c0e85c76cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22879
11120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2287911120
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2173919733
Short name T1464
Test name
Test status
Simulation time 172754025 ps
CPU time 0.95 seconds
Started Jul 27 07:35:16 PM PDT 24
Finished Jul 27 07:35:17 PM PDT 24
Peak memory 207092 kb
Host smart-3ec43ef2-0e83-4fb4-a940-eea68485a5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21739
19733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2173919733
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.3456894517
Short name T2478
Test name
Test status
Simulation time 919976881 ps
CPU time 2.2 seconds
Started Jul 27 07:35:16 PM PDT 24
Finished Jul 27 07:35:18 PM PDT 24
Peak memory 207260 kb
Host smart-937de5e9-b1f1-47c7-b0c6-8cc5127a636f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34568
94517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.3456894517
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3713410331
Short name T508
Test name
Test status
Simulation time 4136190590 ps
CPU time 122.32 seconds
Started Jul 27 07:35:19 PM PDT 24
Finished Jul 27 07:37:22 PM PDT 24
Peak memory 215600 kb
Host smart-1290013c-f70f-4bca-98e8-15746d54f9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37134
10331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3713410331
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.2597734199
Short name T2073
Test name
Test status
Simulation time 313048736 ps
CPU time 4.73 seconds
Started Jul 27 07:35:04 PM PDT 24
Finished Jul 27 07:35:09 PM PDT 24
Peak memory 207312 kb
Host smart-53ccdc69-b0c2-445c-99d7-8a5c5df1abd5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597734199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host
_handshake.2597734199
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.1102214476
Short name T2015
Test name
Test status
Simulation time 74476516 ps
CPU time 0.72 seconds
Started Jul 27 07:35:36 PM PDT 24
Finished Jul 27 07:35:37 PM PDT 24
Peak memory 207100 kb
Host smart-55202e21-1852-4eed-bd6d-a30dbb863574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1102214476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.1102214476
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.907826068
Short name T9
Test name
Test status
Simulation time 4417712792 ps
CPU time 6.67 seconds
Started Jul 27 07:35:21 PM PDT 24
Finished Jul 27 07:35:27 PM PDT 24
Peak memory 207416 kb
Host smart-5abc3f14-6e0a-4ce5-bf5b-bd9b99c0d632
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907826068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon
_wake_disconnect.907826068
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2070263340
Short name T2496
Test name
Test status
Simulation time 13579077158 ps
CPU time 15.51 seconds
Started Jul 27 07:35:16 PM PDT 24
Finished Jul 27 07:35:32 PM PDT 24
Peak memory 207412 kb
Host smart-53b23e94-b83b-4777-9e96-9f1dfa272c6f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070263340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2070263340
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.1154673946
Short name T2847
Test name
Test status
Simulation time 23325319504 ps
CPU time 26.29 seconds
Started Jul 27 07:35:17 PM PDT 24
Finished Jul 27 07:35:43 PM PDT 24
Peak memory 207328 kb
Host smart-e5b2f4f5-041c-4204-8da6-29aa96386ff9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154673946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.1154673946
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3870962092
Short name T101
Test name
Test status
Simulation time 175423036 ps
CPU time 0.87 seconds
Started Jul 27 07:35:25 PM PDT 24
Finished Jul 27 07:35:26 PM PDT 24
Peak memory 207028 kb
Host smart-94c931e2-0f81-4406-b1d4-07876848a4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38709
62092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3870962092
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1491294396
Short name T1258
Test name
Test status
Simulation time 147222018 ps
CPU time 0.9 seconds
Started Jul 27 07:35:15 PM PDT 24
Finished Jul 27 07:35:16 PM PDT 24
Peak memory 207188 kb
Host smart-6b1fd553-433f-43da-9a8a-5cf640d67f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14912
94396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1491294396
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3368720429
Short name T2501
Test name
Test status
Simulation time 518723127 ps
CPU time 1.87 seconds
Started Jul 27 07:35:25 PM PDT 24
Finished Jul 27 07:35:27 PM PDT 24
Peak memory 207156 kb
Host smart-7eb0091d-8bb6-4104-ad6b-da9b52f624e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33687
20429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3368720429
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.1417723496
Short name T2311
Test name
Test status
Simulation time 1318194636 ps
CPU time 3.39 seconds
Started Jul 27 07:35:24 PM PDT 24
Finished Jul 27 07:35:28 PM PDT 24
Peak memory 207316 kb
Host smart-ac782775-cbaa-4722-9320-6971cd56b3e7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1417723496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.1417723496
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.1436088311
Short name T1503
Test name
Test status
Simulation time 20710414427 ps
CPU time 46.12 seconds
Started Jul 27 07:35:24 PM PDT 24
Finished Jul 27 07:36:10 PM PDT 24
Peak memory 207368 kb
Host smart-52581faf-5687-466f-a953-3eb6224db26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14360
88311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.1436088311
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.179742488
Short name T250
Test name
Test status
Simulation time 4338125417 ps
CPU time 29.77 seconds
Started Jul 27 07:35:25 PM PDT 24
Finished Jul 27 07:35:55 PM PDT 24
Peak memory 207340 kb
Host smart-4682f073-d24a-4a8f-bdf6-daa7398b2a2c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179742488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.179742488
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.3997656884
Short name T221
Test name
Test status
Simulation time 306225381 ps
CPU time 1.23 seconds
Started Jul 27 07:35:22 PM PDT 24
Finished Jul 27 07:35:24 PM PDT 24
Peak memory 207060 kb
Host smart-599f549e-39a0-481c-b3a1-5c862b7222b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39976
56884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.3997656884
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3138448315
Short name T2860
Test name
Test status
Simulation time 182506349 ps
CPU time 0.81 seconds
Started Jul 27 07:35:29 PM PDT 24
Finished Jul 27 07:35:30 PM PDT 24
Peak memory 207092 kb
Host smart-36b4fc9e-3411-46d0-a557-13261faa788c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31384
48315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3138448315
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2343078421
Short name T771
Test name
Test status
Simulation time 108900402 ps
CPU time 0.76 seconds
Started Jul 27 07:35:24 PM PDT 24
Finished Jul 27 07:35:25 PM PDT 24
Peak memory 207072 kb
Host smart-cc978849-0392-4556-b36b-392ce924e988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23430
78421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2343078421
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1498908716
Short name T914
Test name
Test status
Simulation time 890960039 ps
CPU time 2.35 seconds
Started Jul 27 07:35:23 PM PDT 24
Finished Jul 27 07:35:26 PM PDT 24
Peak memory 207280 kb
Host smart-5073bf67-84bb-4bce-8f12-ae7b62c66f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14989
08716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1498908716
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1831735429
Short name T2685
Test name
Test status
Simulation time 220703778 ps
CPU time 2.07 seconds
Started Jul 27 07:35:24 PM PDT 24
Finished Jul 27 07:35:26 PM PDT 24
Peak memory 207260 kb
Host smart-8b34e098-aeae-464b-8da6-44f42e717fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18317
35429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1831735429
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.1802845763
Short name T1463
Test name
Test status
Simulation time 224373217 ps
CPU time 1.06 seconds
Started Jul 27 07:35:24 PM PDT 24
Finished Jul 27 07:35:25 PM PDT 24
Peak memory 207324 kb
Host smart-136b7dcb-f775-4b9f-adc9-26a2254841cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1802845763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.1802845763
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2177542062
Short name T2308
Test name
Test status
Simulation time 147097579 ps
CPU time 0.79 seconds
Started Jul 27 07:35:23 PM PDT 24
Finished Jul 27 07:35:24 PM PDT 24
Peak memory 207108 kb
Host smart-816a62cb-0f77-4c15-bc37-72c62a2af06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21775
42062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2177542062
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.728540071
Short name T2707
Test name
Test status
Simulation time 193596105 ps
CPU time 0.9 seconds
Started Jul 27 07:35:23 PM PDT 24
Finished Jul 27 07:35:24 PM PDT 24
Peak memory 207088 kb
Host smart-0b6283dc-9375-4e3e-89f8-bfe1fadcd6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72854
0071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.728540071
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.505849209
Short name T1921
Test name
Test status
Simulation time 9871265199 ps
CPU time 285.85 seconds
Started Jul 27 07:35:24 PM PDT 24
Finished Jul 27 07:40:10 PM PDT 24
Peak memory 215564 kb
Host smart-5c8aa3a0-121f-4e38-882e-17ae56db623a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=505849209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.505849209
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.18669993
Short name T1352
Test name
Test status
Simulation time 15758954600 ps
CPU time 103.94 seconds
Started Jul 27 07:35:26 PM PDT 24
Finished Jul 27 07:37:10 PM PDT 24
Peak memory 207328 kb
Host smart-5072fc41-e7b6-4e7b-be66-bf42b24091c6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=18669993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.18669993
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.901733129
Short name T2767
Test name
Test status
Simulation time 203474626 ps
CPU time 0.94 seconds
Started Jul 27 07:35:28 PM PDT 24
Finished Jul 27 07:35:29 PM PDT 24
Peak memory 207220 kb
Host smart-50978943-02a9-4570-bafd-efb623c7f565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90173
3129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.901733129
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.1265895567
Short name T840
Test name
Test status
Simulation time 23293474683 ps
CPU time 34.1 seconds
Started Jul 27 07:35:24 PM PDT 24
Finished Jul 27 07:35:59 PM PDT 24
Peak memory 207348 kb
Host smart-679cf49e-f8a4-48e4-8de4-f8deeced685e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12658
95567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.1265895567
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.811561517
Short name T1974
Test name
Test status
Simulation time 3389700371 ps
CPU time 5.09 seconds
Started Jul 27 07:35:24 PM PDT 24
Finished Jul 27 07:35:29 PM PDT 24
Peak memory 207356 kb
Host smart-b644347f-7ea0-4aab-a479-408dce710ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81156
1517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.811561517
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.3760917441
Short name T1675
Test name
Test status
Simulation time 5722263564 ps
CPU time 43.98 seconds
Started Jul 27 07:35:24 PM PDT 24
Finished Jul 27 07:36:08 PM PDT 24
Peak memory 223636 kb
Host smart-7cc99689-831f-4e0d-9fac-c060598596e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37609
17441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3760917441
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.525203967
Short name T155
Test name
Test status
Simulation time 4019654573 ps
CPU time 39.33 seconds
Started Jul 27 07:35:24 PM PDT 24
Finished Jul 27 07:36:04 PM PDT 24
Peak memory 216896 kb
Host smart-a9e20418-5fed-4cdb-b887-7b233e110684
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=525203967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.525203967
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2897890600
Short name T1382
Test name
Test status
Simulation time 244155315 ps
CPU time 0.95 seconds
Started Jul 27 07:35:25 PM PDT 24
Finished Jul 27 07:35:26 PM PDT 24
Peak memory 207144 kb
Host smart-ce1ed068-4eae-4827-a42c-03fb8b87d5e8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2897890600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2897890600
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2788523007
Short name T2536
Test name
Test status
Simulation time 195234012 ps
CPU time 0.91 seconds
Started Jul 27 07:35:25 PM PDT 24
Finished Jul 27 07:35:26 PM PDT 24
Peak memory 207164 kb
Host smart-1d3d09ca-b014-4126-bfc4-a5e3c63e5cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27885
23007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2788523007
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1955140800
Short name T1450
Test name
Test status
Simulation time 5876715083 ps
CPU time 167.53 seconds
Started Jul 27 07:35:28 PM PDT 24
Finished Jul 27 07:38:16 PM PDT 24
Peak memory 215632 kb
Host smart-c30122a4-4eec-4650-95b1-ecc067fe048c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19551
40800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1955140800
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.2064035113
Short name T2503
Test name
Test status
Simulation time 5637117254 ps
CPU time 57.49 seconds
Started Jul 27 07:35:23 PM PDT 24
Finished Jul 27 07:36:21 PM PDT 24
Peak memory 207384 kb
Host smart-55ee8de6-f0a2-49bb-87e0-e86a12d013eb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2064035113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.2064035113
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.706766191
Short name T1273
Test name
Test status
Simulation time 190922955 ps
CPU time 0.96 seconds
Started Jul 27 07:35:30 PM PDT 24
Finished Jul 27 07:35:31 PM PDT 24
Peak memory 207136 kb
Host smart-908b0f8e-913f-4397-be4b-889659805585
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=706766191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.706766191
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1014035918
Short name T672
Test name
Test status
Simulation time 176796815 ps
CPU time 0.88 seconds
Started Jul 27 07:35:25 PM PDT 24
Finished Jul 27 07:35:26 PM PDT 24
Peak memory 207092 kb
Host smart-5874930e-d9f0-4461-8477-45341a10ed3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10140
35918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1014035918
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.654910436
Short name T2251
Test name
Test status
Simulation time 186959337 ps
CPU time 0.9 seconds
Started Jul 27 07:35:28 PM PDT 24
Finished Jul 27 07:35:29 PM PDT 24
Peak memory 207216 kb
Host smart-cb0b8a7c-a936-4473-9ef0-28e042b8b650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65491
0436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.654910436
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.957236308
Short name T1644
Test name
Test status
Simulation time 193138660 ps
CPU time 0.96 seconds
Started Jul 27 07:35:30 PM PDT 24
Finished Jul 27 07:35:31 PM PDT 24
Peak memory 207108 kb
Host smart-87996546-c8fd-465c-8d7a-3f7863da4b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95723
6308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.957236308
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.452165023
Short name T1218
Test name
Test status
Simulation time 204261955 ps
CPU time 0.87 seconds
Started Jul 27 07:35:28 PM PDT 24
Finished Jul 27 07:35:29 PM PDT 24
Peak memory 207112 kb
Host smart-538621d9-2e50-4994-b3c7-282b6cb47802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45216
5023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.452165023
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2985215334
Short name T1807
Test name
Test status
Simulation time 185531578 ps
CPU time 0.9 seconds
Started Jul 27 07:35:32 PM PDT 24
Finished Jul 27 07:35:33 PM PDT 24
Peak memory 207140 kb
Host smart-bdc1b1a3-d526-4d44-bb63-6df99f7d69a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29852
15334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2985215334
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3416829733
Short name T1767
Test name
Test status
Simulation time 157349443 ps
CPU time 0.84 seconds
Started Jul 27 07:35:33 PM PDT 24
Finished Jul 27 07:35:34 PM PDT 24
Peak memory 207120 kb
Host smart-159b1f7a-39ee-4591-ac73-a6fc064a2c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34168
29733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3416829733
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.2824015937
Short name T428
Test name
Test status
Simulation time 240447684 ps
CPU time 1.03 seconds
Started Jul 27 07:35:33 PM PDT 24
Finished Jul 27 07:35:34 PM PDT 24
Peak memory 207148 kb
Host smart-c77485c2-e09d-4b55-b332-71d90606a60e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2824015937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.2824015937
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.3994868468
Short name T524
Test name
Test status
Simulation time 157443031 ps
CPU time 0.82 seconds
Started Jul 27 07:35:28 PM PDT 24
Finished Jul 27 07:35:29 PM PDT 24
Peak memory 207060 kb
Host smart-dff9ccb9-4410-4450-bac7-0c240de424a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39948
68468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.3994868468
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.109857414
Short name T1889
Test name
Test status
Simulation time 63256106 ps
CPU time 0.7 seconds
Started Jul 27 07:35:33 PM PDT 24
Finished Jul 27 07:35:34 PM PDT 24
Peak memory 207088 kb
Host smart-60ce24e4-ebbb-455d-a4bb-9a9f7b62d37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10985
7414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.109857414
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.550730714
Short name T1719
Test name
Test status
Simulation time 13293943565 ps
CPU time 35.46 seconds
Started Jul 27 07:35:28 PM PDT 24
Finished Jul 27 07:36:04 PM PDT 24
Peak memory 215588 kb
Host smart-dc1e9bfc-96e4-4aae-8c28-d480e16994f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55073
0714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.550730714
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1633956154
Short name T41
Test name
Test status
Simulation time 175664396 ps
CPU time 0.87 seconds
Started Jul 27 07:35:29 PM PDT 24
Finished Jul 27 07:35:30 PM PDT 24
Peak memory 207140 kb
Host smart-041f4018-1724-4cb3-afdf-6769c6d5a329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16339
56154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1633956154
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1440415082
Short name T2692
Test name
Test status
Simulation time 153342966 ps
CPU time 0.86 seconds
Started Jul 27 07:35:28 PM PDT 24
Finished Jul 27 07:35:29 PM PDT 24
Peak memory 207112 kb
Host smart-102eeb77-3c5c-4344-b2d2-ae457c807c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14404
15082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1440415082
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.2987623174
Short name T2414
Test name
Test status
Simulation time 7884457853 ps
CPU time 52.69 seconds
Started Jul 27 07:35:29 PM PDT 24
Finished Jul 27 07:36:21 PM PDT 24
Peak memory 216904 kb
Host smart-8da85979-a986-4ff9-b35d-8bafefcf9b07
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987623174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.2987623174
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.340683482
Short name T2710
Test name
Test status
Simulation time 11063053792 ps
CPU time 221.46 seconds
Started Jul 27 07:35:32 PM PDT 24
Finished Jul 27 07:39:13 PM PDT 24
Peak memory 215552 kb
Host smart-0b421113-cc26-4802-b276-485c99523664
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=340683482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.340683482
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2533708411
Short name T1928
Test name
Test status
Simulation time 12743483171 ps
CPU time 98.62 seconds
Started Jul 27 07:35:36 PM PDT 24
Finished Jul 27 07:37:15 PM PDT 24
Peak memory 223784 kb
Host smart-97d8db52-9dfa-4f26-ab5b-b1202a3d73d0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533708411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2533708411
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3348397940
Short name T548
Test name
Test status
Simulation time 232973217 ps
CPU time 1.02 seconds
Started Jul 27 07:35:29 PM PDT 24
Finished Jul 27 07:35:30 PM PDT 24
Peak memory 207096 kb
Host smart-7249ceaf-20f1-4b70-b59b-a9725c1a5d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33483
97940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3348397940
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2908799830
Short name T2518
Test name
Test status
Simulation time 178548890 ps
CPU time 0.88 seconds
Started Jul 27 07:35:28 PM PDT 24
Finished Jul 27 07:35:29 PM PDT 24
Peak memory 207108 kb
Host smart-7965d621-c40a-44a5-af1c-fa26ae454a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29087
99830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2908799830
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.3339194072
Short name T2355
Test name
Test status
Simulation time 152764033 ps
CPU time 0.85 seconds
Started Jul 27 07:35:33 PM PDT 24
Finished Jul 27 07:35:34 PM PDT 24
Peak memory 207104 kb
Host smart-1d11a47c-a7bc-4bb8-8418-fd7aa5bd9dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33391
94072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3339194072
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.682567005
Short name T2108
Test name
Test status
Simulation time 160525071 ps
CPU time 0.79 seconds
Started Jul 27 07:35:29 PM PDT 24
Finished Jul 27 07:35:29 PM PDT 24
Peak memory 207056 kb
Host smart-01965c3a-e12b-4cab-af3d-c0bbbbfd8952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68256
7005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.682567005
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.4082858326
Short name T363
Test name
Test status
Simulation time 168813013 ps
CPU time 0.82 seconds
Started Jul 27 07:35:33 PM PDT 24
Finished Jul 27 07:35:34 PM PDT 24
Peak memory 207124 kb
Host smart-95659042-d106-47be-925a-792c5257b609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40828
58326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.4082858326
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2765026416
Short name T2709
Test name
Test status
Simulation time 252733438 ps
CPU time 1.12 seconds
Started Jul 27 07:35:35 PM PDT 24
Finished Jul 27 07:35:37 PM PDT 24
Peak memory 207036 kb
Host smart-a6755900-5cc6-4c34-8f7f-072c4a625706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27650
26416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2765026416
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2921668426
Short name T2705
Test name
Test status
Simulation time 5429569142 ps
CPU time 53.92 seconds
Started Jul 27 07:35:36 PM PDT 24
Finished Jul 27 07:36:30 PM PDT 24
Peak memory 215512 kb
Host smart-e6772813-5a1d-4f0b-b914-4ec4f05f7211
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2921668426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2921668426
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1645325312
Short name T773
Test name
Test status
Simulation time 155567760 ps
CPU time 0.85 seconds
Started Jul 27 07:35:36 PM PDT 24
Finished Jul 27 07:35:37 PM PDT 24
Peak memory 207144 kb
Host smart-bdd7774f-9605-44d3-9eaa-767e9b2a01c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16453
25312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1645325312
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2897426884
Short name T452
Test name
Test status
Simulation time 142068896 ps
CPU time 0.78 seconds
Started Jul 27 07:35:34 PM PDT 24
Finished Jul 27 07:35:35 PM PDT 24
Peak memory 207128 kb
Host smart-83f7e242-c7c2-4d4a-8304-da06ce9eb2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28974
26884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2897426884
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.2343719309
Short name T1109
Test name
Test status
Simulation time 819157967 ps
CPU time 2.02 seconds
Started Jul 27 07:35:34 PM PDT 24
Finished Jul 27 07:35:36 PM PDT 24
Peak memory 207096 kb
Host smart-ef42d002-ac17-407f-8ffe-b7d2d2850423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23437
19309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2343719309
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.1041890315
Short name T1447
Test name
Test status
Simulation time 7585416192 ps
CPU time 58.55 seconds
Started Jul 27 07:35:36 PM PDT 24
Finished Jul 27 07:36:34 PM PDT 24
Peak memory 207272 kb
Host smart-e9ea79ca-0d3d-40f6-a51b-86348feb8a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10418
90315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1041890315
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.490792141
Short name T2540
Test name
Test status
Simulation time 182918474 ps
CPU time 0.94 seconds
Started Jul 27 07:35:23 PM PDT 24
Finished Jul 27 07:35:24 PM PDT 24
Peak memory 207004 kb
Host smart-b107102f-c254-4c33-a706-7ac7abb740b4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490792141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host_
handshake.490792141
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.74786564
Short name T1046
Test name
Test status
Simulation time 35668470 ps
CPU time 0.65 seconds
Started Jul 27 07:35:51 PM PDT 24
Finished Jul 27 07:35:52 PM PDT 24
Peak memory 207052 kb
Host smart-b90e520e-da21-44fd-8058-0975e75c7f08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=74786564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.74786564
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.710322482
Short name T2425
Test name
Test status
Simulation time 3533511766 ps
CPU time 4.87 seconds
Started Jul 27 07:35:36 PM PDT 24
Finished Jul 27 07:35:41 PM PDT 24
Peak memory 207380 kb
Host smart-4b057ddd-9f03-44db-b5e2-689efc09b155
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710322482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon
_wake_disconnect.710322482
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.929401864
Short name T758
Test name
Test status
Simulation time 13408925862 ps
CPU time 15.37 seconds
Started Jul 27 07:35:35 PM PDT 24
Finished Jul 27 07:35:51 PM PDT 24
Peak memory 207376 kb
Host smart-d283363e-d9f7-4fe9-bbc0-47a6fdf21072
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=929401864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.929401864
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.4153997806
Short name T2544
Test name
Test status
Simulation time 23375895358 ps
CPU time 29.73 seconds
Started Jul 27 07:35:37 PM PDT 24
Finished Jul 27 07:36:07 PM PDT 24
Peak memory 207364 kb
Host smart-54570c13-5e2b-4284-8a8d-7c07f765d42c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153997806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.4153997806
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.4171009433
Short name T1732
Test name
Test status
Simulation time 171249687 ps
CPU time 0.98 seconds
Started Jul 27 07:35:40 PM PDT 24
Finished Jul 27 07:35:41 PM PDT 24
Peak memory 207144 kb
Host smart-da9bee76-29d8-4a1d-9d39-7f184970b4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41710
09433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.4171009433
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2291653814
Short name T1945
Test name
Test status
Simulation time 222905572 ps
CPU time 0.9 seconds
Started Jul 27 07:35:36 PM PDT 24
Finished Jul 27 07:35:37 PM PDT 24
Peak memory 207084 kb
Host smart-8b85db53-bb92-492a-a8d9-7f38be42a6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22916
53814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2291653814
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.1675329981
Short name T747
Test name
Test status
Simulation time 286558179 ps
CPU time 1.15 seconds
Started Jul 27 07:35:35 PM PDT 24
Finished Jul 27 07:35:37 PM PDT 24
Peak memory 207068 kb
Host smart-bedfe73f-193c-49b8-a1b6-804e2e431c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16753
29981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.1675329981
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2554595132
Short name T665
Test name
Test status
Simulation time 1291661686 ps
CPU time 3.31 seconds
Started Jul 27 07:35:37 PM PDT 24
Finished Jul 27 07:35:40 PM PDT 24
Peak memory 207364 kb
Host smart-f5f46c95-5be9-419a-bc97-59575ce57060
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2554595132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2554595132
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.3215632573
Short name T87
Test name
Test status
Simulation time 19950556523 ps
CPU time 42.63 seconds
Started Jul 27 07:35:35 PM PDT 24
Finished Jul 27 07:36:18 PM PDT 24
Peak memory 207432 kb
Host smart-7df17e35-56f6-46c2-82e7-c14b9575e0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32156
32573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.3215632573
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.2599695071
Short name T1790
Test name
Test status
Simulation time 306604362 ps
CPU time 4.41 seconds
Started Jul 27 07:35:37 PM PDT 24
Finished Jul 27 07:35:42 PM PDT 24
Peak memory 207356 kb
Host smart-eab311d0-9526-49dd-b4aa-9d0505309be4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599695071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.2599695071
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.3248266193
Short name T1104
Test name
Test status
Simulation time 403643137 ps
CPU time 1.44 seconds
Started Jul 27 07:35:40 PM PDT 24
Finished Jul 27 07:35:41 PM PDT 24
Peak memory 207112 kb
Host smart-1e11c637-8f40-454b-9879-1a6724951f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32482
66193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.3248266193
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.3671033673
Short name T378
Test name
Test status
Simulation time 141118168 ps
CPU time 0.8 seconds
Started Jul 27 07:35:33 PM PDT 24
Finished Jul 27 07:35:34 PM PDT 24
Peak memory 207092 kb
Host smart-c25567a3-5dca-4f29-98cc-f2449c25802e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36710
33673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.3671033673
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.1477416156
Short name T426
Test name
Test status
Simulation time 75149236 ps
CPU time 0.75 seconds
Started Jul 27 07:35:34 PM PDT 24
Finished Jul 27 07:35:35 PM PDT 24
Peak memory 207056 kb
Host smart-451bac0d-f49b-41e0-805b-4fa019db1a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14774
16156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1477416156
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3144070849
Short name T1836
Test name
Test status
Simulation time 929584548 ps
CPU time 2.65 seconds
Started Jul 27 07:35:35 PM PDT 24
Finished Jul 27 07:35:38 PM PDT 24
Peak memory 207340 kb
Host smart-b5d0ece1-ea55-4bb0-96fc-99b218f08496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31440
70849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3144070849
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.853327875
Short name T2649
Test name
Test status
Simulation time 261588706 ps
CPU time 2.01 seconds
Started Jul 27 07:35:35 PM PDT 24
Finished Jul 27 07:35:38 PM PDT 24
Peak memory 207288 kb
Host smart-3e38d2b1-140d-42f7-8deb-42032fac13e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85332
7875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.853327875
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.490942429
Short name T2063
Test name
Test status
Simulation time 199004014 ps
CPU time 1.1 seconds
Started Jul 27 07:35:36 PM PDT 24
Finished Jul 27 07:35:37 PM PDT 24
Peak memory 215520 kb
Host smart-a3c9ebbc-151a-4c3a-9fdf-9a90d1db9ad5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=490942429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.490942429
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.4052974566
Short name T1119
Test name
Test status
Simulation time 144728647 ps
CPU time 0.84 seconds
Started Jul 27 07:35:38 PM PDT 24
Finished Jul 27 07:35:39 PM PDT 24
Peak memory 207068 kb
Host smart-40d5d4f6-609f-4dae-b58d-6f0fb75974d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40529
74566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.4052974566
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1929880873
Short name T1208
Test name
Test status
Simulation time 264226402 ps
CPU time 1.04 seconds
Started Jul 27 07:35:36 PM PDT 24
Finished Jul 27 07:35:37 PM PDT 24
Peak memory 207120 kb
Host smart-87a19699-3064-43a3-acec-e21f594e7d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19298
80873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1929880873
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.2949530143
Short name T2411
Test name
Test status
Simulation time 5909593868 ps
CPU time 46.04 seconds
Started Jul 27 07:35:34 PM PDT 24
Finished Jul 27 07:36:20 PM PDT 24
Peak memory 216928 kb
Host smart-863df66f-c86a-4aa2-869a-ed710f7862bd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2949530143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.2949530143
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.3793734700
Short name T110
Test name
Test status
Simulation time 10181261451 ps
CPU time 118.92 seconds
Started Jul 27 07:35:38 PM PDT 24
Finished Jul 27 07:37:37 PM PDT 24
Peak memory 207320 kb
Host smart-5bf9c458-7b18-48e0-bdae-32364ae85786
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3793734700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.3793734700
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.4173355506
Short name T598
Test name
Test status
Simulation time 224395208 ps
CPU time 0.96 seconds
Started Jul 27 07:35:35 PM PDT 24
Finished Jul 27 07:35:36 PM PDT 24
Peak memory 207096 kb
Host smart-e879cd7a-55cd-4453-8646-5e2f7f0ceb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41733
55506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.4173355506
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.3382489607
Short name T2641
Test name
Test status
Simulation time 23331617743 ps
CPU time 27.54 seconds
Started Jul 27 07:35:45 PM PDT 24
Finished Jul 27 07:36:13 PM PDT 24
Peak memory 207344 kb
Host smart-9e12cacd-aa4e-443a-a0df-8af184b0b94e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33824
89607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3382489607
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1025942195
Short name T547
Test name
Test status
Simulation time 3297871151 ps
CPU time 4.94 seconds
Started Jul 27 07:35:43 PM PDT 24
Finished Jul 27 07:35:48 PM PDT 24
Peak memory 207360 kb
Host smart-e6cd4a78-a90d-44c6-b63e-3dedbbc97f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10259
42195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1025942195
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3916922809
Short name T1711
Test name
Test status
Simulation time 8624516706 ps
CPU time 63.88 seconds
Started Jul 27 07:35:43 PM PDT 24
Finished Jul 27 07:36:47 PM PDT 24
Peak memory 217584 kb
Host smart-14fdfed5-4973-40d9-a2ef-a70c6ea1d909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39169
22809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3916922809
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.2029976136
Short name T1941
Test name
Test status
Simulation time 5741083375 ps
CPU time 168.15 seconds
Started Jul 27 07:35:44 PM PDT 24
Finished Jul 27 07:38:33 PM PDT 24
Peak memory 223452 kb
Host smart-ffb9a47b-75db-4270-b1d2-07587d911f59
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2029976136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.2029976136
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.3544280089
Short name T1171
Test name
Test status
Simulation time 255443801 ps
CPU time 1.01 seconds
Started Jul 27 07:35:42 PM PDT 24
Finished Jul 27 07:35:44 PM PDT 24
Peak memory 207104 kb
Host smart-68a61a25-d048-44eb-9f0d-2b61c2001d42
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3544280089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.3544280089
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2243021932
Short name T2799
Test name
Test status
Simulation time 209781987 ps
CPU time 0.92 seconds
Started Jul 27 07:35:43 PM PDT 24
Finished Jul 27 07:35:44 PM PDT 24
Peak memory 207064 kb
Host smart-18b52319-ecf3-4393-a013-eaf11734421c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22430
21932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2243021932
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.1756160830
Short name T1930
Test name
Test status
Simulation time 3342666864 ps
CPU time 34.26 seconds
Started Jul 27 07:35:43 PM PDT 24
Finished Jul 27 07:36:17 PM PDT 24
Peak memory 215608 kb
Host smart-107f0f0f-bdc6-45b7-8f3d-fdad0181cc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17561
60830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1756160830
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1660162424
Short name T340
Test name
Test status
Simulation time 5465938369 ps
CPU time 57.76 seconds
Started Jul 27 07:35:42 PM PDT 24
Finished Jul 27 07:36:40 PM PDT 24
Peak memory 216892 kb
Host smart-9ed07730-e12b-4550-ad94-1963c6a74a9a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1660162424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1660162424
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3660837778
Short name T1296
Test name
Test status
Simulation time 164124617 ps
CPU time 0.87 seconds
Started Jul 27 07:35:42 PM PDT 24
Finished Jul 27 07:35:43 PM PDT 24
Peak memory 207140 kb
Host smart-d0e66c80-70d3-4e64-addd-61c7dcde8053
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3660837778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3660837778
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.721896038
Short name T1627
Test name
Test status
Simulation time 156355838 ps
CPU time 0.8 seconds
Started Jul 27 07:35:43 PM PDT 24
Finished Jul 27 07:35:44 PM PDT 24
Peak memory 207112 kb
Host smart-be9bd9cf-3584-4282-a1c8-3b75fe67bd12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72189
6038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.721896038
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.357419317
Short name T126
Test name
Test status
Simulation time 204093705 ps
CPU time 0.93 seconds
Started Jul 27 07:35:43 PM PDT 24
Finished Jul 27 07:35:44 PM PDT 24
Peak memory 207120 kb
Host smart-5504885d-eb15-48c5-9308-3bdc5e5b909b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35741
9317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.357419317
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.926798086
Short name T2456
Test name
Test status
Simulation time 171042681 ps
CPU time 0.9 seconds
Started Jul 27 07:35:45 PM PDT 24
Finished Jul 27 07:35:47 PM PDT 24
Peak memory 207156 kb
Host smart-9e4adfa5-dff6-4b96-9c14-b1b2784133db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92679
8086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.926798086
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2379089519
Short name T1542
Test name
Test status
Simulation time 194799458 ps
CPU time 0.89 seconds
Started Jul 27 07:35:43 PM PDT 24
Finished Jul 27 07:35:44 PM PDT 24
Peak memory 207112 kb
Host smart-a046a251-e16a-4774-bcce-2bcac791f968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790
89519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2379089519
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2916764584
Short name T889
Test name
Test status
Simulation time 195709599 ps
CPU time 0.93 seconds
Started Jul 27 07:35:43 PM PDT 24
Finished Jul 27 07:35:44 PM PDT 24
Peak memory 207140 kb
Host smart-88c47da7-50bb-4073-b452-b15125e9f4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29167
64584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2916764584
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1129114769
Short name T177
Test name
Test status
Simulation time 164990859 ps
CPU time 0.86 seconds
Started Jul 27 07:35:43 PM PDT 24
Finished Jul 27 07:35:43 PM PDT 24
Peak memory 207020 kb
Host smart-614311f1-0918-49f1-933a-8a9110f13017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11291
14769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1129114769
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.466317256
Short name T1274
Test name
Test status
Simulation time 267270450 ps
CPU time 1.13 seconds
Started Jul 27 07:35:45 PM PDT 24
Finished Jul 27 07:35:46 PM PDT 24
Peak memory 207104 kb
Host smart-2c65c38f-c8a3-4c6d-81fd-94dc1681cfbd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=466317256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.466317256
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2197849347
Short name T444
Test name
Test status
Simulation time 184137641 ps
CPU time 0.84 seconds
Started Jul 27 07:35:41 PM PDT 24
Finished Jul 27 07:35:42 PM PDT 24
Peak memory 207068 kb
Host smart-9ef82ed0-d6c2-4c07-bfef-739511ef3f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21978
49347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2197849347
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2842519673
Short name T1958
Test name
Test status
Simulation time 28847065 ps
CPU time 0.7 seconds
Started Jul 27 07:35:43 PM PDT 24
Finished Jul 27 07:35:44 PM PDT 24
Peak memory 207048 kb
Host smart-fe7798c8-f73c-44eb-b268-8ab0fe6a1123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28425
19673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2842519673
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1024269160
Short name T1666
Test name
Test status
Simulation time 7724145148 ps
CPU time 20.42 seconds
Started Jul 27 07:35:44 PM PDT 24
Finished Jul 27 07:36:04 PM PDT 24
Peak memory 220140 kb
Host smart-3f356ecc-f291-4ffb-882f-ca0eee545e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10242
69160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1024269160
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.497588904
Short name T2657
Test name
Test status
Simulation time 202128209 ps
CPU time 0.99 seconds
Started Jul 27 07:35:46 PM PDT 24
Finished Jul 27 07:35:47 PM PDT 24
Peak memory 207144 kb
Host smart-72986aed-265d-42e8-bf83-6512640c79aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49758
8904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.497588904
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3257610481
Short name T1057
Test name
Test status
Simulation time 198290461 ps
CPU time 0.91 seconds
Started Jul 27 07:35:45 PM PDT 24
Finished Jul 27 07:35:46 PM PDT 24
Peak memory 207064 kb
Host smart-0dbe3d56-886d-483a-9053-4dcebd9bc59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32576
10481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3257610481
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1940760507
Short name T2731
Test name
Test status
Simulation time 6869880474 ps
CPU time 179.62 seconds
Started Jul 27 07:35:46 PM PDT 24
Finished Jul 27 07:38:45 PM PDT 24
Peak memory 215584 kb
Host smart-4e0a95c3-24c1-4018-bf66-fbc2f3ddf7dc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940760507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1940760507
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.4141952017
Short name T2290
Test name
Test status
Simulation time 16279304263 ps
CPU time 124.13 seconds
Started Jul 27 07:35:45 PM PDT 24
Finished Jul 27 07:37:49 PM PDT 24
Peak memory 218344 kb
Host smart-ae8c9591-d571-4293-a773-83d12abaf35a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4141952017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.4141952017
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.2284621384
Short name T566
Test name
Test status
Simulation time 12943883028 ps
CPU time 103.04 seconds
Started Jul 27 07:35:44 PM PDT 24
Finished Jul 27 07:37:27 PM PDT 24
Peak memory 217392 kb
Host smart-453b0235-3c76-418c-b75d-474af067fddb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284621384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2284621384
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1295271596
Short name T2607
Test name
Test status
Simulation time 209895388 ps
CPU time 0.99 seconds
Started Jul 27 07:35:46 PM PDT 24
Finished Jul 27 07:35:47 PM PDT 24
Peak memory 207096 kb
Host smart-bc5a2a77-bbec-4177-8553-f29b690dc172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12952
71596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1295271596
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.3402098831
Short name T1294
Test name
Test status
Simulation time 176158607 ps
CPU time 0.85 seconds
Started Jul 27 07:35:41 PM PDT 24
Finished Jul 27 07:35:42 PM PDT 24
Peak memory 207104 kb
Host smart-fa08d17a-b84b-4a40-a400-17601b5d8ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34020
98831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.3402098831
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1539453970
Short name T2703
Test name
Test status
Simulation time 161005212 ps
CPU time 0.87 seconds
Started Jul 27 07:35:42 PM PDT 24
Finished Jul 27 07:35:43 PM PDT 24
Peak memory 207328 kb
Host smart-e98c042b-07dd-4670-8806-3daedc9e1d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15394
53970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1539453970
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2419114367
Short name T443
Test name
Test status
Simulation time 152022773 ps
CPU time 0.83 seconds
Started Jul 27 07:35:43 PM PDT 24
Finished Jul 27 07:35:44 PM PDT 24
Peak memory 207152 kb
Host smart-76ecf36a-5561-46fc-9acc-18d2d449a5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24191
14367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2419114367
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1892299439
Short name T1120
Test name
Test status
Simulation time 149025392 ps
CPU time 0.83 seconds
Started Jul 27 07:35:50 PM PDT 24
Finished Jul 27 07:35:51 PM PDT 24
Peak memory 207140 kb
Host smart-43c1bb8d-c98a-4ebe-a07b-3e917e82786d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18922
99439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1892299439
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2276794905
Short name T1605
Test name
Test status
Simulation time 203065871 ps
CPU time 1 seconds
Started Jul 27 07:35:49 PM PDT 24
Finished Jul 27 07:35:50 PM PDT 24
Peak memory 207112 kb
Host smart-1017e86f-aa90-4485-b0bd-629b964dfaba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22767
94905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2276794905
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.473703308
Short name T945
Test name
Test status
Simulation time 4426835440 ps
CPU time 43.91 seconds
Started Jul 27 07:35:49 PM PDT 24
Finished Jul 27 07:36:34 PM PDT 24
Peak memory 217116 kb
Host smart-1da8d285-5ea7-4652-b92d-cab1b5b59cb5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=473703308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.473703308
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3800467447
Short name T923
Test name
Test status
Simulation time 177827016 ps
CPU time 0.87 seconds
Started Jul 27 07:35:49 PM PDT 24
Finished Jul 27 07:35:50 PM PDT 24
Peak memory 207104 kb
Host smart-8882fe96-4d36-4540-a30f-b90b318a5ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38004
67447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3800467447
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.917982890
Short name T1967
Test name
Test status
Simulation time 195898579 ps
CPU time 0.88 seconds
Started Jul 27 07:35:49 PM PDT 24
Finished Jul 27 07:35:50 PM PDT 24
Peak memory 207184 kb
Host smart-8deb075b-9ec4-4d49-8c76-abac7a354be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91798
2890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.917982890
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2653395534
Short name T1246
Test name
Test status
Simulation time 414163365 ps
CPU time 1.25 seconds
Started Jul 27 07:35:53 PM PDT 24
Finished Jul 27 07:35:55 PM PDT 24
Peak memory 207100 kb
Host smart-b58070c8-def8-420d-8a17-a7ea3787a69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26533
95534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2653395534
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.2379698130
Short name T2081
Test name
Test status
Simulation time 7496973548 ps
CPU time 211.47 seconds
Started Jul 27 07:35:50 PM PDT 24
Finished Jul 27 07:39:21 PM PDT 24
Peak memory 215576 kb
Host smart-cabc0f19-749b-4b64-893d-c65a084c892f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23796
98130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.2379698130
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.1452181871
Short name T1948
Test name
Test status
Simulation time 1126831289 ps
CPU time 25.91 seconds
Started Jul 27 07:35:40 PM PDT 24
Finished Jul 27 07:36:06 PM PDT 24
Peak memory 207384 kb
Host smart-0e9a91b3-c3cf-421d-aa52-b5884836847e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452181871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.1452181871
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.974984417
Short name T498
Test name
Test status
Simulation time 41335798 ps
CPU time 0.74 seconds
Started Jul 27 07:36:01 PM PDT 24
Finished Jul 27 07:36:02 PM PDT 24
Peak memory 207156 kb
Host smart-c21d9236-60de-4f52-88fe-791d78e6b286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=974984417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.974984417
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3381348038
Short name T1602
Test name
Test status
Simulation time 13317001978 ps
CPU time 15.29 seconds
Started Jul 27 07:35:52 PM PDT 24
Finished Jul 27 07:36:08 PM PDT 24
Peak memory 207424 kb
Host smart-877273e4-b99e-4670-81db-6c7bd68e04ac
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381348038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3381348038
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.2319099657
Short name T1531
Test name
Test status
Simulation time 23359033948 ps
CPU time 30.16 seconds
Started Jul 27 07:35:51 PM PDT 24
Finished Jul 27 07:36:21 PM PDT 24
Peak memory 207344 kb
Host smart-caf7081f-9d3a-4cb2-aca3-bd629151f9b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319099657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.2319099657
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3493981638
Short name T1844
Test name
Test status
Simulation time 187119661 ps
CPU time 0.88 seconds
Started Jul 27 07:35:52 PM PDT 24
Finished Jul 27 07:35:53 PM PDT 24
Peak memory 207140 kb
Host smart-d232c755-5667-4b3a-a996-ad720c6b0fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34939
81638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3493981638
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.4190452921
Short name T990
Test name
Test status
Simulation time 150306976 ps
CPU time 0.85 seconds
Started Jul 27 07:35:54 PM PDT 24
Finished Jul 27 07:35:55 PM PDT 24
Peak memory 207100 kb
Host smart-b924e76d-d76e-496d-a52f-3f5ee4290326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41904
52921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.4190452921
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.626128280
Short name T1145
Test name
Test status
Simulation time 232474467 ps
CPU time 1 seconds
Started Jul 27 07:35:50 PM PDT 24
Finished Jul 27 07:35:51 PM PDT 24
Peak memory 207088 kb
Host smart-8ff98a03-7019-4ab1-ade8-f66b94427765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62612
8280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.626128280
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3053326821
Short name T2686
Test name
Test status
Simulation time 1395408584 ps
CPU time 3.5 seconds
Started Jul 27 07:35:54 PM PDT 24
Finished Jul 27 07:35:58 PM PDT 24
Peak memory 207348 kb
Host smart-30739384-ad9e-4d73-95e8-c0706df6ad92
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3053326821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3053326821
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.3344784369
Short name T1365
Test name
Test status
Simulation time 10812716113 ps
CPU time 25.29 seconds
Started Jul 27 07:35:54 PM PDT 24
Finished Jul 27 07:36:19 PM PDT 24
Peak memory 207396 kb
Host smart-f0da496d-6a44-4fca-a898-d0d81a3925d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33447
84369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.3344784369
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.3040938583
Short name T1687
Test name
Test status
Simulation time 1558502164 ps
CPU time 9.93 seconds
Started Jul 27 07:35:51 PM PDT 24
Finished Jul 27 07:36:01 PM PDT 24
Peak memory 207372 kb
Host smart-76c9b570-0e39-4e4e-b57f-c346db2f1578
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040938583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.3040938583
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.2319580057
Short name T1194
Test name
Test status
Simulation time 467599843 ps
CPU time 1.53 seconds
Started Jul 27 07:35:53 PM PDT 24
Finished Jul 27 07:35:55 PM PDT 24
Peak memory 207160 kb
Host smart-0a7e0488-162d-4549-984f-32e2766d0689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23195
80057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.2319580057
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.3987097229
Short name T1199
Test name
Test status
Simulation time 158913382 ps
CPU time 0.82 seconds
Started Jul 27 07:36:00 PM PDT 24
Finished Jul 27 07:36:01 PM PDT 24
Peak memory 207164 kb
Host smart-c39c48fa-2f63-4c59-a774-ba51541ed34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39870
97229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.3987097229
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2574356096
Short name T1134
Test name
Test status
Simulation time 41995242 ps
CPU time 0.72 seconds
Started Jul 27 07:35:56 PM PDT 24
Finished Jul 27 07:35:57 PM PDT 24
Peak memory 207108 kb
Host smart-1b706d1f-d99f-4520-bc21-59f887944a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25743
56096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2574356096
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2928464602
Short name T533
Test name
Test status
Simulation time 799362910 ps
CPU time 2.27 seconds
Started Jul 27 07:35:55 PM PDT 24
Finished Jul 27 07:35:58 PM PDT 24
Peak memory 207328 kb
Host smart-81b65b5b-a8a1-4dcd-9291-99f15fdf4692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29284
64602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2928464602
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.548675786
Short name T2101
Test name
Test status
Simulation time 187073954 ps
CPU time 2.03 seconds
Started Jul 27 07:35:54 PM PDT 24
Finished Jul 27 07:35:56 PM PDT 24
Peak memory 207376 kb
Host smart-861d2db0-f29a-4b24-af00-160182bb3da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54867
5786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.548675786
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.447000063
Short name T564
Test name
Test status
Simulation time 230176178 ps
CPU time 1.12 seconds
Started Jul 27 07:35:57 PM PDT 24
Finished Jul 27 07:35:58 PM PDT 24
Peak memory 215604 kb
Host smart-90ea4d82-fce9-48c9-8b45-d0cc5bc4d739
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=447000063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.447000063
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1901554553
Short name T1999
Test name
Test status
Simulation time 176109082 ps
CPU time 0.85 seconds
Started Jul 27 07:35:56 PM PDT 24
Finished Jul 27 07:35:57 PM PDT 24
Peak memory 207104 kb
Host smart-b7237a5c-20d1-4455-8fd9-6336670419ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19015
54553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1901554553
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1173532821
Short name T1716
Test name
Test status
Simulation time 251077676 ps
CPU time 0.97 seconds
Started Jul 27 07:35:58 PM PDT 24
Finished Jul 27 07:35:59 PM PDT 24
Peak memory 207100 kb
Host smart-2ce0f817-5fef-4171-81f4-66405642cc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11735
32821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1173532821
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.3650954449
Short name T748
Test name
Test status
Simulation time 8822567695 ps
CPU time 261.57 seconds
Started Jul 27 07:35:55 PM PDT 24
Finished Jul 27 07:40:17 PM PDT 24
Peak memory 215508 kb
Host smart-545d81dd-056e-45c3-8745-543ff45e5b4e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3650954449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.3650954449
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.1393928154
Short name T1012
Test name
Test status
Simulation time 6754577964 ps
CPU time 49.14 seconds
Started Jul 27 07:35:55 PM PDT 24
Finished Jul 27 07:36:44 PM PDT 24
Peak memory 207248 kb
Host smart-42606eff-02c0-4181-bc46-2f1bdab5d0f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1393928154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.1393928154
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3261088681
Short name T1444
Test name
Test status
Simulation time 223918994 ps
CPU time 0.95 seconds
Started Jul 27 07:36:00 PM PDT 24
Finished Jul 27 07:36:01 PM PDT 24
Peak memory 207192 kb
Host smart-e8a9f9df-4611-43d1-b355-4eea53e56332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32610
88681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3261088681
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3429763075
Short name T2499
Test name
Test status
Simulation time 23327474351 ps
CPU time 26.58 seconds
Started Jul 27 07:35:55 PM PDT 24
Finished Jul 27 07:36:22 PM PDT 24
Peak memory 207360 kb
Host smart-29e062a0-4c03-40f4-841c-09d48cc28193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34297
63075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3429763075
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.4277416516
Short name T1932
Test name
Test status
Simulation time 3262907990 ps
CPU time 5.8 seconds
Started Jul 27 07:35:55 PM PDT 24
Finished Jul 27 07:36:00 PM PDT 24
Peak memory 207316 kb
Host smart-64b6cf47-9b17-4d3d-bf02-1b028cf87e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42774
16516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.4277416516
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.2780824108
Short name T1195
Test name
Test status
Simulation time 4867453563 ps
CPU time 137.03 seconds
Started Jul 27 07:35:56 PM PDT 24
Finished Jul 27 07:38:13 PM PDT 24
Peak memory 215620 kb
Host smart-d9023f6e-c78a-4289-b982-2c966f890fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27808
24108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.2780824108
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3942273633
Short name T1586
Test name
Test status
Simulation time 2782437586 ps
CPU time 79 seconds
Started Jul 27 07:35:55 PM PDT 24
Finished Jul 27 07:37:14 PM PDT 24
Peak memory 215488 kb
Host smart-b7002f0c-a492-4741-a441-5f97af083456
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3942273633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3942273633
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.1001363809
Short name T2472
Test name
Test status
Simulation time 253011595 ps
CPU time 0.97 seconds
Started Jul 27 07:35:54 PM PDT 24
Finished Jul 27 07:35:55 PM PDT 24
Peak memory 207100 kb
Host smart-a2f9e462-0bcb-4bcf-9b43-db3b3ffb3763
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1001363809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.1001363809
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1776659079
Short name T1302
Test name
Test status
Simulation time 208903877 ps
CPU time 0.95 seconds
Started Jul 27 07:35:57 PM PDT 24
Finished Jul 27 07:35:58 PM PDT 24
Peak memory 207124 kb
Host smart-3c0dbd4e-e36e-402c-86ac-00fbf462e031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17766
59079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1776659079
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.951201871
Short name T869
Test name
Test status
Simulation time 3705466653 ps
CPU time 110.99 seconds
Started Jul 27 07:35:54 PM PDT 24
Finished Jul 27 07:37:45 PM PDT 24
Peak memory 215588 kb
Host smart-fbcb358a-a1e5-44d7-b679-49bc3c58a4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95120
1871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.951201871
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3644788378
Short name T223
Test name
Test status
Simulation time 3264053165 ps
CPU time 93.55 seconds
Started Jul 27 07:35:56 PM PDT 24
Finished Jul 27 07:37:30 PM PDT 24
Peak memory 215644 kb
Host smart-602eee0c-3993-471c-a0cd-148994af308e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3644788378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3644788378
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3307825460
Short name T456
Test name
Test status
Simulation time 196150201 ps
CPU time 0.88 seconds
Started Jul 27 07:36:00 PM PDT 24
Finished Jul 27 07:36:01 PM PDT 24
Peak memory 207172 kb
Host smart-31810edb-028b-45bc-8423-edd92ecf8d58
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3307825460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3307825460
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3935260726
Short name T1087
Test name
Test status
Simulation time 152437352 ps
CPU time 0.85 seconds
Started Jul 27 07:35:55 PM PDT 24
Finished Jul 27 07:35:56 PM PDT 24
Peak memory 207156 kb
Host smart-f2cf8939-d649-487b-9bf5-61e1d814fd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39352
60726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3935260726
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3789902528
Short name T1619
Test name
Test status
Simulation time 247841368 ps
CPU time 1.06 seconds
Started Jul 27 07:35:58 PM PDT 24
Finished Jul 27 07:35:59 PM PDT 24
Peak memory 207108 kb
Host smart-e4eca944-6d6b-4ed1-b57f-f47adcd92492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37899
02528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3789902528
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.541481125
Short name T1835
Test name
Test status
Simulation time 163289674 ps
CPU time 0.85 seconds
Started Jul 27 07:36:01 PM PDT 24
Finished Jul 27 07:36:02 PM PDT 24
Peak memory 207068 kb
Host smart-e203fb71-0e60-49d8-bc3c-d07a066ff062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54148
1125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.541481125
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1430529303
Short name T1112
Test name
Test status
Simulation time 185104290 ps
CPU time 0.94 seconds
Started Jul 27 07:36:03 PM PDT 24
Finished Jul 27 07:36:04 PM PDT 24
Peak memory 207072 kb
Host smart-658d6392-7840-4557-b0f4-37aa8da0ce3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14305
29303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1430529303
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1650172583
Short name T2126
Test name
Test status
Simulation time 172687592 ps
CPU time 0.89 seconds
Started Jul 27 07:36:02 PM PDT 24
Finished Jul 27 07:36:03 PM PDT 24
Peak memory 207140 kb
Host smart-5976d269-8e18-4ab0-898d-a55799136ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16501
72583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1650172583
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2017596763
Short name T2128
Test name
Test status
Simulation time 151812786 ps
CPU time 0.81 seconds
Started Jul 27 07:36:00 PM PDT 24
Finished Jul 27 07:36:01 PM PDT 24
Peak memory 207088 kb
Host smart-38e8284d-4294-42e8-9c95-1d5bb32c49a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20175
96763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2017596763
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.1942612026
Short name T2326
Test name
Test status
Simulation time 242763532 ps
CPU time 1.03 seconds
Started Jul 27 07:36:01 PM PDT 24
Finished Jul 27 07:36:03 PM PDT 24
Peak memory 207092 kb
Host smart-1ac157d7-d684-4ac1-ab4f-ce4bea4a6398
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1942612026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.1942612026
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3126943805
Short name T402
Test name
Test status
Simulation time 141754995 ps
CPU time 0.83 seconds
Started Jul 27 07:36:03 PM PDT 24
Finished Jul 27 07:36:04 PM PDT 24
Peak memory 207088 kb
Host smart-2f665020-d4a8-41e8-8d7d-b1d4fcedddab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31269
43805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3126943805
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2667123501
Short name T2375
Test name
Test status
Simulation time 63179108 ps
CPU time 0.71 seconds
Started Jul 27 07:36:07 PM PDT 24
Finished Jul 27 07:36:08 PM PDT 24
Peak memory 207028 kb
Host smart-54c86bf3-653c-4402-9309-f411fa71a9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26671
23501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2667123501
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3548546696
Short name T2609
Test name
Test status
Simulation time 8712382494 ps
CPU time 22.61 seconds
Started Jul 27 07:36:01 PM PDT 24
Finished Jul 27 07:36:23 PM PDT 24
Peak memory 215652 kb
Host smart-78d48108-e1e7-48f9-8271-67a37a47374f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35485
46696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3548546696
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.269932313
Short name T2385
Test name
Test status
Simulation time 226387453 ps
CPU time 0.97 seconds
Started Jul 27 07:36:01 PM PDT 24
Finished Jul 27 07:36:02 PM PDT 24
Peak memory 207108 kb
Host smart-a6e17416-b61a-4d05-9bf2-c42764a69efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26993
2313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.269932313
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.429780112
Short name T298
Test name
Test status
Simulation time 251153465 ps
CPU time 0.99 seconds
Started Jul 27 07:36:01 PM PDT 24
Finished Jul 27 07:36:02 PM PDT 24
Peak memory 207080 kb
Host smart-8c56fdee-ac79-44b2-a7f9-57df0b3a9786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42978
0112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.429780112
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1921727522
Short name T1748
Test name
Test status
Simulation time 8516379469 ps
CPU time 147.97 seconds
Started Jul 27 07:36:00 PM PDT 24
Finished Jul 27 07:38:28 PM PDT 24
Peak memory 215588 kb
Host smart-bb85e9cb-e83a-4b3a-bbbe-d974ef3ffcb3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921727522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1921727522
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1066220366
Short name T180
Test name
Test status
Simulation time 9701307151 ps
CPU time 59.76 seconds
Started Jul 27 07:36:02 PM PDT 24
Finished Jul 27 07:37:02 PM PDT 24
Peak memory 223636 kb
Host smart-8a901acb-f79a-4b52-ad95-14b8872737c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1066220366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1066220366
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.2017742488
Short name T688
Test name
Test status
Simulation time 13491558304 ps
CPU time 295.52 seconds
Started Jul 27 07:35:59 PM PDT 24
Finished Jul 27 07:40:55 PM PDT 24
Peak memory 215592 kb
Host smart-08af1b5a-27c2-4c68-acde-01d25d836de9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017742488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.2017742488
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.3527812838
Short name T382
Test name
Test status
Simulation time 229158528 ps
CPU time 0.99 seconds
Started Jul 27 07:36:06 PM PDT 24
Finished Jul 27 07:36:07 PM PDT 24
Peak memory 207156 kb
Host smart-14e15608-2ccf-437a-ba0e-a0d8b868a9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35278
12838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.3527812838
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.2522699726
Short name T838
Test name
Test status
Simulation time 186218429 ps
CPU time 0.9 seconds
Started Jul 27 07:36:01 PM PDT 24
Finished Jul 27 07:36:02 PM PDT 24
Peak memory 207140 kb
Host smart-37fe231d-03c0-4b75-a457-7df636e624fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25226
99726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.2522699726
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.549294597
Short name T2846
Test name
Test status
Simulation time 224585841 ps
CPU time 0.93 seconds
Started Jul 27 07:36:02 PM PDT 24
Finished Jul 27 07:36:03 PM PDT 24
Peak memory 207088 kb
Host smart-e1db2c96-3932-4119-ace6-c47dc87238dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54929
4597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.549294597
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1818080734
Short name T567
Test name
Test status
Simulation time 173569070 ps
CPU time 0.87 seconds
Started Jul 27 07:36:02 PM PDT 24
Finished Jul 27 07:36:03 PM PDT 24
Peak memory 207064 kb
Host smart-a9b1e544-974d-4ba0-90ae-3a5faf674152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18180
80734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1818080734
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.988477820
Short name T2861
Test name
Test status
Simulation time 146161856 ps
CPU time 0.88 seconds
Started Jul 27 07:36:02 PM PDT 24
Finished Jul 27 07:36:03 PM PDT 24
Peak memory 207156 kb
Host smart-f8766889-860e-4558-8363-2884c9388feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98847
7820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.988477820
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1457695153
Short name T1175
Test name
Test status
Simulation time 205334459 ps
CPU time 0.94 seconds
Started Jul 27 07:36:07 PM PDT 24
Finished Jul 27 07:36:08 PM PDT 24
Peak memory 207060 kb
Host smart-a666c79a-01b9-400c-ba5c-d3f32b9687a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14576
95153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1457695153
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.851956244
Short name T948
Test name
Test status
Simulation time 4403031371 ps
CPU time 126.48 seconds
Started Jul 27 07:36:02 PM PDT 24
Finished Jul 27 07:38:08 PM PDT 24
Peak memory 215496 kb
Host smart-44cb332a-2e45-4c81-a2e4-95212e526759
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=851956244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.851956244
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1292846446
Short name T2339
Test name
Test status
Simulation time 156164156 ps
CPU time 0.9 seconds
Started Jul 27 07:36:07 PM PDT 24
Finished Jul 27 07:36:08 PM PDT 24
Peak memory 207068 kb
Host smart-2872ea16-25ef-40a3-a9a3-95c9d4ad9569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12928
46446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1292846446
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.589248940
Short name T1131
Test name
Test status
Simulation time 161642432 ps
CPU time 0.88 seconds
Started Jul 27 07:36:00 PM PDT 24
Finished Jul 27 07:36:01 PM PDT 24
Peak memory 207108 kb
Host smart-857bfea3-f67a-4925-9c8e-b4f6da6b12c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58924
8940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.589248940
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.3121489658
Short name T2370
Test name
Test status
Simulation time 256253215 ps
CPU time 1.06 seconds
Started Jul 27 07:36:02 PM PDT 24
Finished Jul 27 07:36:03 PM PDT 24
Peak memory 207036 kb
Host smart-e1424f06-c2fd-45ed-b252-d1d28f7f8838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31214
89658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3121489658
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1997204860
Short name T1776
Test name
Test status
Simulation time 5439345692 ps
CPU time 49.92 seconds
Started Jul 27 07:36:01 PM PDT 24
Finished Jul 27 07:36:51 PM PDT 24
Peak memory 217124 kb
Host smart-3e3358d3-16b7-4f2e-8758-724964b10cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19972
04860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1997204860
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.1745018426
Short name T2221
Test name
Test status
Simulation time 844912757 ps
CPU time 5.04 seconds
Started Jul 27 07:35:53 PM PDT 24
Finished Jul 27 07:35:58 PM PDT 24
Peak memory 207372 kb
Host smart-5c1a2583-b1a0-42de-b987-6e50ddeed6c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745018426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host
_handshake.1745018426
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%