Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	168693	1		T1	2		T2	2		T3	3
all_values[1]	168693	1		T1	2		T2	2		T3	3
all_values[2]	168693	1		T1	2		T2	2		T3	3
all_values[3]	168693	1		T1	2		T2	2		T3	3
all_values[4]	168693	1		T1	2		T2	2		T3	3
all_values[5]	168693	1		T1	2		T2	2		T3	3
all_values[6]	168693	1		T1	2		T2	2		T3	3
all_values[7]	168693	1		T1	2		T2	2		T3	3
all_values[8]	168693	1		T1	2		T2	2		T3	3
all_values[9]	168693	1		T1	2		T2	2		T3	3
all_values[10]	168693	1		T1	2		T2	2		T3	3
all_values[11]	168693	1		T1	2		T2	2		T3	3
all_values[12]	168693	1		T1	2		T2	2		T3	3
all_values[13]	168693	1		T1	2		T2	2		T3	3
all_values[14]	168693	1		T1	2		T2	2		T3	3
all_values[15]	168693	1		T1	2		T2	2		T3	3
all_values[16]	168693	1		T1	2		T2	2		T3	3
all_values[17]	168693	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5391211	1		T1	64		T2	64		T3	93
auto[1]	6965	1		T3	3		T7	2		T34	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4623591	1		T1	62		T2	57		T3	83
auto[1]	774585	1		T1	2		T2	7		T3	13

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142712	1		T1	2		T2	2		T3	3
all_values[0]	auto[0]	auto[1]	25156	1		T27	1		T28	1		T17	13
all_values[0]	auto[1]	auto[0]	721	1		T44	3		T45	3		T46	3
all_values[0]	auto[1]	auto[1]	104	1		T46	1		T288	1		T289	1
all_values[1]	auto[0]	auto[0]	165461	1		T1	2		T2	2		T27	4
all_values[1]	auto[0]	auto[1]	1561	1		T4	2		T18	2		T22	3
all_values[1]	auto[1]	auto[0]	662	1		T3	2		T7	1		T34	1
all_values[1]	auto[1]	auto[1]	1009	1		T3	1		T7	1		T34	1
all_values[2]	auto[0]	auto[0]	2965	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	165494	1		T1	1		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	137	1		T35	1		T39	1		T40	1
all_values[2]	auto[1]	auto[1]	97	1		T35	1		T39	1		T40	1
all_values[3]	auto[0]	auto[0]	166519	1		T1	2		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	538	1		T4	1		T5	1		T18	1
all_values[3]	auto[1]	auto[0]	1581	1		T43	1483		T197	2		T198	3
all_values[3]	auto[1]	auto[1]	55	1		T43	1		T196	1		T198	1
all_values[4]	auto[0]	auto[0]	2928	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	165601	1		T1	1		T2	1		T3	2
all_values[4]	auto[1]	auto[0]	104	1		T64	1		T196	1		T197	1
all_values[4]	auto[1]	auto[1]	60	1		T64	1		T196	3		T199	2
all_values[5]	auto[0]	auto[0]	168184	1		T1	2		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	350	1		T7	1		T6	1		T34	1
all_values[5]	auto[1]	auto[0]	85	1		T197	3		T199	6		T276	2
all_values[5]	auto[1]	auto[1]	74	1		T198	1		T199	1		T200	2
all_values[6]	auto[0]	auto[0]	168258	1		T1	2		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	271	1		T6	1		T8	1		T9	1
all_values[6]	auto[1]	auto[0]	87	1		T196	1		T198	1		T199	2
all_values[6]	auto[1]	auto[1]	77	1		T196	2		T197	2		T198	3
all_values[7]	auto[0]	auto[0]	114074	1		T1	2		T4	2		T7	2
all_values[7]	auto[0]	auto[1]	54447	1		T2	2		T3	3		T27	4
all_values[7]	auto[1]	auto[0]	117	1		T49	1		T50	1		T196	4
all_values[7]	auto[1]	auto[1]	55	1		T49	1		T50	1		T197	2
all_values[8]	auto[0]	auto[0]	168464	1		T1	2		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	60	1		T196	1		T197	1		T198	1
all_values[8]	auto[1]	auto[0]	110	1		T53	10		T196	2		T197	2
all_values[8]	auto[1]	auto[1]	59	1		T53	1		T197	1		T198	1
all_values[9]	auto[0]	auto[0]	168438	1		T1	2		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	61	1		T196	1		T199	2		T277	4
all_values[9]	auto[1]	auto[0]	136	1		T61	3		T62	3		T63	3
all_values[9]	auto[1]	auto[1]	58	1		T61	2		T62	2		T63	2
all_values[10]	auto[0]	auto[0]	168220	1		T1	2		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	297	1		T58	1		T59	1		T60	1
all_values[10]	auto[1]	auto[0]	107	1		T196	1		T197	4		T198	4
all_values[10]	auto[1]	auto[1]	69	1		T196	1		T197	3		T198	1
all_values[11]	auto[0]	auto[0]	168299	1		T1	2		T2	2		T3	3
all_values[11]	auto[0]	auto[1]	121	1		T6	1		T72	1		T66	4
all_values[11]	auto[1]	auto[0]	156	1		T69	1		T70	1		T71	1
all_values[11]	auto[1]	auto[1]	117	1		T69	1		T70	1		T71	1
all_values[12]	auto[0]	auto[0]	168426	1		T1	2		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	71	1		T6	1		T38	1		T76	1
all_values[12]	auto[1]	auto[0]	103	1		T73	2		T74	2		T75	2
all_values[12]	auto[1]	auto[1]	93	1		T73	1		T74	1		T75	1
all_values[13]	auto[0]	auto[0]	168358	1		T1	2		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	69	1		T6	1		T38	1		T76	1
all_values[13]	auto[1]	auto[0]	160	1		T72	1		T77	1		T78	1
all_values[13]	auto[1]	auto[1]	106	1		T72	1		T77	1		T78	1
all_values[14]	auto[0]	auto[0]	31869	1		T1	2		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	136652	1		T4	1		T7	2		T5	1
all_values[14]	auto[1]	auto[0]	94	1		T197	2		T198	1		T199	2
all_values[14]	auto[1]	auto[1]	78	1		T196	1		T198	3		T200	1
all_values[15]	auto[0]	auto[0]	2975	1		T1	2		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	165552	1		T2	1		T3	2		T27	3
all_values[15]	auto[1]	auto[0]	108	1		T196	3		T197	7		T198	4
all_values[15]	auto[1]	auto[1]	58	1		T196	2		T199	2		T276	2
all_values[16]	auto[0]	auto[0]	168103	1		T1	2		T2	2		T3	3
all_values[16]	auto[0]	auto[1]	416	1		T18	1		T19	1		T65	1
all_values[16]	auto[1]	auto[0]	105	1		T66	4		T67	4		T68	4
all_values[16]	auto[1]	auto[1]	69	1		T66	4		T67	4		T68	4
all_values[17]	auto[0]	auto[0]	112967	1		T1	2		T4	2		T7	2
all_values[17]	auto[0]	auto[1]	55572	1		T2	2		T3	3		T27	4
all_values[17]	auto[1]	auto[0]	96	1		T55	1		T56	1		T57	1
all_values[17]	auto[1]	auto[1]	58	1		T55	1		T56	1		T57	1