Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	132890	1		T3	1		T27	1		T28	1
auto[1]	61953	1		T3	1		T4	81		T7	1

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixty_four	30210	1		T4	6		T17	13		T23	850
sixty_three	1264	1		T4	4		T5	4		T93	6
sixty_two	1197	1		T4	2		T5	2		T6	7
sixty_one	1170	1		T4	2		T5	4		T6	3
five	1615	1		T28	1		T4	2		T6	2
four	1477	1		T4	2		T5	2		T6	3
three	1558	1		T4	2		T5	8		T19	1
one	1721	1		T5	6		T6	5		T93	2
zero	11690	1		T27	1		T4	6		T5	2

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixty_four	auto[0]	24651	1		T4	3		T17	13		T23	850
sixty_four	auto[1]	5559	1		T4	3		T6	1		T93	1
sixty_three	auto[0]	770	1		T4	2		T5	2		T93	3
sixty_three	auto[1]	494	1		T4	2		T5	2		T93	3
sixty_two	auto[0]	750	1		T4	1		T5	1		T6	4
sixty_two	auto[1]	447	1		T4	1		T5	1		T6	3
sixty_one	auto[0]	741	1		T4	1		T5	2		T6	2
sixty_one	auto[1]	429	1		T4	1		T5	2		T6	1
five	auto[0]	852	1		T28	1		T4	1		T6	1
five	auto[1]	763	1		T4	1		T6	1		T37	1
four	auto[0]	762	1		T4	1		T5	1		T6	2
four	auto[1]	715	1		T4	1		T5	1		T6	1
three	auto[0]	824	1		T4	1		T5	4		T19	1
three	auto[1]	734	1		T4	1		T5	4		T6	1
one	auto[0]	849	1		T5	3		T6	4		T93	1
one	auto[1]	872	1		T5	3		T6	1		T93	1
zero	auto[0]	960	1		T27	1		T4	3		T5	1
zero	auto[1]	10730	1		T4	3		T5	1		T24	1