Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
42.67	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	6	16	72.73
Crosses	128	80	48	37.50

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	16	4	12	75.00	100	1	1	16
cp_pid	4	2	2	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	128	80	48	37.50	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	87944	1		T3	1		T27	1		T28	1
auto[1]	56484	1		T3	1		T4	81		T7	1

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	16	4	12	75.00

Automatically Generated Bins for cp_endp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[12] - auto[15]]	--	--	4

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	11709	1		T18	37		T93	40		T37	50
auto[1]	11143	1		T28	1		T5	32		T18	15
auto[2]	13606	1		T5	32		T18	56		T6	32
auto[3]	11392	1		T3	2		T5	32		T18	45
auto[4]	13476	1		T17	13		T5	32		T19	1
auto[5]	14054	1		T4	162		T18	41		T22	2
auto[6]	11048	1		T5	32		T18	37		T29	1
auto[7]	12334	1		T5	32		T24	2		T6	31
auto[8]	13460	1		T27	1		T6	33		T37	50
auto[9]	10803	1		T5	32		T6	32		T37	50
auto[10]	9352	1		T5	32		T18	49		T104	1
auto[11]	12051	1		T7	2		T23	850		T6	30

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
nak	0	1	1
ack	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	67886	1		T4	80		T17	6		T5	125
data0	76513	1		T3	2		T27	1		T28	1

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	80	48	37.50	80

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER
[nak , ack]	*	*	--	--	64
[data1 , data0]	*	[auto[12] - auto[15]]	--	--	16

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	auto[0]	auto[0]	2744	1		T18	13		T93	6		T37	7
data1	auto[0]	auto[1]	2747	1		T5	8		T37	8		T146	5
data1	auto[0]	auto[2]	3620	1		T5	6		T18	16		T6	5
data1	auto[0]	auto[3]	2983	1		T5	8		T18	24		T102	2
data1	auto[0]	auto[4]	3873	1		T17	6		T5	8		T112	1
data1	auto[0]	auto[5]	3943	1		T4	40		T6	4		T93	7
data1	auto[0]	auto[6]	2860	1		T5	5		T93	10		T148	4
data1	auto[0]	auto[7]	2938	1		T5	8		T6	8		T97	2
data1	auto[0]	auto[8]	3954	1		T6	5		T37	12		T148	6
data1	auto[0]	auto[9]	2601	1		T5	7		T6	4		T37	9
data1	auto[0]	auto[10]	1990	1		T5	6		T18	30		T146	8
data1	auto[0]	auto[11]	3069	1		T23	425		T6	7		T37	12
data1	auto[1]	auto[0]	2672	1		T93	14		T37	17		T148	9
data1	auto[1]	auto[1]	2493	1		T5	8		T18	12		T37	17
data1	auto[1]	auto[2]	2848	1		T5	9		T18	9		T6	10
data1	auto[1]	auto[3]	2419	1		T5	8		T148	8		T152	7
data1	auto[1]	auto[4]	2530	1		T5	8		T146	10		T148	6
data1	auto[1]	auto[5]	2625	1		T4	40		T18	5		T6	10
data1	auto[1]	auto[6]	2310	1		T5	10		T93	10		T148	9
data1	auto[1]	auto[7]	2913	1		T5	8		T6	7		T97	1
data1	auto[1]	auto[8]	2354	1		T6	10		T37	12		T148	6
data1	auto[1]	auto[9]	2386	1		T5	9		T6	10		T37	16
data1	auto[1]	auto[10]	2355	1		T5	9		T146	8		T58	5
data1	auto[1]	auto[11]	2659	1		T6	7		T37	12		T98	5
data0	auto[0]	auto[0]	4088	1		T18	24		T93	14		T37	18
data0	auto[0]	auto[1]	3751	1		T28	1		T5	8		T44	1
data0	auto[0]	auto[2]	4824	1		T5	10		T18	28		T6	11
data0	auto[0]	auto[3]	3982	1		T3	1		T5	8		T18	21
data0	auto[0]	auto[4]	4966	1		T17	7		T5	8		T19	1
data0	auto[0]	auto[5]	5195	1		T4	41		T18	34		T22	1
data0	auto[0]	auto[6]	3841	1		T5	11		T18	37		T29	1
data0	auto[0]	auto[7]	4034	1		T5	8		T24	1		T6	8
data0	auto[0]	auto[8]	5083	1		T27	1		T6	12		T37	13
data0	auto[0]	auto[9]	3693	1		T5	9		T6	11		T37	16
data0	auto[0]	auto[10]	3016	1		T5	10		T18	19		T104	1
data0	auto[0]	auto[11]	4120	1		T7	1		T23	425		T6	8
data0	auto[1]	auto[0]	2205	1		T93	6		T37	8		T145	1
data0	auto[1]	auto[1]	2149	1		T5	8		T18	3		T37	8
data0	auto[1]	auto[2]	2312	1		T5	7		T18	3		T6	5
data0	auto[1]	auto[3]	2006	1		T3	1		T5	8		T147	1
data0	auto[1]	auto[4]	2106	1		T5	8		T34	1		T146	6
data0	auto[1]	auto[5]	2283	1		T4	41		T18	2		T22	1
data0	auto[1]	auto[6]	2036	1		T5	6		T93	10		T9	1
data0	auto[1]	auto[7]	2447	1		T5	8		T24	1		T6	8
data0	auto[1]	auto[8]	2066	1		T6	5		T37	13		T148	7
data0	auto[1]	auto[9]	2117	1		T5	7		T6	5		T37	9
data0	auto[1]	auto[10]	1990	1		T5	7		T146	8		T58	8
data0	auto[1]	auto[11]	2203	1		T7	1		T6	8		T37	13