Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
33.85	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	1	10	90.91
Crosses	54	42	12	22.22

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	1	2	66.67	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	42	12	22.22	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	42035	1		T4	81		T5	128		T6	137
solo	88997	1		T3	1		T27	1		T28	1
empty	1740	1		T18	20		T44	1		T104	1

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	42031	1		T4	81		T5	128		T6	137
solo	44946	1		T18	1244		T20	21		T100	2
empty	45850	1		T3	1		T27	1		T28	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
out	106542	1		T3	1		T27	1		T28	1
setup	26293	1		T5	21		T18	477		T20	10

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_rx

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
full	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
solo	14	1		T66	1		T51	2		T52	2
empty	109333	1		T3	1		T27	1		T28	1

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	42	12	22.22	42

Automatically Generated Cross Bins for cr_fifo_X_pid

Element holes

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER
[full]	[full]	[full , solo]	*	--	--	4
[full]	[solo , empty]	*	*	--	--	12
[solo]	[full]	[full , solo]	*	--	--	4
[solo]	[solo]	[full]	*	--	--	2
[solo]	[empty]	[full]	*	--	--	2
[empty]	[full]	*	*	--	--	6
[empty]	[solo]	[full , solo]	*	--	--	4
[empty]	[empty]	[full , solo]	*	--	--	4

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER
[solo]	[full]	[empty]	[setup]	0	1	1
[solo]	[empty]	[solo , empty]	[out]	--	--	2
[empty]	[solo]	[empty]	[setup]	0	1	1

Covered bins

cp_avsetup

cp_avout

cp_rx

cp_pid

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

full

full

empty

out

32079

1

T4

81

T5

107

T6

102

full

full

empty

setup

9951

1

T5

21

T6

35

T93

21

solo

full

empty

out

5

1

T51

1

T52

1

T54

1

solo

solo

solo

out

5

1

T51

1

T52

1

T54

1

solo

solo

solo

setup

5

1

T51

1

T52

1

T54

1

solo

solo

empty

out

16440

1

T18

453

T20

11

T100

1

solo

solo

empty

setup

8142

1

T18

218

T20

10

T100

1

solo

empty

solo

setup

1

1

T53

1

-

-

-

-

solo

empty

empty

setup

305

1

T104

1

T151

1

T275

1

empty

solo

empty

out

42197

1

T3

1

T27

1

T28

1

empty

empty

empty

out

152

1

T43

149

T66

1

T67

1

empty

empty

empty

setup

50

1

T44

1

T45

1

T268

1