Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	168693	1		T1	2		T2	2		T3	3
all_pins[1]	168693	1		T1	2		T2	2		T3	3
all_pins[2]	168693	1		T1	2		T2	2		T3	3
all_pins[3]	168693	1		T1	2		T2	2		T3	3
all_pins[4]	168693	1		T1	2		T2	2		T3	3
all_pins[5]	168693	1		T1	2		T2	2		T3	3
all_pins[6]	168693	1		T1	2		T2	2		T3	3
all_pins[7]	168693	1		T1	2		T2	2		T3	3
all_pins[8]	168693	1		T1	2		T2	2		T3	3
all_pins[9]	168693	1		T1	2		T2	2		T3	3
all_pins[10]	168693	1		T1	2		T2	2		T3	3
all_pins[11]	168693	1		T1	2		T2	2		T3	3
all_pins[12]	168693	1		T1	2		T2	2		T3	3
all_pins[13]	168693	1		T1	2		T2	2		T3	3
all_pins[14]	168693	1		T1	2		T2	2		T3	3
all_pins[15]	168693	1		T1	2		T2	2		T3	3
all_pins[16]	168693	1		T1	2		T2	2		T3	3
all_pins[17]	168693	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5395880	1		T1	64		T2	64		T3	95
values[0x1]	2296	1		T3	1		T7	1		T34	1
transitions[0x0=>0x1]	2027	1		T3	1		T7	1		T34	1
transitions[0x1=>0x0]	2027	1		T3	1		T7	1		T34	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	168589	1		T1	2		T2	2		T3	3
all_pins[0]	values[0x1]	104	1		T46	1		T288	1		T289	1
all_pins[0]	transitions[0x0=>0x1]	92	1		T46	1		T288	1		T289	1
all_pins[0]	transitions[0x1=>0x0]	997	1		T3	1		T7	1		T34	1
all_pins[1]	values[0x0]	167684	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	1009	1		T3	1		T7	1		T34	1
all_pins[1]	transitions[0x0=>0x1]	996	1		T3	1		T7	1		T34	1
all_pins[1]	transitions[0x1=>0x0]	84	1		T35	1		T39	1		T40	1
all_pins[2]	values[0x0]	168596	1		T1	2		T2	2		T3	3
all_pins[2]	values[0x1]	97	1		T35	1		T39	1		T40	1
all_pins[2]	transitions[0x0=>0x1]	86	1		T35	1		T39	1		T40	1
all_pins[2]	transitions[0x1=>0x0]	44	1		T43	1		T196	1		T198	1
all_pins[3]	values[0x0]	168638	1		T1	2		T2	2		T3	3
all_pins[3]	values[0x1]	55	1		T43	1		T196	1		T198	1
all_pins[3]	transitions[0x0=>0x1]	41	1		T43	1		T196	1		T198	1
all_pins[3]	transitions[0x1=>0x0]	46	1		T64	1		T196	3		T199	2
all_pins[4]	values[0x0]	168633	1		T1	2		T2	2		T3	3
all_pins[4]	values[0x1]	60	1		T64	1		T196	3		T199	2
all_pins[4]	transitions[0x0=>0x1]	43	1		T64	1		T196	3		T199	2
all_pins[4]	transitions[0x1=>0x0]	57	1		T198	1		T199	1		T277	5
all_pins[5]	values[0x0]	168619	1		T1	2		T2	2		T3	3
all_pins[5]	values[0x1]	74	1		T198	1		T199	1		T200	2
all_pins[5]	transitions[0x0=>0x1]	50	1		T198	1		T199	1		T200	2
all_pins[5]	transitions[0x1=>0x0]	53	1		T196	2		T197	2		T198	3
all_pins[6]	values[0x0]	168616	1		T1	2		T2	2		T3	3
all_pins[6]	values[0x1]	77	1		T196	2		T197	2		T198	3
all_pins[6]	transitions[0x0=>0x1]	60	1		T196	2		T197	2		T198	2
all_pins[6]	transitions[0x1=>0x0]	38	1		T49	1		T50	1		T197	2
all_pins[7]	values[0x0]	168638	1		T1	2		T2	2		T3	3
all_pins[7]	values[0x1]	55	1		T49	1		T50	1		T197	2
all_pins[7]	transitions[0x0=>0x1]	44	1		T49	1		T50	1		T197	2
all_pins[7]	transitions[0x1=>0x0]	48	1		T53	1		T197	1		T198	1
all_pins[8]	values[0x0]	168634	1		T1	2		T2	2		T3	3
all_pins[8]	values[0x1]	59	1		T53	1		T197	1		T198	1
all_pins[8]	transitions[0x0=>0x1]	48	1		T53	1		T200	2		T277	2
all_pins[8]	transitions[0x1=>0x0]	47	1		T61	2		T62	2		T63	2
all_pins[9]	values[0x0]	168635	1		T1	2		T2	2		T3	3
all_pins[9]	values[0x1]	58	1		T61	2		T62	2		T63	2
all_pins[9]	transitions[0x0=>0x1]	42	1		T61	2		T62	2		T63	2
all_pins[9]	transitions[0x1=>0x0]	53	1		T196	1		T199	2		T200	4
all_pins[10]	values[0x0]	168624	1		T1	2		T2	2		T3	3
all_pins[10]	values[0x1]	69	1		T196	1		T197	3		T198	1
all_pins[10]	transitions[0x0=>0x1]	52	1		T196	1		T197	1		T200	4
all_pins[10]	transitions[0x1=>0x0]	100	1		T69	1		T70	1		T71	1
all_pins[11]	values[0x0]	168576	1		T1	2		T2	2		T3	3
all_pins[11]	values[0x1]	117	1		T69	1		T70	1		T71	1
all_pins[11]	transitions[0x0=>0x1]	93	1		T69	1		T70	1		T71	1
all_pins[11]	transitions[0x1=>0x0]	69	1		T73	1		T74	1		T75	1
all_pins[12]	values[0x0]	168600	1		T1	2		T2	2		T3	3
all_pins[12]	values[0x1]	93	1		T73	1		T74	1		T75	1
all_pins[12]	transitions[0x0=>0x1]	74	1		T73	1		T74	1		T75	1
all_pins[12]	transitions[0x1=>0x0]	87	1		T72	1		T77	1		T78	1
all_pins[13]	values[0x0]	168587	1		T1	2		T2	2		T3	3
all_pins[13]	values[0x1]	106	1		T72	1		T77	1		T78	1
all_pins[13]	transitions[0x0=>0x1]	85	1		T72	1		T77	1		T78	1
all_pins[13]	transitions[0x1=>0x0]	57	1		T196	1		T198	3		T200	1
all_pins[14]	values[0x0]	168615	1		T1	2		T2	2		T3	3
all_pins[14]	values[0x1]	78	1		T196	1		T198	3		T200	1
all_pins[14]	transitions[0x0=>0x1]	60	1		T198	3		T200	1		T277	1
all_pins[14]	transitions[0x1=>0x0]	40	1		T196	1		T199	2		T276	2
all_pins[15]	values[0x0]	168635	1		T1	2		T2	2		T3	3
all_pins[15]	values[0x1]	58	1		T196	2		T199	2		T276	2
all_pins[15]	transitions[0x0=>0x1]	45	1		T196	2		T276	2		T277	1
all_pins[15]	transitions[0x1=>0x0]	56	1		T66	4		T67	4		T68	4
all_pins[16]	values[0x0]	168624	1		T1	2		T2	2		T3	3
all_pins[16]	values[0x1]	69	1		T66	4		T67	4		T68	4
all_pins[16]	transitions[0x0=>0x1]	58	1		T66	4		T67	4		T68	4
all_pins[16]	transitions[0x1=>0x0]	47	1		T55	1		T56	1		T57	1
all_pins[17]	values[0x0]	168635	1		T1	2		T2	2		T3	3
all_pins[17]	values[0x1]	58	1		T55	1		T56	1		T57	1
all_pins[17]	transitions[0x0=>0x1]	58	1		T55	1		T56	1		T57	1