Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[12]	4928	1		T18	121		T6	3		T90	114
invalid_ep[13]	5036	1		T18	109		T6	3		T90	102
invalid_ep[14]	5091	1		T18	114		T6	7		T90	131
invalid_ep[15]	5131	1		T18	125		T6	6		T90	113
endpoints[0]	15288	1		T18	113		T20	2		T6	2
endpoints[1]	14689	1		T28	1		T5	33		T18	124
endpoints[2]	17805	1		T2	1		T5	33		T18	110
endpoints[3]	15238	1		T3	2		T5	33		T18	122
endpoints[4]	17640	1		T17	13		T5	33		T18	97
endpoints[5]	17441	1		T4	163		T18	91		T20	10
endpoints[6]	15575	1		T5	33		T18	100		T29	2
endpoints[7]	16158	1		T5	33		T18	116		T20	6
endpoints[8]	17509	1		T27	1		T18	126		T20	1
endpoints[9]	14455	1		T5	33		T18	109		T6	36
endpoints[10]	13096	1		T5	33		T18	108		T20	2
endpoints[11]	16094	1		T7	2		T18	119		T20	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	26293	1		T5	21		T18	477		T20	10
pkt_types[PidTypeOutToken]	106542	1		T3	1		T27	1		T28	1
pkt_types[PidTypeInToken]	78265	1		T2	1		T3	1		T4	82

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[12]	983	1		T18	35		T90	18		T92	16
pkt_types[PidTypeSetupToken]	invalid_ep[13]	982	1		T18	29		T90	28		T92	22
pkt_types[PidTypeSetupToken]	invalid_ep[14]	1012	1		T18	31		T90	38		T92	23
pkt_types[PidTypeSetupToken]	invalid_ep[15]	982	1		T18	35		T90	17		T92	24
pkt_types[PidTypeSetupToken]	endpoints[0]	1973	1		T18	33		T20	1		T93	11
pkt_types[PidTypeSetupToken]	endpoints[1]	1693	1		T18	36		T20	1		T44	1
pkt_types[PidTypeSetupToken]	endpoints[2]	2112	1		T5	3		T18	33		T20	1
pkt_types[PidTypeSetupToken]	endpoints[3]	1911	1		T18	31		T148	5		T90	35
pkt_types[PidTypeSetupToken]	endpoints[4]	1855	1		T18	20		T146	6		T90	23
pkt_types[PidTypeSetupToken]	endpoints[5]	1824	1		T18	24		T20	2		T6	8
pkt_types[PidTypeSetupToken]	endpoints[6]	1686	1		T5	8		T18	29		T148	7
pkt_types[PidTypeSetupToken]	endpoints[7]	1985	1		T18	28		T20	3		T148	4
pkt_types[PidTypeSetupToken]	endpoints[8]	1787	1		T18	33		T20	1		T6	8
pkt_types[PidTypeSetupToken]	endpoints[9]	1784	1		T5	5		T18	28		T6	9
pkt_types[PidTypeSetupToken]	endpoints[10]	1790	1		T5	5		T18	28		T20	1
pkt_types[PidTypeSetupToken]	endpoints[11]	1934	1		T18	24		T152	6		T90	29
pkt_types[PidTypeOutToken]	invalid_ep[12]	2966	1		T18	59		T6	3		T90	64
pkt_types[PidTypeOutToken]	invalid_ep[13]	3097	1		T18	67		T6	3		T90	51
pkt_types[PidTypeOutToken]	invalid_ep[14]	3104	1		T18	60		T6	7		T90	61
pkt_types[PidTypeOutToken]	invalid_ep[15]	3140	1		T18	60		T6	6		T90	61
pkt_types[PidTypeOutToken]	endpoints[0]	7182	1		T18	53		T93	9		T37	11
pkt_types[PidTypeOutToken]	endpoints[1]	6978	1		T28	1		T5	16		T18	58
pkt_types[PidTypeOutToken]	endpoints[2]	8823	1		T5	13		T18	53		T20	2
pkt_types[PidTypeOutToken]	endpoints[3]	7574	1		T3	1		T5	16		T18	57
pkt_types[PidTypeOutToken]	endpoints[4]	9441	1		T17	13		T5	16		T18	51
pkt_types[PidTypeOutToken]	endpoints[5]	9631	1		T4	81		T18	47		T20	5
pkt_types[PidTypeOutToken]	endpoints[6]	7355	1		T5	8		T18	39		T29	1
pkt_types[PidTypeOutToken]	endpoints[7]	7272	1		T5	16		T18	57		T20	1
pkt_types[PidTypeOutToken]	endpoints[8]	9710	1		T27	1		T18	64		T6	11
pkt_types[PidTypeOutToken]	endpoints[9]	7000	1		T5	11		T18	47		T6	10
pkt_types[PidTypeOutToken]	endpoints[10]	5548	1		T5	11		T18	53		T20	1
pkt_types[PidTypeOutToken]	endpoints[11]	7721	1		T7	1		T18	69		T20	1
pkt_types[PidTypeInToken]	invalid_ep[12]	979	1		T18	27		T90	32		T92	20
pkt_types[PidTypeInToken]	invalid_ep[13]	957	1		T18	13		T90	23		T92	21
pkt_types[PidTypeInToken]	invalid_ep[14]	975	1		T18	23		T90	32		T92	24
pkt_types[PidTypeInToken]	invalid_ep[15]	1009	1		T18	30		T90	35		T92	16
pkt_types[PidTypeInToken]	endpoints[0]	6121	1		T18	27		T20	1		T6	1
pkt_types[PidTypeInToken]	endpoints[1]	6010	1		T5	17		T18	30		T37	26
pkt_types[PidTypeInToken]	endpoints[2]	6868	1		T2	1		T5	17		T18	24
pkt_types[PidTypeInToken]	endpoints[3]	5751	1		T3	1		T5	17		T18	34
pkt_types[PidTypeInToken]	endpoints[4]	6341	1		T5	17		T18	26		T34	1
pkt_types[PidTypeInToken]	endpoints[5]	5978	1		T4	82		T18	20		T20	3
pkt_types[PidTypeInToken]	endpoints[6]	6530	1		T5	17		T18	32		T29	1
pkt_types[PidTypeInToken]	endpoints[7]	6897	1		T5	17		T18	31		T20	2
pkt_types[PidTypeInToken]	endpoints[8]	6006	1		T18	29		T6	17		T37	26
pkt_types[PidTypeInToken]	endpoints[9]	5663	1		T5	17		T18	34		T6	16
pkt_types[PidTypeInToken]	endpoints[10]	5751	1		T5	17		T18	27		T146	17
pkt_types[PidTypeInToken]	endpoints[11]	6429	1		T7	1		T18	26		T20	1