Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.77 97.81 93.76 97.44 73.44 96.21 98.17 71.55


Total test records in report: 2978
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html | tests63.html
T2817 /workspace/coverage/default/13.usbdev_bitstuff_err.4091938243 Jul 28 07:40:15 PM PDT 24 Jul 28 07:40:16 PM PDT 24 168005753 ps
T2818 /workspace/coverage/default/6.usbdev_streaming_out.2037739125 Jul 28 07:39:23 PM PDT 24 Jul 28 07:39:57 PM PDT 24 3499071659 ps
T2819 /workspace/coverage/default/36.usbdev_link_suspend.1816780351 Jul 28 07:43:30 PM PDT 24 Jul 28 07:43:45 PM PDT 24 3322859829 ps
T2820 /workspace/coverage/default/15.usbdev_nak_trans.237586299 Jul 28 07:40:36 PM PDT 24 Jul 28 07:40:37 PM PDT 24 230433291 ps
T2821 /workspace/coverage/default/0.usbdev_out_iso.3147122894 Jul 28 07:37:58 PM PDT 24 Jul 28 07:37:59 PM PDT 24 174871753 ps
T2822 /workspace/coverage/default/47.usbdev_setup_trans_ignored.913500281 Jul 28 07:44:57 PM PDT 24 Jul 28 07:44:58 PM PDT 24 153969145 ps
T2823 /workspace/coverage/default/17.usbdev_random_length_in_transaction.2020271505 Jul 28 07:40:59 PM PDT 24 Jul 28 07:41:00 PM PDT 24 201853775 ps
T2824 /workspace/coverage/default/11.usbdev_bitstuff_err.1446908486 Jul 28 07:39:55 PM PDT 24 Jul 28 07:39:56 PM PDT 24 171139047 ps
T2825 /workspace/coverage/default/23.usbdev_disconnected.830385909 Jul 28 07:41:48 PM PDT 24 Jul 28 07:41:49 PM PDT 24 151964388 ps
T2826 /workspace/coverage/default/34.usbdev_out_stall.2561454531 Jul 28 07:43:22 PM PDT 24 Jul 28 07:43:23 PM PDT 24 148510658 ps
T2827 /workspace/coverage/default/17.usbdev_av_buffer.1556714944 Jul 28 07:40:51 PM PDT 24 Jul 28 07:40:52 PM PDT 24 143304572 ps
T2828 /workspace/coverage/default/39.usbdev_stall_trans.3376279454 Jul 28 07:44:05 PM PDT 24 Jul 28 07:44:06 PM PDT 24 168644444 ps
T2829 /workspace/coverage/default/31.usbdev_random_length_out_transaction.3146320753 Jul 28 07:43:08 PM PDT 24 Jul 28 07:43:09 PM PDT 24 185071776 ps
T2830 /workspace/coverage/default/45.usbdev_invalid_sync.335388361 Jul 28 07:44:45 PM PDT 24 Jul 28 07:46:26 PM PDT 24 9498530805 ps
T2831 /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3500040418 Jul 28 07:44:57 PM PDT 24 Jul 28 07:45:05 PM PDT 24 4287416386 ps
T2832 /workspace/coverage/default/19.usbdev_pkt_received.3676193870 Jul 28 07:41:17 PM PDT 24 Jul 28 07:41:18 PM PDT 24 183339652 ps
T2833 /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1118630600 Jul 28 07:44:45 PM PDT 24 Jul 28 07:44:51 PM PDT 24 3979855468 ps
T2834 /workspace/coverage/default/1.usbdev_rx_pid_err.3240281866 Jul 28 07:38:29 PM PDT 24 Jul 28 07:38:30 PM PDT 24 214585717 ps
T2835 /workspace/coverage/default/14.usbdev_out_stall.2806212605 Jul 28 07:40:30 PM PDT 24 Jul 28 07:40:31 PM PDT 24 189474567 ps
T2836 /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1744157681 Jul 28 07:44:27 PM PDT 24 Jul 28 07:45:17 PM PDT 24 6157080060 ps
T2837 /workspace/coverage/default/30.usbdev_stall_trans.1008969639 Jul 28 07:42:55 PM PDT 24 Jul 28 07:42:56 PM PDT 24 175301906 ps
T2838 /workspace/coverage/default/15.usbdev_stream_len_max.4100027942 Jul 28 07:40:39 PM PDT 24 Jul 28 07:40:41 PM PDT 24 605773610 ps
T2839 /workspace/coverage/default/35.usbdev_aon_wake_reset.2812363594 Jul 28 07:43:20 PM PDT 24 Jul 28 07:43:35 PM PDT 24 13373951733 ps
T2840 /workspace/coverage/default/26.usbdev_aon_wake_resume.461691467 Jul 28 07:42:13 PM PDT 24 Jul 28 07:42:48 PM PDT 24 23373740486 ps
T2841 /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.3480699539 Jul 28 07:44:48 PM PDT 24 Jul 28 07:44:57 PM PDT 24 1047715487 ps
T2842 /workspace/coverage/default/3.usbdev_disable_endpoint.684792080 Jul 28 07:38:37 PM PDT 24 Jul 28 07:38:38 PM PDT 24 392932278 ps
T2843 /workspace/coverage/default/33.usbdev_aon_wake_reset.540537026 Jul 28 07:43:02 PM PDT 24 Jul 28 07:43:17 PM PDT 24 13340559539 ps
T2844 /workspace/coverage/default/22.usbdev_stream_len_max.1082254049 Jul 28 07:41:52 PM PDT 24 Jul 28 07:41:55 PM PDT 24 1201153661 ps
T2845 /workspace/coverage/default/15.usbdev_pkt_received.1070534875 Jul 28 07:40:37 PM PDT 24 Jul 28 07:40:39 PM PDT 24 176480066 ps
T2846 /workspace/coverage/default/31.usbdev_enable.303862972 Jul 28 07:42:57 PM PDT 24 Jul 28 07:42:58 PM PDT 24 86236587 ps
T2847 /workspace/coverage/default/0.usbdev_stream_len_max.3821000428 Jul 28 07:38:04 PM PDT 24 Jul 28 07:38:05 PM PDT 24 381516946 ps
T2848 /workspace/coverage/default/31.usbdev_av_buffer.160726613 Jul 28 07:42:58 PM PDT 24 Jul 28 07:42:59 PM PDT 24 160853497 ps
T2849 /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.493188118 Jul 28 07:40:47 PM PDT 24 Jul 28 07:41:33 PM PDT 24 4838550659 ps
T2850 /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2952126610 Jul 28 07:44:50 PM PDT 24 Jul 28 07:44:51 PM PDT 24 153624918 ps
T2851 /workspace/coverage/default/30.usbdev_setup_trans_ignored.2322947439 Jul 28 07:42:57 PM PDT 24 Jul 28 07:42:58 PM PDT 24 174127711 ps
T2852 /workspace/coverage/default/27.usbdev_stall_trans.4196013584 Jul 28 07:42:27 PM PDT 24 Jul 28 07:42:28 PM PDT 24 228982672 ps
T2853 /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2840161945 Jul 28 07:42:16 PM PDT 24 Jul 28 07:42:52 PM PDT 24 4519112478 ps
T2854 /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1323528627 Jul 28 07:43:21 PM PDT 24 Jul 28 07:43:22 PM PDT 24 152486688 ps
T2855 /workspace/coverage/default/49.usbdev_av_buffer.1078425723 Jul 28 07:45:14 PM PDT 24 Jul 28 07:45:20 PM PDT 24 221041011 ps
T2856 /workspace/coverage/default/22.usbdev_max_usb_traffic.3032195996 Jul 28 07:41:53 PM PDT 24 Jul 28 07:42:40 PM PDT 24 4623871037 ps
T2857 /workspace/coverage/default/34.usbdev_disable_endpoint.752343930 Jul 28 07:43:15 PM PDT 24 Jul 28 07:43:17 PM PDT 24 490616462 ps
T2858 /workspace/coverage/default/40.usbdev_out_iso.3677345294 Jul 28 07:44:08 PM PDT 24 Jul 28 07:44:09 PM PDT 24 168842245 ps
T2859 /workspace/coverage/default/22.usbdev_rx_crc_err.1661035361 Jul 28 07:41:44 PM PDT 24 Jul 28 07:41:45 PM PDT 24 159621783 ps
T2860 /workspace/coverage/default/36.usbdev_av_buffer.1982338337 Jul 28 07:43:25 PM PDT 24 Jul 28 07:43:26 PM PDT 24 182414902 ps
T2861 /workspace/coverage/default/20.usbdev_rx_crc_err.3729957071 Jul 28 07:41:24 PM PDT 24 Jul 28 07:41:25 PM PDT 24 167903504 ps
T2862 /workspace/coverage/default/27.usbdev_alert_test.736904274 Jul 28 07:42:25 PM PDT 24 Jul 28 07:42:26 PM PDT 24 104034827 ps
T2863 /workspace/coverage/default/39.usbdev_aon_wake_resume.407513064 Jul 28 07:44:09 PM PDT 24 Jul 28 07:44:39 PM PDT 24 23391057993 ps
T2864 /workspace/coverage/default/34.usbdev_stream_len_max.543374944 Jul 28 07:43:15 PM PDT 24 Jul 28 07:43:17 PM PDT 24 627093241 ps
T2865 /workspace/coverage/default/7.usbdev_in_stall.4280454283 Jul 28 07:39:29 PM PDT 24 Jul 28 07:39:30 PM PDT 24 142186803 ps
T2866 /workspace/coverage/default/18.usbdev_max_length_in_transaction.1784892077 Jul 28 07:41:06 PM PDT 24 Jul 28 07:41:07 PM PDT 24 233887842 ps
T2867 /workspace/coverage/default/49.usbdev_pkt_buffer.4200778446 Jul 28 07:45:19 PM PDT 24 Jul 28 07:45:48 PM PDT 24 11634740193 ps
T2868 /workspace/coverage/default/16.usbdev_stall_trans.221582332 Jul 28 07:41:00 PM PDT 24 Jul 28 07:41:01 PM PDT 24 182616049 ps
T2869 /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1457673391 Jul 28 07:39:56 PM PDT 24 Jul 28 07:40:02 PM PDT 24 4440665978 ps
T2870 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4069868265 Jul 28 07:22:21 PM PDT 24 Jul 28 07:22:24 PM PDT 24 105875169 ps
T190 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3986514683 Jul 28 07:22:55 PM PDT 24 Jul 28 07:22:58 PM PDT 24 485260710 ps
T196 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1194101289 Jul 28 07:23:05 PM PDT 24 Jul 28 07:23:06 PM PDT 24 40431962 ps
T226 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2778019307 Jul 28 07:22:52 PM PDT 24 Jul 28 07:22:53 PM PDT 24 65834449 ps
T191 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1900065999 Jul 28 07:22:44 PM PDT 24 Jul 28 07:22:49 PM PDT 24 727883912 ps
T197 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2332382112 Jul 28 07:22:43 PM PDT 24 Jul 28 07:22:43 PM PDT 24 56649844 ps
T2871 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.510228730 Jul 28 07:22:33 PM PDT 24 Jul 28 07:22:36 PM PDT 24 367684276 ps
T192 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1757114888 Jul 28 07:23:01 PM PDT 24 Jul 28 07:23:03 PM PDT 24 185106888 ps
T212 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2575445754 Jul 28 07:22:33 PM PDT 24 Jul 28 07:22:35 PM PDT 24 295903519 ps
T209 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2404952730 Jul 28 07:22:40 PM PDT 24 Jul 28 07:22:42 PM PDT 24 347075826 ps
T198 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1292346429 Jul 28 07:23:08 PM PDT 24 Jul 28 07:23:09 PM PDT 24 78209459 ps
T229 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.4218119574 Jul 28 07:23:03 PM PDT 24 Jul 28 07:23:10 PM PDT 24 2220207722 ps
T242 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4035873499 Jul 28 07:22:32 PM PDT 24 Jul 28 07:22:34 PM PDT 24 73273439 ps
T243 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.4101549365 Jul 28 07:22:30 PM PDT 24 Jul 28 07:22:31 PM PDT 24 97433682 ps
T253 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4095275864 Jul 28 07:22:31 PM PDT 24 Jul 28 07:22:32 PM PDT 24 94476068 ps
T201 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4294943502 Jul 28 07:22:26 PM PDT 24 Jul 28 07:22:27 PM PDT 24 100890943 ps
T199 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3465660998 Jul 28 07:22:30 PM PDT 24 Jul 28 07:22:31 PM PDT 24 56331565 ps
T230 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.732737104 Jul 28 07:22:22 PM PDT 24 Jul 28 07:22:25 PM PDT 24 444461118 ps
T276 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2351338857 Jul 28 07:22:59 PM PDT 24 Jul 28 07:23:00 PM PDT 24 34736989 ps
T200 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1352756131 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:07 PM PDT 24 51557754 ps
T277 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3401086255 Jul 28 07:23:13 PM PDT 24 Jul 28 07:23:14 PM PDT 24 36299188 ps
T254 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2395131345 Jul 28 07:22:23 PM PDT 24 Jul 28 07:22:24 PM PDT 24 196711017 ps
T210 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.9108912 Jul 28 07:22:57 PM PDT 24 Jul 28 07:23:00 PM PDT 24 314743266 ps
T255 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2218914149 Jul 28 07:22:27 PM PDT 24 Jul 28 07:22:28 PM PDT 24 52118433 ps
T256 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3695505856 Jul 28 07:22:39 PM PDT 24 Jul 28 07:22:40 PM PDT 24 73700104 ps
T257 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1784573522 Jul 28 07:23:00 PM PDT 24 Jul 28 07:23:01 PM PDT 24 214720292 ps
T263 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2378545437 Jul 28 07:22:39 PM PDT 24 Jul 28 07:22:40 PM PDT 24 49154437 ps
T258 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3518453855 Jul 28 07:22:56 PM PDT 24 Jul 28 07:22:58 PM PDT 24 206469803 ps
T278 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1496515757 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:07 PM PDT 24 65577530 ps
T211 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2180844445 Jul 28 07:22:55 PM PDT 24 Jul 28 07:22:57 PM PDT 24 144279224 ps
T231 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1753758135 Jul 28 07:22:29 PM PDT 24 Jul 28 07:22:30 PM PDT 24 132031765 ps
T259 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3085133035 Jul 28 07:22:28 PM PDT 24 Jul 28 07:22:29 PM PDT 24 186110620 ps
T264 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2911245950 Jul 28 07:23:00 PM PDT 24 Jul 28 07:23:01 PM PDT 24 45691225 ps
T279 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1792073454 Jul 28 07:22:51 PM PDT 24 Jul 28 07:22:52 PM PDT 24 45957119 ps
T280 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3488204682 Jul 28 07:23:16 PM PDT 24 Jul 28 07:23:17 PM PDT 24 40881195 ps
T232 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.415466874 Jul 28 07:22:49 PM PDT 24 Jul 28 07:22:52 PM PDT 24 500692797 ps
T244 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3701065693 Jul 28 07:22:21 PM PDT 24 Jul 28 07:22:24 PM PDT 24 175463225 ps
T245 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.640620478 Jul 28 07:22:26 PM PDT 24 Jul 28 07:22:32 PM PDT 24 910154800 ps
T246 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3034063699 Jul 28 07:22:30 PM PDT 24 Jul 28 07:22:34 PM PDT 24 125060790 ps
T233 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1641673756 Jul 28 07:22:38 PM PDT 24 Jul 28 07:22:40 PM PDT 24 53328779 ps
T2872 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1922127168 Jul 28 07:22:58 PM PDT 24 Jul 28 07:23:00 PM PDT 24 111622980 ps
T234 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.4206520409 Jul 28 07:22:58 PM PDT 24 Jul 28 07:23:00 PM PDT 24 152055815 ps
T224 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1680922550 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:08 PM PDT 24 117532802 ps
T247 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3026761587 Jul 28 07:22:37 PM PDT 24 Jul 28 07:22:38 PM PDT 24 58005349 ps
T2873 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.768183512 Jul 28 07:22:33 PM PDT 24 Jul 28 07:22:35 PM PDT 24 438827998 ps
T281 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.229523664 Jul 28 07:23:11 PM PDT 24 Jul 28 07:23:12 PM PDT 24 39465881 ps
T2874 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.319337896 Jul 28 07:22:45 PM PDT 24 Jul 28 07:22:47 PM PDT 24 176245033 ps
T216 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1751849815 Jul 28 07:22:43 PM PDT 24 Jul 28 07:22:47 PM PDT 24 290606123 ps
T2875 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2777670973 Jul 28 07:23:07 PM PDT 24 Jul 28 07:23:09 PM PDT 24 204789122 ps
T2876 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.10046182 Jul 28 07:22:20 PM PDT 24 Jul 28 07:22:22 PM PDT 24 178152603 ps
T284 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2198058830 Jul 28 07:22:19 PM PDT 24 Jul 28 07:22:25 PM PDT 24 1467144292 ps
T282 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3869225630 Jul 28 07:23:16 PM PDT 24 Jul 28 07:23:17 PM PDT 24 40264607 ps
T248 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.726838795 Jul 28 07:22:22 PM PDT 24 Jul 28 07:22:23 PM PDT 24 193294762 ps
T2877 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.339803885 Jul 28 07:23:11 PM PDT 24 Jul 28 07:23:12 PM PDT 24 39414508 ps
T2878 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.254965715 Jul 28 07:22:54 PM PDT 24 Jul 28 07:22:55 PM PDT 24 144245951 ps
T2879 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1119111747 Jul 28 07:22:30 PM PDT 24 Jul 28 07:22:32 PM PDT 24 196710783 ps
T2880 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1165228921 Jul 28 07:23:15 PM PDT 24 Jul 28 07:23:16 PM PDT 24 31287083 ps
T2881 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.58948228 Jul 28 07:23:17 PM PDT 24 Jul 28 07:23:18 PM PDT 24 38822401 ps
T2882 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1655761717 Jul 28 07:22:18 PM PDT 24 Jul 28 07:22:25 PM PDT 24 1106001362 ps
T217 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2712488079 Jul 28 07:22:22 PM PDT 24 Jul 28 07:22:24 PM PDT 24 198496927 ps
T249 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2235260697 Jul 28 07:22:39 PM PDT 24 Jul 28 07:22:48 PM PDT 24 1889015187 ps
T218 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2436077998 Jul 28 07:22:44 PM PDT 24 Jul 28 07:22:47 PM PDT 24 145067700 ps
T2883 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3305392914 Jul 28 07:22:39 PM PDT 24 Jul 28 07:22:43 PM PDT 24 485038777 ps
T250 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3767278861 Jul 28 07:22:30 PM PDT 24 Jul 28 07:22:31 PM PDT 24 83175291 ps
T2884 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.163411899 Jul 28 07:23:05 PM PDT 24 Jul 28 07:23:06 PM PDT 24 34622135 ps
T251 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2552856903 Jul 28 07:22:43 PM PDT 24 Jul 28 07:22:44 PM PDT 24 90983304 ps
T2885 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.919574000 Jul 28 07:22:34 PM PDT 24 Jul 28 07:22:36 PM PDT 24 178899940 ps
T2886 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2313522207 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:07 PM PDT 24 34916970 ps
T2887 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.420272971 Jul 28 07:22:19 PM PDT 24 Jul 28 07:22:20 PM PDT 24 70915040 ps
T2888 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4258986259 Jul 28 07:22:36 PM PDT 24 Jul 28 07:22:38 PM PDT 24 279057640 ps
T2889 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4098320095 Jul 28 07:23:08 PM PDT 24 Jul 28 07:23:09 PM PDT 24 82362928 ps
T252 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2321403420 Jul 28 07:22:46 PM PDT 24 Jul 28 07:22:47 PM PDT 24 88109654 ps
T219 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2272054820 Jul 28 07:22:43 PM PDT 24 Jul 28 07:22:44 PM PDT 24 94594901 ps
T222 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2988667270 Jul 28 07:22:20 PM PDT 24 Jul 28 07:22:23 PM PDT 24 103957132 ps
T2890 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.172775066 Jul 28 07:22:45 PM PDT 24 Jul 28 07:22:48 PM PDT 24 1109620946 ps
T2891 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.943813204 Jul 28 07:22:52 PM PDT 24 Jul 28 07:22:54 PM PDT 24 98468879 ps
T225 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.476303050 Jul 28 07:22:27 PM PDT 24 Jul 28 07:22:30 PM PDT 24 307847169 ps
T2892 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.725024423 Jul 28 07:22:44 PM PDT 24 Jul 28 07:22:46 PM PDT 24 84240705 ps
T2893 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2016074394 Jul 28 07:22:29 PM PDT 24 Jul 28 07:22:34 PM PDT 24 706691413 ps
T2894 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2074230031 Jul 28 07:22:17 PM PDT 24 Jul 28 07:22:18 PM PDT 24 108171196 ps
T2895 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3891548175 Jul 28 07:22:18 PM PDT 24 Jul 28 07:22:21 PM PDT 24 322521012 ps
T227 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2403629200 Jul 28 07:23:01 PM PDT 24 Jul 28 07:23:03 PM PDT 24 139611827 ps
T2896 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3633789708 Jul 28 07:23:14 PM PDT 24 Jul 28 07:23:15 PM PDT 24 54110224 ps
T2897 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3754194399 Jul 28 07:23:14 PM PDT 24 Jul 28 07:23:15 PM PDT 24 55337212 ps
T2898 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3076885878 Jul 28 07:22:35 PM PDT 24 Jul 28 07:22:36 PM PDT 24 56948047 ps
T2899 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3628304522 Jul 28 07:22:32 PM PDT 24 Jul 28 07:22:33 PM PDT 24 172163126 ps
T286 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.930834913 Jul 28 07:22:30 PM PDT 24 Jul 28 07:22:33 PM PDT 24 403010926 ps
T2900 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.636055240 Jul 28 07:23:11 PM PDT 24 Jul 28 07:23:12 PM PDT 24 45135053 ps
T2901 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.4149552979 Jul 28 07:22:59 PM PDT 24 Jul 28 07:23:00 PM PDT 24 60389949 ps
T2902 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2847568158 Jul 28 07:22:32 PM PDT 24 Jul 28 07:22:33 PM PDT 24 74563917 ps
T2903 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3874419804 Jul 28 07:23:02 PM PDT 24 Jul 28 07:23:02 PM PDT 24 46675930 ps
T2904 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2129004394 Jul 28 07:22:33 PM PDT 24 Jul 28 07:22:34 PM PDT 24 59476276 ps
T2905 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3014749401 Jul 28 07:22:39 PM PDT 24 Jul 28 07:22:40 PM PDT 24 126529975 ps
T220 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3354733644 Jul 28 07:22:36 PM PDT 24 Jul 28 07:22:38 PM PDT 24 106369380 ps
T2906 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4161350539 Jul 28 07:22:44 PM PDT 24 Jul 28 07:22:45 PM PDT 24 57927377 ps
T2907 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3272596594 Jul 28 07:22:44 PM PDT 24 Jul 28 07:22:46 PM PDT 24 69040543 ps
T2908 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3562737844 Jul 28 07:22:53 PM PDT 24 Jul 28 07:22:54 PM PDT 24 63912684 ps
T2909 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1290337636 Jul 28 07:22:31 PM PDT 24 Jul 28 07:22:32 PM PDT 24 55947433 ps
T2910 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2978142176 Jul 28 07:22:19 PM PDT 24 Jul 28 07:22:20 PM PDT 24 165440242 ps
T2911 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4149274327 Jul 28 07:22:53 PM PDT 24 Jul 28 07:22:55 PM PDT 24 157307344 ps
T2912 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1719751133 Jul 28 07:23:12 PM PDT 24 Jul 28 07:23:13 PM PDT 24 37507633 ps
T2913 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.964061232 Jul 28 07:22:36 PM PDT 24 Jul 28 07:22:38 PM PDT 24 144104621 ps
T2914 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.465358643 Jul 28 07:23:02 PM PDT 24 Jul 28 07:23:03 PM PDT 24 98591726 ps
T2915 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.312073497 Jul 28 07:22:50 PM PDT 24 Jul 28 07:22:51 PM PDT 24 43142228 ps
T2916 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4205097902 Jul 28 07:23:01 PM PDT 24 Jul 28 07:23:03 PM PDT 24 153010490 ps
T2917 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2066481150 Jul 28 07:23:09 PM PDT 24 Jul 28 07:23:10 PM PDT 24 38557433 ps
T2918 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3440813350 Jul 28 07:22:44 PM PDT 24 Jul 28 07:22:45 PM PDT 24 39581294 ps
T2919 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1640800244 Jul 28 07:22:35 PM PDT 24 Jul 28 07:22:37 PM PDT 24 212158849 ps
T2920 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3696456535 Jul 28 07:22:19 PM PDT 24 Jul 28 07:22:20 PM PDT 24 49543533 ps
T2921 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3452680294 Jul 28 07:22:18 PM PDT 24 Jul 28 07:22:20 PM PDT 24 158500576 ps
T2922 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2397794298 Jul 28 07:22:57 PM PDT 24 Jul 28 07:22:58 PM PDT 24 110545008 ps
T2923 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3552813407 Jul 28 07:22:39 PM PDT 24 Jul 28 07:22:40 PM PDT 24 179838510 ps
T2924 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4099573127 Jul 28 07:22:25 PM PDT 24 Jul 28 07:22:26 PM PDT 24 116297364 ps
T2925 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3438355436 Jul 28 07:22:28 PM PDT 24 Jul 28 07:22:33 PM PDT 24 829428779 ps
T2926 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2127319206 Jul 28 07:22:20 PM PDT 24 Jul 28 07:22:22 PM PDT 24 78282668 ps
T2927 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3023113302 Jul 28 07:22:35 PM PDT 24 Jul 28 07:22:35 PM PDT 24 50064923 ps
T2928 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.37366099 Jul 28 07:22:34 PM PDT 24 Jul 28 07:22:36 PM PDT 24 177560642 ps
T2929 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3017302532 Jul 28 07:23:11 PM PDT 24 Jul 28 07:23:11 PM PDT 24 46732480 ps
T283 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3537257443 Jul 28 07:22:27 PM PDT 24 Jul 28 07:22:32 PM PDT 24 709229871 ps
T2930 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1969046490 Jul 28 07:22:39 PM PDT 24 Jul 28 07:22:40 PM PDT 24 79133053 ps
T290 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.748404864 Jul 28 07:22:16 PM PDT 24 Jul 28 07:22:19 PM PDT 24 382966660 ps
T2931 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.748912484 Jul 28 07:23:08 PM PDT 24 Jul 28 07:23:09 PM PDT 24 61852567 ps
T2932 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1144617769 Jul 28 07:22:40 PM PDT 24 Jul 28 07:22:42 PM PDT 24 175424852 ps
T2933 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2141451432 Jul 28 07:22:44 PM PDT 24 Jul 28 07:22:46 PM PDT 24 84264334 ps
T221 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3509841145 Jul 28 07:22:54 PM PDT 24 Jul 28 07:22:56 PM PDT 24 239861524 ps
T2934 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3220821872 Jul 28 07:22:20 PM PDT 24 Jul 28 07:22:24 PM PDT 24 131301482 ps
T2935 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2825432015 Jul 28 07:22:21 PM PDT 24 Jul 28 07:22:30 PM PDT 24 743964482 ps
T2936 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1490943884 Jul 28 07:22:39 PM PDT 24 Jul 28 07:22:40 PM PDT 24 193097926 ps
T2937 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2120745632 Jul 28 07:23:12 PM PDT 24 Jul 28 07:23:13 PM PDT 24 46273297 ps
T2938 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.16101636 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:07 PM PDT 24 71097330 ps
T2939 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2271623093 Jul 28 07:23:05 PM PDT 24 Jul 28 07:23:06 PM PDT 24 188403189 ps
T2940 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.91952005 Jul 28 07:23:12 PM PDT 24 Jul 28 07:23:13 PM PDT 24 92782261 ps
T2941 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2789493527 Jul 28 07:22:20 PM PDT 24 Jul 28 07:22:21 PM PDT 24 44254910 ps
T2942 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1956763690 Jul 28 07:22:35 PM PDT 24 Jul 28 07:22:36 PM PDT 24 60849881 ps
T2943 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3475401517 Jul 28 07:22:31 PM PDT 24 Jul 28 07:22:33 PM PDT 24 239511534 ps
T2944 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2778243923 Jul 28 07:23:02 PM PDT 24 Jul 28 07:23:04 PM PDT 24 62141199 ps
T2945 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1346421259 Jul 28 07:23:05 PM PDT 24 Jul 28 07:23:06 PM PDT 24 31340693 ps
T2946 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.355435107 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:07 PM PDT 24 54780323 ps
T285 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3368572302 Jul 28 07:22:49 PM PDT 24 Jul 28 07:22:52 PM PDT 24 390545642 ps
T2947 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3689415638 Jul 28 07:22:30 PM PDT 24 Jul 28 07:22:31 PM PDT 24 130377189 ps
T2948 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.4118851056 Jul 28 07:22:34 PM PDT 24 Jul 28 07:22:36 PM PDT 24 78086629 ps
T223 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.459994428 Jul 28 07:22:34 PM PDT 24 Jul 28 07:22:37 PM PDT 24 457156208 ps
T2949 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1905177823 Jul 28 07:22:55 PM PDT 24 Jul 28 07:22:57 PM PDT 24 61015350 ps
T2950 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.214171944 Jul 28 07:22:33 PM PDT 24 Jul 28 07:22:34 PM PDT 24 80376220 ps
T291 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2409514235 Jul 28 07:22:35 PM PDT 24 Jul 28 07:22:40 PM PDT 24 1003016077 ps
T2951 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.4288588622 Jul 28 07:23:07 PM PDT 24 Jul 28 07:23:08 PM PDT 24 62999727 ps
T2952 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3021624174 Jul 28 07:22:35 PM PDT 24 Jul 28 07:22:37 PM PDT 24 170638123 ps
T2953 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2529748535 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:07 PM PDT 24 37271046 ps
T2954 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2049075146 Jul 28 07:23:01 PM PDT 24 Jul 28 07:23:06 PM PDT 24 879023926 ps
T2955 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3547294513 Jul 28 07:22:39 PM PDT 24 Jul 28 07:22:41 PM PDT 24 139457684 ps
T2956 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2787071206 Jul 28 07:22:47 PM PDT 24 Jul 28 07:22:50 PM PDT 24 138440988 ps
T2957 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3098700019 Jul 28 07:22:39 PM PDT 24 Jul 28 07:22:40 PM PDT 24 93300123 ps
T2958 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2056167272 Jul 28 07:22:23 PM PDT 24 Jul 28 07:22:25 PM PDT 24 171011841 ps
T2959 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2759212016 Jul 28 07:22:31 PM PDT 24 Jul 28 07:22:33 PM PDT 24 87318393 ps
T2960 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.439544675 Jul 28 07:22:58 PM PDT 24 Jul 28 07:22:58 PM PDT 24 51912111 ps
T2961 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1850172693 Jul 28 07:23:10 PM PDT 24 Jul 28 07:23:11 PM PDT 24 53903166 ps
T2962 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.4290453841 Jul 28 07:22:32 PM PDT 24 Jul 28 07:22:34 PM PDT 24 309446031 ps
T287 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2946523398 Jul 28 07:22:58 PM PDT 24 Jul 28 07:23:03 PM PDT 24 756230920 ps
T2963 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2877808875 Jul 28 07:22:34 PM PDT 24 Jul 28 07:22:35 PM PDT 24 100105010 ps
T2964 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1625969941 Jul 28 07:22:41 PM PDT 24 Jul 28 07:22:42 PM PDT 24 42777846 ps
T2965 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.937786013 Jul 28 07:22:19 PM PDT 24 Jul 28 07:22:21 PM PDT 24 141777314 ps
T2966 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.425063645 Jul 28 07:22:33 PM PDT 24 Jul 28 07:22:35 PM PDT 24 136379361 ps
T2967 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2363390696 Jul 28 07:22:19 PM PDT 24 Jul 28 07:22:19 PM PDT 24 35976099 ps
T2968 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.973208134 Jul 28 07:22:43 PM PDT 24 Jul 28 07:22:44 PM PDT 24 62284701 ps
T2969 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2679409902 Jul 28 07:22:48 PM PDT 24 Jul 28 07:22:49 PM PDT 24 50309278 ps
T2970 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4093787204 Jul 28 07:22:19 PM PDT 24 Jul 28 07:22:22 PM PDT 24 388428920 ps
T292 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1576863121 Jul 28 07:22:52 PM PDT 24 Jul 28 07:22:57 PM PDT 24 896134312 ps
T2971 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1823363200 Jul 28 07:22:37 PM PDT 24 Jul 28 07:22:40 PM PDT 24 151896276 ps
T2972 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2701867632 Jul 28 07:23:04 PM PDT 24 Jul 28 07:23:04 PM PDT 24 39934298 ps
T2973 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1271375221 Jul 28 07:22:48 PM PDT 24 Jul 28 07:22:49 PM PDT 24 117916302 ps
T2974 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2436143645 Jul 28 07:22:25 PM PDT 24 Jul 28 07:22:28 PM PDT 24 176245174 ps
T2975 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.499572707 Jul 28 07:23:11 PM PDT 24 Jul 28 07:23:12 PM PDT 24 46833533 ps
T2976 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3509982781 Jul 28 07:22:33 PM PDT 24 Jul 28 07:22:35 PM PDT 24 85305005 ps
T2977 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.525549776 Jul 28 07:22:21 PM PDT 24 Jul 28 07:22:23 PM PDT 24 78296907 ps
T2978 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2322439126 Jul 28 07:22:30 PM PDT 24 Jul 28 07:22:31 PM PDT 24 107646622 ps

Test location /workspace/coverage/default/0.usbdev_streaming_out.3552499616
Short name T4
Test name
Test status
Simulation time 5144477094 ps
CPU time 50.84 seconds
Started Jul 28 07:38:17 PM PDT 24
Finished Jul 28 07:39:08 PM PDT 24
Peak memory 207352 kb
Host smart-9dfff376-a2f8-4e1f-8963-c73177be092a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35524
99616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3552499616
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_device_address.1207002106
Short name T18
Test name
Test status
Simulation time 20730553036 ps
CPU time 46.43 seconds
Started Jul 28 07:39:03 PM PDT 24
Finished Jul 28 07:39:50 PM PDT 24
Peak memory 207372 kb
Host smart-c21b7090-e168-49df-bbf1-9b69517fcb5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12070
02106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1207002106
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2621143607
Short name T8
Test name
Test status
Simulation time 23307488271 ps
CPU time 28.12 seconds
Started Jul 28 07:40:04 PM PDT 24
Finished Jul 28 07:40:32 PM PDT 24
Peak memory 207364 kb
Host smart-18de1ddc-0add-4ce4-a975-ac9fbe98b8bb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621143607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_resume.2621143607
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3465660998
Short name T199
Test name
Test status
Simulation time 56331565 ps
CPU time 0.77 seconds
Started Jul 28 07:22:30 PM PDT 24
Finished Jul 28 07:22:31 PM PDT 24
Peak memory 206128 kb
Host smart-98b1f046-f657-4501-8be8-4e6d57803a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3465660998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3465660998
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1757114888
Short name T192
Test name
Test status
Simulation time 185106888 ps
CPU time 2.07 seconds
Started Jul 28 07:23:01 PM PDT 24
Finished Jul 28 07:23:03 PM PDT 24
Peak memory 214772 kb
Host smart-63a6c34d-032d-419a-b44a-ab9e09112872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757114888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1757114888
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.940758557
Short name T99
Test name
Test status
Simulation time 197718617 ps
CPU time 0.95 seconds
Started Jul 28 07:38:19 PM PDT 24
Finished Jul 28 07:38:20 PM PDT 24
Peak memory 207148 kb
Host smart-af1e7600-3bb9-42b1-9945-d741637e4930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94075
8557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.940758557
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1705809074
Short name T6
Test name
Test status
Simulation time 11432594077 ps
CPU time 113.25 seconds
Started Jul 28 07:38:14 PM PDT 24
Finished Jul 28 07:40:07 PM PDT 24
Peak memory 217880 kb
Host smart-b0769358-2d3e-4a7e-9d79-72e472d12075
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705809074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.1705809074
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2251699851
Short name T29
Test name
Test status
Simulation time 172334104 ps
CPU time 0.97 seconds
Started Jul 28 07:43:32 PM PDT 24
Finished Jul 28 07:43:33 PM PDT 24
Peak memory 207196 kb
Host smart-5494ad81-b9c5-4d40-b7eb-4b92b1dd27f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2251699851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2251699851
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.2942637600
Short name T39
Test name
Test status
Simulation time 163620680 ps
CPU time 0.84 seconds
Started Jul 28 07:40:34 PM PDT 24
Finished Jul 28 07:40:35 PM PDT 24
Peak memory 207096 kb
Host smart-73c17f05-1f0a-4086-9b48-a6a860deb3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29426
37600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2942637600
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.956507899
Short name T187
Test name
Test status
Simulation time 1341026327 ps
CPU time 2.22 seconds
Started Jul 28 07:38:26 PM PDT 24
Finished Jul 28 07:38:29 PM PDT 24
Peak memory 223908 kb
Host smart-f065a908-2567-4729-b306-2e57f09cb363
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=956507899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.956507899
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2053854902
Short name T112
Test name
Test status
Simulation time 205421227 ps
CPU time 0.98 seconds
Started Jul 28 07:44:14 PM PDT 24
Finished Jul 28 07:44:15 PM PDT 24
Peak memory 207136 kb
Host smart-0e3e349a-a4f7-4b65-a2da-0ee4af2fdeec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20538
54902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2053854902
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1557478238
Short name T7
Test name
Test status
Simulation time 4210698513 ps
CPU time 6.31 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:42:24 PM PDT 24
Peak memory 207348 kb
Host smart-263084f5-5774-4eb8-b9e1-492429ea07d0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557478238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_disconnect.1557478238
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2378545437
Short name T263
Test name
Test status
Simulation time 49154437 ps
CPU time 0.73 seconds
Started Jul 28 07:22:39 PM PDT 24
Finished Jul 28 07:22:40 PM PDT 24
Peak memory 206060 kb
Host smart-0478e7fe-3123-4de6-8961-6111ceb363f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2378545437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2378545437
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1227785477
Short name T375
Test name
Test status
Simulation time 95570426 ps
CPU time 0.74 seconds
Started Jul 28 07:40:38 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207052 kb
Host smart-c7f4fe85-16e1-45d0-8b26-24508f788392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12277
85477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1227785477
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.4018379485
Short name T85
Test name
Test status
Simulation time 1474393785 ps
CPU time 3.81 seconds
Started Jul 28 07:43:49 PM PDT 24
Finished Jul 28 07:43:53 PM PDT 24
Peak memory 207380 kb
Host smart-549a2a84-a70b-4cd9-82e9-3dd309b1049d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4018379485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.4018379485
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.4190989517
Short name T90
Test name
Test status
Simulation time 20422860362 ps
CPU time 40.68 seconds
Started Jul 28 07:40:56 PM PDT 24
Finished Jul 28 07:41:37 PM PDT 24
Peak memory 207392 kb
Host smart-4a796959-0e6e-422a-a8fb-d397582946dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41909
89517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.4190989517
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.1559260779
Short name T79
Test name
Test status
Simulation time 306524149 ps
CPU time 1.09 seconds
Started Jul 28 07:38:05 PM PDT 24
Finished Jul 28 07:38:06 PM PDT 24
Peak memory 207052 kb
Host smart-ef5af28a-5e1e-44ed-93fc-748d43eaef8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15592
60779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.1559260779
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.4218119574
Short name T229
Test name
Test status
Simulation time 2220207722 ps
CPU time 6.58 seconds
Started Jul 28 07:23:03 PM PDT 24
Finished Jul 28 07:23:10 PM PDT 24
Peak memory 206488 kb
Host smart-06c314b6-a453-49ce-b107-c56575f7cc44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4218119574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.4218119574
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2139065846
Short name T38
Test name
Test status
Simulation time 14155576347 ps
CPU time 140.46 seconds
Started Jul 28 07:38:01 PM PDT 24
Finished Jul 28 07:40:22 PM PDT 24
Peak memory 215612 kb
Host smart-a210391c-5f9c-4256-aadd-bc24561fb967
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139065846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2139065846
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.3928291810
Short name T42
Test name
Test status
Simulation time 20168651729 ps
CPU time 24.29 seconds
Started Jul 28 07:38:04 PM PDT 24
Finished Jul 28 07:38:28 PM PDT 24
Peak memory 207088 kb
Host smart-30e14bbd-6716-447a-835f-e691ffa2e489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39282
91810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.3928291810
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4294943502
Short name T201
Test name
Test status
Simulation time 100890943 ps
CPU time 0.93 seconds
Started Jul 28 07:22:26 PM PDT 24
Finished Jul 28 07:22:27 PM PDT 24
Peak memory 206236 kb
Host smart-6da493ca-a7db-4d4b-bce0-02ddcfcef263
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4294943502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.4294943502
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1496515757
Short name T278
Test name
Test status
Simulation time 65577530 ps
CPU time 0.74 seconds
Started Jul 28 07:23:06 PM PDT 24
Finished Jul 28 07:23:07 PM PDT 24
Peak memory 206092 kb
Host smart-4d67edc9-bd41-482e-8ece-e72bd9057695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1496515757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1496515757
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2988667270
Short name T222
Test name
Test status
Simulation time 103957132 ps
CPU time 2.62 seconds
Started Jul 28 07:22:20 PM PDT 24
Finished Jul 28 07:22:23 PM PDT 24
Peak memory 219800 kb
Host smart-443ec28f-c1e7-4cab-8027-f09db9fce86e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2988667270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2988667270
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.520923967
Short name T148
Test name
Test status
Simulation time 5837396134 ps
CPU time 174.83 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:47:57 PM PDT 24
Peak memory 215552 kb
Host smart-ae462fb4-88d8-4b1c-a787-867f1d94fce3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=520923967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.520923967
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1610152948
Short name T69
Test name
Test status
Simulation time 146822966 ps
CPU time 0.81 seconds
Started Jul 28 07:38:03 PM PDT 24
Finished Jul 28 07:38:03 PM PDT 24
Peak memory 207120 kb
Host smart-3f85169b-1f08-4bdc-8a48-15e614b589df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16101
52948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1610152948
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.2969786980
Short name T562
Test name
Test status
Simulation time 153090433 ps
CPU time 0.86 seconds
Started Jul 28 07:39:47 PM PDT 24
Finished Jul 28 07:39:48 PM PDT 24
Peak memory 207052 kb
Host smart-b4215e14-c875-4152-b506-940bf9db5334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29697
86980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.2969786980
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2863626169
Short name T46
Test name
Test status
Simulation time 244412541 ps
CPU time 1 seconds
Started Jul 28 07:38:36 PM PDT 24
Finished Jul 28 07:38:37 PM PDT 24
Peak memory 207124 kb
Host smart-f1b54657-e2e6-4ae3-839a-3f056ce51d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28636
26169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2863626169
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_device_address.1601445065
Short name T160
Test name
Test status
Simulation time 6852441913 ps
CPU time 15.61 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:17 PM PDT 24
Peak memory 207412 kb
Host smart-4472d607-bd3d-41b4-899b-b574f3eb1798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16014
45065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.1601445065
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.4078803107
Short name T2633
Test name
Test status
Simulation time 421159874 ps
CPU time 1.49 seconds
Started Jul 28 07:38:17 PM PDT 24
Finished Jul 28 07:38:18 PM PDT 24
Peak memory 207060 kb
Host smart-d41b3f63-f54f-47eb-8e5a-6957ba6aee0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40788
03107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.4078803107
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.963102836
Short name T66
Test name
Test status
Simulation time 517270601 ps
CPU time 1.5 seconds
Started Jul 28 07:37:56 PM PDT 24
Finished Jul 28 07:37:57 PM PDT 24
Peak memory 207116 kb
Host smart-32353ebd-9bdd-46e5-8062-64d4be742be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96310
2836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.963102836
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.2945197505
Short name T466
Test name
Test status
Simulation time 53107551 ps
CPU time 0.71 seconds
Started Jul 28 07:38:03 PM PDT 24
Finished Jul 28 07:38:04 PM PDT 24
Peak memory 207152 kb
Host smart-51b7bfeb-faa1-4cc4-9519-e3e84e296b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2945197505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.2945197505
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.597235319
Short name T58
Test name
Test status
Simulation time 906455097 ps
CPU time 19.35 seconds
Started Jul 28 07:42:32 PM PDT 24
Finished Jul 28 07:42:51 PM PDT 24
Peak memory 207236 kb
Host smart-50c8c174-a5a5-4201-92f2-584900c34037
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597235319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.597235319
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3955830346
Short name T213
Test name
Test status
Simulation time 13322819487 ps
CPU time 14.87 seconds
Started Jul 28 07:41:14 PM PDT 24
Finished Jul 28 07:41:29 PM PDT 24
Peak memory 207376 kb
Host smart-d209aee3-6afb-4b07-ade8-871d6bcda902
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955830346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3955830346
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.2418015830
Short name T304
Test name
Test status
Simulation time 117198577179 ps
CPU time 220.68 seconds
Started Jul 28 07:38:03 PM PDT 24
Finished Jul 28 07:41:44 PM PDT 24
Peak memory 207384 kb
Host smart-5eba521f-fd05-4dd0-93b8-c613f5a56890
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2418015830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2418015830
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1900065999
Short name T191
Test name
Test status
Simulation time 727883912 ps
CPU time 4.74 seconds
Started Jul 28 07:22:44 PM PDT 24
Finished Jul 28 07:22:49 PM PDT 24
Peak memory 206512 kb
Host smart-fd2e72bc-3591-49b2-8ad7-f7dd0bda9faa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1900065999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1900065999
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2395131345
Short name T254
Test name
Test status
Simulation time 196711017 ps
CPU time 1.71 seconds
Started Jul 28 07:22:23 PM PDT 24
Finished Jul 28 07:22:24 PM PDT 24
Peak memory 206456 kb
Host smart-038f5ef2-72c5-4656-a17d-cda548faf2d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2395131345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2395131345
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.3927342148
Short name T2241
Test name
Test status
Simulation time 133465437 ps
CPU time 0.82 seconds
Started Jul 28 07:37:57 PM PDT 24
Finished Jul 28 07:37:57 PM PDT 24
Peak memory 207020 kb
Host smart-56196617-4d10-49e6-a04b-8f0c3e9daa9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39273
42148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3927342148
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2332382112
Short name T197
Test name
Test status
Simulation time 56649844 ps
CPU time 0.74 seconds
Started Jul 28 07:22:43 PM PDT 24
Finished Jul 28 07:22:43 PM PDT 24
Peak memory 206164 kb
Host smart-17113648-e893-4f66-956e-d7ba2c0df8ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2332382112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2332382112
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2787071206
Short name T2956
Test name
Test status
Simulation time 138440988 ps
CPU time 3.78 seconds
Started Jul 28 07:22:47 PM PDT 24
Finished Jul 28 07:22:50 PM PDT 24
Peak memory 222728 kb
Host smart-b7228582-f07f-4993-8db5-27372cad20f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2787071206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2787071206
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.3288959147
Short name T205
Test name
Test status
Simulation time 9498832471 ps
CPU time 279.52 seconds
Started Jul 28 07:42:02 PM PDT 24
Finished Jul 28 07:46:41 PM PDT 24
Peak memory 215632 kb
Host smart-06e671cc-6c2d-42f2-b4da-d88c5594ff42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32889
59147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.3288959147
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.2240875556
Short name T53
Test name
Test status
Simulation time 254904370 ps
CPU time 1.06 seconds
Started Jul 28 07:38:03 PM PDT 24
Finished Jul 28 07:38:05 PM PDT 24
Peak memory 207092 kb
Host smart-0c66bdfd-47d6-4b19-9ecb-b1fa0e7653db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22408
75556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.2240875556
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1348915613
Short name T236
Test name
Test status
Simulation time 8890436124 ps
CPU time 26.83 seconds
Started Jul 28 07:40:36 PM PDT 24
Finished Jul 28 07:41:03 PM PDT 24
Peak memory 215768 kb
Host smart-e1f6a525-f270-4022-9d5d-66c139fc70e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13489
15613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1348915613
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.4197750268
Short name T458
Test name
Test status
Simulation time 32822760 ps
CPU time 0.7 seconds
Started Jul 28 07:40:32 PM PDT 24
Finished Jul 28 07:40:33 PM PDT 24
Peak memory 207104 kb
Host smart-c54cf512-76a0-45d6-8443-6c477e412921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41977
50268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.4197750268
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1191176348
Short name T162
Test name
Test status
Simulation time 10290189651 ps
CPU time 289.01 seconds
Started Jul 28 07:39:31 PM PDT 24
Finished Jul 28 07:44:21 PM PDT 24
Peak memory 215580 kb
Host smart-e1d6ba80-297d-4799-b379-f8913e9ca372
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1191176348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1191176348
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.686241071
Short name T672
Test name
Test status
Simulation time 169795938 ps
CPU time 0.86 seconds
Started Jul 28 07:41:44 PM PDT 24
Finished Jul 28 07:41:45 PM PDT 24
Peak memory 207116 kb
Host smart-6925c3e8-e316-4ee9-9bd0-f1d767e65d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68624
1071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.686241071
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.748404864
Short name T290
Test name
Test status
Simulation time 382966660 ps
CPU time 2.98 seconds
Started Jul 28 07:22:16 PM PDT 24
Finished Jul 28 07:22:19 PM PDT 24
Peak memory 206592 kb
Host smart-2a666eae-5d09-46ef-9144-a055c8db9450
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=748404864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.748404864
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.4149552979
Short name T2901
Test name
Test status
Simulation time 60389949 ps
CPU time 0.76 seconds
Started Jul 28 07:22:59 PM PDT 24
Finished Jul 28 07:23:00 PM PDT 24
Peak memory 206144 kb
Host smart-2670b1f7-cf0c-4638-a2d2-c68ab17fb455
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4149552979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.4149552979
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3685394799
Short name T305
Test name
Test status
Simulation time 5123554162 ps
CPU time 143.41 seconds
Started Jul 28 07:38:16 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 215624 kb
Host smart-0fb88e96-5ddb-4c08-89d0-8c4e4a2ae342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36853
94799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3685394799
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.4108624487
Short name T294
Test name
Test status
Simulation time 98136342087 ps
CPU time 149.11 seconds
Started Jul 28 07:38:03 PM PDT 24
Finished Jul 28 07:40:32 PM PDT 24
Peak memory 207408 kb
Host smart-bd106a72-4d58-4725-8a9a-fb1d465ea8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108624487 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.4108624487
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.760362979
Short name T301
Test name
Test status
Simulation time 120153317686 ps
CPU time 193.56 seconds
Started Jul 28 07:38:07 PM PDT 24
Finished Jul 28 07:41:21 PM PDT 24
Peak memory 207344 kb
Host smart-076c1985-a98c-4e3c-856f-5d1f978dde3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760362979 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.760362979
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3400548020
Short name T594
Test name
Test status
Simulation time 171245779 ps
CPU time 0.83 seconds
Started Jul 28 07:40:12 PM PDT 24
Finished Jul 28 07:40:13 PM PDT 24
Peak memory 207200 kb
Host smart-a2cb3a00-2925-4e77-bbc9-2648e465e728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34005
48020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3400548020
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.1157615079
Short name T307
Test name
Test status
Simulation time 93172766506 ps
CPU time 144.65 seconds
Started Jul 28 07:38:20 PM PDT 24
Finished Jul 28 07:40:45 PM PDT 24
Peak memory 207392 kb
Host smart-832b6b91-e876-4528-8cd0-82721453a335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157615079 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.1157615079
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3403312786
Short name T19
Test name
Test status
Simulation time 154827780 ps
CPU time 0.91 seconds
Started Jul 28 07:42:29 PM PDT 24
Finished Jul 28 07:42:30 PM PDT 24
Peak memory 207120 kb
Host smart-2f5a51e0-6a38-4df2-9964-8f499bd376d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34033
12786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3403312786
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3702950297
Short name T297
Test name
Test status
Simulation time 16889282574 ps
CPU time 43.92 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 215724 kb
Host smart-863b9603-b809-4a18-b5d3-47ff55b4ef12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37029
50297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3702950297
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.2096101766
Short name T15
Test name
Test status
Simulation time 4327400732 ps
CPU time 6.13 seconds
Started Jul 28 07:41:07 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207412 kb
Host smart-717f404a-11df-4f96-9132-430ff9659253
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096101766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.2096101766
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.4114033492
Short name T179
Test name
Test status
Simulation time 275002594 ps
CPU time 1.93 seconds
Started Jul 28 07:40:06 PM PDT 24
Finished Jul 28 07:40:08 PM PDT 24
Peak memory 207264 kb
Host smart-9333f8cd-3ed9-434f-a68b-2a4ddb454848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41140
33492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.4114033492
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.699957299
Short name T61
Test name
Test status
Simulation time 189674498 ps
CPU time 0.88 seconds
Started Jul 28 07:38:22 PM PDT 24
Finished Jul 28 07:38:23 PM PDT 24
Peak memory 207112 kb
Host smart-38014e07-2a6c-4969-80e1-7658311ee674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69995
7299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.699957299
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.2929230911
Short name T394
Test name
Test status
Simulation time 9524527151 ps
CPU time 99.94 seconds
Started Jul 28 07:43:34 PM PDT 24
Finished Jul 28 07:45:14 PM PDT 24
Peak memory 216660 kb
Host smart-105fc49b-d335-4e54-a695-e4f8b993103a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2929230911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.2929230911
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.1548680021
Short name T49
Test name
Test status
Simulation time 180192193 ps
CPU time 0.99 seconds
Started Jul 28 07:37:52 PM PDT 24
Finished Jul 28 07:37:54 PM PDT 24
Peak memory 207156 kb
Host smart-4d67995a-ed30-4193-a6c0-e37b45c21b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15486
80021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.1548680021
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3378572594
Short name T43
Test name
Test status
Simulation time 4190516702 ps
CPU time 9.76 seconds
Started Jul 28 07:37:55 PM PDT 24
Finished Jul 28 07:38:05 PM PDT 24
Peak memory 207316 kb
Host smart-5c1565f8-ce68-4d77-a746-b92176ec3b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33785
72594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3378572594
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.3716915515
Short name T64
Test name
Test status
Simulation time 204056466 ps
CPU time 0.9 seconds
Started Jul 28 07:38:01 PM PDT 24
Finished Jul 28 07:38:02 PM PDT 24
Peak memory 207168 kb
Host smart-0e2f03c2-a12d-4f90-a03d-63c7c418245d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37169
15515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.3716915515
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.2768696826
Short name T73
Test name
Test status
Simulation time 168116620 ps
CPU time 0.94 seconds
Started Jul 28 07:38:01 PM PDT 24
Finished Jul 28 07:38:02 PM PDT 24
Peak memory 207128 kb
Host smart-d9a3f43c-0e56-48dc-92c3-a6af5312f809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27686
96826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2768696826
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.2623745026
Short name T55
Test name
Test status
Simulation time 152225314 ps
CPU time 0.85 seconds
Started Jul 28 07:38:08 PM PDT 24
Finished Jul 28 07:38:09 PM PDT 24
Peak memory 207196 kb
Host smart-3360a11f-db84-44aa-9919-00f46af7c9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26237
45026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2623745026
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.459994428
Short name T223
Test name
Test status
Simulation time 457156208 ps
CPU time 2.94 seconds
Started Jul 28 07:22:34 PM PDT 24
Finished Jul 28 07:22:37 PM PDT 24
Peak memory 206440 kb
Host smart-51205cc9-a332-475a-abf6-e64b7b898831
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=459994428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.459994428
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.4227140633
Short name T117
Test name
Test status
Simulation time 210354784 ps
CPU time 0.92 seconds
Started Jul 28 07:37:57 PM PDT 24
Finished Jul 28 07:37:58 PM PDT 24
Peak memory 207096 kb
Host smart-0e72eb50-af40-40c9-8eca-2c8d8649771e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42271
40633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.4227140633
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1430773502
Short name T130
Test name
Test status
Simulation time 224731010 ps
CPU time 0.92 seconds
Started Jul 28 07:38:18 PM PDT 24
Finished Jul 28 07:38:19 PM PDT 24
Peak memory 207204 kb
Host smart-963356dc-a31b-4421-913c-a7de3c5a3390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14307
73502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1430773502
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2560117840
Short name T128
Test name
Test status
Simulation time 179925010 ps
CPU time 0.93 seconds
Started Jul 28 07:39:50 PM PDT 24
Finished Jul 28 07:39:51 PM PDT 24
Peak memory 207136 kb
Host smart-09063a60-1575-49b5-ab50-925e85a47127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25601
17840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2560117840
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.995997372
Short name T1541
Test name
Test status
Simulation time 215988839 ps
CPU time 0.98 seconds
Started Jul 28 07:40:13 PM PDT 24
Finished Jul 28 07:40:14 PM PDT 24
Peak memory 207204 kb
Host smart-e2bc98bc-509d-45b3-964e-6e6343fa40a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99599
7372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.995997372
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2693751042
Short name T121
Test name
Test status
Simulation time 181537346 ps
CPU time 0.91 seconds
Started Jul 28 07:40:18 PM PDT 24
Finished Jul 28 07:40:19 PM PDT 24
Peak memory 207120 kb
Host smart-47147e2b-a4ae-4e0e-8084-8255e10322d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26937
51042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2693751042
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1062173895
Short name T138
Test name
Test status
Simulation time 186011222 ps
CPU time 0.93 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:13 PM PDT 24
Peak memory 207172 kb
Host smart-a30ec4ae-6242-4232-843a-b8242355a6fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10621
73895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1062173895
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.178882002
Short name T1115
Test name
Test status
Simulation time 203238285 ps
CPU time 0.97 seconds
Started Jul 28 07:38:32 PM PDT 24
Finished Jul 28 07:38:33 PM PDT 24
Peak memory 207120 kb
Host smart-6c3db248-7ed3-4819-a6ce-a24a1d9e6ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17888
2002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.178882002
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3883552768
Short name T155
Test name
Test status
Simulation time 3634645983 ps
CPU time 28.68 seconds
Started Jul 28 07:38:25 PM PDT 24
Finished Jul 28 07:38:54 PM PDT 24
Peak memory 217240 kb
Host smart-9878a461-ec4e-47ef-b2f9-e09005250df6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3883552768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3883552768
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1122229644
Short name T144
Test name
Test status
Simulation time 210284855 ps
CPU time 0.89 seconds
Started Jul 28 07:41:40 PM PDT 24
Finished Jul 28 07:41:41 PM PDT 24
Peak memory 207140 kb
Host smart-4c4d9a5a-bbdd-4025-9f4e-7faca684a649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11222
29644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1122229644
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.482019662
Short name T2088
Test name
Test status
Simulation time 213436598 ps
CPU time 0.96 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:42:14 PM PDT 24
Peak memory 207112 kb
Host smart-44c671f2-f287-4556-bbdb-91c76785810b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48201
9662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.482019662
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2328722317
Short name T136
Test name
Test status
Simulation time 180560853 ps
CPU time 0.89 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:09 PM PDT 24
Peak memory 207064 kb
Host smart-eeb2cefb-ac56-422f-a414-5aa4d8a20a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23287
22317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2328722317
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.4266850270
Short name T135
Test name
Test status
Simulation time 226068481 ps
CPU time 0.95 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207128 kb
Host smart-a173c02a-86d7-4aee-8de2-cdd44be295f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42668
50270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.4266850270
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3220821872
Short name T2934
Test name
Test status
Simulation time 131301482 ps
CPU time 3.2 seconds
Started Jul 28 07:22:20 PM PDT 24
Finished Jul 28 07:22:24 PM PDT 24
Peak memory 206348 kb
Host smart-aef6c3c8-1621-4304-99ed-8f32e3230986
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3220821872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3220821872
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1655761717
Short name T2882
Test name
Test status
Simulation time 1106001362 ps
CPU time 7.67 seconds
Started Jul 28 07:22:18 PM PDT 24
Finished Jul 28 07:22:25 PM PDT 24
Peak memory 206372 kb
Host smart-2fe28ee1-d811-4b10-a28c-6416ee5318cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1655761717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1655761717
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2074230031
Short name T2894
Test name
Test status
Simulation time 108171196 ps
CPU time 0.96 seconds
Started Jul 28 07:22:17 PM PDT 24
Finished Jul 28 07:22:18 PM PDT 24
Peak memory 206228 kb
Host smart-8494f184-b60a-4402-b326-b94bdd0dd1d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2074230031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2074230031
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.937786013
Short name T2965
Test name
Test status
Simulation time 141777314 ps
CPU time 1.98 seconds
Started Jul 28 07:22:19 PM PDT 24
Finished Jul 28 07:22:21 PM PDT 24
Peak memory 214808 kb
Host smart-b3314906-735d-4493-afca-803f739c34f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937786013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.937786013
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3696456535
Short name T2920
Test name
Test status
Simulation time 49543533 ps
CPU time 0.81 seconds
Started Jul 28 07:22:19 PM PDT 24
Finished Jul 28 07:22:20 PM PDT 24
Peak memory 206156 kb
Host smart-870ea4e4-f269-4c81-9585-74416ee2b518
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3696456535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3696456535
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2363390696
Short name T2967
Test name
Test status
Simulation time 35976099 ps
CPU time 0.74 seconds
Started Jul 28 07:22:19 PM PDT 24
Finished Jul 28 07:22:19 PM PDT 24
Peak memory 206128 kb
Host smart-f290693f-8a58-4006-82f1-9807855b1f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2363390696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2363390696
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2978142176
Short name T2910
Test name
Test status
Simulation time 165440242 ps
CPU time 1.53 seconds
Started Jul 28 07:22:19 PM PDT 24
Finished Jul 28 07:22:20 PM PDT 24
Peak memory 214580 kb
Host smart-582aced0-7ca3-496d-9aa1-66162da5969d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2978142176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2978142176
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4093787204
Short name T2970
Test name
Test status
Simulation time 388428920 ps
CPU time 2.74 seconds
Started Jul 28 07:22:19 PM PDT 24
Finished Jul 28 07:22:22 PM PDT 24
Peak memory 206296 kb
Host smart-c91cd027-1bc6-4aae-8fa1-a40563f8a1e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4093787204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.4093787204
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.10046182
Short name T2876
Test name
Test status
Simulation time 178152603 ps
CPU time 1.69 seconds
Started Jul 28 07:22:20 PM PDT 24
Finished Jul 28 07:22:22 PM PDT 24
Peak memory 206492 kb
Host smart-99e26f13-df57-4eb1-b436-3f3acd910647
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=10046182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.10046182
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3452680294
Short name T2921
Test name
Test status
Simulation time 158500576 ps
CPU time 1.88 seconds
Started Jul 28 07:22:18 PM PDT 24
Finished Jul 28 07:22:20 PM PDT 24
Peak memory 222724 kb
Host smart-315c5283-9f66-4714-89e0-5e6873ee6ef3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3452680294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3452680294
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2198058830
Short name T284
Test name
Test status
Simulation time 1467144292 ps
CPU time 5.98 seconds
Started Jul 28 07:22:19 PM PDT 24
Finished Jul 28 07:22:25 PM PDT 24
Peak memory 206400 kb
Host smart-21a52299-1d87-43b2-a9ab-22a43c17faf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2198058830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2198058830
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2056167272
Short name T2958
Test name
Test status
Simulation time 171011841 ps
CPU time 2.17 seconds
Started Jul 28 07:22:23 PM PDT 24
Finished Jul 28 07:22:25 PM PDT 24
Peak memory 206312 kb
Host smart-e0f3fb2b-e8a0-4f0b-9e72-c978e7529f15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2056167272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2056167272
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2825432015
Short name T2935
Test name
Test status
Simulation time 743964482 ps
CPU time 8.25 seconds
Started Jul 28 07:22:21 PM PDT 24
Finished Jul 28 07:22:30 PM PDT 24
Peak memory 206384 kb
Host smart-b1dc0766-62be-4238-aaec-07c1eb0a4d78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2825432015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2825432015
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.726838795
Short name T248
Test name
Test status
Simulation time 193294762 ps
CPU time 1.03 seconds
Started Jul 28 07:22:22 PM PDT 24
Finished Jul 28 07:22:23 PM PDT 24
Peak memory 206216 kb
Host smart-4672af3d-27e7-43c3-ae1a-61f18573d33e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=726838795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.726838795
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.525549776
Short name T2977
Test name
Test status
Simulation time 78296907 ps
CPU time 1.84 seconds
Started Jul 28 07:22:21 PM PDT 24
Finished Jul 28 07:22:23 PM PDT 24
Peak memory 214660 kb
Host smart-3de8d906-77cc-48f1-85ad-9a6e4fb1d13f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525549776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.525549776
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4099573127
Short name T2924
Test name
Test status
Simulation time 116297364 ps
CPU time 0.93 seconds
Started Jul 28 07:22:25 PM PDT 24
Finished Jul 28 07:22:26 PM PDT 24
Peak memory 206152 kb
Host smart-eec38623-389c-45fa-a7ed-639c4d3442c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4099573127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.4099573127
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2789493527
Short name T2941
Test name
Test status
Simulation time 44254910 ps
CPU time 0.74 seconds
Started Jul 28 07:22:20 PM PDT 24
Finished Jul 28 07:22:21 PM PDT 24
Peak memory 206116 kb
Host smart-a2b16a73-abde-41d7-a3e0-5636f270a15f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2789493527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2789493527
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2127319206
Short name T2926
Test name
Test status
Simulation time 78282668 ps
CPU time 2.27 seconds
Started Jul 28 07:22:20 PM PDT 24
Finished Jul 28 07:22:22 PM PDT 24
Peak memory 214492 kb
Host smart-80eb17d4-e0a2-4c42-b4bd-8eae5211b86a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2127319206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2127319206
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3891548175
Short name T2895
Test name
Test status
Simulation time 322521012 ps
CPU time 2.4 seconds
Started Jul 28 07:22:18 PM PDT 24
Finished Jul 28 07:22:21 PM PDT 24
Peak memory 206348 kb
Host smart-ccde0985-ac3a-4645-a200-429811780ec0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3891548175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3891548175
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3547294513
Short name T2955
Test name
Test status
Simulation time 139457684 ps
CPU time 1.26 seconds
Started Jul 28 07:22:39 PM PDT 24
Finished Jul 28 07:22:41 PM PDT 24
Peak memory 214728 kb
Host smart-a3193ab5-daee-4c02-806d-deb9cf412136
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547294513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3547294513
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3695505856
Short name T256
Test name
Test status
Simulation time 73700104 ps
CPU time 0.8 seconds
Started Jul 28 07:22:39 PM PDT 24
Finished Jul 28 07:22:40 PM PDT 24
Peak memory 206112 kb
Host smart-11da0510-4da3-444d-aeef-4c7a83b41a01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3695505856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3695505856
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1625969941
Short name T2964
Test name
Test status
Simulation time 42777846 ps
CPU time 0.7 seconds
Started Jul 28 07:22:41 PM PDT 24
Finished Jul 28 07:22:42 PM PDT 24
Peak memory 206084 kb
Host smart-a2e95793-57c1-4dd6-9887-db6e9dfe4c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1625969941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1625969941
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1144617769
Short name T2932
Test name
Test status
Simulation time 175424852 ps
CPU time 1.62 seconds
Started Jul 28 07:22:40 PM PDT 24
Finished Jul 28 07:22:42 PM PDT 24
Peak memory 206376 kb
Host smart-30216ca2-4d0f-4eee-93a1-33c506956b30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1144617769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1144617769
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.964061232
Short name T2913
Test name
Test status
Simulation time 144104621 ps
CPU time 1.67 seconds
Started Jul 28 07:22:36 PM PDT 24
Finished Jul 28 07:22:38 PM PDT 24
Peak memory 206476 kb
Host smart-ccecbabe-2ade-4904-a373-e0da1aeb52bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=964061232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.964061232
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2404952730
Short name T209
Test name
Test status
Simulation time 347075826 ps
CPU time 2.39 seconds
Started Jul 28 07:22:40 PM PDT 24
Finished Jul 28 07:22:42 PM PDT 24
Peak memory 206428 kb
Host smart-f112757d-e712-4aa5-88a7-43b371a2dbcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2404952730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2404952730
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3272596594
Short name T2907
Test name
Test status
Simulation time 69040543 ps
CPU time 1.18 seconds
Started Jul 28 07:22:44 PM PDT 24
Finished Jul 28 07:22:46 PM PDT 24
Peak memory 214036 kb
Host smart-7458cc44-e2c0-4c32-9c4d-b747e42af504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272596594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3272596594
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4161350539
Short name T2906
Test name
Test status
Simulation time 57927377 ps
CPU time 0.83 seconds
Started Jul 28 07:22:44 PM PDT 24
Finished Jul 28 07:22:45 PM PDT 24
Peak memory 206040 kb
Host smart-3f47cc88-604e-4ffe-9113-525112f9b60e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4161350539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.4161350539
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.319337896
Short name T2874
Test name
Test status
Simulation time 176245033 ps
CPU time 1.59 seconds
Started Jul 28 07:22:45 PM PDT 24
Finished Jul 28 07:22:47 PM PDT 24
Peak memory 206408 kb
Host smart-1ddab083-de2d-4698-8cab-7fe26116e0fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=319337896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.319337896
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1751849815
Short name T216
Test name
Test status
Simulation time 290606123 ps
CPU time 3.23 seconds
Started Jul 28 07:22:43 PM PDT 24
Finished Jul 28 07:22:47 PM PDT 24
Peak memory 222176 kb
Host smart-b769e594-ffb5-4410-9b0c-09185db82d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1751849815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1751849815
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2141451432
Short name T2933
Test name
Test status
Simulation time 84264334 ps
CPU time 1.91 seconds
Started Jul 28 07:22:44 PM PDT 24
Finished Jul 28 07:22:46 PM PDT 24
Peak memory 214052 kb
Host smart-e199ad44-bb82-4a7f-9328-1177289cf721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141451432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.2141451432
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2552856903
Short name T251
Test name
Test status
Simulation time 90983304 ps
CPU time 1 seconds
Started Jul 28 07:22:43 PM PDT 24
Finished Jul 28 07:22:44 PM PDT 24
Peak memory 206228 kb
Host smart-a6a5f71f-bc4e-42c0-97c2-bfe4cfc11a4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2552856903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2552856903
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3440813350
Short name T2918
Test name
Test status
Simulation time 39581294 ps
CPU time 0.78 seconds
Started Jul 28 07:22:44 PM PDT 24
Finished Jul 28 07:22:45 PM PDT 24
Peak memory 206080 kb
Host smart-c2f3e999-16b4-489b-b8ae-e364158cf0fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3440813350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3440813350
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.725024423
Short name T2892
Test name
Test status
Simulation time 84240705 ps
CPU time 1.1 seconds
Started Jul 28 07:22:44 PM PDT 24
Finished Jul 28 07:22:46 PM PDT 24
Peak memory 206400 kb
Host smart-b6e4ef14-412b-413e-873e-54e266a7ece0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=725024423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.725024423
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2436077998
Short name T218
Test name
Test status
Simulation time 145067700 ps
CPU time 3.54 seconds
Started Jul 28 07:22:44 PM PDT 24
Finished Jul 28 07:22:47 PM PDT 24
Peak memory 214664 kb
Host smart-66770036-c875-4093-99fb-dcec0109b748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2436077998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2436077998
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.172775066
Short name T2890
Test name
Test status
Simulation time 1109620946 ps
CPU time 3.5 seconds
Started Jul 28 07:22:45 PM PDT 24
Finished Jul 28 07:22:48 PM PDT 24
Peak memory 206460 kb
Host smart-12fbb4c3-a316-478c-9a5a-95d716ac9bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=172775066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.172775066
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4149274327
Short name T2911
Test name
Test status
Simulation time 157307344 ps
CPU time 1.81 seconds
Started Jul 28 07:22:53 PM PDT 24
Finished Jul 28 07:22:55 PM PDT 24
Peak memory 218324 kb
Host smart-9d65aee9-5da3-4062-9509-9eccdd033b2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149274327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.4149274327
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2321403420
Short name T252
Test name
Test status
Simulation time 88109654 ps
CPU time 1.07 seconds
Started Jul 28 07:22:46 PM PDT 24
Finished Jul 28 07:22:47 PM PDT 24
Peak memory 206204 kb
Host smart-490b3f51-56fa-4e7f-ae2b-220cf386903d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2321403420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2321403420
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2679409902
Short name T2969
Test name
Test status
Simulation time 50309278 ps
CPU time 0.72 seconds
Started Jul 28 07:22:48 PM PDT 24
Finished Jul 28 07:22:49 PM PDT 24
Peak memory 206080 kb
Host smart-dda7becd-5447-442b-ab9b-8fbb76e20020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2679409902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2679409902
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1271375221
Short name T2973
Test name
Test status
Simulation time 117916302 ps
CPU time 1.58 seconds
Started Jul 28 07:22:48 PM PDT 24
Finished Jul 28 07:22:49 PM PDT 24
Peak memory 206468 kb
Host smart-a0c51a11-ef1d-4394-8b72-201bfb1dbbb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1271375221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1271375221
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2272054820
Short name T219
Test name
Test status
Simulation time 94594901 ps
CPU time 1.35 seconds
Started Jul 28 07:22:43 PM PDT 24
Finished Jul 28 07:22:44 PM PDT 24
Peak memory 206496 kb
Host smart-be490abe-faf7-499c-a57e-68261f4ad510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2272054820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2272054820
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.415466874
Short name T232
Test name
Test status
Simulation time 500692797 ps
CPU time 2.85 seconds
Started Jul 28 07:22:49 PM PDT 24
Finished Jul 28 07:22:52 PM PDT 24
Peak memory 206484 kb
Host smart-e7abfbe9-4601-443d-807e-593866fa8bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=415466874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.415466874
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.943813204
Short name T2891
Test name
Test status
Simulation time 98468879 ps
CPU time 1.8 seconds
Started Jul 28 07:22:52 PM PDT 24
Finished Jul 28 07:22:54 PM PDT 24
Peak memory 214696 kb
Host smart-7d6c0150-b498-425b-91bc-070849404572
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943813204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.943813204
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3562737844
Short name T2908
Test name
Test status
Simulation time 63912684 ps
CPU time 0.86 seconds
Started Jul 28 07:22:53 PM PDT 24
Finished Jul 28 07:22:54 PM PDT 24
Peak memory 206088 kb
Host smart-5c00b8d2-5eec-4bce-b715-c14ff1090f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3562737844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3562737844
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.312073497
Short name T2915
Test name
Test status
Simulation time 43142228 ps
CPU time 0.72 seconds
Started Jul 28 07:22:50 PM PDT 24
Finished Jul 28 07:22:51 PM PDT 24
Peak memory 206068 kb
Host smart-9cc671a3-b59c-4dd0-a478-ba30a8042fa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=312073497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.312073497
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1922127168
Short name T2872
Test name
Test status
Simulation time 111622980 ps
CPU time 1.16 seconds
Started Jul 28 07:22:58 PM PDT 24
Finished Jul 28 07:23:00 PM PDT 24
Peak memory 206464 kb
Host smart-e3a9259a-60c9-4ef9-b46f-6a58079ed155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1922127168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1922127168
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3368572302
Short name T285
Test name
Test status
Simulation time 390545642 ps
CPU time 2.54 seconds
Started Jul 28 07:22:49 PM PDT 24
Finished Jul 28 07:22:52 PM PDT 24
Peak memory 206472 kb
Host smart-375d827d-b209-47ef-9894-04b1812df68b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3368572302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3368572302
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2180844445
Short name T211
Test name
Test status
Simulation time 144279224 ps
CPU time 2.06 seconds
Started Jul 28 07:22:55 PM PDT 24
Finished Jul 28 07:22:57 PM PDT 24
Peak memory 214716 kb
Host smart-9018e09f-1b61-444f-98eb-1285174c1b4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180844445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2180844445
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2778019307
Short name T226
Test name
Test status
Simulation time 65834449 ps
CPU time 1.03 seconds
Started Jul 28 07:22:52 PM PDT 24
Finished Jul 28 07:22:53 PM PDT 24
Peak memory 206084 kb
Host smart-bde4eff1-7af0-4b45-80cf-2f9d3de87575
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2778019307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2778019307
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1792073454
Short name T279
Test name
Test status
Simulation time 45957119 ps
CPU time 0.71 seconds
Started Jul 28 07:22:51 PM PDT 24
Finished Jul 28 07:22:52 PM PDT 24
Peak memory 206124 kb
Host smart-09b56200-953c-4629-90ba-19701f2f79fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1792073454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1792073454
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1784573522
Short name T257
Test name
Test status
Simulation time 214720292 ps
CPU time 1.65 seconds
Started Jul 28 07:23:00 PM PDT 24
Finished Jul 28 07:23:01 PM PDT 24
Peak memory 206496 kb
Host smart-2f6a9338-66b7-48ee-a32a-c32d1e3e1fea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1784573522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1784573522
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3509841145
Short name T221
Test name
Test status
Simulation time 239861524 ps
CPU time 2.5 seconds
Started Jul 28 07:22:54 PM PDT 24
Finished Jul 28 07:22:56 PM PDT 24
Peak memory 222064 kb
Host smart-c8de8844-e790-40f1-aca4-b9c3a013ada5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3509841145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3509841145
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1576863121
Short name T292
Test name
Test status
Simulation time 896134312 ps
CPU time 4.5 seconds
Started Jul 28 07:22:52 PM PDT 24
Finished Jul 28 07:22:57 PM PDT 24
Peak memory 206396 kb
Host smart-793f09cb-1c74-4ab7-8f82-08883f810a06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1576863121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1576863121
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.4206520409
Short name T234
Test name
Test status
Simulation time 152055815 ps
CPU time 1.77 seconds
Started Jul 28 07:22:58 PM PDT 24
Finished Jul 28 07:23:00 PM PDT 24
Peak memory 214752 kb
Host smart-b0139e17-e532-476d-be51-9606378d4867
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206520409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.4206520409
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.439544675
Short name T2960
Test name
Test status
Simulation time 51912111 ps
CPU time 0.8 seconds
Started Jul 28 07:22:58 PM PDT 24
Finished Jul 28 07:22:58 PM PDT 24
Peak memory 206060 kb
Host smart-8864da9d-6081-48e2-8bde-eef6ca5378ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=439544675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.439544675
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2351338857
Short name T276
Test name
Test status
Simulation time 34736989 ps
CPU time 0.73 seconds
Started Jul 28 07:22:59 PM PDT 24
Finished Jul 28 07:23:00 PM PDT 24
Peak memory 206128 kb
Host smart-019700fd-6014-419d-a3f3-708929aee5da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2351338857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2351338857
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3518453855
Short name T258
Test name
Test status
Simulation time 206469803 ps
CPU time 1.66 seconds
Started Jul 28 07:22:56 PM PDT 24
Finished Jul 28 07:22:58 PM PDT 24
Peak memory 206556 kb
Host smart-1b849f21-00fb-419f-8783-c97804e7a3f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3518453855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3518453855
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1905177823
Short name T2949
Test name
Test status
Simulation time 61015350 ps
CPU time 1.61 seconds
Started Jul 28 07:22:55 PM PDT 24
Finished Jul 28 07:22:57 PM PDT 24
Peak memory 206436 kb
Host smart-042dffe5-cc3c-46d4-bdf6-b131d2b6eef3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1905177823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1905177823
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3986514683
Short name T190
Test name
Test status
Simulation time 485260710 ps
CPU time 2.98 seconds
Started Jul 28 07:22:55 PM PDT 24
Finished Jul 28 07:22:58 PM PDT 24
Peak memory 206416 kb
Host smart-ecd73ad4-1542-44d8-b1d1-eddb55eceb36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3986514683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3986514683
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2397794298
Short name T2922
Test name
Test status
Simulation time 110545008 ps
CPU time 1.05 seconds
Started Jul 28 07:22:57 PM PDT 24
Finished Jul 28 07:22:58 PM PDT 24
Peak memory 206152 kb
Host smart-7b4c14e1-618c-47cc-a775-6dac2362ec2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2397794298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2397794298
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.254965715
Short name T2878
Test name
Test status
Simulation time 144245951 ps
CPU time 1.2 seconds
Started Jul 28 07:22:54 PM PDT 24
Finished Jul 28 07:22:55 PM PDT 24
Peak memory 206560 kb
Host smart-a904c38d-b291-44b0-947f-77b254377844
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=254965715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.254965715
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.9108912
Short name T210
Test name
Test status
Simulation time 314743266 ps
CPU time 3.28 seconds
Started Jul 28 07:22:57 PM PDT 24
Finished Jul 28 07:23:00 PM PDT 24
Peak memory 222696 kb
Host smart-2fa9881e-ab7d-4e0a-aa4d-6cd343a9b488
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=9108912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.9108912
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2946523398
Short name T287
Test name
Test status
Simulation time 756230920 ps
CPU time 5.24 seconds
Started Jul 28 07:22:58 PM PDT 24
Finished Jul 28 07:23:03 PM PDT 24
Peak memory 206492 kb
Host smart-40da6c43-3bf0-405f-922e-a2ba6578f222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2946523398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2946523398
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2778243923
Short name T2944
Test name
Test status
Simulation time 62141199 ps
CPU time 1.67 seconds
Started Jul 28 07:23:02 PM PDT 24
Finished Jul 28 07:23:04 PM PDT 24
Peak memory 214616 kb
Host smart-908891f7-8200-4b0d-b05c-fca693977499
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778243923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2778243923
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3874419804
Short name T2903
Test name
Test status
Simulation time 46675930 ps
CPU time 0.86 seconds
Started Jul 28 07:23:02 PM PDT 24
Finished Jul 28 07:23:02 PM PDT 24
Peak memory 206156 kb
Host smart-dc55b1a0-900a-4175-bdef-943e98a9d1f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3874419804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3874419804
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2911245950
Short name T264
Test name
Test status
Simulation time 45691225 ps
CPU time 0.77 seconds
Started Jul 28 07:23:00 PM PDT 24
Finished Jul 28 07:23:01 PM PDT 24
Peak memory 206168 kb
Host smart-0ddb0c5a-0c6b-446d-b418-280ca9d4248b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2911245950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2911245950
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2271623093
Short name T2939
Test name
Test status
Simulation time 188403189 ps
CPU time 1.15 seconds
Started Jul 28 07:23:05 PM PDT 24
Finished Jul 28 07:23:06 PM PDT 24
Peak memory 206508 kb
Host smart-f7cc6c53-9598-4f78-aa75-d3ecb6826bd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2271623093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2271623093
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2403629200
Short name T227
Test name
Test status
Simulation time 139611827 ps
CPU time 1.75 seconds
Started Jul 28 07:23:01 PM PDT 24
Finished Jul 28 07:23:03 PM PDT 24
Peak memory 206384 kb
Host smart-80b604e2-ff39-433d-b8c8-dac7941c81ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2403629200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2403629200
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1680922550
Short name T224
Test name
Test status
Simulation time 117532802 ps
CPU time 1.24 seconds
Started Jul 28 07:23:06 PM PDT 24
Finished Jul 28 07:23:08 PM PDT 24
Peak memory 214444 kb
Host smart-752e86d8-181d-476b-91d0-19a7309787df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680922550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1680922550
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.465358643
Short name T2914
Test name
Test status
Simulation time 98591726 ps
CPU time 1 seconds
Started Jul 28 07:23:02 PM PDT 24
Finished Jul 28 07:23:03 PM PDT 24
Peak memory 206184 kb
Host smart-4a1fd9e3-743a-4b9a-b94b-27101f2e95ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=465358643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.465358643
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2066481150
Short name T2917
Test name
Test status
Simulation time 38557433 ps
CPU time 0.7 seconds
Started Jul 28 07:23:09 PM PDT 24
Finished Jul 28 07:23:10 PM PDT 24
Peak memory 206128 kb
Host smart-6c5bc8f6-5793-4ba0-bc6e-ccb0c0a81889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2066481150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2066481150
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2777670973
Short name T2875
Test name
Test status
Simulation time 204789122 ps
CPU time 1.65 seconds
Started Jul 28 07:23:07 PM PDT 24
Finished Jul 28 07:23:09 PM PDT 24
Peak memory 206484 kb
Host smart-b4658caf-c517-4dc5-8eac-923361ce04f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2777670973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2777670973
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4205097902
Short name T2916
Test name
Test status
Simulation time 153010490 ps
CPU time 1.76 seconds
Started Jul 28 07:23:01 PM PDT 24
Finished Jul 28 07:23:03 PM PDT 24
Peak memory 206460 kb
Host smart-b30a21c3-6fff-4d44-b0d5-4d7045bc6859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4205097902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.4205097902
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2049075146
Short name T2954
Test name
Test status
Simulation time 879023926 ps
CPU time 4.88 seconds
Started Jul 28 07:23:01 PM PDT 24
Finished Jul 28 07:23:06 PM PDT 24
Peak memory 206444 kb
Host smart-82c591e9-4e4a-4320-bc34-61c43158fc8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2049075146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2049075146
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2436143645
Short name T2974
Test name
Test status
Simulation time 176245174 ps
CPU time 2.08 seconds
Started Jul 28 07:22:25 PM PDT 24
Finished Jul 28 07:22:28 PM PDT 24
Peak memory 206484 kb
Host smart-18016fd0-09ad-4a6e-bb8a-675302fb4988
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2436143645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2436143645
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3438355436
Short name T2925
Test name
Test status
Simulation time 829428779 ps
CPU time 5.06 seconds
Started Jul 28 07:22:28 PM PDT 24
Finished Jul 28 07:22:33 PM PDT 24
Peak memory 206348 kb
Host smart-92e1c509-0c2c-4840-ab6c-f5236574d37e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3438355436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3438355436
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1753758135
Short name T231
Test name
Test status
Simulation time 132031765 ps
CPU time 1.32 seconds
Started Jul 28 07:22:29 PM PDT 24
Finished Jul 28 07:22:30 PM PDT 24
Peak memory 214588 kb
Host smart-09470613-7812-4946-a3d8-92d29c4f6ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753758135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1753758135
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2218914149
Short name T255
Test name
Test status
Simulation time 52118433 ps
CPU time 0.85 seconds
Started Jul 28 07:22:27 PM PDT 24
Finished Jul 28 07:22:28 PM PDT 24
Peak memory 206180 kb
Host smart-412a6c72-5c57-429a-8d84-15b51fe031e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2218914149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2218914149
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.420272971
Short name T2887
Test name
Test status
Simulation time 70915040 ps
CPU time 0.74 seconds
Started Jul 28 07:22:19 PM PDT 24
Finished Jul 28 07:22:20 PM PDT 24
Peak memory 206172 kb
Host smart-f7f2277d-cf9a-4a1d-90a6-10ae25662b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=420272971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.420272971
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3701065693
Short name T244
Test name
Test status
Simulation time 175463225 ps
CPU time 2.4 seconds
Started Jul 28 07:22:21 PM PDT 24
Finished Jul 28 07:22:24 PM PDT 24
Peak memory 214604 kb
Host smart-01c3f058-91b4-4f4c-be75-db4cdf487650
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3701065693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3701065693
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4069868265
Short name T2870
Test name
Test status
Simulation time 105875169 ps
CPU time 2.35 seconds
Started Jul 28 07:22:21 PM PDT 24
Finished Jul 28 07:22:24 PM PDT 24
Peak memory 206360 kb
Host smart-48ae4af8-f5c2-4f07-a1c9-928c29578da3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4069868265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.4069868265
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3085133035
Short name T259
Test name
Test status
Simulation time 186110620 ps
CPU time 1.56 seconds
Started Jul 28 07:22:28 PM PDT 24
Finished Jul 28 07:22:29 PM PDT 24
Peak memory 206380 kb
Host smart-d815047f-fffc-406e-b402-8298a657d0ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3085133035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3085133035
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2712488079
Short name T217
Test name
Test status
Simulation time 198496927 ps
CPU time 2.08 seconds
Started Jul 28 07:22:22 PM PDT 24
Finished Jul 28 07:22:24 PM PDT 24
Peak memory 214732 kb
Host smart-c92473ad-aa82-4fc8-b305-19a4b8b0a545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2712488079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2712488079
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.732737104
Short name T230
Test name
Test status
Simulation time 444461118 ps
CPU time 2.62 seconds
Started Jul 28 07:22:22 PM PDT 24
Finished Jul 28 07:22:25 PM PDT 24
Peak memory 206524 kb
Host smart-75076a62-ed17-4bb8-a72f-cdc8885540fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=732737104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.732737104
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2701867632
Short name T2972
Test name
Test status
Simulation time 39934298 ps
CPU time 0.72 seconds
Started Jul 28 07:23:04 PM PDT 24
Finished Jul 28 07:23:04 PM PDT 24
Peak memory 206232 kb
Host smart-39288bb5-b2a5-44d9-924e-ed8c09b2365a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2701867632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2701867632
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1352756131
Short name T200
Test name
Test status
Simulation time 51557754 ps
CPU time 0.7 seconds
Started Jul 28 07:23:06 PM PDT 24
Finished Jul 28 07:23:07 PM PDT 24
Peak memory 206064 kb
Host smart-43f6af78-e4fc-45ae-a259-557fb9ac2eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1352756131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1352756131
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2529748535
Short name T2953
Test name
Test status
Simulation time 37271046 ps
CPU time 0.72 seconds
Started Jul 28 07:23:06 PM PDT 24
Finished Jul 28 07:23:07 PM PDT 24
Peak memory 206232 kb
Host smart-3d7f231d-cbfe-45f5-b490-e9d3697bdf16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2529748535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2529748535
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1346421259
Short name T2945
Test name
Test status
Simulation time 31340693 ps
CPU time 0.68 seconds
Started Jul 28 07:23:05 PM PDT 24
Finished Jul 28 07:23:06 PM PDT 24
Peak memory 206080 kb
Host smart-75d7b352-e7cf-4e63-827c-01c54f303089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1346421259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1346421259
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1194101289
Short name T196
Test name
Test status
Simulation time 40431962 ps
CPU time 0.71 seconds
Started Jul 28 07:23:05 PM PDT 24
Finished Jul 28 07:23:06 PM PDT 24
Peak memory 206160 kb
Host smart-10b156a8-f2c8-4ca5-b4e8-03ff861d86d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1194101289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1194101289
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.748912484
Short name T2931
Test name
Test status
Simulation time 61852567 ps
CPU time 0.72 seconds
Started Jul 28 07:23:08 PM PDT 24
Finished Jul 28 07:23:09 PM PDT 24
Peak memory 206108 kb
Host smart-f0c94e9e-945d-4136-8c43-8dc7dab4885a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=748912484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.748912484
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.355435107
Short name T2946
Test name
Test status
Simulation time 54780323 ps
CPU time 0.72 seconds
Started Jul 28 07:23:06 PM PDT 24
Finished Jul 28 07:23:07 PM PDT 24
Peak memory 206216 kb
Host smart-4414ede6-7586-4e1a-b847-f3867a0feff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=355435107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.355435107
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.4288588622
Short name T2951
Test name
Test status
Simulation time 62999727 ps
CPU time 0.82 seconds
Started Jul 28 07:23:07 PM PDT 24
Finished Jul 28 07:23:08 PM PDT 24
Peak memory 206176 kb
Host smart-e6717efc-9f2e-412a-b998-e83cf3b67880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4288588622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.4288588622
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1292346429
Short name T198
Test name
Test status
Simulation time 78209459 ps
CPU time 0.77 seconds
Started Jul 28 07:23:08 PM PDT 24
Finished Jul 28 07:23:09 PM PDT 24
Peak memory 206120 kb
Host smart-d29583e0-2740-418f-96bd-533a4c4f2200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1292346429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1292346429
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3034063699
Short name T246
Test name
Test status
Simulation time 125060790 ps
CPU time 3.41 seconds
Started Jul 28 07:22:30 PM PDT 24
Finished Jul 28 07:22:34 PM PDT 24
Peak memory 206372 kb
Host smart-fb04223d-183d-4795-9f0f-8c056dbcda2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3034063699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3034063699
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.640620478
Short name T245
Test name
Test status
Simulation time 910154800 ps
CPU time 5.17 seconds
Started Jul 28 07:22:26 PM PDT 24
Finished Jul 28 07:22:32 PM PDT 24
Peak memory 206384 kb
Host smart-815a84f2-992b-4e10-958a-aa41d58a839d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=640620478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.640620478
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3767278861
Short name T250
Test name
Test status
Simulation time 83175291 ps
CPU time 0.93 seconds
Started Jul 28 07:22:30 PM PDT 24
Finished Jul 28 07:22:31 PM PDT 24
Peak memory 206188 kb
Host smart-ab7053f3-018c-40f7-a534-42d2369508be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3767278861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3767278861
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3628304522
Short name T2899
Test name
Test status
Simulation time 172163126 ps
CPU time 1.32 seconds
Started Jul 28 07:22:32 PM PDT 24
Finished Jul 28 07:22:33 PM PDT 24
Peak memory 214820 kb
Host smart-a3ab96bf-3ddf-4169-8225-606bc15008f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628304522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3628304522
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.4101549365
Short name T243
Test name
Test status
Simulation time 97433682 ps
CPU time 1.1 seconds
Started Jul 28 07:22:30 PM PDT 24
Finished Jul 28 07:22:31 PM PDT 24
Peak memory 206148 kb
Host smart-e05e038f-1f64-4d85-b4d2-66459baf29f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4101549365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.4101549365
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3689415638
Short name T2947
Test name
Test status
Simulation time 130377189 ps
CPU time 0.85 seconds
Started Jul 28 07:22:30 PM PDT 24
Finished Jul 28 07:22:31 PM PDT 24
Peak memory 206152 kb
Host smart-308b9faf-a4c8-4a68-b77d-5ccc440a972e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3689415638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3689415638
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2322439126
Short name T2978
Test name
Test status
Simulation time 107646622 ps
CPU time 1.42 seconds
Started Jul 28 07:22:30 PM PDT 24
Finished Jul 28 07:22:31 PM PDT 24
Peak memory 206332 kb
Host smart-90798d5f-646e-4b0e-a09d-28be6011ce5e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2322439126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2322439126
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2016074394
Short name T2893
Test name
Test status
Simulation time 706691413 ps
CPU time 5.02 seconds
Started Jul 28 07:22:29 PM PDT 24
Finished Jul 28 07:22:34 PM PDT 24
Peak memory 206364 kb
Host smart-7b979561-e91d-4de0-ba01-ddaf6233eb85
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2016074394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2016074394
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1119111747
Short name T2879
Test name
Test status
Simulation time 196710783 ps
CPU time 1.62 seconds
Started Jul 28 07:22:30 PM PDT 24
Finished Jul 28 07:22:32 PM PDT 24
Peak memory 206364 kb
Host smart-0d9b6483-8af1-41fd-9586-a079ce645072
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1119111747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1119111747
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.476303050
Short name T225
Test name
Test status
Simulation time 307847169 ps
CPU time 3.28 seconds
Started Jul 28 07:22:27 PM PDT 24
Finished Jul 28 07:22:30 PM PDT 24
Peak memory 219908 kb
Host smart-77f6f4da-f9fa-4abc-8c06-72bf17aa75e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=476303050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.476303050
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3537257443
Short name T283
Test name
Test status
Simulation time 709229871 ps
CPU time 4.78 seconds
Started Jul 28 07:22:27 PM PDT 24
Finished Jul 28 07:22:32 PM PDT 24
Peak memory 206460 kb
Host smart-00e61586-5fd7-431f-9d98-21e4ac5dab6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3537257443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3537257443
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.16101636
Short name T2938
Test name
Test status
Simulation time 71097330 ps
CPU time 0.75 seconds
Started Jul 28 07:23:06 PM PDT 24
Finished Jul 28 07:23:07 PM PDT 24
Peak memory 206192 kb
Host smart-90beab0f-e2da-423c-b822-f53e4ec4a689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=16101636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.16101636
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2313522207
Short name T2886
Test name
Test status
Simulation time 34916970 ps
CPU time 0.67 seconds
Started Jul 28 07:23:06 PM PDT 24
Finished Jul 28 07:23:07 PM PDT 24
Peak memory 206116 kb
Host smart-2cce325e-f12d-4ce4-b5f1-49efc60bd728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2313522207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2313522207
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.163411899
Short name T2884
Test name
Test status
Simulation time 34622135 ps
CPU time 0.7 seconds
Started Jul 28 07:23:05 PM PDT 24
Finished Jul 28 07:23:06 PM PDT 24
Peak memory 206128 kb
Host smart-3a06080a-50d7-4bdd-85c2-0078a419b68a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=163411899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.163411899
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.499572707
Short name T2975
Test name
Test status
Simulation time 46833533 ps
CPU time 0.74 seconds
Started Jul 28 07:23:11 PM PDT 24
Finished Jul 28 07:23:12 PM PDT 24
Peak memory 206176 kb
Host smart-4f77c58c-a259-4848-8c40-85be4362e057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=499572707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.499572707
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3017302532
Short name T2929
Test name
Test status
Simulation time 46732480 ps
CPU time 0.72 seconds
Started Jul 28 07:23:11 PM PDT 24
Finished Jul 28 07:23:11 PM PDT 24
Peak memory 206176 kb
Host smart-a887006c-34d7-4d89-a9f4-d7fa7f064dad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3017302532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3017302532
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4098320095
Short name T2889
Test name
Test status
Simulation time 82362928 ps
CPU time 0.76 seconds
Started Jul 28 07:23:08 PM PDT 24
Finished Jul 28 07:23:09 PM PDT 24
Peak memory 206124 kb
Host smart-a691f08a-985d-4726-bb21-2ef756288462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4098320095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.4098320095
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2120745632
Short name T2937
Test name
Test status
Simulation time 46273297 ps
CPU time 0.72 seconds
Started Jul 28 07:23:12 PM PDT 24
Finished Jul 28 07:23:13 PM PDT 24
Peak memory 206092 kb
Host smart-ee5e3d10-d93b-4f66-8e12-dd650d018cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2120745632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2120745632
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.339803885
Short name T2877
Test name
Test status
Simulation time 39414508 ps
CPU time 0.75 seconds
Started Jul 28 07:23:11 PM PDT 24
Finished Jul 28 07:23:12 PM PDT 24
Peak memory 206028 kb
Host smart-097ddbc8-b268-4a4a-a409-29b3f8ae4757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=339803885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.339803885
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3869225630
Short name T282
Test name
Test status
Simulation time 40264607 ps
CPU time 0.73 seconds
Started Jul 28 07:23:16 PM PDT 24
Finished Jul 28 07:23:17 PM PDT 24
Peak memory 206204 kb
Host smart-2106d1cf-959f-448e-87a8-07814736e061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3869225630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3869225630
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1850172693
Short name T2961
Test name
Test status
Simulation time 53903166 ps
CPU time 0.74 seconds
Started Jul 28 07:23:10 PM PDT 24
Finished Jul 28 07:23:11 PM PDT 24
Peak memory 206172 kb
Host smart-54ca6e3e-540e-4b4d-9f81-c13eea3ca99c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1850172693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1850172693
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.919574000
Short name T2885
Test name
Test status
Simulation time 178899940 ps
CPU time 2.12 seconds
Started Jul 28 07:22:34 PM PDT 24
Finished Jul 28 07:22:36 PM PDT 24
Peak memory 206304 kb
Host smart-f87dd6cb-014b-428b-89f1-b1bc4d8e882a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=919574000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.919574000
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2235260697
Short name T249
Test name
Test status
Simulation time 1889015187 ps
CPU time 8.5 seconds
Started Jul 28 07:22:39 PM PDT 24
Finished Jul 28 07:22:48 PM PDT 24
Peak memory 206396 kb
Host smart-bef39625-e5ae-4240-b8f9-7f9e98971688
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2235260697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2235260697
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1490943884
Short name T2936
Test name
Test status
Simulation time 193097926 ps
CPU time 1.06 seconds
Started Jul 28 07:22:39 PM PDT 24
Finished Jul 28 07:22:40 PM PDT 24
Peak memory 206052 kb
Host smart-7f9b0b22-aacf-4405-8ea7-3080dfb8a03e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1490943884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1490943884
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2759212016
Short name T2959
Test name
Test status
Simulation time 87318393 ps
CPU time 2.07 seconds
Started Jul 28 07:22:31 PM PDT 24
Finished Jul 28 07:22:33 PM PDT 24
Peak memory 214668 kb
Host smart-36f07eb3-c2ef-4ca8-88f8-a2fd592f7a5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759212016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2759212016
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.214171944
Short name T2950
Test name
Test status
Simulation time 80376220 ps
CPU time 1 seconds
Started Jul 28 07:22:33 PM PDT 24
Finished Jul 28 07:22:34 PM PDT 24
Peak memory 206236 kb
Host smart-fe605556-765e-467f-9224-647b89690f73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=214171944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.214171944
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2877808875
Short name T2963
Test name
Test status
Simulation time 100105010 ps
CPU time 1.56 seconds
Started Jul 28 07:22:34 PM PDT 24
Finished Jul 28 07:22:35 PM PDT 24
Peak memory 206356 kb
Host smart-43099e69-e38b-4d23-8b02-8c2ecef45b2d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2877808875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2877808875
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.510228730
Short name T2871
Test name
Test status
Simulation time 367684276 ps
CPU time 2.71 seconds
Started Jul 28 07:22:33 PM PDT 24
Finished Jul 28 07:22:36 PM PDT 24
Peak memory 206376 kb
Host smart-43b765c6-f7b3-46e5-a46e-76ecf58fd492
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=510228730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.510228730
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4095275864
Short name T253
Test name
Test status
Simulation time 94476068 ps
CPU time 1.1 seconds
Started Jul 28 07:22:31 PM PDT 24
Finished Jul 28 07:22:32 PM PDT 24
Peak memory 206448 kb
Host smart-a9bd70f1-f089-4020-8504-48c8edc74b86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4095275864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.4095275864
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1290337636
Short name T2909
Test name
Test status
Simulation time 55947433 ps
CPU time 1.51 seconds
Started Jul 28 07:22:31 PM PDT 24
Finished Jul 28 07:22:32 PM PDT 24
Peak memory 206408 kb
Host smart-ea78b990-e53f-4d99-9bf1-5fffe19be1db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1290337636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1290337636
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.4290453841
Short name T2962
Test name
Test status
Simulation time 309446031 ps
CPU time 2.43 seconds
Started Jul 28 07:22:32 PM PDT 24
Finished Jul 28 07:22:34 PM PDT 24
Peak memory 206416 kb
Host smart-534d1583-52bf-458b-8204-5115a3a37a04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4290453841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.4290453841
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.636055240
Short name T2900
Test name
Test status
Simulation time 45135053 ps
CPU time 0.71 seconds
Started Jul 28 07:23:11 PM PDT 24
Finished Jul 28 07:23:12 PM PDT 24
Peak memory 206240 kb
Host smart-ce6690b4-b39b-4987-9b8a-79aeb887d089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=636055240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.636055240
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1719751133
Short name T2912
Test name
Test status
Simulation time 37507633 ps
CPU time 0.7 seconds
Started Jul 28 07:23:12 PM PDT 24
Finished Jul 28 07:23:13 PM PDT 24
Peak memory 206116 kb
Host smart-8dc6ab00-e3d8-437d-88ec-5dbf35ee9308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1719751133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1719751133
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.229523664
Short name T281
Test name
Test status
Simulation time 39465881 ps
CPU time 0.72 seconds
Started Jul 28 07:23:11 PM PDT 24
Finished Jul 28 07:23:12 PM PDT 24
Peak memory 206160 kb
Host smart-02864c70-8d85-49c1-a986-a43f45382592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=229523664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.229523664
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3401086255
Short name T277
Test name
Test status
Simulation time 36299188 ps
CPU time 0.72 seconds
Started Jul 28 07:23:13 PM PDT 24
Finished Jul 28 07:23:14 PM PDT 24
Peak memory 206128 kb
Host smart-f9b37926-8d61-433e-be2a-8c36004118d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3401086255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3401086255
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3633789708
Short name T2896
Test name
Test status
Simulation time 54110224 ps
CPU time 0.73 seconds
Started Jul 28 07:23:14 PM PDT 24
Finished Jul 28 07:23:15 PM PDT 24
Peak memory 206128 kb
Host smart-f3d9395b-b826-436e-9baa-ca38b7340b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3633789708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3633789708
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3754194399
Short name T2897
Test name
Test status
Simulation time 55337212 ps
CPU time 0.75 seconds
Started Jul 28 07:23:14 PM PDT 24
Finished Jul 28 07:23:15 PM PDT 24
Peak memory 206144 kb
Host smart-3f57f10d-8779-4470-b78c-a2828d4e8a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3754194399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3754194399
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1165228921
Short name T2880
Test name
Test status
Simulation time 31287083 ps
CPU time 0.69 seconds
Started Jul 28 07:23:15 PM PDT 24
Finished Jul 28 07:23:16 PM PDT 24
Peak memory 206128 kb
Host smart-00a6fa35-8632-427d-b15d-e0074c4f822b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1165228921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1165228921
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.58948228
Short name T2881
Test name
Test status
Simulation time 38822401 ps
CPU time 0.7 seconds
Started Jul 28 07:23:17 PM PDT 24
Finished Jul 28 07:23:18 PM PDT 24
Peak memory 206176 kb
Host smart-a7e8d8e7-6e13-442f-a777-091a78ac3ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=58948228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.58948228
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.91952005
Short name T2940
Test name
Test status
Simulation time 92782261 ps
CPU time 0.8 seconds
Started Jul 28 07:23:12 PM PDT 24
Finished Jul 28 07:23:13 PM PDT 24
Peak memory 206188 kb
Host smart-f550e692-a15c-4215-9e5e-966ce1f1c535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=91952005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.91952005
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3488204682
Short name T280
Test name
Test status
Simulation time 40881195 ps
CPU time 0.8 seconds
Started Jul 28 07:23:16 PM PDT 24
Finished Jul 28 07:23:17 PM PDT 24
Peak memory 206104 kb
Host smart-1997604e-1409-4d62-a92b-b15c30b31507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3488204682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3488204682
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.4118851056
Short name T2948
Test name
Test status
Simulation time 78086629 ps
CPU time 1.66 seconds
Started Jul 28 07:22:34 PM PDT 24
Finished Jul 28 07:22:36 PM PDT 24
Peak memory 214560 kb
Host smart-ee84f6f4-a05e-4386-8ffa-0cada873a465
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118851056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.4118851056
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1969046490
Short name T2930
Test name
Test status
Simulation time 79133053 ps
CPU time 1.05 seconds
Started Jul 28 07:22:39 PM PDT 24
Finished Jul 28 07:22:40 PM PDT 24
Peak memory 206148 kb
Host smart-001ae960-7913-4a0d-b717-d18e3f09d9dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1969046490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1969046490
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2847568158
Short name T2902
Test name
Test status
Simulation time 74563917 ps
CPU time 0.74 seconds
Started Jul 28 07:22:32 PM PDT 24
Finished Jul 28 07:22:33 PM PDT 24
Peak memory 206148 kb
Host smart-e2611c0f-c5f0-4835-9c73-8b6bd4fadb43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2847568158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2847568158
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.768183512
Short name T2873
Test name
Test status
Simulation time 438827998 ps
CPU time 2.06 seconds
Started Jul 28 07:22:33 PM PDT 24
Finished Jul 28 07:22:35 PM PDT 24
Peak memory 206420 kb
Host smart-d29df3c8-e905-4619-b63d-3253f1a75055
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=768183512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.768183512
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3509982781
Short name T2976
Test name
Test status
Simulation time 85305005 ps
CPU time 1.81 seconds
Started Jul 28 07:22:33 PM PDT 24
Finished Jul 28 07:22:35 PM PDT 24
Peak memory 222712 kb
Host smart-e3dd7a96-5ed0-43a8-9be9-de9c10765c36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3509982781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3509982781
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.930834913
Short name T286
Test name
Test status
Simulation time 403010926 ps
CPU time 2.67 seconds
Started Jul 28 07:22:30 PM PDT 24
Finished Jul 28 07:22:33 PM PDT 24
Peak memory 206296 kb
Host smart-463a1d87-4d9a-483c-8724-107e96b4e893
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=930834913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.930834913
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3098700019
Short name T2957
Test name
Test status
Simulation time 93300123 ps
CPU time 1.21 seconds
Started Jul 28 07:22:39 PM PDT 24
Finished Jul 28 07:22:40 PM PDT 24
Peak memory 214416 kb
Host smart-9c6c2254-d7fd-4f57-905c-0201fd07cd8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098700019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3098700019
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2129004394
Short name T2904
Test name
Test status
Simulation time 59476276 ps
CPU time 0.86 seconds
Started Jul 28 07:22:33 PM PDT 24
Finished Jul 28 07:22:34 PM PDT 24
Peak memory 206092 kb
Host smart-51009d97-e856-43c2-a280-7f0fdb2fa890
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2129004394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2129004394
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3475401517
Short name T2943
Test name
Test status
Simulation time 239511534 ps
CPU time 1.43 seconds
Started Jul 28 07:22:31 PM PDT 24
Finished Jul 28 07:22:33 PM PDT 24
Peak memory 206352 kb
Host smart-d84f782f-7faa-4e1a-925e-5dddb36f6b50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3475401517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3475401517
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.425063645
Short name T2966
Test name
Test status
Simulation time 136379361 ps
CPU time 1.65 seconds
Started Jul 28 07:22:33 PM PDT 24
Finished Jul 28 07:22:35 PM PDT 24
Peak memory 206456 kb
Host smart-cc06ba8c-1834-4df4-adb8-52fb72fced9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=425063645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.425063645
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2575445754
Short name T212
Test name
Test status
Simulation time 295903519 ps
CPU time 2.4 seconds
Started Jul 28 07:22:33 PM PDT 24
Finished Jul 28 07:22:35 PM PDT 24
Peak memory 206356 kb
Host smart-e7cd1ac0-895b-45d2-b4d5-1c2b144bdc22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2575445754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2575445754
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1640800244
Short name T2919
Test name
Test status
Simulation time 212158849 ps
CPU time 1.88 seconds
Started Jul 28 07:22:35 PM PDT 24
Finished Jul 28 07:22:37 PM PDT 24
Peak memory 214784 kb
Host smart-774d702c-eaf8-423b-940e-f25a676bdc45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640800244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1640800244
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3026761587
Short name T247
Test name
Test status
Simulation time 58005349 ps
CPU time 0.84 seconds
Started Jul 28 07:22:37 PM PDT 24
Finished Jul 28 07:22:38 PM PDT 24
Peak memory 206108 kb
Host smart-e108d51a-6abb-42e1-a38b-4aa35d56b48d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3026761587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3026761587
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3023113302
Short name T2927
Test name
Test status
Simulation time 50064923 ps
CPU time 0.73 seconds
Started Jul 28 07:22:35 PM PDT 24
Finished Jul 28 07:22:35 PM PDT 24
Peak memory 206120 kb
Host smart-2f4f09c8-7381-4b8e-82f2-2e0d3c56943b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3023113302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3023113302
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3552813407
Short name T2923
Test name
Test status
Simulation time 179838510 ps
CPU time 1.5 seconds
Started Jul 28 07:22:39 PM PDT 24
Finished Jul 28 07:22:40 PM PDT 24
Peak memory 206504 kb
Host smart-82b57256-6b3f-44f6-9ee6-6f889507da14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3552813407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3552813407
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3354733644
Short name T220
Test name
Test status
Simulation time 106369380 ps
CPU time 1.37 seconds
Started Jul 28 07:22:36 PM PDT 24
Finished Jul 28 07:22:38 PM PDT 24
Peak memory 206412 kb
Host smart-0a70a9e4-e011-4f03-996c-92e63be1fa4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3354733644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3354733644
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.37366099
Short name T2928
Test name
Test status
Simulation time 177560642 ps
CPU time 1.28 seconds
Started Jul 28 07:22:34 PM PDT 24
Finished Jul 28 07:22:36 PM PDT 24
Peak memory 217020 kb
Host smart-cc87aaae-0d5d-4865-82f3-471aa52fd219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37366099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_
csr_mem_rw_with_rand_reset.37366099
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4035873499
Short name T242
Test name
Test status
Simulation time 73273439 ps
CPU time 0.94 seconds
Started Jul 28 07:22:32 PM PDT 24
Finished Jul 28 07:22:34 PM PDT 24
Peak memory 206316 kb
Host smart-5891f85c-40e9-4855-9459-0803d145b05a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4035873499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.4035873499
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3076885878
Short name T2898
Test name
Test status
Simulation time 56948047 ps
CPU time 0.75 seconds
Started Jul 28 07:22:35 PM PDT 24
Finished Jul 28 07:22:36 PM PDT 24
Peak memory 206116 kb
Host smart-137009f5-267c-4394-a6d1-21e89946fdbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3076885878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3076885878
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4258986259
Short name T2888
Test name
Test status
Simulation time 279057640 ps
CPU time 1.78 seconds
Started Jul 28 07:22:36 PM PDT 24
Finished Jul 28 07:22:38 PM PDT 24
Peak memory 206424 kb
Host smart-db498006-4cdb-45af-a739-e2ddafab68ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4258986259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.4258986259
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1823363200
Short name T2971
Test name
Test status
Simulation time 151896276 ps
CPU time 2.16 seconds
Started Jul 28 07:22:37 PM PDT 24
Finished Jul 28 07:22:40 PM PDT 24
Peak memory 206392 kb
Host smart-5230ea1f-b326-4715-a609-2c30f087565d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1823363200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1823363200
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3305392914
Short name T2883
Test name
Test status
Simulation time 485038777 ps
CPU time 4 seconds
Started Jul 28 07:22:39 PM PDT 24
Finished Jul 28 07:22:43 PM PDT 24
Peak memory 206492 kb
Host smart-bcb9da33-7493-4989-b3f7-57caf8a2d3e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3305392914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3305392914
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1641673756
Short name T233
Test name
Test status
Simulation time 53328779 ps
CPU time 1.48 seconds
Started Jul 28 07:22:38 PM PDT 24
Finished Jul 28 07:22:40 PM PDT 24
Peak memory 214712 kb
Host smart-2459d8c2-8e83-4aaa-a6b8-cf2694008a9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641673756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1641673756
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.973208134
Short name T2968
Test name
Test status
Simulation time 62284701 ps
CPU time 0.92 seconds
Started Jul 28 07:22:43 PM PDT 24
Finished Jul 28 07:22:44 PM PDT 24
Peak memory 206148 kb
Host smart-78e9cb26-98e3-4d13-be3a-68769370a869
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=973208134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.973208134
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1956763690
Short name T2942
Test name
Test status
Simulation time 60849881 ps
CPU time 0.69 seconds
Started Jul 28 07:22:35 PM PDT 24
Finished Jul 28 07:22:36 PM PDT 24
Peak memory 206096 kb
Host smart-699e66c9-9124-4899-9163-392cc3fd14eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1956763690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1956763690
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3014749401
Short name T2905
Test name
Test status
Simulation time 126529975 ps
CPU time 1.1 seconds
Started Jul 28 07:22:39 PM PDT 24
Finished Jul 28 07:22:40 PM PDT 24
Peak memory 206476 kb
Host smart-4881d485-1485-4c5a-807d-921a1f4e5357
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3014749401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3014749401
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3021624174
Short name T2952
Test name
Test status
Simulation time 170638123 ps
CPU time 2.22 seconds
Started Jul 28 07:22:35 PM PDT 24
Finished Jul 28 07:22:37 PM PDT 24
Peak memory 206392 kb
Host smart-5b0eb2c6-0afd-4d93-bdaf-874f7cdbbac0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3021624174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3021624174
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2409514235
Short name T291
Test name
Test status
Simulation time 1003016077 ps
CPU time 5.04 seconds
Started Jul 28 07:22:35 PM PDT 24
Finished Jul 28 07:22:40 PM PDT 24
Peak memory 206504 kb
Host smart-39b1155e-5df7-42b4-a48e-3d32724222b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2409514235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2409514235
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1287187499
Short name T1294
Test name
Test status
Simulation time 3633806020 ps
CPU time 6.03 seconds
Started Jul 28 07:37:53 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 207316 kb
Host smart-71988c9c-2a8c-4c3c-ad62-5c0690e8ec62
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287187499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.1287187499
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.1464907369
Short name T1388
Test name
Test status
Simulation time 13338290120 ps
CPU time 16.36 seconds
Started Jul 28 07:37:52 PM PDT 24
Finished Jul 28 07:38:09 PM PDT 24
Peak memory 207372 kb
Host smart-3e4590fb-fd8d-408e-a5e9-f84ae2e1395e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464907369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.1464907369
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2710576210
Short name T1633
Test name
Test status
Simulation time 23366107265 ps
CPU time 28.43 seconds
Started Jul 28 07:37:53 PM PDT 24
Finished Jul 28 07:38:21 PM PDT 24
Peak memory 207404 kb
Host smart-d32fedb7-73be-4a7b-93e7-52da111701fb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710576210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.2710576210
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1691585166
Short name T2627
Test name
Test status
Simulation time 148897568 ps
CPU time 0.82 seconds
Started Jul 28 07:37:51 PM PDT 24
Finished Jul 28 07:37:52 PM PDT 24
Peak memory 207152 kb
Host smart-93423e63-94aa-476d-adc9-fa5caa7ccb6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16915
85166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1691585166
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1800725730
Short name T1287
Test name
Test status
Simulation time 145485658 ps
CPU time 0.82 seconds
Started Jul 28 07:37:58 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 207172 kb
Host smart-414081e9-48f4-4f83-9d90-3b440b68e8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18007
25730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1800725730
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.1691006890
Short name T2190
Test name
Test status
Simulation time 638334210 ps
CPU time 2.05 seconds
Started Jul 28 07:37:57 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 207136 kb
Host smart-dd82d837-942a-49e5-9836-3a9ab8cf7c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16910
06890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.1691006890
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2131681405
Short name T86
Test name
Test status
Simulation time 677981352 ps
CPU time 1.85 seconds
Started Jul 28 07:37:59 PM PDT 24
Finished Jul 28 07:38:01 PM PDT 24
Peak memory 207120 kb
Host smart-0c3f2dff-b34e-40e3-96b0-cef23b0306c2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2131681405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2131681405
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.1729138799
Short name T2326
Test name
Test status
Simulation time 11651882467 ps
CPU time 25.51 seconds
Started Jul 28 07:38:03 PM PDT 24
Finished Jul 28 07:38:29 PM PDT 24
Peak memory 207324 kb
Host smart-63b45700-31c7-4070-ae74-8eca0f27ba6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17291
38799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.1729138799
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.3359557086
Short name T1781
Test name
Test status
Simulation time 4375417365 ps
CPU time 28.08 seconds
Started Jul 28 07:38:04 PM PDT 24
Finished Jul 28 07:38:32 PM PDT 24
Peak memory 207340 kb
Host smart-adddaca0-eab9-417e-b6ae-b690278b43b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359557086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.3359557086
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.626577461
Short name T1596
Test name
Test status
Simulation time 515572133 ps
CPU time 1.68 seconds
Started Jul 28 07:37:58 PM PDT 24
Finished Jul 28 07:38:00 PM PDT 24
Peak memory 207096 kb
Host smart-9b61d4b7-6b61-485b-bcd1-c5d149eb0d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62657
7461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.626577461
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.2764236564
Short name T1747
Test name
Test status
Simulation time 140532516 ps
CPU time 0.81 seconds
Started Jul 28 07:37:59 PM PDT 24
Finished Jul 28 07:38:00 PM PDT 24
Peak memory 207088 kb
Host smart-688a3295-4b31-4469-8e31-f1622c35043b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27642
36564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2764236564
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.452507953
Short name T2359
Test name
Test status
Simulation time 45190149 ps
CPU time 0.7 seconds
Started Jul 28 07:37:59 PM PDT 24
Finished Jul 28 07:38:00 PM PDT 24
Peak memory 207092 kb
Host smart-2951c190-03ce-4c9f-920a-66216864e464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45250
7953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.452507953
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1407380263
Short name T916
Test name
Test status
Simulation time 870290755 ps
CPU time 2.47 seconds
Started Jul 28 07:38:03 PM PDT 24
Finished Jul 28 07:38:05 PM PDT 24
Peak memory 207232 kb
Host smart-f678fb74-7076-4128-ba22-539d812b31bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14073
80263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1407380263
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3581387790
Short name T1532
Test name
Test status
Simulation time 167836239 ps
CPU time 1.33 seconds
Started Jul 28 07:38:02 PM PDT 24
Finished Jul 28 07:38:04 PM PDT 24
Peak memory 207340 kb
Host smart-b6f11e97-3a4d-4b41-9d33-9c3cedd00235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35813
87790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3581387790
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.1957311419
Short name T303
Test name
Test status
Simulation time 101105804276 ps
CPU time 156.04 seconds
Started Jul 28 07:37:57 PM PDT 24
Finished Jul 28 07:40:33 PM PDT 24
Peak memory 207416 kb
Host smart-9245a9d4-6840-4b2e-99ab-b5af14772d07
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1957311419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.1957311419
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.3726363415
Short name T306
Test name
Test status
Simulation time 103074417038 ps
CPU time 171.53 seconds
Started Jul 28 07:37:58 PM PDT 24
Finished Jul 28 07:40:50 PM PDT 24
Peak memory 207476 kb
Host smart-d8a353cb-6661-4a08-9080-c0e716fd3411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726363415 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.3726363415
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.78873096
Short name T2557
Test name
Test status
Simulation time 106180923927 ps
CPU time 170.66 seconds
Started Jul 28 07:38:01 PM PDT 24
Finished Jul 28 07:40:51 PM PDT 24
Peak memory 207492 kb
Host smart-3081fab8-b86d-46fa-830f-781ba96359a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78873
096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.78873096
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.360648021
Short name T637
Test name
Test status
Simulation time 181505968 ps
CPU time 1.02 seconds
Started Jul 28 07:38:01 PM PDT 24
Finished Jul 28 07:38:02 PM PDT 24
Peak memory 215448 kb
Host smart-13c645ae-4983-40d9-9b14-7681312c455f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=360648021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.360648021
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3446822068
Short name T1118
Test name
Test status
Simulation time 140825465 ps
CPU time 0.83 seconds
Started Jul 28 07:37:59 PM PDT 24
Finished Jul 28 07:38:00 PM PDT 24
Peak memory 207108 kb
Host smart-3062c513-36ea-4b52-a8f7-85bc7f6a48bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34468
22068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3446822068
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1185108676
Short name T1209
Test name
Test status
Simulation time 224537835 ps
CPU time 0.97 seconds
Started Jul 28 07:37:58 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 207136 kb
Host smart-581580c9-c747-4df5-80e1-31100f311613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11851
08676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1185108676
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.3131410994
Short name T88
Test name
Test status
Simulation time 6430216534 ps
CPU time 48.74 seconds
Started Jul 28 07:37:59 PM PDT 24
Finished Jul 28 07:38:48 PM PDT 24
Peak memory 215680 kb
Host smart-d8087524-ac16-40ea-bf00-eccffa474c5e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3131410994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.3131410994
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.591325765
Short name T2052
Test name
Test status
Simulation time 193569025 ps
CPU time 0.96 seconds
Started Jul 28 07:38:04 PM PDT 24
Finished Jul 28 07:38:05 PM PDT 24
Peak memory 207168 kb
Host smart-2029bfd4-1c7f-4117-9314-2fe43c97c763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59132
5765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.591325765
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.3336079150
Short name T68
Test name
Test status
Simulation time 556018109 ps
CPU time 1.57 seconds
Started Jul 28 07:38:00 PM PDT 24
Finished Jul 28 07:38:01 PM PDT 24
Peak memory 207164 kb
Host smart-68bd6c2a-2e5d-43b5-bfd5-19c2ec60a0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33360
79150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.3336079150
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.738440285
Short name T1864
Test name
Test status
Simulation time 23285255289 ps
CPU time 26.71 seconds
Started Jul 28 07:38:01 PM PDT 24
Finished Jul 28 07:38:28 PM PDT 24
Peak memory 207296 kb
Host smart-d43aa23a-07cd-4289-9f27-bf3e79f82c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73844
0285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.738440285
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1537395412
Short name T388
Test name
Test status
Simulation time 3355640414 ps
CPU time 5.58 seconds
Started Jul 28 07:37:59 PM PDT 24
Finished Jul 28 07:38:05 PM PDT 24
Peak memory 207352 kb
Host smart-61f855ed-4680-4037-a1fa-f0e92bb86144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15373
95412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1537395412
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.2143474139
Short name T400
Test name
Test status
Simulation time 7528224771 ps
CPU time 207.15 seconds
Started Jul 28 07:37:59 PM PDT 24
Finished Jul 28 07:41:26 PM PDT 24
Peak memory 215596 kb
Host smart-84564181-c094-4f92-b648-cac9130dce8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21434
74139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.2143474139
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.1314846670
Short name T836
Test name
Test status
Simulation time 4269602008 ps
CPU time 119.26 seconds
Started Jul 28 07:37:59 PM PDT 24
Finished Jul 28 07:39:59 PM PDT 24
Peak memory 215644 kb
Host smart-3e5e415f-7ac4-41ad-9b42-dcc3a58847f3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1314846670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.1314846670
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1815613306
Short name T2344
Test name
Test status
Simulation time 251093487 ps
CPU time 1.08 seconds
Started Jul 28 07:37:57 PM PDT 24
Finished Jul 28 07:37:58 PM PDT 24
Peak memory 207076 kb
Host smart-bec61a46-3a6f-48b2-9589-6e67d633d253
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1815613306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1815613306
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1089064611
Short name T350
Test name
Test status
Simulation time 185652913 ps
CPU time 0.91 seconds
Started Jul 28 07:37:58 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 207144 kb
Host smart-4ab420a7-bc82-4753-a558-4f603b278deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10890
64611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1089064611
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2206267608
Short name T1513
Test name
Test status
Simulation time 6894473438 ps
CPU time 203.87 seconds
Started Jul 28 07:37:59 PM PDT 24
Finished Jul 28 07:41:23 PM PDT 24
Peak memory 215588 kb
Host smart-801bf5d8-1afc-49dd-9aa8-a55f782d4105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22062
67608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2206267608
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.3067610431
Short name T1084
Test name
Test status
Simulation time 3031278470 ps
CPU time 30.53 seconds
Started Jul 28 07:38:01 PM PDT 24
Finished Jul 28 07:38:32 PM PDT 24
Peak memory 215536 kb
Host smart-3e53a64d-e08d-4377-bbaa-d8eace93904f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3067610431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.3067610431
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.984128909
Short name T1728
Test name
Test status
Simulation time 193285462 ps
CPU time 0.98 seconds
Started Jul 28 07:38:03 PM PDT 24
Finished Jul 28 07:38:04 PM PDT 24
Peak memory 207048 kb
Host smart-929ac0e5-26cb-4450-9342-484a86ce16ff
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=984128909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.984128909
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.936523322
Short name T524
Test name
Test status
Simulation time 161268449 ps
CPU time 0.88 seconds
Started Jul 28 07:38:00 PM PDT 24
Finished Jul 28 07:38:00 PM PDT 24
Peak memory 207132 kb
Host smart-67783b47-1585-4603-8622-44fb56607f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93652
3322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.936523322
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2408857230
Short name T67
Test name
Test status
Simulation time 476527737 ps
CPU time 1.46 seconds
Started Jul 28 07:37:58 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 207076 kb
Host smart-4b0e85c2-b583-4ad6-b293-fdb001493a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24088
57230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2408857230
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3147122894
Short name T2821
Test name
Test status
Simulation time 174871753 ps
CPU time 0.96 seconds
Started Jul 28 07:37:58 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 207100 kb
Host smart-ace95e8c-d7c2-44ca-b281-ecc77e0f024b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31471
22894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3147122894
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.254743229
Short name T2430
Test name
Test status
Simulation time 179198972 ps
CPU time 0.87 seconds
Started Jul 28 07:37:58 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 207084 kb
Host smart-ed37467a-71fb-4636-9919-5bb0af832d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25474
3229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.254743229
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2443087341
Short name T1078
Test name
Test status
Simulation time 173635363 ps
CPU time 0.91 seconds
Started Jul 28 07:38:04 PM PDT 24
Finished Jul 28 07:38:05 PM PDT 24
Peak memory 207028 kb
Host smart-384a736d-1623-4a9a-9c76-0c1934721bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24430
87341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2443087341
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2842033210
Short name T1707
Test name
Test status
Simulation time 173242995 ps
CPU time 0.88 seconds
Started Jul 28 07:38:01 PM PDT 24
Finished Jul 28 07:38:02 PM PDT 24
Peak memory 207116 kb
Host smart-382b7f36-20f0-4a6e-a74f-0fe1ac6cd475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28420
33210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2842033210
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.388495575
Short name T2597
Test name
Test status
Simulation time 167913054 ps
CPU time 0.93 seconds
Started Jul 28 07:38:11 PM PDT 24
Finished Jul 28 07:38:12 PM PDT 24
Peak memory 207200 kb
Host smart-93ac9952-9319-4c6d-a135-413571a4f2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38849
5575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.388495575
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.2832979005
Short name T468
Test name
Test status
Simulation time 235371723 ps
CPU time 1.04 seconds
Started Jul 28 07:38:20 PM PDT 24
Finished Jul 28 07:38:21 PM PDT 24
Peak memory 207068 kb
Host smart-28eb80d7-fadd-4bf2-bc85-59e3eb4e3fc8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2832979005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.2832979005
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.3756034811
Short name T2085
Test name
Test status
Simulation time 192121340 ps
CPU time 0.95 seconds
Started Jul 28 07:38:07 PM PDT 24
Finished Jul 28 07:38:08 PM PDT 24
Peak memory 207144 kb
Host smart-1a7abb27-300c-473d-a0a9-f320d6c63a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37560
34811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.3756034811
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1142017350
Short name T1027
Test name
Test status
Simulation time 234732100 ps
CPU time 1.09 seconds
Started Jul 28 07:38:23 PM PDT 24
Finished Jul 28 07:38:25 PM PDT 24
Peak memory 207092 kb
Host smart-52509b12-a4ed-428d-9ea3-f353e4c632e0
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1142017350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1142017350
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.631692760
Short name T962
Test name
Test status
Simulation time 227283739 ps
CPU time 1 seconds
Started Jul 28 07:38:29 PM PDT 24
Finished Jul 28 07:38:30 PM PDT 24
Peak memory 207072 kb
Host smart-3a376542-9730-449e-941f-7b5d019f7e78
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=631692760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.631692760
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.669033673
Short name T2391
Test name
Test status
Simulation time 155831233 ps
CPU time 0.86 seconds
Started Jul 28 07:38:14 PM PDT 24
Finished Jul 28 07:38:15 PM PDT 24
Peak memory 207048 kb
Host smart-a53ea01d-3e17-461d-a9a3-0d13c3ea55fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66903
3673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.669033673
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1122868597
Short name T814
Test name
Test status
Simulation time 62325665 ps
CPU time 0.75 seconds
Started Jul 28 07:38:20 PM PDT 24
Finished Jul 28 07:38:21 PM PDT 24
Peak memory 207012 kb
Host smart-e98b7311-133e-419c-8f51-de16e3191788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11228
68597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1122868597
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.624272590
Short name T238
Test name
Test status
Simulation time 13500460696 ps
CPU time 35.72 seconds
Started Jul 28 07:38:03 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 215688 kb
Host smart-46b94a1f-94db-447c-b2a3-250bdc6b5505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62427
2590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.624272590
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.4050341287
Short name T289
Test name
Test status
Simulation time 151323527 ps
CPU time 0.85 seconds
Started Jul 28 07:38:05 PM PDT 24
Finished Jul 28 07:38:06 PM PDT 24
Peak memory 207080 kb
Host smart-5016e14b-ed51-4d95-ad61-269e74e38fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40503
41287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.4050341287
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.343046299
Short name T2017
Test name
Test status
Simulation time 188429038 ps
CPU time 0.94 seconds
Started Jul 28 07:38:24 PM PDT 24
Finished Jul 28 07:38:25 PM PDT 24
Peak memory 207056 kb
Host smart-c4850983-6035-4e96-93ac-1b727040bdfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34304
6299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.343046299
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.3154732646
Short name T2809
Test name
Test status
Simulation time 7245564359 ps
CPU time 210.41 seconds
Started Jul 28 07:38:04 PM PDT 24
Finished Jul 28 07:41:35 PM PDT 24
Peak memory 215556 kb
Host smart-a22f7da9-267e-49d6-9d01-8e29afd4a77b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154732646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.3154732646
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1267752789
Short name T2522
Test name
Test status
Simulation time 7839139313 ps
CPU time 207.17 seconds
Started Jul 28 07:38:03 PM PDT 24
Finished Jul 28 07:41:30 PM PDT 24
Peak memory 215572 kb
Host smart-9160929b-121c-4fcf-b3bc-2d8694ce59b8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1267752789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1267752789
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1309368812
Short name T2390
Test name
Test status
Simulation time 20731186437 ps
CPU time 127.77 seconds
Started Jul 28 07:38:17 PM PDT 24
Finished Jul 28 07:40:25 PM PDT 24
Peak memory 223492 kb
Host smart-7f1284d7-cbd9-430e-8984-8f9c4477e908
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309368812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1309368812
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.347048695
Short name T605
Test name
Test status
Simulation time 185172240 ps
CPU time 0.91 seconds
Started Jul 28 07:38:04 PM PDT 24
Finished Jul 28 07:38:05 PM PDT 24
Peak memory 207108 kb
Host smart-57e14a67-da41-478d-8b89-98e0754ad06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34704
8695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.347048695
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.1761627708
Short name T314
Test name
Test status
Simulation time 168420795 ps
CPU time 0.86 seconds
Started Jul 28 07:38:02 PM PDT 24
Finished Jul 28 07:38:03 PM PDT 24
Peak memory 207124 kb
Host smart-c9ab16c1-a7f5-4719-bca2-f307802b84f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17616
27708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.1761627708
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.113761460
Short name T202
Test name
Test status
Simulation time 304175371 ps
CPU time 1.14 seconds
Started Jul 28 07:38:03 PM PDT 24
Finished Jul 28 07:38:04 PM PDT 24
Peak memory 222988 kb
Host smart-478f5dfd-c1fd-43ee-85a1-1c537f234561
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=113761460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.113761460
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.659761527
Short name T920
Test name
Test status
Simulation time 211164733 ps
CPU time 1.01 seconds
Started Jul 28 07:38:04 PM PDT 24
Finished Jul 28 07:38:05 PM PDT 24
Peak memory 207052 kb
Host smart-67b12097-238a-44c8-899b-27df5e2f9f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65976
1527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.659761527
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3291879605
Short name T912
Test name
Test status
Simulation time 197483890 ps
CPU time 0.88 seconds
Started Jul 28 07:38:17 PM PDT 24
Finished Jul 28 07:38:18 PM PDT 24
Peak memory 207024 kb
Host smart-b609b9ce-8022-4647-87bb-28e47e4d8ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32918
79605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3291879605
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1686384177
Short name T2636
Test name
Test status
Simulation time 153461496 ps
CPU time 0.88 seconds
Started Jul 28 07:38:20 PM PDT 24
Finished Jul 28 07:38:21 PM PDT 24
Peak memory 207048 kb
Host smart-a628cace-ef4f-4fe2-b605-462af127e678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16863
84177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1686384177
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.966996069
Short name T1033
Test name
Test status
Simulation time 224203168 ps
CPU time 1 seconds
Started Jul 28 07:38:05 PM PDT 24
Finished Jul 28 07:38:06 PM PDT 24
Peak memory 207116 kb
Host smart-43161aad-ea86-4514-a740-2dfa79d48f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96699
6069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.966996069
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.347039912
Short name T686
Test name
Test status
Simulation time 4493976319 ps
CPU time 35.51 seconds
Started Jul 28 07:38:00 PM PDT 24
Finished Jul 28 07:38:36 PM PDT 24
Peak memory 216716 kb
Host smart-b13b7a2b-707c-4544-9ac9-11bc49237030
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=347039912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.347039912
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1907010753
Short name T1286
Test name
Test status
Simulation time 190569108 ps
CPU time 0.91 seconds
Started Jul 28 07:38:01 PM PDT 24
Finished Jul 28 07:38:02 PM PDT 24
Peak memory 207272 kb
Host smart-91d2461e-2cd0-407f-bf41-32a8499fab93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19070
10753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1907010753
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.1223620579
Short name T1018
Test name
Test status
Simulation time 217086748 ps
CPU time 0.88 seconds
Started Jul 28 07:38:29 PM PDT 24
Finished Jul 28 07:38:30 PM PDT 24
Peak memory 207044 kb
Host smart-8d466648-878b-4ffb-b785-9402827a4850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12236
20579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.1223620579
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.3821000428
Short name T2847
Test name
Test status
Simulation time 381516946 ps
CPU time 1.22 seconds
Started Jul 28 07:38:04 PM PDT 24
Finished Jul 28 07:38:05 PM PDT 24
Peak memory 207016 kb
Host smart-3a1bfe68-f36c-449a-a66b-1421ebca7aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38210
00428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.3821000428
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.3811195336
Short name T1926
Test name
Test status
Simulation time 154191100 ps
CPU time 0.93 seconds
Started Jul 28 07:37:54 PM PDT 24
Finished Jul 28 07:37:55 PM PDT 24
Peak memory 207156 kb
Host smart-65b4ed46-7000-4e4b-8a5f-b3466b66cf3d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811195336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host
_handshake.3811195336
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.1860698309
Short name T1307
Test name
Test status
Simulation time 80221411 ps
CPU time 0.72 seconds
Started Jul 28 07:38:13 PM PDT 24
Finished Jul 28 07:38:14 PM PDT 24
Peak memory 207108 kb
Host smart-651c70db-d649-4aec-8075-9d450f0acf05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1860698309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1860698309
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.241379425
Short name T1475
Test name
Test status
Simulation time 4289836053 ps
CPU time 6.43 seconds
Started Jul 28 07:38:06 PM PDT 24
Finished Jul 28 07:38:12 PM PDT 24
Peak memory 207344 kb
Host smart-c2a76d0a-5449-42d9-b033-ac49a5671387
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241379425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon
_wake_disconnect.241379425
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1680688257
Short name T215
Test name
Test status
Simulation time 13494760496 ps
CPU time 18.16 seconds
Started Jul 28 07:38:02 PM PDT 24
Finished Jul 28 07:38:20 PM PDT 24
Peak memory 207448 kb
Host smart-610b3dd6-14c5-44d8-8cd0-1d33ee48729e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680688257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1680688257
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1686101226
Short name T1878
Test name
Test status
Simulation time 23341141105 ps
CPU time 32.32 seconds
Started Jul 28 07:38:18 PM PDT 24
Finished Jul 28 07:38:50 PM PDT 24
Peak memory 207300 kb
Host smart-90693491-8826-458f-9cd5-b5d79904a0a2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686101226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.1686101226
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2011646587
Short name T784
Test name
Test status
Simulation time 176119740 ps
CPU time 0.93 seconds
Started Jul 28 07:38:12 PM PDT 24
Finished Jul 28 07:38:13 PM PDT 24
Peak memory 207204 kb
Host smart-c894e591-f062-4f7d-b23f-13deba5876df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20116
46587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2011646587
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.2717957168
Short name T62
Test name
Test status
Simulation time 132665883 ps
CPU time 0.87 seconds
Started Jul 28 07:38:13 PM PDT 24
Finished Jul 28 07:38:14 PM PDT 24
Peak memory 207048 kb
Host smart-0999e940-98cd-44e6-b235-769b05105e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27179
57168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.2717957168
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.3573636950
Short name T2814
Test name
Test status
Simulation time 149920464 ps
CPU time 0.87 seconds
Started Jul 28 07:38:05 PM PDT 24
Finished Jul 28 07:38:06 PM PDT 24
Peak memory 207088 kb
Host smart-acf3c228-4a2d-468a-a25c-4eb45acc6ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35736
36950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.3573636950
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.325319134
Short name T455
Test name
Test status
Simulation time 473555549 ps
CPU time 1.63 seconds
Started Jul 28 07:38:04 PM PDT 24
Finished Jul 28 07:38:06 PM PDT 24
Peak memory 207140 kb
Host smart-c30c226f-e6ce-4a7f-9211-5fd54400bfe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32531
9134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.325319134
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.644951961
Short name T2421
Test name
Test status
Simulation time 1015577637 ps
CPU time 2.52 seconds
Started Jul 28 07:38:02 PM PDT 24
Finished Jul 28 07:38:05 PM PDT 24
Peak memory 207376 kb
Host smart-3cc271f6-98d5-45a5-b2c1-11efbed4bb95
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=644951961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.644951961
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.416918176
Short name T2704
Test name
Test status
Simulation time 14607029562 ps
CPU time 28.3 seconds
Started Jul 28 07:38:25 PM PDT 24
Finished Jul 28 07:38:53 PM PDT 24
Peak memory 207344 kb
Host smart-02c04bca-487f-4466-b1e8-4ed1926708dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41691
8176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.416918176
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.3368106983
Short name T418
Test name
Test status
Simulation time 4323981959 ps
CPU time 35.27 seconds
Started Jul 28 07:38:03 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 207392 kb
Host smart-eac4c412-110a-4931-bf07-08a0a2dd411a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368106983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.3368106983
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2610597828
Short name T1626
Test name
Test status
Simulation time 365543558 ps
CPU time 1.34 seconds
Started Jul 28 07:38:02 PM PDT 24
Finished Jul 28 07:38:04 PM PDT 24
Peak memory 207104 kb
Host smart-56b07a85-47c3-4827-86c7-b7f93b725584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26105
97828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2610597828
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.2578424583
Short name T2417
Test name
Test status
Simulation time 147295740 ps
CPU time 0.85 seconds
Started Jul 28 07:38:19 PM PDT 24
Finished Jul 28 07:38:20 PM PDT 24
Peak memory 207080 kb
Host smart-f2f315eb-35f4-4b30-b7e5-c8ddc577704e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25784
24583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2578424583
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3290689039
Short name T2102
Test name
Test status
Simulation time 56352572 ps
CPU time 0.73 seconds
Started Jul 28 07:38:15 PM PDT 24
Finished Jul 28 07:38:16 PM PDT 24
Peak memory 207112 kb
Host smart-3148c8fd-ac7e-42de-8165-7156eb8cf619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32906
89039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3290689039
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.3519094894
Short name T1330
Test name
Test status
Simulation time 1086736922 ps
CPU time 2.97 seconds
Started Jul 28 07:38:08 PM PDT 24
Finished Jul 28 07:38:11 PM PDT 24
Peak memory 207348 kb
Host smart-3bde9a69-524c-438c-8e53-add51e5e431a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35190
94894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.3519094894
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.349591509
Short name T1300
Test name
Test status
Simulation time 172103719 ps
CPU time 1.81 seconds
Started Jul 28 07:38:06 PM PDT 24
Finished Jul 28 07:38:08 PM PDT 24
Peak memory 207348 kb
Host smart-08c17642-a234-4e0c-9c64-a2a15859d528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34959
1509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.349591509
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.2998885689
Short name T923
Test name
Test status
Simulation time 117194743631 ps
CPU time 179.64 seconds
Started Jul 28 07:38:08 PM PDT 24
Finished Jul 28 07:41:08 PM PDT 24
Peak memory 207328 kb
Host smart-3d194edc-1f32-4f21-ac13-7a2d9b12f5a0
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2998885689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.2998885689
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.1719303256
Short name T817
Test name
Test status
Simulation time 104109737979 ps
CPU time 168.34 seconds
Started Jul 28 07:38:16 PM PDT 24
Finished Jul 28 07:41:04 PM PDT 24
Peak memory 207248 kb
Host smart-6898e17f-b153-40e5-a0ad-8efc9c74a4f4
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1719303256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.1719303256
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.1069037807
Short name T302
Test name
Test status
Simulation time 119920200557 ps
CPU time 193.24 seconds
Started Jul 28 07:38:26 PM PDT 24
Finished Jul 28 07:41:39 PM PDT 24
Peak memory 207436 kb
Host smart-1dfc26f2-6dc1-4a5e-baaf-e9b0d3b62e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069037807 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.1069037807
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.156644142
Short name T1578
Test name
Test status
Simulation time 87233592831 ps
CPU time 137.14 seconds
Started Jul 28 07:38:08 PM PDT 24
Finished Jul 28 07:40:26 PM PDT 24
Peak memory 207352 kb
Host smart-ebf6e805-ed3d-4e26-bed8-28b666a00b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15664
4142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.156644142
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2045186288
Short name T1428
Test name
Test status
Simulation time 240570259 ps
CPU time 1.16 seconds
Started Jul 28 07:38:09 PM PDT 24
Finished Jul 28 07:38:10 PM PDT 24
Peak memory 207300 kb
Host smart-7775377f-e082-4025-9fc2-460c8b6db823
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2045186288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2045186288
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1890905942
Short name T2387
Test name
Test status
Simulation time 142869396 ps
CPU time 0.84 seconds
Started Jul 28 07:38:28 PM PDT 24
Finished Jul 28 07:38:29 PM PDT 24
Peak memory 207084 kb
Host smart-fcbe7682-58be-4178-adec-cdcc0e59a6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18909
05942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1890905942
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2446325693
Short name T997
Test name
Test status
Simulation time 234341228 ps
CPU time 1.07 seconds
Started Jul 28 07:38:17 PM PDT 24
Finished Jul 28 07:38:18 PM PDT 24
Peak memory 207172 kb
Host smart-dcbbc42c-a3bf-4d66-a20d-d352952d46df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24463
25693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2446325693
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.2732159812
Short name T1495
Test name
Test status
Simulation time 9942376493 ps
CPU time 302.98 seconds
Started Jul 28 07:38:07 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 215528 kb
Host smart-2789f130-64aa-4e2a-911c-0584811fb2ce
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2732159812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2732159812
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.257670455
Short name T634
Test name
Test status
Simulation time 10569421095 ps
CPU time 67.72 seconds
Started Jul 28 07:38:08 PM PDT 24
Finished Jul 28 07:39:16 PM PDT 24
Peak memory 207532 kb
Host smart-4170fe5d-eeac-4ce1-a3f0-980f224aa570
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=257670455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.257670455
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.1698498911
Short name T2064
Test name
Test status
Simulation time 165002496 ps
CPU time 0.88 seconds
Started Jul 28 07:38:07 PM PDT 24
Finished Jul 28 07:38:08 PM PDT 24
Peak memory 207172 kb
Host smart-fd9aa4e5-2aa3-4c44-b1df-15e77368bc28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16984
98911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1698498911
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.483172171
Short name T840
Test name
Test status
Simulation time 23315266477 ps
CPU time 28.1 seconds
Started Jul 28 07:38:08 PM PDT 24
Finished Jul 28 07:38:36 PM PDT 24
Peak memory 207360 kb
Host smart-192c5774-a2db-4257-b320-a2d2322ffce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48317
2171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.483172171
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1084745766
Short name T2732
Test name
Test status
Simulation time 3300017029 ps
CPU time 4.77 seconds
Started Jul 28 07:38:07 PM PDT 24
Finished Jul 28 07:38:12 PM PDT 24
Peak memory 207360 kb
Host smart-61fb35a4-c83f-4d09-a2c2-a61c96c2e7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10847
45766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1084745766
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.557592915
Short name T1661
Test name
Test status
Simulation time 5473130328 ps
CPU time 52.75 seconds
Started Jul 28 07:38:15 PM PDT 24
Finished Jul 28 07:39:08 PM PDT 24
Peak memory 223792 kb
Host smart-6ee9f802-f16e-4ed4-9c6d-6a6e233975df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55759
2915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.557592915
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.865362972
Short name T669
Test name
Test status
Simulation time 5463316690 ps
CPU time 57.46 seconds
Started Jul 28 07:38:24 PM PDT 24
Finished Jul 28 07:39:22 PM PDT 24
Peak memory 207492 kb
Host smart-1a3db8fb-98db-4f9c-bdab-1f18de517f44
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=865362972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.865362972
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.4259514068
Short name T1671
Test name
Test status
Simulation time 247422674 ps
CPU time 1 seconds
Started Jul 28 07:38:08 PM PDT 24
Finished Jul 28 07:38:09 PM PDT 24
Peak memory 207152 kb
Host smart-9a720556-c243-4fca-95e6-efbe77b68dfd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4259514068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.4259514068
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.21599889
Short name T2380
Test name
Test status
Simulation time 215334505 ps
CPU time 0.94 seconds
Started Jul 28 07:38:19 PM PDT 24
Finished Jul 28 07:38:20 PM PDT 24
Peak memory 207128 kb
Host smart-78c39a37-b74e-4fbf-820d-4bbc4775816b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21599
889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.21599889
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.1538176858
Short name T5
Test name
Test status
Simulation time 7187581856 ps
CPU time 216.59 seconds
Started Jul 28 07:38:07 PM PDT 24
Finished Jul 28 07:41:44 PM PDT 24
Peak memory 215776 kb
Host smart-d9317a87-9770-479a-9dc2-b9f5b73df66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15381
76858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.1538176858
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3229648809
Short name T801
Test name
Test status
Simulation time 4737613013 ps
CPU time 49.99 seconds
Started Jul 28 07:38:08 PM PDT 24
Finished Jul 28 07:38:58 PM PDT 24
Peak memory 207392 kb
Host smart-d54a0908-3d03-443b-aac7-93d9e1c9d500
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3229648809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3229648809
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.3421646397
Short name T597
Test name
Test status
Simulation time 167405526 ps
CPU time 0.84 seconds
Started Jul 28 07:38:15 PM PDT 24
Finished Jul 28 07:38:16 PM PDT 24
Peak memory 207160 kb
Host smart-6421a012-9cf4-4df0-822d-84dac79e7fb4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3421646397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.3421646397
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1940345095
Short name T2648
Test name
Test status
Simulation time 146947231 ps
CPU time 0.91 seconds
Started Jul 28 07:38:13 PM PDT 24
Finished Jul 28 07:38:14 PM PDT 24
Peak memory 207140 kb
Host smart-ec596238-ac6a-4353-8346-8a102da11f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19403
45095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1940345095
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1613582491
Short name T915
Test name
Test status
Simulation time 204579427 ps
CPU time 0.9 seconds
Started Jul 28 07:38:17 PM PDT 24
Finished Jul 28 07:38:18 PM PDT 24
Peak memory 207132 kb
Host smart-59c81637-847f-44d6-af4e-e9b5e0cbca59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16135
82491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1613582491
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2720960656
Short name T1131
Test name
Test status
Simulation time 146164725 ps
CPU time 0.89 seconds
Started Jul 28 07:38:13 PM PDT 24
Finished Jul 28 07:38:14 PM PDT 24
Peak memory 207120 kb
Host smart-6066a0bb-d68d-402e-aafd-e5de57061b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27209
60656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2720960656
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.34359416
Short name T2253
Test name
Test status
Simulation time 175397670 ps
CPU time 0.85 seconds
Started Jul 28 07:38:08 PM PDT 24
Finished Jul 28 07:38:09 PM PDT 24
Peak memory 207080 kb
Host smart-35c01302-b2e5-481b-92ab-5901e77f6c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34359
416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.34359416
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.4105805272
Short name T2756
Test name
Test status
Simulation time 205949450 ps
CPU time 0.98 seconds
Started Jul 28 07:38:12 PM PDT 24
Finished Jul 28 07:38:13 PM PDT 24
Peak memory 207176 kb
Host smart-bbae1775-af24-4fcc-9120-9a5488705e1f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4105805272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.4105805272
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.2619786341
Short name T193
Test name
Test status
Simulation time 216693710 ps
CPU time 1.07 seconds
Started Jul 28 07:38:13 PM PDT 24
Finished Jul 28 07:38:14 PM PDT 24
Peak memory 207124 kb
Host smart-951f1c10-8eaa-48b1-b88c-026680c76df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26197
86341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.2619786341
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2858699893
Short name T1712
Test name
Test status
Simulation time 138090212 ps
CPU time 0.78 seconds
Started Jul 28 07:38:08 PM PDT 24
Finished Jul 28 07:38:09 PM PDT 24
Peak memory 207064 kb
Host smart-9610c384-6e28-4980-8b8d-6bc3ad3b0e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28586
99893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2858699893
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3255033210
Short name T1032
Test name
Test status
Simulation time 38914651 ps
CPU time 0.67 seconds
Started Jul 28 07:38:12 PM PDT 24
Finished Jul 28 07:38:13 PM PDT 24
Peak memory 207068 kb
Host smart-cc15e17c-d5cc-412d-b4d4-c99e5c9de688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32550
33210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3255033210
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2053885424
Short name T260
Test name
Test status
Simulation time 7070829924 ps
CPU time 18.28 seconds
Started Jul 28 07:38:09 PM PDT 24
Finished Jul 28 07:38:28 PM PDT 24
Peak memory 215640 kb
Host smart-7043e98c-e54f-4ae5-bca7-7821dd786f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20538
85424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2053885424
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3038485046
Short name T966
Test name
Test status
Simulation time 170353265 ps
CPU time 0.89 seconds
Started Jul 28 07:38:14 PM PDT 24
Finished Jul 28 07:38:15 PM PDT 24
Peak memory 207068 kb
Host smart-f1299074-3c41-4b8c-8238-1b2e35cfbcea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30384
85046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3038485046
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1662648950
Short name T1761
Test name
Test status
Simulation time 302148667 ps
CPU time 1.04 seconds
Started Jul 28 07:38:15 PM PDT 24
Finished Jul 28 07:38:16 PM PDT 24
Peak memory 207196 kb
Host smart-0d87b77d-8b19-448c-bf71-0f03aabd12d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16626
48950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1662648950
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2429278939
Short name T159
Test name
Test status
Simulation time 10130283947 ps
CPU time 51 seconds
Started Jul 28 07:38:21 PM PDT 24
Finished Jul 28 07:39:12 PM PDT 24
Peak memory 219120 kb
Host smart-8d3c1bea-16f8-4331-94c0-495bd8886ec9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429278939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2429278939
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2907097964
Short name T2275
Test name
Test status
Simulation time 12661285920 ps
CPU time 72.5 seconds
Started Jul 28 07:38:15 PM PDT 24
Finished Jul 28 07:39:28 PM PDT 24
Peak memory 218320 kb
Host smart-f8a644e6-b870-4d2f-a0a2-a449d0ca8912
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2907097964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2907097964
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.2084079527
Short name T1562
Test name
Test status
Simulation time 16974189283 ps
CPU time 386.34 seconds
Started Jul 28 07:38:21 PM PDT 24
Finished Jul 28 07:44:47 PM PDT 24
Peak memory 215676 kb
Host smart-1184c745-fda2-4772-9760-6319af542c73
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084079527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.2084079527
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3967996350
Short name T1462
Test name
Test status
Simulation time 218545004 ps
CPU time 0.95 seconds
Started Jul 28 07:38:21 PM PDT 24
Finished Jul 28 07:38:22 PM PDT 24
Peak memory 207128 kb
Host smart-227031ea-531d-466a-aa0e-8cf5bdf155eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39679
96350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3967996350
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.531229558
Short name T2555
Test name
Test status
Simulation time 187483571 ps
CPU time 0.93 seconds
Started Jul 28 07:38:27 PM PDT 24
Finished Jul 28 07:38:28 PM PDT 24
Peak memory 207152 kb
Host smart-7538013e-09f5-4b2b-a254-646bc459eb6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53122
9558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.531229558
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.136138200
Short name T71
Test name
Test status
Simulation time 160943135 ps
CPU time 0.84 seconds
Started Jul 28 07:38:16 PM PDT 24
Finished Jul 28 07:38:17 PM PDT 24
Peak memory 207136 kb
Host smart-8b4527bc-ceba-4cd8-a616-fb72202365a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13613
8200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.136138200
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.3240281866
Short name T2834
Test name
Test status
Simulation time 214585717 ps
CPU time 0.91 seconds
Started Jul 28 07:38:29 PM PDT 24
Finished Jul 28 07:38:30 PM PDT 24
Peak memory 207060 kb
Host smart-36a7583d-a757-4c3c-8c76-01a25f5abff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32402
81866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.3240281866
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2609140554
Short name T189
Test name
Test status
Simulation time 739854500 ps
CPU time 1.52 seconds
Started Jul 28 07:38:21 PM PDT 24
Finished Jul 28 07:38:22 PM PDT 24
Peak memory 222924 kb
Host smart-d04ab2d3-8874-4897-ba93-179886680ba0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2609140554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2609140554
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1439321041
Short name T54
Test name
Test status
Simulation time 422075886 ps
CPU time 1.48 seconds
Started Jul 28 07:38:24 PM PDT 24
Finished Jul 28 07:38:25 PM PDT 24
Peak memory 207132 kb
Host smart-8c30955a-d3e1-4447-9c02-5c51949a56dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14393
21041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1439321041
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.2106377201
Short name T165
Test name
Test status
Simulation time 189638975 ps
CPU time 0.98 seconds
Started Jul 28 07:38:11 PM PDT 24
Finished Jul 28 07:38:12 PM PDT 24
Peak memory 207292 kb
Host smart-e63a0912-715b-4547-8bf4-a18a9e6ada3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21063
77201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.2106377201
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2898959788
Short name T1225
Test name
Test status
Simulation time 162972461 ps
CPU time 0.82 seconds
Started Jul 28 07:38:23 PM PDT 24
Finished Jul 28 07:38:24 PM PDT 24
Peak memory 206992 kb
Host smart-47b0297f-7df9-4824-99ca-223b15a2aac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28989
59788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2898959788
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.800830292
Short name T2130
Test name
Test status
Simulation time 155205749 ps
CPU time 0.87 seconds
Started Jul 28 07:38:14 PM PDT 24
Finished Jul 28 07:38:15 PM PDT 24
Peak memory 207132 kb
Host smart-efc9bf95-6a4d-4cfe-bb56-75423b5ec52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80083
0292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.800830292
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1330504231
Short name T1932
Test name
Test status
Simulation time 211494104 ps
CPU time 1.07 seconds
Started Jul 28 07:38:17 PM PDT 24
Finished Jul 28 07:38:18 PM PDT 24
Peak memory 207132 kb
Host smart-4c113006-f7ad-406a-9627-81baf875643d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13305
04231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1330504231
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2528029581
Short name T2514
Test name
Test status
Simulation time 4282117545 ps
CPU time 44.68 seconds
Started Jul 28 07:38:22 PM PDT 24
Finished Jul 28 07:39:07 PM PDT 24
Peak memory 217080 kb
Host smart-8478b08b-e301-4e0c-8ea3-81840d51c06d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2528029581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2528029581
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.3618217192
Short name T1863
Test name
Test status
Simulation time 175739037 ps
CPU time 0.89 seconds
Started Jul 28 07:38:15 PM PDT 24
Finished Jul 28 07:38:16 PM PDT 24
Peak memory 207128 kb
Host smart-bb1fe7e6-9d05-4470-9283-678362c3d4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36182
17192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.3618217192
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1875043452
Short name T2093
Test name
Test status
Simulation time 220209938 ps
CPU time 0.94 seconds
Started Jul 28 07:38:27 PM PDT 24
Finished Jul 28 07:38:28 PM PDT 24
Peak memory 207148 kb
Host smart-421ba146-67ad-4924-b18f-88960c47a5c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18750
43452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1875043452
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.3989063105
Short name T2503
Test name
Test status
Simulation time 597047891 ps
CPU time 1.6 seconds
Started Jul 28 07:38:14 PM PDT 24
Finished Jul 28 07:38:16 PM PDT 24
Peak memory 207088 kb
Host smart-0615c85e-f634-46c5-86ba-4f01ae6e608f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39890
63105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.3989063105
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.1938600572
Short name T2315
Test name
Test status
Simulation time 6365849592 ps
CPU time 47.19 seconds
Started Jul 28 07:38:16 PM PDT 24
Finished Jul 28 07:39:03 PM PDT 24
Peak memory 207320 kb
Host smart-0bc3d2ab-e4b4-48a0-aee7-3aa3ad2821f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19386
00572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.1938600572
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.4176038133
Short name T1292
Test name
Test status
Simulation time 1140806819 ps
CPU time 26.57 seconds
Started Jul 28 07:38:20 PM PDT 24
Finished Jul 28 07:38:47 PM PDT 24
Peak memory 207260 kb
Host smart-2fcc68af-802f-449c-8617-a7859dcc5463
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176038133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.4176038133
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.205833570
Short name T2453
Test name
Test status
Simulation time 49249263 ps
CPU time 0.7 seconds
Started Jul 28 07:39:56 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 207136 kb
Host smart-c96d62d2-683f-4812-8a4e-c3f368e8678a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=205833570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.205833570
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3202436010
Short name T2054
Test name
Test status
Simulation time 3703778848 ps
CPU time 5.39 seconds
Started Jul 28 07:39:48 PM PDT 24
Finished Jul 28 07:39:54 PM PDT 24
Peak memory 207376 kb
Host smart-b77485e9-e9f8-453e-a228-6a899f8385df
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202436010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.3202436010
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3166425827
Short name T1488
Test name
Test status
Simulation time 13315223631 ps
CPU time 15.56 seconds
Started Jul 28 07:39:44 PM PDT 24
Finished Jul 28 07:40:00 PM PDT 24
Peak memory 207392 kb
Host smart-3104703b-112f-4ca9-83ee-99d55c2b147f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166425827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3166425827
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3568693033
Short name T527
Test name
Test status
Simulation time 23325967804 ps
CPU time 28.7 seconds
Started Jul 28 07:39:44 PM PDT 24
Finished Jul 28 07:40:13 PM PDT 24
Peak memory 207520 kb
Host smart-ee7e1e95-57b1-417d-a62c-bf0e1bcb5e09
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568693033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.3568693033
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1285923843
Short name T1340
Test name
Test status
Simulation time 154238637 ps
CPU time 0.91 seconds
Started Jul 28 07:39:48 PM PDT 24
Finished Jul 28 07:39:49 PM PDT 24
Peak memory 207180 kb
Host smart-d9dcc89d-c43b-437a-8dbb-5f0b91c5e30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12859
23843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1285923843
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.826548236
Short name T2562
Test name
Test status
Simulation time 546942561 ps
CPU time 1.72 seconds
Started Jul 28 07:39:47 PM PDT 24
Finished Jul 28 07:39:49 PM PDT 24
Peak memory 207148 kb
Host smart-171bbdfb-b5b2-47e5-9213-f6f907627e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82654
8236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.826548236
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.783418094
Short name T1237
Test name
Test status
Simulation time 945348694 ps
CPU time 2.71 seconds
Started Jul 28 07:39:47 PM PDT 24
Finished Jul 28 07:39:50 PM PDT 24
Peak memory 207256 kb
Host smart-47155427-0d7e-422e-a06b-6295029d40a0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=783418094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.783418094
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.3452508616
Short name T1894
Test name
Test status
Simulation time 11542633739 ps
CPU time 24.43 seconds
Started Jul 28 07:39:48 PM PDT 24
Finished Jul 28 07:40:12 PM PDT 24
Peak memory 207388 kb
Host smart-b2225709-ef75-430c-aa73-3faf036ac93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34525
08616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3452508616
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.3670566287
Short name T1696
Test name
Test status
Simulation time 1438303471 ps
CPU time 33.54 seconds
Started Jul 28 07:39:51 PM PDT 24
Finished Jul 28 07:40:25 PM PDT 24
Peak memory 207280 kb
Host smart-6e9c1970-c202-469b-afd9-5a3739697caf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670566287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.3670566287
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.1550133810
Short name T1221
Test name
Test status
Simulation time 474882583 ps
CPU time 1.57 seconds
Started Jul 28 07:39:49 PM PDT 24
Finished Jul 28 07:39:51 PM PDT 24
Peak memory 207076 kb
Host smart-abf52a41-822f-4a46-ba87-0628e7bebbcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15501
33810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.1550133810
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3768285549
Short name T1612
Test name
Test status
Simulation time 148960155 ps
CPU time 0.86 seconds
Started Jul 28 07:39:51 PM PDT 24
Finished Jul 28 07:39:52 PM PDT 24
Peak memory 207096 kb
Host smart-e78ee8f3-9342-4ec6-bcae-1e417e6132f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37682
85549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3768285549
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3823583113
Short name T2600
Test name
Test status
Simulation time 59720323 ps
CPU time 0.76 seconds
Started Jul 28 07:39:44 PM PDT 24
Finished Jul 28 07:39:45 PM PDT 24
Peak memory 207084 kb
Host smart-8a8aa091-a945-4388-aa0a-aefe90798b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38235
83113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3823583113
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.1374253224
Short name T1723
Test name
Test status
Simulation time 926346156 ps
CPU time 2.35 seconds
Started Jul 28 07:39:48 PM PDT 24
Finished Jul 28 07:39:50 PM PDT 24
Peak memory 207348 kb
Host smart-e75dac7a-b06e-4a0a-826a-6081764969ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13742
53224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.1374253224
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2391872970
Short name T1269
Test name
Test status
Simulation time 198395104 ps
CPU time 1.53 seconds
Started Jul 28 07:39:56 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 207180 kb
Host smart-91ea9c07-69fb-46ed-b64c-2fc02493160c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23918
72970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2391872970
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1500362231
Short name T1816
Test name
Test status
Simulation time 217249540 ps
CPU time 1.23 seconds
Started Jul 28 07:39:52 PM PDT 24
Finished Jul 28 07:39:53 PM PDT 24
Peak memory 215564 kb
Host smart-5a05b4b7-f6bc-4051-bb26-ef83dae71aa1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1500362231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1500362231
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.926613420
Short name T311
Test name
Test status
Simulation time 142954283 ps
CPU time 0.83 seconds
Started Jul 28 07:39:50 PM PDT 24
Finished Jul 28 07:39:51 PM PDT 24
Peak memory 207052 kb
Host smart-250c777b-f931-4916-9a74-1ac5875b58b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92661
3420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.926613420
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.289905000
Short name T1278
Test name
Test status
Simulation time 230246033 ps
CPU time 0.99 seconds
Started Jul 28 07:39:50 PM PDT 24
Finished Jul 28 07:39:51 PM PDT 24
Peak memory 207136 kb
Host smart-9d8319b9-a382-4c06-bd61-63a363d2088a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28990
5000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.289905000
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.1896855300
Short name T850
Test name
Test status
Simulation time 6706566365 ps
CPU time 197.62 seconds
Started Jul 28 07:39:51 PM PDT 24
Finished Jul 28 07:43:08 PM PDT 24
Peak memory 215596 kb
Host smart-bff0b3a9-1ce3-44c1-912d-769bd6f46918
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1896855300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.1896855300
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.1321245699
Short name T1857
Test name
Test status
Simulation time 13379030658 ps
CPU time 96.67 seconds
Started Jul 28 07:39:48 PM PDT 24
Finished Jul 28 07:41:25 PM PDT 24
Peak memory 207424 kb
Host smart-b04816b1-4ffe-4056-a5c8-9817bda30b77
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1321245699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.1321245699
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3876741255
Short name T1697
Test name
Test status
Simulation time 268785016 ps
CPU time 0.98 seconds
Started Jul 28 07:39:53 PM PDT 24
Finished Jul 28 07:39:54 PM PDT 24
Peak memory 207116 kb
Host smart-e2c6290d-3542-496e-b4d3-4fa69b5ddab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38767
41255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3876741255
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.926765755
Short name T1877
Test name
Test status
Simulation time 23304915910 ps
CPU time 28.32 seconds
Started Jul 28 07:39:50 PM PDT 24
Finished Jul 28 07:40:19 PM PDT 24
Peak memory 207372 kb
Host smart-2c9f73e3-360b-4e28-838b-ae1e4cc9109b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92676
5755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.926765755
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.2601686212
Short name T661
Test name
Test status
Simulation time 3294590723 ps
CPU time 4.51 seconds
Started Jul 28 07:39:49 PM PDT 24
Finished Jul 28 07:39:53 PM PDT 24
Peak memory 207432 kb
Host smart-4f61fbf6-3d61-4867-84b7-542ff8b5e4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26016
86212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.2601686212
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.1662929429
Short name T586
Test name
Test status
Simulation time 6793193909 ps
CPU time 199.65 seconds
Started Jul 28 07:39:54 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 215584 kb
Host smart-bb209f43-8466-4be3-abd6-5d2d79a1cc6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16629
29429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.1662929429
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.4002639174
Short name T2806
Test name
Test status
Simulation time 4973187629 ps
CPU time 144.65 seconds
Started Jul 28 07:39:52 PM PDT 24
Finished Jul 28 07:42:17 PM PDT 24
Peak memory 215484 kb
Host smart-e4ea2ba3-bc33-42cb-beb8-c7217bd63509
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4002639174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.4002639174
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2217636500
Short name T1162
Test name
Test status
Simulation time 250206712 ps
CPU time 1.02 seconds
Started Jul 28 07:39:54 PM PDT 24
Finished Jul 28 07:39:55 PM PDT 24
Peak memory 207036 kb
Host smart-71857fd3-29be-43b3-8723-d91baedcda79
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2217636500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2217636500
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1046043938
Short name T2721
Test name
Test status
Simulation time 220640477 ps
CPU time 0.97 seconds
Started Jul 28 07:39:48 PM PDT 24
Finished Jul 28 07:39:49 PM PDT 24
Peak memory 207140 kb
Host smart-1acf827b-63f0-4a94-b600-3864a7387f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10460
43938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1046043938
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2539436105
Short name T1012
Test name
Test status
Simulation time 5703725011 ps
CPU time 41.95 seconds
Started Jul 28 07:39:54 PM PDT 24
Finished Jul 28 07:40:36 PM PDT 24
Peak memory 217092 kb
Host smart-63823dc2-a2e2-4452-ab36-b40063ba6c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25394
36105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2539436105
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1586057694
Short name T2812
Test name
Test status
Simulation time 4105355041 ps
CPU time 33.47 seconds
Started Jul 28 07:39:51 PM PDT 24
Finished Jul 28 07:40:25 PM PDT 24
Peak memory 216928 kb
Host smart-30bbaa23-3913-4873-b37a-1cdd1c459c5e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1586057694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1586057694
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.844978974
Short name T901
Test name
Test status
Simulation time 238721796 ps
CPU time 1.02 seconds
Started Jul 28 07:39:54 PM PDT 24
Finished Jul 28 07:39:55 PM PDT 24
Peak memory 207052 kb
Host smart-7c1bc2a3-b57c-4d6f-bb46-f84f01c29d3a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=844978974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.844978974
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3099404162
Short name T1329
Test name
Test status
Simulation time 148741047 ps
CPU time 0.79 seconds
Started Jul 28 07:39:48 PM PDT 24
Finished Jul 28 07:39:49 PM PDT 24
Peak memory 207116 kb
Host smart-05bb2c53-a340-4361-8536-70f42ea52057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30994
04162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3099404162
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.3967026944
Short name T2286
Test name
Test status
Simulation time 205462965 ps
CPU time 0.89 seconds
Started Jul 28 07:39:50 PM PDT 24
Finished Jul 28 07:39:51 PM PDT 24
Peak memory 207084 kb
Host smart-56c52bcc-ef12-4c75-8557-c09a9be80e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39670
26944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.3967026944
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1589616311
Short name T2044
Test name
Test status
Simulation time 151861755 ps
CPU time 0.93 seconds
Started Jul 28 07:39:50 PM PDT 24
Finished Jul 28 07:39:51 PM PDT 24
Peak memory 207116 kb
Host smart-05c4c87b-04d5-4c47-a124-4d5967afbc52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15896
16311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1589616311
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.750832259
Short name T2495
Test name
Test status
Simulation time 167555868 ps
CPU time 0.84 seconds
Started Jul 28 07:39:53 PM PDT 24
Finished Jul 28 07:39:54 PM PDT 24
Peak memory 207116 kb
Host smart-028c4ddf-b831-4cfb-9cd8-78d65102bf5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75083
2259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.750832259
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1400234422
Short name T1486
Test name
Test status
Simulation time 155492959 ps
CPU time 0.92 seconds
Started Jul 28 07:39:49 PM PDT 24
Finished Jul 28 07:39:50 PM PDT 24
Peak memory 207176 kb
Host smart-55482d46-ef42-46f5-b55b-c7d099bd76e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14002
34422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1400234422
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.3222013678
Short name T1440
Test name
Test status
Simulation time 216620676 ps
CPU time 1 seconds
Started Jul 28 07:39:50 PM PDT 24
Finished Jul 28 07:39:51 PM PDT 24
Peak memory 207140 kb
Host smart-414fc153-93e3-4ea6-bfe4-bc2b60e14083
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3222013678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.3222013678
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.584049849
Short name T1213
Test name
Test status
Simulation time 160498407 ps
CPU time 0.87 seconds
Started Jul 28 07:39:52 PM PDT 24
Finished Jul 28 07:39:53 PM PDT 24
Peak memory 207008 kb
Host smart-db4d949d-0bb6-4432-9f44-2614abd98784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58404
9849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.584049849
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.648598630
Short name T414
Test name
Test status
Simulation time 44983514 ps
CPU time 0.75 seconds
Started Jul 28 07:39:57 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 207168 kb
Host smart-86e0f30c-0244-4cb8-9cd0-781907e3f3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64859
8630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.648598630
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2218955480
Short name T1594
Test name
Test status
Simulation time 13955947892 ps
CPU time 32.65 seconds
Started Jul 28 07:39:55 PM PDT 24
Finished Jul 28 07:40:27 PM PDT 24
Peak memory 215600 kb
Host smart-7292c0b5-fe45-466e-89bd-ee362da3789e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22189
55480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2218955480
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1058554732
Short name T1216
Test name
Test status
Simulation time 203389741 ps
CPU time 0.88 seconds
Started Jul 28 07:39:52 PM PDT 24
Finished Jul 28 07:39:53 PM PDT 24
Peak memory 207164 kb
Host smart-10b2f485-baaf-4acd-b270-818da7949741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10585
54732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1058554732
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1915440367
Short name T1107
Test name
Test status
Simulation time 260718562 ps
CPU time 1.04 seconds
Started Jul 28 07:39:55 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 207100 kb
Host smart-43fd9bf9-0d03-4132-8443-a204c32da25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19154
40367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1915440367
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3786179051
Short name T1992
Test name
Test status
Simulation time 166456742 ps
CPU time 0.86 seconds
Started Jul 28 07:39:55 PM PDT 24
Finished Jul 28 07:39:56 PM PDT 24
Peak memory 207080 kb
Host smart-550cb84a-ed77-4608-bd40-441ae853f982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37861
79051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3786179051
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.2686771766
Short name T926
Test name
Test status
Simulation time 160667156 ps
CPU time 0.92 seconds
Started Jul 28 07:39:59 PM PDT 24
Finished Jul 28 07:40:00 PM PDT 24
Peak memory 207112 kb
Host smart-8801d51e-ba07-43c7-9897-bfea099c4f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26867
71766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.2686771766
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1791558533
Short name T1964
Test name
Test status
Simulation time 145829167 ps
CPU time 0.87 seconds
Started Jul 28 07:39:55 PM PDT 24
Finished Jul 28 07:39:56 PM PDT 24
Peak memory 207136 kb
Host smart-a3f05882-fb8a-48ec-89f1-998b6647f3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17915
58533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1791558533
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.4049187728
Short name T870
Test name
Test status
Simulation time 145290956 ps
CPU time 0.86 seconds
Started Jul 28 07:39:59 PM PDT 24
Finished Jul 28 07:40:00 PM PDT 24
Peak memory 207088 kb
Host smart-86bd4db6-5420-45b6-924c-dfd406f3a5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40491
87728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.4049187728
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.815750691
Short name T2741
Test name
Test status
Simulation time 155295740 ps
CPU time 0.85 seconds
Started Jul 28 07:40:04 PM PDT 24
Finished Jul 28 07:40:05 PM PDT 24
Peak memory 207116 kb
Host smart-ced8b203-3a64-4a0b-a95e-23299eb09259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81575
0691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.815750691
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2617263925
Short name T1020
Test name
Test status
Simulation time 197362084 ps
CPU time 0.98 seconds
Started Jul 28 07:39:59 PM PDT 24
Finished Jul 28 07:40:00 PM PDT 24
Peak memory 207108 kb
Host smart-76543b3f-31a0-40fe-9c3f-e45e34204b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26172
63925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2617263925
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.1250284383
Short name T1363
Test name
Test status
Simulation time 6081118637 ps
CPU time 182.05 seconds
Started Jul 28 07:39:54 PM PDT 24
Finished Jul 28 07:42:56 PM PDT 24
Peak memory 215524 kb
Host smart-6b1f7d7c-958f-4c28-9d7a-a4089af33df6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1250284383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.1250284383
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3331209019
Short name T2744
Test name
Test status
Simulation time 182261807 ps
CPU time 0.93 seconds
Started Jul 28 07:39:54 PM PDT 24
Finished Jul 28 07:39:55 PM PDT 24
Peak memory 207168 kb
Host smart-e4b63e37-ed00-40d5-b92a-dbc82117f552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33312
09019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3331209019
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3678815621
Short name T1672
Test name
Test status
Simulation time 175476192 ps
CPU time 0.92 seconds
Started Jul 28 07:39:59 PM PDT 24
Finished Jul 28 07:40:00 PM PDT 24
Peak memory 207112 kb
Host smart-3674ed1d-1dfb-42fd-9d66-2308be576da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36788
15621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3678815621
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.629131441
Short name T2145
Test name
Test status
Simulation time 948355420 ps
CPU time 2.64 seconds
Started Jul 28 07:39:57 PM PDT 24
Finished Jul 28 07:40:00 PM PDT 24
Peak memory 207496 kb
Host smart-1a4d49e6-0de3-48be-9ded-abbfe97fd992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62913
1441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.629131441
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.298787731
Short name T2328
Test name
Test status
Simulation time 3873904991 ps
CPU time 31.9 seconds
Started Jul 28 07:39:55 PM PDT 24
Finished Jul 28 07:40:27 PM PDT 24
Peak memory 215608 kb
Host smart-398169d0-3d77-4929-8895-3362d5497b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29878
7731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.298787731
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.3792923679
Short name T703
Test name
Test status
Simulation time 1293840062 ps
CPU time 28.12 seconds
Started Jul 28 07:39:50 PM PDT 24
Finished Jul 28 07:40:18 PM PDT 24
Peak memory 207384 kb
Host smart-c9a76f2a-8ae2-4b3c-b787-6108e5b8415d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792923679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.3792923679
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.1538409648
Short name T36
Test name
Test status
Simulation time 44380382 ps
CPU time 0.7 seconds
Started Jul 28 07:39:58 PM PDT 24
Finished Jul 28 07:39:59 PM PDT 24
Peak memory 207216 kb
Host smart-b8bde1ee-071f-4d4b-a77f-78e750170838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1538409648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.1538409648
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1457673391
Short name T2869
Test name
Test status
Simulation time 4440665978 ps
CPU time 6.41 seconds
Started Jul 28 07:39:56 PM PDT 24
Finished Jul 28 07:40:02 PM PDT 24
Peak memory 207388 kb
Host smart-3736762e-a59a-42b4-965d-ad79fe6f77ce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457673391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.1457673391
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3267840455
Short name T2657
Test name
Test status
Simulation time 13411164093 ps
CPU time 15.76 seconds
Started Jul 28 07:40:02 PM PDT 24
Finished Jul 28 07:40:18 PM PDT 24
Peak memory 207392 kb
Host smart-96c42eb8-4f7d-4808-beb7-e6935d41cd48
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267840455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3267840455
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1001112114
Short name T1282
Test name
Test status
Simulation time 23374945582 ps
CPU time 29.31 seconds
Started Jul 28 07:39:54 PM PDT 24
Finished Jul 28 07:40:23 PM PDT 24
Peak memory 207388 kb
Host smart-6ccfc816-e90c-4cf5-929f-557813088262
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001112114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.1001112114
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.995652356
Short name T2331
Test name
Test status
Simulation time 183507876 ps
CPU time 0.94 seconds
Started Jul 28 07:39:56 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 207136 kb
Host smart-42a4262c-c48a-434a-bc3d-45b413aa3231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99565
2356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.995652356
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.1446908486
Short name T2824
Test name
Test status
Simulation time 171139047 ps
CPU time 0.87 seconds
Started Jul 28 07:39:55 PM PDT 24
Finished Jul 28 07:39:56 PM PDT 24
Peak memory 207048 kb
Host smart-eb9e2141-abe3-4c1c-99c8-b4edd509db15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14469
08486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1446908486
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.1134079806
Short name T515
Test name
Test status
Simulation time 241692229 ps
CPU time 1.02 seconds
Started Jul 28 07:39:56 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 207156 kb
Host smart-0b2322ba-ae42-4ca9-a80d-4e34811df954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11340
79806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.1134079806
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.251023626
Short name T2094
Test name
Test status
Simulation time 1448412846 ps
CPU time 3.79 seconds
Started Jul 28 07:40:03 PM PDT 24
Finished Jul 28 07:40:07 PM PDT 24
Peak memory 207356 kb
Host smart-817463ea-ce33-46d6-b4b1-c51861977b59
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=251023626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.251023626
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1974193816
Short name T2678
Test name
Test status
Simulation time 13728456415 ps
CPU time 31.13 seconds
Started Jul 28 07:39:58 PM PDT 24
Finished Jul 28 07:40:29 PM PDT 24
Peak memory 207248 kb
Host smart-65002ac5-6d0a-4e70-8347-580b29e8877d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19741
93816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1974193816
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.2858339782
Short name T481
Test name
Test status
Simulation time 158396747 ps
CPU time 0.85 seconds
Started Jul 28 07:39:56 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 207092 kb
Host smart-b9fa59e2-eb53-42c4-833d-5016702d1b9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858339782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.2858339782
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.4065544198
Short name T710
Test name
Test status
Simulation time 327038612 ps
CPU time 1.2 seconds
Started Jul 28 07:39:56 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 207032 kb
Host smart-68624681-95d2-4cce-bc8a-2becee4800ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40655
44198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.4065544198
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1671290485
Short name T1702
Test name
Test status
Simulation time 160738850 ps
CPU time 0.82 seconds
Started Jul 28 07:39:53 PM PDT 24
Finished Jul 28 07:39:54 PM PDT 24
Peak memory 207132 kb
Host smart-c32e5330-dddc-4622-9227-72088e2cb85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16712
90485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1671290485
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3783293537
Short name T456
Test name
Test status
Simulation time 55926230 ps
CPU time 0.71 seconds
Started Jul 28 07:39:56 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 207008 kb
Host smart-3097e11d-4f8b-489b-b22c-73db46bead40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37832
93537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3783293537
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2415994856
Short name T663
Test name
Test status
Simulation time 977056342 ps
CPU time 2.66 seconds
Started Jul 28 07:39:57 PM PDT 24
Finished Jul 28 07:39:59 PM PDT 24
Peak memory 207460 kb
Host smart-43738078-ea1a-4dd9-a359-913cf0838bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24159
94856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2415994856
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1687008348
Short name T1230
Test name
Test status
Simulation time 289936121 ps
CPU time 2.23 seconds
Started Jul 28 07:39:59 PM PDT 24
Finished Jul 28 07:40:01 PM PDT 24
Peak memory 207316 kb
Host smart-e66d0494-cca4-4550-9833-aa92b74e04b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16870
08348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1687008348
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2417974902
Short name T2395
Test name
Test status
Simulation time 225803101 ps
CPU time 1.08 seconds
Started Jul 28 07:39:57 PM PDT 24
Finished Jul 28 07:39:58 PM PDT 24
Peak memory 207304 kb
Host smart-3a3b1f19-d3dd-416e-a496-08b225b6d729
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2417974902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2417974902
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3294703990
Short name T2019
Test name
Test status
Simulation time 157613901 ps
CPU time 0.84 seconds
Started Jul 28 07:40:02 PM PDT 24
Finished Jul 28 07:40:03 PM PDT 24
Peak memory 207084 kb
Host smart-b8a5537c-e468-404c-84a3-1b9c6cfadf4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32947
03990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3294703990
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.222423529
Short name T421
Test name
Test status
Simulation time 184004407 ps
CPU time 0.92 seconds
Started Jul 28 07:40:05 PM PDT 24
Finished Jul 28 07:40:06 PM PDT 24
Peak memory 207088 kb
Host smart-1ec774cb-cb02-49c6-93f8-050b595f5965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22242
3529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.222423529
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.1841889846
Short name T1161
Test name
Test status
Simulation time 4604895156 ps
CPU time 36.45 seconds
Started Jul 28 07:39:52 PM PDT 24
Finished Jul 28 07:40:28 PM PDT 24
Peak memory 216904 kb
Host smart-a5a9b564-2db2-45a7-9147-18a84bf74953
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1841889846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1841889846
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.1910855718
Short name T879
Test name
Test status
Simulation time 9214976765 ps
CPU time 58.53 seconds
Started Jul 28 07:40:05 PM PDT 24
Finished Jul 28 07:41:04 PM PDT 24
Peak memory 207428 kb
Host smart-394c93aa-099d-415b-9ed6-18b4d1076d6d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1910855718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.1910855718
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.3751890164
Short name T1037
Test name
Test status
Simulation time 159456468 ps
CPU time 0.85 seconds
Started Jul 28 07:40:01 PM PDT 24
Finished Jul 28 07:40:02 PM PDT 24
Peak memory 207120 kb
Host smart-7c819547-9019-489c-8c63-bb73bdd94916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37518
90164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.3751890164
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.4247884271
Short name T2457
Test name
Test status
Simulation time 23328033121 ps
CPU time 27.94 seconds
Started Jul 28 07:40:05 PM PDT 24
Finished Jul 28 07:40:33 PM PDT 24
Peak memory 207304 kb
Host smart-8af735ec-b334-447b-bfaf-508ac76c5a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42478
84271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.4247884271
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.919916538
Short name T2798
Test name
Test status
Simulation time 3351985879 ps
CPU time 5.1 seconds
Started Jul 28 07:40:05 PM PDT 24
Finished Jul 28 07:40:10 PM PDT 24
Peak memory 207348 kb
Host smart-29ab4446-7f9f-489c-8a7b-2a6008b953fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91991
6538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.919916538
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.4051958963
Short name T1776
Test name
Test status
Simulation time 9581112505 ps
CPU time 77.99 seconds
Started Jul 28 07:40:05 PM PDT 24
Finished Jul 28 07:41:24 PM PDT 24
Peak memory 217320 kb
Host smart-dbeee81f-9954-4181-946c-3c4f9ad0ac00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40519
58963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.4051958963
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.2391912169
Short name T431
Test name
Test status
Simulation time 3779496548 ps
CPU time 28.6 seconds
Started Jul 28 07:40:03 PM PDT 24
Finished Jul 28 07:40:32 PM PDT 24
Peak memory 217072 kb
Host smart-49cf321f-ea6b-4a8d-9ded-cd6aa6be2683
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2391912169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.2391912169
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.4115316590
Short name T2110
Test name
Test status
Simulation time 242914886 ps
CPU time 1.01 seconds
Started Jul 28 07:40:06 PM PDT 24
Finished Jul 28 07:40:07 PM PDT 24
Peak memory 207160 kb
Host smart-284f5071-f8f5-4e01-97ca-a6e68da07615
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4115316590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.4115316590
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.4147931359
Short name T899
Test name
Test status
Simulation time 215169357 ps
CPU time 1 seconds
Started Jul 28 07:40:06 PM PDT 24
Finished Jul 28 07:40:07 PM PDT 24
Peak memory 207148 kb
Host smart-dac3f293-7554-4200-ae29-6d400fbb8d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41479
31359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.4147931359
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.860932163
Short name T2673
Test name
Test status
Simulation time 3965044352 ps
CPU time 110.69 seconds
Started Jul 28 07:40:03 PM PDT 24
Finished Jul 28 07:41:54 PM PDT 24
Peak memory 215496 kb
Host smart-0725636b-c1a1-4aa7-8e57-cd3e013feff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86093
2163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.860932163
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.949685018
Short name T2257
Test name
Test status
Simulation time 4672402095 ps
CPU time 146.74 seconds
Started Jul 28 07:40:03 PM PDT 24
Finished Jul 28 07:42:30 PM PDT 24
Peak memory 223440 kb
Host smart-822c3eef-f7fd-4145-81a8-039505350d33
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=949685018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.949685018
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.4114589187
Short name T2520
Test name
Test status
Simulation time 153322152 ps
CPU time 0.86 seconds
Started Jul 28 07:40:04 PM PDT 24
Finished Jul 28 07:40:05 PM PDT 24
Peak memory 207160 kb
Host smart-08915639-d7c2-48e5-bcf1-2e032860353d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4114589187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.4114589187
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2376436616
Short name T2746
Test name
Test status
Simulation time 217000887 ps
CPU time 0.94 seconds
Started Jul 28 07:40:03 PM PDT 24
Finished Jul 28 07:40:05 PM PDT 24
Peak memory 207168 kb
Host smart-9937607a-9f98-47ec-b9b7-29ad60231632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23764
36616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2376436616
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2652901647
Short name T127
Test name
Test status
Simulation time 195404453 ps
CPU time 0.88 seconds
Started Jul 28 07:40:03 PM PDT 24
Finished Jul 28 07:40:05 PM PDT 24
Peak memory 207112 kb
Host smart-0e6fbedf-b0a0-4e7b-ab98-e6ac27d4b5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26529
01647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2652901647
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.1400734029
Short name T1641
Test name
Test status
Simulation time 188043607 ps
CPU time 0.99 seconds
Started Jul 28 07:40:08 PM PDT 24
Finished Jul 28 07:40:09 PM PDT 24
Peak memory 207160 kb
Host smart-c65e5d0c-3a21-4823-8cad-b9516f932a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14007
34029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.1400734029
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1301172388
Short name T1824
Test name
Test status
Simulation time 150247387 ps
CPU time 0.87 seconds
Started Jul 28 07:40:04 PM PDT 24
Finished Jul 28 07:40:05 PM PDT 24
Peak memory 207100 kb
Host smart-f2bb1949-1761-4883-87b8-e544996cd2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13011
72388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1301172388
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3394807581
Short name T270
Test name
Test status
Simulation time 204924205 ps
CPU time 0.98 seconds
Started Jul 28 07:40:00 PM PDT 24
Finished Jul 28 07:40:01 PM PDT 24
Peak memory 207124 kb
Host smart-ae828008-5600-4c2a-a7e6-d3694563e9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33948
07581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3394807581
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3592319164
Short name T2532
Test name
Test status
Simulation time 170805747 ps
CPU time 0.88 seconds
Started Jul 28 07:40:04 PM PDT 24
Finished Jul 28 07:40:06 PM PDT 24
Peak memory 207080 kb
Host smart-cb029aa7-9989-4a10-b10d-199ec458aa53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35923
19164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3592319164
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.2874013603
Short name T1749
Test name
Test status
Simulation time 229924163 ps
CPU time 1.04 seconds
Started Jul 28 07:40:04 PM PDT 24
Finished Jul 28 07:40:06 PM PDT 24
Peak memory 207188 kb
Host smart-f229f980-afe5-4321-be19-375b44f9a5bc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2874013603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.2874013603
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2907489849
Short name T1988
Test name
Test status
Simulation time 144079126 ps
CPU time 0.83 seconds
Started Jul 28 07:40:00 PM PDT 24
Finished Jul 28 07:40:01 PM PDT 24
Peak memory 207092 kb
Host smart-b3c62c58-d1ee-4704-b28b-7b94e58c0cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29074
89849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2907489849
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1705505082
Short name T503
Test name
Test status
Simulation time 51207475 ps
CPU time 0.72 seconds
Started Jul 28 07:40:04 PM PDT 24
Finished Jul 28 07:40:05 PM PDT 24
Peak memory 207120 kb
Host smart-8db09959-3a3a-4e27-b2c3-09141067b469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17055
05082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1705505082
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.137918745
Short name T2450
Test name
Test status
Simulation time 9543005445 ps
CPU time 24.01 seconds
Started Jul 28 07:40:01 PM PDT 24
Finished Jul 28 07:40:25 PM PDT 24
Peak memory 215616 kb
Host smart-e65ebb69-9a72-47bf-aa59-c55b9dd7d18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13791
8745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.137918745
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1283303114
Short name T1063
Test name
Test status
Simulation time 188427555 ps
CPU time 0.93 seconds
Started Jul 28 07:40:02 PM PDT 24
Finished Jul 28 07:40:03 PM PDT 24
Peak memory 207140 kb
Host smart-80d5b813-3ecf-4064-8706-10448f826c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12833
03114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1283303114
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1679318676
Short name T1327
Test name
Test status
Simulation time 201587600 ps
CPU time 0.95 seconds
Started Jul 28 07:40:00 PM PDT 24
Finished Jul 28 07:40:02 PM PDT 24
Peak memory 207056 kb
Host smart-bd93d82e-4c3f-4102-9c28-d293cdb7d876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16793
18676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1679318676
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.4141728640
Short name T2021
Test name
Test status
Simulation time 225013630 ps
CPU time 0.93 seconds
Started Jul 28 07:40:00 PM PDT 24
Finished Jul 28 07:40:01 PM PDT 24
Peak memory 207128 kb
Host smart-4219b7a6-cd7b-495b-86af-34fad701063d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41417
28640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.4141728640
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.2381527263
Short name T2219
Test name
Test status
Simulation time 183034317 ps
CPU time 0.9 seconds
Started Jul 28 07:40:08 PM PDT 24
Finished Jul 28 07:40:09 PM PDT 24
Peak memory 207156 kb
Host smart-66a6eae4-4426-4e0d-93fe-f64e3914cc42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23815
27263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2381527263
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.605183235
Short name T1466
Test name
Test status
Simulation time 154645706 ps
CPU time 0.86 seconds
Started Jul 28 07:39:59 PM PDT 24
Finished Jul 28 07:40:00 PM PDT 24
Peak memory 207016 kb
Host smart-ffefe6c9-2117-4b6f-bbb5-478c73b0aaf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60518
3235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.605183235
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1962912496
Short name T2574
Test name
Test status
Simulation time 150642014 ps
CPU time 0.9 seconds
Started Jul 28 07:40:00 PM PDT 24
Finished Jul 28 07:40:01 PM PDT 24
Peak memory 207080 kb
Host smart-bbb39e74-6612-4460-9f82-67ca09f6003b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19629
12496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1962912496
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_smoke.114477277
Short name T874
Test name
Test status
Simulation time 252730100 ps
CPU time 1.14 seconds
Started Jul 28 07:40:01 PM PDT 24
Finished Jul 28 07:40:02 PM PDT 24
Peak memory 207172 kb
Host smart-37f2b1a0-70b3-4ec2-9737-7ddc12678078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11447
7277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.114477277
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.1008947113
Short name T704
Test name
Test status
Simulation time 4262108134 ps
CPU time 42.93 seconds
Started Jul 28 07:39:59 PM PDT 24
Finished Jul 28 07:40:42 PM PDT 24
Peak memory 215572 kb
Host smart-8835195d-8211-4acf-9900-9d4359ecff8a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1008947113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.1008947113
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.25230719
Short name T991
Test name
Test status
Simulation time 219484669 ps
CPU time 1.04 seconds
Started Jul 28 07:40:03 PM PDT 24
Finished Jul 28 07:40:04 PM PDT 24
Peak memory 207172 kb
Host smart-fee6758c-5a39-4242-8806-c9263c96f99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25230
719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.25230719
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2562459725
Short name T756
Test name
Test status
Simulation time 166018417 ps
CPU time 0.82 seconds
Started Jul 28 07:40:04 PM PDT 24
Finished Jul 28 07:40:05 PM PDT 24
Peak memory 207152 kb
Host smart-702e8bf0-2515-4b46-97e4-b3f4d956fa81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25624
59725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2562459725
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.208624690
Short name T1621
Test name
Test status
Simulation time 1394875563 ps
CPU time 3.63 seconds
Started Jul 28 07:39:58 PM PDT 24
Finished Jul 28 07:40:02 PM PDT 24
Peak memory 207324 kb
Host smart-3d1c5d93-318e-4f9d-ad3d-bcc76bd6567f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20862
4690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.208624690
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1186952292
Short name T1606
Test name
Test status
Simulation time 3859094938 ps
CPU time 36.57 seconds
Started Jul 28 07:39:57 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 215732 kb
Host smart-1b30964b-6581-4507-967e-f94cdd862305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11869
52292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1186952292
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.1875813292
Short name T2479
Test name
Test status
Simulation time 4359448837 ps
CPU time 30.83 seconds
Started Jul 28 07:39:56 PM PDT 24
Finished Jul 28 07:40:27 PM PDT 24
Peak memory 207400 kb
Host smart-f98cef2c-ccef-4901-b276-50ff7633c055
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875813292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.1875813292
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.4032996376
Short name T2164
Test name
Test status
Simulation time 41313607 ps
CPU time 0.69 seconds
Started Jul 28 07:40:22 PM PDT 24
Finished Jul 28 07:40:23 PM PDT 24
Peak memory 207088 kb
Host smart-825ec04a-428d-4980-b2c2-8bf1482ef79a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4032996376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.4032996376
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.2806777214
Short name T2184
Test name
Test status
Simulation time 4135006859 ps
CPU time 6.74 seconds
Started Jul 28 07:40:04 PM PDT 24
Finished Jul 28 07:40:11 PM PDT 24
Peak memory 207356 kb
Host smart-fefef9a2-764f-431c-97ea-14699a030ed8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806777214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_disconnect.2806777214
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.686234476
Short name T2640
Test name
Test status
Simulation time 13360474836 ps
CPU time 15.51 seconds
Started Jul 28 07:40:04 PM PDT 24
Finished Jul 28 07:40:20 PM PDT 24
Peak memory 207420 kb
Host smart-f1163cd1-3014-44ab-b82f-760d1962a644
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=686234476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.686234476
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2095183876
Short name T972
Test name
Test status
Simulation time 146877013 ps
CPU time 0.86 seconds
Started Jul 28 07:40:07 PM PDT 24
Finished Jul 28 07:40:08 PM PDT 24
Peak memory 207104 kb
Host smart-20bd33cd-0075-4d01-bcd0-2bbe79f087c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20951
83876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2095183876
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.2987243650
Short name T1306
Test name
Test status
Simulation time 186133618 ps
CPU time 0.89 seconds
Started Jul 28 07:40:06 PM PDT 24
Finished Jul 28 07:40:07 PM PDT 24
Peak memory 207128 kb
Host smart-d84dda07-386b-48bb-b245-8c15dce0435b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29872
43650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.2987243650
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.474546422
Short name T531
Test name
Test status
Simulation time 613095979 ps
CPU time 1.79 seconds
Started Jul 28 07:40:03 PM PDT 24
Finished Jul 28 07:40:05 PM PDT 24
Peak memory 207136 kb
Host smart-6c2311ff-ad5e-40f2-bebb-39cae92a9675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47454
6422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.474546422
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3551944451
Short name T2144
Test name
Test status
Simulation time 1445150617 ps
CPU time 4.11 seconds
Started Jul 28 07:40:06 PM PDT 24
Finished Jul 28 07:40:11 PM PDT 24
Peak memory 207376 kb
Host smart-3c98ff21-f83d-4fab-982c-3b0b40f8d368
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3551944451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3551944451
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.3406674366
Short name T1168
Test name
Test status
Simulation time 8048453597 ps
CPU time 16.15 seconds
Started Jul 28 07:40:17 PM PDT 24
Finished Jul 28 07:40:33 PM PDT 24
Peak memory 207480 kb
Host smart-ba291db4-a650-408b-b12d-5ed9d5225228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34066
74366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.3406674366
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.3246711805
Short name T60
Test name
Test status
Simulation time 1435765852 ps
CPU time 32.74 seconds
Started Jul 28 07:40:06 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207496 kb
Host smart-381befd2-c4f2-4dcd-8033-ab9cbc8da8f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246711805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.3246711805
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3813498263
Short name T2192
Test name
Test status
Simulation time 383585767 ps
CPU time 1.37 seconds
Started Jul 28 07:40:05 PM PDT 24
Finished Jul 28 07:40:06 PM PDT 24
Peak memory 207096 kb
Host smart-c7870a1b-ae63-4b54-8545-a6a49698978d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38134
98263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3813498263
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.951952913
Short name T1703
Test name
Test status
Simulation time 211204374 ps
CPU time 0.87 seconds
Started Jul 28 07:40:08 PM PDT 24
Finished Jul 28 07:40:09 PM PDT 24
Peak memory 207168 kb
Host smart-607fbfe0-8380-4591-8cba-52baee560398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95195
2913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.951952913
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.3297027845
Short name T1899
Test name
Test status
Simulation time 37762868 ps
CPU time 0.68 seconds
Started Jul 28 07:40:08 PM PDT 24
Finished Jul 28 07:40:09 PM PDT 24
Peak memory 207172 kb
Host smart-41b4a0b9-9676-4469-a7e1-6afad9be4802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32970
27845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3297027845
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1887311702
Short name T2499
Test name
Test status
Simulation time 934410109 ps
CPU time 2.33 seconds
Started Jul 28 07:40:07 PM PDT 24
Finished Jul 28 07:40:10 PM PDT 24
Peak memory 207268 kb
Host smart-439785df-b840-4f2d-917f-81f60d9d7b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18873
11702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1887311702
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.491414454
Short name T353
Test name
Test status
Simulation time 173097953 ps
CPU time 0.94 seconds
Started Jul 28 07:40:07 PM PDT 24
Finished Jul 28 07:40:08 PM PDT 24
Peak memory 207084 kb
Host smart-722a0695-aa60-47f0-bccb-91b3daf15c18
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=491414454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.491414454
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.306915425
Short name T2468
Test name
Test status
Simulation time 156280368 ps
CPU time 0.79 seconds
Started Jul 28 07:40:05 PM PDT 24
Finished Jul 28 07:40:06 PM PDT 24
Peak memory 207080 kb
Host smart-513c3e2e-ddbc-4965-91a5-1d330c45f69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30691
5425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.306915425
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1589231000
Short name T439
Test name
Test status
Simulation time 223258476 ps
CPU time 1.03 seconds
Started Jul 28 07:40:08 PM PDT 24
Finished Jul 28 07:40:10 PM PDT 24
Peak memory 207204 kb
Host smart-ebdf8685-1507-401f-a2d6-0d2fa71a89dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15892
31000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1589231000
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.136116581
Short name T1768
Test name
Test status
Simulation time 7004014281 ps
CPU time 70.05 seconds
Started Jul 28 07:40:10 PM PDT 24
Finished Jul 28 07:41:20 PM PDT 24
Peak memory 207384 kb
Host smart-ddf4914c-dd0d-4b3d-a842-5f531e51ce56
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=136116581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.136116581
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.1209508507
Short name T837
Test name
Test status
Simulation time 12774571931 ps
CPU time 153.07 seconds
Started Jul 28 07:40:13 PM PDT 24
Finished Jul 28 07:42:46 PM PDT 24
Peak memory 207424 kb
Host smart-bc1550a6-3b8d-4cc2-962c-6fcfddc25748
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1209508507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.1209508507
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.106092067
Short name T83
Test name
Test status
Simulation time 244681260 ps
CPU time 0.97 seconds
Started Jul 28 07:40:07 PM PDT 24
Finished Jul 28 07:40:08 PM PDT 24
Peak memory 207116 kb
Host smart-b12454b8-05e0-4019-80cc-3311e183f6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10609
2067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.106092067
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2484870531
Short name T2573
Test name
Test status
Simulation time 23278441280 ps
CPU time 29.16 seconds
Started Jul 28 07:40:13 PM PDT 24
Finished Jul 28 07:40:42 PM PDT 24
Peak memory 207384 kb
Host smart-9af814bb-3c32-49b5-808b-2b43caab684a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24848
70531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2484870531
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.1933277960
Short name T1135
Test name
Test status
Simulation time 3340809024 ps
CPU time 5.54 seconds
Started Jul 28 07:40:05 PM PDT 24
Finished Jul 28 07:40:11 PM PDT 24
Peak memory 207360 kb
Host smart-f15873a4-581f-4e15-9a05-fb0785b4be81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19332
77960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.1933277960
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2074607497
Short name T670
Test name
Test status
Simulation time 5252324189 ps
CPU time 154.38 seconds
Started Jul 28 07:40:05 PM PDT 24
Finished Jul 28 07:42:40 PM PDT 24
Peak memory 215520 kb
Host smart-6808e5ec-351e-4fb0-b8d2-01ac39891df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20746
07497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2074607497
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.3305603097
Short name T2782
Test name
Test status
Simulation time 5660851605 ps
CPU time 164.74 seconds
Started Jul 28 07:40:05 PM PDT 24
Finished Jul 28 07:42:50 PM PDT 24
Peak memory 215628 kb
Host smart-bfd78811-062a-4d81-9e80-b5d846739841
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3305603097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3305603097
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.1669997615
Short name T1210
Test name
Test status
Simulation time 303033711 ps
CPU time 1.06 seconds
Started Jul 28 07:40:08 PM PDT 24
Finished Jul 28 07:40:10 PM PDT 24
Peak memory 207052 kb
Host smart-86a87136-05b0-4ad0-a50f-0a11f8dcf1f6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1669997615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.1669997615
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1188884397
Short name T2310
Test name
Test status
Simulation time 216900221 ps
CPU time 1.02 seconds
Started Jul 28 07:40:06 PM PDT 24
Finished Jul 28 07:40:07 PM PDT 24
Peak memory 207104 kb
Host smart-5bde7c49-b7a4-4a15-a5e7-150f8cdb4986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11888
84397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1188884397
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2956826650
Short name T952
Test name
Test status
Simulation time 3440392347 ps
CPU time 102.5 seconds
Started Jul 28 07:40:10 PM PDT 24
Finished Jul 28 07:41:53 PM PDT 24
Peak memory 215528 kb
Host smart-eb3f6ab0-10ef-42c9-9868-0eb2fd802c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29568
26650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2956826650
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.2247671425
Short name T352
Test name
Test status
Simulation time 5249550285 ps
CPU time 54.34 seconds
Started Jul 28 07:40:13 PM PDT 24
Finished Jul 28 07:41:07 PM PDT 24
Peak memory 207424 kb
Host smart-76da3a60-1937-4b4a-9e99-c8d80e8300d5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2247671425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.2247671425
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.867498709
Short name T688
Test name
Test status
Simulation time 181904391 ps
CPU time 0.91 seconds
Started Jul 28 07:40:11 PM PDT 24
Finished Jul 28 07:40:12 PM PDT 24
Peak memory 207120 kb
Host smart-b701f43e-bc64-4d68-9512-335144f28b93
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=867498709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.867498709
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1091845483
Short name T1007
Test name
Test status
Simulation time 148356561 ps
CPU time 0.85 seconds
Started Jul 28 07:40:09 PM PDT 24
Finished Jul 28 07:40:10 PM PDT 24
Peak memory 207040 kb
Host smart-91d4bbf6-a7a1-432a-8ca6-79bdc9c7971d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10918
45483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1091845483
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.2955617870
Short name T544
Test name
Test status
Simulation time 223755876 ps
CPU time 1 seconds
Started Jul 28 07:40:13 PM PDT 24
Finished Jul 28 07:40:14 PM PDT 24
Peak memory 207144 kb
Host smart-ca882724-5974-472f-af9e-a21b8c3b6a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29556
17870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2955617870
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1199392136
Short name T2341
Test name
Test status
Simulation time 199089097 ps
CPU time 0.91 seconds
Started Jul 28 07:40:06 PM PDT 24
Finished Jul 28 07:40:07 PM PDT 24
Peak memory 207280 kb
Host smart-01ed94c3-71fc-4f70-9204-f8f7ca164807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11993
92136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1199392136
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.570381846
Short name T2527
Test name
Test status
Simulation time 190405794 ps
CPU time 0.87 seconds
Started Jul 28 07:40:04 PM PDT 24
Finished Jul 28 07:40:06 PM PDT 24
Peak memory 207056 kb
Host smart-4b6441eb-f82f-4a66-9bb0-b3e4ed946b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57038
1846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.570381846
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2716491301
Short name T168
Test name
Test status
Simulation time 145178282 ps
CPU time 0.83 seconds
Started Jul 28 07:40:06 PM PDT 24
Finished Jul 28 07:40:07 PM PDT 24
Peak memory 207160 kb
Host smart-bdcdaf5a-0266-469b-aca8-fdd2d22fc600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27164
91301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2716491301
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.734578997
Short name T47
Test name
Test status
Simulation time 243843380 ps
CPU time 1.04 seconds
Started Jul 28 07:40:05 PM PDT 24
Finished Jul 28 07:40:06 PM PDT 24
Peak memory 207160 kb
Host smart-60d2b320-c39f-4513-8686-b2e0223a1b07
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=734578997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.734578997
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1145931662
Short name T1305
Test name
Test status
Simulation time 206681319 ps
CPU time 0.88 seconds
Started Jul 28 07:40:11 PM PDT 24
Finished Jul 28 07:40:12 PM PDT 24
Peak memory 207068 kb
Host smart-a2a64dd1-0e5d-447c-98be-3e43ef3d4d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11459
31662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1145931662
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.4082008460
Short name T32
Test name
Test status
Simulation time 54934829 ps
CPU time 0.75 seconds
Started Jul 28 07:40:20 PM PDT 24
Finished Jul 28 07:40:21 PM PDT 24
Peak memory 207012 kb
Host smart-24498473-f001-4385-80b9-5dff2672a8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40820
08460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.4082008460
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1641542431
Short name T296
Test name
Test status
Simulation time 16738430120 ps
CPU time 42.18 seconds
Started Jul 28 07:40:15 PM PDT 24
Finished Jul 28 07:40:57 PM PDT 24
Peak memory 215552 kb
Host smart-83d0025a-e06e-4763-a6a0-6db9f8eec7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16415
42431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1641542431
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2388917748
Short name T717
Test name
Test status
Simulation time 221951578 ps
CPU time 0.95 seconds
Started Jul 28 07:40:11 PM PDT 24
Finished Jul 28 07:40:12 PM PDT 24
Peak memory 207128 kb
Host smart-f65f8da2-db90-4367-b4f1-7f3a6d422a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23889
17748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2388917748
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3982385802
Short name T699
Test name
Test status
Simulation time 227775126 ps
CPU time 1.03 seconds
Started Jul 28 07:40:17 PM PDT 24
Finished Jul 28 07:40:18 PM PDT 24
Peak memory 207088 kb
Host smart-189c6a38-b3f0-4847-9d9d-c10e3555bdd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39823
85802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3982385802
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.3797342281
Short name T866
Test name
Test status
Simulation time 163190367 ps
CPU time 0.96 seconds
Started Jul 28 07:40:16 PM PDT 24
Finished Jul 28 07:40:17 PM PDT 24
Peak memory 207044 kb
Host smart-f7aace33-da6f-40be-9103-450c1c1cd884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37973
42281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.3797342281
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.3250083350
Short name T390
Test name
Test status
Simulation time 189665292 ps
CPU time 0.92 seconds
Started Jul 28 07:40:16 PM PDT 24
Finished Jul 28 07:40:17 PM PDT 24
Peak memory 207164 kb
Host smart-a04c1a23-63af-49de-978e-ed661a4fb82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32500
83350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.3250083350
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2729201357
Short name T1693
Test name
Test status
Simulation time 138274290 ps
CPU time 0.81 seconds
Started Jul 28 07:40:10 PM PDT 24
Finished Jul 28 07:40:11 PM PDT 24
Peak memory 207240 kb
Host smart-4cb71c41-e886-4c2c-a3b3-4d1ba7cdcd8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27292
01357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2729201357
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3674037740
Short name T2438
Test name
Test status
Simulation time 202015098 ps
CPU time 0.9 seconds
Started Jul 28 07:40:10 PM PDT 24
Finished Jul 28 07:40:11 PM PDT 24
Peak memory 207088 kb
Host smart-57ca0485-dbdc-4fc3-87b6-ed027c911ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36740
37740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3674037740
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1257758483
Short name T1365
Test name
Test status
Simulation time 158863743 ps
CPU time 0.82 seconds
Started Jul 28 07:40:13 PM PDT 24
Finished Jul 28 07:40:14 PM PDT 24
Peak memory 207200 kb
Host smart-f6fe2ec9-a759-4581-abfc-0865a48cd103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12577
58483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1257758483
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3024715015
Short name T1536
Test name
Test status
Simulation time 209866625 ps
CPU time 1.08 seconds
Started Jul 28 07:40:10 PM PDT 24
Finished Jul 28 07:40:11 PM PDT 24
Peak memory 207076 kb
Host smart-e1a11774-8565-4a2d-8fbb-06281b53c23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30247
15015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3024715015
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2974053563
Short name T1186
Test name
Test status
Simulation time 4533497375 ps
CPU time 123.63 seconds
Started Jul 28 07:40:15 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 215584 kb
Host smart-5bb1f75c-519d-4dcf-a780-445feab0c871
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2974053563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2974053563
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3138773798
Short name T845
Test name
Test status
Simulation time 225350019 ps
CPU time 0.95 seconds
Started Jul 28 07:40:15 PM PDT 24
Finished Jul 28 07:40:16 PM PDT 24
Peak memory 207120 kb
Host smart-9b4de0b1-b398-4833-b1d5-b3cf1b66dcb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31387
73798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3138773798
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1431918635
Short name T815
Test name
Test status
Simulation time 190151879 ps
CPU time 0.95 seconds
Started Jul 28 07:40:15 PM PDT 24
Finished Jul 28 07:40:16 PM PDT 24
Peak memory 207116 kb
Host smart-7cc0a8b5-497c-49dd-b8a6-96f961c006ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14319
18635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1431918635
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.466249052
Short name T1322
Test name
Test status
Simulation time 387208954 ps
CPU time 1.26 seconds
Started Jul 28 07:40:07 PM PDT 24
Finished Jul 28 07:40:08 PM PDT 24
Peak memory 207292 kb
Host smart-b1b53199-fc3d-4e73-830b-985eb9f2d1b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46624
9052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.466249052
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.121665393
Short name T1872
Test name
Test status
Simulation time 3943242218 ps
CPU time 107.02 seconds
Started Jul 28 07:40:13 PM PDT 24
Finished Jul 28 07:42:01 PM PDT 24
Peak memory 215492 kb
Host smart-fdc36ae3-6b28-49f8-831a-817a98520865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12166
5393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.121665393
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.1873054793
Short name T2539
Test name
Test status
Simulation time 1206831393 ps
CPU time 27.37 seconds
Started Jul 28 07:40:08 PM PDT 24
Finished Jul 28 07:40:35 PM PDT 24
Peak memory 207284 kb
Host smart-41978627-e52c-4230-8db7-5ff68f8ec87c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873054793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.1873054793
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.2499215325
Short name T1351
Test name
Test status
Simulation time 74255524 ps
CPU time 0.74 seconds
Started Jul 28 07:40:26 PM PDT 24
Finished Jul 28 07:40:27 PM PDT 24
Peak memory 207088 kb
Host smart-d558beb3-6fdc-410d-bcec-9d161f5ed8f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2499215325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.2499215325
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.879494620
Short name T475
Test name
Test status
Simulation time 3871949714 ps
CPU time 6.2 seconds
Started Jul 28 07:40:16 PM PDT 24
Finished Jul 28 07:40:22 PM PDT 24
Peak memory 207392 kb
Host smart-2d1eec72-98ea-441e-8b66-0dd06b858430
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879494620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_ao
n_wake_disconnect.879494620
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3693237051
Short name T2381
Test name
Test status
Simulation time 13334094926 ps
CPU time 16.62 seconds
Started Jul 28 07:40:16 PM PDT 24
Finished Jul 28 07:40:33 PM PDT 24
Peak memory 207436 kb
Host smart-ed973525-e8f6-4e6c-96e4-863d0a054680
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693237051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3693237051
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.1418665634
Short name T1825
Test name
Test status
Simulation time 23367484105 ps
CPU time 27.75 seconds
Started Jul 28 07:40:13 PM PDT 24
Finished Jul 28 07:40:41 PM PDT 24
Peak memory 207288 kb
Host smart-698b3004-4683-40c2-a938-10f5e37be7c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418665634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.1418665634
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1542912881
Short name T2199
Test name
Test status
Simulation time 147671770 ps
CPU time 0.87 seconds
Started Jul 28 07:40:09 PM PDT 24
Finished Jul 28 07:40:10 PM PDT 24
Peak memory 207096 kb
Host smart-7406edd6-bec3-4da8-b172-65fed66da574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15429
12881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1542912881
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.4091938243
Short name T2817
Test name
Test status
Simulation time 168005753 ps
CPU time 0.89 seconds
Started Jul 28 07:40:15 PM PDT 24
Finished Jul 28 07:40:16 PM PDT 24
Peak memory 207084 kb
Host smart-dbb9e98d-c1ce-4b33-94a7-0a4984e36d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40919
38243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.4091938243
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3300799886
Short name T674
Test name
Test status
Simulation time 197899438 ps
CPU time 0.93 seconds
Started Jul 28 07:40:15 PM PDT 24
Finished Jul 28 07:40:16 PM PDT 24
Peak memory 207068 kb
Host smart-7f10abbc-1296-46a4-9e5b-481f69970153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33007
99886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3300799886
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.4045612073
Short name T1073
Test name
Test status
Simulation time 1299796631 ps
CPU time 3.21 seconds
Started Jul 28 07:40:18 PM PDT 24
Finished Jul 28 07:40:21 PM PDT 24
Peak memory 207308 kb
Host smart-ed3d9426-980c-4853-880b-7a1049bb60b3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4045612073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.4045612073
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.863406826
Short name T2125
Test name
Test status
Simulation time 12725500007 ps
CPU time 26.38 seconds
Started Jul 28 07:40:23 PM PDT 24
Finished Jul 28 07:40:50 PM PDT 24
Peak memory 207276 kb
Host smart-3605e553-ae4b-4a13-9077-60d226414ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86340
6826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.863406826
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.4165930770
Short name T1598
Test name
Test status
Simulation time 2578679620 ps
CPU time 23.56 seconds
Started Jul 28 07:40:20 PM PDT 24
Finished Jul 28 07:40:43 PM PDT 24
Peak memory 207420 kb
Host smart-e500b768-d3ab-44af-b0c5-11cfc7ae3dfd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165930770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.4165930770
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.3035808110
Short name T731
Test name
Test status
Simulation time 485859236 ps
CPU time 1.58 seconds
Started Jul 28 07:40:13 PM PDT 24
Finished Jul 28 07:40:14 PM PDT 24
Peak memory 207096 kb
Host smart-fa5de3e4-c624-401f-a7aa-64ddddd1fd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30358
08110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.3035808110
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.1903161918
Short name T2639
Test name
Test status
Simulation time 135877372 ps
CPU time 0.81 seconds
Started Jul 28 07:40:13 PM PDT 24
Finished Jul 28 07:40:14 PM PDT 24
Peak memory 207096 kb
Host smart-4dfeca3d-f87d-42e4-a694-a5139f50f557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19031
61918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1903161918
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.1940361026
Short name T589
Test name
Test status
Simulation time 40480130 ps
CPU time 0.7 seconds
Started Jul 28 07:40:14 PM PDT 24
Finished Jul 28 07:40:15 PM PDT 24
Peak memory 207108 kb
Host smart-f80276a7-bb81-4593-9636-1b1eb25944d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19403
61026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1940361026
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2075885658
Short name T1566
Test name
Test status
Simulation time 965476220 ps
CPU time 2.61 seconds
Started Jul 28 07:40:17 PM PDT 24
Finished Jul 28 07:40:20 PM PDT 24
Peak memory 207364 kb
Host smart-96e716ac-2b1d-4edf-8eca-e829d416a738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20758
85658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2075885658
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1318085038
Short name T2485
Test name
Test status
Simulation time 322695250 ps
CPU time 2.23 seconds
Started Jul 28 07:40:12 PM PDT 24
Finished Jul 28 07:40:15 PM PDT 24
Peak memory 207340 kb
Host smart-159ecfa6-874c-4f1e-99ba-89d7c350fe7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13180
85038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1318085038
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1322082187
Short name T2330
Test name
Test status
Simulation time 218251243 ps
CPU time 1.1 seconds
Started Jul 28 07:40:23 PM PDT 24
Finished Jul 28 07:40:25 PM PDT 24
Peak memory 215540 kb
Host smart-848d6208-4400-4695-b099-5f51659c6cab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1322082187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1322082187
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.4043074172
Short name T2006
Test name
Test status
Simulation time 171168459 ps
CPU time 0.87 seconds
Started Jul 28 07:40:18 PM PDT 24
Finished Jul 28 07:40:19 PM PDT 24
Peak memory 207088 kb
Host smart-fd03e34d-d5fb-4b8a-ba8d-b7ef3f07268b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40430
74172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.4043074172
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.3430781267
Short name T3
Test name
Test status
Simulation time 248100639 ps
CPU time 0.98 seconds
Started Jul 28 07:40:18 PM PDT 24
Finished Jul 28 07:40:19 PM PDT 24
Peak memory 207104 kb
Host smart-18c93f39-f058-440f-ba6d-535834dab650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34307
81267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.3430781267
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.2821757437
Short name T1791
Test name
Test status
Simulation time 7484731571 ps
CPU time 217.57 seconds
Started Jul 28 07:40:22 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 217024 kb
Host smart-9c738b0e-9219-4931-b154-03c5b0961720
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2821757437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.2821757437
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.2530525229
Short name T559
Test name
Test status
Simulation time 9253129744 ps
CPU time 57.84 seconds
Started Jul 28 07:40:15 PM PDT 24
Finished Jul 28 07:41:13 PM PDT 24
Peak memory 207332 kb
Host smart-2fa8b7a7-61ee-4181-9162-f29f562192e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2530525229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.2530525229
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.3469562203
Short name T2467
Test name
Test status
Simulation time 219437152 ps
CPU time 0.97 seconds
Started Jul 28 07:40:22 PM PDT 24
Finished Jul 28 07:40:23 PM PDT 24
Peak memory 207152 kb
Host smart-43dc2976-d32e-4ea4-934f-586628439023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34695
62203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.3469562203
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3960398987
Short name T495
Test name
Test status
Simulation time 23361582633 ps
CPU time 27.38 seconds
Started Jul 28 07:40:15 PM PDT 24
Finished Jul 28 07:40:42 PM PDT 24
Peak memory 207364 kb
Host smart-6f902ea6-0e55-4189-9b38-52eac9cc2ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39603
98987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3960398987
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3896796017
Short name T1852
Test name
Test status
Simulation time 3337055501 ps
CPU time 5.02 seconds
Started Jul 28 07:40:23 PM PDT 24
Finished Jul 28 07:40:28 PM PDT 24
Peak memory 207372 kb
Host smart-138d8133-0673-4438-a209-0665d417417d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38967
96017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3896796017
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.663638597
Short name T2084
Test name
Test status
Simulation time 7675223620 ps
CPU time 220.35 seconds
Started Jul 28 07:40:23 PM PDT 24
Finished Jul 28 07:44:03 PM PDT 24
Peak memory 215456 kb
Host smart-3bc94843-f086-4ad9-82fa-8ba1e944797b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66363
8597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.663638597
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1833930561
Short name T541
Test name
Test status
Simulation time 7333334126 ps
CPU time 54.33 seconds
Started Jul 28 07:40:25 PM PDT 24
Finished Jul 28 07:41:19 PM PDT 24
Peak memory 207304 kb
Host smart-576c4eb6-3091-4b6d-b464-de281c487507
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1833930561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1833930561
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.573148166
Short name T2349
Test name
Test status
Simulation time 263183635 ps
CPU time 1.07 seconds
Started Jul 28 07:40:21 PM PDT 24
Finished Jul 28 07:40:23 PM PDT 24
Peak memory 207208 kb
Host smart-5c435408-58ed-4217-94fb-973c0a60f84b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=573148166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.573148166
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.411636954
Short name T1285
Test name
Test status
Simulation time 212395858 ps
CPU time 0.99 seconds
Started Jul 28 07:40:17 PM PDT 24
Finished Jul 28 07:40:18 PM PDT 24
Peak memory 207136 kb
Host smart-646b93e9-b3d0-421b-a27a-90957c6f3964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41163
6954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.411636954
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.391639896
Short name T811
Test name
Test status
Simulation time 5663081035 ps
CPU time 44.69 seconds
Started Jul 28 07:40:19 PM PDT 24
Finished Jul 28 07:41:04 PM PDT 24
Peak memory 207456 kb
Host smart-8422b7bc-023f-41ed-93ea-78087a809810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39163
9896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.391639896
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.1774521934
Short name T1750
Test name
Test status
Simulation time 4177935219 ps
CPU time 32.87 seconds
Started Jul 28 07:40:18 PM PDT 24
Finished Jul 28 07:40:51 PM PDT 24
Peak memory 207416 kb
Host smart-c88c6b45-523d-421f-91ef-7027d8d6cfc7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1774521934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.1774521934
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.911567421
Short name T1087
Test name
Test status
Simulation time 181604135 ps
CPU time 0.92 seconds
Started Jul 28 07:40:15 PM PDT 24
Finished Jul 28 07:40:15 PM PDT 24
Peak memory 207120 kb
Host smart-16533587-fb28-457c-bfdd-2d8bb4a531b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=911567421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.911567421
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1987824526
Short name T530
Test name
Test status
Simulation time 150158719 ps
CPU time 0.87 seconds
Started Jul 28 07:40:19 PM PDT 24
Finished Jul 28 07:40:20 PM PDT 24
Peak memory 207080 kb
Host smart-3a511d2a-c92f-4ce6-b579-7bc87729f8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19878
24526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1987824526
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1804917499
Short name T1526
Test name
Test status
Simulation time 169084295 ps
CPU time 0.88 seconds
Started Jul 28 07:40:24 PM PDT 24
Finished Jul 28 07:40:25 PM PDT 24
Peak memory 207044 kb
Host smart-89e8fa30-1704-4151-9bc8-bfbb87bb1d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18049
17499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1804917499
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.318708234
Short name T739
Test name
Test status
Simulation time 180091089 ps
CPU time 0.91 seconds
Started Jul 28 07:40:17 PM PDT 24
Finished Jul 28 07:40:18 PM PDT 24
Peak memory 207128 kb
Host smart-8dfb48b0-4f3b-4957-af1c-c536edec4010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31870
8234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.318708234
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.4156616442
Short name T331
Test name
Test status
Simulation time 183023807 ps
CPU time 0.92 seconds
Started Jul 28 07:40:25 PM PDT 24
Finished Jul 28 07:40:26 PM PDT 24
Peak memory 207144 kb
Host smart-b79eba6e-e873-439f-b517-c6d0f67f9fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41566
16442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.4156616442
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2096298609
Short name T104
Test name
Test status
Simulation time 150568531 ps
CPU time 0.83 seconds
Started Jul 28 07:40:26 PM PDT 24
Finished Jul 28 07:40:27 PM PDT 24
Peak memory 207020 kb
Host smart-2158b2cd-6084-4f56-82d2-bad6975adda1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20962
98609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2096298609
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3612190004
Short name T415
Test name
Test status
Simulation time 202547296 ps
CPU time 0.99 seconds
Started Jul 28 07:40:21 PM PDT 24
Finished Jul 28 07:40:22 PM PDT 24
Peak memory 207120 kb
Host smart-6a4232af-7b45-46c0-9eca-ddc5788981c7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3612190004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3612190004
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3664586339
Short name T2293
Test name
Test status
Simulation time 146986891 ps
CPU time 0.81 seconds
Started Jul 28 07:40:26 PM PDT 24
Finished Jul 28 07:40:27 PM PDT 24
Peak memory 207020 kb
Host smart-b93c5556-67c5-4565-9b00-d1768b565ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36645
86339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3664586339
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.884086888
Short name T707
Test name
Test status
Simulation time 41813888 ps
CPU time 0.66 seconds
Started Jul 28 07:40:18 PM PDT 24
Finished Jul 28 07:40:19 PM PDT 24
Peak memory 207084 kb
Host smart-32408301-f4de-439e-be6f-c96ad6f79c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88408
6888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.884086888
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2724498719
Short name T1263
Test name
Test status
Simulation time 18493286228 ps
CPU time 46.58 seconds
Started Jul 28 07:40:18 PM PDT 24
Finished Jul 28 07:41:05 PM PDT 24
Peak memory 215592 kb
Host smart-547d0432-e5df-40a9-a9cb-6d0ada6bff38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27244
98719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2724498719
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2448862239
Short name T825
Test name
Test status
Simulation time 176879309 ps
CPU time 0.95 seconds
Started Jul 28 07:40:18 PM PDT 24
Finished Jul 28 07:40:19 PM PDT 24
Peak memory 207168 kb
Host smart-97d9fd2b-cfb1-4d27-9db3-cb59834a0bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24488
62239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2448862239
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.4011626890
Short name T376
Test name
Test status
Simulation time 205019757 ps
CPU time 0.94 seconds
Started Jul 28 07:40:19 PM PDT 24
Finished Jul 28 07:40:20 PM PDT 24
Peak memory 207172 kb
Host smart-2db7571e-d4d6-4a2e-8317-9fd115fa9277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40116
26890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.4011626890
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.2415355884
Short name T2069
Test name
Test status
Simulation time 219482347 ps
CPU time 0.95 seconds
Started Jul 28 07:40:17 PM PDT 24
Finished Jul 28 07:40:18 PM PDT 24
Peak memory 207296 kb
Host smart-8fb50fd4-0f45-416b-872c-321ccbe2cc77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24153
55884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.2415355884
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.1660991183
Short name T625
Test name
Test status
Simulation time 175488223 ps
CPU time 0.86 seconds
Started Jul 28 07:40:22 PM PDT 24
Finished Jul 28 07:40:24 PM PDT 24
Peak memory 207200 kb
Host smart-cc425b78-6135-4566-96e7-55b9265f0756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16609
91183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.1660991183
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.216758832
Short name T863
Test name
Test status
Simulation time 144627900 ps
CPU time 0.85 seconds
Started Jul 28 07:40:17 PM PDT 24
Finished Jul 28 07:40:18 PM PDT 24
Peak memory 207020 kb
Host smart-c3ff3c0b-91d9-494c-89e5-9ae5ede510f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21675
8832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.216758832
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.2365612937
Short name T2446
Test name
Test status
Simulation time 243631931 ps
CPU time 0.98 seconds
Started Jul 28 07:40:24 PM PDT 24
Finished Jul 28 07:40:25 PM PDT 24
Peak memory 207072 kb
Host smart-03de03e1-4b0f-415a-b810-f243c0920aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23656
12937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.2365612937
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2724375943
Short name T2133
Test name
Test status
Simulation time 205706099 ps
CPU time 0.91 seconds
Started Jul 28 07:40:17 PM PDT 24
Finished Jul 28 07:40:18 PM PDT 24
Peak memory 207124 kb
Host smart-ee3983cd-2fe0-4994-9790-f58389bd031f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27243
75943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2724375943
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.197750300
Short name T2728
Test name
Test status
Simulation time 237452091 ps
CPU time 1.02 seconds
Started Jul 28 07:40:24 PM PDT 24
Finished Jul 28 07:40:25 PM PDT 24
Peak memory 207132 kb
Host smart-0ceb6b3e-0b38-4410-a764-f15db01b8b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19775
0300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.197750300
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.366335560
Short name T467
Test name
Test status
Simulation time 5202524582 ps
CPU time 152 seconds
Started Jul 28 07:40:18 PM PDT 24
Finished Jul 28 07:42:50 PM PDT 24
Peak memory 215552 kb
Host smart-8cbdda9e-54ce-425e-a49f-38110f14bfc1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=366335560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.366335560
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1923074081
Short name T2126
Test name
Test status
Simulation time 179443672 ps
CPU time 0.87 seconds
Started Jul 28 07:40:19 PM PDT 24
Finished Jul 28 07:40:20 PM PDT 24
Peak memory 207124 kb
Host smart-0a6b7137-139b-414e-83f7-259c41da3674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19230
74081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1923074081
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3074184732
Short name T2760
Test name
Test status
Simulation time 184964428 ps
CPU time 0.91 seconds
Started Jul 28 07:40:29 PM PDT 24
Finished Jul 28 07:40:30 PM PDT 24
Peak memory 207080 kb
Host smart-71e88607-ad62-4960-9c5c-b3460315996f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30741
84732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3074184732
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1724934808
Short name T1217
Test name
Test status
Simulation time 1159930530 ps
CPU time 2.72 seconds
Started Jul 28 07:40:25 PM PDT 24
Finished Jul 28 07:40:28 PM PDT 24
Peak memory 207228 kb
Host smart-ce6330c6-3b6b-43da-92d1-98d7b28a83d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17249
34808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1724934808
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.418735467
Short name T1911
Test name
Test status
Simulation time 4253605145 ps
CPU time 34.72 seconds
Started Jul 28 07:40:23 PM PDT 24
Finished Jul 28 07:40:58 PM PDT 24
Peak memory 217044 kb
Host smart-48489264-7f46-4cb0-b432-818e53e4ef6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41873
5467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.418735467
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.2459139739
Short name T2176
Test name
Test status
Simulation time 905068785 ps
CPU time 18.93 seconds
Started Jul 28 07:40:11 PM PDT 24
Finished Jul 28 07:40:30 PM PDT 24
Peak memory 207356 kb
Host smart-dba602ac-2b03-4985-afe8-f445cbe1f14e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459139739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.2459139739
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.44290445
Short name T1724
Test name
Test status
Simulation time 75266630 ps
CPU time 0.72 seconds
Started Jul 28 07:40:33 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207092 kb
Host smart-19626eea-567d-48c6-ac3c-46c4c4b3ccf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=44290445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.44290445
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.335719791
Short name T2129
Test name
Test status
Simulation time 3415091842 ps
CPU time 4.97 seconds
Started Jul 28 07:40:25 PM PDT 24
Finished Jul 28 07:40:30 PM PDT 24
Peak memory 207416 kb
Host smart-810cb77b-09ee-482e-a88e-ce98569f724a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335719791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_ao
n_wake_disconnect.335719791
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3227187345
Short name T882
Test name
Test status
Simulation time 13376025334 ps
CPU time 16.16 seconds
Started Jul 28 07:40:23 PM PDT 24
Finished Jul 28 07:40:40 PM PDT 24
Peak memory 207276 kb
Host smart-2948e446-b5c3-4c0a-a882-fcb91851415c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227187345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3227187345
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2215175590
Short name T2519
Test name
Test status
Simulation time 23358115255 ps
CPU time 29.47 seconds
Started Jul 28 07:40:28 PM PDT 24
Finished Jul 28 07:40:58 PM PDT 24
Peak memory 207372 kb
Host smart-c8b243d0-679d-4840-9156-033323a4f770
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215175590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.2215175590
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.376663292
Short name T355
Test name
Test status
Simulation time 192743408 ps
CPU time 0.94 seconds
Started Jul 28 07:40:22 PM PDT 24
Finished Jul 28 07:40:23 PM PDT 24
Peak memory 207136 kb
Host smart-e34cfb3a-e89a-412c-bc75-884732ec25f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37666
3292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.376663292
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.465682670
Short name T1035
Test name
Test status
Simulation time 158055165 ps
CPU time 0.84 seconds
Started Jul 28 07:40:30 PM PDT 24
Finished Jul 28 07:40:31 PM PDT 24
Peak memory 207012 kb
Host smart-2950cf6d-bda0-48db-a040-279b424e4b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46568
2670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.465682670
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.806348829
Short name T1397
Test name
Test status
Simulation time 523462397 ps
CPU time 1.72 seconds
Started Jul 28 07:40:22 PM PDT 24
Finished Jul 28 07:40:24 PM PDT 24
Peak memory 207152 kb
Host smart-f6c55832-663f-46b6-ae26-e6deeb9ae374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80634
8829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.806348829
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2430688051
Short name T1991
Test name
Test status
Simulation time 693743940 ps
CPU time 1.98 seconds
Started Jul 28 07:40:30 PM PDT 24
Finished Jul 28 07:40:32 PM PDT 24
Peak memory 207044 kb
Host smart-076d70f2-1ae8-4f5e-9d1b-5c59eaddf528
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2430688051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2430688051
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.1211039775
Short name T174
Test name
Test status
Simulation time 22663074153 ps
CPU time 50.68 seconds
Started Jul 28 07:40:26 PM PDT 24
Finished Jul 28 07:41:16 PM PDT 24
Peak memory 207436 kb
Host smart-c36dc5f7-9055-4979-bacd-18aa2bbab9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12110
39775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.1211039775
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.1729206900
Short name T538
Test name
Test status
Simulation time 5671231811 ps
CPU time 37.28 seconds
Started Jul 28 07:40:21 PM PDT 24
Finished Jul 28 07:40:59 PM PDT 24
Peak memory 207376 kb
Host smart-3fd51606-c837-4174-a66b-4e52324cce99
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729206900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.1729206900
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3859419503
Short name T711
Test name
Test status
Simulation time 416671476 ps
CPU time 1.46 seconds
Started Jul 28 07:40:21 PM PDT 24
Finished Jul 28 07:40:22 PM PDT 24
Peak memory 207128 kb
Host smart-9981c8d5-f53b-4f2a-a88a-c00f5485e710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38594
19503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3859419503
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.598763444
Short name T2780
Test name
Test status
Simulation time 132638084 ps
CPU time 0.81 seconds
Started Jul 28 07:40:30 PM PDT 24
Finished Jul 28 07:40:31 PM PDT 24
Peak memory 207008 kb
Host smart-e772b4fc-af11-4d2b-8219-06045400016b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59876
3444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.598763444
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.2073583404
Short name T1763
Test name
Test status
Simulation time 44104031 ps
CPU time 0.72 seconds
Started Jul 28 07:40:25 PM PDT 24
Finished Jul 28 07:40:26 PM PDT 24
Peak memory 207128 kb
Host smart-5812473e-07bb-4522-b090-83d6babba6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20735
83404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2073583404
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.2243918748
Short name T2473
Test name
Test status
Simulation time 1027647241 ps
CPU time 2.45 seconds
Started Jul 28 07:40:26 PM PDT 24
Finished Jul 28 07:40:29 PM PDT 24
Peak memory 207388 kb
Host smart-bb01c2ce-300f-45eb-982c-e723306f1a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22439
18748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.2243918748
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3503497010
Short name T2240
Test name
Test status
Simulation time 270317165 ps
CPU time 2.06 seconds
Started Jul 28 07:40:31 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207276 kb
Host smart-1376cf8c-1700-4753-95be-37e27202f1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35034
97010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3503497010
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.910588284
Short name T2742
Test name
Test status
Simulation time 207158774 ps
CPU time 1.08 seconds
Started Jul 28 07:40:29 PM PDT 24
Finished Jul 28 07:40:30 PM PDT 24
Peak memory 215556 kb
Host smart-b661d8e6-7f8f-40f5-8a08-d76fbb62cf2a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=910588284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.910588284
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.259340467
Short name T2500
Test name
Test status
Simulation time 158250897 ps
CPU time 0.9 seconds
Started Jul 28 07:40:27 PM PDT 24
Finished Jul 28 07:40:28 PM PDT 24
Peak memory 207268 kb
Host smart-11e5f1b5-f383-4941-8e4e-9084f83819ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25934
0467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.259340467
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2365217438
Short name T408
Test name
Test status
Simulation time 207156477 ps
CPU time 0.98 seconds
Started Jul 28 07:40:27 PM PDT 24
Finished Jul 28 07:40:28 PM PDT 24
Peak memory 207092 kb
Host smart-9aa04f9a-948d-465f-a748-f13ddcc45b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23652
17438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2365217438
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.3243679293
Short name T2484
Test name
Test status
Simulation time 9264905769 ps
CPU time 90.82 seconds
Started Jul 28 07:40:31 PM PDT 24
Finished Jul 28 07:42:02 PM PDT 24
Peak memory 216712 kb
Host smart-3615c957-0a31-49e2-b9e7-f2ca1ef44538
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3243679293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.3243679293
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.4231606519
Short name T2735
Test name
Test status
Simulation time 12237879801 ps
CPU time 143.11 seconds
Started Jul 28 07:40:28 PM PDT 24
Finished Jul 28 07:42:51 PM PDT 24
Peak memory 207332 kb
Host smart-86023ae8-dee7-42d8-bd64-5791feb2aa7f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4231606519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.4231606519
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.2520126106
Short name T1666
Test name
Test status
Simulation time 202980873 ps
CPU time 0.91 seconds
Started Jul 28 07:40:29 PM PDT 24
Finished Jul 28 07:40:30 PM PDT 24
Peak memory 207084 kb
Host smart-1fb45881-2e3c-4d1b-991c-b7a9ea1f1d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
26106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.2520126106
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.4245331520
Short name T2615
Test name
Test status
Simulation time 23336521558 ps
CPU time 28.3 seconds
Started Jul 28 07:40:30 PM PDT 24
Finished Jul 28 07:40:58 PM PDT 24
Peak memory 207320 kb
Host smart-b8b18eee-7b46-4840-95e0-f13ca4082828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42453
31520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.4245331520
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.4202374308
Short name T1625
Test name
Test status
Simulation time 3274234798 ps
CPU time 5.4 seconds
Started Jul 28 07:40:28 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207372 kb
Host smart-58ae8ffa-81bc-4750-b799-6871ea99d17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42023
74308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.4202374308
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.3930421229
Short name T2541
Test name
Test status
Simulation time 5619642466 ps
CPU time 161.56 seconds
Started Jul 28 07:40:32 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 215616 kb
Host smart-a17d781e-7d80-45e2-81a6-5e876fa71c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39304
21229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.3930421229
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.3927375053
Short name T430
Test name
Test status
Simulation time 3939033486 ps
CPU time 39.33 seconds
Started Jul 28 07:40:29 PM PDT 24
Finished Jul 28 07:41:08 PM PDT 24
Peak memory 207464 kb
Host smart-32f013e9-a3ce-4c47-b111-16f96fcc8762
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3927375053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3927375053
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.490007739
Short name T1760
Test name
Test status
Simulation time 270460398 ps
CPU time 1.03 seconds
Started Jul 28 07:40:30 PM PDT 24
Finished Jul 28 07:40:32 PM PDT 24
Peak memory 207164 kb
Host smart-6960ce92-d443-409c-ba00-bfdeed451150
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=490007739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.490007739
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.4164494475
Short name T2567
Test name
Test status
Simulation time 187393600 ps
CPU time 1.01 seconds
Started Jul 28 07:40:30 PM PDT 24
Finished Jul 28 07:40:31 PM PDT 24
Peak memory 207140 kb
Host smart-b678a7c8-f576-4a60-a4e2-dadacd0a27f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41644
94475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.4164494475
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.366888754
Short name T2699
Test name
Test status
Simulation time 6326361071 ps
CPU time 49.66 seconds
Started Jul 28 07:40:29 PM PDT 24
Finished Jul 28 07:41:18 PM PDT 24
Peak memory 217036 kb
Host smart-763f8214-5140-4d2b-9002-73c8ca897196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36688
8754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.366888754
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2832164417
Short name T1154
Test name
Test status
Simulation time 3970163952 ps
CPU time 112.48 seconds
Started Jul 28 07:40:32 PM PDT 24
Finished Jul 28 07:42:25 PM PDT 24
Peak memory 215464 kb
Host smart-4fd7266a-7887-41aa-86ba-65c5067dcc59
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2832164417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2832164417
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.277838796
Short name T2647
Test name
Test status
Simulation time 177781655 ps
CPU time 0.87 seconds
Started Jul 28 07:40:30 PM PDT 24
Finished Jul 28 07:40:31 PM PDT 24
Peak memory 207140 kb
Host smart-ee8a31ef-b588-4cb9-a88d-a32b52c7c29c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=277838796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.277838796
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3683353858
Short name T1008
Test name
Test status
Simulation time 153962203 ps
CPU time 0.84 seconds
Started Jul 28 07:40:28 PM PDT 24
Finished Jul 28 07:40:29 PM PDT 24
Peak memory 207204 kb
Host smart-45795810-6c2a-4b52-a791-ba56f49cf45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36833
53858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3683353858
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.577302620
Short name T139
Test name
Test status
Simulation time 198922328 ps
CPU time 0.94 seconds
Started Jul 28 07:40:33 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207168 kb
Host smart-82b9e9c2-4fdc-4617-96d9-77b7a8835d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57730
2620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.577302620
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2511463117
Short name T1341
Test name
Test status
Simulation time 171032357 ps
CPU time 0.91 seconds
Started Jul 28 07:40:27 PM PDT 24
Finished Jul 28 07:40:28 PM PDT 24
Peak memory 207044 kb
Host smart-df7a566d-3206-46cc-9dd7-281a339e9b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25114
63117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2511463117
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.2806212605
Short name T2835
Test name
Test status
Simulation time 189474567 ps
CPU time 0.94 seconds
Started Jul 28 07:40:30 PM PDT 24
Finished Jul 28 07:40:31 PM PDT 24
Peak memory 207176 kb
Host smart-01c4e216-d61a-48fd-97c3-ef2ab48c8fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28062
12605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.2806212605
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3304617434
Short name T576
Test name
Test status
Simulation time 229124111 ps
CPU time 0.95 seconds
Started Jul 28 07:40:38 PM PDT 24
Finished Jul 28 07:40:40 PM PDT 24
Peak memory 207048 kb
Host smart-2663bc72-604a-4221-8c4d-141cba947de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33046
17434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3304617434
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3750655724
Short name T163
Test name
Test status
Simulation time 152873535 ps
CPU time 0.84 seconds
Started Jul 28 07:40:33 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207112 kb
Host smart-89439302-e14c-4a8d-8130-97201a616840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37506
55724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3750655724
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.831602712
Short name T1575
Test name
Test status
Simulation time 237680417 ps
CPU time 1.04 seconds
Started Jul 28 07:40:29 PM PDT 24
Finished Jul 28 07:40:30 PM PDT 24
Peak memory 207136 kb
Host smart-10ab8ca2-b294-4aa8-918d-42c9ccb3c47c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=831602712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.831602712
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2845076719
Short name T2663
Test name
Test status
Simulation time 143166560 ps
CPU time 0.81 seconds
Started Jul 28 07:40:29 PM PDT 24
Finished Jul 28 07:40:29 PM PDT 24
Peak memory 207076 kb
Host smart-15df3140-9578-4c0c-a54c-796b4f52091e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28450
76719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2845076719
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.4271537291
Short name T2375
Test name
Test status
Simulation time 19771795468 ps
CPU time 46.31 seconds
Started Jul 28 07:40:31 PM PDT 24
Finished Jul 28 07:41:17 PM PDT 24
Peak memory 215664 kb
Host smart-c8b85370-76bf-4fca-8f00-918369b75f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42715
37291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.4271537291
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1121326598
Short name T2273
Test name
Test status
Simulation time 161124981 ps
CPU time 0.9 seconds
Started Jul 28 07:40:33 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207116 kb
Host smart-1fc4ef24-bcff-4047-806c-f30d6dacbfd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11213
26598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1121326598
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2830759291
Short name T1483
Test name
Test status
Simulation time 254124412 ps
CPU time 1.06 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:38 PM PDT 24
Peak memory 207056 kb
Host smart-ff8857b9-5bb7-4939-8d04-5ac4868331fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28307
59291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2830759291
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3974042717
Short name T507
Test name
Test status
Simulation time 245681862 ps
CPU time 1.07 seconds
Started Jul 28 07:40:32 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207068 kb
Host smart-b6727c6a-8258-4eb8-8142-45cbad228fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39740
42717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3974042717
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.319965196
Short name T2306
Test name
Test status
Simulation time 147753277 ps
CPU time 0.84 seconds
Started Jul 28 07:40:33 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207080 kb
Host smart-1efcb04a-706d-403d-a298-a3b4b7127513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31996
5196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.319965196
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.1928711590
Short name T2816
Test name
Test status
Simulation time 158362093 ps
CPU time 0.87 seconds
Started Jul 28 07:40:33 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207140 kb
Host smart-4d6babc3-6def-4e83-ab22-db52a55e06f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19287
11590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.1928711590
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2626499423
Short name T1038
Test name
Test status
Simulation time 146065574 ps
CPU time 0.87 seconds
Started Jul 28 07:40:38 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207048 kb
Host smart-3da25825-d2f4-43ac-8c08-0d37dce15fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26264
99423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2626499423
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.405150709
Short name T45
Test name
Test status
Simulation time 144086734 ps
CPU time 0.84 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:38 PM PDT 24
Peak memory 207084 kb
Host smart-3d445b96-1e45-422d-98e0-3e36539a0239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40515
0709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.405150709
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2148319962
Short name T1709
Test name
Test status
Simulation time 201397569 ps
CPU time 0.96 seconds
Started Jul 28 07:40:33 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207112 kb
Host smart-7126e58d-3904-49f5-9340-4197cec013b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21483
19962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2148319962
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2983452871
Short name T724
Test name
Test status
Simulation time 5463444181 ps
CPU time 158.54 seconds
Started Jul 28 07:40:35 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 215448 kb
Host smart-11c3f6a3-0a5a-4290-98bc-1c482f356cd8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2983452871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2983452871
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3194068079
Short name T1871
Test name
Test status
Simulation time 195400858 ps
CPU time 0.89 seconds
Started Jul 28 07:40:31 PM PDT 24
Finished Jul 28 07:40:32 PM PDT 24
Peak memory 207204 kb
Host smart-62bf54ec-1493-4463-b90e-a680f7626465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31940
68079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3194068079
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3946637377
Short name T1104
Test name
Test status
Simulation time 161142313 ps
CPU time 0.88 seconds
Started Jul 28 07:40:34 PM PDT 24
Finished Jul 28 07:40:35 PM PDT 24
Peak memory 207044 kb
Host smart-d9c77c46-4498-4059-ba37-62c7eb9e36a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39466
37377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3946637377
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.1802209986
Short name T1137
Test name
Test status
Simulation time 1186716586 ps
CPU time 3.11 seconds
Started Jul 28 07:40:36 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207332 kb
Host smart-c6aa7fe4-fdb2-46c8-96bb-5e47f140c6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18022
09986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.1802209986
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3177040097
Short name T764
Test name
Test status
Simulation time 6498016999 ps
CPU time 66.8 seconds
Started Jul 28 07:40:38 PM PDT 24
Finished Jul 28 07:41:45 PM PDT 24
Peak memory 207368 kb
Host smart-6ceace1e-0477-43c8-8fc4-3671e2bff573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31770
40097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3177040097
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.1850546525
Short name T1585
Test name
Test status
Simulation time 4321647501 ps
CPU time 36.8 seconds
Started Jul 28 07:40:25 PM PDT 24
Finished Jul 28 07:41:02 PM PDT 24
Peak memory 207404 kb
Host smart-2de781dc-434f-409e-94fc-fda6652ebac7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850546525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.1850546525
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2438766211
Short name T892
Test name
Test status
Simulation time 32092117 ps
CPU time 0.66 seconds
Started Jul 28 07:40:48 PM PDT 24
Finished Jul 28 07:40:49 PM PDT 24
Peak memory 207116 kb
Host smart-1ec3f5c5-9876-4aa9-813c-5329ebe59e1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2438766211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2438766211
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.3585030122
Short name T1787
Test name
Test status
Simulation time 4020497891 ps
CPU time 5.64 seconds
Started Jul 28 07:40:33 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207352 kb
Host smart-d6ac5527-4ef3-4a1c-9877-6086c40ff825
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585030122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.3585030122
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.408885447
Short name T16
Test name
Test status
Simulation time 13339883187 ps
CPU time 14.56 seconds
Started Jul 28 07:40:31 PM PDT 24
Finished Jul 28 07:40:46 PM PDT 24
Peak memory 207432 kb
Host smart-083e3143-7345-477e-8693-ddc9fc3cdf87
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=408885447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.408885447
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.4088035663
Short name T1856
Test name
Test status
Simulation time 23339720865 ps
CPU time 29.86 seconds
Started Jul 28 07:40:30 PM PDT 24
Finished Jul 28 07:41:00 PM PDT 24
Peak memory 207404 kb
Host smart-67f51ecd-6eca-4cdb-870e-57181a224a6a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088035663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.4088035663
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1509692145
Short name T2218
Test name
Test status
Simulation time 192297063 ps
CPU time 0.93 seconds
Started Jul 28 07:40:33 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207124 kb
Host smart-5dd5ba89-74aa-4f9f-9960-41c3da7629cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096
92145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1509692145
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.1319228607
Short name T80
Test name
Test status
Simulation time 185037502 ps
CPU time 0.93 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207144 kb
Host smart-5809bcc0-7186-49af-9e03-b0e69f2c2c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13192
28607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.1319228607
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.930623681
Short name T1378
Test name
Test status
Simulation time 227715783 ps
CPU time 1.01 seconds
Started Jul 28 07:40:33 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207132 kb
Host smart-105ef5ed-8b4e-4ab4-98c9-7f866a419536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93062
3681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.930623681
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3715692293
Short name T1937
Test name
Test status
Simulation time 385423550 ps
CPU time 1.28 seconds
Started Jul 28 07:40:32 PM PDT 24
Finished Jul 28 07:40:33 PM PDT 24
Peak memory 207128 kb
Host smart-100a32c1-1e7e-449d-add6-217dfff92851
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3715692293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3715692293
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3070853736
Short name T2751
Test name
Test status
Simulation time 14389569444 ps
CPU time 34.38 seconds
Started Jul 28 07:40:36 PM PDT 24
Finished Jul 28 07:41:11 PM PDT 24
Peak memory 207396 kb
Host smart-42a74f80-da5e-4e27-bda3-749fdd26e547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30708
53736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3070853736
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.2474798307
Short name T2136
Test name
Test status
Simulation time 200450241 ps
CPU time 0.83 seconds
Started Jul 28 07:40:33 PM PDT 24
Finished Jul 28 07:40:34 PM PDT 24
Peak memory 207128 kb
Host smart-d6c6d391-fd74-4fdb-ad27-3e9dc4e89847
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474798307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.2474798307
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3730880439
Short name T1117
Test name
Test status
Simulation time 378649636 ps
CPU time 1.35 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:38 PM PDT 24
Peak memory 207248 kb
Host smart-9ec888f5-c34f-4dad-8968-d960529179a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37308
80439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3730880439
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_enable.4130148990
Short name T2355
Test name
Test status
Simulation time 41427556 ps
CPU time 0.73 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:38 PM PDT 24
Peak memory 207136 kb
Host smart-1e32bd36-54d4-4a9b-ab82-babebc25907a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41301
48990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.4130148990
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.2149893852
Short name T2329
Test name
Test status
Simulation time 947612329 ps
CPU time 2.49 seconds
Started Jul 28 07:40:34 PM PDT 24
Finished Jul 28 07:40:37 PM PDT 24
Peak memory 207364 kb
Host smart-8bc47961-0004-4ab5-a752-2a67842efba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21498
93852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2149893852
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2840715227
Short name T1051
Test name
Test status
Simulation time 265906314 ps
CPU time 1.9 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207220 kb
Host smart-3ba521d4-1433-41f9-96f0-423156489af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28407
15227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2840715227
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3505585721
Short name T720
Test name
Test status
Simulation time 198015096 ps
CPU time 0.98 seconds
Started Jul 28 07:40:34 PM PDT 24
Finished Jul 28 07:40:35 PM PDT 24
Peak memory 215440 kb
Host smart-357fde19-5269-4e0b-a2cf-b0c37a5068da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3505585721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3505585721
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1777418339
Short name T1497
Test name
Test status
Simulation time 144365654 ps
CPU time 0.91 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:38 PM PDT 24
Peak memory 207044 kb
Host smart-eb702720-c191-43e1-ab47-47a91b60b3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17774
18339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1777418339
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1417304497
Short name T2546
Test name
Test status
Simulation time 223210582 ps
CPU time 1.01 seconds
Started Jul 28 07:40:34 PM PDT 24
Finished Jul 28 07:40:35 PM PDT 24
Peak memory 207160 kb
Host smart-2f25a990-9150-4c71-9c5b-e88d7868bcd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14173
04497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1417304497
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.35769230
Short name T2444
Test name
Test status
Simulation time 6066100866 ps
CPU time 169.31 seconds
Started Jul 28 07:40:32 PM PDT 24
Finished Jul 28 07:43:21 PM PDT 24
Peak memory 215604 kb
Host smart-f2760a4c-06c0-412a-860f-740fc0a6bbb6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=35769230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.35769230
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.3847033297
Short name T2779
Test name
Test status
Simulation time 4702689624 ps
CPU time 36.77 seconds
Started Jul 28 07:40:35 PM PDT 24
Finished Jul 28 07:41:12 PM PDT 24
Peak memory 207516 kb
Host smart-8c4f4491-4586-4f6b-8423-425d73c640d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3847033297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.3847033297
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1741924085
Short name T1677
Test name
Test status
Simulation time 199162450 ps
CPU time 0.93 seconds
Started Jul 28 07:40:38 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207104 kb
Host smart-86e65fe4-e2e8-4313-bf10-32cabb92c4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17419
24085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1741924085
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3751411851
Short name T2708
Test name
Test status
Simulation time 23349458646 ps
CPU time 28.89 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:41:06 PM PDT 24
Peak memory 207520 kb
Host smart-5ba3892d-16c5-4d5e-a762-59668af74212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37514
11851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3751411851
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.451428894
Short name T2135
Test name
Test status
Simulation time 3311511154 ps
CPU time 5.17 seconds
Started Jul 28 07:40:36 PM PDT 24
Finished Jul 28 07:40:41 PM PDT 24
Peak memory 207448 kb
Host smart-8427aba7-512a-4e1e-a7aa-3a8f0342065f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45142
8894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.451428894
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2907128477
Short name T2277
Test name
Test status
Simulation time 7568415098 ps
CPU time 54.56 seconds
Started Jul 28 07:40:39 PM PDT 24
Finished Jul 28 07:41:34 PM PDT 24
Peak memory 217276 kb
Host smart-b9da393d-a1b0-4c6d-8a8b-0dad8f2756c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29071
28477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2907128477
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.158771487
Short name T2043
Test name
Test status
Simulation time 3173108918 ps
CPU time 88.73 seconds
Started Jul 28 07:40:34 PM PDT 24
Finished Jul 28 07:42:03 PM PDT 24
Peak memory 215604 kb
Host smart-acf2cd58-385a-4315-bf51-ae8a64c29784
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=158771487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.158771487
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3652136144
Short name T384
Test name
Test status
Simulation time 232754797 ps
CPU time 1.02 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:38 PM PDT 24
Peak memory 207036 kb
Host smart-8d47646b-8e79-48a4-8d5d-bec3ab1563f1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3652136144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3652136144
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1211573285
Short name T417
Test name
Test status
Simulation time 226795824 ps
CPU time 0.96 seconds
Started Jul 28 07:40:38 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207136 kb
Host smart-56dc8a35-77a4-4c98-9f8a-bb2d348124fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12115
73285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1211573285
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.110226720
Short name T1111
Test name
Test status
Simulation time 3343831455 ps
CPU time 93.63 seconds
Started Jul 28 07:40:39 PM PDT 24
Finished Jul 28 07:42:13 PM PDT 24
Peak memory 215520 kb
Host smart-be8ad310-fd0b-4750-b5ca-b060f1782589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11022
6720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.110226720
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1676362799
Short name T299
Test name
Test status
Simulation time 7376579071 ps
CPU time 79.28 seconds
Started Jul 28 07:40:42 PM PDT 24
Finished Jul 28 07:42:01 PM PDT 24
Peak memory 207404 kb
Host smart-fba7797d-e817-426e-adb3-01152a7f1a67
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1676362799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1676362799
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1876207608
Short name T761
Test name
Test status
Simulation time 148930796 ps
CPU time 0.86 seconds
Started Jul 28 07:40:39 PM PDT 24
Finished Jul 28 07:40:40 PM PDT 24
Peak memory 207116 kb
Host smart-f517eefc-ab1c-4c30-b0a2-36b21f3e5669
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1876207608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1876207608
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.435698463
Short name T2302
Test name
Test status
Simulation time 168114836 ps
CPU time 0.86 seconds
Started Jul 28 07:40:41 PM PDT 24
Finished Jul 28 07:40:41 PM PDT 24
Peak memory 207196 kb
Host smart-ad54770f-ec77-4c9a-9d92-647722ea71b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43569
8463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.435698463
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.237586299
Short name T2820
Test name
Test status
Simulation time 230433291 ps
CPU time 0.94 seconds
Started Jul 28 07:40:36 PM PDT 24
Finished Jul 28 07:40:37 PM PDT 24
Peak memory 207132 kb
Host smart-d1e8935d-36fd-4f57-9d1c-5c852337b79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23758
6299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.237586299
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.1185867667
Short name T110
Test name
Test status
Simulation time 174032118 ps
CPU time 0.85 seconds
Started Jul 28 07:40:34 PM PDT 24
Finished Jul 28 07:40:35 PM PDT 24
Peak memory 207164 kb
Host smart-da0422ab-ef1b-4fd5-ae09-cd43f91d6280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11858
67667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.1185867667
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3534588776
Short name T2731
Test name
Test status
Simulation time 166542382 ps
CPU time 0.85 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:38 PM PDT 24
Peak memory 207060 kb
Host smart-58b9c91b-87a6-42fd-92ef-1644143bd450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35345
88776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3534588776
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3213605879
Short name T1226
Test name
Test status
Simulation time 178369761 ps
CPU time 0.89 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:38 PM PDT 24
Peak memory 207088 kb
Host smart-9f45dd6a-1efd-4fa6-982d-95e85405d779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32136
05879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3213605879
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.623694656
Short name T2362
Test name
Test status
Simulation time 157209395 ps
CPU time 0.81 seconds
Started Jul 28 07:40:38 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207084 kb
Host smart-21cc3456-966f-4bee-9fc4-e8bdb36e6da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62369
4656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.623694656
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.3953201613
Short name T2649
Test name
Test status
Simulation time 256582503 ps
CPU time 1 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:38 PM PDT 24
Peak memory 207136 kb
Host smart-6cd2128a-162a-4b3e-a95f-0836e70b2078
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3953201613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.3953201613
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2259437022
Short name T851
Test name
Test status
Simulation time 158235896 ps
CPU time 0.83 seconds
Started Jul 28 07:40:40 PM PDT 24
Finished Jul 28 07:40:41 PM PDT 24
Peak memory 207112 kb
Host smart-55e0efa8-269a-4433-a69c-4705c239d082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22594
37022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2259437022
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1070534875
Short name T2845
Test name
Test status
Simulation time 176480066 ps
CPU time 0.93 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207160 kb
Host smart-69856010-bcf7-4aca-af6f-8de70330cead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705
34875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1070534875
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2405785886
Short name T1423
Test name
Test status
Simulation time 296977705 ps
CPU time 1.03 seconds
Started Jul 28 07:40:36 PM PDT 24
Finished Jul 28 07:40:42 PM PDT 24
Peak memory 207052 kb
Host smart-4ea6d218-9744-4402-af9d-31905042f5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24057
85886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2405785886
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3413416114
Short name T1674
Test name
Test status
Simulation time 198531044 ps
CPU time 0.98 seconds
Started Jul 28 07:40:38 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207128 kb
Host smart-7a6dd771-4f8c-4241-8d7c-d519e7d9dedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34134
16114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3413416114
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2430852798
Short name T2593
Test name
Test status
Simulation time 185330255 ps
CPU time 0.91 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:40:38 PM PDT 24
Peak memory 207088 kb
Host smart-238f421a-834c-4cd5-b675-cbb55f531f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24308
52798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2430852798
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.401480060
Short name T2668
Test name
Test status
Simulation time 147385005 ps
CPU time 0.84 seconds
Started Jul 28 07:40:38 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 207072 kb
Host smart-a55c7f7c-d1a8-4243-b7c6-ced9ae1cd5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40148
0060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.401480060
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3816728605
Short name T2659
Test name
Test status
Simulation time 154082512 ps
CPU time 0.9 seconds
Started Jul 28 07:40:44 PM PDT 24
Finished Jul 28 07:40:45 PM PDT 24
Peak memory 207080 kb
Host smart-daf27613-290f-487f-a058-d498ceccf0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38167
28605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3816728605
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.634683194
Short name T1056
Test name
Test status
Simulation time 158328856 ps
CPU time 0.85 seconds
Started Jul 28 07:40:41 PM PDT 24
Finished Jul 28 07:40:42 PM PDT 24
Peak memory 207132 kb
Host smart-f094a887-5d26-4379-919b-2e8ed18dc6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63468
3194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.634683194
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1655924102
Short name T2526
Test name
Test status
Simulation time 195736338 ps
CPU time 1 seconds
Started Jul 28 07:40:40 PM PDT 24
Finished Jul 28 07:40:41 PM PDT 24
Peak memory 207192 kb
Host smart-b15197ed-7661-47c7-9557-fb884e73a465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16559
24102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1655924102
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2313445904
Short name T2379
Test name
Test status
Simulation time 5663179105 ps
CPU time 174.06 seconds
Started Jul 28 07:40:39 PM PDT 24
Finished Jul 28 07:43:33 PM PDT 24
Peak memory 215588 kb
Host smart-b9b380b9-14df-4517-9393-73a5fc410ada
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2313445904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2313445904
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2168271754
Short name T2015
Test name
Test status
Simulation time 162975494 ps
CPU time 0.83 seconds
Started Jul 28 07:40:36 PM PDT 24
Finished Jul 28 07:40:37 PM PDT 24
Peak memory 207124 kb
Host smart-3da860aa-62a4-4d6e-8c8d-fdde99dc3690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21682
71754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2168271754
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3305500013
Short name T2545
Test name
Test status
Simulation time 197528177 ps
CPU time 0.98 seconds
Started Jul 28 07:41:13 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207112 kb
Host smart-0166193c-d820-4216-a24f-6bd268b7da57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33055
00013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3305500013
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.4100027942
Short name T2838
Test name
Test status
Simulation time 605773610 ps
CPU time 1.62 seconds
Started Jul 28 07:40:39 PM PDT 24
Finished Jul 28 07:40:41 PM PDT 24
Peak memory 207136 kb
Host smart-e7f45f92-02f1-4f8f-99c0-0c2d0ac24431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41000
27942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.4100027942
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.603003012
Short name T2757
Test name
Test status
Simulation time 7292000128 ps
CPU time 76.06 seconds
Started Jul 28 07:40:41 PM PDT 24
Finished Jul 28 07:41:57 PM PDT 24
Peak memory 207412 kb
Host smart-0c9694e6-699a-413d-aba1-cc931630e366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60300
3012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.603003012
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.1632174640
Short name T2618
Test name
Test status
Simulation time 1277492661 ps
CPU time 30.2 seconds
Started Jul 28 07:40:37 PM PDT 24
Finished Jul 28 07:41:07 PM PDT 24
Peak memory 207412 kb
Host smart-831ca530-5382-4271-a853-0d8e9ff0d465
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632174640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.1632174640
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.3283973959
Short name T747
Test name
Test status
Simulation time 40543035 ps
CPU time 0.7 seconds
Started Jul 28 07:40:51 PM PDT 24
Finished Jul 28 07:40:51 PM PDT 24
Peak memory 207192 kb
Host smart-3ab68947-624d-4c8b-877f-22f895fb60d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3283973959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.3283973959
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.2718920353
Short name T1121
Test name
Test status
Simulation time 3740320202 ps
CPU time 6.14 seconds
Started Jul 28 07:40:46 PM PDT 24
Finished Jul 28 07:40:52 PM PDT 24
Peak memory 207460 kb
Host smart-39db2763-c1a4-4dbe-b6ab-7c406e9012dc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718920353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.2718920353
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3504845695
Short name T1052
Test name
Test status
Simulation time 13324110850 ps
CPU time 14.94 seconds
Started Jul 28 07:40:45 PM PDT 24
Finished Jul 28 07:41:00 PM PDT 24
Peak memory 207436 kb
Host smart-ce7fc22e-2e04-43a1-9592-7862b68dc740
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504845695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3504845695
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2976787120
Short name T2427
Test name
Test status
Simulation time 23366477624 ps
CPU time 31.1 seconds
Started Jul 28 07:40:57 PM PDT 24
Finished Jul 28 07:41:29 PM PDT 24
Peak memory 207388 kb
Host smart-07b17fd5-1f87-4854-b13a-a440a43fd9e0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976787120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.2976787120
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2961186310
Short name T934
Test name
Test status
Simulation time 205147673 ps
CPU time 0.96 seconds
Started Jul 28 07:40:43 PM PDT 24
Finished Jul 28 07:40:45 PM PDT 24
Peak memory 207176 kb
Host smart-731f38bc-065c-48b8-814c-cc3946fb20a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29611
86310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2961186310
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3586792486
Short name T1109
Test name
Test status
Simulation time 161100289 ps
CPU time 0.9 seconds
Started Jul 28 07:40:52 PM PDT 24
Finished Jul 28 07:40:53 PM PDT 24
Peak memory 207052 kb
Host smart-d5c4402c-14db-4b14-b098-acdb85894ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35867
92486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3586792486
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1783439628
Short name T2074
Test name
Test status
Simulation time 400788440 ps
CPU time 1.42 seconds
Started Jul 28 07:40:41 PM PDT 24
Finished Jul 28 07:40:43 PM PDT 24
Peak memory 207136 kb
Host smart-5d25162e-59f1-44d4-a846-f19129abd701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17834
39628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1783439628
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3075904854
Short name T2787
Test name
Test status
Simulation time 1513444170 ps
CPU time 3.78 seconds
Started Jul 28 07:40:53 PM PDT 24
Finished Jul 28 07:40:57 PM PDT 24
Peak memory 207344 kb
Host smart-b77813dc-fbbf-40fd-9e45-f9f4f1d948c5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3075904854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3075904854
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.865118480
Short name T1093
Test name
Test status
Simulation time 21543706261 ps
CPU time 51.1 seconds
Started Jul 28 07:40:44 PM PDT 24
Finished Jul 28 07:41:36 PM PDT 24
Peak memory 207368 kb
Host smart-c9969e24-72f2-4faa-8d10-b9724a299e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86511
8480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.865118480
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.1363070899
Short name T2758
Test name
Test status
Simulation time 661997224 ps
CPU time 5.07 seconds
Started Jul 28 07:40:46 PM PDT 24
Finished Jul 28 07:40:51 PM PDT 24
Peak memory 207356 kb
Host smart-c131e1af-be47-40b5-b5ed-550203f8fccb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363070899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.1363070899
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3887211909
Short name T2225
Test name
Test status
Simulation time 360364015 ps
CPU time 1.46 seconds
Started Jul 28 07:40:47 PM PDT 24
Finished Jul 28 07:40:48 PM PDT 24
Peak memory 207088 kb
Host smart-a59eb233-89c4-4261-a2c3-82e611840b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38872
11909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3887211909
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.571949854
Short name T2279
Test name
Test status
Simulation time 142640491 ps
CPU time 0.85 seconds
Started Jul 28 07:40:42 PM PDT 24
Finished Jul 28 07:40:43 PM PDT 24
Peak memory 207088 kb
Host smart-62afd0c4-d65f-4088-a5e9-cf2486f2bbb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57194
9854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.571949854
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.758761085
Short name T2652
Test name
Test status
Simulation time 33120825 ps
CPU time 0.71 seconds
Started Jul 28 07:40:46 PM PDT 24
Finished Jul 28 07:40:47 PM PDT 24
Peak memory 207124 kb
Host smart-09aa0bf1-5e15-4fc0-ab54-e508199873d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75876
1085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.758761085
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2455201130
Short name T2367
Test name
Test status
Simulation time 907994301 ps
CPU time 2.23 seconds
Started Jul 28 07:40:43 PM PDT 24
Finished Jul 28 07:40:45 PM PDT 24
Peak memory 207324 kb
Host smart-d77fc5ee-6cda-40f0-8048-f807d88407be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24552
01130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2455201130
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.1882730720
Short name T2416
Test name
Test status
Simulation time 195159504 ps
CPU time 2.09 seconds
Started Jul 28 07:40:46 PM PDT 24
Finished Jul 28 07:40:49 PM PDT 24
Peak memory 207328 kb
Host smart-99e977ec-6818-4afd-86b0-da25e5c79fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18827
30720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.1882730720
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.361860530
Short name T762
Test name
Test status
Simulation time 168457882 ps
CPU time 0.94 seconds
Started Jul 28 07:40:48 PM PDT 24
Finished Jul 28 07:40:49 PM PDT 24
Peak memory 207152 kb
Host smart-3845308b-a227-4a8e-9712-64308b43a9b7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=361860530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.361860530
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1276203978
Short name T2586
Test name
Test status
Simulation time 150077933 ps
CPU time 0.79 seconds
Started Jul 28 07:40:48 PM PDT 24
Finished Jul 28 07:40:49 PM PDT 24
Peak memory 207028 kb
Host smart-6fae4134-bcfb-4bc4-a37e-3856d2f1bf92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12762
03978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1276203978
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2226467865
Short name T1105
Test name
Test status
Simulation time 229479383 ps
CPU time 1.1 seconds
Started Jul 28 07:40:42 PM PDT 24
Finished Jul 28 07:40:43 PM PDT 24
Peak memory 207124 kb
Host smart-74f40e4d-7d38-45b9-8d31-8077e646252c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22264
67865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2226467865
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.3370169064
Short name T671
Test name
Test status
Simulation time 9213848046 ps
CPU time 278.18 seconds
Started Jul 28 07:40:59 PM PDT 24
Finished Jul 28 07:45:37 PM PDT 24
Peak memory 215636 kb
Host smart-0ff2895b-5563-4962-aa41-30b0ccfaf784
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3370169064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.3370169064
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.4073875878
Short name T1995
Test name
Test status
Simulation time 6080495735 ps
CPU time 37.27 seconds
Started Jul 28 07:40:45 PM PDT 24
Finished Jul 28 07:41:22 PM PDT 24
Peak memory 207324 kb
Host smart-76acd4ec-33bf-4a5f-be0c-0c0f72653efa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4073875878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.4073875878
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.1345501873
Short name T938
Test name
Test status
Simulation time 243773596 ps
CPU time 0.99 seconds
Started Jul 28 07:40:47 PM PDT 24
Finished Jul 28 07:40:48 PM PDT 24
Peak memory 207068 kb
Host smart-1b4b2ae7-e9b6-4ceb-a20b-c8f6e69fa58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13455
01873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.1345501873
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.1451791588
Short name T843
Test name
Test status
Simulation time 23331426424 ps
CPU time 30.09 seconds
Started Jul 28 07:40:45 PM PDT 24
Finished Jul 28 07:41:16 PM PDT 24
Peak memory 207352 kb
Host smart-a9a8a05b-9ad5-4f4a-818a-921d473da5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14517
91588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1451791588
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.245502102
Short name T2650
Test name
Test status
Simulation time 3367117940 ps
CPU time 4.92 seconds
Started Jul 28 07:40:47 PM PDT 24
Finished Jul 28 07:40:52 PM PDT 24
Peak memory 207416 kb
Host smart-69a04277-ca8f-4338-a2d9-7147cfc8fe91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24550
2102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.245502102
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.2461397856
Short name T2690
Test name
Test status
Simulation time 6309520533 ps
CPU time 186.48 seconds
Started Jul 28 07:40:50 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 215628 kb
Host smart-6622085d-e892-4cde-b044-a5dad6b2fa50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24613
97856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.2461397856
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.4013421070
Short name T658
Test name
Test status
Simulation time 5453998721 ps
CPU time 40.15 seconds
Started Jul 28 07:40:50 PM PDT 24
Finished Jul 28 07:41:30 PM PDT 24
Peak memory 207360 kb
Host smart-34dca565-14d0-4bf3-8f11-14a6c62086a1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4013421070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.4013421070
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.3973047384
Short name T1280
Test name
Test status
Simulation time 235883042 ps
CPU time 0.98 seconds
Started Jul 28 07:40:45 PM PDT 24
Finished Jul 28 07:40:47 PM PDT 24
Peak memory 207136 kb
Host smart-2d685444-8c44-4c69-9dcc-fe871a16e890
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3973047384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.3973047384
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3931529495
Short name T974
Test name
Test status
Simulation time 214228905 ps
CPU time 0.94 seconds
Started Jul 28 07:40:45 PM PDT 24
Finished Jul 28 07:40:46 PM PDT 24
Peak memory 207164 kb
Host smart-e517e8f4-98ad-45e7-a675-7d60f831a92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39315
29495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3931529495
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.3942876743
Short name T2727
Test name
Test status
Simulation time 5417689615 ps
CPU time 44.31 seconds
Started Jul 28 07:40:44 PM PDT 24
Finished Jul 28 07:41:29 PM PDT 24
Peak memory 217320 kb
Host smart-a8d3c8ac-300d-4ad5-bebd-13ac7bfbc1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39428
76743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.3942876743
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1797421661
Short name T1414
Test name
Test status
Simulation time 7013473012 ps
CPU time 51.6 seconds
Started Jul 28 07:40:47 PM PDT 24
Finished Jul 28 07:41:39 PM PDT 24
Peak memory 207404 kb
Host smart-e50db191-7b08-45aa-ac3f-d34108d5719a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1797421661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1797421661
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.1393842632
Short name T2336
Test name
Test status
Simulation time 167568166 ps
CPU time 0.86 seconds
Started Jul 28 07:40:58 PM PDT 24
Finished Jul 28 07:40:59 PM PDT 24
Peak memory 207140 kb
Host smart-87559b57-b0f1-4e6d-89fe-f742742ea0a1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1393842632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.1393842632
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3566395286
Short name T2234
Test name
Test status
Simulation time 139765925 ps
CPU time 0.84 seconds
Started Jul 28 07:40:52 PM PDT 24
Finished Jul 28 07:40:53 PM PDT 24
Peak memory 207096 kb
Host smart-bf53bd23-8826-40ad-b522-0dcf34490aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35663
95286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3566395286
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2156398371
Short name T122
Test name
Test status
Simulation time 219618845 ps
CPU time 0.98 seconds
Started Jul 28 07:40:45 PM PDT 24
Finished Jul 28 07:40:46 PM PDT 24
Peak memory 207124 kb
Host smart-cc5bce88-4056-4da9-890e-983e954511c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21563
98371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2156398371
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2753628974
Short name T780
Test name
Test status
Simulation time 212191851 ps
CPU time 0.95 seconds
Started Jul 28 07:40:53 PM PDT 24
Finished Jul 28 07:40:54 PM PDT 24
Peak memory 207064 kb
Host smart-f51e788f-eaed-4b74-ab22-ea855f189c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27536
28974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2753628974
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3023851475
Short name T1794
Test name
Test status
Simulation time 162923597 ps
CPU time 0.85 seconds
Started Jul 28 07:40:47 PM PDT 24
Finished Jul 28 07:40:48 PM PDT 24
Peak memory 207140 kb
Host smart-f64e5ce9-d4b2-440f-9d6b-be9d828d2fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30238
51475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3023851475
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.4275747382
Short name T2166
Test name
Test status
Simulation time 218853965 ps
CPU time 0.92 seconds
Started Jul 28 07:40:51 PM PDT 24
Finished Jul 28 07:40:52 PM PDT 24
Peak memory 207076 kb
Host smart-28437476-494d-4f9f-b5b9-4e3d107508e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42757
47382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.4275747382
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.379703995
Short name T1138
Test name
Test status
Simulation time 159191747 ps
CPU time 0.88 seconds
Started Jul 28 07:40:48 PM PDT 24
Finished Jul 28 07:40:49 PM PDT 24
Peak memory 207060 kb
Host smart-2e27ff39-e460-423e-aabd-84d5fdeab076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37970
3995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.379703995
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.3430756123
Short name T2805
Test name
Test status
Simulation time 238794449 ps
CPU time 1.04 seconds
Started Jul 28 07:40:56 PM PDT 24
Finished Jul 28 07:40:57 PM PDT 24
Peak memory 207172 kb
Host smart-5931515f-3a3c-42bf-9f23-8b95cd4b141e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3430756123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.3430756123
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1738671742
Short name T1989
Test name
Test status
Simulation time 145838741 ps
CPU time 0.83 seconds
Started Jul 28 07:40:49 PM PDT 24
Finished Jul 28 07:40:50 PM PDT 24
Peak memory 207068 kb
Host smart-ff3753cf-d92a-4fda-84a2-bda8609f9116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17386
71742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1738671742
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2109309930
Short name T1417
Test name
Test status
Simulation time 47527580 ps
CPU time 0.69 seconds
Started Jul 28 07:41:03 PM PDT 24
Finished Jul 28 07:41:04 PM PDT 24
Peak memory 207120 kb
Host smart-c0da4006-260a-4d31-a8ad-98128a0cd7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21093
09930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2109309930
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.402317491
Short name T2169
Test name
Test status
Simulation time 14981577800 ps
CPU time 36.87 seconds
Started Jul 28 07:40:47 PM PDT 24
Finished Jul 28 07:41:24 PM PDT 24
Peak memory 215556 kb
Host smart-5173b0ed-b6cb-4df8-9373-3e7945d0c074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40231
7491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.402317491
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.830619434
Short name T519
Test name
Test status
Simulation time 204270792 ps
CPU time 0.95 seconds
Started Jul 28 07:41:00 PM PDT 24
Finished Jul 28 07:41:01 PM PDT 24
Peak memory 207128 kb
Host smart-54848195-80a2-4f27-8185-c8edbe37b97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83061
9434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.830619434
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3898735196
Short name T2493
Test name
Test status
Simulation time 153888058 ps
CPU time 0.89 seconds
Started Jul 28 07:40:50 PM PDT 24
Finished Jul 28 07:40:51 PM PDT 24
Peak memory 207056 kb
Host smart-3ab0855c-c6fa-4885-904b-e0cedc075173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38987
35196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3898735196
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1870198854
Short name T1783
Test name
Test status
Simulation time 181872269 ps
CPU time 0.89 seconds
Started Jul 28 07:40:51 PM PDT 24
Finished Jul 28 07:40:52 PM PDT 24
Peak memory 207076 kb
Host smart-7b09ad87-4b72-4034-9ad9-516b7f4784bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18701
98854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1870198854
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.3610439931
Short name T1114
Test name
Test status
Simulation time 185508258 ps
CPU time 0.95 seconds
Started Jul 28 07:41:00 PM PDT 24
Finished Jul 28 07:41:01 PM PDT 24
Peak memory 207156 kb
Host smart-99cf2293-d6f6-452f-bf78-164cd7083ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36104
39931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3610439931
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.625740759
Short name T1436
Test name
Test status
Simulation time 168907893 ps
CPU time 0.92 seconds
Started Jul 28 07:40:47 PM PDT 24
Finished Jul 28 07:40:48 PM PDT 24
Peak memory 207012 kb
Host smart-32b607ff-4fc5-4187-948b-352bc4178726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62574
0759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.625740759
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3051546020
Short name T461
Test name
Test status
Simulation time 217020590 ps
CPU time 0.91 seconds
Started Jul 28 07:40:53 PM PDT 24
Finished Jul 28 07:40:54 PM PDT 24
Peak memory 207136 kb
Host smart-c6e37ef6-c3bf-4bc2-9b19-c9b4e1df0d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30515
46020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3051546020
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3723887182
Short name T1077
Test name
Test status
Simulation time 152171034 ps
CPU time 0.87 seconds
Started Jul 28 07:40:58 PM PDT 24
Finished Jul 28 07:40:59 PM PDT 24
Peak memory 207108 kb
Host smart-424f988f-8788-4195-b5fd-1763cae99afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37238
87182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3723887182
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3263969126
Short name T1196
Test name
Test status
Simulation time 193629387 ps
CPU time 0.95 seconds
Started Jul 28 07:40:49 PM PDT 24
Finished Jul 28 07:40:50 PM PDT 24
Peak memory 207080 kb
Host smart-6f323c8e-d181-4d71-8069-f5b7574b7ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32639
69126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3263969126
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.3495175383
Short name T623
Test name
Test status
Simulation time 4607803890 ps
CPU time 45.59 seconds
Started Jul 28 07:40:54 PM PDT 24
Finished Jul 28 07:41:40 PM PDT 24
Peak memory 215572 kb
Host smart-3065cdd9-4ba9-462f-9959-326c05215523
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3495175383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.3495175383
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2109947560
Short name T2753
Test name
Test status
Simulation time 163637089 ps
CPU time 0.88 seconds
Started Jul 28 07:40:47 PM PDT 24
Finished Jul 28 07:40:48 PM PDT 24
Peak memory 207060 kb
Host smart-1dd0edf5-99e2-4c91-8747-25254fdc6824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21099
47560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2109947560
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.221582332
Short name T2868
Test name
Test status
Simulation time 182616049 ps
CPU time 0.84 seconds
Started Jul 28 07:41:00 PM PDT 24
Finished Jul 28 07:41:01 PM PDT 24
Peak memory 207100 kb
Host smart-59a6c182-6d51-4c6b-b7ab-d8e7f7f3ea7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22158
2332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.221582332
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.192996188
Short name T2207
Test name
Test status
Simulation time 437325089 ps
CPU time 1.4 seconds
Started Jul 28 07:40:47 PM PDT 24
Finished Jul 28 07:40:48 PM PDT 24
Peak memory 207268 kb
Host smart-7a94f8ed-ba89-4faa-a443-3ef391152e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19299
6188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.192996188
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.4026687508
Short name T925
Test name
Test status
Simulation time 4011164316 ps
CPU time 118.15 seconds
Started Jul 28 07:40:47 PM PDT 24
Finished Jul 28 07:42:46 PM PDT 24
Peak memory 215572 kb
Host smart-c1bd976f-a3d9-45df-9674-73a1caa5f6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40266
87508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.4026687508
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.493188118
Short name T2849
Test name
Test status
Simulation time 4838550659 ps
CPU time 45.63 seconds
Started Jul 28 07:40:47 PM PDT 24
Finished Jul 28 07:41:33 PM PDT 24
Peak memory 207344 kb
Host smart-68ba24d2-6ce1-4d6b-b009-5cdd154dcab5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493188118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_host
_handshake.493188118
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.992715532
Short name T647
Test name
Test status
Simulation time 68683922 ps
CPU time 0.69 seconds
Started Jul 28 07:41:14 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207156 kb
Host smart-59368cad-2cb5-4d6c-9df9-b7231646a80b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=992715532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.992715532
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2748344489
Short name T2250
Test name
Test status
Simulation time 3615975390 ps
CPU time 5.59 seconds
Started Jul 28 07:40:58 PM PDT 24
Finished Jul 28 07:41:04 PM PDT 24
Peak memory 207404 kb
Host smart-2eafea4d-2999-4473-b280-273467118c12
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748344489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.2748344489
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3427886979
Short name T1169
Test name
Test status
Simulation time 13405327622 ps
CPU time 15.41 seconds
Started Jul 28 07:40:46 PM PDT 24
Finished Jul 28 07:41:01 PM PDT 24
Peak memory 207368 kb
Host smart-662aaddf-255c-4870-99f6-e181d6ab55a7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427886979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3427886979
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.392485839
Short name T1194
Test name
Test status
Simulation time 23294806918 ps
CPU time 31.75 seconds
Started Jul 28 07:40:58 PM PDT 24
Finished Jul 28 07:41:30 PM PDT 24
Peak memory 207456 kb
Host smart-9e022675-b320-4063-bc5f-ac4717dee841
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392485839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_ao
n_wake_resume.392485839
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1556714944
Short name T2827
Test name
Test status
Simulation time 143304572 ps
CPU time 0.85 seconds
Started Jul 28 07:40:51 PM PDT 24
Finished Jul 28 07:40:52 PM PDT 24
Peak memory 207072 kb
Host smart-91db1386-b236-4c16-8918-38d15485f0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15567
14944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1556714944
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.2815089498
Short name T557
Test name
Test status
Simulation time 147498417 ps
CPU time 0.87 seconds
Started Jul 28 07:40:45 PM PDT 24
Finished Jul 28 07:40:46 PM PDT 24
Peak memory 207068 kb
Host smart-05b1943a-4c0f-469d-a096-58ec5e45b166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28150
89498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.2815089498
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.553807921
Short name T830
Test name
Test status
Simulation time 163499195 ps
CPU time 0.93 seconds
Started Jul 28 07:40:47 PM PDT 24
Finished Jul 28 07:40:48 PM PDT 24
Peak memory 207060 kb
Host smart-eed48f79-6a4d-40be-8fe1-1131e011d087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55380
7921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.553807921
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2315517291
Short name T2409
Test name
Test status
Simulation time 1502263175 ps
CPU time 3.36 seconds
Started Jul 28 07:40:53 PM PDT 24
Finished Jul 28 07:40:57 PM PDT 24
Peak memory 207308 kb
Host smart-d87bcfc6-6401-4d1c-9c4d-8438a89a100b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2315517291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2315517291
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.1684516004
Short name T161
Test name
Test status
Simulation time 18364359280 ps
CPU time 38.91 seconds
Started Jul 28 07:41:02 PM PDT 24
Finished Jul 28 07:41:41 PM PDT 24
Peak memory 207332 kb
Host smart-f60f7533-9ebf-4949-8649-aeae126791ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16845
16004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.1684516004
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.2852475597
Short name T599
Test name
Test status
Simulation time 1124170635 ps
CPU time 9.34 seconds
Started Jul 28 07:40:56 PM PDT 24
Finished Jul 28 07:41:06 PM PDT 24
Peak memory 207288 kb
Host smart-6a2ee05c-6880-4521-9bbb-d01e8912d52b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852475597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.2852475597
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.2086734199
Short name T2080
Test name
Test status
Simulation time 418332274 ps
CPU time 1.5 seconds
Started Jul 28 07:40:53 PM PDT 24
Finished Jul 28 07:40:55 PM PDT 24
Peak memory 207096 kb
Host smart-14a530ea-3afa-4b25-b83a-03fdb6580263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20867
34199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.2086734199
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2652076380
Short name T2271
Test name
Test status
Simulation time 140362556 ps
CPU time 0.82 seconds
Started Jul 28 07:40:54 PM PDT 24
Finished Jul 28 07:40:55 PM PDT 24
Peak memory 207108 kb
Host smart-6c588ab2-8a9e-4740-8e61-dc4c34ec372e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26520
76380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2652076380
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.213024357
Short name T2734
Test name
Test status
Simulation time 63974266 ps
CPU time 0.74 seconds
Started Jul 28 07:40:51 PM PDT 24
Finished Jul 28 07:40:52 PM PDT 24
Peak memory 207044 kb
Host smart-c46ce1ee-959b-4d2e-8672-665e6d0d7a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21302
4357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.213024357
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.3057737733
Short name T419
Test name
Test status
Simulation time 998977085 ps
CPU time 2.78 seconds
Started Jul 28 07:40:59 PM PDT 24
Finished Jul 28 07:41:01 PM PDT 24
Peak memory 207372 kb
Host smart-87837f4a-3f79-4a3c-b792-274aae2e6deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30577
37733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.3057737733
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3438932862
Short name T1356
Test name
Test status
Simulation time 161331332 ps
CPU time 1.43 seconds
Started Jul 28 07:41:02 PM PDT 24
Finished Jul 28 07:41:03 PM PDT 24
Peak memory 207304 kb
Host smart-18c53ea0-34f9-47c8-831e-4a628229b32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34389
32862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3438932862
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1676925800
Short name T824
Test name
Test status
Simulation time 236834157 ps
CPU time 1.25 seconds
Started Jul 28 07:41:02 PM PDT 24
Finished Jul 28 07:41:03 PM PDT 24
Peak memory 215536 kb
Host smart-1e8e0c71-21a6-459a-a694-ee5778cc4d91
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1676925800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1676925800
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.1651477143
Short name T2653
Test name
Test status
Simulation time 170851162 ps
CPU time 0.82 seconds
Started Jul 28 07:40:54 PM PDT 24
Finished Jul 28 07:40:55 PM PDT 24
Peak memory 207100 kb
Host smart-79633355-bae5-4024-a7bb-256144646c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16514
77143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1651477143
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1983310352
Short name T578
Test name
Test status
Simulation time 214946103 ps
CPU time 0.99 seconds
Started Jul 28 07:41:03 PM PDT 24
Finished Jul 28 07:41:04 PM PDT 24
Peak memory 207116 kb
Host smart-6cbfde68-661e-4b4e-853e-1004ccd97e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19833
10352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1983310352
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.2686572876
Short name T883
Test name
Test status
Simulation time 8835881364 ps
CPU time 92.26 seconds
Started Jul 28 07:40:50 PM PDT 24
Finished Jul 28 07:42:22 PM PDT 24
Peak memory 215708 kb
Host smart-81107f23-b882-433e-8810-2545d3b530bf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2686572876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.2686572876
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.845232623
Short name T1818
Test name
Test status
Simulation time 3687345581 ps
CPU time 42.05 seconds
Started Jul 28 07:41:00 PM PDT 24
Finished Jul 28 07:41:42 PM PDT 24
Peak memory 207324 kb
Host smart-fbaf42e3-7745-4ea0-a901-47c980cae1ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=845232623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.845232623
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2619103987
Short name T960
Test name
Test status
Simulation time 185627343 ps
CPU time 0.87 seconds
Started Jul 28 07:40:52 PM PDT 24
Finished Jul 28 07:40:53 PM PDT 24
Peak memory 207144 kb
Host smart-f0541be3-7baf-4610-8c7f-82f8062a4bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26191
03987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2619103987
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.4201592342
Short name T1517
Test name
Test status
Simulation time 23289177239 ps
CPU time 26.78 seconds
Started Jul 28 07:40:58 PM PDT 24
Finished Jul 28 07:41:25 PM PDT 24
Peak memory 207444 kb
Host smart-3b22db9b-17d8-452f-b0ba-da0f31372b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42015
92342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.4201592342
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2023794439
Short name T1433
Test name
Test status
Simulation time 3286938626 ps
CPU time 4.88 seconds
Started Jul 28 07:41:00 PM PDT 24
Finished Jul 28 07:41:05 PM PDT 24
Peak memory 207292 kb
Host smart-1937ff59-15dc-4ec3-ae11-e71967339d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20237
94439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2023794439
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.1422721608
Short name T1058
Test name
Test status
Simulation time 8424316202 ps
CPU time 61.62 seconds
Started Jul 28 07:40:53 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 217288 kb
Host smart-2becc4ef-bcab-4e9d-a9d1-7d6e2c9e9a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14227
21608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.1422721608
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2899903996
Short name T2685
Test name
Test status
Simulation time 4103626934 ps
CPU time 31.81 seconds
Started Jul 28 07:40:55 PM PDT 24
Finished Jul 28 07:41:27 PM PDT 24
Peak memory 207428 kb
Host smart-fbbb18ce-3c43-496d-8736-c8b59d94451b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2899903996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2899903996
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.2032240131
Short name T517
Test name
Test status
Simulation time 254658454 ps
CPU time 1.06 seconds
Started Jul 28 07:40:59 PM PDT 24
Finished Jul 28 07:41:00 PM PDT 24
Peak memory 207052 kb
Host smart-77ce3116-0ee4-4c7e-9e11-3b8ac2d59897
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2032240131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.2032240131
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2826323942
Short name T2463
Test name
Test status
Simulation time 178202870 ps
CPU time 0.93 seconds
Started Jul 28 07:40:54 PM PDT 24
Finished Jul 28 07:40:55 PM PDT 24
Peak memory 207108 kb
Host smart-cc4eaad7-1ef1-4b41-8b28-0e8bc677d54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28263
23942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2826323942
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.3957957254
Short name T2609
Test name
Test status
Simulation time 3766823378 ps
CPU time 109.24 seconds
Started Jul 28 07:40:53 PM PDT 24
Finished Jul 28 07:42:42 PM PDT 24
Peak memory 215576 kb
Host smart-31644c53-b6bc-45fd-be0a-a87628197bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39579
57254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.3957957254
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3026080496
Short name T613
Test name
Test status
Simulation time 4868700097 ps
CPU time 51.36 seconds
Started Jul 28 07:40:54 PM PDT 24
Finished Jul 28 07:41:45 PM PDT 24
Peak memory 217092 kb
Host smart-e2dde1ad-2c6b-4c8b-a05c-a6b9572480fb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3026080496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3026080496
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.1105678294
Short name T810
Test name
Test status
Simulation time 151357716 ps
CPU time 0.97 seconds
Started Jul 28 07:40:50 PM PDT 24
Finished Jul 28 07:40:51 PM PDT 24
Peak memory 207152 kb
Host smart-0f88f2f3-25c3-400a-8379-fb8e38514a75
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1105678294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.1105678294
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1638401980
Short name T1851
Test name
Test status
Simulation time 179367208 ps
CPU time 0.88 seconds
Started Jul 28 07:41:01 PM PDT 24
Finished Jul 28 07:41:02 PM PDT 24
Peak memory 207064 kb
Host smart-35505b0a-9e8b-4554-b982-a101464ddb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16384
01980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1638401980
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2184145713
Short name T2794
Test name
Test status
Simulation time 219170843 ps
CPU time 1.02 seconds
Started Jul 28 07:40:58 PM PDT 24
Finished Jul 28 07:40:59 PM PDT 24
Peak memory 207108 kb
Host smart-93c590ca-53e2-487d-ac3d-168546bd5147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21841
45713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2184145713
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1053129711
Short name T2345
Test name
Test status
Simulation time 175753374 ps
CPU time 0.96 seconds
Started Jul 28 07:40:56 PM PDT 24
Finished Jul 28 07:40:57 PM PDT 24
Peak memory 207284 kb
Host smart-d89efd8c-0ffb-4e4f-8869-27fa84e60755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10531
29711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1053129711
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.187599101
Short name T1339
Test name
Test status
Simulation time 190265877 ps
CPU time 0.93 seconds
Started Jul 28 07:40:57 PM PDT 24
Finished Jul 28 07:40:58 PM PDT 24
Peak memory 207116 kb
Host smart-8015ada2-354c-4c8b-a2dd-42677619f845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18759
9101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.187599101
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3604207180
Short name T1962
Test name
Test status
Simulation time 174930694 ps
CPU time 0.91 seconds
Started Jul 28 07:41:01 PM PDT 24
Finished Jul 28 07:41:02 PM PDT 24
Peak memory 207204 kb
Host smart-2fada35d-cd79-46b5-97b3-a061e5d30292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36042
07180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3604207180
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2067992309
Short name T746
Test name
Test status
Simulation time 171596703 ps
CPU time 0.9 seconds
Started Jul 28 07:40:56 PM PDT 24
Finished Jul 28 07:40:57 PM PDT 24
Peak memory 207144 kb
Host smart-1c5a9ca1-e4ea-4ac2-8423-afcb56af6f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20679
92309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2067992309
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.608806292
Short name T1163
Test name
Test status
Simulation time 210528745 ps
CPU time 0.95 seconds
Started Jul 28 07:41:08 PM PDT 24
Finished Jul 28 07:41:09 PM PDT 24
Peak memory 207092 kb
Host smart-56926db7-f16f-4036-b16b-7c0fb66c1c6b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=608806292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.608806292
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.392445642
Short name T941
Test name
Test status
Simulation time 190754800 ps
CPU time 0.83 seconds
Started Jul 28 07:40:57 PM PDT 24
Finished Jul 28 07:40:58 PM PDT 24
Peak memory 207116 kb
Host smart-c3510541-e9be-492f-9eba-36f5b5bc0930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39244
5642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.392445642
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1962721275
Short name T30
Test name
Test status
Simulation time 36174453 ps
CPU time 0.69 seconds
Started Jul 28 07:40:59 PM PDT 24
Finished Jul 28 07:40:59 PM PDT 24
Peak memory 207016 kb
Host smart-bc396495-067d-4286-b8e1-67fdad467fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19627
21275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1962721275
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3657224118
Short name T2072
Test name
Test status
Simulation time 16888829972 ps
CPU time 43.42 seconds
Started Jul 28 07:40:58 PM PDT 24
Finished Jul 28 07:41:42 PM PDT 24
Peak memory 223740 kb
Host smart-b22c26bb-66cf-409c-b0ab-98aeb968111d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36572
24118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3657224118
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1041353699
Short name T2449
Test name
Test status
Simulation time 195453307 ps
CPU time 0.94 seconds
Started Jul 28 07:40:53 PM PDT 24
Finished Jul 28 07:40:54 PM PDT 24
Peak memory 207168 kb
Host smart-f1dff50e-fd0c-42cb-9995-822ce7ae2526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10413
53699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1041353699
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.324742843
Short name T1016
Test name
Test status
Simulation time 227086523 ps
CPU time 0.93 seconds
Started Jul 28 07:41:11 PM PDT 24
Finished Jul 28 07:41:12 PM PDT 24
Peak memory 207128 kb
Host smart-939284a4-bd80-42dc-a648-df135636a65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32474
2843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.324742843
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2020271505
Short name T2823
Test name
Test status
Simulation time 201853775 ps
CPU time 0.92 seconds
Started Jul 28 07:40:59 PM PDT 24
Finished Jul 28 07:41:00 PM PDT 24
Peak memory 207140 kb
Host smart-0149b39e-c50d-4c0c-886b-b92fb06e1690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20202
71505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2020271505
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1355711372
Short name T1784
Test name
Test status
Simulation time 205564466 ps
CPU time 1.04 seconds
Started Jul 28 07:41:04 PM PDT 24
Finished Jul 28 07:41:05 PM PDT 24
Peak memory 207164 kb
Host smart-2f87cf6b-e193-420f-8e7d-9e2787e372df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13557
11372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1355711372
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2988858460
Short name T1103
Test name
Test status
Simulation time 186564414 ps
CPU time 0.95 seconds
Started Jul 28 07:41:08 PM PDT 24
Finished Jul 28 07:41:09 PM PDT 24
Peak memory 207160 kb
Host smart-715a3f3f-3a78-454a-b40a-725dadf98ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29888
58460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2988858460
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1185033197
Short name T2083
Test name
Test status
Simulation time 197612165 ps
CPU time 0.98 seconds
Started Jul 28 07:41:04 PM PDT 24
Finished Jul 28 07:41:06 PM PDT 24
Peak memory 207136 kb
Host smart-f2085f1b-ab25-47d8-94c0-685423da7e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11850
33197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1185033197
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.824545014
Short name T2082
Test name
Test status
Simulation time 201499311 ps
CPU time 0.97 seconds
Started Jul 28 07:41:00 PM PDT 24
Finished Jul 28 07:41:01 PM PDT 24
Peak memory 207176 kb
Host smart-9438974e-9990-4fd8-a52a-19da3b5bfc49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82454
5014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.824545014
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3411988288
Short name T2687
Test name
Test status
Simulation time 212667992 ps
CPU time 0.95 seconds
Started Jul 28 07:41:10 PM PDT 24
Finished Jul 28 07:41:11 PM PDT 24
Peak memory 207040 kb
Host smart-b82d536d-a348-4662-9296-1ed11639bf28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34119
88288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3411988288
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2394518515
Short name T2022
Test name
Test status
Simulation time 3501803464 ps
CPU time 26.8 seconds
Started Jul 28 07:41:02 PM PDT 24
Finished Jul 28 07:41:29 PM PDT 24
Peak memory 217012 kb
Host smart-4bc40312-bddf-4178-881a-34d4f8f7ebc7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2394518515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2394518515
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3390347467
Short name T1334
Test name
Test status
Simulation time 193057230 ps
CPU time 0.88 seconds
Started Jul 28 07:41:02 PM PDT 24
Finished Jul 28 07:41:03 PM PDT 24
Peak memory 207104 kb
Host smart-be6b425e-d4cc-4e60-b23f-64c14c813957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33903
47467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3390347467
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1289464655
Short name T2187
Test name
Test status
Simulation time 212760051 ps
CPU time 0.95 seconds
Started Jul 28 07:41:02 PM PDT 24
Finished Jul 28 07:41:03 PM PDT 24
Peak memory 207160 kb
Host smart-70a6c87c-185a-4623-b9f7-282b4e27fa8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12894
64655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1289464655
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.2374362940
Short name T2534
Test name
Test status
Simulation time 1124918648 ps
CPU time 3.02 seconds
Started Jul 28 07:40:57 PM PDT 24
Finished Jul 28 07:41:00 PM PDT 24
Peak memory 207268 kb
Host smart-25dda7bf-643f-4d7a-8394-29de809afa7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23743
62940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.2374362940
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2434535097
Short name T2803
Test name
Test status
Simulation time 7302119526 ps
CPU time 227.16 seconds
Started Jul 28 07:41:02 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 215580 kb
Host smart-abdec8ad-3928-4341-a91a-2488c0d9a720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24345
35097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2434535097
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.2296198936
Short name T2460
Test name
Test status
Simulation time 4995694076 ps
CPU time 34.44 seconds
Started Jul 28 07:40:52 PM PDT 24
Finished Jul 28 07:41:27 PM PDT 24
Peak memory 207396 kb
Host smart-8cb04d71-aba3-4d16-b3bb-af16ec7c4ce6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296198936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_hos
t_handshake.2296198936
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.3974569459
Short name T1792
Test name
Test status
Simulation time 49169154 ps
CPU time 0.66 seconds
Started Jul 28 07:41:07 PM PDT 24
Finished Jul 28 07:41:07 PM PDT 24
Peak memory 207124 kb
Host smart-1709c153-a85b-4c00-a6d8-6268e1b6cf5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3974569459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.3974569459
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.64423740
Short name T1381
Test name
Test status
Simulation time 4102404875 ps
CPU time 6.26 seconds
Started Jul 28 07:41:08 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207392 kb
Host smart-c00a48b2-cd4b-43b7-ba63-db49bf0b1e2f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64423740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon
_wake_disconnect.64423740
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1773936958
Short name T1946
Test name
Test status
Simulation time 13383959218 ps
CPU time 16.25 seconds
Started Jul 28 07:40:59 PM PDT 24
Finished Jul 28 07:41:15 PM PDT 24
Peak memory 207412 kb
Host smart-0ba4f610-0a81-4e83-be1f-4147c30e3aca
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773936958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1773936958
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.2204270107
Short name T499
Test name
Test status
Simulation time 23380107734 ps
CPU time 32.33 seconds
Started Jul 28 07:41:02 PM PDT 24
Finished Jul 28 07:41:35 PM PDT 24
Peak memory 207356 kb
Host smart-41963e57-0e6c-43b7-9e37-34b069134f89
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204270107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.2204270107
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2270975506
Short name T1156
Test name
Test status
Simulation time 171411231 ps
CPU time 0.85 seconds
Started Jul 28 07:40:58 PM PDT 24
Finished Jul 28 07:40:59 PM PDT 24
Peak memory 207112 kb
Host smart-f2d8b1aa-066f-4b3c-9090-7b569681a9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22709
75506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2270975506
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1133549233
Short name T2036
Test name
Test status
Simulation time 161388646 ps
CPU time 0.81 seconds
Started Jul 28 07:40:59 PM PDT 24
Finished Jul 28 07:41:00 PM PDT 24
Peak memory 207016 kb
Host smart-eaa92beb-2e67-450d-9b1a-bcdbf2d1aadd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11335
49233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1133549233
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3606619205
Short name T2001
Test name
Test status
Simulation time 283390464 ps
CPU time 1.2 seconds
Started Jul 28 07:40:59 PM PDT 24
Finished Jul 28 07:41:01 PM PDT 24
Peak memory 207128 kb
Host smart-31f88053-521c-4e02-b8f1-967f39b34320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36066
19205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3606619205
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1832159590
Short name T1922
Test name
Test status
Simulation time 962367396 ps
CPU time 2.48 seconds
Started Jul 28 07:41:00 PM PDT 24
Finished Jul 28 07:41:03 PM PDT 24
Peak memory 207296 kb
Host smart-015f1982-eae4-44a8-9798-fb32242dabdc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1832159590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1832159590
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.2915170257
Short name T1955
Test name
Test status
Simulation time 2458688571 ps
CPU time 22.56 seconds
Started Jul 28 07:41:00 PM PDT 24
Finished Jul 28 07:41:22 PM PDT 24
Peak memory 207444 kb
Host smart-7c7cdcce-0037-4ee3-9ed9-ca8cdace5919
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915170257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.2915170257
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.4101924688
Short name T267
Test name
Test status
Simulation time 378696984 ps
CPU time 1.25 seconds
Started Jul 28 07:41:00 PM PDT 24
Finished Jul 28 07:41:01 PM PDT 24
Peak memory 207016 kb
Host smart-fed296e3-1ae7-45ad-a551-0350b1f9df09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41019
24688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.4101924688
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.2261057028
Short name T40
Test name
Test status
Simulation time 138359345 ps
CPU time 0.83 seconds
Started Jul 28 07:41:01 PM PDT 24
Finished Jul 28 07:41:02 PM PDT 24
Peak memory 207024 kb
Host smart-ebda1da3-6481-4060-8ead-c53ecd8bca4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22610
57028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.2261057028
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3175914806
Short name T1150
Test name
Test status
Simulation time 126731726 ps
CPU time 0.82 seconds
Started Jul 28 07:41:01 PM PDT 24
Finished Jul 28 07:41:02 PM PDT 24
Peak memory 207096 kb
Host smart-18ad8d9b-f5ea-4bc1-b06f-ba226283b6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31759
14806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3175914806
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.800803415
Short name T924
Test name
Test status
Simulation time 1129984361 ps
CPU time 2.83 seconds
Started Jul 28 07:41:09 PM PDT 24
Finished Jul 28 07:41:12 PM PDT 24
Peak memory 207276 kb
Host smart-2e1669a0-bfc6-40c2-a2cd-a3a6d7a93dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80080
3415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.800803415
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2861982626
Short name T1941
Test name
Test status
Simulation time 340058719 ps
CPU time 2.13 seconds
Started Jul 28 07:41:00 PM PDT 24
Finished Jul 28 07:41:02 PM PDT 24
Peak memory 207288 kb
Host smart-52c586b9-b088-4b53-86ee-f6aba486e197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28619
82626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2861982626
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.1030356069
Short name T1164
Test name
Test status
Simulation time 203477328 ps
CPU time 1.11 seconds
Started Jul 28 07:40:58 PM PDT 24
Finished Jul 28 07:40:59 PM PDT 24
Peak memory 215712 kb
Host smart-a2fba338-36d2-4a13-9282-71b5146c051b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1030356069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.1030356069
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2070848031
Short name T1971
Test name
Test status
Simulation time 154016223 ps
CPU time 0.9 seconds
Started Jul 28 07:41:02 PM PDT 24
Finished Jul 28 07:41:03 PM PDT 24
Peak memory 207084 kb
Host smart-47d91ea7-351f-426b-b79d-e998019f8fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20708
48031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2070848031
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.479423650
Short name T835
Test name
Test status
Simulation time 235236813 ps
CPU time 1.01 seconds
Started Jul 28 07:41:03 PM PDT 24
Finished Jul 28 07:41:04 PM PDT 24
Peak memory 207128 kb
Host smart-6687b31e-e4fc-4562-b280-3739841a6c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47942
3650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.479423650
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.2329587454
Short name T2123
Test name
Test status
Simulation time 6945931077 ps
CPU time 207.2 seconds
Started Jul 28 07:41:04 PM PDT 24
Finished Jul 28 07:44:31 PM PDT 24
Peak memory 215596 kb
Host smart-ee3c740d-fe56-460a-8e5b-2e92dacd4beb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2329587454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.2329587454
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.527089042
Short name T752
Test name
Test status
Simulation time 13101901509 ps
CPU time 82.55 seconds
Started Jul 28 07:41:01 PM PDT 24
Finished Jul 28 07:42:23 PM PDT 24
Peak memory 207348 kb
Host smart-fbd27286-a77c-497e-b56f-6ba955b89f07
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=527089042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.527089042
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.4117648662
Short name T500
Test name
Test status
Simulation time 220175859 ps
CPU time 1.15 seconds
Started Jul 28 07:41:00 PM PDT 24
Finished Jul 28 07:41:01 PM PDT 24
Peak memory 207128 kb
Host smart-bcfa82ad-55e0-4ac3-b8ab-0642c7c93a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41176
48662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.4117648662
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1645915848
Short name T2676
Test name
Test status
Simulation time 23346900990 ps
CPU time 35.65 seconds
Started Jul 28 07:41:01 PM PDT 24
Finished Jul 28 07:41:37 PM PDT 24
Peak memory 207420 kb
Host smart-64e1727f-df7b-4482-a382-f87880e13f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16459
15848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1645915848
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.232390136
Short name T1644
Test name
Test status
Simulation time 3309884476 ps
CPU time 4.81 seconds
Started Jul 28 07:41:02 PM PDT 24
Finished Jul 28 07:41:07 PM PDT 24
Peak memory 207400 kb
Host smart-ed19ea89-6b03-498c-95aa-5967679db87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23239
0136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.232390136
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3278582578
Short name T1914
Test name
Test status
Simulation time 10258175760 ps
CPU time 101.7 seconds
Started Jul 28 07:40:58 PM PDT 24
Finished Jul 28 07:42:39 PM PDT 24
Peak memory 223920 kb
Host smart-19d68a4a-e3b7-4e8e-ac6b-02f23173d660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32785
82578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3278582578
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.3886855569
Short name T779
Test name
Test status
Simulation time 3645122026 ps
CPU time 104.95 seconds
Started Jul 28 07:41:03 PM PDT 24
Finished Jul 28 07:42:48 PM PDT 24
Peak memory 215560 kb
Host smart-def362b9-419e-4eca-a1af-6991c3dbdb6a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3886855569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.3886855569
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.1784892077
Short name T2866
Test name
Test status
Simulation time 233887842 ps
CPU time 0.93 seconds
Started Jul 28 07:41:06 PM PDT 24
Finished Jul 28 07:41:07 PM PDT 24
Peak memory 207112 kb
Host smart-06503834-c853-426c-ab46-6d3072e894d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1784892077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.1784892077
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1605271743
Short name T2761
Test name
Test status
Simulation time 211310444 ps
CPU time 1 seconds
Started Jul 28 07:41:00 PM PDT 24
Finished Jul 28 07:41:01 PM PDT 24
Peak memory 207204 kb
Host smart-a541d613-c770-4473-8b54-971cdc4733f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16052
71743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1605271743
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.1258125815
Short name T426
Test name
Test status
Simulation time 6655535881 ps
CPU time 72.15 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:42:31 PM PDT 24
Peak memory 215548 kb
Host smart-ebcfd20f-11dc-468b-9d18-cd76112f364b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12581
25815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.1258125815
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1968253839
Short name T1569
Test name
Test status
Simulation time 2831602096 ps
CPU time 79.8 seconds
Started Jul 28 07:41:06 PM PDT 24
Finished Jul 28 07:42:26 PM PDT 24
Peak memory 215608 kb
Host smart-f980aad4-4d6f-4364-abcb-bdf3e10face4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1968253839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1968253839
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.63683905
Short name T2195
Test name
Test status
Simulation time 154371376 ps
CPU time 0.85 seconds
Started Jul 28 07:41:13 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207156 kb
Host smart-b2a74ba1-1001-4220-82e2-8f8db659a3c7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=63683905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.63683905
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.433100501
Short name T1968
Test name
Test status
Simulation time 156658647 ps
CPU time 0.84 seconds
Started Jul 28 07:41:06 PM PDT 24
Finished Jul 28 07:41:06 PM PDT 24
Peak memory 207040 kb
Host smart-cbe2c2d1-5900-4fae-9ad1-0c708e274251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43310
0501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.433100501
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.798913693
Short name T1404
Test name
Test status
Simulation time 159599396 ps
CPU time 0.91 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:13 PM PDT 24
Peak memory 207084 kb
Host smart-80701050-06a5-4bbb-81bb-f0493f2e1e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79891
3693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.798913693
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3209010102
Short name T1831
Test name
Test status
Simulation time 171275938 ps
CPU time 0.92 seconds
Started Jul 28 07:41:02 PM PDT 24
Finished Jul 28 07:41:03 PM PDT 24
Peak memory 207176 kb
Host smart-39cfe633-13ab-4271-bed3-a7907bb81232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32090
10102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3209010102
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3077801729
Short name T516
Test name
Test status
Simulation time 172022500 ps
CPU time 0.86 seconds
Started Jul 28 07:41:05 PM PDT 24
Finished Jul 28 07:41:06 PM PDT 24
Peak memory 207116 kb
Host smart-817246b4-96af-49b4-a646-80ad4d3c24a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30778
01729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3077801729
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.4154936357
Short name T2529
Test name
Test status
Simulation time 157368611 ps
CPU time 0.95 seconds
Started Jul 28 07:41:05 PM PDT 24
Finished Jul 28 07:41:06 PM PDT 24
Peak memory 207136 kb
Host smart-6a8d92d6-30d0-4955-a7ae-0b2ab5b32d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41549
36357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.4154936357
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.2657080602
Short name T2412
Test name
Test status
Simulation time 185444027 ps
CPU time 0.92 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:17 PM PDT 24
Peak memory 207188 kb
Host smart-17336610-c12a-4d7b-b362-19516adf8f65
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2657080602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.2657080602
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3405769347
Short name T1897
Test name
Test status
Simulation time 143108455 ps
CPU time 0.83 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:13 PM PDT 24
Peak memory 207172 kb
Host smart-274164b8-0300-4c1f-a990-6904a10c21bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34057
69347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3405769347
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.4114213533
Short name T558
Test name
Test status
Simulation time 35085253 ps
CPU time 0.69 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:13 PM PDT 24
Peak memory 206992 kb
Host smart-d080a56f-f8ae-4105-8124-80afeb6aec26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41142
13533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.4114213533
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1960207939
Short name T261
Test name
Test status
Simulation time 23772961456 ps
CPU time 59.76 seconds
Started Jul 28 07:41:15 PM PDT 24
Finished Jul 28 07:42:15 PM PDT 24
Peak memory 219656 kb
Host smart-da666953-ae95-41f3-a198-aba39eb9f22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19602
07939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1960207939
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.216894082
Short name T1245
Test name
Test status
Simulation time 147085964 ps
CPU time 0.84 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:17 PM PDT 24
Peak memory 207044 kb
Host smart-91957cb8-1ef4-4c89-a866-a02052a0330f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21689
4082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.216894082
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1263783062
Short name T1097
Test name
Test status
Simulation time 267498869 ps
CPU time 1.01 seconds
Started Jul 28 07:41:13 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207084 kb
Host smart-6917038c-3924-4f67-becf-b110b705fe66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12637
83062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1263783062
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2460111331
Short name T798
Test name
Test status
Simulation time 191278887 ps
CPU time 0.92 seconds
Started Jul 28 07:41:11 PM PDT 24
Finished Jul 28 07:41:12 PM PDT 24
Peak memory 207132 kb
Host smart-1f8ceea1-e082-47c6-a4c0-17789422f1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24601
11331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2460111331
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.2017315022
Short name T1736
Test name
Test status
Simulation time 173821077 ps
CPU time 0.87 seconds
Started Jul 28 07:41:05 PM PDT 24
Finished Jul 28 07:41:06 PM PDT 24
Peak memory 207120 kb
Host smart-49e16df9-fc9e-4114-815a-476dcad260c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20173
15022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2017315022
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3066930314
Short name T1009
Test name
Test status
Simulation time 173374578 ps
CPU time 0.91 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:17 PM PDT 24
Peak memory 207032 kb
Host smart-06ecf083-5d05-4bba-abde-c18139714911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30669
30314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3066930314
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3710296341
Short name T1299
Test name
Test status
Simulation time 147763589 ps
CPU time 0.85 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:13 PM PDT 24
Peak memory 207136 kb
Host smart-4f28e86d-1050-4ec3-802b-44d05c63c0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37102
96341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3710296341
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1729082522
Short name T1983
Test name
Test status
Simulation time 160715530 ps
CPU time 0.9 seconds
Started Jul 28 07:41:14 PM PDT 24
Finished Jul 28 07:41:15 PM PDT 24
Peak memory 207112 kb
Host smart-2c43f0f8-e9f6-4519-8610-008936c8dcb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17290
82522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1729082522
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1024561773
Short name T1623
Test name
Test status
Simulation time 213107133 ps
CPU time 1.05 seconds
Started Jul 28 07:41:05 PM PDT 24
Finished Jul 28 07:41:07 PM PDT 24
Peak memory 207112 kb
Host smart-c899992b-4953-49bb-bf01-a70bde1050c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10245
61773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1024561773
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3333058862
Short name T1160
Test name
Test status
Simulation time 5562199662 ps
CPU time 168.89 seconds
Started Jul 28 07:41:11 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 215552 kb
Host smart-0b3e516e-58c7-4471-b826-7e6aac1faba5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3333058862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3333058862
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.571250587
Short name T1919
Test name
Test status
Simulation time 190656460 ps
CPU time 0.87 seconds
Started Jul 28 07:41:13 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207108 kb
Host smart-602bc4e5-4689-47f0-93c4-2fed8577d0d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57125
0587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.571250587
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2013956371
Short name T1145
Test name
Test status
Simulation time 205537850 ps
CPU time 0.9 seconds
Started Jul 28 07:41:09 PM PDT 24
Finished Jul 28 07:41:10 PM PDT 24
Peak memory 207128 kb
Host smart-319dc80f-bd23-4049-8b81-081278ee5fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20139
56371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2013956371
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.994965941
Short name T443
Test name
Test status
Simulation time 431984099 ps
CPU time 1.33 seconds
Started Jul 28 07:41:05 PM PDT 24
Finished Jul 28 07:41:07 PM PDT 24
Peak memory 207092 kb
Host smart-12f5d100-d1d8-488b-b7da-3f59fbf5234b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99496
5941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.994965941
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1047726729
Short name T1835
Test name
Test status
Simulation time 2939497264 ps
CPU time 85.13 seconds
Started Jul 28 07:41:14 PM PDT 24
Finished Jul 28 07:42:40 PM PDT 24
Peak memory 215540 kb
Host smart-6ed6606a-fa10-44db-9606-5394c1fe9cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10477
26729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1047726729
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.875760983
Short name T2023
Test name
Test status
Simulation time 841580657 ps
CPU time 5.51 seconds
Started Jul 28 07:41:05 PM PDT 24
Finished Jul 28 07:41:10 PM PDT 24
Peak memory 207344 kb
Host smart-075cdc35-d9e5-4d03-a130-b01f825a667a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875760983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_host
_handshake.875760983
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.1545091516
Short name T1514
Test name
Test status
Simulation time 46866245 ps
CPU time 0.67 seconds
Started Jul 28 07:41:13 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207184 kb
Host smart-ffcd3f66-dbcd-44a1-8b04-1631abf7dd9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1545091516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.1545091516
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1688038411
Short name T2521
Test name
Test status
Simulation time 23431335216 ps
CPU time 33.63 seconds
Started Jul 28 07:41:14 PM PDT 24
Finished Jul 28 07:41:48 PM PDT 24
Peak memory 207392 kb
Host smart-76ace6cc-b7b8-419d-88dc-ce32139a3702
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688038411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_resume.1688038411
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1969818235
Short name T1580
Test name
Test status
Simulation time 149004425 ps
CPU time 0.87 seconds
Started Jul 28 07:41:09 PM PDT 24
Finished Jul 28 07:41:10 PM PDT 24
Peak memory 207136 kb
Host smart-515b6bee-4c49-47de-a62b-709460e37485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19698
18235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1969818235
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.2712752455
Short name T887
Test name
Test status
Simulation time 161960124 ps
CPU time 0.85 seconds
Started Jul 28 07:41:10 PM PDT 24
Finished Jul 28 07:41:11 PM PDT 24
Peak memory 207088 kb
Host smart-f523562c-dc14-4a7c-a628-09e7332a2a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27127
52455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.2712752455
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.3546978630
Short name T1739
Test name
Test status
Simulation time 246607941 ps
CPU time 1.02 seconds
Started Jul 28 07:41:11 PM PDT 24
Finished Jul 28 07:41:12 PM PDT 24
Peak memory 207064 kb
Host smart-a0a2fdcf-efa8-4371-b211-5e4b121b09fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35469
78630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.3546978630
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3753196522
Short name T719
Test name
Test status
Simulation time 1091337691 ps
CPU time 2.61 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207280 kb
Host smart-3ae7ce0f-0e22-4367-9653-da25b441fcf7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3753196522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3753196522
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.1453677991
Short name T293
Test name
Test status
Simulation time 18608517408 ps
CPU time 38.4 seconds
Started Jul 28 07:41:21 PM PDT 24
Finished Jul 28 07:42:00 PM PDT 24
Peak memory 207436 kb
Host smart-5dbca0de-1b1c-40ce-b8d7-1bd1bc103c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14536
77991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.1453677991
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.3472794785
Short name T2226
Test name
Test status
Simulation time 4795832118 ps
CPU time 42.51 seconds
Started Jul 28 07:41:18 PM PDT 24
Finished Jul 28 07:42:01 PM PDT 24
Peak memory 207428 kb
Host smart-338452d8-6fcc-4665-8b84-796b6d13855c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472794785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.3472794785
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3713728148
Short name T2353
Test name
Test status
Simulation time 410528453 ps
CPU time 1.39 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:13 PM PDT 24
Peak memory 207108 kb
Host smart-7dfa6f9f-e965-4c34-8795-d7db0a86783a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37137
28148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3713728148
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.2095941949
Short name T2669
Test name
Test status
Simulation time 160652902 ps
CPU time 0.83 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:17 PM PDT 24
Peak memory 207012 kb
Host smart-0cf2400c-4c11-434d-912f-a1aa252f9e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20959
41949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.2095941949
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.3856473930
Short name T772
Test name
Test status
Simulation time 36215561 ps
CPU time 0.7 seconds
Started Jul 28 07:41:09 PM PDT 24
Finished Jul 28 07:41:10 PM PDT 24
Peak memory 206984 kb
Host smart-9c50ac61-6faf-46b0-b9fe-e992a8a12249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38564
73930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3856473930
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.896168372
Short name T548
Test name
Test status
Simulation time 848452685 ps
CPU time 2.32 seconds
Started Jul 28 07:41:15 PM PDT 24
Finished Jul 28 07:41:17 PM PDT 24
Peak memory 207388 kb
Host smart-4bc99a93-b6d8-4846-8a22-6458ce3c7668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89616
8372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.896168372
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2731879895
Short name T2264
Test name
Test status
Simulation time 300052073 ps
CPU time 2.28 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207316 kb
Host smart-7c1c7707-9bf8-4666-8cc0-e6d7c0e65b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27318
79895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2731879895
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3896985686
Short name T721
Test name
Test status
Simulation time 208945283 ps
CPU time 1.13 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:13 PM PDT 24
Peak memory 207320 kb
Host smart-b4229aa7-85cb-4313-9056-c58bf6549d3f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3896985686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3896985686
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.762718621
Short name T2418
Test name
Test status
Simulation time 150955085 ps
CPU time 0.82 seconds
Started Jul 28 07:41:15 PM PDT 24
Finished Jul 28 07:41:16 PM PDT 24
Peak memory 207172 kb
Host smart-750bf9a8-b8d0-40fc-91a3-2a19343f63c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76271
8621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.762718621
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3104843872
Short name T903
Test name
Test status
Simulation time 232861193 ps
CPU time 0.99 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:17 PM PDT 24
Peak memory 207156 kb
Host smart-30d25b0d-6c48-4a48-a183-4fe96f6086d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31048
43872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3104843872
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.3185954140
Short name T1181
Test name
Test status
Simulation time 8507677337 ps
CPU time 88.64 seconds
Started Jul 28 07:41:17 PM PDT 24
Finished Jul 28 07:42:46 PM PDT 24
Peak memory 217224 kb
Host smart-c890e697-dd5d-4ec8-919d-648c452e5420
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3185954140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.3185954140
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1376748960
Short name T422
Test name
Test status
Simulation time 246443806 ps
CPU time 1.01 seconds
Started Jul 28 07:41:17 PM PDT 24
Finished Jul 28 07:41:18 PM PDT 24
Peak memory 207104 kb
Host smart-ee6eb95d-5c54-44c3-a8b2-7f8492c50386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13767
48960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1376748960
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.2674406741
Short name T363
Test name
Test status
Simulation time 23301587281 ps
CPU time 31.96 seconds
Started Jul 28 07:41:20 PM PDT 24
Finished Jul 28 07:41:52 PM PDT 24
Peak memory 207412 kb
Host smart-eb901a09-00c1-4b0a-ae7f-dd85991b6f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26744
06741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.2674406741
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2015367149
Short name T1846
Test name
Test status
Simulation time 3314322971 ps
CPU time 6.09 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:19 PM PDT 24
Peak memory 207388 kb
Host smart-09c81087-4db5-4105-bbbe-81ccd4b39e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20153
67149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2015367149
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.2707203872
Short name T2791
Test name
Test status
Simulation time 9487674492 ps
CPU time 264.4 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:45:40 PM PDT 24
Peak memory 215484 kb
Host smart-ec5714a3-a908-4c62-959d-6aac0d66b944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27072
03872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.2707203872
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.3772549995
Short name T1628
Test name
Test status
Simulation time 4977719624 ps
CPU time 145.28 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:43:45 PM PDT 24
Peak memory 215620 kb
Host smart-9ffb9055-5427-469e-8ffb-3486ecbeb2fb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3772549995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.3772549995
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.1733902404
Short name T2423
Test name
Test status
Simulation time 239170284 ps
CPU time 1.05 seconds
Started Jul 28 07:41:13 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207148 kb
Host smart-4482ad37-aadf-4173-8bdb-e7ce591b3368
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1733902404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.1733902404
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1668806793
Short name T1354
Test name
Test status
Simulation time 217860482 ps
CPU time 1.09 seconds
Started Jul 28 07:41:14 PM PDT 24
Finished Jul 28 07:41:15 PM PDT 24
Peak memory 207064 kb
Host smart-4d8e0563-b131-4da9-b61f-4010b30bd5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16688
06793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1668806793
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2363984775
Short name T463
Test name
Test status
Simulation time 3736084089 ps
CPU time 27.95 seconds
Started Jul 28 07:41:13 PM PDT 24
Finished Jul 28 07:41:41 PM PDT 24
Peak memory 217088 kb
Host smart-d25442ee-f211-4544-a5aa-5b2c60ddbc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23639
84775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2363984775
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.3775885293
Short name T561
Test name
Test status
Simulation time 4085893820 ps
CPU time 41.3 seconds
Started Jul 28 07:41:17 PM PDT 24
Finished Jul 28 07:41:58 PM PDT 24
Peak memory 216652 kb
Host smart-88928f96-ff37-4295-95c4-eedc136f1d8e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3775885293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.3775885293
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.2166759639
Short name T532
Test name
Test status
Simulation time 149310312 ps
CPU time 0.88 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:17 PM PDT 24
Peak memory 207112 kb
Host smart-122f4420-8780-4782-abfb-2e349d807e68
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2166759639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.2166759639
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.50541840
Short name T2117
Test name
Test status
Simulation time 139095384 ps
CPU time 0.88 seconds
Started Jul 28 07:41:10 PM PDT 24
Finished Jul 28 07:41:11 PM PDT 24
Peak memory 207160 kb
Host smart-81e08bb0-ae6d-40b3-acf5-245fd1455162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50541
840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.50541840
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1320541950
Short name T2680
Test name
Test status
Simulation time 251808671 ps
CPU time 1.03 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:13 PM PDT 24
Peak memory 207140 kb
Host smart-b450fd5a-5ae0-48a7-8dc4-4c30f824d5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13205
41950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1320541950
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.1821008699
Short name T2551
Test name
Test status
Simulation time 226223353 ps
CPU time 1.01 seconds
Started Jul 28 07:41:11 PM PDT 24
Finished Jul 28 07:41:12 PM PDT 24
Peak memory 207112 kb
Host smart-afc1748d-38a8-44cc-ac43-69dbc57bd5d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18210
08699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.1821008699
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2608148675
Short name T1978
Test name
Test status
Simulation time 175328138 ps
CPU time 0.86 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:13 PM PDT 24
Peak memory 207092 kb
Host smart-5f92c456-82a9-4e80-86a8-d7c1cf5b360d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26081
48675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2608148675
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2069200080
Short name T666
Test name
Test status
Simulation time 178380585 ps
CPU time 0.96 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:13 PM PDT 24
Peak memory 207296 kb
Host smart-47d08575-635b-4910-997f-6a48048b2d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20692
00080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2069200080
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1455119211
Short name T1355
Test name
Test status
Simulation time 199339645 ps
CPU time 0.92 seconds
Started Jul 28 07:41:17 PM PDT 24
Finished Jul 28 07:41:18 PM PDT 24
Peak memory 207000 kb
Host smart-d6c7ef26-33b7-4f0e-8e7c-32785fca1827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14551
19211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1455119211
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.2993871276
Short name T2182
Test name
Test status
Simulation time 241175882 ps
CPU time 1.1 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207140 kb
Host smart-46af9b28-a900-4689-a8a2-759c93a82bdb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2993871276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.2993871276
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2204482161
Short name T1806
Test name
Test status
Simulation time 141986794 ps
CPU time 0.81 seconds
Started Jul 28 07:41:12 PM PDT 24
Finished Jul 28 07:41:13 PM PDT 24
Peak memory 207084 kb
Host smart-47c448ac-3798-4ef1-a1f8-c8d9f80c9f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22044
82161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2204482161
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1488085735
Short name T2388
Test name
Test status
Simulation time 38831579 ps
CPU time 0.7 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:17 PM PDT 24
Peak memory 207048 kb
Host smart-78a6005f-d157-4af4-acf7-ad9fac49f7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14880
85735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1488085735
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.580030575
Short name T1314
Test name
Test status
Simulation time 13521459941 ps
CPU time 33.45 seconds
Started Jul 28 07:41:10 PM PDT 24
Finished Jul 28 07:41:44 PM PDT 24
Peak memory 215688 kb
Host smart-6fb63fcf-ba70-440d-a775-7601bb8aa092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58003
0575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.580030575
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3676193870
Short name T2832
Test name
Test status
Simulation time 183339652 ps
CPU time 0.98 seconds
Started Jul 28 07:41:17 PM PDT 24
Finished Jul 28 07:41:18 PM PDT 24
Peak memory 207144 kb
Host smart-8077747f-8ea3-40ea-9583-35fa60adabee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36761
93870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3676193870
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.619708759
Short name T325
Test name
Test status
Simulation time 212444033 ps
CPU time 0.99 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:41:21 PM PDT 24
Peak memory 207100 kb
Host smart-928bb57d-9362-4d3c-a743-2dc894f872b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61970
8759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.619708759
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.1535131268
Short name T1474
Test name
Test status
Simulation time 227869162 ps
CPU time 1.02 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:18 PM PDT 24
Peak memory 207156 kb
Host smart-a3b39997-285d-4cdd-a994-3f6ebe5825ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15351
31268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.1535131268
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.201923337
Short name T1752
Test name
Test status
Simulation time 164947260 ps
CPU time 0.92 seconds
Started Jul 28 07:41:18 PM PDT 24
Finished Jul 28 07:41:19 PM PDT 24
Peak memory 207156 kb
Host smart-9f5b1947-841b-4ca9-a0a5-7290e5f6c57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20192
3337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.201923337
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1627681511
Short name T1055
Test name
Test status
Simulation time 152621017 ps
CPU time 0.83 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:41:20 PM PDT 24
Peak memory 207072 kb
Host smart-5f97ec83-7561-473c-b56d-0ab2f929769d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16276
81511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1627681511
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3360263157
Short name T642
Test name
Test status
Simulation time 153266934 ps
CPU time 0.92 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:41:21 PM PDT 24
Peak memory 207176 kb
Host smart-79e9b618-f4c4-4706-a5e8-bf9117f20886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33602
63157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3360263157
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.4026037357
Short name T869
Test name
Test status
Simulation time 184902714 ps
CPU time 1 seconds
Started Jul 28 07:41:18 PM PDT 24
Finished Jul 28 07:41:19 PM PDT 24
Peak memory 207164 kb
Host smart-b8f7692c-e2e8-41a5-bef9-7731efaf4f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40260
37357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.4026037357
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3978501942
Short name T2221
Test name
Test status
Simulation time 298530680 ps
CPU time 1.1 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:41:20 PM PDT 24
Peak memory 207040 kb
Host smart-acc4ce43-406a-4c0e-a4b1-582314bdf8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39785
01942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3978501942
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2533652120
Short name T2611
Test name
Test status
Simulation time 3787364640 ps
CPU time 29.97 seconds
Started Jul 28 07:41:13 PM PDT 24
Finished Jul 28 07:41:43 PM PDT 24
Peak memory 215756 kb
Host smart-a8ba6efd-4ace-4a3b-88fd-5da0b3743722
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2533652120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2533652120
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1533994385
Short name T1970
Test name
Test status
Simulation time 155033662 ps
CPU time 0.93 seconds
Started Jul 28 07:41:15 PM PDT 24
Finished Jul 28 07:41:16 PM PDT 24
Peak memory 207088 kb
Host smart-a0aab658-5dc0-47aa-a745-bfe243661c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15339
94385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1533994385
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3348951818
Short name T971
Test name
Test status
Simulation time 177288916 ps
CPU time 0.93 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:41:20 PM PDT 24
Peak memory 207104 kb
Host smart-2e5112c5-a99c-4443-81fd-746b9d33e3dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33489
51818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3348951818
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.923102024
Short name T1311
Test name
Test status
Simulation time 406315072 ps
CPU time 1.25 seconds
Started Jul 28 07:41:17 PM PDT 24
Finished Jul 28 07:41:18 PM PDT 24
Peak memory 207088 kb
Host smart-e8f7e95b-bf08-4664-ba6a-a9431c2a7947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92310
2024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.923102024
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.583714267
Short name T2077
Test name
Test status
Simulation time 3347778436 ps
CPU time 98.66 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:42:58 PM PDT 24
Peak memory 215504 kb
Host smart-8d066e1f-81b7-4b64-be37-c272d37dd61a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58371
4267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.583714267
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.3294283384
Short name T1220
Test name
Test status
Simulation time 188703532 ps
CPU time 0.88 seconds
Started Jul 28 07:41:09 PM PDT 24
Finished Jul 28 07:41:10 PM PDT 24
Peak memory 207132 kb
Host smart-138131dd-66a2-44b6-b936-dda3e2674c92
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294283384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.3294283384
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.2107576980
Short name T890
Test name
Test status
Simulation time 42787690 ps
CPU time 0.69 seconds
Started Jul 28 07:38:30 PM PDT 24
Finished Jul 28 07:38:31 PM PDT 24
Peak memory 207156 kb
Host smart-36f47a2c-2eb8-42cd-bf39-942c251b5439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2107576980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.2107576980
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.3420692597
Short name T1509
Test name
Test status
Simulation time 3673835442 ps
CPU time 5.46 seconds
Started Jul 28 07:38:19 PM PDT 24
Finished Jul 28 07:38:25 PM PDT 24
Peak memory 207312 kb
Host smart-9da97e86-ede2-41b5-80bf-ed19d5c2b52d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420692597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.3420692597
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1939859085
Short name T14
Test name
Test status
Simulation time 13578145162 ps
CPU time 16.74 seconds
Started Jul 28 07:38:20 PM PDT 24
Finished Jul 28 07:38:37 PM PDT 24
Peak memory 207408 kb
Host smart-d1ec5ae6-1b46-4cdc-98ec-cc5f4e9faacc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939859085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1939859085
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1164542404
Short name T529
Test name
Test status
Simulation time 23370142702 ps
CPU time 31.28 seconds
Started Jul 28 07:38:14 PM PDT 24
Finished Jul 28 07:38:45 PM PDT 24
Peak memory 207352 kb
Host smart-166bb993-1d82-4e36-8c42-266d13bd86f9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164542404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.1164542404
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3813602617
Short name T1597
Test name
Test status
Simulation time 164196307 ps
CPU time 0.85 seconds
Started Jul 28 07:38:17 PM PDT 24
Finished Jul 28 07:38:18 PM PDT 24
Peak memory 207044 kb
Host smart-6d66f228-bea6-4728-ad37-50a43711694b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38136
02617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3813602617
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.2626051664
Short name T56
Test name
Test status
Simulation time 156857955 ps
CPU time 0.85 seconds
Started Jul 28 07:38:25 PM PDT 24
Finished Jul 28 07:38:26 PM PDT 24
Peak memory 207156 kb
Host smart-775887b7-67f3-4c72-9f85-59bd53373af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26260
51664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.2626051664
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1092285158
Short name T1066
Test name
Test status
Simulation time 153256915 ps
CPU time 0.84 seconds
Started Jul 28 07:38:17 PM PDT 24
Finished Jul 28 07:38:18 PM PDT 24
Peak memory 207108 kb
Host smart-18bc0923-67a0-4eb3-bdfb-5db3c856b156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10922
85158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1092285158
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.21570863
Short name T1683
Test name
Test status
Simulation time 162338639 ps
CPU time 0.83 seconds
Started Jul 28 07:38:14 PM PDT 24
Finished Jul 28 07:38:15 PM PDT 24
Peak memory 207096 kb
Host smart-301545fd-d695-4913-b819-85abfe256eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21570
863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.21570863
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.2882298840
Short name T2726
Test name
Test status
Simulation time 950592448 ps
CPU time 2.53 seconds
Started Jul 28 07:38:16 PM PDT 24
Finished Jul 28 07:38:18 PM PDT 24
Peak memory 207296 kb
Host smart-e526e1cd-f062-4db5-b9e8-197d9e721839
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2882298840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.2882298840
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.2517711410
Short name T980
Test name
Test status
Simulation time 16111327414 ps
CPU time 36.35 seconds
Started Jul 28 07:38:19 PM PDT 24
Finished Jul 28 07:38:56 PM PDT 24
Peak memory 207380 kb
Host smart-4a98d023-3a8e-4771-ae57-6ccd3195a0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25177
11410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.2517711410
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.2277500818
Short name T1270
Test name
Test status
Simulation time 2016406400 ps
CPU time 17.87 seconds
Started Jul 28 07:38:36 PM PDT 24
Finished Jul 28 07:38:54 PM PDT 24
Peak memory 207276 kb
Host smart-5d4f2a8a-c18f-404b-8040-5d415683cb4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277500818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.2277500818
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.1027745242
Short name T2808
Test name
Test status
Simulation time 355053404 ps
CPU time 1.29 seconds
Started Jul 28 07:38:35 PM PDT 24
Finished Jul 28 07:38:36 PM PDT 24
Peak memory 207072 kb
Host smart-ad5604c7-e27e-4732-a77d-0e0f32217bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10277
45242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.1027745242
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.16202918
Short name T785
Test name
Test status
Simulation time 173621342 ps
CPU time 0.81 seconds
Started Jul 28 07:38:31 PM PDT 24
Finished Jul 28 07:38:32 PM PDT 24
Peak memory 207128 kb
Host smart-d859940c-0886-4c2f-8e99-dbad795569ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16202
918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.16202918
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.53743382
Short name T2435
Test name
Test status
Simulation time 33952337 ps
CPU time 0.74 seconds
Started Jul 28 07:38:19 PM PDT 24
Finished Jul 28 07:38:20 PM PDT 24
Peak memory 207012 kb
Host smart-ce0de4a9-bdc1-4983-a302-b2dac6697c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53743
382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.53743382
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.2574452106
Short name T2197
Test name
Test status
Simulation time 1031733551 ps
CPU time 2.54 seconds
Started Jul 28 07:38:21 PM PDT 24
Finished Jul 28 07:38:23 PM PDT 24
Peak memory 207348 kb
Host smart-192f0eb7-3475-4c17-946a-81ca480f61e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25744
52106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2574452106
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.206710242
Short name T518
Test name
Test status
Simulation time 207635154 ps
CPU time 2.07 seconds
Started Jul 28 07:38:34 PM PDT 24
Finished Jul 28 07:38:36 PM PDT 24
Peak memory 207180 kb
Host smart-4af85e82-a33a-4c44-9644-372edea25c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20671
0242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.206710242
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1855904588
Short name T1504
Test name
Test status
Simulation time 93212483258 ps
CPU time 144.92 seconds
Started Jul 28 07:38:20 PM PDT 24
Finished Jul 28 07:40:45 PM PDT 24
Peak memory 207368 kb
Host smart-5f190bce-b921-41f4-aa25-098d39cef1a7
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1855904588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1855904588
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.593804637
Short name T2039
Test name
Test status
Simulation time 101105122744 ps
CPU time 150.1 seconds
Started Jul 28 07:38:42 PM PDT 24
Finished Jul 28 07:41:12 PM PDT 24
Peak memory 207432 kb
Host smart-12d97c87-220a-4c75-a401-df1cbd96b5af
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=593804637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.593804637
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.2110382472
Short name T1431
Test name
Test status
Simulation time 87180695324 ps
CPU time 139.77 seconds
Started Jul 28 07:38:25 PM PDT 24
Finished Jul 28 07:40:45 PM PDT 24
Peak memory 207320 kb
Host smart-a71abd32-48ba-4e54-a867-c438c8238b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110382472 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.2110382472
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.3631471521
Short name T931
Test name
Test status
Simulation time 94173569433 ps
CPU time 149.89 seconds
Started Jul 28 07:38:34 PM PDT 24
Finished Jul 28 07:41:04 PM PDT 24
Peak memory 207384 kb
Host smart-52327d83-5f7e-4095-9a7a-69845da73599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36314
71521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3631471521
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3858903691
Short name T1876
Test name
Test status
Simulation time 206010012 ps
CPU time 1.02 seconds
Started Jul 28 07:38:19 PM PDT 24
Finished Jul 28 07:38:20 PM PDT 24
Peak memory 207236 kb
Host smart-eb41e6f7-45ed-4e1b-9e52-fdbb4ddd783a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3858903691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3858903691
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.621361204
Short name T1207
Test name
Test status
Simulation time 198763370 ps
CPU time 0.89 seconds
Started Jul 28 07:38:31 PM PDT 24
Finished Jul 28 07:38:32 PM PDT 24
Peak memory 207068 kb
Host smart-cc817199-310b-4cc9-936e-0b291637e3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62136
1204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.621361204
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3944968417
Short name T2361
Test name
Test status
Simulation time 242235000 ps
CPU time 1 seconds
Started Jul 28 07:38:20 PM PDT 24
Finished Jul 28 07:38:21 PM PDT 24
Peak memory 207140 kb
Host smart-8a301a70-9602-4644-8b79-1a10aaa39567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39449
68417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3944968417
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.1320844760
Short name T1521
Test name
Test status
Simulation time 5369463444 ps
CPU time 44.53 seconds
Started Jul 28 07:38:15 PM PDT 24
Finished Jul 28 07:39:00 PM PDT 24
Peak memory 215588 kb
Host smart-258c059f-f9f4-44ba-be75-5c30c35a05bf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1320844760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.1320844760
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.3452111345
Short name T1456
Test name
Test status
Simulation time 12111148229 ps
CPU time 86.41 seconds
Started Jul 28 07:38:19 PM PDT 24
Finished Jul 28 07:39:45 PM PDT 24
Peak memory 207356 kb
Host smart-dcc175ff-884a-4f06-aa61-4c75307baa67
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3452111345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.3452111345
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2547913317
Short name T449
Test name
Test status
Simulation time 263392162 ps
CPU time 0.98 seconds
Started Jul 28 07:38:34 PM PDT 24
Finished Jul 28 07:38:35 PM PDT 24
Peak memory 207028 kb
Host smart-90c8f807-8d47-4bc1-8071-3ba0ffdce33f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25479
13317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2547913317
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.3665248981
Short name T2366
Test name
Test status
Simulation time 23325732325 ps
CPU time 30.97 seconds
Started Jul 28 07:38:26 PM PDT 24
Finished Jul 28 07:38:57 PM PDT 24
Peak memory 207400 kb
Host smart-7668ffa0-7bb7-4b56-a357-2b27a9641ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36652
48981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.3665248981
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.2816190982
Short name T1715
Test name
Test status
Simulation time 3275692942 ps
CPU time 4.86 seconds
Started Jul 28 07:38:31 PM PDT 24
Finished Jul 28 07:38:36 PM PDT 24
Peak memory 207408 kb
Host smart-a5cb5934-5707-48da-91b5-dad62330168e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28161
90982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2816190982
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.1543621415
Short name T1649
Test name
Test status
Simulation time 9968031073 ps
CPU time 72.55 seconds
Started Jul 28 07:38:20 PM PDT 24
Finished Jul 28 07:39:32 PM PDT 24
Peak memory 217508 kb
Host smart-14fbad1f-500e-4229-86e0-d487080a0a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15436
21415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.1543621415
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3809707926
Short name T1918
Test name
Test status
Simulation time 5281672836 ps
CPU time 41.7 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:39:19 PM PDT 24
Peak memory 216952 kb
Host smart-fd3b5854-ba42-4cf7-a517-a08266290ce0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3809707926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3809707926
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.4164637155
Short name T379
Test name
Test status
Simulation time 253061368 ps
CPU time 0.97 seconds
Started Jul 28 07:38:24 PM PDT 24
Finished Jul 28 07:38:25 PM PDT 24
Peak memory 207076 kb
Host smart-ac706f91-d98f-4ed8-8bb5-bdafb75754e6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4164637155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.4164637155
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.851523807
Short name T2737
Test name
Test status
Simulation time 192708993 ps
CPU time 0.94 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 207168 kb
Host smart-c86e3ee0-aa88-4cef-a666-80792695cc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85152
3807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.851523807
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.3767440053
Short name T569
Test name
Test status
Simulation time 6080607087 ps
CPU time 185.6 seconds
Started Jul 28 07:38:33 PM PDT 24
Finished Jul 28 07:41:38 PM PDT 24
Peak memory 215600 kb
Host smart-ed1a807c-c6da-4b19-bfac-8e55e62e0b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37674
40053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.3767440053
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1721574679
Short name T745
Test name
Test status
Simulation time 5520697482 ps
CPU time 162.61 seconds
Started Jul 28 07:38:20 PM PDT 24
Finished Jul 28 07:41:03 PM PDT 24
Peak memory 215568 kb
Host smart-cfe2d3e8-9423-4860-b9d6-1d6b6d5d32f0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1721574679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1721574679
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1341142726
Short name T1353
Test name
Test status
Simulation time 153401501 ps
CPU time 0.84 seconds
Started Jul 28 07:38:19 PM PDT 24
Finished Jul 28 07:38:20 PM PDT 24
Peak memory 207144 kb
Host smart-f4839cec-e3cb-48b5-a621-6c5753245740
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1341142726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1341142726
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1274703903
Short name T508
Test name
Test status
Simulation time 157603368 ps
CPU time 0.93 seconds
Started Jul 28 07:38:34 PM PDT 24
Finished Jul 28 07:38:35 PM PDT 24
Peak memory 207024 kb
Host smart-963786a1-fedd-4998-af20-5e5a3bd6c1f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12747
03903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1274703903
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1145941928
Short name T1206
Test name
Test status
Simulation time 157379867 ps
CPU time 0.87 seconds
Started Jul 28 07:38:18 PM PDT 24
Finished Jul 28 07:38:19 PM PDT 24
Peak memory 207136 kb
Host smart-66e1d3dc-d7cc-4c30-9809-6cd61ceef2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11459
41928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1145941928
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3333657517
Short name T2291
Test name
Test status
Simulation time 180015171 ps
CPU time 0.95 seconds
Started Jul 28 07:38:36 PM PDT 24
Finished Jul 28 07:38:37 PM PDT 24
Peak memory 207152 kb
Host smart-ff32a245-a326-4680-b21a-df75ea3e6769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33336
57517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3333657517
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2627308000
Short name T1275
Test name
Test status
Simulation time 175610436 ps
CPU time 0.86 seconds
Started Jul 28 07:38:32 PM PDT 24
Finished Jul 28 07:38:33 PM PDT 24
Peak memory 207204 kb
Host smart-022b7821-d31d-4b92-a014-47f34dfec520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26273
08000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2627308000
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2388065990
Short name T176
Test name
Test status
Simulation time 179242978 ps
CPU time 0.84 seconds
Started Jul 28 07:38:18 PM PDT 24
Finished Jul 28 07:38:19 PM PDT 24
Peak memory 207080 kb
Host smart-032b5f3b-baa4-4530-80ec-3455a31cb7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23880
65990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2388065990
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.1035393340
Short name T492
Test name
Test status
Simulation time 248734390 ps
CPU time 1.06 seconds
Started Jul 28 07:38:36 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 207168 kb
Host smart-b9eb0ee2-de51-4a59-96a1-038f41592b1b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1035393340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.1035393340
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.3268035601
Short name T1745
Test name
Test status
Simulation time 233635563 ps
CPU time 0.98 seconds
Started Jul 28 07:38:31 PM PDT 24
Finished Jul 28 07:38:32 PM PDT 24
Peak memory 207024 kb
Host smart-ea71aea7-7333-4e23-94c3-035a822e526b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32680
35601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.3268035601
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3859620514
Short name T813
Test name
Test status
Simulation time 138227499 ps
CPU time 0.89 seconds
Started Jul 28 07:38:34 PM PDT 24
Finished Jul 28 07:38:35 PM PDT 24
Peak memory 206992 kb
Host smart-cbfb5248-b045-4656-86ab-795936572b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38596
20514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3859620514
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3968715266
Short name T1491
Test name
Test status
Simulation time 36650434 ps
CPU time 0.71 seconds
Started Jul 28 07:38:17 PM PDT 24
Finished Jul 28 07:38:18 PM PDT 24
Peak memory 207288 kb
Host smart-0b7cca25-81a9-46b2-8439-06669c629b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39687
15266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3968715266
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.864785341
Short name T1101
Test name
Test status
Simulation time 15925148861 ps
CPU time 38.94 seconds
Started Jul 28 07:38:31 PM PDT 24
Finished Jul 28 07:39:10 PM PDT 24
Peak memory 215544 kb
Host smart-3b1a8038-0922-45cd-abbc-be83c1a578f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86478
5341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.864785341
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3481217842
Short name T795
Test name
Test status
Simulation time 194968344 ps
CPU time 0.99 seconds
Started Jul 28 07:38:32 PM PDT 24
Finished Jul 28 07:38:33 PM PDT 24
Peak memory 207160 kb
Host smart-2830a399-ddea-40a4-b091-eba8a87ae22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34812
17842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3481217842
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3434729724
Short name T2384
Test name
Test status
Simulation time 181185005 ps
CPU time 0.9 seconds
Started Jul 28 07:38:33 PM PDT 24
Finished Jul 28 07:38:34 PM PDT 24
Peak memory 207048 kb
Host smart-9c7a3642-87a2-4fb3-93b0-6411a875a719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34347
29724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3434729724
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.1153582809
Short name T364
Test name
Test status
Simulation time 13283104085 ps
CPU time 97.45 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:40:16 PM PDT 24
Peak memory 217492 kb
Host smart-90bf0351-0dc4-45aa-a696-d86b0d981580
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153582809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.1153582809
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3439118049
Short name T1060
Test name
Test status
Simulation time 10151077146 ps
CPU time 194.73 seconds
Started Jul 28 07:38:36 PM PDT 24
Finished Jul 28 07:41:51 PM PDT 24
Peak memory 215512 kb
Host smart-55e8bcff-f30f-4803-8a0e-12a5f2e05316
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439118049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3439118049
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3793302803
Short name T2229
Test name
Test status
Simulation time 223043881 ps
CPU time 0.95 seconds
Started Jul 28 07:38:40 PM PDT 24
Finished Jul 28 07:38:41 PM PDT 24
Peak memory 207128 kb
Host smart-b066c0ca-2b8f-418c-b71e-c3190a3b0b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37933
02803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3793302803
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.2646243169
Short name T2307
Test name
Test status
Simulation time 161170246 ps
CPU time 0.89 seconds
Started Jul 28 07:38:31 PM PDT 24
Finished Jul 28 07:38:32 PM PDT 24
Peak memory 207164 kb
Host smart-3fa618bf-4659-4d7b-b970-c28c9472433c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26462
43169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.2646243169
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3061444607
Short name T1849
Test name
Test status
Simulation time 161239728 ps
CPU time 0.91 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:38:39 PM PDT 24
Peak memory 207148 kb
Host smart-f3c7da6b-0706-4ddc-8030-6e3f2e4535a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30614
44607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3061444607
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.445758595
Short name T75
Test name
Test status
Simulation time 169148868 ps
CPU time 0.86 seconds
Started Jul 28 07:38:31 PM PDT 24
Finished Jul 28 07:38:32 PM PDT 24
Peak memory 207116 kb
Host smart-595a6311-9d92-417e-8c5e-73030f93e96c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44575
8595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.445758595
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.2201784945
Short name T2571
Test name
Test status
Simulation time 430132459 ps
CPU time 1.35 seconds
Started Jul 28 07:38:24 PM PDT 24
Finished Jul 28 07:38:25 PM PDT 24
Peak memory 207100 kb
Host smart-f8c22795-6b62-4083-87b8-4571330fc81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22017
84945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.2201784945
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.4150860508
Short name T1100
Test name
Test status
Simulation time 231436594 ps
CPU time 0.99 seconds
Started Jul 28 07:38:26 PM PDT 24
Finished Jul 28 07:38:27 PM PDT 24
Peak memory 207112 kb
Host smart-7dbc8c8c-7764-458b-8024-a625c27d827f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41508
60508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.4150860508
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.4197460573
Short name T1001
Test name
Test status
Simulation time 146948819 ps
CPU time 0.81 seconds
Started Jul 28 07:38:27 PM PDT 24
Finished Jul 28 07:38:28 PM PDT 24
Peak memory 207076 kb
Host smart-117d0a2d-ad11-4a39-aa69-cd05c589ed65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41974
60573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.4197460573
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.1176153386
Short name T1553
Test name
Test status
Simulation time 149375270 ps
CPU time 0.83 seconds
Started Jul 28 07:38:36 PM PDT 24
Finished Jul 28 07:38:37 PM PDT 24
Peak memory 207088 kb
Host smart-4b807b15-5730-467c-88cb-f47c4664d8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11761
53386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.1176153386
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.4245615739
Short name T441
Test name
Test status
Simulation time 218414202 ps
CPU time 1.08 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:38:39 PM PDT 24
Peak memory 207140 kb
Host smart-db23c9b1-6fe8-488c-a63d-39f0265bb7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42456
15739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.4245615739
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.3924601298
Short name T1200
Test name
Test status
Simulation time 4792869511 ps
CPU time 47.13 seconds
Started Jul 28 07:38:39 PM PDT 24
Finished Jul 28 07:39:27 PM PDT 24
Peak memory 215572 kb
Host smart-92b0955e-9e77-49b5-86aa-604659e45717
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3924601298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.3924601298
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.829571108
Short name T1574
Test name
Test status
Simulation time 154272833 ps
CPU time 0.86 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:37 PM PDT 24
Peak memory 207100 kb
Host smart-b834fdaf-39eb-4c53-9ae2-9b431989c6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82957
1108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.829571108
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2993740490
Short name T1416
Test name
Test status
Simulation time 177298970 ps
CPU time 0.91 seconds
Started Jul 28 07:38:34 PM PDT 24
Finished Jul 28 07:38:35 PM PDT 24
Peak memory 207128 kb
Host smart-7ac7d7ac-3c70-4163-932b-12c1aec2eacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29937
40490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2993740490
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.4040463055
Short name T1026
Test name
Test status
Simulation time 318743434 ps
CPU time 1.12 seconds
Started Jul 28 07:38:27 PM PDT 24
Finished Jul 28 07:38:28 PM PDT 24
Peak memory 207080 kb
Host smart-8be3fafc-5fc7-4676-bc93-dc6ae94e1fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40404
63055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.4040463055
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2904714842
Short name T1473
Test name
Test status
Simulation time 5050860350 ps
CPU time 140.91 seconds
Started Jul 28 07:38:25 PM PDT 24
Finished Jul 28 07:40:46 PM PDT 24
Peak memory 215576 kb
Host smart-e97f2de1-98ad-4eb1-8f63-2c1396f7a70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29047
14842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2904714842
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.1793067093
Short name T76
Test name
Test status
Simulation time 10351329170 ps
CPU time 55.05 seconds
Started Jul 28 07:38:25 PM PDT 24
Finished Jul 28 07:39:20 PM PDT 24
Peak memory 223764 kb
Host smart-226c1ff2-f114-4a92-a710-31bd3a045972
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793067093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.1793067093
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.1716968958
Short name T1921
Test name
Test status
Simulation time 1156182108 ps
CPU time 24.44 seconds
Started Jul 28 07:38:20 PM PDT 24
Finished Jul 28 07:38:44 PM PDT 24
Peak memory 207404 kb
Host smart-68c3b898-e9af-4d44-88f3-28662fdc1f49
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716968958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host
_handshake.1716968958
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3934881298
Short name T1826
Test name
Test status
Simulation time 46665889 ps
CPU time 0.65 seconds
Started Jul 28 07:41:26 PM PDT 24
Finished Jul 28 07:41:27 PM PDT 24
Peak memory 207152 kb
Host smart-280d6bc1-48f4-4727-9667-019a8635df6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3934881298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3934881298
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2416485625
Short name T685
Test name
Test status
Simulation time 4165671181 ps
CPU time 6.11 seconds
Started Jul 28 07:41:18 PM PDT 24
Finished Jul 28 07:41:24 PM PDT 24
Peak memory 207360 kb
Host smart-0dd1f00b-f0e3-41be-a658-94bbaa5eb7c5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416485625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_disconnect.2416485625
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1476524883
Short name T988
Test name
Test status
Simulation time 13494450956 ps
CPU time 16.19 seconds
Started Jul 28 07:41:21 PM PDT 24
Finished Jul 28 07:41:38 PM PDT 24
Peak memory 207444 kb
Host smart-77062d0a-9506-4ebe-a8a0-f1f643fac2c1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476524883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1476524883
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.4022510256
Short name T2002
Test name
Test status
Simulation time 23420791997 ps
CPU time 28.27 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:45 PM PDT 24
Peak memory 207420 kb
Host smart-9352ca54-8961-4f74-a14e-c85fd0f982ae
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022510256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.4022510256
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3027892211
Short name T2811
Test name
Test status
Simulation time 152303008 ps
CPU time 0.81 seconds
Started Jul 28 07:41:22 PM PDT 24
Finished Jul 28 07:41:23 PM PDT 24
Peak memory 207044 kb
Host smart-78cc5473-e42c-4abd-8f57-2b51ae2d5f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30278
92211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3027892211
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.2123893848
Short name T2543
Test name
Test status
Simulation time 215248186 ps
CPU time 0.89 seconds
Started Jul 28 07:41:15 PM PDT 24
Finished Jul 28 07:41:16 PM PDT 24
Peak memory 207104 kb
Host smart-16d75100-253d-47d4-b6ad-af0c15da9798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21238
93848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.2123893848
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.4062218080
Short name T725
Test name
Test status
Simulation time 283408167 ps
CPU time 1.21 seconds
Started Jul 28 07:41:14 PM PDT 24
Finished Jul 28 07:41:15 PM PDT 24
Peak memory 207160 kb
Host smart-28dd0180-61b5-4a60-b359-1b8c625f3fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40622
18080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.4062218080
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.4077344177
Short name T2518
Test name
Test status
Simulation time 656953474 ps
CPU time 1.82 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:18 PM PDT 24
Peak memory 207108 kb
Host smart-74a1b8c7-4bef-4dc0-a499-cabcd6bf9966
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4077344177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.4077344177
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.62687165
Short name T1539
Test name
Test status
Simulation time 8176719818 ps
CPU time 17.29 seconds
Started Jul 28 07:41:15 PM PDT 24
Finished Jul 28 07:41:32 PM PDT 24
Peak memory 207372 kb
Host smart-97a2af43-0b2c-4b2a-8f2c-fc8825667f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62687
165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.62687165
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.4252123050
Short name T2654
Test name
Test status
Simulation time 452224310 ps
CPU time 7.89 seconds
Started Jul 28 07:41:14 PM PDT 24
Finished Jul 28 07:41:22 PM PDT 24
Peak memory 207276 kb
Host smart-e57d82b6-24b6-41d0-bb46-472b7af98614
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252123050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.4252123050
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.4026421874
Short name T1434
Test name
Test status
Simulation time 426921728 ps
CPU time 1.49 seconds
Started Jul 28 07:41:18 PM PDT 24
Finished Jul 28 07:41:20 PM PDT 24
Peak memory 207048 kb
Host smart-19264de6-e673-4697-9488-20a9d78d19a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40264
21874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.4026421874
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.698867804
Short name T410
Test name
Test status
Simulation time 146258343 ps
CPU time 0.85 seconds
Started Jul 28 07:41:14 PM PDT 24
Finished Jul 28 07:41:15 PM PDT 24
Peak memory 207092 kb
Host smart-d66e1a02-caa2-4115-80f4-3989866f1a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69886
7804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.698867804
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1548960879
Short name T1139
Test name
Test status
Simulation time 105901224 ps
CPU time 0.76 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:17 PM PDT 24
Peak memory 207116 kb
Host smart-dc69e94e-5622-41d9-b639-0e2598228c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15489
60879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1548960879
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3328468826
Short name T617
Test name
Test status
Simulation time 928134782 ps
CPU time 2.71 seconds
Started Jul 28 07:41:15 PM PDT 24
Finished Jul 28 07:41:18 PM PDT 24
Peak memory 207364 kb
Host smart-53ad4247-51fe-43b3-9efa-82e99bec4d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33284
68826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3328468826
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.877639066
Short name T2155
Test name
Test status
Simulation time 151214268 ps
CPU time 1.35 seconds
Started Jul 28 07:41:14 PM PDT 24
Finished Jul 28 07:41:15 PM PDT 24
Peak memory 207260 kb
Host smart-26e686ef-901d-464f-931f-9ded726e51c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87763
9066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.877639066
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2108746265
Short name T1700
Test name
Test status
Simulation time 210535129 ps
CPU time 1.07 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:17 PM PDT 24
Peak memory 215516 kb
Host smart-77be315c-91e9-401d-b46d-3ec2bb98a9b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2108746265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2108746265
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3169943542
Short name T1313
Test name
Test status
Simulation time 151419892 ps
CPU time 0.85 seconds
Started Jul 28 07:41:15 PM PDT 24
Finished Jul 28 07:41:16 PM PDT 24
Peak memory 207152 kb
Host smart-6c3261cf-a560-4fcb-add1-f23fe64947c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31699
43542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3169943542
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.863230232
Short name T2383
Test name
Test status
Simulation time 236609778 ps
CPU time 1.06 seconds
Started Jul 28 07:41:17 PM PDT 24
Finished Jul 28 07:41:18 PM PDT 24
Peak memory 207156 kb
Host smart-6ccd5500-ca71-4877-b1af-3571d04f6d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86323
0232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.863230232
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.348859121
Short name T1828
Test name
Test status
Simulation time 5801110011 ps
CPU time 61.3 seconds
Started Jul 28 07:41:14 PM PDT 24
Finished Jul 28 07:42:16 PM PDT 24
Peak memory 215556 kb
Host smart-9b8a45ac-cbc3-4fab-803a-d0ecad87ec4f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=348859121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.348859121
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.2790302210
Short name T2171
Test name
Test status
Simulation time 8421245632 ps
CPU time 108.83 seconds
Started Jul 28 07:41:21 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 207384 kb
Host smart-6b8fcd3e-3272-4eb9-aac6-65822676a562
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2790302210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.2790302210
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.2352305202
Short name T1468
Test name
Test status
Simulation time 201239317 ps
CPU time 0.94 seconds
Started Jul 28 07:41:17 PM PDT 24
Finished Jul 28 07:41:18 PM PDT 24
Peak memory 207112 kb
Host smart-6ae9a006-b953-4a8a-a2fd-2f38d8b42f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23523
05202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.2352305202
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.1362559231
Short name T1716
Test name
Test status
Simulation time 23361380652 ps
CPU time 28.53 seconds
Started Jul 28 07:41:15 PM PDT 24
Finished Jul 28 07:41:44 PM PDT 24
Peak memory 207368 kb
Host smart-0a14406a-a7f9-4da4-915d-abce23d88b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13625
59231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.1362559231
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2060591633
Short name T320
Test name
Test status
Simulation time 3266298126 ps
CPU time 5.13 seconds
Started Jul 28 07:41:17 PM PDT 24
Finished Jul 28 07:41:23 PM PDT 24
Peak memory 207364 kb
Host smart-5677bd4b-3c8c-4e76-8a33-50fb63713355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20605
91633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2060591633
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.896816674
Short name T2437
Test name
Test status
Simulation time 5710530539 ps
CPU time 54.67 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:42:18 PM PDT 24
Peak memory 217412 kb
Host smart-7c5890a8-5c98-4c8b-9802-4c2abebb67d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89681
6674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.896816674
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.3544732972
Short name T819
Test name
Test status
Simulation time 3074682365 ps
CPU time 30.38 seconds
Started Jul 28 07:41:16 PM PDT 24
Finished Jul 28 07:41:46 PM PDT 24
Peak memory 217072 kb
Host smart-750b48fd-2957-4c4e-91d0-33b7347002f0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3544732972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.3544732972
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.576886754
Short name T2788
Test name
Test status
Simulation time 255466831 ps
CPU time 1.05 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:41:21 PM PDT 24
Peak memory 207052 kb
Host smart-6c97ac57-7d26-4ef6-a4e3-b215d88f96ea
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=576886754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.576886754
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1292739716
Short name T504
Test name
Test status
Simulation time 189700153 ps
CPU time 0.94 seconds
Started Jul 28 07:41:17 PM PDT 24
Finished Jul 28 07:41:18 PM PDT 24
Peak memory 207112 kb
Host smart-89219e89-c513-4294-a303-b58cc18e604a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12927
39716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1292739716
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3914529697
Short name T2314
Test name
Test status
Simulation time 5673443472 ps
CPU time 56.53 seconds
Started Jul 28 07:41:22 PM PDT 24
Finished Jul 28 07:42:18 PM PDT 24
Peak memory 217060 kb
Host smart-bc59433f-18ce-42c8-87b5-45c049b200a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39145
29697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3914529697
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.544183763
Short name T412
Test name
Test status
Simulation time 5617237958 ps
CPU time 46.12 seconds
Started Jul 28 07:41:15 PM PDT 24
Finished Jul 28 07:42:02 PM PDT 24
Peak memory 216944 kb
Host smart-7f9a4f18-7677-46fd-917f-068255099a57
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=544183763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.544183763
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.678755574
Short name T958
Test name
Test status
Simulation time 152889574 ps
CPU time 0.92 seconds
Started Jul 28 07:41:21 PM PDT 24
Finished Jul 28 07:41:22 PM PDT 24
Peak memory 207188 kb
Host smart-e79debce-50b0-4e0c-8a26-8ea099cf02b5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=678755574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.678755574
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1103245919
Short name T2174
Test name
Test status
Simulation time 162758718 ps
CPU time 0.82 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:41:19 PM PDT 24
Peak memory 207072 kb
Host smart-1ca58af7-14ae-438c-adee-4d89c06d74b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11032
45919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1103245919
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3099297803
Short name T1075
Test name
Test status
Simulation time 211726481 ps
CPU time 1.03 seconds
Started Jul 28 07:41:18 PM PDT 24
Finished Jul 28 07:41:19 PM PDT 24
Peak memory 207080 kb
Host smart-bcac3d65-64a4-4ebf-910c-5bafda66bf30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30992
97803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3099297803
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2963400726
Short name T1188
Test name
Test status
Simulation time 155432557 ps
CPU time 0.86 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:41:20 PM PDT 24
Peak memory 207024 kb
Host smart-0c25572b-b5b2-4c02-8956-b1f3424d38a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29634
00726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2963400726
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2683382328
Short name T1441
Test name
Test status
Simulation time 175587113 ps
CPU time 0.91 seconds
Started Jul 28 07:41:21 PM PDT 24
Finished Jul 28 07:41:22 PM PDT 24
Peak memory 207116 kb
Host smart-ebaacba5-ff36-49e5-824b-f0a403e4cad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26833
82328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2683382328
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.571890028
Short name T1869
Test name
Test status
Simulation time 150081649 ps
CPU time 0.89 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:41:20 PM PDT 24
Peak memory 207080 kb
Host smart-8f6c2efe-bc77-43c3-880c-e72fe76bbe1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57189
0028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.571890028
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.154646356
Short name T2000
Test name
Test status
Simulation time 147217033 ps
CPU time 0.83 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:41:20 PM PDT 24
Peak memory 207112 kb
Host smart-641631c7-a1a8-4163-bdd6-53c52b789381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15464
6356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.154646356
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.1431747070
Short name T1046
Test name
Test status
Simulation time 200192952 ps
CPU time 1.01 seconds
Started Jul 28 07:41:29 PM PDT 24
Finished Jul 28 07:41:30 PM PDT 24
Peak memory 207172 kb
Host smart-65c872d4-9d26-46ef-b3c8-1670ae3b5b32
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1431747070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.1431747070
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1010959052
Short name T2720
Test name
Test status
Simulation time 153891318 ps
CPU time 0.87 seconds
Started Jul 28 07:41:21 PM PDT 24
Finished Jul 28 07:41:22 PM PDT 24
Peak memory 207132 kb
Host smart-2763d308-84f2-44d2-a557-0fd3f7e0720a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10109
59052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1010959052
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1100502988
Short name T2494
Test name
Test status
Simulation time 29876985 ps
CPU time 0.69 seconds
Started Jul 28 07:41:22 PM PDT 24
Finished Jul 28 07:41:23 PM PDT 24
Peak memory 207140 kb
Host smart-92e7fe2b-33cf-41c7-a418-0f2dc9826ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11005
02988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1100502988
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.4137509102
Short name T1653
Test name
Test status
Simulation time 8069463269 ps
CPU time 22.48 seconds
Started Jul 28 07:41:22 PM PDT 24
Finished Jul 28 07:41:45 PM PDT 24
Peak memory 223908 kb
Host smart-13179794-93b9-4b38-86c9-54cd9fd2fd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41375
09102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.4137509102
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.51569164
Short name T1533
Test name
Test status
Simulation time 157147434 ps
CPU time 0.85 seconds
Started Jul 28 07:41:21 PM PDT 24
Finished Jul 28 07:41:22 PM PDT 24
Peak memory 207040 kb
Host smart-0b5bd962-347c-40df-a101-b1ae2ba60139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51569
164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.51569164
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.112402471
Short name T675
Test name
Test status
Simulation time 270897038 ps
CPU time 0.99 seconds
Started Jul 28 07:41:27 PM PDT 24
Finished Jul 28 07:41:28 PM PDT 24
Peak memory 207092 kb
Host smart-6708595c-671a-49c7-8a67-0676c749aaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11240
2471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.112402471
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.2502098317
Short name T742
Test name
Test status
Simulation time 276133911 ps
CPU time 1.05 seconds
Started Jul 28 07:41:18 PM PDT 24
Finished Jul 28 07:41:20 PM PDT 24
Peak memory 207152 kb
Host smart-d6c043de-fe5e-4972-b8e7-f070ab59acf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25020
98317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.2502098317
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.3288157139
Short name T668
Test name
Test status
Simulation time 172547897 ps
CPU time 0.88 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:41:20 PM PDT 24
Peak memory 207116 kb
Host smart-6856e922-5990-4f2c-bfea-c6102de8faef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32881
57139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3288157139
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3729957071
Short name T2861
Test name
Test status
Simulation time 167903504 ps
CPU time 0.85 seconds
Started Jul 28 07:41:24 PM PDT 24
Finished Jul 28 07:41:25 PM PDT 24
Peak memory 207104 kb
Host smart-5cfbbaac-0a9b-43da-8da0-a7e76ff627d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37299
57071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3729957071
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3975400212
Short name T2035
Test name
Test status
Simulation time 164699362 ps
CPU time 0.84 seconds
Started Jul 28 07:41:20 PM PDT 24
Finished Jul 28 07:41:21 PM PDT 24
Peak memory 207048 kb
Host smart-fb792857-6a48-40e8-9d81-e97c5c3f2931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754
00212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3975400212
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3926500853
Short name T878
Test name
Test status
Simulation time 163951602 ps
CPU time 0.86 seconds
Started Jul 28 07:41:26 PM PDT 24
Finished Jul 28 07:41:27 PM PDT 24
Peak memory 207140 kb
Host smart-bac03f1c-6640-4df8-9d74-0c29477c919a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39265
00853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3926500853
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3065963522
Short name T2587
Test name
Test status
Simulation time 204015537 ps
CPU time 0.99 seconds
Started Jul 28 07:41:20 PM PDT 24
Finished Jul 28 07:41:21 PM PDT 24
Peak memory 207128 kb
Host smart-3df7d507-a025-48dc-b23d-c8b19c211d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30659
63522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3065963522
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1486632840
Short name T1485
Test name
Test status
Simulation time 5483100376 ps
CPU time 54.49 seconds
Started Jul 28 07:41:21 PM PDT 24
Finished Jul 28 07:42:15 PM PDT 24
Peak memory 215500 kb
Host smart-dd40f669-055c-4708-ab8b-a0e9a4d1d482
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1486632840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1486632840
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1313244344
Short name T2578
Test name
Test status
Simulation time 246457928 ps
CPU time 0.96 seconds
Started Jul 28 07:41:21 PM PDT 24
Finished Jul 28 07:41:22 PM PDT 24
Peak memory 207172 kb
Host smart-cadc4871-5b4c-401c-844b-12f6ef0c6a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13132
44344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1313244344
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.629253365
Short name T2455
Test name
Test status
Simulation time 163662030 ps
CPU time 0.86 seconds
Started Jul 28 07:41:19 PM PDT 24
Finished Jul 28 07:41:20 PM PDT 24
Peak memory 207120 kb
Host smart-b07f96ac-7030-401f-b5e7-866bdc6b4940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62925
3365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.629253365
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.2723549421
Short name T318
Test name
Test status
Simulation time 1361591518 ps
CPU time 3.03 seconds
Started Jul 28 07:41:24 PM PDT 24
Finished Jul 28 07:41:27 PM PDT 24
Peak memory 207280 kb
Host smart-a880b145-a143-493e-b2c5-5101fb7e8bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27235
49421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2723549421
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.2684346338
Short name T584
Test name
Test status
Simulation time 4097383612 ps
CPU time 119.86 seconds
Started Jul 28 07:41:24 PM PDT 24
Finished Jul 28 07:43:24 PM PDT 24
Peak memory 215632 kb
Host smart-a23e15ba-da82-4d5a-81e0-e6998418eb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26843
46338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2684346338
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.1301459093
Short name T450
Test name
Test status
Simulation time 163254962 ps
CPU time 0.93 seconds
Started Jul 28 07:41:13 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207284 kb
Host smart-8a8f09e8-121e-4b62-9298-c810d837fe4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301459093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.1301459093
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.3348283472
Short name T648
Test name
Test status
Simulation time 62337308 ps
CPU time 0.7 seconds
Started Jul 28 07:41:45 PM PDT 24
Finished Jul 28 07:41:46 PM PDT 24
Peak memory 207224 kb
Host smart-e32197b1-2527-455c-9cb5-54c572d5fba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3348283472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.3348283472
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3923870931
Short name T1122
Test name
Test status
Simulation time 3468804200 ps
CPU time 5.14 seconds
Started Jul 28 07:41:25 PM PDT 24
Finished Jul 28 07:41:30 PM PDT 24
Peak memory 207436 kb
Host smart-48958ead-a3a9-40e6-9f1a-8d63590787ce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923870931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.3923870931
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.4028776605
Short name T733
Test name
Test status
Simulation time 13407769615 ps
CPU time 15.07 seconds
Started Jul 28 07:41:28 PM PDT 24
Finished Jul 28 07:41:43 PM PDT 24
Peak memory 207344 kb
Host smart-7cb75fd2-2dd4-45d4-a1fb-02e9f1a3e0f0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028776605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.4028776605
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2025729276
Short name T1755
Test name
Test status
Simulation time 23326079961 ps
CPU time 28.5 seconds
Started Jul 28 07:41:25 PM PDT 24
Finished Jul 28 07:41:54 PM PDT 24
Peak memory 207300 kb
Host smart-2d009e0a-26a2-41a0-b65c-3df551baf41a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025729276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.2025729276
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1577536406
Short name T894
Test name
Test status
Simulation time 194345199 ps
CPU time 0.93 seconds
Started Jul 28 07:41:29 PM PDT 24
Finished Jul 28 07:41:30 PM PDT 24
Peak memory 207160 kb
Host smart-932eab26-5c95-4ca2-99b2-09c0bf4c05f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15775
36406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1577536406
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.1140031400
Short name T2309
Test name
Test status
Simulation time 159613592 ps
CPU time 0.89 seconds
Started Jul 28 07:41:23 PM PDT 24
Finished Jul 28 07:41:24 PM PDT 24
Peak memory 207112 kb
Host smart-624ede97-e121-4bd7-b019-a66c9636f6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11400
31400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.1140031400
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1220128795
Short name T1637
Test name
Test status
Simulation time 325493048 ps
CPU time 1.39 seconds
Started Jul 28 07:41:25 PM PDT 24
Finished Jul 28 07:41:26 PM PDT 24
Peak memory 207136 kb
Host smart-734f1620-1880-4ee5-9ae8-58cc37b06e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12201
28795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1220128795
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2512609695
Short name T683
Test name
Test status
Simulation time 757264284 ps
CPU time 2.01 seconds
Started Jul 28 07:41:26 PM PDT 24
Finished Jul 28 07:41:28 PM PDT 24
Peak memory 207132 kb
Host smart-bc42c4e5-5e84-4ab1-96c9-52f7df99da76
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2512609695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2512609695
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3912689721
Short name T2265
Test name
Test status
Simulation time 7826646678 ps
CPU time 16.01 seconds
Started Jul 28 07:41:24 PM PDT 24
Finished Jul 28 07:41:40 PM PDT 24
Peak memory 207456 kb
Host smart-098fc108-3dc0-44ba-9228-89bac9da4a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39126
89721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3912689721
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.556584828
Short name T1119
Test name
Test status
Simulation time 2559427225 ps
CPU time 17.92 seconds
Started Jul 28 07:41:26 PM PDT 24
Finished Jul 28 07:41:44 PM PDT 24
Peak memory 207500 kb
Host smart-555e7faf-f8a5-495f-b472-5f1a2d691a5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556584828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.556584828
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3863062531
Short name T730
Test name
Test status
Simulation time 466636601 ps
CPU time 1.56 seconds
Started Jul 28 07:41:25 PM PDT 24
Finished Jul 28 07:41:27 PM PDT 24
Peak memory 207136 kb
Host smart-cbf8aa15-14f4-4d25-84f1-ea699e946b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38630
62531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3863062531
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3730993362
Short name T567
Test name
Test status
Simulation time 143193511 ps
CPU time 0.8 seconds
Started Jul 28 07:41:23 PM PDT 24
Finished Jul 28 07:41:24 PM PDT 24
Peak memory 207036 kb
Host smart-62420dd5-aa8c-4444-a565-1be9be86756e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37309
93362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3730993362
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2926203329
Short name T632
Test name
Test status
Simulation time 45888153 ps
CPU time 0.7 seconds
Started Jul 28 07:41:27 PM PDT 24
Finished Jul 28 07:41:27 PM PDT 24
Peak memory 207004 kb
Host smart-38a758c5-7769-4636-b605-d5fa8e2f0437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29262
03329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2926203329
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3671001962
Short name T2394
Test name
Test status
Simulation time 945563823 ps
CPU time 2.36 seconds
Started Jul 28 07:41:22 PM PDT 24
Finished Jul 28 07:41:25 PM PDT 24
Peak memory 207344 kb
Host smart-ba64a8db-6cd6-4262-926c-73cbd508c37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36710
01962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3671001962
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.4288091055
Short name T2031
Test name
Test status
Simulation time 249894618 ps
CPU time 1.79 seconds
Started Jul 28 07:41:27 PM PDT 24
Finished Jul 28 07:41:29 PM PDT 24
Peak memory 207352 kb
Host smart-c46c0ff3-8ec5-48e4-a53a-70b3c28c6c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42880
91055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.4288091055
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.4098927270
Short name T1974
Test name
Test status
Simulation time 280219453 ps
CPU time 1.25 seconds
Started Jul 28 07:41:24 PM PDT 24
Finished Jul 28 07:41:25 PM PDT 24
Peak memory 215488 kb
Host smart-303a7ea1-ba4a-45e5-b38e-0097d2aad5af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4098927270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.4098927270
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2706339352
Short name T2189
Test name
Test status
Simulation time 149425755 ps
CPU time 0.85 seconds
Started Jul 28 07:41:24 PM PDT 24
Finished Jul 28 07:41:25 PM PDT 24
Peak memory 207096 kb
Host smart-39774ec8-0f47-45f3-acec-f13dddb71ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27063
39352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2706339352
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3125386423
Short name T1764
Test name
Test status
Simulation time 160712847 ps
CPU time 0.86 seconds
Started Jul 28 07:41:24 PM PDT 24
Finished Jul 28 07:41:25 PM PDT 24
Peak memory 207156 kb
Host smart-9481b8ee-8e0f-41ce-b90a-1c36e41c4d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31253
86423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3125386423
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.2537235434
Short name T2220
Test name
Test status
Simulation time 8605414505 ps
CPU time 253.42 seconds
Started Jul 28 07:41:24 PM PDT 24
Finished Jul 28 07:45:37 PM PDT 24
Peak memory 215628 kb
Host smart-26577ff4-d0d2-487a-8f16-922f3ee2ded3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2537235434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.2537235434
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.3405891182
Short name T554
Test name
Test status
Simulation time 10949456358 ps
CPU time 79.61 seconds
Started Jul 28 07:41:26 PM PDT 24
Finished Jul 28 07:42:45 PM PDT 24
Peak memory 207424 kb
Host smart-5d2b16f4-2ee7-4a5f-9a6e-2d1a27a35124
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3405891182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.3405891182
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3678607699
Short name T2332
Test name
Test status
Simulation time 227179647 ps
CPU time 1.03 seconds
Started Jul 28 07:41:29 PM PDT 24
Finished Jul 28 07:41:30 PM PDT 24
Peak memory 207112 kb
Host smart-9a064f5e-41cd-4de6-9cb0-a99e6f499558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36786
07699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3678607699
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.882047551
Short name T490
Test name
Test status
Simulation time 23301285498 ps
CPU time 28.61 seconds
Started Jul 28 07:41:25 PM PDT 24
Finished Jul 28 07:41:54 PM PDT 24
Peak memory 207388 kb
Host smart-6021fc57-f3b4-4659-94e1-0d577baf56a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88204
7551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.882047551
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.4063504236
Short name T2632
Test name
Test status
Simulation time 3288257956 ps
CPU time 5.28 seconds
Started Jul 28 07:41:27 PM PDT 24
Finished Jul 28 07:41:32 PM PDT 24
Peak memory 207360 kb
Host smart-e3a3b06d-ef5c-400b-9663-5896522940ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40635
04236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.4063504236
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.2286949268
Short name T793
Test name
Test status
Simulation time 9607510533 ps
CPU time 70.15 seconds
Started Jul 28 07:41:32 PM PDT 24
Finished Jul 28 07:42:42 PM PDT 24
Peak memory 223764 kb
Host smart-6a70ee86-83b1-463e-833e-3addc10bf74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22869
49268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.2286949268
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.1533668604
Short name T1438
Test name
Test status
Simulation time 4286738021 ps
CPU time 33.39 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:42:13 PM PDT 24
Peak memory 215644 kb
Host smart-a730cda3-cabc-4ebc-8d21-96d1ab9030f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1533668604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.1533668604
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.1722191285
Short name T1945
Test name
Test status
Simulation time 303019702 ps
CPU time 1.09 seconds
Started Jul 28 07:41:27 PM PDT 24
Finished Jul 28 07:41:28 PM PDT 24
Peak memory 207136 kb
Host smart-68ea3860-0dfc-4ebc-b20e-7e1f724056ad
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1722191285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.1722191285
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.324330374
Short name T2004
Test name
Test status
Simulation time 219923405 ps
CPU time 0.96 seconds
Started Jul 28 07:41:31 PM PDT 24
Finished Jul 28 07:41:32 PM PDT 24
Peak memory 207112 kb
Host smart-0587a4db-0d72-47ce-bcea-9419a6e74def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32433
0374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.324330374
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.465959400
Short name T361
Test name
Test status
Simulation time 6355448753 ps
CPU time 185.99 seconds
Started Jul 28 07:41:38 PM PDT 24
Finished Jul 28 07:44:44 PM PDT 24
Peak memory 215556 kb
Host smart-12565b77-07fc-4f25-b7e7-38152cd2699a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46595
9400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.465959400
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1994865591
Short name T655
Test name
Test status
Simulation time 6276281543 ps
CPU time 186.48 seconds
Started Jul 28 07:41:38 PM PDT 24
Finished Jul 28 07:44:44 PM PDT 24
Peak memory 215612 kb
Host smart-7b53c446-6762-47dd-bc76-1082f64e45ec
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1994865591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1994865591
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1867872145
Short name T1550
Test name
Test status
Simulation time 166080336 ps
CPU time 0.85 seconds
Started Jul 28 07:41:28 PM PDT 24
Finished Jul 28 07:41:29 PM PDT 24
Peak memory 207136 kb
Host smart-658271c1-6ff0-4f92-9707-02d554cade9b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1867872145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1867872145
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3950238787
Short name T1453
Test name
Test status
Simulation time 202933507 ps
CPU time 0.88 seconds
Started Jul 28 07:41:37 PM PDT 24
Finished Jul 28 07:41:38 PM PDT 24
Peak memory 207140 kb
Host smart-96930d81-6f6c-407b-93f1-212639b24f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39502
38787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3950238787
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3730197396
Short name T1302
Test name
Test status
Simulation time 164380154 ps
CPU time 0.87 seconds
Started Jul 28 07:41:35 PM PDT 24
Finished Jul 28 07:41:36 PM PDT 24
Peak memory 207064 kb
Host smart-8e00987e-337f-471e-abb5-e0dd3e97c8bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37301
97396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3730197396
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.229330013
Short name T1265
Test name
Test status
Simulation time 177113553 ps
CPU time 0.96 seconds
Started Jul 28 07:41:30 PM PDT 24
Finished Jul 28 07:41:32 PM PDT 24
Peak memory 207172 kb
Host smart-80f119bd-b72e-4347-874b-74c4531e1825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22933
0013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.229330013
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3512261141
Short name T1090
Test name
Test status
Simulation time 183337158 ps
CPU time 0.93 seconds
Started Jul 28 07:41:38 PM PDT 24
Finished Jul 28 07:41:39 PM PDT 24
Peak memory 207140 kb
Host smart-ec46af04-3e61-4166-bee1-24ee6d8ba73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35122
61141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3512261141
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2063747128
Short name T713
Test name
Test status
Simulation time 155857670 ps
CPU time 0.86 seconds
Started Jul 28 07:41:28 PM PDT 24
Finished Jul 28 07:41:30 PM PDT 24
Peak memory 207128 kb
Host smart-ec9286d0-81fe-484a-98d4-d70b1f4efd76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20637
47128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2063747128
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.4127784676
Short name T460
Test name
Test status
Simulation time 206066633 ps
CPU time 0.99 seconds
Started Jul 28 07:41:31 PM PDT 24
Finished Jul 28 07:41:32 PM PDT 24
Peak memory 207184 kb
Host smart-f3d151a6-d8ec-4816-9292-6597e282b012
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4127784676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.4127784676
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3590466931
Short name T2451
Test name
Test status
Simulation time 141580983 ps
CPU time 0.87 seconds
Started Jul 28 07:41:27 PM PDT 24
Finished Jul 28 07:41:28 PM PDT 24
Peak memory 207100 kb
Host smart-de069cd0-7a03-442c-a4ef-baf9b3fce38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35904
66931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3590466931
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3710145184
Short name T2311
Test name
Test status
Simulation time 39917515 ps
CPU time 0.73 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:41:40 PM PDT 24
Peak memory 207096 kb
Host smart-b2b93acb-6d3a-4e6d-90ff-ed0679b8b09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37101
45184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3710145184
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.397528662
Short name T2346
Test name
Test status
Simulation time 7188389256 ps
CPU time 20.31 seconds
Started Jul 28 07:41:37 PM PDT 24
Finished Jul 28 07:41:57 PM PDT 24
Peak memory 220164 kb
Host smart-3d2da3d8-1bfa-4009-8e8a-e89c2b82d5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39752
8662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.397528662
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.4024191624
Short name T2478
Test name
Test status
Simulation time 164540881 ps
CPU time 0.89 seconds
Started Jul 28 07:41:29 PM PDT 24
Finished Jul 28 07:41:30 PM PDT 24
Peak memory 207084 kb
Host smart-c32d4564-c6e2-41c6-a2bc-ad3cb00143e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40241
91624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.4024191624
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.4092871752
Short name T2016
Test name
Test status
Simulation time 224798798 ps
CPU time 0.97 seconds
Started Jul 28 07:41:30 PM PDT 24
Finished Jul 28 07:41:31 PM PDT 24
Peak memory 207172 kb
Host smart-2bb89d61-8d36-4006-98e8-a4007cedf08d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40928
71752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.4092871752
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.2791933773
Short name T1002
Test name
Test status
Simulation time 178382770 ps
CPU time 0.97 seconds
Started Jul 28 07:41:30 PM PDT 24
Finished Jul 28 07:41:31 PM PDT 24
Peak memory 207084 kb
Host smart-3f8c62fd-87d8-4c2f-b237-47c6e50d2cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27919
33773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.2791933773
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2479628073
Short name T2707
Test name
Test status
Simulation time 192643716 ps
CPU time 0.99 seconds
Started Jul 28 07:41:27 PM PDT 24
Finished Jul 28 07:41:29 PM PDT 24
Peak memory 207288 kb
Host smart-c174674b-b05f-45de-8140-4277a7f3c4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24796
28073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2479628073
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.4117679230
Short name T1040
Test name
Test status
Simulation time 173645622 ps
CPU time 0.84 seconds
Started Jul 28 07:41:29 PM PDT 24
Finished Jul 28 07:41:30 PM PDT 24
Peak memory 207136 kb
Host smart-85f012f9-383d-4d7c-9e43-49e25105a8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41176
79230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.4117679230
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.735169754
Short name T2748
Test name
Test status
Simulation time 164521602 ps
CPU time 0.85 seconds
Started Jul 28 07:41:30 PM PDT 24
Finished Jul 28 07:41:31 PM PDT 24
Peak memory 207108 kb
Host smart-06650b4d-3e3a-4fe0-84c1-989422081bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73516
9754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.735169754
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1057992753
Short name T1834
Test name
Test status
Simulation time 153239952 ps
CPU time 0.8 seconds
Started Jul 28 07:41:27 PM PDT 24
Finished Jul 28 07:41:28 PM PDT 24
Peak memory 207124 kb
Host smart-6ff9a127-6409-447c-9e61-db5e8f700fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10579
92753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1057992753
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.739266312
Short name T2625
Test name
Test status
Simulation time 255380593 ps
CPU time 1.05 seconds
Started Jul 28 07:41:38 PM PDT 24
Finished Jul 28 07:41:39 PM PDT 24
Peak memory 207096 kb
Host smart-d594c4a3-32b6-4ff7-a609-564b3f15ffe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73926
6312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.739266312
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3256192823
Short name T1158
Test name
Test status
Simulation time 6661302782 ps
CPU time 196.39 seconds
Started Jul 28 07:41:36 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 215536 kb
Host smart-90951445-b002-409d-95c5-3c87c547e618
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3256192823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3256192823
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2595560198
Short name T2178
Test name
Test status
Simulation time 200573324 ps
CPU time 0.92 seconds
Started Jul 28 07:41:28 PM PDT 24
Finished Jul 28 07:41:29 PM PDT 24
Peak memory 207200 kb
Host smart-00d4b30d-b31f-4590-b2cf-7f3972317cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25955
60198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2595560198
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.132382724
Short name T1951
Test name
Test status
Simulation time 161595026 ps
CPU time 0.86 seconds
Started Jul 28 07:41:29 PM PDT 24
Finished Jul 28 07:41:30 PM PDT 24
Peak memory 207108 kb
Host smart-db63f9f2-4562-49f4-a929-8afe818c92c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13238
2724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.132382724
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.1397347463
Short name T959
Test name
Test status
Simulation time 997418312 ps
CPU time 2.64 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:41:42 PM PDT 24
Peak memory 207252 kb
Host smart-67a0d3ba-9b1a-4067-866d-2dc455acc07a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13973
47463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.1397347463
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.2775098930
Short name T1401
Test name
Test status
Simulation time 5077287312 ps
CPU time 51.11 seconds
Started Jul 28 07:41:26 PM PDT 24
Finished Jul 28 07:42:18 PM PDT 24
Peak memory 207476 kb
Host smart-3515f5d7-59f1-4962-adae-0854105663ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27750
98930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.2775098930
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.1854764327
Short name T902
Test name
Test status
Simulation time 2058152873 ps
CPU time 17.51 seconds
Started Jul 28 07:41:30 PM PDT 24
Finished Jul 28 07:41:48 PM PDT 24
Peak memory 207356 kb
Host smart-55931254-8049-48c3-820f-537aa1a1195d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854764327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.1854764327
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.143831299
Short name T2025
Test name
Test status
Simulation time 50250390 ps
CPU time 0.7 seconds
Started Jul 28 07:41:45 PM PDT 24
Finished Jul 28 07:41:46 PM PDT 24
Peak memory 207292 kb
Host smart-b8783c08-fd1e-4f58-b524-f90078a73713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=143831299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.143831299
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1584224071
Short name T1599
Test name
Test status
Simulation time 3739755128 ps
CPU time 6.53 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:41:46 PM PDT 24
Peak memory 207384 kb
Host smart-12ce03c2-051e-40f7-8a2c-e6b1454a55be
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584224071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.1584224071
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.375230598
Short name T1204
Test name
Test status
Simulation time 13312186121 ps
CPU time 17.17 seconds
Started Jul 28 07:41:53 PM PDT 24
Finished Jul 28 07:42:10 PM PDT 24
Peak memory 207336 kb
Host smart-e8db76dd-9cdf-413e-9763-1ad7966bf29f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=375230598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.375230598
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.644016625
Short name T1870
Test name
Test status
Simulation time 23403600995 ps
CPU time 28.98 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:42:08 PM PDT 24
Peak memory 207568 kb
Host smart-2897e497-9b8f-4023-8d31-0a6c53f53110
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644016625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ao
n_wake_resume.644016625
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.836089457
Short name T2193
Test name
Test status
Simulation time 147601088 ps
CPU time 0.87 seconds
Started Jul 28 07:41:44 PM PDT 24
Finished Jul 28 07:41:45 PM PDT 24
Peak memory 207172 kb
Host smart-55a127aa-8d85-4954-b69d-d32541a1d85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83608
9457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.836089457
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2676402813
Short name T1405
Test name
Test status
Simulation time 148521764 ps
CPU time 0.9 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:41:40 PM PDT 24
Peak memory 207048 kb
Host smart-7d440669-ff56-4880-a3fd-6eabd9410800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26764
02813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2676402813
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.415332130
Short name T97
Test name
Test status
Simulation time 477448678 ps
CPU time 1.59 seconds
Started Jul 28 07:41:40 PM PDT 24
Finished Jul 28 07:41:42 PM PDT 24
Peak memory 207080 kb
Host smart-67163477-23ef-493c-bf21-616c9bbd7fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41533
2130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.415332130
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.437496451
Short name T1821
Test name
Test status
Simulation time 383954752 ps
CPU time 1.24 seconds
Started Jul 28 07:41:35 PM PDT 24
Finished Jul 28 07:41:36 PM PDT 24
Peak memory 207160 kb
Host smart-ce16209a-4e66-4336-9c65-10557692e44c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=437496451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.437496451
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.1409112010
Short name T2251
Test name
Test status
Simulation time 20931256114 ps
CPU time 43.38 seconds
Started Jul 28 07:41:36 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207452 kb
Host smart-ff341764-3d1e-42ab-a457-5dd3791ec996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14091
12010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1409112010
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.4004333113
Short name T2020
Test name
Test status
Simulation time 733785267 ps
CPU time 5.05 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:41:44 PM PDT 24
Peak memory 207352 kb
Host smart-c49649c1-e4d2-40ac-953f-a93e5543f545
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004333113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.4004333113
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2200387011
Short name T1624
Test name
Test status
Simulation time 444918577 ps
CPU time 1.43 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:41:40 PM PDT 24
Peak memory 207088 kb
Host smart-10102629-7b54-498e-86b9-c68e7eeaa95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22003
87011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2200387011
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.158345275
Short name T1358
Test name
Test status
Simulation time 141728865 ps
CPU time 0.82 seconds
Started Jul 28 07:41:40 PM PDT 24
Finished Jul 28 07:41:41 PM PDT 24
Peak memory 207020 kb
Host smart-e40cebbb-de26-4376-9a53-16d3eab3fcd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15834
5275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.158345275
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.3401517953
Short name T1303
Test name
Test status
Simulation time 53473901 ps
CPU time 0.7 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:41:40 PM PDT 24
Peak memory 207104 kb
Host smart-fa24b7ef-63ea-48d5-8001-fd22ba965729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34015
17953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3401517953
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1058900210
Short name T1516
Test name
Test status
Simulation time 999557188 ps
CPU time 2.59 seconds
Started Jul 28 07:41:42 PM PDT 24
Finished Jul 28 07:41:45 PM PDT 24
Peak memory 207288 kb
Host smart-14dc3af1-62fd-449a-a410-dbb1bfe93c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10589
00210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1058900210
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1724530985
Short name T1808
Test name
Test status
Simulation time 184398427 ps
CPU time 2.25 seconds
Started Jul 28 07:41:40 PM PDT 24
Finished Jul 28 07:41:42 PM PDT 24
Peak memory 207324 kb
Host smart-2b927843-1d72-487e-9835-6175d244efb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245
30985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1724530985
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3249255566
Short name T2807
Test name
Test status
Simulation time 205362048 ps
CPU time 1.12 seconds
Started Jul 28 07:41:40 PM PDT 24
Finished Jul 28 07:41:41 PM PDT 24
Peak memory 207316 kb
Host smart-732b7652-2ba3-45fc-8e2b-be561ac971d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3249255566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3249255566
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.619096761
Short name T635
Test name
Test status
Simulation time 160391212 ps
CPU time 0.84 seconds
Started Jul 28 07:41:40 PM PDT 24
Finished Jul 28 07:41:41 PM PDT 24
Peak memory 207140 kb
Host smart-697440e4-7776-4d48-944b-a1b3f6ec486e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61909
6761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.619096761
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2174309742
Short name T1102
Test name
Test status
Simulation time 226025835 ps
CPU time 1.05 seconds
Started Jul 28 07:41:34 PM PDT 24
Finished Jul 28 07:41:35 PM PDT 24
Peak memory 207028 kb
Host smart-ee7b86a0-ea8b-4d2d-83c6-bc8837107b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21743
09742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2174309742
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.1439949773
Short name T744
Test name
Test status
Simulation time 6414297949 ps
CPU time 66.55 seconds
Started Jul 28 07:41:40 PM PDT 24
Finished Jul 28 07:42:47 PM PDT 24
Peak memory 217072 kb
Host smart-faefe592-8cf2-4ed1-aca9-7eb5d5d5f273
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1439949773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1439949773
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3472533012
Short name T1157
Test name
Test status
Simulation time 200646433 ps
CPU time 0.99 seconds
Started Jul 28 07:41:54 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 207104 kb
Host smart-02c0beb0-3e20-48eb-8c69-1e272e12a7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34725
33012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3472533012
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.4141924492
Short name T1887
Test name
Test status
Simulation time 23338417581 ps
CPU time 26.63 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:42:06 PM PDT 24
Peak memory 207336 kb
Host smart-7b90d442-3325-4d1b-b0dc-8162a1f1a80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41419
24492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.4141924492
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2620309209
Short name T1866
Test name
Test status
Simulation time 3346335196 ps
CPU time 5.91 seconds
Started Jul 28 07:41:52 PM PDT 24
Finished Jul 28 07:41:58 PM PDT 24
Peak memory 207400 kb
Host smart-70ba3e30-b607-4126-af81-864213a5bbee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26203
09209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2620309209
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.3151758040
Short name T627
Test name
Test status
Simulation time 4460428098 ps
CPU time 35.2 seconds
Started Jul 28 07:41:38 PM PDT 24
Finished Jul 28 07:42:13 PM PDT 24
Peak memory 223720 kb
Host smart-90d4c773-fd67-423b-9127-4684fd524e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31517
58040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.3151758040
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.1389853484
Short name T349
Test name
Test status
Simulation time 3551426010 ps
CPU time 102.58 seconds
Started Jul 28 07:41:41 PM PDT 24
Finished Jul 28 07:43:24 PM PDT 24
Peak memory 215548 kb
Host smart-c9e83dcb-b401-46af-b394-c4e0f8a91cc8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1389853484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.1389853484
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.967457285
Short name T1898
Test name
Test status
Simulation time 254436489 ps
CPU time 1 seconds
Started Jul 28 07:41:55 PM PDT 24
Finished Jul 28 07:41:56 PM PDT 24
Peak memory 207208 kb
Host smart-e2575bb3-0ea1-495a-9041-4644fa9c5e2c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=967457285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.967457285
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.942207021
Short name T922
Test name
Test status
Simulation time 190749303 ps
CPU time 0.92 seconds
Started Jul 28 07:41:47 PM PDT 24
Finished Jul 28 07:41:48 PM PDT 24
Peak memory 207204 kb
Host smart-77eab01d-768c-4e0b-951d-7c2a69628f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94220
7021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.942207021
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3032195996
Short name T2856
Test name
Test status
Simulation time 4623871037 ps
CPU time 46.28 seconds
Started Jul 28 07:41:53 PM PDT 24
Finished Jul 28 07:42:40 PM PDT 24
Peak memory 215520 kb
Host smart-267a8e6d-7b83-4e75-8023-d6f05a0e13b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30321
95996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3032195996
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.3109938787
Short name T1419
Test name
Test status
Simulation time 6917516447 ps
CPU time 193.04 seconds
Started Jul 28 07:41:44 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 215548 kb
Host smart-e0155cfa-da5b-49c0-8f25-86017525186a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3109938787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3109938787
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1557725232
Short name T2038
Test name
Test status
Simulation time 204995582 ps
CPU time 0.89 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:41:41 PM PDT 24
Peak memory 207152 kb
Host smart-ddacbd58-f15b-4523-abdf-5ae5e9fea023
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1557725232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1557725232
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2168522828
Short name T1258
Test name
Test status
Simulation time 172426995 ps
CPU time 0.88 seconds
Started Jul 28 07:41:57 PM PDT 24
Finished Jul 28 07:41:58 PM PDT 24
Peak memory 207108 kb
Host smart-3c7a4c9f-e8b9-4a47-a245-69be71becfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21685
22828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2168522828
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3260047914
Short name T129
Test name
Test status
Simulation time 192325419 ps
CPU time 0.91 seconds
Started Jul 28 07:41:51 PM PDT 24
Finished Jul 28 07:41:52 PM PDT 24
Peak memory 207184 kb
Host smart-65584857-4142-455a-a6d8-19dff0326169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32600
47914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3260047914
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.2968863196
Short name T1029
Test name
Test status
Simulation time 183042949 ps
CPU time 0.92 seconds
Started Jul 28 07:41:38 PM PDT 24
Finished Jul 28 07:41:39 PM PDT 24
Peak memory 207088 kb
Host smart-feaa78ea-6fc7-4cb8-a165-b516ed1db357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29688
63196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2968863196
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2198053757
Short name T587
Test name
Test status
Simulation time 184476511 ps
CPU time 0.96 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:41:40 PM PDT 24
Peak memory 207128 kb
Host smart-417dac4b-fe2b-48ee-8186-f4a7bcf82b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21980
53757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2198053757
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.803659373
Short name T633
Test name
Test status
Simulation time 172629294 ps
CPU time 0.85 seconds
Started Jul 28 07:41:44 PM PDT 24
Finished Jul 28 07:41:45 PM PDT 24
Peak memory 207128 kb
Host smart-7d59f540-7d22-4a5f-a810-abb0d917bbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80365
9373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.803659373
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3687856875
Short name T2472
Test name
Test status
Simulation time 154646487 ps
CPU time 0.88 seconds
Started Jul 28 07:41:43 PM PDT 24
Finished Jul 28 07:41:44 PM PDT 24
Peak memory 207120 kb
Host smart-579bfa70-075e-4a1d-bac4-fd287601caaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36878
56875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3687856875
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.802273824
Short name T2259
Test name
Test status
Simulation time 238600058 ps
CPU time 1.15 seconds
Started Jul 28 07:41:44 PM PDT 24
Finished Jul 28 07:41:45 PM PDT 24
Peak memory 207116 kb
Host smart-adab804a-cdb2-4de6-a013-9ec8470ad14e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=802273824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.802273824
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2237582888
Short name T1386
Test name
Test status
Simulation time 50842917 ps
CPU time 0.73 seconds
Started Jul 28 07:41:54 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 207012 kb
Host smart-cefc4601-9b19-4549-a928-c69574cae9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22375
82888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2237582888
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.157577725
Short name T1043
Test name
Test status
Simulation time 8088519036 ps
CPU time 19.73 seconds
Started Jul 28 07:41:51 PM PDT 24
Finished Jul 28 07:42:11 PM PDT 24
Peak memory 215620 kb
Host smart-1745ceb1-5dc2-4ba1-8bdb-c02faaffbf10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15757
7725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.157577725
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2882850628
Short name T687
Test name
Test status
Simulation time 184079496 ps
CPU time 0.92 seconds
Started Jul 28 07:41:37 PM PDT 24
Finished Jul 28 07:41:38 PM PDT 24
Peak memory 207260 kb
Host smart-f4b07340-b29b-449f-b87a-3f6d5138bacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28828
50628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2882850628
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.72587439
Short name T1324
Test name
Test status
Simulation time 245372736 ps
CPU time 0.96 seconds
Started Jul 28 07:41:59 PM PDT 24
Finished Jul 28 07:42:00 PM PDT 24
Peak memory 207156 kb
Host smart-46ac5a0f-c473-4d24-b727-44a46f4cfc40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72587
439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.72587439
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.4055145757
Short name T1908
Test name
Test status
Simulation time 182498395 ps
CPU time 0.93 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:41:41 PM PDT 24
Peak memory 207136 kb
Host smart-d6a235cf-01b0-4290-82d6-f5cf543ef6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40551
45757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.4055145757
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3004798381
Short name T2523
Test name
Test status
Simulation time 160241874 ps
CPU time 0.86 seconds
Started Jul 28 07:41:45 PM PDT 24
Finished Jul 28 07:41:46 PM PDT 24
Peak memory 207108 kb
Host smart-51536e45-073f-4329-8e04-cfcefbbd5077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30047
98381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3004798381
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1661035361
Short name T2859
Test name
Test status
Simulation time 159621783 ps
CPU time 0.85 seconds
Started Jul 28 07:41:44 PM PDT 24
Finished Jul 28 07:41:45 PM PDT 24
Peak memory 207092 kb
Host smart-9a5a1ed6-ba28-4776-99c6-876dfe6966f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16610
35361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1661035361
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3087945978
Short name T1176
Test name
Test status
Simulation time 178594593 ps
CPU time 0.88 seconds
Started Jul 28 07:41:46 PM PDT 24
Finished Jul 28 07:41:47 PM PDT 24
Peak memory 207176 kb
Host smart-bb696625-8cf4-4091-af75-2ed5c1f39e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30879
45978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3087945978
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.687033602
Short name T1875
Test name
Test status
Simulation time 175476561 ps
CPU time 0.86 seconds
Started Jul 28 07:42:00 PM PDT 24
Finished Jul 28 07:42:00 PM PDT 24
Peak memory 207136 kb
Host smart-84fe1bcd-e651-4110-a761-197beb0bc8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68703
3602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.687033602
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.4270834213
Short name T2337
Test name
Test status
Simulation time 261294674 ps
CPU time 1.07 seconds
Started Jul 28 07:41:53 PM PDT 24
Finished Jul 28 07:41:54 PM PDT 24
Peak memory 207056 kb
Host smart-2c56092f-5103-468b-b821-f3947a1b0b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42708
34213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.4270834213
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.3900800954
Short name T1459
Test name
Test status
Simulation time 6344292006 ps
CPU time 187.06 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 215648 kb
Host smart-71fe6fa2-83e3-425c-a33e-d651911a0cde
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3900800954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.3900800954
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.639638289
Short name T1797
Test name
Test status
Simulation time 160344072 ps
CPU time 0.87 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:41:57 PM PDT 24
Peak memory 207076 kb
Host smart-780499c9-6a33-4c0a-8e61-a6d3158f603e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63963
8289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.639638289
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.1240085846
Short name T967
Test name
Test status
Simulation time 187201506 ps
CPU time 0.93 seconds
Started Jul 28 07:41:52 PM PDT 24
Finished Jul 28 07:41:53 PM PDT 24
Peak memory 207152 kb
Host smart-f66a6b57-3850-4203-92af-0b8e4fcc376d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12400
85846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1240085846
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.1082254049
Short name T2844
Test name
Test status
Simulation time 1201153661 ps
CPU time 2.8 seconds
Started Jul 28 07:41:52 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 207372 kb
Host smart-6854971b-80b7-46e8-8ef1-ce061b361a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10822
54049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.1082254049
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.2924658529
Short name T2440
Test name
Test status
Simulation time 5446582834 ps
CPU time 161.87 seconds
Started Jul 28 07:41:59 PM PDT 24
Finished Jul 28 07:44:41 PM PDT 24
Peak memory 215464 kb
Host smart-2183bc61-596d-4612-9a57-de68781fd853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29246
58529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2924658529
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.3799426479
Short name T999
Test name
Test status
Simulation time 9045112627 ps
CPU time 59.52 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:42:39 PM PDT 24
Peak memory 207532 kb
Host smart-cf344734-699f-460a-85bb-00a509407376
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799426479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.3799426479
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.2327443941
Short name T1976
Test name
Test status
Simulation time 66553805 ps
CPU time 0.68 seconds
Started Jul 28 07:41:50 PM PDT 24
Finished Jul 28 07:41:51 PM PDT 24
Peak memory 207168 kb
Host smart-f6f0793f-8a1a-4b77-84ec-5c3d4d2dcc67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2327443941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2327443941
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.1233638796
Short name T1607
Test name
Test status
Simulation time 3690320719 ps
CPU time 6.38 seconds
Started Jul 28 07:41:47 PM PDT 24
Finished Jul 28 07:41:53 PM PDT 24
Peak memory 207328 kb
Host smart-ec24a025-5c88-4cf0-9c3e-27690bc58181
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233638796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.1233638796
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.4060132746
Short name T1800
Test name
Test status
Simulation time 13346832662 ps
CPU time 19.29 seconds
Started Jul 28 07:41:43 PM PDT 24
Finished Jul 28 07:42:02 PM PDT 24
Peak memory 207388 kb
Host smart-62d9c7df-12ff-43d3-9c3a-40f48418189c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060132746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.4060132746
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.4061298270
Short name T570
Test name
Test status
Simulation time 23391040895 ps
CPU time 27.63 seconds
Started Jul 28 07:41:42 PM PDT 24
Finished Jul 28 07:42:10 PM PDT 24
Peak memory 207352 kb
Host smart-69bbdf4e-f7f0-4896-a7ba-695ea983c058
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061298270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.4061298270
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2834586416
Short name T818
Test name
Test status
Simulation time 250326771 ps
CPU time 0.93 seconds
Started Jul 28 07:41:39 PM PDT 24
Finished Jul 28 07:41:41 PM PDT 24
Peak memory 207140 kb
Host smart-d64489d6-3b3d-4d39-a085-d0adf221a34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28345
86416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2834586416
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.14587579
Short name T2702
Test name
Test status
Simulation time 154589419 ps
CPU time 0.86 seconds
Started Jul 28 07:41:57 PM PDT 24
Finished Jul 28 07:41:58 PM PDT 24
Peak memory 207168 kb
Host smart-1076726e-af15-496d-87c2-301ae657fea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14587
579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.14587579
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1284412656
Short name T502
Test name
Test status
Simulation time 379689826 ps
CPU time 1.41 seconds
Started Jul 28 07:41:54 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 207052 kb
Host smart-b63101d4-cf87-47c6-bfc2-74bb6ff3173c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12844
12656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1284412656
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2770896096
Short name T1732
Test name
Test status
Simulation time 909587338 ps
CPU time 2.49 seconds
Started Jul 28 07:41:55 PM PDT 24
Finished Jul 28 07:41:58 PM PDT 24
Peak memory 207240 kb
Host smart-fd7722c7-0f47-4204-8cda-062349b447ca
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2770896096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2770896096
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2098155291
Short name T1479
Test name
Test status
Simulation time 10712116061 ps
CPU time 22.37 seconds
Started Jul 28 07:41:41 PM PDT 24
Finished Jul 28 07:42:03 PM PDT 24
Peak memory 207508 kb
Host smart-b57e6052-6596-4afd-8adf-903004c482a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20981
55291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2098155291
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.1848000131
Short name T1954
Test name
Test status
Simulation time 849651574 ps
CPU time 18.96 seconds
Started Jul 28 07:41:46 PM PDT 24
Finished Jul 28 07:42:05 PM PDT 24
Peak memory 207344 kb
Host smart-60255d5e-5444-4509-baf6-8d68b87b3484
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848000131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.1848000131
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3785633389
Short name T976
Test name
Test status
Simulation time 430732126 ps
CPU time 1.51 seconds
Started Jul 28 07:41:50 PM PDT 24
Finished Jul 28 07:41:52 PM PDT 24
Peak memory 207124 kb
Host smart-a2cf8f13-c706-4758-945d-391941ac4326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37856
33389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3785633389
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.830385909
Short name T2825
Test name
Test status
Simulation time 151964388 ps
CPU time 0.92 seconds
Started Jul 28 07:41:48 PM PDT 24
Finished Jul 28 07:41:49 PM PDT 24
Peak memory 207152 kb
Host smart-a27b3044-a7ca-45f3-b6ec-ef7fbdddd029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83038
5909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.830385909
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.1599453469
Short name T2060
Test name
Test status
Simulation time 95149830 ps
CPU time 0.8 seconds
Started Jul 28 07:41:54 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 207112 kb
Host smart-a037646b-6a1c-4e0c-94df-c88c33ed9d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15994
53469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1599453469
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.3254248287
Short name T2426
Test name
Test status
Simulation time 934367457 ps
CPU time 2.58 seconds
Started Jul 28 07:41:46 PM PDT 24
Finished Jul 28 07:41:48 PM PDT 24
Peak memory 207304 kb
Host smart-18e61ebb-7f50-4ecc-b2fb-cc917a442c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32542
48287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.3254248287
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3558605896
Short name T760
Test name
Test status
Simulation time 323323458 ps
CPU time 2.77 seconds
Started Jul 28 07:41:51 PM PDT 24
Finished Jul 28 07:41:54 PM PDT 24
Peak memory 207272 kb
Host smart-08fdd08f-9700-4328-9ef8-28a568454bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35586
05896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3558605896
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.862474381
Short name T2406
Test name
Test status
Simulation time 186098804 ps
CPU time 0.95 seconds
Started Jul 28 07:41:47 PM PDT 24
Finished Jul 28 07:41:48 PM PDT 24
Peak memory 215280 kb
Host smart-d3c3f86e-91dc-4e75-9645-7ea16a94e017
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=862474381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.862474381
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.75289101
Short name T1487
Test name
Test status
Simulation time 143540575 ps
CPU time 0.78 seconds
Started Jul 28 07:41:47 PM PDT 24
Finished Jul 28 07:41:48 PM PDT 24
Peak memory 207048 kb
Host smart-623e27ac-5bb4-4f92-8646-1923e83f75c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75289
101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.75289101
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2064482469
Short name T2248
Test name
Test status
Simulation time 210279169 ps
CPU time 0.94 seconds
Started Jul 28 07:41:43 PM PDT 24
Finished Jul 28 07:41:44 PM PDT 24
Peak memory 207172 kb
Host smart-0b373a1f-efd1-4db9-a6a0-9995bab94448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20644
82469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2064482469
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.3846726864
Short name T2096
Test name
Test status
Simulation time 10402510605 ps
CPU time 80.09 seconds
Started Jul 28 07:41:54 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 217036 kb
Host smart-a6a0c889-6b45-4d67-85f6-fac867ef7147
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3846726864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3846726864
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.4011312845
Short name T2116
Test name
Test status
Simulation time 5337255008 ps
CPU time 39.66 seconds
Started Jul 28 07:41:47 PM PDT 24
Finished Jul 28 07:42:27 PM PDT 24
Peak memory 207296 kb
Host smart-3390886b-b96d-4e34-ace0-c84807815dd2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4011312845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.4011312845
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1564192003
Short name T2465
Test name
Test status
Simulation time 193765692 ps
CPU time 0.93 seconds
Started Jul 28 07:41:55 PM PDT 24
Finished Jul 28 07:41:56 PM PDT 24
Peak memory 207044 kb
Host smart-d8d1e010-f331-4472-9d0b-c5a1bd3be847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15641
92003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1564192003
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.562000114
Short name T2272
Test name
Test status
Simulation time 23327626741 ps
CPU time 27.99 seconds
Started Jul 28 07:41:51 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207284 kb
Host smart-ac81f900-1dfc-45e4-a2f4-47e8cfffb262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56200
0114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.562000114
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.4152318517
Short name T1426
Test name
Test status
Simulation time 3277135195 ps
CPU time 4.85 seconds
Started Jul 28 07:42:05 PM PDT 24
Finished Jul 28 07:42:10 PM PDT 24
Peak memory 207392 kb
Host smart-b3d01628-ffea-41c6-91a4-91dfcc36a37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41523
18517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.4152318517
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.2697766432
Short name T2285
Test name
Test status
Simulation time 6522803600 ps
CPU time 50.67 seconds
Started Jul 28 07:41:47 PM PDT 24
Finished Jul 28 07:42:38 PM PDT 24
Peak memory 223784 kb
Host smart-781ca9e3-beca-4cb6-adfe-1d3d6b23103f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26977
66432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.2697766432
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1183429396
Short name T1396
Test name
Test status
Simulation time 5215892111 ps
CPU time 39.67 seconds
Started Jul 28 07:41:47 PM PDT 24
Finished Jul 28 07:42:26 PM PDT 24
Peak memory 217068 kb
Host smart-c7cea9ca-e585-426b-97af-34380a6e2fc6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1183429396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1183429396
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3410010728
Short name T2452
Test name
Test status
Simulation time 270097007 ps
CPU time 1.08 seconds
Started Jul 28 07:41:46 PM PDT 24
Finished Jul 28 07:41:47 PM PDT 24
Peak memory 207144 kb
Host smart-a036e2d8-e8e5-4544-8692-6494fb74abb2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3410010728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3410010728
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3451198749
Short name T1947
Test name
Test status
Simulation time 210066163 ps
CPU time 0.95 seconds
Started Jul 28 07:41:42 PM PDT 24
Finished Jul 28 07:41:43 PM PDT 24
Peak memory 207148 kb
Host smart-592e7ada-24dc-4acf-abf4-5d64d20ec42d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34511
98749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3451198749
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.1626532306
Short name T416
Test name
Test status
Simulation time 6495174026 ps
CPU time 48.84 seconds
Started Jul 28 07:41:46 PM PDT 24
Finished Jul 28 07:42:35 PM PDT 24
Peak memory 207032 kb
Host smart-08b97a19-b9ea-42ee-a030-85bda4ba2455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16265
32306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.1626532306
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.1908889284
Short name T565
Test name
Test status
Simulation time 4722867325 ps
CPU time 36.53 seconds
Started Jul 28 07:41:58 PM PDT 24
Finished Jul 28 07:42:35 PM PDT 24
Peak memory 215548 kb
Host smart-96c471b3-9f30-4cfd-8dee-7f371403c28d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1908889284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.1908889284
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.1057854375
Short name T2111
Test name
Test status
Simulation time 156903933 ps
CPU time 0.87 seconds
Started Jul 28 07:41:48 PM PDT 24
Finished Jul 28 07:41:54 PM PDT 24
Peak memory 207184 kb
Host smart-fad176b0-c9f8-44e2-8ff6-f09ce437ad22
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1057854375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.1057854375
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1941092546
Short name T1331
Test name
Test status
Simulation time 142873091 ps
CPU time 0.83 seconds
Started Jul 28 07:41:42 PM PDT 24
Finished Jul 28 07:41:44 PM PDT 24
Peak memory 207024 kb
Host smart-fb474773-f51b-45cb-b2af-2f42d39bf79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19410
92546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1941092546
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3547305584
Short name T120
Test name
Test status
Simulation time 223460037 ps
CPU time 1.04 seconds
Started Jul 28 07:41:48 PM PDT 24
Finished Jul 28 07:41:50 PM PDT 24
Peak memory 207156 kb
Host smart-7b296d77-3530-4def-9788-77957511e06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35473
05584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3547305584
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3669666002
Short name T2365
Test name
Test status
Simulation time 169402342 ps
CPU time 0.9 seconds
Started Jul 28 07:41:47 PM PDT 24
Finished Jul 28 07:41:48 PM PDT 24
Peak memory 207072 kb
Host smart-0114a860-4c28-4e7c-b365-71f392a41f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36696
66002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3669666002
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2910822867
Short name T936
Test name
Test status
Simulation time 190389890 ps
CPU time 0.98 seconds
Started Jul 28 07:41:51 PM PDT 24
Finished Jul 28 07:41:52 PM PDT 24
Peak memory 207188 kb
Host smart-4343b084-8bc8-4b16-9e9b-25bd4ac6040d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29108
22867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2910822867
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2275833413
Short name T269
Test name
Test status
Simulation time 182973087 ps
CPU time 0.88 seconds
Started Jul 28 07:41:46 PM PDT 24
Finished Jul 28 07:41:47 PM PDT 24
Peak memory 207116 kb
Host smart-68854284-2691-4422-8009-ee8817480772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22758
33413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2275833413
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2580656190
Short name T646
Test name
Test status
Simulation time 159621037 ps
CPU time 0.92 seconds
Started Jul 28 07:41:47 PM PDT 24
Finished Jul 28 07:41:48 PM PDT 24
Peak memory 207176 kb
Host smart-6f533214-2420-49b0-89a8-d372aac86510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25806
56190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2580656190
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1120736824
Short name T737
Test name
Test status
Simulation time 244145532 ps
CPU time 1.13 seconds
Started Jul 28 07:42:05 PM PDT 24
Finished Jul 28 07:42:06 PM PDT 24
Peak memory 207136 kb
Host smart-16414273-e008-4a55-83f4-819489223df3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1120736824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1120736824
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.452753571
Short name T1557
Test name
Test status
Simulation time 150757200 ps
CPU time 0.83 seconds
Started Jul 28 07:41:46 PM PDT 24
Finished Jul 28 07:41:47 PM PDT 24
Peak memory 206872 kb
Host smart-a4a4d353-3d4e-48e7-90a3-411b06d9f00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45275
3571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.452753571
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2319084319
Short name T1461
Test name
Test status
Simulation time 76218882 ps
CPU time 0.74 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:09 PM PDT 24
Peak memory 207108 kb
Host smart-07f6ab34-2ab0-45ff-8e25-f86a82a25184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23190
84319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2319084319
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.4027508209
Short name T1465
Test name
Test status
Simulation time 11692920572 ps
CPU time 27.23 seconds
Started Jul 28 07:41:59 PM PDT 24
Finished Jul 28 07:42:26 PM PDT 24
Peak memory 215604 kb
Host smart-25e342f9-6cc4-40f8-aaba-288a365f1ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40275
08209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.4027508209
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3767359419
Short name T1297
Test name
Test status
Simulation time 218142284 ps
CPU time 0.95 seconds
Started Jul 28 07:41:51 PM PDT 24
Finished Jul 28 07:41:52 PM PDT 24
Peak memory 207144 kb
Host smart-32025266-5094-4ae8-adf0-797cee2eecc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37673
59419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3767359419
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.976681399
Short name T2656
Test name
Test status
Simulation time 172084237 ps
CPU time 0.89 seconds
Started Jul 28 07:41:51 PM PDT 24
Finished Jul 28 07:41:52 PM PDT 24
Peak memory 207068 kb
Host smart-f089c33d-2e09-4f3e-a9b6-443a5f8e9c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97668
1399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.976681399
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.1236932556
Short name T714
Test name
Test status
Simulation time 231348360 ps
CPU time 0.93 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:09 PM PDT 24
Peak memory 207116 kb
Host smart-54ed324a-1fad-400e-9d68-589f01193cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12369
32556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.1236932556
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3874914032
Short name T28
Test name
Test status
Simulation time 166445398 ps
CPU time 0.86 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:09 PM PDT 24
Peak memory 207200 kb
Host smart-8036f11e-e9e5-4620-b62b-5f9892743329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38749
14032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3874914032
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2153003273
Short name T1719
Test name
Test status
Simulation time 202580002 ps
CPU time 0.89 seconds
Started Jul 28 07:42:02 PM PDT 24
Finished Jul 28 07:42:03 PM PDT 24
Peak memory 207168 kb
Host smart-80a5533b-7646-44d8-9fef-e7ea9017ad4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21530
03273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2153003273
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1927563014
Short name T1701
Test name
Test status
Simulation time 148658706 ps
CPU time 0.82 seconds
Started Jul 28 07:41:49 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 207048 kb
Host smart-d809591a-3e22-4fd1-aef9-01fab47216aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19275
63014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1927563014
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.919740239
Short name T2745
Test name
Test status
Simulation time 154263405 ps
CPU time 0.87 seconds
Started Jul 28 07:41:52 PM PDT 24
Finished Jul 28 07:41:52 PM PDT 24
Peak memory 207144 kb
Host smart-47813595-2d89-4099-9107-99d8a44048c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91974
0239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.919740239
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3502730098
Short name T2433
Test name
Test status
Simulation time 252661304 ps
CPU time 1.08 seconds
Started Jul 28 07:41:49 PM PDT 24
Finished Jul 28 07:41:51 PM PDT 24
Peak memory 207176 kb
Host smart-fd092655-d8f2-4172-9cfd-c262576e4bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35027
30098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3502730098
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.3092188351
Short name T1729
Test name
Test status
Simulation time 5852893431 ps
CPU time 61.74 seconds
Started Jul 28 07:42:04 PM PDT 24
Finished Jul 28 07:43:06 PM PDT 24
Peak memory 215632 kb
Host smart-fadd8ce7-e4ef-406c-b320-c4a392520726
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3092188351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3092188351
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3807003328
Short name T2146
Test name
Test status
Simulation time 170563225 ps
CPU time 0.9 seconds
Started Jul 28 07:42:10 PM PDT 24
Finished Jul 28 07:42:11 PM PDT 24
Peak memory 207088 kb
Host smart-89f2752f-d4dd-4984-8210-ad067a525656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38070
03328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3807003328
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1699174251
Short name T2290
Test name
Test status
Simulation time 182738912 ps
CPU time 0.89 seconds
Started Jul 28 07:41:51 PM PDT 24
Finished Jul 28 07:41:51 PM PDT 24
Peak memory 207140 kb
Host smart-51b10e07-0f47-4379-a3fb-9d6560f24a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16991
74251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1699174251
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.843672921
Short name T1998
Test name
Test status
Simulation time 1182436486 ps
CPU time 2.92 seconds
Started Jul 28 07:41:48 PM PDT 24
Finished Jul 28 07:41:51 PM PDT 24
Peak memory 207344 kb
Host smart-2d99f4e6-84f0-443c-82bb-ff94fd832bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84367
2921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.843672921
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2507048729
Short name T1629
Test name
Test status
Simulation time 4855529446 ps
CPU time 137.04 seconds
Started Jul 28 07:42:03 PM PDT 24
Finished Jul 28 07:44:21 PM PDT 24
Peak memory 215588 kb
Host smart-af9abc88-68ab-424b-a249-b4b76e48011a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25070
48729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2507048729
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.3999026221
Short name T2041
Test name
Test status
Simulation time 1548310185 ps
CPU time 13.64 seconds
Started Jul 28 07:41:57 PM PDT 24
Finished Jul 28 07:42:11 PM PDT 24
Peak memory 207408 kb
Host smart-cef941d6-d6d3-40dd-ae15-1fdd336a4d0f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999026221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.3999026221
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.827107846
Short name T181
Test name
Test status
Simulation time 32600224 ps
CPU time 0.66 seconds
Started Jul 28 07:42:06 PM PDT 24
Finished Jul 28 07:42:07 PM PDT 24
Peak memory 207300 kb
Host smart-6ef446de-1155-4d2f-b360-8c4fee1795bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=827107846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.827107846
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.1864696408
Short name T535
Test name
Test status
Simulation time 3439633444 ps
CPU time 5.55 seconds
Started Jul 28 07:41:50 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 207328 kb
Host smart-ca21c6fb-cfbb-4694-ab41-05f1fb19db3c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864696408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_disconnect.1864696408
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1088879663
Short name T2598
Test name
Test status
Simulation time 13475647282 ps
CPU time 16.77 seconds
Started Jul 28 07:42:02 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207396 kb
Host smart-47549938-5fa7-4fdd-8f6a-eaeeebf9c9b2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088879663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1088879663
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.4257987402
Short name T528
Test name
Test status
Simulation time 23407951875 ps
CPU time 30.31 seconds
Started Jul 28 07:41:53 PM PDT 24
Finished Jul 28 07:42:24 PM PDT 24
Peak memory 207548 kb
Host smart-f44a95af-567d-43b8-a405-2b72007cd1b5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257987402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.4257987402
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3667705686
Short name T564
Test name
Test status
Simulation time 152285643 ps
CPU time 0.83 seconds
Started Jul 28 07:42:11 PM PDT 24
Finished Jul 28 07:42:11 PM PDT 24
Peak memory 207168 kb
Host smart-2746b90b-b128-442d-b421-0669a36bc948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36677
05686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3667705686
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3601930418
Short name T453
Test name
Test status
Simulation time 163001786 ps
CPU time 0.88 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:09 PM PDT 24
Peak memory 207036 kb
Host smart-b39c4cf6-e77c-45de-bce8-9116e0b5f382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36019
30418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3601930418
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.2496679396
Short name T2510
Test name
Test status
Simulation time 282929791 ps
CPU time 1.11 seconds
Started Jul 28 07:42:00 PM PDT 24
Finished Jul 28 07:42:01 PM PDT 24
Peak memory 207156 kb
Host smart-3839198f-59fa-4efa-906f-225b02a0ec82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24966
79396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.2496679396
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.362566827
Short name T1261
Test name
Test status
Simulation time 1533708241 ps
CPU time 4.12 seconds
Started Jul 28 07:42:05 PM PDT 24
Finished Jul 28 07:42:09 PM PDT 24
Peak memory 207260 kb
Host smart-b9832e35-da72-4e92-936f-97e1c03c0808
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=362566827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.362566827
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.3785652085
Short name T2752
Test name
Test status
Simulation time 11152625730 ps
CPU time 22.74 seconds
Started Jul 28 07:41:53 PM PDT 24
Finished Jul 28 07:42:16 PM PDT 24
Peak memory 207320 kb
Host smart-c070122e-1c59-4ead-a347-032f00748b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37856
52085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3785652085
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.3227897671
Short name T1235
Test name
Test status
Simulation time 1949580974 ps
CPU time 13.84 seconds
Started Jul 28 07:42:05 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207204 kb
Host smart-df467acc-d30e-459a-8d79-b74a28f0655f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227897671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.3227897671
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.678255262
Short name T1874
Test name
Test status
Simulation time 364724080 ps
CPU time 1.34 seconds
Started Jul 28 07:41:57 PM PDT 24
Finished Jul 28 07:41:59 PM PDT 24
Peak memory 206992 kb
Host smart-0a4a1e26-6dbd-4f86-a914-4ccdfa4e23b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67825
5262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.678255262
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.2888791427
Short name T2547
Test name
Test status
Simulation time 148096495 ps
CPU time 0.89 seconds
Started Jul 28 07:42:03 PM PDT 24
Finished Jul 28 07:42:04 PM PDT 24
Peak memory 207132 kb
Host smart-e0640aa1-c945-44d0-9f92-367471be19c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28887
91427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.2888791427
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.1919106600
Short name T1847
Test name
Test status
Simulation time 32502343 ps
CPU time 0.7 seconds
Started Jul 28 07:42:05 PM PDT 24
Finished Jul 28 07:42:06 PM PDT 24
Peak memory 207092 kb
Host smart-57d737fd-7d2a-4528-80e3-7e4e95171b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19191
06600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1919106600
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1521863029
Short name T2297
Test name
Test status
Simulation time 809496212 ps
CPU time 2.24 seconds
Started Jul 28 07:41:53 PM PDT 24
Finished Jul 28 07:41:56 PM PDT 24
Peak memory 207488 kb
Host smart-8ab0600b-fca2-4da8-a46b-0ebff7de62c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15218
63029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1521863029
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1256013219
Short name T765
Test name
Test status
Simulation time 289427654 ps
CPU time 2.5 seconds
Started Jul 28 07:41:54 PM PDT 24
Finished Jul 28 07:41:57 PM PDT 24
Peak memory 207256 kb
Host smart-ca3353bb-73b2-4f41-846e-1a9a67c10ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12560
13219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1256013219
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.910097711
Short name T1445
Test name
Test status
Simulation time 266663802 ps
CPU time 1.14 seconds
Started Jul 28 07:41:49 PM PDT 24
Finished Jul 28 07:41:50 PM PDT 24
Peak memory 207328 kb
Host smart-3660a4ff-c64a-4146-b395-74e3dcdee6dc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=910097711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.910097711
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3645917173
Short name T1036
Test name
Test status
Simulation time 142229261 ps
CPU time 0.82 seconds
Started Jul 28 07:42:01 PM PDT 24
Finished Jul 28 07:42:02 PM PDT 24
Peak memory 207056 kb
Host smart-a7dfaf62-3f8a-4bf7-8e71-ccf30abb7a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36459
17173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3645917173
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1101530815
Short name T2227
Test name
Test status
Simulation time 162784417 ps
CPU time 0.85 seconds
Started Jul 28 07:41:49 PM PDT 24
Finished Jul 28 07:41:50 PM PDT 24
Peak memory 207112 kb
Host smart-c2ed4e81-febd-4334-a1b9-f940b273aaae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11015
30815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1101530815
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.3347237281
Short name T2334
Test name
Test status
Simulation time 10701306618 ps
CPU time 88.61 seconds
Started Jul 28 07:42:01 PM PDT 24
Finished Jul 28 07:43:30 PM PDT 24
Peak memory 216800 kb
Host smart-99d92194-5a39-487e-aa09-a0dcad4de626
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3347237281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.3347237281
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.1807076509
Short name T534
Test name
Test status
Simulation time 11295799589 ps
CPU time 79.79 seconds
Started Jul 28 07:42:05 PM PDT 24
Finished Jul 28 07:43:25 PM PDT 24
Peak memory 207424 kb
Host smart-bcb5065a-e883-417c-902a-0c5f1ae3221a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1807076509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.1807076509
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.4248802271
Short name T1089
Test name
Test status
Simulation time 211948891 ps
CPU time 0.92 seconds
Started Jul 28 07:42:06 PM PDT 24
Finished Jul 28 07:42:07 PM PDT 24
Peak memory 207128 kb
Host smart-f1a1d88b-c293-463e-8daf-aae67be79279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42488
02271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.4248802271
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1174545469
Short name T750
Test name
Test status
Simulation time 23305338565 ps
CPU time 28.94 seconds
Started Jul 28 07:41:51 PM PDT 24
Finished Jul 28 07:42:20 PM PDT 24
Peak memory 207376 kb
Host smart-e24850a6-adb5-43b9-9cea-4c709603c616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11745
45469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1174545469
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.723011727
Short name T484
Test name
Test status
Simulation time 3326711495 ps
CPU time 5.72 seconds
Started Jul 28 07:41:54 PM PDT 24
Finished Jul 28 07:42:00 PM PDT 24
Peak memory 207352 kb
Host smart-0a4ae5fe-7fcc-4209-a205-334aea52b6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72301
1727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.723011727
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.2002364611
Short name T1845
Test name
Test status
Simulation time 4754298687 ps
CPU time 47.28 seconds
Started Jul 28 07:42:02 PM PDT 24
Finished Jul 28 07:42:49 PM PDT 24
Peak memory 207348 kb
Host smart-10c2bd0b-07fe-439f-aea2-03560d617d66
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2002364611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.2002364611
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1204760758
Short name T921
Test name
Test status
Simulation time 313394414 ps
CPU time 1.05 seconds
Started Jul 28 07:42:06 PM PDT 24
Finished Jul 28 07:42:07 PM PDT 24
Peak memory 207136 kb
Host smart-cc7128c1-debc-4066-b068-39dbc3a5b374
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1204760758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1204760758
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3768059323
Short name T473
Test name
Test status
Simulation time 224403071 ps
CPU time 1 seconds
Started Jul 28 07:42:06 PM PDT 24
Finished Jul 28 07:42:07 PM PDT 24
Peak memory 207204 kb
Host smart-aaa29643-c8d0-4559-8fd6-e75566ab5343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37680
59323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3768059323
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.3414800859
Short name T153
Test name
Test status
Simulation time 3596694217 ps
CPU time 26.75 seconds
Started Jul 28 07:41:53 PM PDT 24
Finished Jul 28 07:42:20 PM PDT 24
Peak memory 215776 kb
Host smart-5b425104-154d-40eb-9ac1-65daeafe1505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34148
00859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.3414800859
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.1475195292
Short name T2589
Test name
Test status
Simulation time 4006468809 ps
CPU time 120.67 seconds
Started Jul 28 07:42:03 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 215632 kb
Host smart-7996bb7f-58b5-4399-a468-1d4c86a70c1f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1475195292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.1475195292
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.245123657
Short name T1544
Test name
Test status
Simulation time 158791499 ps
CPU time 0.85 seconds
Started Jul 28 07:41:54 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 207108 kb
Host smart-7c8c700f-6bd1-45bd-ac20-2ed0f869e4e2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=245123657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.245123657
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2202791383
Short name T868
Test name
Test status
Simulation time 142956797 ps
CPU time 0.82 seconds
Started Jul 28 07:41:53 PM PDT 24
Finished Jul 28 07:41:54 PM PDT 24
Peak memory 207156 kb
Host smart-aacacbe3-71ae-4d1b-a642-bb677de6c6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22027
91383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2202791383
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.1584659869
Short name T1371
Test name
Test status
Simulation time 246849670 ps
CPU time 0.97 seconds
Started Jul 28 07:41:54 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 207104 kb
Host smart-5cad0a7e-2def-46b9-a7bf-328536915a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15846
59869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.1584659869
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2778923636
Short name T487
Test name
Test status
Simulation time 150118283 ps
CPU time 0.83 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:41:57 PM PDT 24
Peak memory 207116 kb
Host smart-3d3075a0-6eb3-485e-939e-1471c64c8351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27789
23636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2778923636
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1557202753
Short name T681
Test name
Test status
Simulation time 199477465 ps
CPU time 0.93 seconds
Started Jul 28 07:41:54 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 207108 kb
Host smart-1fbc0cf7-3fc2-417e-b475-2bc101fd6428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15572
02753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1557202753
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2167794022
Short name T2013
Test name
Test status
Simulation time 151123332 ps
CPU time 0.88 seconds
Started Jul 28 07:41:54 PM PDT 24
Finished Jul 28 07:42:00 PM PDT 24
Peak memory 207120 kb
Host smart-3a2a31a0-3b2c-4e85-a985-34869bff5e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21677
94022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2167794022
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3968596752
Short name T822
Test name
Test status
Simulation time 202831050 ps
CPU time 0.95 seconds
Started Jul 28 07:41:57 PM PDT 24
Finished Jul 28 07:41:58 PM PDT 24
Peak memory 207052 kb
Host smart-83ae7d54-bdab-4839-853e-8e9d4b2eec49
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3968596752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3968596752
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2449264362
Short name T2730
Test name
Test status
Simulation time 140593471 ps
CPU time 0.82 seconds
Started Jul 28 07:41:53 PM PDT 24
Finished Jul 28 07:41:54 PM PDT 24
Peak memory 207128 kb
Host smart-9d8b82f1-4f83-45e4-8ea1-dc2f3a07eceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24492
64362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2449264362
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.124219886
Short name T664
Test name
Test status
Simulation time 37422911 ps
CPU time 0.7 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:42:02 PM PDT 24
Peak memory 207088 kb
Host smart-ac8e1f84-24a1-40ec-bef1-acf446ce0296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12421
9886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.124219886
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2429632923
Short name T2333
Test name
Test status
Simulation time 22412390391 ps
CPU time 57.67 seconds
Started Jul 28 07:42:05 PM PDT 24
Finished Jul 28 07:43:03 PM PDT 24
Peak memory 215644 kb
Host smart-d2962ebb-a4cd-4eec-a318-049e3f2dacc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24296
32923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2429632923
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1341681191
Short name T1811
Test name
Test status
Simulation time 201395476 ps
CPU time 0.92 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:41:57 PM PDT 24
Peak memory 207104 kb
Host smart-e4ed0b89-1a8a-4bda-b461-3ca339158a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13416
81191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1341681191
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.882056252
Short name T2350
Test name
Test status
Simulation time 238906207 ps
CPU time 0.94 seconds
Started Jul 28 07:42:09 PM PDT 24
Finished Jul 28 07:42:10 PM PDT 24
Peak memory 207156 kb
Host smart-4ff453ea-1448-45b1-aadb-78e71ac4b73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88205
6252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.882056252
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.2098938612
Short name T2762
Test name
Test status
Simulation time 235472209 ps
CPU time 1.08 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:41:58 PM PDT 24
Peak memory 207160 kb
Host smart-e5420c9d-6183-46f0-9d2a-e896cbb388a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20989
38612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.2098938612
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3402781010
Short name T362
Test name
Test status
Simulation time 248895509 ps
CPU time 0.97 seconds
Started Jul 28 07:41:54 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 207112 kb
Host smart-f03521d0-5aec-4099-bcec-5ae3a39a7147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34027
81010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3402781010
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.1422739629
Short name T1743
Test name
Test status
Simulation time 173681860 ps
CPU time 0.9 seconds
Started Jul 28 07:42:04 PM PDT 24
Finished Jul 28 07:42:05 PM PDT 24
Peak memory 207128 kb
Host smart-fd824148-e352-4988-984f-dd9e96079abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14227
39629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1422739629
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3863450841
Short name T1535
Test name
Test status
Simulation time 148932461 ps
CPU time 0.82 seconds
Started Jul 28 07:42:04 PM PDT 24
Finished Jul 28 07:42:05 PM PDT 24
Peak memory 207100 kb
Host smart-21ed11cc-ea81-49a0-90c2-b3e55453c5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38634
50841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3863450841
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2612735678
Short name T854
Test name
Test status
Simulation time 179086140 ps
CPU time 0.84 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:41:57 PM PDT 24
Peak memory 207128 kb
Host smart-d421f2b5-9fd2-4a13-b153-f4f75566d5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26127
35678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2612735678
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.216152457
Short name T2537
Test name
Test status
Simulation time 289500616 ps
CPU time 1.05 seconds
Started Jul 28 07:42:05 PM PDT 24
Finished Jul 28 07:42:06 PM PDT 24
Peak memory 207112 kb
Host smart-a73011d5-3653-4311-b188-0db33d25d288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21615
2457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.216152457
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.64650378
Short name T2552
Test name
Test status
Simulation time 4475382943 ps
CPU time 125.16 seconds
Started Jul 28 07:42:04 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 215744 kb
Host smart-637cd219-1b02-4053-a74c-dc22bd101708
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=64650378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.64650378
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.633778153
Short name T1718
Test name
Test status
Simulation time 181924434 ps
CPU time 0.87 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:09 PM PDT 24
Peak memory 207132 kb
Host smart-42964880-5155-4795-9b74-8a3e34a8bea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63377
8153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.633778153
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2202769826
Short name T1837
Test name
Test status
Simulation time 167275901 ps
CPU time 0.85 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:41:57 PM PDT 24
Peak memory 207116 kb
Host smart-4264a402-7b8d-4119-b2c0-7914f36dfbcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22027
69826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2202769826
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.489946501
Short name T2376
Test name
Test status
Simulation time 448455249 ps
CPU time 1.41 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:09 PM PDT 24
Peak memory 207236 kb
Host smart-d0517a73-9c83-4995-a29f-2c5e7bac4fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48994
6501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.489946501
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.2442710661
Short name T2173
Test name
Test status
Simulation time 5623439588 ps
CPU time 166.25 seconds
Started Jul 28 07:41:53 PM PDT 24
Finished Jul 28 07:44:39 PM PDT 24
Peak memory 215588 kb
Host smart-e3398b4a-b223-4530-ba88-f605273ef4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24427
10661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.2442710661
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.437466879
Short name T1786
Test name
Test status
Simulation time 2425723987 ps
CPU time 21.16 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:42:17 PM PDT 24
Peak memory 207268 kb
Host smart-79699d55-b5d6-4ff7-8209-18d71fbc3aa0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437466879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_host
_handshake.437466879
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.1419218094
Short name T1271
Test name
Test status
Simulation time 43643827 ps
CPU time 0.67 seconds
Started Jul 28 07:42:06 PM PDT 24
Finished Jul 28 07:42:07 PM PDT 24
Peak memory 207200 kb
Host smart-8da9a224-5784-4f9c-8f06-41cd9e22d27f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1419218094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.1419218094
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.2760569027
Short name T1240
Test name
Test status
Simulation time 4307490392 ps
CPU time 6.16 seconds
Started Jul 28 07:41:58 PM PDT 24
Finished Jul 28 07:42:04 PM PDT 24
Peak memory 207292 kb
Host smart-bb9f3dd3-6fcf-4303-8804-df8dc3ceb624
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760569027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.2760569027
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.782188466
Short name T2269
Test name
Test status
Simulation time 13386349716 ps
CPU time 15.33 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:42:12 PM PDT 24
Peak memory 207388 kb
Host smart-e72fd981-686d-4b86-bf0d-fc72d74b8d9b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=782188466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.782188466
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.3215295405
Short name T2683
Test name
Test status
Simulation time 23394967786 ps
CPU time 28.33 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:42:24 PM PDT 24
Peak memory 207360 kb
Host smart-92653c95-8171-4e5f-8a07-94fce38081d4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215295405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.3215295405
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1828125096
Short name T591
Test name
Test status
Simulation time 151015934 ps
CPU time 0.91 seconds
Started Jul 28 07:42:03 PM PDT 24
Finished Jul 28 07:42:04 PM PDT 24
Peak memory 207176 kb
Host smart-4559f000-ac92-431a-afe9-dbcac4eb6980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18281
25096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1828125096
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.4001629881
Short name T1873
Test name
Test status
Simulation time 148387770 ps
CPU time 0.86 seconds
Started Jul 28 07:41:57 PM PDT 24
Finished Jul 28 07:41:58 PM PDT 24
Peak memory 207020 kb
Host smart-8c0effdc-12c1-482c-bebb-7a9ef76301a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40016
29881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.4001629881
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.1488429264
Short name T506
Test name
Test status
Simulation time 226582196 ps
CPU time 1.09 seconds
Started Jul 28 07:41:57 PM PDT 24
Finished Jul 28 07:41:59 PM PDT 24
Peak memory 207068 kb
Host smart-08620412-2b61-49d9-887d-4ba16f0b3dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14884
29264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.1488429264
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.509341724
Short name T1879
Test name
Test status
Simulation time 731250279 ps
CPU time 1.86 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:10 PM PDT 24
Peak memory 207156 kb
Host smart-52562e83-4770-4eac-8979-1958c92558af
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=509341724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.509341724
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.1108769980
Short name T177
Test name
Test status
Simulation time 12162218715 ps
CPU time 24.38 seconds
Started Jul 28 07:42:07 PM PDT 24
Finished Jul 28 07:42:32 PM PDT 24
Peak memory 207364 kb
Host smart-934f684f-3f66-43b5-b81b-91df8812013d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11087
69980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.1108769980
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.3733175114
Short name T1155
Test name
Test status
Simulation time 4966646911 ps
CPU time 34.61 seconds
Started Jul 28 07:42:02 PM PDT 24
Finished Jul 28 07:42:36 PM PDT 24
Peak memory 207440 kb
Host smart-3897e19a-12f7-4a22-ad4c-c1e4778eb4a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733175114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.3733175114
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.376066354
Short name T2411
Test name
Test status
Simulation time 432556226 ps
CPU time 1.38 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:41:58 PM PDT 24
Peak memory 207096 kb
Host smart-ba20a98b-5193-4eec-968b-452d3c63bdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37606
6354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.376066354
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.3153051176
Short name T1634
Test name
Test status
Simulation time 134424790 ps
CPU time 0.87 seconds
Started Jul 28 07:42:10 PM PDT 24
Finished Jul 28 07:42:11 PM PDT 24
Peak memory 207036 kb
Host smart-bb52ad8a-98d0-4f7f-83d9-c2c5fdc3afb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31530
51176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3153051176
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1012494927
Short name T662
Test name
Test status
Simulation time 35567066 ps
CPU time 0.75 seconds
Started Jul 28 07:42:05 PM PDT 24
Finished Jul 28 07:42:06 PM PDT 24
Peak memory 207092 kb
Host smart-f570fd7e-630d-4b6d-aa9d-c06661f930e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10124
94927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1012494927
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.2763582553
Short name T1884
Test name
Test status
Simulation time 917441156 ps
CPU time 2.4 seconds
Started Jul 28 07:42:12 PM PDT 24
Finished Jul 28 07:42:14 PM PDT 24
Peak memory 207348 kb
Host smart-949bbf44-cd5b-49c8-8f89-505d6906fc22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27635
82553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.2763582553
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.4125668467
Short name T692
Test name
Test status
Simulation time 199921185 ps
CPU time 1.4 seconds
Started Jul 28 07:42:11 PM PDT 24
Finished Jul 28 07:42:13 PM PDT 24
Peak memory 207304 kb
Host smart-c5919a23-f68a-4bc5-811a-395e20e9b5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41256
68467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.4125668467
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2154615187
Short name T2509
Test name
Test status
Simulation time 230344678 ps
CPU time 1.05 seconds
Started Jul 28 07:42:07 PM PDT 24
Finished Jul 28 07:42:08 PM PDT 24
Peak memory 207392 kb
Host smart-c5bd29c5-32f7-4a36-80e9-2c9c1d1f48eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2154615187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2154615187
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2064128082
Short name T1350
Test name
Test status
Simulation time 143684501 ps
CPU time 0.87 seconds
Started Jul 28 07:42:19 PM PDT 24
Finished Jul 28 07:42:20 PM PDT 24
Peak memory 207128 kb
Host smart-c9657783-6ade-4c36-ae10-acca192b361c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20641
28082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2064128082
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3481044566
Short name T2712
Test name
Test status
Simulation time 209313674 ps
CPU time 0.93 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:09 PM PDT 24
Peak memory 207048 kb
Host smart-02732a8a-3917-4b99-9096-5ce3a94bfb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34810
44566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3481044566
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.2559623480
Short name T861
Test name
Test status
Simulation time 6713710606 ps
CPU time 66.12 seconds
Started Jul 28 07:42:07 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 217164 kb
Host smart-54e8c902-f34a-466a-96f6-f23c2e02df75
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2559623480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.2559623480
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.3131835445
Short name T1529
Test name
Test status
Simulation time 5517299325 ps
CPU time 41.35 seconds
Started Jul 28 07:42:15 PM PDT 24
Finished Jul 28 07:42:56 PM PDT 24
Peak memory 207296 kb
Host smart-9cb5767c-d44a-46e0-931f-4c09bec6a591
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3131835445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.3131835445
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3663450652
Short name T1062
Test name
Test status
Simulation time 232818284 ps
CPU time 0.98 seconds
Started Jul 28 07:42:19 PM PDT 24
Finished Jul 28 07:42:20 PM PDT 24
Peak memory 207160 kb
Host smart-2ce98cfc-8837-4486-8e4e-ba1a9ee08848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36634
50652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3663450652
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.3486158811
Short name T1762
Test name
Test status
Simulation time 23275569140 ps
CPU time 26.92 seconds
Started Jul 28 07:41:58 PM PDT 24
Finished Jul 28 07:42:25 PM PDT 24
Peak memory 207376 kb
Host smart-a3239f71-1856-4396-95dd-84acf8953ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34861
58811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.3486158811
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1123552240
Short name T411
Test name
Test status
Simulation time 3275006557 ps
CPU time 5.99 seconds
Started Jul 28 07:42:10 PM PDT 24
Finished Jul 28 07:42:16 PM PDT 24
Peak memory 207412 kb
Host smart-99ca3231-0e36-49ee-b876-b04bdcc7361e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11235
52240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1123552240
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.3653082932
Short name T1680
Test name
Test status
Simulation time 6160456155 ps
CPU time 176.22 seconds
Started Jul 28 07:41:59 PM PDT 24
Finished Jul 28 07:44:55 PM PDT 24
Peak memory 215616 kb
Host smart-6f962b5f-eb14-4862-a1b9-c79d6648c740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36530
82932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3653082932
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.1409031808
Short name T1477
Test name
Test status
Simulation time 7548902721 ps
CPU time 76.21 seconds
Started Jul 28 07:42:03 PM PDT 24
Finished Jul 28 07:43:19 PM PDT 24
Peak memory 207388 kb
Host smart-0b26df6d-7a95-4749-a510-81c52c27be45
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1409031808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.1409031808
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2487094199
Short name T378
Test name
Test status
Simulation time 241704449 ps
CPU time 1.1 seconds
Started Jul 28 07:42:02 PM PDT 24
Finished Jul 28 07:42:04 PM PDT 24
Peak memory 207192 kb
Host smart-56c62274-d765-43f9-90a2-087ee276230d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2487094199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2487094199
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1959418530
Short name T367
Test name
Test status
Simulation time 180942968 ps
CPU time 0.91 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207156 kb
Host smart-e4b863d4-c051-4a49-9d93-40a940c56f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19594
18530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1959418530
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.1247011041
Short name T2140
Test name
Test status
Simulation time 4440358239 ps
CPU time 127.04 seconds
Started Jul 28 07:41:58 PM PDT 24
Finished Jul 28 07:44:05 PM PDT 24
Peak memory 215552 kb
Host smart-cfeadedd-679b-45c7-b69f-3c33b60c4857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12470
11041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.1247011041
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.4256594658
Short name T2108
Test name
Test status
Simulation time 5485102062 ps
CPU time 41.69 seconds
Started Jul 28 07:41:57 PM PDT 24
Finished Jul 28 07:42:39 PM PDT 24
Peak memory 207376 kb
Host smart-62a9613a-738e-4bba-9a78-9eee085acb31
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4256594658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.4256594658
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.3974864114
Short name T1203
Test name
Test status
Simulation time 203060325 ps
CPU time 0.9 seconds
Started Jul 28 07:41:58 PM PDT 24
Finished Jul 28 07:41:59 PM PDT 24
Peak memory 207132 kb
Host smart-f1c829ea-7e8b-466b-a53c-6d4c9f63906e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3974864114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.3974864114
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.274510146
Short name T1376
Test name
Test status
Simulation time 151220067 ps
CPU time 0.82 seconds
Started Jul 28 07:42:01 PM PDT 24
Finished Jul 28 07:42:02 PM PDT 24
Peak memory 207060 kb
Host smart-81b0dd4c-02d4-4d1a-8028-db2ed9dd656a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27451
0146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.274510146
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.317538310
Short name T864
Test name
Test status
Simulation time 179673897 ps
CPU time 0.89 seconds
Started Jul 28 07:42:04 PM PDT 24
Finished Jul 28 07:42:05 PM PDT 24
Peak memory 207104 kb
Host smart-7cdf6cef-6ae0-4c5f-9dbf-976aa238b544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31753
8310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.317538310
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1451178280
Short name T2209
Test name
Test status
Simulation time 194609501 ps
CPU time 0.91 seconds
Started Jul 28 07:42:04 PM PDT 24
Finished Jul 28 07:42:05 PM PDT 24
Peak memory 207116 kb
Host smart-beec3c12-42e9-4b94-8776-e613e65f429a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14511
78280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1451178280
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.121802819
Short name T1380
Test name
Test status
Simulation time 186278946 ps
CPU time 0.93 seconds
Started Jul 28 07:41:59 PM PDT 24
Finished Jul 28 07:42:00 PM PDT 24
Peak memory 207052 kb
Host smart-2dc46d27-1823-405d-b922-bf35c619fea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12180
2819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.121802819
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1501744255
Short name T2149
Test name
Test status
Simulation time 151495499 ps
CPU time 0.82 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:09 PM PDT 24
Peak memory 207112 kb
Host smart-22cdf598-0c0b-458f-bee5-c6df221c2f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15017
44255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1501744255
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2675057694
Short name T855
Test name
Test status
Simulation time 207197862 ps
CPU time 0.97 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:42:14 PM PDT 24
Peak memory 207176 kb
Host smart-b7d0600c-4c8c-47b3-931e-e8fa88ee7820
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2675057694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2675057694
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1318133865
Short name T804
Test name
Test status
Simulation time 231033601 ps
CPU time 0.92 seconds
Started Jul 28 07:42:07 PM PDT 24
Finished Jul 28 07:42:08 PM PDT 24
Peak memory 207076 kb
Host smart-bc12fe9c-b03d-455d-a62b-1e4b02b66ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13181
33865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1318133865
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.852786462
Short name T805
Test name
Test status
Simulation time 40694454 ps
CPU time 0.7 seconds
Started Jul 28 07:42:06 PM PDT 24
Finished Jul 28 07:42:07 PM PDT 24
Peak memory 207120 kb
Host smart-1e1e9d34-ac41-4089-9216-911f5f7b9c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85278
6462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.852786462
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.832178730
Short name T2672
Test name
Test status
Simulation time 22037239593 ps
CPU time 55.64 seconds
Started Jul 28 07:42:20 PM PDT 24
Finished Jul 28 07:43:16 PM PDT 24
Peak memory 215672 kb
Host smart-b515e6f1-594c-45a0-a3b4-1beb8f8654f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83217
8730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.832178730
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2333543295
Short name T2772
Test name
Test status
Simulation time 153163416 ps
CPU time 0.82 seconds
Started Jul 28 07:41:57 PM PDT 24
Finished Jul 28 07:41:58 PM PDT 24
Peak memory 207076 kb
Host smart-e417e979-6220-4241-8e5f-633394b648fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23335
43295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2333543295
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.4122297201
Short name T382
Test name
Test status
Simulation time 252331738 ps
CPU time 0.99 seconds
Started Jul 28 07:42:12 PM PDT 24
Finished Jul 28 07:42:14 PM PDT 24
Peak memory 207072 kb
Host smart-84f44815-412d-4c8a-a4c3-feee8f2fbf5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41222
97201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.4122297201
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.2283207479
Short name T2483
Test name
Test status
Simulation time 225700284 ps
CPU time 0.96 seconds
Started Jul 28 07:41:57 PM PDT 24
Finished Jul 28 07:41:58 PM PDT 24
Peak memory 207136 kb
Host smart-73dcc6c8-4cb8-42e1-9835-104624edf63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22832
07479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2283207479
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.2352621789
Short name T1345
Test name
Test status
Simulation time 145273230 ps
CPU time 0.86 seconds
Started Jul 28 07:41:57 PM PDT 24
Finished Jul 28 07:41:58 PM PDT 24
Peak memory 207056 kb
Host smart-451f885a-33af-473d-8f2f-6230135e2ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23526
21789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.2352621789
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.196247146
Short name T2783
Test name
Test status
Simulation time 180947568 ps
CPU time 0.9 seconds
Started Jul 28 07:42:10 PM PDT 24
Finished Jul 28 07:42:11 PM PDT 24
Peak memory 207172 kb
Host smart-4bf01b8c-3e3b-4d3b-b810-23de18e4af57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19624
7146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.196247146
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2365887732
Short name T2288
Test name
Test status
Simulation time 177055984 ps
CPU time 0.88 seconds
Started Jul 28 07:42:15 PM PDT 24
Finished Jul 28 07:42:16 PM PDT 24
Peak memory 207024 kb
Host smart-3f25c963-c1da-4560-a4bd-ea485cfa0160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23658
87732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2365887732
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2230577940
Short name T457
Test name
Test status
Simulation time 188812476 ps
CPU time 0.87 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207132 kb
Host smart-9326da4b-a0cc-4f9a-a4dd-1306e2ec298b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22305
77940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2230577940
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3510872275
Short name T497
Test name
Test status
Simulation time 219276942 ps
CPU time 1.02 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:10 PM PDT 24
Peak memory 207120 kb
Host smart-4def1abd-1daf-4b8f-9c50-fc286ea536d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35108
72275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3510872275
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.1904489105
Short name T152
Test name
Test status
Simulation time 3521790375 ps
CPU time 101.51 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:43:54 PM PDT 24
Peak memory 215508 kb
Host smart-ae02ebe5-a09b-4e37-bf42-c0f4f4a41bcb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1904489105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.1904489105
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2352402701
Short name T1429
Test name
Test status
Simulation time 168508770 ps
CPU time 0.88 seconds
Started Jul 28 07:42:15 PM PDT 24
Finished Jul 28 07:42:16 PM PDT 24
Peak memory 207124 kb
Host smart-defcbf27-9e08-4164-a7bd-cf9bf15caab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23524
02701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2352402701
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.571649825
Short name T271
Test name
Test status
Simulation time 213957177 ps
CPU time 0.99 seconds
Started Jul 28 07:42:16 PM PDT 24
Finished Jul 28 07:42:17 PM PDT 24
Peak memory 207120 kb
Host smart-687c1fe4-f2c4-4357-b3bc-c96f0ecd8dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57164
9825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.571649825
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.1197973655
Short name T782
Test name
Test status
Simulation time 905399850 ps
CPU time 2.32 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:42:16 PM PDT 24
Peak memory 207280 kb
Host smart-8a7afa48-2b3e-44eb-b4cf-50a4be5ac65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11979
73655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.1197973655
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.971319414
Short name T1673
Test name
Test status
Simulation time 3331865808 ps
CPU time 34.67 seconds
Started Jul 28 07:42:15 PM PDT 24
Finished Jul 28 07:42:50 PM PDT 24
Peak memory 216860 kb
Host smart-4575bb5c-a051-4b88-9dd4-f8b6f3f83c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97131
9414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.971319414
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.1603636849
Short name T1620
Test name
Test status
Simulation time 2006470058 ps
CPU time 16.75 seconds
Started Jul 28 07:41:56 PM PDT 24
Finished Jul 28 07:42:13 PM PDT 24
Peak memory 207352 kb
Host smart-2d363202-f32e-4396-b876-a4e2c5c71ba4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603636849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.1603636849
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.7560423
Short name T1296
Test name
Test status
Simulation time 42771035 ps
CPU time 0.68 seconds
Started Jul 28 07:42:15 PM PDT 24
Finished Jul 28 07:42:16 PM PDT 24
Peak memory 207280 kb
Host smart-4d153784-364f-4315-bd05-7dc2ebce3f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=7560423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.7560423
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.1103667672
Short name T2143
Test name
Test status
Simulation time 13500826923 ps
CPU time 15.57 seconds
Started Jul 28 07:42:11 PM PDT 24
Finished Jul 28 07:42:27 PM PDT 24
Peak memory 207372 kb
Host smart-59322015-de4f-4e43-9e2e-181b5afb17d9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103667672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.1103667672
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.461691467
Short name T2840
Test name
Test status
Simulation time 23373740486 ps
CPU time 35.05 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:42:48 PM PDT 24
Peak memory 207288 kb
Host smart-1a4716f2-2942-49bc-963c-35f566dcb8dd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461691467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_ao
n_wake_resume.461691467
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.378399386
Short name T2059
Test name
Test status
Simulation time 182936622 ps
CPU time 0.87 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:42:14 PM PDT 24
Peak memory 207120 kb
Host smart-e5bffd69-7a0f-4b3f-b719-3c9991cfbc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37839
9386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.378399386
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1324750147
Short name T935
Test name
Test status
Simulation time 158614981 ps
CPU time 0.87 seconds
Started Jul 28 07:42:10 PM PDT 24
Finished Jul 28 07:42:11 PM PDT 24
Peak memory 207124 kb
Host smart-5881ac9f-4c52-4b86-bbe9-ef9cd78ebcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13247
50147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1324750147
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.3123413343
Short name T2163
Test name
Test status
Simulation time 514126653 ps
CPU time 1.76 seconds
Started Jul 28 07:42:12 PM PDT 24
Finished Jul 28 07:42:14 PM PDT 24
Peak memory 207112 kb
Host smart-b54f1878-9844-48eb-a7e3-d556246bd2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31234
13343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3123413343
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1470342578
Short name T1571
Test name
Test status
Simulation time 367638645 ps
CPU time 1.28 seconds
Started Jul 28 07:42:09 PM PDT 24
Finished Jul 28 07:42:10 PM PDT 24
Peak memory 207120 kb
Host smart-3b60a7f0-7c6e-4f7e-a011-ab38bde18fb5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1470342578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1470342578
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.291165583
Short name T1028
Test name
Test status
Simulation time 7123065421 ps
CPU time 17.87 seconds
Started Jul 28 07:42:07 PM PDT 24
Finished Jul 28 07:42:25 PM PDT 24
Peak memory 207480 kb
Host smart-14b0617d-36ac-4dc2-b349-8d5364dffa2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29116
5583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.291165583
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.862133067
Short name T1939
Test name
Test status
Simulation time 3009167955 ps
CPU time 24.14 seconds
Started Jul 28 07:42:14 PM PDT 24
Finished Jul 28 07:42:39 PM PDT 24
Peak memory 207416 kb
Host smart-95dcb247-b8bd-4219-b766-c2ce08148cf8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862133067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.862133067
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.4113735858
Short name T2770
Test name
Test status
Simulation time 513617942 ps
CPU time 1.56 seconds
Started Jul 28 07:42:19 PM PDT 24
Finished Jul 28 07:42:20 PM PDT 24
Peak memory 207048 kb
Host smart-81b82af0-7710-48d3-9cbc-7c892216aae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41137
35858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.4113735858
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2818992682
Short name T585
Test name
Test status
Simulation time 165164690 ps
CPU time 0.91 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:09 PM PDT 24
Peak memory 207120 kb
Host smart-63ea4323-c748-4448-b1ef-4d2ece39f150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28189
92682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2818992682
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.3564447808
Short name T324
Test name
Test status
Simulation time 44213447 ps
CPU time 0.71 seconds
Started Jul 28 07:42:14 PM PDT 24
Finished Jul 28 07:42:15 PM PDT 24
Peak memory 207044 kb
Host smart-17aa223b-ceb6-4d17-9131-cd9fe780da79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35644
47808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3564447808
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.47461818
Short name T1570
Test name
Test status
Simulation time 816721492 ps
CPU time 2.22 seconds
Started Jul 28 07:42:11 PM PDT 24
Finished Jul 28 07:42:13 PM PDT 24
Peak memory 207396 kb
Host smart-75e19323-03a9-43e5-870b-b93130331033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47461
818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.47461818
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2473789239
Short name T2323
Test name
Test status
Simulation time 212687744 ps
CPU time 1.57 seconds
Started Jul 28 07:42:15 PM PDT 24
Finished Jul 28 07:42:17 PM PDT 24
Peak memory 207268 kb
Host smart-88057804-c943-488e-9112-bf3b8deafcc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24737
89239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2473789239
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.184387963
Short name T1057
Test name
Test status
Simulation time 244933894 ps
CPU time 1.1 seconds
Started Jul 28 07:42:05 PM PDT 24
Finished Jul 28 07:42:07 PM PDT 24
Peak memory 215568 kb
Host smart-e17c2237-476e-4fb7-974a-949383fe77b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=184387963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.184387963
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.4258263991
Short name T624
Test name
Test status
Simulation time 145772137 ps
CPU time 0.94 seconds
Started Jul 28 07:42:16 PM PDT 24
Finished Jul 28 07:42:17 PM PDT 24
Peak memory 207128 kb
Host smart-ea1cfc32-8b67-4440-b33b-131cda4660ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42582
63991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.4258263991
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2217354272
Short name T1042
Test name
Test status
Simulation time 183665721 ps
CPU time 0.9 seconds
Started Jul 28 07:42:16 PM PDT 24
Finished Jul 28 07:42:17 PM PDT 24
Peak memory 207052 kb
Host smart-e1960189-d1f5-4df7-81db-9370763cf78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22173
54272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2217354272
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.3160569429
Short name T1503
Test name
Test status
Simulation time 8061499171 ps
CPU time 82.87 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:43:36 PM PDT 24
Peak memory 217176 kb
Host smart-73070e87-f59d-4af8-b66a-bcbd7f8a3c37
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3160569429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.3160569429
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.3352371052
Short name T1174
Test name
Test status
Simulation time 5857700781 ps
CPU time 70.09 seconds
Started Jul 28 07:42:12 PM PDT 24
Finished Jul 28 07:43:22 PM PDT 24
Peak memory 207272 kb
Host smart-17d2c3f8-fe69-44db-a442-1693edab1f75
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3352371052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.3352371052
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3435246635
Short name T1031
Test name
Test status
Simulation time 224173447 ps
CPU time 0.95 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:42:14 PM PDT 24
Peak memory 207100 kb
Host smart-71561f5a-3bc1-4493-a9e6-6b1006ef84c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34352
46635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3435246635
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.2763900006
Short name T1218
Test name
Test status
Simulation time 23341559808 ps
CPU time 27.5 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:36 PM PDT 24
Peak memory 207396 kb
Host smart-55fbf668-26e0-40e8-9a99-b040fa81a6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27639
00006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.2763900006
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1859303058
Short name T389
Test name
Test status
Simulation time 3359891838 ps
CPU time 4.95 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:42:18 PM PDT 24
Peak memory 207300 kb
Host smart-948e87f7-6f7b-4588-8dd4-8c8add16b331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18593
03058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1859303058
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.91638141
Short name T526
Test name
Test status
Simulation time 7817994870 ps
CPU time 77.03 seconds
Started Jul 28 07:42:04 PM PDT 24
Finished Jul 28 07:43:21 PM PDT 24
Peak memory 223716 kb
Host smart-e15e2e49-99de-4b87-b51c-809c45190bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91638
141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.91638141
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1688412812
Short name T2677
Test name
Test status
Simulation time 5495822860 ps
CPU time 162.31 seconds
Started Jul 28 07:42:17 PM PDT 24
Finished Jul 28 07:44:59 PM PDT 24
Peak memory 223500 kb
Host smart-b302e8ca-6d2c-4d2e-8275-96bf916c9c1c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1688412812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1688412812
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.2880589307
Short name T1044
Test name
Test status
Simulation time 266954062 ps
CPU time 1.03 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207152 kb
Host smart-f3f698de-906c-4735-8159-9dc543611a1a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2880589307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.2880589307
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2171646339
Short name T1147
Test name
Test status
Simulation time 205280231 ps
CPU time 0.96 seconds
Started Jul 28 07:42:17 PM PDT 24
Finished Jul 28 07:42:18 PM PDT 24
Peak memory 207204 kb
Host smart-a9e12fc2-c2a7-4c34-8245-b0ee8edf90dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21716
46339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2171646339
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.1824437359
Short name T1963
Test name
Test status
Simulation time 5856834574 ps
CPU time 60.24 seconds
Started Jul 28 07:42:22 PM PDT 24
Finished Jul 28 07:43:22 PM PDT 24
Peak memory 215588 kb
Host smart-287ff3a9-5315-4c9c-b455-9cb667b76d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18244
37359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.1824437359
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.2382483048
Short name T2620
Test name
Test status
Simulation time 7287089866 ps
CPU time 70.08 seconds
Started Jul 28 07:42:19 PM PDT 24
Finished Jul 28 07:43:29 PM PDT 24
Peak memory 207372 kb
Host smart-7067aec2-c4a4-4837-b248-ba8f8b51a4b8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2382483048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.2382483048
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.2902395917
Short name T397
Test name
Test status
Simulation time 163429323 ps
CPU time 0.87 seconds
Started Jul 28 07:42:11 PM PDT 24
Finished Jul 28 07:42:13 PM PDT 24
Peak memory 207120 kb
Host smart-6cdd5132-4e46-447c-9da5-f4e36ad99f42
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2902395917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.2902395917
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2251258581
Short name T606
Test name
Test status
Simulation time 171952405 ps
CPU time 0.88 seconds
Started Jul 28 07:42:14 PM PDT 24
Finished Jul 28 07:42:15 PM PDT 24
Peak memory 207148 kb
Host smart-68f515dd-2e36-476b-9582-bdc58586abb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22512
58581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2251258581
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1387700237
Short name T2131
Test name
Test status
Simulation time 187314263 ps
CPU time 0.96 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:42:20 PM PDT 24
Peak memory 207132 kb
Host smart-263515ce-a158-4c5b-892f-f9f970f8b2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13877
00237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1387700237
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.2876545664
Short name T2368
Test name
Test status
Simulation time 195930755 ps
CPU time 0.93 seconds
Started Jul 28 07:42:15 PM PDT 24
Finished Jul 28 07:42:16 PM PDT 24
Peak memory 207128 kb
Host smart-50ca5d02-3038-4f82-9a88-e85eb61ff932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28765
45664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.2876545664
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2639031420
Short name T1458
Test name
Test status
Simulation time 218578825 ps
CPU time 0.99 seconds
Started Jul 28 07:42:17 PM PDT 24
Finished Jul 28 07:42:18 PM PDT 24
Peak memory 207112 kb
Host smart-cd203c21-f7b3-45d6-af8b-4e3703b493f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26390
31420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2639031420
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1965480156
Short name T885
Test name
Test status
Simulation time 228236389 ps
CPU time 0.92 seconds
Started Jul 28 07:42:08 PM PDT 24
Finished Jul 28 07:42:09 PM PDT 24
Peak memory 207156 kb
Host smart-d354c2cf-fb07-45a5-adf3-fddf43f1f5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19654
80156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1965480156
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1404970219
Short name T1564
Test name
Test status
Simulation time 219777226 ps
CPU time 0.92 seconds
Started Jul 28 07:42:11 PM PDT 24
Finished Jul 28 07:42:12 PM PDT 24
Peak memory 207148 kb
Host smart-b0697d68-9d21-425c-bdcc-735e156cd824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14049
70219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1404970219
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.243129602
Short name T2736
Test name
Test status
Simulation time 259363727 ps
CPU time 1.09 seconds
Started Jul 28 07:42:22 PM PDT 24
Finished Jul 28 07:42:23 PM PDT 24
Peak memory 207132 kb
Host smart-b9b9aac4-9303-4646-83a4-404d63b3ae3b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=243129602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.243129602
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.887692488
Short name T1548
Test name
Test status
Simulation time 139583772 ps
CPU time 0.81 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:42:14 PM PDT 24
Peak memory 207032 kb
Host smart-a1c0bc3a-bd7c-43c9-a833-f2c5b8863009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88769
2488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.887692488
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1918573510
Short name T2114
Test name
Test status
Simulation time 31617985 ps
CPU time 0.7 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207092 kb
Host smart-883dac7b-5041-49ed-9b1f-2c0f338121e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19185
73510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1918573510
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1608454678
Short name T1232
Test name
Test status
Simulation time 8146189499 ps
CPU time 23.92 seconds
Started Jul 28 07:42:11 PM PDT 24
Finished Jul 28 07:42:35 PM PDT 24
Peak memory 215636 kb
Host smart-4e06cc94-c84a-46a8-81e5-5a4506844e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16084
54678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1608454678
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1693001436
Short name T2585
Test name
Test status
Simulation time 148213366 ps
CPU time 0.85 seconds
Started Jul 28 07:42:17 PM PDT 24
Finished Jul 28 07:42:18 PM PDT 24
Peak memory 207116 kb
Host smart-d969b944-db7e-44f1-a597-64dc2091bbdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16930
01436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1693001436
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1850592070
Short name T424
Test name
Test status
Simulation time 225415335 ps
CPU time 0.99 seconds
Started Jul 28 07:42:12 PM PDT 24
Finished Jul 28 07:42:13 PM PDT 24
Peak memory 207192 kb
Host smart-f37be580-9c74-44c6-baf8-4968c33bf01b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18505
92070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1850592070
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.3112149759
Short name T309
Test name
Test status
Simulation time 235230951 ps
CPU time 1 seconds
Started Jul 28 07:42:16 PM PDT 24
Finished Jul 28 07:42:17 PM PDT 24
Peak memory 207120 kb
Host smart-3604e271-4532-40c8-a638-1b0069fc7903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31121
49759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.3112149759
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.2771041714
Short name T2012
Test name
Test status
Simulation time 202585286 ps
CPU time 0.94 seconds
Started Jul 28 07:42:37 PM PDT 24
Finished Jul 28 07:42:38 PM PDT 24
Peak memory 207160 kb
Host smart-110c64cc-03a3-407d-8ce9-ac11aec72e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27710
41714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.2771041714
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3403920093
Short name T2631
Test name
Test status
Simulation time 153728728 ps
CPU time 0.85 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207116 kb
Host smart-7892956f-285d-4fe2-bcbe-06723542282b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34039
20093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3403920093
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3731675108
Short name T454
Test name
Test status
Simulation time 193727681 ps
CPU time 0.88 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:42:14 PM PDT 24
Peak memory 207072 kb
Host smart-533174fb-2148-45f2-b47a-ce200341c788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37316
75108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3731675108
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2054356768
Short name T2119
Test name
Test status
Simulation time 159557110 ps
CPU time 0.86 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207108 kb
Host smart-2e1c9edf-e6e3-47af-83b6-fb8227b657d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20543
56768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2054356768
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2878724596
Short name T1201
Test name
Test status
Simulation time 245861772 ps
CPU time 1.04 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:42:14 PM PDT 24
Peak memory 207152 kb
Host smart-ccef30fb-7252-43ec-8cee-f7ca25af82be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28787
24596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2878724596
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2840161945
Short name T2853
Test name
Test status
Simulation time 4519112478 ps
CPU time 36.51 seconds
Started Jul 28 07:42:16 PM PDT 24
Finished Jul 28 07:42:52 PM PDT 24
Peak memory 215592 kb
Host smart-23d35c98-6950-4900-bfdb-98659da260ce
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2840161945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2840161945
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1654049596
Short name T1744
Test name
Test status
Simulation time 177001982 ps
CPU time 0.89 seconds
Started Jul 28 07:42:19 PM PDT 24
Finished Jul 28 07:42:20 PM PDT 24
Peak memory 207180 kb
Host smart-cfc14e22-c89c-4c15-973b-aaf73b8ee90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16540
49596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1654049596
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2414484395
Short name T272
Test name
Test status
Simulation time 220747903 ps
CPU time 0.95 seconds
Started Jul 28 07:42:19 PM PDT 24
Finished Jul 28 07:42:20 PM PDT 24
Peak memory 207140 kb
Host smart-8dd03e7b-cfda-4e0a-9360-9256be1a8077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24144
84395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2414484395
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.358626312
Short name T2343
Test name
Test status
Simulation time 608496730 ps
CPU time 1.64 seconds
Started Jul 28 07:42:14 PM PDT 24
Finished Jul 28 07:42:16 PM PDT 24
Peak memory 207020 kb
Host smart-96f0cd7a-9163-4be3-9c81-49a87c4885db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35862
6312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.358626312
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.141402475
Short name T2076
Test name
Test status
Simulation time 3398737623 ps
CPU time 24.89 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:42:43 PM PDT 24
Peak memory 215540 kb
Host smart-3f721ca8-fab3-4a2f-8c6e-fc804c66e276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14140
2475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.141402475
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.2807192277
Short name T1640
Test name
Test status
Simulation time 1306217089 ps
CPU time 30.28 seconds
Started Jul 28 07:42:07 PM PDT 24
Finished Jul 28 07:42:38 PM PDT 24
Peak memory 207424 kb
Host smart-9f998c0c-e2dd-4286-a2d9-aacd89ee02cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807192277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.2807192277
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.736904274
Short name T2862
Test name
Test status
Simulation time 104034827 ps
CPU time 0.75 seconds
Started Jul 28 07:42:25 PM PDT 24
Finished Jul 28 07:42:26 PM PDT 24
Peak memory 207160 kb
Host smart-e7598c2c-cd27-419a-9454-a9ae0fa661b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=736904274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.736904274
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.4126808199
Short name T2046
Test name
Test status
Simulation time 3639495038 ps
CPU time 5.22 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:42:23 PM PDT 24
Peak memory 207564 kb
Host smart-caf6841b-93db-4764-a57f-dbc0319ef4c4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126808199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.4126808199
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.277661525
Short name T12
Test name
Test status
Simulation time 13342466227 ps
CPU time 17.68 seconds
Started Jul 28 07:42:13 PM PDT 24
Finished Jul 28 07:42:31 PM PDT 24
Peak memory 207436 kb
Host smart-601de793-9f82-4bf2-8344-7d896dbb858d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=277661525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.277661525
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.107360294
Short name T2056
Test name
Test status
Simulation time 23321848488 ps
CPU time 27.81 seconds
Started Jul 28 07:42:17 PM PDT 24
Finished Jul 28 07:42:45 PM PDT 24
Peak memory 207332 kb
Host smart-7b7a3471-d1fa-4d6a-a137-b7094071c4ca
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107360294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_ao
n_wake_resume.107360294
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.464425387
Short name T1576
Test name
Test status
Simulation time 157873673 ps
CPU time 0.84 seconds
Started Jul 28 07:42:12 PM PDT 24
Finished Jul 28 07:42:13 PM PDT 24
Peak memory 207200 kb
Host smart-4bddaa24-9cd0-424c-83f6-09c221fab5c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46442
5387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.464425387
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.3555103234
Short name T1650
Test name
Test status
Simulation time 144464477 ps
CPU time 0.79 seconds
Started Jul 28 07:42:12 PM PDT 24
Finished Jul 28 07:42:13 PM PDT 24
Peak memory 207172 kb
Host smart-eeaf67ef-a56b-4ab1-a2c8-0e579226d3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35551
03234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.3555103234
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2310036745
Short name T1802
Test name
Test status
Simulation time 322655067 ps
CPU time 1.21 seconds
Started Jul 28 07:42:17 PM PDT 24
Finished Jul 28 07:42:18 PM PDT 24
Peak memory 207156 kb
Host smart-1b8bbbae-d6f9-4f10-9f17-d4572d24f547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23100
36745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2310036745
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.1781688778
Short name T1171
Test name
Test status
Simulation time 850434497 ps
CPU time 2.75 seconds
Started Jul 28 07:42:20 PM PDT 24
Finished Jul 28 07:42:23 PM PDT 24
Peak memory 207260 kb
Host smart-be02ea80-3df1-47ea-82c7-762ada6523c2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1781688778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1781688778
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.4039643198
Short name T166
Test name
Test status
Simulation time 14926460141 ps
CPU time 35.07 seconds
Started Jul 28 07:42:19 PM PDT 24
Finished Jul 28 07:42:54 PM PDT 24
Peak memory 207412 kb
Host smart-ec2d41f4-5c22-4191-989e-7ea2cf83764b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
43198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.4039643198
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.1238821626
Short name T1096
Test name
Test status
Simulation time 1056245145 ps
CPU time 9.45 seconds
Started Jul 28 07:42:44 PM PDT 24
Finished Jul 28 07:42:54 PM PDT 24
Peak memory 207240 kb
Host smart-3bc9b832-f2d2-42cf-99c1-26e3f3f0a1ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238821626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.1238821626
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1534758363
Short name T755
Test name
Test status
Simulation time 370233667 ps
CPU time 1.36 seconds
Started Jul 28 07:42:15 PM PDT 24
Finished Jul 28 07:42:16 PM PDT 24
Peak memory 207132 kb
Host smart-c38dd2ac-6e2e-47b5-9679-632c96010462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15347
58363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1534758363
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.4012077183
Short name T480
Test name
Test status
Simulation time 184424723 ps
CPU time 0.88 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207128 kb
Host smart-6e8adeb2-eeb9-4c55-acaa-8515ba4321fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40120
77183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.4012077183
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.3728966565
Short name T2340
Test name
Test status
Simulation time 65091589 ps
CPU time 0.75 seconds
Started Jul 28 07:42:26 PM PDT 24
Finished Jul 28 07:42:27 PM PDT 24
Peak memory 207084 kb
Host smart-482f1c9c-e2f9-40e8-967e-dd3adc503252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37289
66565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3728966565
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.2505359629
Short name T1733
Test name
Test status
Simulation time 878334481 ps
CPU time 2.14 seconds
Started Jul 28 07:42:16 PM PDT 24
Finished Jul 28 07:42:18 PM PDT 24
Peak memory 207296 kb
Host smart-c6145573-95af-43b3-8086-c3fd20c4dafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25053
59629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2505359629
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3174678309
Short name T1558
Test name
Test status
Simulation time 214185096 ps
CPU time 1.48 seconds
Started Jul 28 07:42:19 PM PDT 24
Finished Jul 28 07:42:20 PM PDT 24
Peak memory 207236 kb
Host smart-4d4b223e-751b-4c82-8655-9e2e631156c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31746
78309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3174678309
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2576169189
Short name T1720
Test name
Test status
Simulation time 212401259 ps
CPU time 1.2 seconds
Started Jul 28 07:42:27 PM PDT 24
Finished Jul 28 07:42:29 PM PDT 24
Peak memory 215508 kb
Host smart-5a7f4ffb-bf5a-48f7-85d2-942834ce6ec6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2576169189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2576169189
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3127449270
Short name T1785
Test name
Test status
Simulation time 177555234 ps
CPU time 0.9 seconds
Started Jul 28 07:42:21 PM PDT 24
Finished Jul 28 07:42:22 PM PDT 24
Peak memory 207240 kb
Host smart-e6136ea7-3ad3-4e84-ba20-52255f5ccb55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31274
49270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3127449270
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1743330061
Short name T770
Test name
Test status
Simulation time 231965143 ps
CPU time 0.97 seconds
Started Jul 28 07:42:21 PM PDT 24
Finished Jul 28 07:42:22 PM PDT 24
Peak memory 207128 kb
Host smart-ca77aa2b-4d5a-46fa-9bf0-35d327017849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17433
30061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1743330061
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.532180300
Short name T1384
Test name
Test status
Simulation time 7677809774 ps
CPU time 78.86 seconds
Started Jul 28 07:42:20 PM PDT 24
Finished Jul 28 07:43:39 PM PDT 24
Peak memory 216552 kb
Host smart-db155793-d588-4a1b-8c44-716bb3dd1b50
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=532180300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.532180300
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.2561529397
Short name T94
Test name
Test status
Simulation time 8400031789 ps
CPU time 97.3 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:43:55 PM PDT 24
Peak memory 207412 kb
Host smart-d488df03-7561-44eb-a058-4d11eb211407
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2561529397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.2561529397
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3219773838
Short name T1146
Test name
Test status
Simulation time 169103966 ps
CPU time 0.88 seconds
Started Jul 28 07:42:24 PM PDT 24
Finished Jul 28 07:42:25 PM PDT 24
Peak memory 207120 kb
Host smart-ddd1d17a-27da-4bd6-849f-7c3bb6728350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32197
73838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3219773838
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.976999483
Short name T2168
Test name
Test status
Simulation time 23365723175 ps
CPU time 26.4 seconds
Started Jul 28 07:42:27 PM PDT 24
Finished Jul 28 07:42:53 PM PDT 24
Peak memory 207416 kb
Host smart-27042adb-01ed-4ecf-9309-1e1933df4787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97699
9483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.976999483
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2613047368
Short name T2471
Test name
Test status
Simulation time 3285258976 ps
CPU time 4.76 seconds
Started Jul 28 07:42:20 PM PDT 24
Finished Jul 28 07:42:25 PM PDT 24
Peak memory 207360 kb
Host smart-70aac5db-b700-4778-b7e8-9e512875c3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26130
47368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2613047368
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3509835383
Short name T860
Test name
Test status
Simulation time 6588414345 ps
CPU time 65.75 seconds
Started Jul 28 07:42:27 PM PDT 24
Finished Jul 28 07:43:33 PM PDT 24
Peak memory 217512 kb
Host smart-3aa2ccf9-bb9c-4873-941e-91047cac551e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35098
35383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3509835383
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.2342289280
Short name T1442
Test name
Test status
Simulation time 7351699425 ps
CPU time 217.48 seconds
Started Jul 28 07:42:22 PM PDT 24
Finished Jul 28 07:45:59 PM PDT 24
Peak memory 215568 kb
Host smart-d738f710-e285-4691-a11a-118efa33a956
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2342289280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.2342289280
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1943553015
Short name T2477
Test name
Test status
Simulation time 239973633 ps
CPU time 0.95 seconds
Started Jul 28 07:42:26 PM PDT 24
Finished Jul 28 07:42:28 PM PDT 24
Peak memory 207168 kb
Host smart-74eed89a-f314-47cc-a3c0-78bb85865333
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1943553015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1943553015
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3671694628
Short name T1610
Test name
Test status
Simulation time 199106445 ps
CPU time 0.93 seconds
Started Jul 28 07:42:20 PM PDT 24
Finished Jul 28 07:42:21 PM PDT 24
Peak memory 207040 kb
Host smart-39ac9cf8-363f-4a0b-ad97-77749e9a8a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36716
94628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3671694628
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.2024079015
Short name T1199
Test name
Test status
Simulation time 4284088978 ps
CPU time 34.2 seconds
Started Jul 28 07:42:24 PM PDT 24
Finished Jul 28 07:42:59 PM PDT 24
Peak memory 216940 kb
Host smart-c2196f67-e3bb-486d-aca3-e5aabb01e330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20240
79015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.2024079015
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.4044240978
Short name T1605
Test name
Test status
Simulation time 6824834839 ps
CPU time 205.09 seconds
Started Jul 28 07:42:22 PM PDT 24
Finished Jul 28 07:45:47 PM PDT 24
Peak memory 215668 kb
Host smart-03223a39-9cfd-401f-ac89-cd2aacac273d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4044240978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.4044240978
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3831156269
Short name T1820
Test name
Test status
Simulation time 158058632 ps
CPU time 0.87 seconds
Started Jul 28 07:42:20 PM PDT 24
Finished Jul 28 07:42:21 PM PDT 24
Peak memory 207096 kb
Host smart-c99cd47f-4d28-4c95-8171-ae068c238f3d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3831156269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3831156269
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1284367868
Short name T493
Test name
Test status
Simulation time 149712951 ps
CPU time 0.88 seconds
Started Jul 28 07:42:21 PM PDT 24
Finished Jul 28 07:42:22 PM PDT 24
Peak memory 207136 kb
Host smart-323fb095-439b-4557-9db7-5348709c01f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12843
67868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1284367868
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.2533451064
Short name T1642
Test name
Test status
Simulation time 246206482 ps
CPU time 1.06 seconds
Started Jul 28 07:42:33 PM PDT 24
Finished Jul 28 07:42:35 PM PDT 24
Peak memory 207108 kb
Host smart-7fa49a0f-5b1c-462e-84f2-83f5856d2beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25334
51064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2533451064
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3604733339
Short name T2377
Test name
Test status
Simulation time 163401494 ps
CPU time 0.86 seconds
Started Jul 28 07:42:20 PM PDT 24
Finished Jul 28 07:42:21 PM PDT 24
Peak memory 207064 kb
Host smart-77434754-199a-4a98-9742-73c84bcd2577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36047
33339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3604733339
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1706468803
Short name T2591
Test name
Test status
Simulation time 170601699 ps
CPU time 0.84 seconds
Started Jul 28 07:42:18 PM PDT 24
Finished Jul 28 07:42:19 PM PDT 24
Peak memory 207144 kb
Host smart-ede74b37-c236-4f67-b1de-b399ea3441e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17064
68803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1706468803
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.791982245
Short name T1960
Test name
Test status
Simulation time 164355165 ps
CPU time 0.86 seconds
Started Jul 28 07:42:16 PM PDT 24
Finished Jul 28 07:42:17 PM PDT 24
Peak memory 207100 kb
Host smart-55d6c46a-20e5-48a6-b415-dfbf5b2cf936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79198
2245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.791982245
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.1930494056
Short name T2428
Test name
Test status
Simulation time 213041213 ps
CPU time 1.01 seconds
Started Jul 28 07:42:23 PM PDT 24
Finished Jul 28 07:42:24 PM PDT 24
Peak memory 207140 kb
Host smart-8bb096f4-02fd-46ba-ab50-e539ad7440c0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1930494056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.1930494056
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.294123673
Short name T1005
Test name
Test status
Simulation time 144627177 ps
CPU time 0.85 seconds
Started Jul 28 07:42:30 PM PDT 24
Finished Jul 28 07:42:32 PM PDT 24
Peak memory 207156 kb
Host smart-b19389d6-68bd-4116-bb20-a4b9aae86d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29412
3673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.294123673
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3013405578
Short name T2292
Test name
Test status
Simulation time 35330576 ps
CPU time 0.68 seconds
Started Jul 28 07:42:27 PM PDT 24
Finished Jul 28 07:42:28 PM PDT 24
Peak memory 207120 kb
Host smart-6cb092f9-876b-4f1f-b671-c5314f024dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30134
05578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3013405578
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1549459150
Short name T963
Test name
Test status
Simulation time 13106085659 ps
CPU time 34.14 seconds
Started Jul 28 07:42:37 PM PDT 24
Finished Jul 28 07:43:11 PM PDT 24
Peak memory 215588 kb
Host smart-f1e0eae2-d5bd-4a5c-8152-baf39d188b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15494
59150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1549459150
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2879245195
Short name T2743
Test name
Test status
Simulation time 154605026 ps
CPU time 0.92 seconds
Started Jul 28 07:42:21 PM PDT 24
Finished Jul 28 07:42:22 PM PDT 24
Peak memory 207204 kb
Host smart-ee5e05fd-3573-46b5-b36f-2a9e467ded17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28792
45195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2879245195
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2117928155
Short name T1850
Test name
Test status
Simulation time 162633241 ps
CPU time 0.87 seconds
Started Jul 28 07:42:26 PM PDT 24
Finished Jul 28 07:42:27 PM PDT 24
Peak memory 207124 kb
Host smart-031784d0-e305-4132-8d45-d655e1e09613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21179
28155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2117928155
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.3880586167
Short name T333
Test name
Test status
Simulation time 156308067 ps
CPU time 0.82 seconds
Started Jul 28 07:42:29 PM PDT 24
Finished Jul 28 07:42:30 PM PDT 24
Peak memory 207140 kb
Host smart-441a0a32-9430-4129-9078-0f130fe66b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38805
86167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.3880586167
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.2643948482
Short name T985
Test name
Test status
Simulation time 219031837 ps
CPU time 0.92 seconds
Started Jul 28 07:42:25 PM PDT 24
Finished Jul 28 07:42:26 PM PDT 24
Peak memory 207132 kb
Host smart-ce31aad4-d33c-4f37-a27b-1ecd5cf3591d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26439
48482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.2643948482
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3106230976
Short name T2206
Test name
Test status
Simulation time 163109312 ps
CPU time 0.85 seconds
Started Jul 28 07:42:27 PM PDT 24
Finished Jul 28 07:42:28 PM PDT 24
Peak memory 207052 kb
Host smart-bc233052-ecdf-4d6a-9b3d-d8999f279abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31062
30976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3106230976
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1045528836
Short name T876
Test name
Test status
Simulation time 166217094 ps
CPU time 0.87 seconds
Started Jul 28 07:42:25 PM PDT 24
Finished Jul 28 07:42:32 PM PDT 24
Peak memory 207176 kb
Host smart-af202511-816e-4fbe-99c9-0dda5d87ebc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10455
28836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1045528836
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2574843662
Short name T2643
Test name
Test status
Simulation time 157838107 ps
CPU time 0.84 seconds
Started Jul 28 07:42:35 PM PDT 24
Finished Jul 28 07:42:36 PM PDT 24
Peak memory 207124 kb
Host smart-cbd64afa-36a7-4a46-af3c-c48bdaabc2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25748
43662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2574843662
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3515833706
Short name T788
Test name
Test status
Simulation time 270398897 ps
CPU time 1.12 seconds
Started Jul 28 07:42:28 PM PDT 24
Finished Jul 28 07:42:29 PM PDT 24
Peak memory 207112 kb
Host smart-8feb9005-fd6e-48b2-a5df-65cf1dda968e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35158
33706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3515833706
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2531180425
Short name T2505
Test name
Test status
Simulation time 4187453196 ps
CPU time 41.34 seconds
Started Jul 28 07:42:24 PM PDT 24
Finished Jul 28 07:43:06 PM PDT 24
Peak memory 217172 kb
Host smart-0a516830-ecf6-4ecf-9748-97e36541e7a4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2531180425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2531180425
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.4196013584
Short name T2852
Test name
Test status
Simulation time 228982672 ps
CPU time 0.97 seconds
Started Jul 28 07:42:27 PM PDT 24
Finished Jul 28 07:42:28 PM PDT 24
Peak memory 207136 kb
Host smart-bae3b85b-4d56-48fe-8c16-7b87d547a9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41960
13584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.4196013584
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.3411925400
Short name T2507
Test name
Test status
Simulation time 457329328 ps
CPU time 1.43 seconds
Started Jul 28 07:42:28 PM PDT 24
Finished Jul 28 07:42:30 PM PDT 24
Peak memory 207100 kb
Host smart-a62656ab-8289-463c-a893-bf133e6b57c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34119
25400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.3411925400
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.2832665950
Short name T857
Test name
Test status
Simulation time 4153578883 ps
CPU time 43.13 seconds
Started Jul 28 07:42:30 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 215568 kb
Host smart-4d70abc0-61bc-4213-a3df-cd946c9dfde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28326
65950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.2832665950
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.1386302036
Short name T59
Test name
Test status
Simulation time 2233971848 ps
CPU time 14.88 seconds
Started Jul 28 07:42:24 PM PDT 24
Finished Jul 28 07:42:39 PM PDT 24
Peak memory 207464 kb
Host smart-9fb6182b-71bc-44ef-b13e-a63794c9a365
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386302036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.1386302036
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.286691759
Short name T391
Test name
Test status
Simulation time 45266851 ps
CPU time 0.69 seconds
Started Jul 28 07:42:42 PM PDT 24
Finished Jul 28 07:42:43 PM PDT 24
Peak memory 207112 kb
Host smart-ed8d0414-acc4-4180-899a-48826371f4f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=286691759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.286691759
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.2399778613
Short name T1064
Test name
Test status
Simulation time 4269476039 ps
CPU time 7.38 seconds
Started Jul 28 07:42:22 PM PDT 24
Finished Jul 28 07:42:30 PM PDT 24
Peak memory 207536 kb
Host smart-8e8c4158-e4d4-4cd6-aa0d-f39c994f7913
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399778613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.2399778613
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.4250591563
Short name T1348
Test name
Test status
Simulation time 13323866814 ps
CPU time 18.88 seconds
Started Jul 28 07:42:34 PM PDT 24
Finished Jul 28 07:42:53 PM PDT 24
Peak memory 207396 kb
Host smart-e0b87677-0cac-40f0-8e9b-f4942b648ddc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250591563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.4250591563
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.1590011839
Short name T2255
Test name
Test status
Simulation time 23315838892 ps
CPU time 31.75 seconds
Started Jul 28 07:42:21 PM PDT 24
Finished Jul 28 07:42:53 PM PDT 24
Peak memory 207372 kb
Host smart-e62b943b-8245-49bc-a0ab-2a448a73a0d0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590011839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.1590011839
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.228730808
Short name T919
Test name
Test status
Simulation time 203342471 ps
CPU time 0.89 seconds
Started Jul 28 07:42:20 PM PDT 24
Finished Jul 28 07:42:21 PM PDT 24
Peak memory 207200 kb
Host smart-74e19ee1-fdf3-41a0-bdbd-a2d7f4e5c0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22873
0808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.228730808
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3574465909
Short name T1810
Test name
Test status
Simulation time 146829992 ps
CPU time 0.81 seconds
Started Jul 28 07:42:20 PM PDT 24
Finished Jul 28 07:42:21 PM PDT 24
Peak memory 207052 kb
Host smart-4c343e25-233e-4dfe-af81-008f932464f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35744
65909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3574465909
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2972077132
Short name T392
Test name
Test status
Simulation time 156420797 ps
CPU time 0.92 seconds
Started Jul 28 07:42:32 PM PDT 24
Finished Jul 28 07:42:33 PM PDT 24
Peak memory 207044 kb
Host smart-7c3f74b9-f116-413b-af54-dc671a6ce13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29720
77132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2972077132
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.301973064
Short name T2481
Test name
Test status
Simulation time 1425788824 ps
CPU time 3.43 seconds
Started Jul 28 07:42:21 PM PDT 24
Finished Jul 28 07:42:24 PM PDT 24
Peak memory 207280 kb
Host smart-7c6e0d12-a62c-4dc9-bc76-b393f66bb305
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=301973064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.301973064
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.3480075456
Short name T167
Test name
Test status
Simulation time 13200158007 ps
CPU time 29.27 seconds
Started Jul 28 07:42:24 PM PDT 24
Finished Jul 28 07:42:54 PM PDT 24
Peak memory 207428 kb
Host smart-4aa65c7f-5030-4f04-aa86-9b8d6d440157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34800
75456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.3480075456
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.2286393400
Short name T1542
Test name
Test status
Simulation time 4251770061 ps
CPU time 28.08 seconds
Started Jul 28 07:42:45 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 207348 kb
Host smart-87d43ed0-5d68-42e3-b570-fed5d1670e1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286393400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.2286393400
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3647690965
Short name T1430
Test name
Test status
Simulation time 310075290 ps
CPU time 1.23 seconds
Started Jul 28 07:42:28 PM PDT 24
Finished Jul 28 07:42:29 PM PDT 24
Peak memory 207088 kb
Host smart-3dd52f37-5233-408f-bfa9-dacb6b767f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36476
90965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3647690965
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.2127787583
Short name T778
Test name
Test status
Simulation time 142847832 ps
CPU time 0.8 seconds
Started Jul 28 07:42:20 PM PDT 24
Finished Jul 28 07:42:21 PM PDT 24
Peak memory 206992 kb
Host smart-ebf28344-80ce-4ea2-b35a-3db357604623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21277
87583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2127787583
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2246954684
Short name T522
Test name
Test status
Simulation time 102877068 ps
CPU time 0.78 seconds
Started Jul 28 07:42:27 PM PDT 24
Finished Jul 28 07:42:33 PM PDT 24
Peak memory 207044 kb
Host smart-207b103d-dc9e-4671-8009-cb9fc532c1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22469
54684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2246954684
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1751733480
Short name T1861
Test name
Test status
Simulation time 801064719 ps
CPU time 2.26 seconds
Started Jul 28 07:42:25 PM PDT 24
Finished Jul 28 07:42:33 PM PDT 24
Peak memory 207312 kb
Host smart-43fdf872-c069-4572-8941-feddd441e11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17517
33480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1751733480
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.450118112
Short name T694
Test name
Test status
Simulation time 162617204 ps
CPU time 1.5 seconds
Started Jul 28 07:42:31 PM PDT 24
Finished Jul 28 07:42:33 PM PDT 24
Peak memory 207308 kb
Host smart-bc5081d9-09be-4b0a-9ffe-2e32bf0bfd3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45011
8112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.450118112
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2056420241
Short name T486
Test name
Test status
Simulation time 192601808 ps
CPU time 0.93 seconds
Started Jul 28 07:42:32 PM PDT 24
Finished Jul 28 07:42:33 PM PDT 24
Peak memory 207308 kb
Host smart-423846c7-b487-4f06-83f2-8ad7fd171040
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2056420241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2056420241
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3788640094
Short name T313
Test name
Test status
Simulation time 141283179 ps
CPU time 0.82 seconds
Started Jul 28 07:42:25 PM PDT 24
Finished Jul 28 07:42:26 PM PDT 24
Peak memory 207096 kb
Host smart-feb857e0-303e-49fd-a7f9-255d0a9f44f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37886
40094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3788640094
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1941169503
Short name T2407
Test name
Test status
Simulation time 198087099 ps
CPU time 0.95 seconds
Started Jul 28 07:42:20 PM PDT 24
Finished Jul 28 07:42:21 PM PDT 24
Peak memory 207112 kb
Host smart-ac3cbd32-55d2-42b3-9ef4-ff96d70ef229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19411
69503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1941169503
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.3977898298
Short name T2198
Test name
Test status
Simulation time 6237894598 ps
CPU time 48.27 seconds
Started Jul 28 07:42:31 PM PDT 24
Finished Jul 28 07:43:20 PM PDT 24
Peak memory 215568 kb
Host smart-9414eeda-aede-4c69-b0c9-e525a7de884c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3977898298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3977898298
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.227356344
Short name T241
Test name
Test status
Simulation time 11394542114 ps
CPU time 146.9 seconds
Started Jul 28 07:42:26 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 207372 kb
Host smart-7aab1234-4c71-420f-b7a4-b362c9dba10e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=227356344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.227356344
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.1789878164
Short name T1910
Test name
Test status
Simulation time 241328432 ps
CPU time 0.95 seconds
Started Jul 28 07:42:31 PM PDT 24
Finished Jul 28 07:42:32 PM PDT 24
Peak memory 207068 kb
Host smart-bc506218-3d02-441e-95ad-7817c7d8310d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17898
78164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1789878164
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.116398700
Short name T1659
Test name
Test status
Simulation time 23311470859 ps
CPU time 35.81 seconds
Started Jul 28 07:42:45 PM PDT 24
Finished Jul 28 07:43:21 PM PDT 24
Peak memory 207456 kb
Host smart-df17aa6a-6ca9-44ae-b81c-486695290d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11639
8700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.116398700
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.768014105
Short name T604
Test name
Test status
Simulation time 3312863183 ps
CPU time 5.16 seconds
Started Jul 28 07:42:28 PM PDT 24
Finished Jul 28 07:42:33 PM PDT 24
Peak memory 207360 kb
Host smart-e52ebae1-a596-4a34-82c9-07a49fa4fa0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76801
4105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.768014105
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.3451856607
Short name T619
Test name
Test status
Simulation time 5903132255 ps
CPU time 42.13 seconds
Started Jul 28 07:42:42 PM PDT 24
Finished Jul 28 07:43:25 PM PDT 24
Peak memory 215668 kb
Host smart-2389024f-f7cf-4f66-829a-87b4a8a613f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34518
56607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.3451856607
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2109454948
Short name T505
Test name
Test status
Simulation time 4964793444 ps
CPU time 38.37 seconds
Started Jul 28 07:42:32 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 207460 kb
Host smart-1b47fd0e-0354-467e-80a0-f6f122bf0ff9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2109454948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2109454948
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.161078005
Short name T438
Test name
Test status
Simulation time 239527228 ps
CPU time 0.97 seconds
Started Jul 28 07:42:24 PM PDT 24
Finished Jul 28 07:42:25 PM PDT 24
Peak memory 207124 kb
Host smart-c9629812-667b-4a31-b7ab-9a96936fc8d7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=161078005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.161078005
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1723447295
Short name T1439
Test name
Test status
Simulation time 220907456 ps
CPU time 1 seconds
Started Jul 28 07:42:30 PM PDT 24
Finished Jul 28 07:42:31 PM PDT 24
Peak memory 207100 kb
Host smart-a75218a0-54c0-44e4-9dbc-3f6207a65a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17234
47295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1723447295
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2073721590
Short name T1592
Test name
Test status
Simulation time 5148408145 ps
CPU time 152.72 seconds
Started Jul 28 07:42:48 PM PDT 24
Finished Jul 28 07:45:21 PM PDT 24
Peak memory 215512 kb
Host smart-c98f2c65-ada6-4941-96f9-970d766bffe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20737
21590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2073721590
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.1137987085
Short name T2320
Test name
Test status
Simulation time 4223406200 ps
CPU time 31.51 seconds
Started Jul 28 07:42:49 PM PDT 24
Finished Jul 28 07:43:21 PM PDT 24
Peak memory 207328 kb
Host smart-aa2c886a-b87e-4276-b727-e84f91ba9eab
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1137987085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.1137987085
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.1703097689
Short name T1631
Test name
Test status
Simulation time 151710747 ps
CPU time 0.86 seconds
Started Jul 28 07:42:31 PM PDT 24
Finished Jul 28 07:42:32 PM PDT 24
Peak memory 207164 kb
Host smart-7bb6d554-e055-4672-bbbc-27f8f7f6dc40
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1703097689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.1703097689
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.789293383
Short name T27
Test name
Test status
Simulation time 137270221 ps
CPU time 0.82 seconds
Started Jul 28 07:42:27 PM PDT 24
Finished Jul 28 07:42:28 PM PDT 24
Peak memory 207148 kb
Host smart-2787d42b-a17e-4444-8132-06305f4a3e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78929
3383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.789293383
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.4239908646
Short name T137
Test name
Test status
Simulation time 228985812 ps
CPU time 0.97 seconds
Started Jul 28 07:42:45 PM PDT 24
Finished Jul 28 07:42:47 PM PDT 24
Peak memory 207100 kb
Host smart-6d9329cb-ce0f-4d0e-89e2-ce81eda86ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42399
08646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.4239908646
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2764757069
Short name T2042
Test name
Test status
Simulation time 177747137 ps
CPU time 0.9 seconds
Started Jul 28 07:42:26 PM PDT 24
Finished Jul 28 07:42:27 PM PDT 24
Peak memory 207140 kb
Host smart-c2cdc11f-c878-4b8a-b57d-80d65d64e12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27647
57069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2764757069
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.2710355790
Short name T609
Test name
Test status
Simulation time 189494901 ps
CPU time 0.95 seconds
Started Jul 28 07:42:29 PM PDT 24
Finished Jul 28 07:42:30 PM PDT 24
Peak memory 207080 kb
Host smart-2088203d-d460-4f48-adb6-06120dc095a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27103
55790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2710355790
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3689255580
Short name T667
Test name
Test status
Simulation time 196399699 ps
CPU time 1 seconds
Started Jul 28 07:42:23 PM PDT 24
Finished Jul 28 07:42:24 PM PDT 24
Peak memory 207324 kb
Host smart-97662d09-f62b-47db-bdf0-63aca686c702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36892
55580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3689255580
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2323275871
Short name T175
Test name
Test status
Simulation time 204062222 ps
CPU time 0.88 seconds
Started Jul 28 07:42:31 PM PDT 24
Finished Jul 28 07:42:32 PM PDT 24
Peak memory 207052 kb
Host smart-6ba4a31f-c733-48ca-b95d-00db564a7509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23232
75871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2323275871
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1299938219
Short name T2810
Test name
Test status
Simulation time 207414417 ps
CPU time 0.95 seconds
Started Jul 28 07:42:29 PM PDT 24
Finished Jul 28 07:42:31 PM PDT 24
Peak memory 207124 kb
Host smart-1e1d876c-ebb3-472f-9f8a-22af8bcc80c9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1299938219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1299938219
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1807990654
Short name T2799
Test name
Test status
Simulation time 141987380 ps
CPU time 0.87 seconds
Started Jul 28 07:42:49 PM PDT 24
Finished Jul 28 07:42:50 PM PDT 24
Peak memory 207116 kb
Host smart-d0a7494a-c295-421d-a82e-a4696fc5a848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18079
90654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1807990654
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3230136756
Short name T611
Test name
Test status
Simulation time 30178646 ps
CPU time 0.66 seconds
Started Jul 28 07:42:27 PM PDT 24
Finished Jul 28 07:42:28 PM PDT 24
Peak memory 207120 kb
Host smart-65045d23-381d-460a-a270-82ea33d8b719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32301
36756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3230136756
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.77577055
Short name T1254
Test name
Test status
Simulation time 10381033805 ps
CPU time 28.03 seconds
Started Jul 28 07:42:29 PM PDT 24
Finished Jul 28 07:42:57 PM PDT 24
Peak memory 215536 kb
Host smart-4ce2e807-f5bf-45d7-a383-c2ba9ec7bba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77577
055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.77577055
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3537701882
Short name T1602
Test name
Test status
Simulation time 187302344 ps
CPU time 0.92 seconds
Started Jul 28 07:42:45 PM PDT 24
Finished Jul 28 07:42:46 PM PDT 24
Peak memory 207204 kb
Host smart-4eb1aaa5-4d46-45e0-baea-efd270c49d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35377
01882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3537701882
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1723404263
Short name T2128
Test name
Test status
Simulation time 246839940 ps
CPU time 1.09 seconds
Started Jul 28 07:42:37 PM PDT 24
Finished Jul 28 07:42:38 PM PDT 24
Peak memory 207160 kb
Host smart-e4498ede-9e6c-4d80-b7cd-9aba0ab647a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17234
04263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1723404263
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.3253331693
Short name T1149
Test name
Test status
Simulation time 229500296 ps
CPU time 1.09 seconds
Started Jul 28 07:42:29 PM PDT 24
Finished Jul 28 07:42:31 PM PDT 24
Peak memory 207128 kb
Host smart-860aece7-c515-4144-b300-86e3bb88f6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32533
31693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.3253331693
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3472572130
Short name T1670
Test name
Test status
Simulation time 163589991 ps
CPU time 0.87 seconds
Started Jul 28 07:42:46 PM PDT 24
Finished Jul 28 07:42:46 PM PDT 24
Peak memory 207084 kb
Host smart-66784666-179e-4073-b7cb-39dc836404ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34725
72130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3472572130
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3445774224
Short name T1127
Test name
Test status
Simulation time 179377188 ps
CPU time 0.95 seconds
Started Jul 28 07:42:29 PM PDT 24
Finished Jul 28 07:42:30 PM PDT 24
Peak memory 207116 kb
Host smart-d26c2bf7-f803-482e-91be-c10d72aabc15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34457
74224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3445774224
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2956218357
Short name T763
Test name
Test status
Simulation time 148410218 ps
CPU time 0.81 seconds
Started Jul 28 07:42:47 PM PDT 24
Finished Jul 28 07:42:48 PM PDT 24
Peak memory 206996 kb
Host smart-d20c70c1-9d3b-4a2c-b587-466f3a843346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29562
18357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2956218357
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.841036157
Short name T1116
Test name
Test status
Simulation time 199058913 ps
CPU time 0.89 seconds
Started Jul 28 07:42:50 PM PDT 24
Finished Jul 28 07:42:51 PM PDT 24
Peak memory 207168 kb
Host smart-ecbfbf0a-db45-4855-b7d7-9b86d6814457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84103
6157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.841036157
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2833300814
Short name T514
Test name
Test status
Simulation time 230471674 ps
CPU time 1.09 seconds
Started Jul 28 07:42:40 PM PDT 24
Finished Jul 28 07:42:41 PM PDT 24
Peak memory 207080 kb
Host smart-d630c452-4887-4895-8826-53dddd2b308c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28333
00814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2833300814
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.3754651534
Short name T1823
Test name
Test status
Simulation time 3119327202 ps
CPU time 89.28 seconds
Started Jul 28 07:42:35 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 215644 kb
Host smart-74365051-c8b5-4e69-8dc1-0b031c4d87bf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3754651534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.3754651534
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2296434526
Short name T786
Test name
Test status
Simulation time 177982573 ps
CPU time 0.86 seconds
Started Jul 28 07:42:36 PM PDT 24
Finished Jul 28 07:42:37 PM PDT 24
Peak memory 207188 kb
Host smart-7b81c219-ea75-4f4d-be7e-2b344c0859a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22964
34526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2296434526
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.607292443
Short name T820
Test name
Test status
Simulation time 196454489 ps
CPU time 0.91 seconds
Started Jul 28 07:42:39 PM PDT 24
Finished Jul 28 07:42:40 PM PDT 24
Peak memory 207072 kb
Host smart-bc8aef11-ab34-4fc1-a6d0-b3f9dc15f236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60729
2443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.607292443
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.2342455796
Short name T2018
Test name
Test status
Simulation time 1006243618 ps
CPU time 2.46 seconds
Started Jul 28 07:42:32 PM PDT 24
Finished Jul 28 07:42:35 PM PDT 24
Peak memory 207336 kb
Host smart-b34c3d25-dba3-4d28-9501-f62b6615f23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23424
55796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.2342455796
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3030843079
Short name T1648
Test name
Test status
Simulation time 6103793688 ps
CPU time 61.42 seconds
Started Jul 28 07:42:38 PM PDT 24
Finished Jul 28 07:43:40 PM PDT 24
Peak memory 207352 kb
Host smart-d8335ba1-8dd0-4180-a058-09bc44a88857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30308
43079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3030843079
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.2782526443
Short name T2153
Test name
Test status
Simulation time 5260153701 ps
CPU time 45.45 seconds
Started Jul 28 07:42:26 PM PDT 24
Finished Jul 28 07:43:12 PM PDT 24
Peak memory 207308 kb
Host smart-b2612edf-7cc2-4964-bdfd-18abc0f34308
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782526443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.2782526443
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.1797797127
Short name T2568
Test name
Test status
Simulation time 61437338 ps
CPU time 0.69 seconds
Started Jul 28 07:42:57 PM PDT 24
Finished Jul 28 07:42:57 PM PDT 24
Peak memory 207072 kb
Host smart-0ac0ccb9-1abc-4975-9a05-122bcfcc8d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1797797127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.1797797127
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.400579775
Short name T789
Test name
Test status
Simulation time 4067295204 ps
CPU time 6.06 seconds
Started Jul 28 07:42:37 PM PDT 24
Finished Jul 28 07:42:43 PM PDT 24
Peak memory 207416 kb
Host smart-fb83b9f6-36e1-42fe-8544-474128383e98
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400579775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ao
n_wake_disconnect.400579775
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2143131080
Short name T593
Test name
Test status
Simulation time 13315822370 ps
CPU time 15.83 seconds
Started Jul 28 07:42:46 PM PDT 24
Finished Jul 28 07:43:02 PM PDT 24
Peak memory 207420 kb
Host smart-8c8f8dda-1e0c-4763-bbf1-58f9a0c9c569
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143131080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2143131080
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2600506034
Short name T808
Test name
Test status
Simulation time 23315376719 ps
CPU time 29.08 seconds
Started Jul 28 07:42:45 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207456 kb
Host smart-7927c81c-f372-4a1f-852c-7c64bd6e725e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600506034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_resume.2600506034
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.4093181941
Short name T2490
Test name
Test status
Simulation time 164947916 ps
CPU time 0.84 seconds
Started Jul 28 07:42:48 PM PDT 24
Finished Jul 28 07:42:48 PM PDT 24
Peak memory 207144 kb
Host smart-aeaf86e6-4f9e-47c2-ab9b-4d58bdab3ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40931
81941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.4093181941
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.951631425
Short name T1394
Test name
Test status
Simulation time 148528083 ps
CPU time 0.87 seconds
Started Jul 28 07:42:31 PM PDT 24
Finished Jul 28 07:42:32 PM PDT 24
Peak memory 207084 kb
Host smart-7c3e6a48-2953-4c77-8203-4c952e37420d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95163
1425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.951631425
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.822048694
Short name T1854
Test name
Test status
Simulation time 236498462 ps
CPU time 1.05 seconds
Started Jul 28 07:42:29 PM PDT 24
Finished Jul 28 07:42:30 PM PDT 24
Peak memory 207140 kb
Host smart-7f1866d4-4306-4131-a119-ed6003aa7f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82204
8694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.822048694
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2535359934
Short name T891
Test name
Test status
Simulation time 1232249502 ps
CPU time 3.09 seconds
Started Jul 28 07:42:47 PM PDT 24
Finished Jul 28 07:42:51 PM PDT 24
Peak memory 207356 kb
Host smart-21072382-ae2a-4657-a7c3-53ce2945625d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2535359934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2535359934
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.28446629
Short name T875
Test name
Test status
Simulation time 10029171696 ps
CPU time 22.24 seconds
Started Jul 28 07:42:32 PM PDT 24
Finished Jul 28 07:42:54 PM PDT 24
Peak memory 207356 kb
Host smart-e9153143-41dd-449c-b73d-2bff2b979b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28446
629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.28446629
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.3274347567
Short name T265
Test name
Test status
Simulation time 402157491 ps
CPU time 1.38 seconds
Started Jul 28 07:42:31 PM PDT 24
Finished Jul 28 07:42:33 PM PDT 24
Peak memory 207108 kb
Host smart-bdd25273-677c-4b71-853f-a1dda4a1fe44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32743
47567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.3274347567
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1259176206
Short name T2560
Test name
Test status
Simulation time 147437045 ps
CPU time 0.83 seconds
Started Jul 28 07:42:39 PM PDT 24
Finished Jul 28 07:42:40 PM PDT 24
Peak memory 207044 kb
Host smart-af78fd8f-0f6f-4de8-8357-62d3a00c6914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12591
76206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1259176206
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1815154064
Short name T992
Test name
Test status
Simulation time 64214661 ps
CPU time 0.72 seconds
Started Jul 28 07:42:38 PM PDT 24
Finished Jul 28 07:42:39 PM PDT 24
Peak memory 207132 kb
Host smart-29f5bb2a-77d3-42ad-bbd8-4f64d4412771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18151
54064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1815154064
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.4030807115
Short name T2434
Test name
Test status
Simulation time 936296986 ps
CPU time 2.33 seconds
Started Jul 28 07:42:37 PM PDT 24
Finished Jul 28 07:42:39 PM PDT 24
Peak memory 207364 kb
Host smart-88a9d86b-0c71-4853-ab3c-af27eaf46f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40308
07115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.4030807115
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1351527274
Short name T626
Test name
Test status
Simulation time 245003615 ps
CPU time 2 seconds
Started Jul 28 07:42:33 PM PDT 24
Finished Jul 28 07:42:35 PM PDT 24
Peak memory 207268 kb
Host smart-811a18bc-5eee-41cc-b130-37d61ea5f9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13515
27274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1351527274
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2043462037
Short name T2089
Test name
Test status
Simulation time 182843759 ps
CPU time 1.01 seconds
Started Jul 28 07:42:48 PM PDT 24
Finished Jul 28 07:42:50 PM PDT 24
Peak memory 215560 kb
Host smart-8ad77eec-361a-452d-8690-2cbbc40cd1e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2043462037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2043462037
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1177355691
Short name T2201
Test name
Test status
Simulation time 152376480 ps
CPU time 0.85 seconds
Started Jul 28 07:42:36 PM PDT 24
Finished Jul 28 07:42:37 PM PDT 24
Peak memory 207140 kb
Host smart-db9f3041-ab82-4a44-99e8-28ff9a1304fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11773
55691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1177355691
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.915736413
Short name T673
Test name
Test status
Simulation time 219834302 ps
CPU time 0.98 seconds
Started Jul 28 07:42:39 PM PDT 24
Finished Jul 28 07:42:45 PM PDT 24
Peak memory 207072 kb
Host smart-b8ed9373-10ea-4728-9981-c4433bcfba6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91573
6413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.915736413
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.1600803568
Short name T2243
Test name
Test status
Simulation time 8172713433 ps
CPU time 77.95 seconds
Started Jul 28 07:42:39 PM PDT 24
Finished Jul 28 07:43:57 PM PDT 24
Peak memory 215552 kb
Host smart-7fc6e3af-4147-45fe-ad47-9d7f4bccd839
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1600803568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.1600803568
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.1687380658
Short name T2693
Test name
Test status
Simulation time 7979201747 ps
CPU time 97.64 seconds
Started Jul 28 07:42:33 PM PDT 24
Finished Jul 28 07:44:10 PM PDT 24
Peak memory 207380 kb
Host smart-f6e817ac-2723-4ff1-9dfd-1e6c217ae4ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1687380658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.1687380658
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1932902494
Short name T1608
Test name
Test status
Simulation time 153966641 ps
CPU time 0.88 seconds
Started Jul 28 07:42:41 PM PDT 24
Finished Jul 28 07:42:42 PM PDT 24
Peak memory 207084 kb
Host smart-d278b985-ce3f-4015-8489-a0f3fce77f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19329
02494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1932902494
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.2226377643
Short name T2392
Test name
Test status
Simulation time 23281308962 ps
CPU time 26.93 seconds
Started Jul 28 07:42:31 PM PDT 24
Finished Jul 28 07:42:58 PM PDT 24
Peak memory 207300 kb
Host smart-52584dc8-5d3f-4e7d-a572-16b42adfc571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22263
77643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.2226377643
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.2599621916
Short name T2733
Test name
Test status
Simulation time 3298593878 ps
CPU time 5.25 seconds
Started Jul 28 07:42:36 PM PDT 24
Finished Jul 28 07:42:41 PM PDT 24
Peak memory 207396 kb
Host smart-a8981fb5-72a2-478f-b4d3-98cc7d04a2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25996
21916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.2599621916
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.3081619038
Short name T2148
Test name
Test status
Simulation time 8132261649 ps
CPU time 231.35 seconds
Started Jul 28 07:42:30 PM PDT 24
Finished Jul 28 07:46:21 PM PDT 24
Peak memory 215648 kb
Host smart-a06808d1-2d63-4e30-b9f8-3b7b18cb09a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30816
19038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3081619038
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.543503719
Short name T1039
Test name
Test status
Simulation time 5157227998 ps
CPU time 37.9 seconds
Started Jul 28 07:42:47 PM PDT 24
Finished Jul 28 07:43:25 PM PDT 24
Peak memory 207400 kb
Host smart-eecc000a-84e2-431b-bf44-8c416761224e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=543503719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.543503719
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1528988953
Short name T1805
Test name
Test status
Simulation time 275939468 ps
CPU time 1 seconds
Started Jul 28 07:42:34 PM PDT 24
Finished Jul 28 07:42:35 PM PDT 24
Peak memory 207164 kb
Host smart-481ab5a5-820d-4a03-9140-011cac83c425
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1528988953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1528988953
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.739603350
Short name T2564
Test name
Test status
Simulation time 192300009 ps
CPU time 1 seconds
Started Jul 28 07:42:51 PM PDT 24
Finished Jul 28 07:42:53 PM PDT 24
Peak memory 207040 kb
Host smart-b65a6602-e257-443b-9cd7-70ebe15992e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73960
3350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.739603350
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3112178756
Short name T2646
Test name
Test status
Simulation time 5330594326 ps
CPU time 40.01 seconds
Started Jul 28 07:42:38 PM PDT 24
Finished Jul 28 07:43:18 PM PDT 24
Peak memory 215576 kb
Host smart-a3483c7c-934f-4bf2-8b24-2bc984b94694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31121
78756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3112178756
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.617639710
Short name T582
Test name
Test status
Simulation time 6760374322 ps
CPU time 50.17 seconds
Started Jul 28 07:42:37 PM PDT 24
Finished Jul 28 07:43:27 PM PDT 24
Peak memory 207384 kb
Host smart-010b7ef3-0c09-4d6c-978e-122724f0745b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=617639710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.617639710
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2341942997
Short name T1528
Test name
Test status
Simulation time 160667670 ps
CPU time 0.89 seconds
Started Jul 28 07:42:54 PM PDT 24
Finished Jul 28 07:42:55 PM PDT 24
Peak memory 207160 kb
Host smart-676baada-fc70-48c0-9c22-4953a482cdfc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2341942997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2341942997
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.222052158
Short name T1082
Test name
Test status
Simulation time 153355863 ps
CPU time 0.84 seconds
Started Jul 28 07:42:50 PM PDT 24
Finished Jul 28 07:42:51 PM PDT 24
Peak memory 207124 kb
Host smart-a2065c82-4b9d-48a1-81af-c3458bb131ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22205
2158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.222052158
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1921524022
Short name T118
Test name
Test status
Simulation time 253587888 ps
CPU time 1.01 seconds
Started Jul 28 07:42:57 PM PDT 24
Finished Jul 28 07:42:58 PM PDT 24
Peak memory 207060 kb
Host smart-8ee7df2c-9393-4dc5-91f8-e1a9dffc61a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
24022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1921524022
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.710502113
Short name T787
Test name
Test status
Simulation time 197762452 ps
CPU time 0.96 seconds
Started Jul 28 07:42:35 PM PDT 24
Finished Jul 28 07:42:36 PM PDT 24
Peak memory 207092 kb
Host smart-8b5d1166-e6b4-4def-9180-d853be82856b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71050
2113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.710502113
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2258116475
Short name T2342
Test name
Test status
Simulation time 196372500 ps
CPU time 0.92 seconds
Started Jul 28 07:42:35 PM PDT 24
Finished Jul 28 07:42:36 PM PDT 24
Peak memory 207116 kb
Host smart-ac1c9bed-e227-4738-bb24-545a59f3309a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22581
16475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2258116475
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2751558456
Short name T1518
Test name
Test status
Simulation time 162920689 ps
CPU time 0.9 seconds
Started Jul 28 07:42:50 PM PDT 24
Finished Jul 28 07:42:51 PM PDT 24
Peak memory 207048 kb
Host smart-2ca1457f-b087-4be3-b25e-827868c3d9c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27515
58456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2751558456
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2979120373
Short name T2276
Test name
Test status
Simulation time 160194779 ps
CPU time 0.87 seconds
Started Jul 28 07:42:52 PM PDT 24
Finished Jul 28 07:42:53 PM PDT 24
Peak memory 207124 kb
Host smart-b42ae15d-61a0-4648-9324-e93fdedcb336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29791
20373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2979120373
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2409261113
Short name T607
Test name
Test status
Simulation time 258957244 ps
CPU time 1.07 seconds
Started Jul 28 07:42:46 PM PDT 24
Finished Jul 28 07:42:47 PM PDT 24
Peak memory 207172 kb
Host smart-c9b23e6f-a814-4055-ac58-c65a18b3fb2a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2409261113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2409261113
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.4288861604
Short name T2274
Test name
Test status
Simulation time 160580106 ps
CPU time 0.86 seconds
Started Jul 28 07:42:38 PM PDT 24
Finished Jul 28 07:42:39 PM PDT 24
Peak memory 207128 kb
Host smart-92696c09-682f-4000-94d3-b20f8e074c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42888
61604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.4288861604
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2932400117
Short name T908
Test name
Test status
Simulation time 41596763 ps
CPU time 0.75 seconds
Started Jul 28 07:42:49 PM PDT 24
Finished Jul 28 07:42:50 PM PDT 24
Peak memory 207120 kb
Host smart-df159590-bfd5-44ff-93dd-b3f450bb8b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29324
00117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2932400117
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.142480597
Short name T2033
Test name
Test status
Simulation time 8026198991 ps
CPU time 20.57 seconds
Started Jul 28 07:43:00 PM PDT 24
Finished Jul 28 07:43:20 PM PDT 24
Peak memory 215600 kb
Host smart-1915043e-426f-42ed-b20d-8cf6af32a9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14248
0597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.142480597
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2505886231
Short name T2763
Test name
Test status
Simulation time 159222559 ps
CPU time 0.82 seconds
Started Jul 28 07:42:42 PM PDT 24
Finished Jul 28 07:42:43 PM PDT 24
Peak memory 207152 kb
Host smart-d73d40e3-c755-42fd-86bd-83dc1c294d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25058
86231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2505886231
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2717136884
Short name T1243
Test name
Test status
Simulation time 193096312 ps
CPU time 0.98 seconds
Started Jul 28 07:42:38 PM PDT 24
Finished Jul 28 07:42:39 PM PDT 24
Peak memory 207096 kb
Host smart-b8dfd845-1e17-484d-81c9-230825635efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27171
36884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2717136884
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.1959196602
Short name T1780
Test name
Test status
Simulation time 171459930 ps
CPU time 0.92 seconds
Started Jul 28 07:42:38 PM PDT 24
Finished Jul 28 07:42:39 PM PDT 24
Peak memory 207140 kb
Host smart-c41a8143-2df3-4eab-a24f-39ba412f6b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19591
96602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.1959196602
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1594783007
Short name T812
Test name
Test status
Simulation time 149423997 ps
CPU time 0.84 seconds
Started Jul 28 07:42:47 PM PDT 24
Finished Jul 28 07:42:48 PM PDT 24
Peak memory 207164 kb
Host smart-a76e88ba-4ad3-4b87-89be-81d73ef3f8c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15947
83007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1594783007
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.417843972
Short name T630
Test name
Test status
Simulation time 165351744 ps
CPU time 0.96 seconds
Started Jul 28 07:42:36 PM PDT 24
Finished Jul 28 07:42:38 PM PDT 24
Peak memory 207108 kb
Host smart-90883a20-a7bc-4d2c-bbc0-7a865ef36abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41784
3972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.417843972
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.1547700455
Short name T1950
Test name
Test status
Simulation time 147615195 ps
CPU time 0.88 seconds
Started Jul 28 07:42:52 PM PDT 24
Finished Jul 28 07:42:54 PM PDT 24
Peak memory 207024 kb
Host smart-85b4fb24-1b56-42c0-aa9f-59b6993cde8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15477
00455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.1547700455
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.112436660
Short name T1289
Test name
Test status
Simulation time 170662167 ps
CPU time 0.88 seconds
Started Jul 28 07:42:39 PM PDT 24
Finished Jul 28 07:42:40 PM PDT 24
Peak memory 207076 kb
Host smart-7a781f1e-22a3-4482-8991-a2f315a7dbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11243
6660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.112436660
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1479561132
Short name T2691
Test name
Test status
Simulation time 207887456 ps
CPU time 0.92 seconds
Started Jul 28 07:42:35 PM PDT 24
Finished Jul 28 07:42:36 PM PDT 24
Peak memory 207124 kb
Host smart-6c583e78-d45d-416d-abb5-c1567de4c74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14795
61132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1479561132
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3494784203
Short name T1859
Test name
Test status
Simulation time 5644088820 ps
CPU time 57.5 seconds
Started Jul 28 07:42:56 PM PDT 24
Finished Jul 28 07:43:54 PM PDT 24
Peak memory 217004 kb
Host smart-8bd5b305-6ee6-4f51-af7f-807672c218fb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3494784203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3494784203
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2149487088
Short name T827
Test name
Test status
Simulation time 192846701 ps
CPU time 0.92 seconds
Started Jul 28 07:42:48 PM PDT 24
Finished Jul 28 07:42:49 PM PDT 24
Peak memory 207104 kb
Host smart-c52b71b0-66b1-42d7-8f8d-256be6cf5e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21494
87088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2149487088
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.670310434
Short name T1982
Test name
Test status
Simulation time 184359595 ps
CPU time 0.87 seconds
Started Jul 28 07:42:50 PM PDT 24
Finished Jul 28 07:42:51 PM PDT 24
Peak memory 207020 kb
Host smart-7ed5b76b-c7d7-4ac3-a5d5-aa3bbb623bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67031
0434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.670310434
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.167134944
Short name T2590
Test name
Test status
Simulation time 1253897840 ps
CPU time 2.82 seconds
Started Jul 28 07:42:35 PM PDT 24
Finished Jul 28 07:42:38 PM PDT 24
Peak memory 207280 kb
Host smart-890addc6-f393-4a9a-bc3d-dc679ffa727a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16713
4944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.167134944
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1575322896
Short name T1710
Test name
Test status
Simulation time 6908587050 ps
CPU time 199.65 seconds
Started Jul 28 07:42:55 PM PDT 24
Finished Jul 28 07:46:15 PM PDT 24
Peak memory 215644 kb
Host smart-adfa6554-0650-401e-8736-7ebed1fc8855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15753
22896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1575322896
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.3722705820
Short name T2212
Test name
Test status
Simulation time 3409949217 ps
CPU time 29.95 seconds
Started Jul 28 07:42:29 PM PDT 24
Finished Jul 28 07:42:59 PM PDT 24
Peak memory 207364 kb
Host smart-3dd7fe74-23b6-4eff-b866-1e7bad6fb1dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722705820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_hos
t_handshake.3722705820
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.638108076
Short name T2692
Test name
Test status
Simulation time 41923503 ps
CPU time 0.67 seconds
Started Jul 28 07:38:39 PM PDT 24
Finished Jul 28 07:38:40 PM PDT 24
Peak memory 207092 kb
Host smart-e8be9da5-7b69-4f7a-ace8-8096842425fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=638108076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.638108076
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1100943907
Short name T11
Test name
Test status
Simulation time 4288901389 ps
CPU time 5.78 seconds
Started Jul 28 07:38:25 PM PDT 24
Finished Jul 28 07:38:31 PM PDT 24
Peak memory 207528 kb
Host smart-67794dc8-95fe-45fc-91d5-82228dbd3d52
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100943907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.1100943907
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1104147115
Short name T1748
Test name
Test status
Simulation time 13398580689 ps
CPU time 15.54 seconds
Started Jul 28 07:38:27 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 207328 kb
Host smart-a4ccb04d-d60c-4e02-bf35-96d5fb8874c3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104147115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1104147115
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.2637862141
Short name T1507
Test name
Test status
Simulation time 23440341323 ps
CPU time 33.49 seconds
Started Jul 28 07:38:36 PM PDT 24
Finished Jul 28 07:39:10 PM PDT 24
Peak memory 207384 kb
Host smart-45d6d304-4689-4fff-b689-4db09b0429f5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637862141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.2637862141
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3542297493
Short name T965
Test name
Test status
Simulation time 159413594 ps
CPU time 0.85 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 207044 kb
Host smart-f7d52371-ef0d-4034-a194-3e7e060663e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35422
97493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3542297493
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.413442789
Short name T57
Test name
Test status
Simulation time 178210651 ps
CPU time 0.83 seconds
Started Jul 28 07:38:35 PM PDT 24
Finished Jul 28 07:38:36 PM PDT 24
Peak memory 207140 kb
Host smart-3f68a754-d198-4354-ab67-04f7b22b0e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41344
2789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.413442789
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.1905148984
Short name T63
Test name
Test status
Simulation time 135177232 ps
CPU time 0.88 seconds
Started Jul 28 07:38:28 PM PDT 24
Finished Jul 28 07:38:29 PM PDT 24
Peak memory 207092 kb
Host smart-00214715-d5eb-48d9-93ff-3e783173cb97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19051
48984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.1905148984
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.2415233292
Short name T525
Test name
Test status
Simulation time 158581704 ps
CPU time 0.82 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 207172 kb
Host smart-78f53a99-8254-4a93-a22a-26f822194c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24152
33292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.2415233292
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.3188106933
Short name T401
Test name
Test status
Simulation time 257272004 ps
CPU time 1.04 seconds
Started Jul 28 07:38:42 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 207200 kb
Host smart-4285dcd2-432f-44a8-86c3-62aa5a6d007a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31881
06933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3188106933
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3534341940
Short name T2024
Test name
Test status
Simulation time 494037332 ps
CPU time 1.56 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:39 PM PDT 24
Peak memory 207028 kb
Host smart-acace1cf-b8d9-43f9-93a8-9eae95c3fbcc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3534341940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3534341940
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.1498659039
Short name T1669
Test name
Test status
Simulation time 19241791158 ps
CPU time 42.65 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:39:21 PM PDT 24
Peak memory 207336 kb
Host smart-427f2ae2-85f0-485f-94af-33a7497ec0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14986
59039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1498659039
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.2845233712
Short name T1192
Test name
Test status
Simulation time 1052546939 ps
CPU time 23.42 seconds
Started Jul 28 07:38:35 PM PDT 24
Finished Jul 28 07:38:58 PM PDT 24
Peak memory 207288 kb
Host smart-a47e058a-e48c-4a34-a0e8-defe27ea2430
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845233712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.2845233712
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.684792080
Short name T2842
Test name
Test status
Simulation time 392932278 ps
CPU time 1.24 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 207116 kb
Host smart-53b70880-a09f-4582-9991-3454637201e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68479
2080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.684792080
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1942809305
Short name T2113
Test name
Test status
Simulation time 134093497 ps
CPU time 0.81 seconds
Started Jul 28 07:38:32 PM PDT 24
Finished Jul 28 07:38:33 PM PDT 24
Peak memory 207048 kb
Host smart-9d3643e9-87e1-4c17-89d7-76d14973b92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19428
09305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1942809305
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.3414553333
Short name T1868
Test name
Test status
Simulation time 45390090 ps
CPU time 0.71 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:38:39 PM PDT 24
Peak memory 207048 kb
Host smart-f5e129c2-3126-4146-a3e1-875352a96dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34145
53333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3414553333
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.1987256415
Short name T1222
Test name
Test status
Simulation time 947536677 ps
CPU time 2.37 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:38:41 PM PDT 24
Peak memory 207312 kb
Host smart-b3b6240f-743a-491e-84d0-3bc45a6ca383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19872
56415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.1987256415
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.2628110633
Short name T1387
Test name
Test status
Simulation time 248332925 ps
CPU time 2 seconds
Started Jul 28 07:38:29 PM PDT 24
Finished Jul 28 07:38:31 PM PDT 24
Peak memory 207392 kb
Host smart-7ac186da-37bd-4250-a3aa-88a080e0ec7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26281
10633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.2628110633
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.448388350
Short name T2348
Test name
Test status
Simulation time 120228859566 ps
CPU time 186.25 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:41:44 PM PDT 24
Peak memory 207428 kb
Host smart-3a85635e-f1e3-4d0c-8f12-d3097c26afb8
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=448388350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.448388350
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.3664197302
Short name T1242
Test name
Test status
Simulation time 114177511954 ps
CPU time 182.05 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:41:39 PM PDT 24
Peak memory 207376 kb
Host smart-4f139f6b-5383-4762-b3c9-402264ead6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664197302 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.3664197302
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.1120190657
Short name T308
Test name
Test status
Simulation time 116117004057 ps
CPU time 190.66 seconds
Started Jul 28 07:38:32 PM PDT 24
Finished Jul 28 07:41:43 PM PDT 24
Peak memory 207360 kb
Host smart-8fdc0644-bd6f-44c8-be7b-423d1164a33d
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1120190657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.1120190657
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.4088826471
Short name T494
Test name
Test status
Simulation time 86061494453 ps
CPU time 125.36 seconds
Started Jul 28 07:38:30 PM PDT 24
Finished Jul 28 07:40:35 PM PDT 24
Peak memory 207352 kb
Host smart-81eb0fbe-c23f-4c8f-956a-d97e88fb86f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088826471 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.4088826471
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.352780873
Short name T23
Test name
Test status
Simulation time 95127113589 ps
CPU time 164.69 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:41:22 PM PDT 24
Peak memory 207296 kb
Host smart-a5c07993-4d12-4615-a5c8-efeb4ff48f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35278
0873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.352780873
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1804263862
Short name T1520
Test name
Test status
Simulation time 232739987 ps
CPU time 1.27 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:38:39 PM PDT 24
Peak memory 215560 kb
Host smart-4868f907-3faf-40e5-b8a8-6cf8ad4ad38b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1804263862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1804263862
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.7690287
Short name T1714
Test name
Test status
Simulation time 147897768 ps
CPU time 0.81 seconds
Started Jul 28 07:38:43 PM PDT 24
Finished Jul 28 07:38:44 PM PDT 24
Peak memory 207168 kb
Host smart-9df5c5a0-3d17-4952-afe3-2330ff7844ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76902
87 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.7690287
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.753144326
Short name T1395
Test name
Test status
Simulation time 213805734 ps
CPU time 1.02 seconds
Started Jul 28 07:38:30 PM PDT 24
Finished Jul 28 07:38:31 PM PDT 24
Peak memory 207264 kb
Host smart-9a8cb176-dd8f-4a5d-aa93-fea054a6aae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75314
4326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.753144326
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.2265428627
Short name T831
Test name
Test status
Simulation time 10014024235 ps
CPU time 77.65 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:39:56 PM PDT 24
Peak memory 217220 kb
Host smart-c2296041-c36d-44d0-8a0d-680ecea3dd92
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2265428627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.2265428627
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.2924528671
Short name T2722
Test name
Test status
Simulation time 7800545845 ps
CPU time 53.99 seconds
Started Jul 28 07:38:28 PM PDT 24
Finished Jul 28 07:39:22 PM PDT 24
Peak memory 207388 kb
Host smart-759bf936-426e-4d20-a6ce-af287d841cca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2924528671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.2924528671
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1310945097
Short name T96
Test name
Test status
Simulation time 170107908 ps
CPU time 0.93 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 207084 kb
Host smart-0f9adef4-c200-4fcc-ba49-33b31b9b4d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13109
45097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1310945097
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.4174055962
Short name T574
Test name
Test status
Simulation time 23325779306 ps
CPU time 35.67 seconds
Started Jul 28 07:38:35 PM PDT 24
Finished Jul 28 07:39:10 PM PDT 24
Peak memory 207352 kb
Host smart-3f543736-2e43-4179-98cd-a741256bb859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41740
55962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.4174055962
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.130315560
Short name T550
Test name
Test status
Simulation time 3335242738 ps
CPU time 4.75 seconds
Started Jul 28 07:38:32 PM PDT 24
Finished Jul 28 07:38:36 PM PDT 24
Peak memory 207412 kb
Host smart-b47c5b88-4156-4692-b06f-b8a5da513fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13031
5560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.130315560
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1951688031
Short name T797
Test name
Test status
Simulation time 10197378109 ps
CPU time 292.74 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:43:30 PM PDT 24
Peak memory 215576 kb
Host smart-aea07aa5-9884-420d-b276-8c10f082b37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19516
88031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1951688031
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1562865961
Short name T1214
Test name
Test status
Simulation time 7216057670 ps
CPU time 202.39 seconds
Started Jul 28 07:38:31 PM PDT 24
Finished Jul 28 07:41:53 PM PDT 24
Peak memory 215636 kb
Host smart-07dcf3a4-13b5-4370-a891-3c7bb1d180fd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1562865961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1562865961
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.1300967406
Short name T357
Test name
Test status
Simulation time 241754279 ps
CPU time 0.92 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:38:39 PM PDT 24
Peak memory 207208 kb
Host smart-601a27b2-318f-4e75-9203-2a85cd7bc16c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1300967406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.1300967406
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1844078609
Short name T447
Test name
Test status
Simulation time 186258087 ps
CPU time 0.96 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:38:39 PM PDT 24
Peak memory 207196 kb
Host smart-9dfbd3a5-f72c-4f0f-8fc4-ec26974769a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18440
78609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1844078609
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3864451226
Short name T1469
Test name
Test status
Simulation time 3946089437 ps
CPU time 113.3 seconds
Started Jul 28 07:38:43 PM PDT 24
Finished Jul 28 07:40:36 PM PDT 24
Peak memory 215496 kb
Host smart-c95826f8-acf8-439c-aff0-6a16e8f07c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38644
51226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3864451226
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.4290277607
Short name T319
Test name
Test status
Simulation time 4540936032 ps
CPU time 121.55 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:40:39 PM PDT 24
Peak memory 215648 kb
Host smart-f721a67c-5ebc-4830-928c-c399c35567cd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4290277607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.4290277607
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.4279919522
Short name T1180
Test name
Test status
Simulation time 183326303 ps
CPU time 0.86 seconds
Started Jul 28 07:38:30 PM PDT 24
Finished Jul 28 07:38:31 PM PDT 24
Peak memory 207120 kb
Host smart-92119b50-edb6-4e1e-bb61-496acc51f182
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4279919522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.4279919522
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1172337922
Short name T340
Test name
Test status
Simulation time 149079028 ps
CPU time 0.87 seconds
Started Jul 28 07:38:44 PM PDT 24
Finished Jul 28 07:38:45 PM PDT 24
Peak memory 207204 kb
Host smart-de6b9525-3e54-425c-b644-e5e5c8cbe212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11723
37922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1172337922
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2445510598
Short name T142
Test name
Test status
Simulation time 175634974 ps
CPU time 0.88 seconds
Started Jul 28 07:38:40 PM PDT 24
Finished Jul 28 07:38:41 PM PDT 24
Peak memory 207132 kb
Host smart-4ccb946c-df52-4520-b94f-10899b2ec302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24455
10598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2445510598
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.1472043542
Short name T2617
Test name
Test status
Simulation time 186673497 ps
CPU time 0.88 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 207148 kb
Host smart-ea5e6727-2a13-4cc8-850c-e5908791bddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14720
43542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.1472043542
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2033461174
Short name T680
Test name
Test status
Simulation time 147672071 ps
CPU time 0.88 seconds
Started Jul 28 07:38:34 PM PDT 24
Finished Jul 28 07:38:35 PM PDT 24
Peak memory 207116 kb
Host smart-fe530308-64be-451e-a56f-0db03cbb9485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20334
61174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2033461174
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2668892506
Short name T335
Test name
Test status
Simulation time 164584589 ps
CPU time 0.85 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:38:39 PM PDT 24
Peak memory 207152 kb
Host smart-92c4c565-4510-4eb0-9813-db55b6fbfab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26688
92506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2668892506
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1073538386
Short name T2548
Test name
Test status
Simulation time 170380559 ps
CPU time 0.86 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 207148 kb
Host smart-76335d14-5c2f-45c1-a945-79735350c800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10735
38386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1073538386
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.1696899931
Short name T828
Test name
Test status
Simulation time 255005900 ps
CPU time 1.11 seconds
Started Jul 28 07:38:28 PM PDT 24
Finished Jul 28 07:38:30 PM PDT 24
Peak memory 207312 kb
Host smart-97bd4ae6-6838-45d7-9df8-0b4206979c6d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1696899931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.1696899931
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.2416740090
Short name T194
Test name
Test status
Simulation time 209860512 ps
CPU time 0.96 seconds
Started Jul 28 07:38:29 PM PDT 24
Finished Jul 28 07:38:30 PM PDT 24
Peak memory 207132 kb
Host smart-3b4f1901-1348-469e-8d06-676076f2dc3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24167
40090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.2416740090
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2337612735
Short name T2786
Test name
Test status
Simulation time 144733899 ps
CPU time 0.8 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 206988 kb
Host smart-7f4c6e38-7c19-494e-b4dc-baae06e39ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23376
12735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2337612735
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.94434790
Short name T413
Test name
Test status
Simulation time 114725936 ps
CPU time 0.76 seconds
Started Jul 28 07:38:44 PM PDT 24
Finished Jul 28 07:38:45 PM PDT 24
Peak memory 207128 kb
Host smart-5d44e42f-c602-4431-804e-d9a33b5692aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94434
790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.94434790
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3440752751
Short name T1293
Test name
Test status
Simulation time 8227786489 ps
CPU time 21.35 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:59 PM PDT 24
Peak memory 215624 kb
Host smart-acd3b98f-e76f-4461-a9a9-bea1f9b1d71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34407
52751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3440752751
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2779611600
Short name T344
Test name
Test status
Simulation time 242019850 ps
CPU time 0.98 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:38:39 PM PDT 24
Peak memory 207108 kb
Host smart-99cc8aff-b553-47ef-81c1-2cb87e1c784e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27796
11600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2779611600
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3586557683
Short name T838
Test name
Test status
Simulation time 5562745861 ps
CPU time 37.32 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:39:19 PM PDT 24
Peak memory 217380 kb
Host smart-6c56b6c8-6b95-4fa3-9e92-662c5c91f718
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586557683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3586557683
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2246433196
Short name T157
Test name
Test status
Simulation time 7268858509 ps
CPU time 73 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:39:51 PM PDT 24
Peak memory 223672 kb
Host smart-b1061af0-289f-497e-85a2-768e558ceff7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2246433196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2246433196
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.3237161108
Short name T183
Test name
Test status
Simulation time 12896316597 ps
CPU time 92.65 seconds
Started Jul 28 07:38:35 PM PDT 24
Finished Jul 28 07:40:08 PM PDT 24
Peak memory 223732 kb
Host smart-6fd1447c-217e-4a6a-be3e-3646739b92d5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237161108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.3237161108
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.2823061293
Short name T749
Test name
Test status
Simulation time 225862305 ps
CPU time 0.98 seconds
Started Jul 28 07:38:39 PM PDT 24
Finished Jul 28 07:38:40 PM PDT 24
Peak memory 207112 kb
Host smart-a248f8ae-5664-48e8-8ed4-0fe707a34ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28230
61293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.2823061293
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.1901287211
Short name T1842
Test name
Test status
Simulation time 186377276 ps
CPU time 0.88 seconds
Started Jul 28 07:38:36 PM PDT 24
Finished Jul 28 07:38:37 PM PDT 24
Peak memory 207168 kb
Host smart-ae883b51-76f8-4a47-8a55-812c1148bf64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19012
87211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.1901287211
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1048114058
Short name T2581
Test name
Test status
Simulation time 175024962 ps
CPU time 0.86 seconds
Started Jul 28 07:38:35 PM PDT 24
Finished Jul 28 07:38:36 PM PDT 24
Peak memory 207096 kb
Host smart-8846791f-8a59-4b88-9a00-858af4a1ca56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10481
14058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1048114058
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.964788005
Short name T2496
Test name
Test status
Simulation time 200496991 ps
CPU time 0.93 seconds
Started Jul 28 07:38:42 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 207172 kb
Host smart-b9914d02-878a-4409-a0fe-1de016c3c8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96478
8005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.964788005
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.664324344
Short name T188
Test name
Test status
Simulation time 773121214 ps
CPU time 1.71 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 223992 kb
Host smart-b96f14cb-6928-4afe-8cf8-03432ea590c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=664324344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.664324344
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.898333150
Short name T52
Test name
Test status
Simulation time 385627627 ps
CPU time 1.29 seconds
Started Jul 28 07:38:35 PM PDT 24
Finished Jul 28 07:38:36 PM PDT 24
Peak memory 207268 kb
Host smart-ef03ad4c-6ec8-4081-ba17-c4c9e67c09a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89833
3150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.898333150
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.1686896689
Short name T2681
Test name
Test status
Simulation time 214746047 ps
CPU time 0.95 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:38:39 PM PDT 24
Peak memory 207080 kb
Host smart-98673756-a775-498a-bc4f-6b3b0f43c695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16868
96689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.1686896689
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.905712148
Short name T768
Test name
Test status
Simulation time 148156549 ps
CPU time 0.85 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:38:39 PM PDT 24
Peak memory 207044 kb
Host smart-47a8a53f-af70-4538-b83a-326f5d41e118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90571
2148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.905712148
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2851546957
Short name T1665
Test name
Test status
Simulation time 146884262 ps
CPU time 0.81 seconds
Started Jul 28 07:38:52 PM PDT 24
Finished Jul 28 07:38:53 PM PDT 24
Peak memory 207156 kb
Host smart-3d17c820-2f84-48c1-8c82-353da7aad8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28515
46957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2851546957
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1904092621
Short name T370
Test name
Test status
Simulation time 238527664 ps
CPU time 0.98 seconds
Started Jul 28 07:38:35 PM PDT 24
Finished Jul 28 07:38:36 PM PDT 24
Peak memory 207128 kb
Host smart-073a6bb0-cb02-487d-b0d8-767d649d8de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19040
92621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1904092621
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.2099657862
Short name T953
Test name
Test status
Simulation time 4886734486 ps
CPU time 49.24 seconds
Started Jul 28 07:38:46 PM PDT 24
Finished Jul 28 07:39:35 PM PDT 24
Peak memory 215540 kb
Host smart-c697efc7-ef3b-4198-81b0-56b06d12cc31
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2099657862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.2099657862
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1293380564
Short name T1067
Test name
Test status
Simulation time 188025366 ps
CPU time 0.92 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:38:38 PM PDT 24
Peak memory 207124 kb
Host smart-14362028-d4a5-4e12-8138-5f6b49382ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12933
80564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1293380564
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.1887636804
Short name T1735
Test name
Test status
Simulation time 181036555 ps
CPU time 0.9 seconds
Started Jul 28 07:38:45 PM PDT 24
Finished Jul 28 07:38:46 PM PDT 24
Peak memory 207080 kb
Host smart-c1b41faf-e88d-44c9-8ac0-cc30a0189d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18876
36804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1887636804
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.55629169
Short name T2674
Test name
Test status
Simulation time 555953636 ps
CPU time 1.51 seconds
Started Jul 28 07:38:42 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 207100 kb
Host smart-f6c27fe9-22e8-4870-9e40-502fc5b3bec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55629
169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.55629169
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.3523062303
Short name T2305
Test name
Test status
Simulation time 6539879682 ps
CPU time 193.07 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:41:55 PM PDT 24
Peak memory 215552 kb
Host smart-bdcf2da5-1ce9-4465-a216-cdea482e8371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35230
62303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.3523062303
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1958354874
Short name T81
Test name
Test status
Simulation time 16057338336 ps
CPU time 342.66 seconds
Started Jul 28 07:38:35 PM PDT 24
Finished Jul 28 07:44:18 PM PDT 24
Peak memory 215520 kb
Host smart-ed8ae5df-1e90-4dfa-aa07-fcf82b6ee285
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958354874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.1958354874
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.1209183499
Short name T807
Test name
Test status
Simulation time 4290896683 ps
CPU time 28.86 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:39:07 PM PDT 24
Peak memory 207472 kb
Host smart-ee2c6cc0-572c-4747-8407-6da2570b5d4c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209183499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.1209183499
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.3607415988
Short name T2385
Test name
Test status
Simulation time 36043092 ps
CPU time 0.65 seconds
Started Jul 28 07:42:52 PM PDT 24
Finished Jul 28 07:42:53 PM PDT 24
Peak memory 207132 kb
Host smart-c6f66eba-38ec-4803-aeea-0ff6e7bef6fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3607415988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3607415988
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.1320573774
Short name T791
Test name
Test status
Simulation time 4330172959 ps
CPU time 6.45 seconds
Started Jul 28 07:42:52 PM PDT 24
Finished Jul 28 07:42:59 PM PDT 24
Peak memory 207328 kb
Host smart-bd6633c4-f40c-4d62-8e89-f62da4ee7008
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320573774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.1320573774
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.651495830
Short name T995
Test name
Test status
Simulation time 13320863282 ps
CPU time 16.68 seconds
Started Jul 28 07:42:48 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207384 kb
Host smart-21f5b760-b786-41b1-8286-5e9ef577472e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=651495830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.651495830
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1839666232
Short name T1688
Test name
Test status
Simulation time 23290047133 ps
CPU time 28.58 seconds
Started Jul 28 07:42:38 PM PDT 24
Finished Jul 28 07:43:07 PM PDT 24
Peak memory 207328 kb
Host smart-310f72d7-2ea1-444a-b514-cca310e2ce04
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839666232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_resume.1839666232
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.468587015
Short name T2266
Test name
Test status
Simulation time 228253279 ps
CPU time 0.9 seconds
Started Jul 28 07:42:56 PM PDT 24
Finished Jul 28 07:42:57 PM PDT 24
Peak memory 207132 kb
Host smart-0b7fecf1-558c-4115-9199-c7b51d4c0305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46858
7015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.468587015
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1510559051
Short name T1746
Test name
Test status
Simulation time 150425706 ps
CPU time 0.84 seconds
Started Jul 28 07:42:40 PM PDT 24
Finished Jul 28 07:42:41 PM PDT 24
Peak memory 207048 kb
Host smart-ca1aa24c-b4de-45c1-a9b1-66259388a257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15105
59051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1510559051
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.372381824
Short name T573
Test name
Test status
Simulation time 167962485 ps
CPU time 0.83 seconds
Started Jul 28 07:42:48 PM PDT 24
Finished Jul 28 07:42:49 PM PDT 24
Peak memory 207048 kb
Host smart-379bdd73-856f-4da6-9a5e-8682e815664e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37238
1824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.372381824
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3609351156
Short name T2488
Test name
Test status
Simulation time 672645108 ps
CPU time 1.83 seconds
Started Jul 28 07:42:38 PM PDT 24
Finished Jul 28 07:42:40 PM PDT 24
Peak memory 207300 kb
Host smart-bcb45650-4b15-46d6-9104-a05448316526
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3609351156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3609351156
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.353242096
Short name T2765
Test name
Test status
Simulation time 8828476389 ps
CPU time 18.05 seconds
Started Jul 28 07:42:52 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 207444 kb
Host smart-8386cf68-8b18-4c39-8340-01ed94156470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35324
2096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.353242096
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.1031074751
Short name T346
Test name
Test status
Simulation time 2966354653 ps
CPU time 26.31 seconds
Started Jul 28 07:42:43 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 207412 kb
Host smart-fa4c9436-9900-4f7c-927c-ea5fe01112dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031074751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.1031074751
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3497329062
Short name T2724
Test name
Test status
Simulation time 420823860 ps
CPU time 1.34 seconds
Started Jul 28 07:42:49 PM PDT 24
Finished Jul 28 07:42:51 PM PDT 24
Peak memory 207096 kb
Host smart-c269c25b-d172-4317-a85e-e3b92bab0224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34973
29062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3497329062
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3754546197
Short name T2498
Test name
Test status
Simulation time 154073144 ps
CPU time 0.84 seconds
Started Jul 28 07:42:39 PM PDT 24
Finished Jul 28 07:42:40 PM PDT 24
Peak memory 207096 kb
Host smart-9041145e-6b02-4e44-880c-2cc2bb972455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37545
46197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3754546197
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2296197052
Short name T451
Test name
Test status
Simulation time 55357468 ps
CPU time 0.73 seconds
Started Jul 28 07:42:59 PM PDT 24
Finished Jul 28 07:43:00 PM PDT 24
Peak memory 207032 kb
Host smart-52d45152-f888-42f8-9067-6d1d173cdf86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22961
97052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2296197052
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.2023343992
Short name T1525
Test name
Test status
Simulation time 792962555 ps
CPU time 2.31 seconds
Started Jul 28 07:42:39 PM PDT 24
Finished Jul 28 07:42:41 PM PDT 24
Peak memory 207324 kb
Host smart-3d8443e9-1506-4abd-8ce2-b342e189f3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20233
43992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.2023343992
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3638612009
Short name T956
Test name
Test status
Simulation time 194812984 ps
CPU time 1.8 seconds
Started Jul 28 07:42:57 PM PDT 24
Finished Jul 28 07:42:59 PM PDT 24
Peak memory 207180 kb
Host smart-f9636150-3887-4d4b-a6b5-313a05f7b252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36386
12009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3638612009
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1236283448
Short name T437
Test name
Test status
Simulation time 187024674 ps
CPU time 0.93 seconds
Started Jul 28 07:42:40 PM PDT 24
Finished Jul 28 07:42:41 PM PDT 24
Peak memory 207084 kb
Host smart-05c93a63-5a66-4392-85ab-3cceaa7da2c1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1236283448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1236283448
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.4028008069
Short name T1751
Test name
Test status
Simulation time 133515208 ps
CPU time 0.85 seconds
Started Jul 28 07:42:49 PM PDT 24
Finished Jul 28 07:42:50 PM PDT 24
Peak memory 207132 kb
Host smart-9f834966-5c18-4bca-81a6-7d842211e76f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40280
08069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.4028008069
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1809871501
Short name T393
Test name
Test status
Simulation time 246178925 ps
CPU time 1.01 seconds
Started Jul 28 07:42:50 PM PDT 24
Finished Jul 28 07:42:51 PM PDT 24
Peak memory 207060 kb
Host smart-45ad2b43-7d12-4bcd-85a7-df3ca9c8c05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18098
71501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1809871501
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.1697267332
Short name T2629
Test name
Test status
Simulation time 8461915531 ps
CPU time 67.83 seconds
Started Jul 28 07:42:50 PM PDT 24
Finished Jul 28 07:43:58 PM PDT 24
Peak memory 216920 kb
Host smart-97bf588d-e9d4-4e54-9a5a-4ab988761722
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1697267332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.1697267332
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.2614452261
Short name T1839
Test name
Test status
Simulation time 4152577607 ps
CPU time 50.81 seconds
Started Jul 28 07:42:40 PM PDT 24
Finished Jul 28 07:43:30 PM PDT 24
Peak memory 207348 kb
Host smart-e5003229-ad56-4216-b199-ef461cfa4d55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2614452261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.2614452261
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1285435500
Short name T1534
Test name
Test status
Simulation time 232211292 ps
CPU time 0.98 seconds
Started Jul 28 07:42:57 PM PDT 24
Finished Jul 28 07:42:58 PM PDT 24
Peak memory 207164 kb
Host smart-d81116d7-d724-4f3d-bdfe-85cdf69454b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12854
35500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1285435500
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.910109427
Short name T1316
Test name
Test status
Simulation time 23316610655 ps
CPU time 31.63 seconds
Started Jul 28 07:42:41 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 207388 kb
Host smart-b708ee7f-d54d-4d32-9730-3ebaf92157e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91010
9427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.910109427
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3108552462
Short name T849
Test name
Test status
Simulation time 3324303742 ps
CPU time 4.98 seconds
Started Jul 28 07:42:40 PM PDT 24
Finished Jul 28 07:42:45 PM PDT 24
Peak memory 207368 kb
Host smart-48da3c55-749c-4829-bf12-999e620f8ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31085
52462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3108552462
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.455119663
Short name T580
Test name
Test status
Simulation time 9205981365 ps
CPU time 90.09 seconds
Started Jul 28 07:42:49 PM PDT 24
Finished Jul 28 07:44:19 PM PDT 24
Peak memory 223900 kb
Host smart-aac6abd6-c4dd-420d-959f-17e182344a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45511
9663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.455119663
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1878850744
Short name T1069
Test name
Test status
Simulation time 6590365494 ps
CPU time 65.78 seconds
Started Jul 28 07:42:51 PM PDT 24
Finished Jul 28 07:43:57 PM PDT 24
Peak memory 207484 kb
Host smart-006df8fa-23da-4b35-a4e4-2afd4e2954ec
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1878850744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1878850744
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.3418602996
Short name T452
Test name
Test status
Simulation time 243527612 ps
CPU time 1.13 seconds
Started Jul 28 07:42:39 PM PDT 24
Finished Jul 28 07:42:40 PM PDT 24
Peak memory 207300 kb
Host smart-4ae77736-c1cd-44b6-96dc-7349f3158752
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3418602996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.3418602996
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.996087384
Short name T769
Test name
Test status
Simulation time 200619791 ps
CPU time 0.97 seconds
Started Jul 28 07:43:06 PM PDT 24
Finished Jul 28 07:43:07 PM PDT 24
Peak memory 207148 kb
Host smart-0197f4f8-e932-4a9f-8292-6d2cfd8d7ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99608
7384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.996087384
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.2081429405
Short name T930
Test name
Test status
Simulation time 4875772258 ps
CPU time 49.4 seconds
Started Jul 28 07:42:51 PM PDT 24
Finished Jul 28 07:43:41 PM PDT 24
Peak memory 207300 kb
Host smart-c1760e35-fafa-4b01-8ba2-50bacc57feea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20814
29405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.2081429405
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.2835208018
Short name T2445
Test name
Test status
Simulation time 6430826592 ps
CPU time 191.02 seconds
Started Jul 28 07:42:44 PM PDT 24
Finished Jul 28 07:45:55 PM PDT 24
Peak memory 215572 kb
Host smart-77d3a8f8-64f6-45f3-8ec6-d99c8d222794
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2835208018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.2835208018
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.629679086
Short name T442
Test name
Test status
Simulation time 159981586 ps
CPU time 0.9 seconds
Started Jul 28 07:42:54 PM PDT 24
Finished Jul 28 07:42:55 PM PDT 24
Peak memory 207064 kb
Host smart-5cdb03d3-9dc7-489c-9575-919d2e698141
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=629679086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.629679086
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.710111794
Short name T2045
Test name
Test status
Simulation time 147723713 ps
CPU time 0.83 seconds
Started Jul 28 07:42:44 PM PDT 24
Finished Jul 28 07:42:45 PM PDT 24
Peak memory 207160 kb
Host smart-8ab8e87a-85bf-4285-a5b1-70a149bb6587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71011
1794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.710111794
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.40244997
Short name T1667
Test name
Test status
Simulation time 242555685 ps
CPU time 0.96 seconds
Started Jul 28 07:42:41 PM PDT 24
Finished Jul 28 07:42:42 PM PDT 24
Peak memory 207144 kb
Host smart-70e5469c-9280-40c1-9c2f-5d6bddfde6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40244
997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.40244997
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3845350439
Short name T1522
Test name
Test status
Simulation time 160612680 ps
CPU time 0.9 seconds
Started Jul 28 07:43:06 PM PDT 24
Finished Jul 28 07:43:07 PM PDT 24
Peak memory 207160 kb
Host smart-dadc9de3-3b8f-4cf5-91c4-fafc620fc846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38453
50439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3845350439
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1954811293
Short name T1572
Test name
Test status
Simulation time 154222402 ps
CPU time 0.84 seconds
Started Jul 28 07:42:38 PM PDT 24
Finished Jul 28 07:42:39 PM PDT 24
Peak memory 207096 kb
Host smart-8a90758c-fc34-4fb7-b8f2-1df0312533fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19548
11293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1954811293
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3262847271
Short name T2696
Test name
Test status
Simulation time 237978988 ps
CPU time 0.93 seconds
Started Jul 28 07:42:44 PM PDT 24
Finished Jul 28 07:42:45 PM PDT 24
Peak memory 207116 kb
Host smart-b032b292-ce64-447f-a0f6-ed10640a5d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32628
47271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3262847271
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3637125432
Short name T150
Test name
Test status
Simulation time 175402016 ps
CPU time 0.86 seconds
Started Jul 28 07:42:59 PM PDT 24
Finished Jul 28 07:43:00 PM PDT 24
Peak memory 207116 kb
Host smart-da10a744-7fa0-4fb8-95ce-5465bda8484c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36371
25432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3637125432
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.908839571
Short name T372
Test name
Test status
Simulation time 227258249 ps
CPU time 1.13 seconds
Started Jul 28 07:43:00 PM PDT 24
Finished Jul 28 07:43:01 PM PDT 24
Peak memory 207208 kb
Host smart-64573840-8fec-474e-8bbc-c3b1b6e92124
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=908839571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.908839571
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3130477793
Short name T932
Test name
Test status
Simulation time 161890018 ps
CPU time 0.88 seconds
Started Jul 28 07:42:42 PM PDT 24
Finished Jul 28 07:42:43 PM PDT 24
Peak memory 207156 kb
Host smart-c724c692-9f3e-4e06-9663-4ce066c64805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31304
77793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3130477793
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2437542771
Short name T33
Test name
Test status
Simulation time 37975458 ps
CPU time 0.7 seconds
Started Jul 28 07:42:43 PM PDT 24
Finished Jul 28 07:42:44 PM PDT 24
Peak memory 207084 kb
Host smart-70902f74-3508-4874-9195-0b3a741eba75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24375
42771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2437542771
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3304957592
Short name T240
Test name
Test status
Simulation time 19856807328 ps
CPU time 48.07 seconds
Started Jul 28 07:42:59 PM PDT 24
Finished Jul 28 07:43:47 PM PDT 24
Peak memory 220192 kb
Host smart-3a9668ac-ed39-4efd-82d5-b2c3673bf9a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33049
57592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3304957592
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1164399782
Short name T520
Test name
Test status
Simulation time 169258856 ps
CPU time 0.85 seconds
Started Jul 28 07:42:41 PM PDT 24
Finished Jul 28 07:42:42 PM PDT 24
Peak memory 207168 kb
Host smart-e83fb567-ba88-444a-94bc-7a969d776fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11643
99782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1164399782
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1090720649
Short name T1815
Test name
Test status
Simulation time 245679245 ps
CPU time 1.04 seconds
Started Jul 28 07:42:44 PM PDT 24
Finished Jul 28 07:42:45 PM PDT 24
Peak memory 207112 kb
Host smart-9cf70ecc-28ad-480b-a858-b8eb38135912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10907
20649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1090720649
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.2789189123
Short name T678
Test name
Test status
Simulation time 190528299 ps
CPU time 0.91 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207132 kb
Host smart-5ff05b32-a118-4365-9485-03f36c82798e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27891
89123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.2789189123
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.3568975180
Short name T488
Test name
Test status
Simulation time 177564516 ps
CPU time 0.91 seconds
Started Jul 28 07:42:52 PM PDT 24
Finished Jul 28 07:42:53 PM PDT 24
Peak memory 207188 kb
Host smart-c5c6cfc0-2698-4eff-81cf-9c0c41ca9860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35689
75180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.3568975180
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.138407369
Short name T1890
Test name
Test status
Simulation time 165948582 ps
CPU time 0.87 seconds
Started Jul 28 07:42:46 PM PDT 24
Finished Jul 28 07:42:47 PM PDT 24
Peak memory 207120 kb
Host smart-fdf5d629-9820-4239-a5a3-5d02c245f232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13840
7369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.138407369
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2144661327
Short name T551
Test name
Test status
Simulation time 158292933 ps
CPU time 0.84 seconds
Started Jul 28 07:42:47 PM PDT 24
Finished Jul 28 07:42:47 PM PDT 24
Peak memory 207092 kb
Host smart-7c7e1dfd-6a9e-4da9-8212-346a54cc0e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21446
61327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2144661327
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2322947439
Short name T2851
Test name
Test status
Simulation time 174127711 ps
CPU time 0.87 seconds
Started Jul 28 07:42:57 PM PDT 24
Finished Jul 28 07:42:58 PM PDT 24
Peak memory 207124 kb
Host smart-278c457a-6ccc-463b-b81a-5b4f847d5210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23229
47439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2322947439
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3464942399
Short name T2382
Test name
Test status
Simulation time 228078678 ps
CPU time 1.13 seconds
Started Jul 28 07:42:40 PM PDT 24
Finished Jul 28 07:42:51 PM PDT 24
Peak memory 207300 kb
Host smart-46794861-847b-4d23-943b-975b5919ce9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34649
42399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3464942399
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.3855210830
Short name T2162
Test name
Test status
Simulation time 4439062255 ps
CPU time 37.46 seconds
Started Jul 28 07:43:01 PM PDT 24
Finished Jul 28 07:43:38 PM PDT 24
Peak memory 215616 kb
Host smart-d05a8b9b-e010-457e-98e1-8e7e5b94aa97
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3855210830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.3855210830
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2489347518
Short name T1344
Test name
Test status
Simulation time 145434129 ps
CPU time 0.86 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207172 kb
Host smart-3109c8ae-ae75-4ad0-8029-ccdfcc04d86f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24893
47518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2489347518
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1008969639
Short name T2837
Test name
Test status
Simulation time 175301906 ps
CPU time 0.89 seconds
Started Jul 28 07:42:55 PM PDT 24
Finished Jul 28 07:42:56 PM PDT 24
Peak memory 207056 kb
Host smart-585e5bd3-3403-4447-a9e1-42e0b7d3d182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10089
69639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1008969639
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.2807378196
Short name T771
Test name
Test status
Simulation time 1119240983 ps
CPU time 2.75 seconds
Started Jul 28 07:42:44 PM PDT 24
Finished Jul 28 07:42:52 PM PDT 24
Peak memory 207304 kb
Host smart-9f8391ef-f378-4ca9-b0c8-7751feb1f164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28073
78196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.2807378196
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.616187206
Short name T796
Test name
Test status
Simulation time 4706647519 ps
CPU time 48.67 seconds
Started Jul 28 07:42:45 PM PDT 24
Finished Jul 28 07:43:38 PM PDT 24
Peak memory 216732 kb
Host smart-7ed5b67b-118b-41ff-a2ad-c6c33a40cc05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61618
7206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.616187206
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.1755884773
Short name T1925
Test name
Test status
Simulation time 584593371 ps
CPU time 11.52 seconds
Started Jul 28 07:42:41 PM PDT 24
Finished Jul 28 07:42:52 PM PDT 24
Peak memory 207320 kb
Host smart-54f6e14d-92d4-4f67-b0b1-175e9482b08b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755884773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.1755884773
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2153684376
Short name T521
Test name
Test status
Simulation time 37069199 ps
CPU time 0.67 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 207164 kb
Host smart-7a76f928-8507-4c77-a738-7c83a6363b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2153684376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2153684376
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.1798281874
Short name T2363
Test name
Test status
Simulation time 4386699564 ps
CPU time 6.42 seconds
Started Jul 28 07:42:52 PM PDT 24
Finished Jul 28 07:42:58 PM PDT 24
Peak memory 207404 kb
Host smart-33f54df3-8aa4-4b48-ae18-457e043927c0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798281874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.1798281874
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.101487276
Short name T1478
Test name
Test status
Simulation time 13352184094 ps
CPU time 17.89 seconds
Started Jul 28 07:42:45 PM PDT 24
Finished Jul 28 07:43:03 PM PDT 24
Peak memory 207388 kb
Host smart-e145875d-fc8a-412f-b7fb-5fb5b4913319
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=101487276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.101487276
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3327079203
Short name T1917
Test name
Test status
Simulation time 23335957852 ps
CPU time 27.37 seconds
Started Jul 28 07:43:06 PM PDT 24
Finished Jul 28 07:43:33 PM PDT 24
Peak memory 207408 kb
Host smart-6428ba2a-7bb4-4651-a007-694df5b5b182
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327079203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.3327079203
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.160726613
Short name T2848
Test name
Test status
Simulation time 160853497 ps
CPU time 0.9 seconds
Started Jul 28 07:42:58 PM PDT 24
Finished Jul 28 07:42:59 PM PDT 24
Peak memory 207116 kb
Host smart-e8cf3742-a6d6-41f0-ad42-398e4883ef5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16072
6613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.160726613
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1467781873
Short name T697
Test name
Test status
Simulation time 159025604 ps
CPU time 0.85 seconds
Started Jul 28 07:42:52 PM PDT 24
Finished Jul 28 07:42:53 PM PDT 24
Peak memory 207052 kb
Host smart-d52b4b39-d1f5-42e3-9266-ea2ce3b8312c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14677
81873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1467781873
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3460196523
Short name T2278
Test name
Test status
Simulation time 202334632 ps
CPU time 0.92 seconds
Started Jul 28 07:42:50 PM PDT 24
Finished Jul 28 07:42:51 PM PDT 24
Peak memory 207108 kb
Host smart-5df4cc2e-311a-42d3-ae7f-baea6eb7626f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34601
96523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3460196523
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2750624179
Short name T2667
Test name
Test status
Simulation time 1258887250 ps
CPU time 3.27 seconds
Started Jul 28 07:42:52 PM PDT 24
Finished Jul 28 07:42:56 PM PDT 24
Peak memory 207392 kb
Host smart-d9203727-0466-4a93-85f5-1e0b151df8fc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2750624179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2750624179
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.583403958
Short name T158
Test name
Test status
Simulation time 17810343504 ps
CPU time 39.52 seconds
Started Jul 28 07:42:54 PM PDT 24
Finished Jul 28 07:43:34 PM PDT 24
Peak memory 207368 kb
Host smart-e1be919e-2088-44ce-9693-478705ee2ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58340
3958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.583403958
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.2425983557
Short name T1965
Test name
Test status
Simulation time 1136492423 ps
CPU time 26.1 seconds
Started Jul 28 07:43:00 PM PDT 24
Finished Jul 28 07:43:27 PM PDT 24
Peak memory 207320 kb
Host smart-97633844-98ac-41a6-8ffd-e8a5f5d8392c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425983557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.2425983557
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.2228224089
Short name T716
Test name
Test status
Simulation time 330565027 ps
CPU time 1.3 seconds
Started Jul 28 07:43:14 PM PDT 24
Finished Jul 28 07:43:16 PM PDT 24
Peak memory 207020 kb
Host smart-70a532dd-1d1c-455a-a66e-d761ae336916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22282
24089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.2228224089
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.1717195244
Short name T471
Test name
Test status
Simulation time 146154756 ps
CPU time 0.83 seconds
Started Jul 28 07:42:55 PM PDT 24
Finished Jul 28 07:42:56 PM PDT 24
Peak memory 206992 kb
Host smart-9dc4d9c3-86b0-4eea-9a75-071800300e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17171
95244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.1717195244
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.303862972
Short name T2846
Test name
Test status
Simulation time 86236587 ps
CPU time 0.74 seconds
Started Jul 28 07:42:57 PM PDT 24
Finished Jul 28 07:42:58 PM PDT 24
Peak memory 207084 kb
Host smart-b023817a-34ea-4bda-ae28-257796a13521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30386
2972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.303862972
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.825579097
Short name T1374
Test name
Test status
Simulation time 799721584 ps
CPU time 2.31 seconds
Started Jul 28 07:42:59 PM PDT 24
Finished Jul 28 07:43:01 PM PDT 24
Peak memory 207372 kb
Host smart-b5844598-d13b-4e30-a5d1-998594d43200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82557
9097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.825579097
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1127049505
Short name T1211
Test name
Test status
Simulation time 183445678 ps
CPU time 1.68 seconds
Started Jul 28 07:42:59 PM PDT 24
Finished Jul 28 07:43:01 PM PDT 24
Peak memory 207452 kb
Host smart-854b9578-ade0-4e9c-9c4f-9f3896a9c723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11270
49505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1127049505
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.4173451413
Short name T1588
Test name
Test status
Simulation time 215894396 ps
CPU time 1.11 seconds
Started Jul 28 07:43:05 PM PDT 24
Finished Jul 28 07:43:06 PM PDT 24
Peak memory 207372 kb
Host smart-e50adab7-4fcb-478a-86bd-602eb16a092d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4173451413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.4173451413
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.4136754389
Short name T2282
Test name
Test status
Simulation time 137331685 ps
CPU time 0.84 seconds
Started Jul 28 07:43:11 PM PDT 24
Finished Jul 28 07:43:12 PM PDT 24
Peak memory 207076 kb
Host smart-b5d98e66-176c-4b77-ac05-b1d4140942a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41367
54389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.4136754389
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3958199595
Short name T2062
Test name
Test status
Simulation time 198067541 ps
CPU time 0.97 seconds
Started Jul 28 07:43:08 PM PDT 24
Finished Jul 28 07:43:09 PM PDT 24
Peak memory 207144 kb
Host smart-aef43fa5-0cdb-4533-b261-29aa7b77cfa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39581
99595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3958199595
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.874972239
Short name T1860
Test name
Test status
Simulation time 5263334081 ps
CPU time 152.56 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:45:37 PM PDT 24
Peak memory 215620 kb
Host smart-12badcc6-2af9-4ea0-8521-04b946675159
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=874972239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.874972239
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.4031650979
Short name T979
Test name
Test status
Simulation time 5460225533 ps
CPU time 66.53 seconds
Started Jul 28 07:42:59 PM PDT 24
Finished Jul 28 07:44:06 PM PDT 24
Peak memory 207376 kb
Host smart-eb441205-7a8d-4c5c-b83f-f32de50e1d09
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4031650979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.4031650979
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3443479860
Short name T1986
Test name
Test status
Simulation time 236543101 ps
CPU time 1.02 seconds
Started Jul 28 07:43:00 PM PDT 24
Finished Jul 28 07:43:01 PM PDT 24
Peak memory 207128 kb
Host smart-5043441b-a7af-4256-b0d8-49de37ebde2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34434
79860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3443479860
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.2972984509
Short name T867
Test name
Test status
Simulation time 23334422436 ps
CPU time 27.7 seconds
Started Jul 28 07:43:05 PM PDT 24
Finished Jul 28 07:43:33 PM PDT 24
Peak memory 207404 kb
Host smart-1356aa3d-096b-4d14-8de3-8c2790cfb515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29729
84509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.2972984509
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2274062783
Short name T1892
Test name
Test status
Simulation time 3288176792 ps
CPU time 4.99 seconds
Started Jul 28 07:43:11 PM PDT 24
Finished Jul 28 07:43:16 PM PDT 24
Peak memory 206992 kb
Host smart-882ac578-a0b4-4efe-936c-8d3e9c4de2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22740
62783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2274062783
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2297393067
Short name T1977
Test name
Test status
Simulation time 8175976884 ps
CPU time 245.86 seconds
Started Jul 28 07:43:00 PM PDT 24
Finished Jul 28 07:47:06 PM PDT 24
Peak memory 215520 kb
Host smart-26940910-98f7-4335-a78d-7dc8f5efdbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22973
93067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2297393067
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.143670996
Short name T2213
Test name
Test status
Simulation time 4523295338 ps
CPU time 35.44 seconds
Started Jul 28 07:42:57 PM PDT 24
Finished Jul 28 07:43:33 PM PDT 24
Peak memory 207448 kb
Host smart-2e7cde99-b6ef-4351-9067-cdfc4da9f257
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=143670996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.143670996
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2665950300
Short name T2684
Test name
Test status
Simulation time 259774552 ps
CPU time 1.02 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207136 kb
Host smart-78a93161-dbce-442b-a835-4fd10be1a205
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2665950300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2665950300
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.146753109
Short name T356
Test name
Test status
Simulation time 196038217 ps
CPU time 0.97 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207148 kb
Host smart-2540a243-05cb-4596-992a-98504295aedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14675
3109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.146753109
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.457213913
Short name T169
Test name
Test status
Simulation time 5824589420 ps
CPU time 58.31 seconds
Started Jul 28 07:43:00 PM PDT 24
Finished Jul 28 07:43:58 PM PDT 24
Peak memory 207552 kb
Host smart-829a2fab-236e-47c7-8315-a092d19e41d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45721
3913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.457213913
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.4241767544
Short name T2768
Test name
Test status
Simulation time 5088952921 ps
CPU time 51.08 seconds
Started Jul 28 07:42:59 PM PDT 24
Finished Jul 28 07:43:51 PM PDT 24
Peak memory 216832 kb
Host smart-3aa82f58-536b-461f-9556-432fc0601cc0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4241767544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.4241767544
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3492262194
Short name T1796
Test name
Test status
Simulation time 177402233 ps
CPU time 0.91 seconds
Started Jul 28 07:43:03 PM PDT 24
Finished Jul 28 07:43:04 PM PDT 24
Peak memory 207076 kb
Host smart-9f13c6ed-36f0-4f99-8b3c-ac870e4cb239
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3492262194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3492262194
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3870949142
Short name T2688
Test name
Test status
Simulation time 172277674 ps
CPU time 0.89 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207132 kb
Host smart-a90660ae-4d34-410f-99d1-1ab6db065e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38709
49142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3870949142
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2795641660
Short name T132
Test name
Test status
Simulation time 202688609 ps
CPU time 0.96 seconds
Started Jul 28 07:43:06 PM PDT 24
Finished Jul 28 07:43:07 PM PDT 24
Peak memory 207116 kb
Host smart-fc4671c8-a81a-4fa9-a0a0-0c943e15cf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27956
41660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2795641660
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3518806181
Short name T917
Test name
Test status
Simulation time 182057759 ps
CPU time 0.91 seconds
Started Jul 28 07:43:02 PM PDT 24
Finished Jul 28 07:43:03 PM PDT 24
Peak memory 207148 kb
Host smart-962dcd74-201b-4f7b-b0ee-82f0db33492f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35188
06181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3518806181
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1758690160
Short name T2670
Test name
Test status
Simulation time 226603888 ps
CPU time 0.97 seconds
Started Jul 28 07:43:01 PM PDT 24
Finished Jul 28 07:43:02 PM PDT 24
Peak memory 207196 kb
Host smart-fbab9a7d-a4e5-4ff6-931f-9001fb172eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17586
90160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1758690160
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.457959499
Short name T1655
Test name
Test status
Simulation time 163826160 ps
CPU time 0.86 seconds
Started Jul 28 07:43:14 PM PDT 24
Finished Jul 28 07:43:15 PM PDT 24
Peak memory 207052 kb
Host smart-701067ec-e094-4d9d-a055-9840108c2c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45795
9499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.457959499
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2296153770
Short name T2610
Test name
Test status
Simulation time 147834247 ps
CPU time 0.82 seconds
Started Jul 28 07:43:00 PM PDT 24
Finished Jul 28 07:43:01 PM PDT 24
Peak memory 207280 kb
Host smart-01ba556b-e95a-43ec-aef8-f737b80782ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22961
53770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2296153770
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.2640338812
Short name T1936
Test name
Test status
Simulation time 251705463 ps
CPU time 1.06 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:08 PM PDT 24
Peak memory 206384 kb
Host smart-d53e9967-b141-49b8-bbd3-3c5fa3dd955d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2640338812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.2640338812
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3775194094
Short name T398
Test name
Test status
Simulation time 151963703 ps
CPU time 0.82 seconds
Started Jul 28 07:43:06 PM PDT 24
Finished Jul 28 07:43:07 PM PDT 24
Peak memory 207096 kb
Host smart-2da57a74-43c1-407b-92c0-0ce25db0bc09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37751
94094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3775194094
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.169994538
Short name T26
Test name
Test status
Simulation time 41768049 ps
CPU time 0.72 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:08 PM PDT 24
Peak memory 207084 kb
Host smart-a050595b-3431-4eb5-8d1f-23f652f2ddff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16999
4538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.169994538
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1893386762
Short name T1928
Test name
Test status
Simulation time 17104624263 ps
CPU time 38.87 seconds
Started Jul 28 07:43:05 PM PDT 24
Finished Jul 28 07:43:44 PM PDT 24
Peak memory 219796 kb
Host smart-3edbf1ad-acc2-48b1-82cc-63d478f8ccce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18933
86762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1893386762
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1586540830
Short name T2154
Test name
Test status
Simulation time 185782447 ps
CPU time 0.89 seconds
Started Jul 28 07:43:09 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 207152 kb
Host smart-425e0752-3447-4960-b6ba-d11ea43e6833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15865
40830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1586540830
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.4754834
Short name T351
Test name
Test status
Simulation time 181096864 ps
CPU time 0.98 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207156 kb
Host smart-d8c5b54d-0500-4019-8231-a7ab6387fd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47548
34 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.4754834
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.4036135763
Short name T1524
Test name
Test status
Simulation time 263560317 ps
CPU time 1.01 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:08 PM PDT 24
Peak memory 207048 kb
Host smart-cf876b6b-a0ab-47ed-85ce-80bf11b0935e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40361
35763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.4036135763
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3146320753
Short name T2829
Test name
Test status
Simulation time 185071776 ps
CPU time 1.01 seconds
Started Jul 28 07:43:08 PM PDT 24
Finished Jul 28 07:43:09 PM PDT 24
Peak memory 207288 kb
Host smart-0b588ad0-b86a-46ae-8f4b-e28ad62bc7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31463
20753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3146320753
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2777167451
Short name T2354
Test name
Test status
Simulation time 200491284 ps
CPU time 0.89 seconds
Started Jul 28 07:43:03 PM PDT 24
Finished Jul 28 07:43:09 PM PDT 24
Peak memory 207052 kb
Host smart-ff5a2d7f-1874-40a0-a24b-43bd0e4d2168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27771
67451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2777167451
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.383261693
Short name T1793
Test name
Test status
Simulation time 207234705 ps
CPU time 0.88 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207172 kb
Host smart-9b48cb07-2125-40d7-b793-e2e4029f37b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38326
1693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.383261693
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1547797168
Short name T1506
Test name
Test status
Simulation time 160532564 ps
CPU time 0.89 seconds
Started Jul 28 07:43:10 PM PDT 24
Finished Jul 28 07:43:11 PM PDT 24
Peak memory 207280 kb
Host smart-ff9afdf8-bca4-4b79-ad98-7acd61f7f6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15477
97168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1547797168
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2056767424
Short name T1360
Test name
Test status
Simulation time 207621324 ps
CPU time 1 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207164 kb
Host smart-28f4a062-a261-41bb-ae27-19a098b8283f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20567
67424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2056767424
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1611477494
Short name T2010
Test name
Test status
Simulation time 5567068412 ps
CPU time 167.19 seconds
Started Jul 28 07:43:15 PM PDT 24
Finished Jul 28 07:46:02 PM PDT 24
Peak memory 215504 kb
Host smart-67ab423e-f9ac-4106-a0e6-911b7593402e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1611477494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1611477494
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1420252192
Short name T1788
Test name
Test status
Simulation time 232780231 ps
CPU time 0.92 seconds
Started Jul 28 07:43:09 PM PDT 24
Finished Jul 28 07:43:11 PM PDT 24
Peak memory 207156 kb
Host smart-1f118f30-c8fa-479b-b670-402037084512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14202
52192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1420252192
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.159802522
Short name T371
Test name
Test status
Simulation time 161603527 ps
CPU time 0.81 seconds
Started Jul 28 07:43:06 PM PDT 24
Finished Jul 28 07:43:07 PM PDT 24
Peak memory 207076 kb
Host smart-b97175f9-0765-461b-964b-66127f7c257a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15980
2522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.159802522
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.1942124212
Short name T677
Test name
Test status
Simulation time 1033696767 ps
CPU time 2.52 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 206544 kb
Host smart-d795c7bd-1495-4f86-9a3a-f0108a7d08c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19421
24212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.1942124212
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.494952501
Short name T2175
Test name
Test status
Simulation time 4500126168 ps
CPU time 33.18 seconds
Started Jul 28 07:43:11 PM PDT 24
Finished Jul 28 07:43:45 PM PDT 24
Peak memory 207392 kb
Host smart-5f819b81-9ac0-4a7a-b19f-0340b455e5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49495
2501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.494952501
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.3744810103
Short name T2338
Test name
Test status
Simulation time 2040026237 ps
CPU time 18.16 seconds
Started Jul 28 07:42:52 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 207344 kb
Host smart-60150d23-dc1c-472c-ad39-2743461d58d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744810103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.3744810103
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.1375467744
Short name T590
Test name
Test status
Simulation time 71204811 ps
CPU time 0.71 seconds
Started Jul 28 07:43:11 PM PDT 24
Finished Jul 28 07:43:12 PM PDT 24
Peak memory 207160 kb
Host smart-f5ff308b-9edf-48ab-9d38-fe4960045394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1375467744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.1375467744
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2403146987
Short name T1737
Test name
Test status
Simulation time 3941744875 ps
CPU time 5.92 seconds
Started Jul 28 07:43:11 PM PDT 24
Finished Jul 28 07:43:18 PM PDT 24
Peak memory 207432 kb
Host smart-5b264488-54a1-49a3-b0ff-afe1124f2ec8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403146987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.2403146987
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.2527996241
Short name T1560
Test name
Test status
Simulation time 13338359606 ps
CPU time 16.02 seconds
Started Jul 28 07:43:06 PM PDT 24
Finished Jul 28 07:43:22 PM PDT 24
Peak memory 207404 kb
Host smart-e684f195-707a-4a2e-9d20-a1b98593b113
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527996241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2527996241
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.2932349283
Short name T1920
Test name
Test status
Simulation time 23429986934 ps
CPU time 30.26 seconds
Started Jul 28 07:43:18 PM PDT 24
Finished Jul 28 07:43:48 PM PDT 24
Peak memory 207284 kb
Host smart-105c2fb0-c9eb-4914-b28f-97da545b8d72
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932349283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.2932349283
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1313489936
Short name T1011
Test name
Test status
Simulation time 217536304 ps
CPU time 0.95 seconds
Started Jul 28 07:43:09 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 207096 kb
Host smart-e21459e2-766e-4f7a-b9a9-2bce4282c078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13134
89936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1313489936
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2469845763
Short name T2759
Test name
Test status
Simulation time 148280573 ps
CPU time 0.88 seconds
Started Jul 28 07:43:00 PM PDT 24
Finished Jul 28 07:43:02 PM PDT 24
Peak memory 207080 kb
Host smart-8a3ffbdc-6fb8-4da3-8e4f-ed22c313599c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24698
45763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2469845763
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1422403759
Short name T1079
Test name
Test status
Simulation time 585636114 ps
CPU time 2.07 seconds
Started Jul 28 07:43:10 PM PDT 24
Finished Jul 28 07:43:12 PM PDT 24
Peak memory 207152 kb
Host smart-a5ac1500-2846-467f-94ab-14e45c43eb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14224
03759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1422403759
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3657415221
Short name T970
Test name
Test status
Simulation time 604947544 ps
CPU time 1.76 seconds
Started Jul 28 07:42:54 PM PDT 24
Finished Jul 28 07:42:55 PM PDT 24
Peak memory 207208 kb
Host smart-bad744b6-3139-473c-9943-21eb4328cabf
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3657415221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3657415221
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.3294715366
Short name T1549
Test name
Test status
Simulation time 19417648243 ps
CPU time 41.5 seconds
Started Jul 28 07:43:10 PM PDT 24
Finished Jul 28 07:43:52 PM PDT 24
Peak memory 207332 kb
Host smart-9183eee2-9d56-4040-bddb-da489de33482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32947
15366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3294715366
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.3366774346
Short name T360
Test name
Test status
Simulation time 2262498803 ps
CPU time 14.63 seconds
Started Jul 28 07:42:53 PM PDT 24
Finished Jul 28 07:43:08 PM PDT 24
Peak memory 207288 kb
Host smart-96d30037-9c40-45c1-9169-76e8e117c1a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366774346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.3366774346
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.185616415
Short name T2078
Test name
Test status
Simulation time 348027105 ps
CPU time 1.24 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 207024 kb
Host smart-0bd5ed7b-f50e-441e-ad56-fffcd09ed9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18561
6415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.185616415
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1310665591
Short name T1958
Test name
Test status
Simulation time 134712767 ps
CPU time 0.87 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207120 kb
Host smart-71ae8ce1-52ac-4905-bba7-df02b1cea91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13106
65591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1310665591
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.1019097417
Short name T2236
Test name
Test status
Simulation time 42065691 ps
CPU time 0.72 seconds
Started Jul 28 07:43:08 PM PDT 24
Finished Jul 28 07:43:09 PM PDT 24
Peak memory 207012 kb
Host smart-1e047e55-692a-42a5-bc39-abe64f19a38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10190
97417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1019097417
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1060223044
Short name T638
Test name
Test status
Simulation time 883551720 ps
CPU time 2.4 seconds
Started Jul 28 07:43:03 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207368 kb
Host smart-c46cb7e5-03c8-4095-b521-c937535935ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10602
23044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1060223044
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1037495373
Short name T696
Test name
Test status
Simulation time 296040850 ps
CPU time 2.75 seconds
Started Jul 28 07:43:02 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207316 kb
Host smart-6677e0a0-5e48-46f9-8721-41199ce67350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10374
95373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1037495373
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.3793381698
Short name T1227
Test name
Test status
Simulation time 235237495 ps
CPU time 1.18 seconds
Started Jul 28 07:42:59 PM PDT 24
Finished Jul 28 07:43:00 PM PDT 24
Peak memory 215528 kb
Host smart-4dce45ff-1856-4b02-bbca-b8525557aa88
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3793381698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.3793381698
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3504478250
Short name T2697
Test name
Test status
Simulation time 171558134 ps
CPU time 0.87 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207088 kb
Host smart-0daffd5f-8725-4591-81be-be53a7206110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35044
78250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3504478250
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1170165974
Short name T1730
Test name
Test status
Simulation time 242826875 ps
CPU time 1.01 seconds
Started Jul 28 07:43:08 PM PDT 24
Finished Jul 28 07:43:09 PM PDT 24
Peak memory 207124 kb
Host smart-40d482b8-839d-47c5-9fd2-8aafdf3a4c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11701
65974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1170165974
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.3206029689
Short name T2105
Test name
Test status
Simulation time 9583207680 ps
CPU time 70.18 seconds
Started Jul 28 07:43:09 PM PDT 24
Finished Jul 28 07:44:19 PM PDT 24
Peak memory 215524 kb
Host smart-ef144bbd-0aa0-415c-8778-b3841699e453
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3206029689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.3206029689
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.1459371784
Short name T106
Test name
Test status
Simulation time 10790171263 ps
CPU time 79.65 seconds
Started Jul 28 07:43:01 PM PDT 24
Finished Jul 28 07:44:20 PM PDT 24
Peak memory 207356 kb
Host smart-489a0787-3a4c-439a-8c25-64adadca7c4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1459371784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.1459371784
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.160700785
Short name T1902
Test name
Test status
Simulation time 233561910 ps
CPU time 0.97 seconds
Started Jul 28 07:43:02 PM PDT 24
Finished Jul 28 07:43:03 PM PDT 24
Peak memory 207152 kb
Host smart-c2e71708-9a86-4297-a1ce-43c0ad9a5a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16070
0785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.160700785
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2912623832
Short name T1452
Test name
Test status
Simulation time 23263532671 ps
CPU time 27.47 seconds
Started Jul 28 07:42:58 PM PDT 24
Finished Jul 28 07:43:26 PM PDT 24
Peak memory 207360 kb
Host smart-ebb395cf-51ce-4621-a882-cb869dcfec9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29126
23832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2912623832
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3258440453
Short name T766
Test name
Test status
Simulation time 3319452412 ps
CPU time 5.69 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:43:18 PM PDT 24
Peak memory 207300 kb
Host smart-eac76964-f5a4-4200-8c8e-bdd954de4de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32584
40453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3258440453
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.2286284146
Short name T1777
Test name
Test status
Simulation time 7602940052 ps
CPU time 210.44 seconds
Started Jul 28 07:43:14 PM PDT 24
Finished Jul 28 07:46:44 PM PDT 24
Peak memory 215560 kb
Host smart-19df2526-bc12-4c4b-b34f-401322db03b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
84146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2286284146
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.1106335525
Short name T759
Test name
Test status
Simulation time 7717996182 ps
CPU time 231.76 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:47:04 PM PDT 24
Peak memory 215612 kb
Host smart-4022dcca-39c6-416a-93ec-99a2771480a5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1106335525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.1106335525
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3419348175
Short name T2718
Test name
Test status
Simulation time 241910070 ps
CPU time 1.02 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207072 kb
Host smart-8752738f-8ed8-4aba-81fe-71db236f41b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3419348175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3419348175
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3848534513
Short name T2689
Test name
Test status
Simulation time 208940168 ps
CPU time 0.99 seconds
Started Jul 28 07:43:10 PM PDT 24
Finished Jul 28 07:43:11 PM PDT 24
Peak memory 207156 kb
Host smart-c34954c6-071e-41fa-846f-abdc39e4e6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38485
34513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3848534513
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.2481993081
Short name T146
Test name
Test status
Simulation time 4768416908 ps
CPU time 141.29 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:45:34 PM PDT 24
Peak memory 215600 kb
Host smart-9b3a7971-7200-41ce-b802-ea051d195ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24819
93081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.2481993081
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1281291730
Short name T1393
Test name
Test status
Simulation time 4860603627 ps
CPU time 38.66 seconds
Started Jul 28 07:43:11 PM PDT 24
Finished Jul 28 07:43:50 PM PDT 24
Peak memory 207416 kb
Host smart-9ddcf7ba-7b60-4204-992e-24ad40f8f3be
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1281291730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1281291730
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.1809031371
Short name T2561
Test name
Test status
Simulation time 172146246 ps
CPU time 0.88 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 207076 kb
Host smart-4f63548c-9c1b-4b09-b76e-e947f2c9e3c4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1809031371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.1809031371
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3802089738
Short name T1601
Test name
Test status
Simulation time 161126706 ps
CPU time 0.85 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 207072 kb
Host smart-152c0c43-a1ef-4160-b976-ed0dd501799c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38020
89738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3802089738
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2586736338
Short name T119
Test name
Test status
Simulation time 228497839 ps
CPU time 0.98 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:08 PM PDT 24
Peak memory 207128 kb
Host smart-c41e64b1-e8d5-4564-bae6-5f1f74e352fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25867
36338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2586736338
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1890414057
Short name T1050
Test name
Test status
Simulation time 159405156 ps
CPU time 0.84 seconds
Started Jul 28 07:43:03 PM PDT 24
Finished Jul 28 07:43:04 PM PDT 24
Peak memory 207084 kb
Host smart-094c5c6d-fdc4-4191-9698-95c741475afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18904
14057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1890414057
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3728602309
Short name T2462
Test name
Test status
Simulation time 170362402 ps
CPU time 0.85 seconds
Started Jul 28 07:43:15 PM PDT 24
Finished Jul 28 07:43:16 PM PDT 24
Peak memory 207052 kb
Host smart-870107ac-5750-4b9f-ae6b-79069cd648a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37286
02309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3728602309
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2167648826
Short name T2614
Test name
Test status
Simulation time 201867133 ps
CPU time 0.99 seconds
Started Jul 28 07:43:03 PM PDT 24
Finished Jul 28 07:43:04 PM PDT 24
Peak memory 207084 kb
Host smart-d9bdc3b6-18ec-49d1-b461-3bc15ef3ecd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21676
48826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2167648826
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.579117200
Short name T2679
Test name
Test status
Simulation time 161079634 ps
CPU time 0.87 seconds
Started Jul 28 07:43:05 PM PDT 24
Finished Jul 28 07:43:06 PM PDT 24
Peak memory 207112 kb
Host smart-796e2b63-686d-4ee1-97df-fa9e66b2905c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57911
7200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.579117200
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2756813902
Short name T2299
Test name
Test status
Simulation time 278176256 ps
CPU time 1.01 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:08 PM PDT 24
Peak memory 207116 kb
Host smart-0c6e915b-7400-48de-baee-c2393f189a76
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2756813902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2756813902
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.268958047
Short name T185
Test name
Test status
Simulation time 142092878 ps
CPU time 0.85 seconds
Started Jul 28 07:43:11 PM PDT 24
Finished Jul 28 07:43:12 PM PDT 24
Peak memory 207128 kb
Host smart-13c7186e-bab3-41bc-a2b9-31fc87b44c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26895
8047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.268958047
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.307571557
Short name T596
Test name
Test status
Simulation time 52406310 ps
CPU time 0.75 seconds
Started Jul 28 07:43:03 PM PDT 24
Finished Jul 28 07:43:04 PM PDT 24
Peak memory 207128 kb
Host smart-7505e709-21e3-4937-91a8-a738d9bc6cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30757
1557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.307571557
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.260487117
Short name T1492
Test name
Test status
Simulation time 14412253365 ps
CPU time 38.31 seconds
Started Jul 28 07:43:00 PM PDT 24
Finished Jul 28 07:43:38 PM PDT 24
Peak memory 215612 kb
Host smart-9060a9c5-4a1e-4ec5-a44b-e9fe40576845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26048
7117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.260487117
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.150353501
Short name T1789
Test name
Test status
Simulation time 160424274 ps
CPU time 0.94 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207052 kb
Host smart-965b7c1f-1ec7-4b02-8c22-c3f8a51696c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15035
3501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.150353501
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1101712938
Short name T2122
Test name
Test status
Simulation time 221732135 ps
CPU time 0.92 seconds
Started Jul 28 07:43:09 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 207112 kb
Host smart-ad142fc5-d199-44e9-b7b8-417cf9da2ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11017
12938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1101712938
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.132768397
Short name T1767
Test name
Test status
Simulation time 171444393 ps
CPU time 0.88 seconds
Started Jul 28 07:43:02 PM PDT 24
Finished Jul 28 07:43:03 PM PDT 24
Peak memory 207164 kb
Host smart-a1947f62-0ee9-4045-a693-b16dff7b3e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13276
8397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.132768397
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.708187740
Short name T2319
Test name
Test status
Simulation time 182993967 ps
CPU time 0.92 seconds
Started Jul 28 07:43:01 PM PDT 24
Finished Jul 28 07:43:02 PM PDT 24
Peak memory 207204 kb
Host smart-d059267f-f604-4748-b061-279eaa72328d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70818
7740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.708187740
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3157089428
Short name T2157
Test name
Test status
Simulation time 183292590 ps
CPU time 0.92 seconds
Started Jul 28 07:43:08 PM PDT 24
Finished Jul 28 07:43:09 PM PDT 24
Peak memory 207296 kb
Host smart-a52a8f83-2911-49cf-a411-3cec70eeda7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31570
89428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3157089428
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3161580839
Short name T842
Test name
Test status
Simulation time 170622884 ps
CPU time 0.84 seconds
Started Jul 28 07:43:05 PM PDT 24
Finished Jul 28 07:43:06 PM PDT 24
Peak memory 207120 kb
Host smart-3e4e504e-007d-470a-9abb-887746b6115a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31615
80839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3161580839
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.564486317
Short name T2138
Test name
Test status
Simulation time 162404635 ps
CPU time 0.84 seconds
Started Jul 28 07:43:09 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 207116 kb
Host smart-f3a3e0b9-8223-4c8f-bed1-ba2327f7baac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56448
6317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.564486317
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.4254107197
Short name T1049
Test name
Test status
Simulation time 219836633 ps
CPU time 1.02 seconds
Started Jul 28 07:43:11 PM PDT 24
Finished Jul 28 07:43:12 PM PDT 24
Peak memory 206716 kb
Host smart-653c498e-7093-48e6-92e7-2f27c5a3d17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42541
07197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.4254107197
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2036968182
Short name T1656
Test name
Test status
Simulation time 4912712655 ps
CPU time 144.95 seconds
Started Jul 28 07:43:09 PM PDT 24
Finished Jul 28 07:45:34 PM PDT 24
Peak memory 215596 kb
Host smart-6e582795-f39a-497e-a7c1-6def4cd3cea9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2036968182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2036968182
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3619645266
Short name T1481
Test name
Test status
Simulation time 188415208 ps
CPU time 0.87 seconds
Started Jul 28 07:43:10 PM PDT 24
Finished Jul 28 07:43:11 PM PDT 24
Peak memory 207084 kb
Host smart-239a7db8-c40a-4e4e-aff8-c1a6cd81f461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36196
45266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3619645266
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2925488229
Short name T2009
Test name
Test status
Simulation time 165086818 ps
CPU time 0.85 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207128 kb
Host smart-a1833606-f1f6-41db-805f-3fa8b349556f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29254
88229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2925488229
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.1561790190
Short name T2086
Test name
Test status
Simulation time 836134599 ps
CPU time 2.2 seconds
Started Jul 28 07:43:03 PM PDT 24
Finished Jul 28 07:43:06 PM PDT 24
Peak memory 207288 kb
Host smart-77f03936-d23b-41bc-8e99-73a82af5cb9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15617
90190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.1561790190
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3612875633
Short name T2230
Test name
Test status
Simulation time 7601540771 ps
CPU time 77.66 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:44:22 PM PDT 24
Peak memory 207288 kb
Host smart-a155341d-f3e5-4e5a-83cf-73711023f9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36128
75633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3612875633
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.2487462313
Short name T1251
Test name
Test status
Simulation time 7735952288 ps
CPU time 49.41 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 207368 kb
Host smart-04daffe7-10dc-4867-b083-0e246a69f804
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487462313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos
t_handshake.2487462313
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.3181697802
Short name T182
Test name
Test status
Simulation time 94335073 ps
CPU time 0.77 seconds
Started Jul 28 07:43:14 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207168 kb
Host smart-de1ca74c-dc23-44b8-a698-8c333e79e8d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3181697802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3181697802
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2728381013
Short name T214
Test name
Test status
Simulation time 3619167860 ps
CPU time 5.53 seconds
Started Jul 28 07:42:58 PM PDT 24
Finished Jul 28 07:43:04 PM PDT 24
Peak memory 207376 kb
Host smart-26997980-5841-4456-a5b1-29e3fe0bbcb4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728381013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_disconnect.2728381013
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.540537026
Short name T2843
Test name
Test status
Simulation time 13340559539 ps
CPU time 15.15 seconds
Started Jul 28 07:43:02 PM PDT 24
Finished Jul 28 07:43:17 PM PDT 24
Peak memory 207400 kb
Host smart-15356624-3be3-4362-9bc1-239dc0bb7882
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=540537026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.540537026
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2364154484
Short name T1909
Test name
Test status
Simulation time 23427088597 ps
CPU time 26.96 seconds
Started Jul 28 07:43:03 PM PDT 24
Finished Jul 28 07:43:31 PM PDT 24
Peak memory 207372 kb
Host smart-d47719c0-b893-4574-a1b3-6079b0ee4d2b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364154484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.2364154484
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1536205403
Short name T2152
Test name
Test status
Simulation time 157466711 ps
CPU time 0.89 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207200 kb
Host smart-b121ad32-65bb-4399-a8c5-92f500363b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15362
05403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1536205403
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2420084686
Short name T2256
Test name
Test status
Simulation time 157190382 ps
CPU time 0.83 seconds
Started Jul 28 07:43:09 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 207084 kb
Host smart-592c8978-dbde-4a97-8576-d9e2ec6d9334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24200
84686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2420084686
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.3945526673
Short name T631
Test name
Test status
Simulation time 208949354 ps
CPU time 1.01 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:09 PM PDT 24
Peak memory 207144 kb
Host smart-8a236d17-9cdc-4286-a176-362d513859b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39455
26673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.3945526673
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.4028833315
Short name T1499
Test name
Test status
Simulation time 969635835 ps
CPU time 2.54 seconds
Started Jul 28 07:43:09 PM PDT 24
Finished Jul 28 07:43:12 PM PDT 24
Peak memory 207336 kb
Host smart-2526e51c-366c-45da-ad19-220d1dc7a761
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4028833315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.4028833315
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2728429401
Short name T2029
Test name
Test status
Simulation time 16280478439 ps
CPU time 33.45 seconds
Started Jul 28 07:43:03 PM PDT 24
Finished Jul 28 07:43:37 PM PDT 24
Peak memory 207288 kb
Host smart-e444cf14-9dfa-4b81-8efb-4e8eabb54e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27284
29401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2728429401
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.3778576268
Short name T2214
Test name
Test status
Simulation time 2240454374 ps
CPU time 14.15 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:21 PM PDT 24
Peak memory 207420 kb
Host smart-ffa62e03-9f5f-4253-9090-4ad6f0cf91e2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778576268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.3778576268
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.2818888255
Short name T706
Test name
Test status
Simulation time 442649981 ps
CPU time 1.41 seconds
Started Jul 28 07:43:05 PM PDT 24
Finished Jul 28 07:43:07 PM PDT 24
Peak memory 207008 kb
Host smart-caa1056c-86e3-4405-97da-af36b3d9cc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28188
88255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.2818888255
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.76033781
Short name T1457
Test name
Test status
Simulation time 144299691 ps
CPU time 0.83 seconds
Started Jul 28 07:43:05 PM PDT 24
Finished Jul 28 07:43:06 PM PDT 24
Peak memory 207120 kb
Host smart-e344284d-1327-498f-bfec-2c968eb76718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76033
781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.76033781
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2714869837
Short name T2185
Test name
Test status
Simulation time 37520104 ps
CPU time 0.76 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 207228 kb
Host smart-971773a7-bb16-4b04-a2d6-957bfa0bdbd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27148
69837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2714869837
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.3681216130
Short name T405
Test name
Test status
Simulation time 793881865 ps
CPU time 2.24 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:43:07 PM PDT 24
Peak memory 207356 kb
Host smart-27bb9a63-b16c-4e97-8797-fc284f956b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36812
16130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.3681216130
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1022430668
Short name T2068
Test name
Test status
Simulation time 194086751 ps
CPU time 1.47 seconds
Started Jul 28 07:43:15 PM PDT 24
Finished Jul 28 07:43:17 PM PDT 24
Peak memory 207332 kb
Host smart-36b6357d-9081-41d7-8439-acee782852df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10224
30668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1022430668
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.463171779
Short name T896
Test name
Test status
Simulation time 209131183 ps
CPU time 1.1 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207356 kb
Host smart-a119af62-ade0-4882-8ebd-9dd8c0f66236
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=463171779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.463171779
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2578257093
Short name T1335
Test name
Test status
Simulation time 144892905 ps
CPU time 0.88 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:08 PM PDT 24
Peak memory 207056 kb
Host smart-067a2720-cfc9-43e2-b358-9c6ec6369752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25782
57093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2578257093
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1447778581
Short name T1424
Test name
Test status
Simulation time 230369386 ps
CPU time 1 seconds
Started Jul 28 07:43:16 PM PDT 24
Finished Jul 28 07:43:17 PM PDT 24
Peak memory 207300 kb
Host smart-8942abe3-1989-43e4-8a11-7361aa7c0770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14477
78581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1447778581
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.887208020
Short name T2339
Test name
Test status
Simulation time 6375717401 ps
CPU time 50.66 seconds
Started Jul 28 07:43:16 PM PDT 24
Finished Jul 28 07:44:07 PM PDT 24
Peak memory 217152 kb
Host smart-2c936e5a-1577-4bde-8630-016b9dbd0711
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=887208020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.887208020
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.4155489776
Short name T856
Test name
Test status
Simulation time 7963151060 ps
CPU time 59.63 seconds
Started Jul 28 07:43:18 PM PDT 24
Finished Jul 28 07:44:18 PM PDT 24
Peak memory 207352 kb
Host smart-2cfd0eaf-1554-498f-8c18-a3dcfafcef09
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4155489776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.4155489776
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3840086640
Short name T1554
Test name
Test status
Simulation time 237819781 ps
CPU time 1.07 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207160 kb
Host smart-999bc2e8-dc78-444a-96ed-4fdc872cd2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38400
86640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3840086640
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.3266614578
Short name T563
Test name
Test status
Simulation time 23357616463 ps
CPU time 28 seconds
Started Jul 28 07:43:09 PM PDT 24
Finished Jul 28 07:43:38 PM PDT 24
Peak memory 207144 kb
Host smart-140af32f-4459-46c7-b770-f2b14d3516df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32666
14578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.3266614578
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3550373577
Short name T312
Test name
Test status
Simulation time 3299822553 ps
CPU time 5.2 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:18 PM PDT 24
Peak memory 207356 kb
Host smart-947d1ee0-9824-4905-aa41-136465e82d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35503
73577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3550373577
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.69691376
Short name T2322
Test name
Test status
Simulation time 5819258672 ps
CPU time 43.13 seconds
Started Jul 28 07:43:17 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 215600 kb
Host smart-bd69eef0-2b59-41a8-b20c-0dc1548fdaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69691
376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.69691376
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.2624200318
Short name T1326
Test name
Test status
Simulation time 4315508490 ps
CPU time 33.88 seconds
Started Jul 28 07:43:09 PM PDT 24
Finished Jul 28 07:43:43 PM PDT 24
Peak memory 207328 kb
Host smart-8fdcb47c-f7ef-48d8-be22-b746974e45d1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2624200318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.2624200318
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.4182578441
Short name T1547
Test name
Test status
Simulation time 245076486 ps
CPU time 1 seconds
Started Jul 28 07:43:06 PM PDT 24
Finished Jul 28 07:43:07 PM PDT 24
Peak memory 207160 kb
Host smart-5a2da2a2-c4fa-42c6-8d32-ccca62f1c721
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4182578441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.4182578441
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3327793825
Short name T1123
Test name
Test status
Simulation time 230571878 ps
CPU time 1.03 seconds
Started Jul 28 07:43:03 PM PDT 24
Finished Jul 28 07:43:05 PM PDT 24
Peak memory 207156 kb
Host smart-094cb616-3292-4187-9da5-e593cbc1c5ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33277
93825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3327793825
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.959751212
Short name T1565
Test name
Test status
Simulation time 4290366518 ps
CPU time 127.14 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:45:12 PM PDT 24
Peak memory 215560 kb
Host smart-d5580b3f-ae86-4e1f-9240-a2e0db27eadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95975
1212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.959751212
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.3287871187
Short name T1281
Test name
Test status
Simulation time 3753828282 ps
CPU time 39.04 seconds
Started Jul 28 07:43:06 PM PDT 24
Finished Jul 28 07:43:45 PM PDT 24
Peak memory 216944 kb
Host smart-51c4ddf8-4dad-4c55-a34b-ee95272d6502
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3287871187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.3287871187
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2411249776
Short name T536
Test name
Test status
Simulation time 155272791 ps
CPU time 0.89 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 207300 kb
Host smart-f4c85ac9-ada7-4922-a6f6-8561de47c0aa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2411249776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2411249776
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2399066873
Short name T1981
Test name
Test status
Simulation time 159859156 ps
CPU time 0.84 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207148 kb
Host smart-87a7ebff-6d69-42c8-a09d-f1373345c816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23990
66873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2399066873
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3992605572
Short name T116
Test name
Test status
Simulation time 213854507 ps
CPU time 0.95 seconds
Started Jul 28 07:43:02 PM PDT 24
Finished Jul 28 07:43:04 PM PDT 24
Peak memory 207132 kb
Host smart-d043eb81-e703-4816-afc2-300039281ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39926
05572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3992605572
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.3212872013
Short name T1437
Test name
Test status
Simulation time 144470203 ps
CPU time 0.83 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207088 kb
Host smart-5b188dbd-e99a-467b-a429-3c029b499198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32128
72013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.3212872013
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3395896257
Short name T65
Test name
Test status
Simulation time 154986042 ps
CPU time 0.84 seconds
Started Jul 28 07:43:19 PM PDT 24
Finished Jul 28 07:43:20 PM PDT 24
Peak memory 207096 kb
Host smart-e6420f07-c498-435e-b5d1-716d997bff95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33958
96257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3395896257
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1280989814
Short name T348
Test name
Test status
Simulation time 185064627 ps
CPU time 0.88 seconds
Started Jul 28 07:43:16 PM PDT 24
Finished Jul 28 07:43:17 PM PDT 24
Peak memory 207156 kb
Host smart-4811d5f0-3e6b-4a98-bb2e-671dee8a3c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12809
89814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1280989814
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.132241718
Short name T533
Test name
Test status
Simulation time 150136569 ps
CPU time 0.8 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 207076 kb
Host smart-a32be956-a554-49ff-9a51-c330bbe2ab7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13224
1718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.132241718
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.1382380567
Short name T1236
Test name
Test status
Simulation time 225450310 ps
CPU time 1.03 seconds
Started Jul 28 07:43:09 PM PDT 24
Finished Jul 28 07:43:11 PM PDT 24
Peak memory 206892 kb
Host smart-459d7554-8913-4278-b19e-df65a5defc93
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1382380567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.1382380567
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1422724465
Short name T1997
Test name
Test status
Simulation time 147487792 ps
CPU time 0.82 seconds
Started Jul 28 07:43:10 PM PDT 24
Finished Jul 28 07:43:11 PM PDT 24
Peak memory 207124 kb
Host smart-81785db3-d92d-4cb9-89f9-9bb9d9bbce7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14227
24465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1422724465
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2825355217
Short name T2289
Test name
Test status
Simulation time 35151919 ps
CPU time 0.77 seconds
Started Jul 28 07:43:20 PM PDT 24
Finished Jul 28 07:43:20 PM PDT 24
Peak memory 207012 kb
Host smart-f4e8e96b-9260-4ca9-8d7e-1a1a5ea29193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28253
55217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2825355217
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.586325660
Short name T1446
Test name
Test status
Simulation time 17112849259 ps
CPU time 43.45 seconds
Started Jul 28 07:43:20 PM PDT 24
Finished Jul 28 07:44:03 PM PDT 24
Peak memory 223848 kb
Host smart-3462b4cc-4d58-43a1-8fe6-6c5aa4ac7d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58632
5660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.586325660
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2836528543
Short name T2364
Test name
Test status
Simulation time 182576303 ps
CPU time 0.94 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207136 kb
Host smart-2b08a059-d99e-4b0f-b435-7ff25acd4c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28365
28543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2836528543
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3911057413
Short name T1699
Test name
Test status
Simulation time 163571359 ps
CPU time 0.89 seconds
Started Jul 28 07:43:15 PM PDT 24
Finished Jul 28 07:43:16 PM PDT 24
Peak memory 207056 kb
Host smart-e3b56e36-27aa-4f2e-a2c9-00063fa5561d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39110
57413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3911057413
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2511122530
Short name T1367
Test name
Test status
Simulation time 178780990 ps
CPU time 0.85 seconds
Started Jul 28 07:43:23 PM PDT 24
Finished Jul 28 07:43:23 PM PDT 24
Peak memory 207296 kb
Host smart-a237f865-1c0b-43a9-9bba-41ce9b92935d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25111
22530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2511122530
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3349006326
Short name T2372
Test name
Test status
Simulation time 185430670 ps
CPU time 0.94 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207080 kb
Host smart-5783c42d-66ad-40d8-9210-76b314b0750d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33490
06326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3349006326
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.3087757269
Short name T602
Test name
Test status
Simulation time 172483265 ps
CPU time 0.89 seconds
Started Jul 28 07:43:15 PM PDT 24
Finished Jul 28 07:43:16 PM PDT 24
Peak memory 207140 kb
Host smart-a1ab7631-9cc3-4029-b0ec-26f6f61cd65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30877
57269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.3087757269
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.710031036
Short name T1019
Test name
Test status
Simulation time 148035525 ps
CPU time 0.82 seconds
Started Jul 28 07:43:08 PM PDT 24
Finished Jul 28 07:43:09 PM PDT 24
Peak memory 207096 kb
Host smart-b91473ab-d939-45af-abc6-586f775e2556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71003
1036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.710031036
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.899442973
Short name T1148
Test name
Test status
Simulation time 149583198 ps
CPU time 0.88 seconds
Started Jul 28 07:43:23 PM PDT 24
Finished Jul 28 07:43:24 PM PDT 24
Peak memory 207272 kb
Host smart-61167c3d-2f1f-4a89-98ca-9689a68b8968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89944
2973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.899442973
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3180029433
Short name T1315
Test name
Test status
Simulation time 246578925 ps
CPU time 0.98 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207144 kb
Host smart-9b421f9c-9448-44b5-94f1-82ed61519021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31800
29433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3180029433
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.298268074
Short name T2106
Test name
Test status
Simulation time 7026684300 ps
CPU time 194.52 seconds
Started Jul 28 07:43:14 PM PDT 24
Finished Jul 28 07:46:28 PM PDT 24
Peak memory 215596 kb
Host smart-5d346813-2a06-4197-96fc-ef1a534e118b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=298268074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.298268074
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3848054133
Short name T273
Test name
Test status
Simulation time 223589543 ps
CPU time 0.92 seconds
Started Jul 28 07:43:17 PM PDT 24
Finished Jul 28 07:43:18 PM PDT 24
Peak memory 207132 kb
Host smart-9aa8c827-9d3a-42e7-885d-5d4745545adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38480
54133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3848054133
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3665686223
Short name T1722
Test name
Test status
Simulation time 176354158 ps
CPU time 0.97 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 207128 kb
Host smart-7c647172-68c7-4373-a2a2-bb278b2c0bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36656
86223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3665686223
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.3587380963
Short name T2284
Test name
Test status
Simulation time 689915292 ps
CPU time 1.96 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207156 kb
Host smart-9685a0dd-2c7d-42fd-82b5-5d4ab585bd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35873
80963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.3587380963
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3882959848
Short name T2774
Test name
Test status
Simulation time 3568797485 ps
CPU time 36.75 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:43:49 PM PDT 24
Peak memory 217184 kb
Host smart-32ee968f-f709-4edc-8eff-c420300b7006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38829
59848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3882959848
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.2577452706
Short name T983
Test name
Test status
Simulation time 1581008141 ps
CPU time 13.56 seconds
Started Jul 28 07:43:04 PM PDT 24
Finished Jul 28 07:43:18 PM PDT 24
Peak memory 207416 kb
Host smart-717cd9df-161d-4091-915a-d0083106703b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577452706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.2577452706
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.918463715
Short name T1143
Test name
Test status
Simulation time 29210004 ps
CPU time 0.65 seconds
Started Jul 28 07:43:22 PM PDT 24
Finished Jul 28 07:43:23 PM PDT 24
Peak memory 207172 kb
Host smart-88a249ad-c472-4c68-9253-349df3f4dacc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=918463715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.918463715
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.176207753
Short name T1471
Test name
Test status
Simulation time 4009225441 ps
CPU time 6.64 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:19 PM PDT 24
Peak memory 207284 kb
Host smart-1c7b10d9-2e9e-47c6-8b65-33b5c5d1f22c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176207753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_ao
n_wake_disconnect.176207753
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.2389384677
Short name T783
Test name
Test status
Simulation time 13361045739 ps
CPU time 16.17 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:23 PM PDT 24
Peak memory 207336 kb
Host smart-0a7fd27c-cdf9-47ac-8122-7168acfd02c5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389384677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.2389384677
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1983607720
Short name T986
Test name
Test status
Simulation time 23303284097 ps
CPU time 28.25 seconds
Started Jul 28 07:43:11 PM PDT 24
Finished Jul 28 07:43:39 PM PDT 24
Peak memory 207344 kb
Host smart-689e82aa-0eb2-4756-a32c-76b75b4e9568
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983607720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.1983607720
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3738380587
Short name T1224
Test name
Test status
Simulation time 225449770 ps
CPU time 0.99 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:08 PM PDT 24
Peak memory 207160 kb
Host smart-5b3c7259-9804-4eb4-9cd8-69bf2009bad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37383
80587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3738380587
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.3295676245
Short name T402
Test name
Test status
Simulation time 154656676 ps
CPU time 0.85 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207036 kb
Host smart-e1a3060a-d9e0-4dfa-802a-58ae5e67bd18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32956
76245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.3295676245
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.405476012
Short name T1460
Test name
Test status
Simulation time 350601554 ps
CPU time 1.44 seconds
Started Jul 28 07:43:16 PM PDT 24
Finished Jul 28 07:43:18 PM PDT 24
Peak memory 207284 kb
Host smart-902161a1-336f-40b6-87d7-fe9d2ff62699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40547
6012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.405476012
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.28580702
Short name T1942
Test name
Test status
Simulation time 486411684 ps
CPU time 1.47 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 207052 kb
Host smart-8841b825-6019-4eba-8359-9b512e44bfe1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=28580702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.28580702
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.3956094109
Short name T1568
Test name
Test status
Simulation time 15039715214 ps
CPU time 36.34 seconds
Started Jul 28 07:43:23 PM PDT 24
Finished Jul 28 07:43:59 PM PDT 24
Peak memory 207336 kb
Host smart-13636a0f-9f47-46f0-b46d-82a8110dc0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39560
94109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3956094109
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.4066256830
Short name T1819
Test name
Test status
Simulation time 558866434 ps
CPU time 11.49 seconds
Started Jul 28 07:43:18 PM PDT 24
Finished Jul 28 07:43:29 PM PDT 24
Peak memory 207304 kb
Host smart-99a6d6b5-1951-4e78-ba10-8af1064ab5a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066256830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.4066256830
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.752343930
Short name T2857
Test name
Test status
Simulation time 490616462 ps
CPU time 1.59 seconds
Started Jul 28 07:43:15 PM PDT 24
Finished Jul 28 07:43:17 PM PDT 24
Peak memory 207116 kb
Host smart-40758d4c-569f-476e-adad-dbac010ab8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75234
3930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.752343930
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.196724910
Short name T1756
Test name
Test status
Simulation time 134561307 ps
CPU time 0.78 seconds
Started Jul 28 07:43:14 PM PDT 24
Finished Jul 28 07:43:15 PM PDT 24
Peak memory 207172 kb
Host smart-595eb3ca-9399-4fd8-be66-94c6a26c8cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19672
4910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.196724910
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1809007078
Short name T2454
Test name
Test status
Simulation time 44083252 ps
CPU time 0.72 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207116 kb
Host smart-4099d0bc-bbff-4d57-b13b-137ffc4d91e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18090
07078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1809007078
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.359175102
Short name T1500
Test name
Test status
Simulation time 930167654 ps
CPU time 2.38 seconds
Started Jul 28 07:43:07 PM PDT 24
Finished Jul 28 07:43:10 PM PDT 24
Peak memory 207316 kb
Host smart-b5cc99ac-27c1-4a8a-b79e-c6859a335417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35917
5102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.359175102
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2255729077
Short name T754
Test name
Test status
Simulation time 401021170 ps
CPU time 2.89 seconds
Started Jul 28 07:43:29 PM PDT 24
Finished Jul 28 07:43:32 PM PDT 24
Peak memory 207364 kb
Host smart-dbdd0427-789a-4ebc-bf00-a0cf2a48fbec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22557
29077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2255729077
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3233961350
Short name T1713
Test name
Test status
Simulation time 182595980 ps
CPU time 0.96 seconds
Started Jul 28 07:43:28 PM PDT 24
Finished Jul 28 07:43:29 PM PDT 24
Peak memory 207336 kb
Host smart-c39568ff-2fc5-4ca5-81a1-f33df2f1cee6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3233961350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3233961350
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3438944732
Short name T880
Test name
Test status
Simulation time 153535482 ps
CPU time 0.83 seconds
Started Jul 28 07:43:19 PM PDT 24
Finished Jul 28 07:43:20 PM PDT 24
Peak memory 207084 kb
Host smart-69943d20-d431-472c-8392-90bfef8cc8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34389
44732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3438944732
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2454282505
Short name T2158
Test name
Test status
Simulation time 221809502 ps
CPU time 0.95 seconds
Started Jul 28 07:43:14 PM PDT 24
Finished Jul 28 07:43:15 PM PDT 24
Peak memory 207060 kb
Host smart-217d10d9-fc6c-438a-9f9e-7e780d785932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24542
82505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2454282505
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.630608689
Short name T1617
Test name
Test status
Simulation time 7473429787 ps
CPU time 224.89 seconds
Started Jul 28 07:43:14 PM PDT 24
Finished Jul 28 07:46:59 PM PDT 24
Peak memory 215536 kb
Host smart-29e51f51-4c9b-47aa-a964-10c2219159c8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=630608689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.630608689
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.2752367160
Short name T91
Test name
Test status
Simulation time 4421229837 ps
CPU time 29.49 seconds
Started Jul 28 07:43:20 PM PDT 24
Finished Jul 28 07:43:49 PM PDT 24
Peak memory 207332 kb
Host smart-29506976-0ed4-4c4a-a7e8-5ae8fd2bd3cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2752367160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.2752367160
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.598296291
Short name T998
Test name
Test status
Simulation time 182384871 ps
CPU time 0.87 seconds
Started Jul 28 07:43:15 PM PDT 24
Finished Jul 28 07:43:16 PM PDT 24
Peak memory 207208 kb
Host smart-71212963-34f2-498c-8eab-a4c292f9421c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59829
6291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.598296291
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.348923007
Short name T968
Test name
Test status
Simulation time 23329503029 ps
CPU time 28.34 seconds
Started Jul 28 07:43:18 PM PDT 24
Finished Jul 28 07:43:46 PM PDT 24
Peak memory 207364 kb
Host smart-a1f2a820-b66f-4fe6-9671-34b9ff2155d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34892
3007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.348923007
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2182556200
Short name T2566
Test name
Test status
Simulation time 3358645516 ps
CPU time 5.34 seconds
Started Jul 28 07:43:14 PM PDT 24
Finished Jul 28 07:43:20 PM PDT 24
Peak memory 207312 kb
Host smart-42e17773-138c-4dae-9a56-677ae5a487ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21825
56200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2182556200
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.1563405611
Short name T1530
Test name
Test status
Simulation time 8867551998 ps
CPU time 64.49 seconds
Started Jul 28 07:43:17 PM PDT 24
Finished Jul 28 07:44:22 PM PDT 24
Peak memory 217444 kb
Host smart-356b746c-2732-42ef-a272-14b4350871b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15634
05611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.1563405611
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.409611261
Short name T775
Test name
Test status
Simulation time 2953205278 ps
CPU time 21.28 seconds
Started Jul 28 07:43:16 PM PDT 24
Finished Jul 28 07:43:37 PM PDT 24
Peak memory 217048 kb
Host smart-0d37582e-93c7-4814-9715-79d0315a1248
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=409611261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.409611261
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.739732570
Short name T652
Test name
Test status
Simulation time 275375990 ps
CPU time 1.01 seconds
Started Jul 28 07:43:13 PM PDT 24
Finished Jul 28 07:43:14 PM PDT 24
Peak memory 207124 kb
Host smart-55c1f603-1e27-4c5c-80a4-ea7f6f728b19
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=739732570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.739732570
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1928866419
Short name T436
Test name
Test status
Simulation time 188494932 ps
CPU time 0.93 seconds
Started Jul 28 07:43:28 PM PDT 24
Finished Jul 28 07:43:29 PM PDT 24
Peak memory 207120 kb
Host smart-88774912-5cc4-4470-bc37-24d509c4f27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19288
66419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1928866419
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.1333237196
Short name T93
Test name
Test status
Simulation time 4336018489 ps
CPU time 34.4 seconds
Started Jul 28 07:43:15 PM PDT 24
Finished Jul 28 07:43:50 PM PDT 24
Peak memory 217012 kb
Host smart-dfdcd928-c897-426f-b123-3cd9d6282302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13332
37196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.1333237196
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3988034142
Short name T2542
Test name
Test status
Simulation time 6342284915 ps
CPU time 61.55 seconds
Started Jul 28 07:43:35 PM PDT 24
Finished Jul 28 07:44:36 PM PDT 24
Peak memory 207436 kb
Host smart-5b34d59b-6685-4d25-ad97-f2aadb657bc5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3988034142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3988034142
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.607147037
Short name T316
Test name
Test status
Simulation time 204644614 ps
CPU time 0.96 seconds
Started Jul 28 07:43:23 PM PDT 24
Finished Jul 28 07:43:24 PM PDT 24
Peak memory 207120 kb
Host smart-2f6060bc-71b1-499f-b17e-48416b001168
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=607147037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.607147037
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.959606441
Short name T510
Test name
Test status
Simulation time 160077926 ps
CPU time 0.86 seconds
Started Jul 28 07:43:15 PM PDT 24
Finished Jul 28 07:43:16 PM PDT 24
Peak memory 207124 kb
Host smart-04efeb28-66d7-497b-9856-a200499d6b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95960
6441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.959606441
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3883406865
Short name T124
Test name
Test status
Simulation time 222883381 ps
CPU time 0.96 seconds
Started Jul 28 07:43:19 PM PDT 24
Finished Jul 28 07:43:20 PM PDT 24
Peak memory 207196 kb
Host smart-296abca0-c1e4-4b41-b027-3219e29d4678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38834
06865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3883406865
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3917529087
Short name T434
Test name
Test status
Simulation time 186856964 ps
CPU time 0.95 seconds
Started Jul 28 07:43:21 PM PDT 24
Finished Jul 28 07:43:22 PM PDT 24
Peak memory 207156 kb
Host smart-6a282a26-e477-4bf9-b95c-b1ec2ae6e492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39175
29087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3917529087
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2561454531
Short name T2826
Test name
Test status
Simulation time 148510658 ps
CPU time 0.78 seconds
Started Jul 28 07:43:22 PM PDT 24
Finished Jul 28 07:43:23 PM PDT 24
Peak memory 207116 kb
Host smart-ca64e8e0-4210-4d4e-99c1-6d11962eb792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25614
54531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2561454531
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1723225326
Short name T975
Test name
Test status
Simulation time 163539102 ps
CPU time 0.88 seconds
Started Jul 28 07:43:20 PM PDT 24
Finished Jul 28 07:43:21 PM PDT 24
Peak memory 207132 kb
Host smart-ef29274b-8446-4c89-aa49-53d65647066e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17232
25326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1723225326
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.3696258894
Short name T2572
Test name
Test status
Simulation time 151133549 ps
CPU time 0.79 seconds
Started Jul 28 07:43:20 PM PDT 24
Finished Jul 28 07:43:20 PM PDT 24
Peak memory 207100 kb
Host smart-3c38800f-859c-406a-b7a2-a6aba0e00d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36962
58894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.3696258894
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.2693747871
Short name T2506
Test name
Test status
Simulation time 189659157 ps
CPU time 0.91 seconds
Started Jul 28 07:43:21 PM PDT 24
Finished Jul 28 07:43:22 PM PDT 24
Peak memory 207152 kb
Host smart-44f389f8-31ec-45d0-9c0b-e06ac991e920
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2693747871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.2693747871
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1323528627
Short name T2854
Test name
Test status
Simulation time 152486688 ps
CPU time 0.85 seconds
Started Jul 28 07:43:21 PM PDT 24
Finished Jul 28 07:43:22 PM PDT 24
Peak memory 207116 kb
Host smart-c71cc5a3-e625-4df8-88b7-5c6031061a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13235
28627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1323528627
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2072769288
Short name T25
Test name
Test status
Simulation time 52654454 ps
CPU time 0.7 seconds
Started Jul 28 07:43:26 PM PDT 24
Finished Jul 28 07:43:27 PM PDT 24
Peak memory 207100 kb
Host smart-4ae593f0-0780-4a4f-af1a-c66256bd3855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20727
69288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2072769288
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1675238427
Short name T2725
Test name
Test status
Simulation time 6753889199 ps
CPU time 19.65 seconds
Started Jul 28 07:43:22 PM PDT 24
Finished Jul 28 07:43:41 PM PDT 24
Peak memory 215596 kb
Host smart-c3d00d42-0eb8-4304-a9f1-26da710ca400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16752
38427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1675238427
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2066116719
Short name T616
Test name
Test status
Simulation time 155827458 ps
CPU time 0.84 seconds
Started Jul 28 07:43:22 PM PDT 24
Finished Jul 28 07:43:23 PM PDT 24
Peak memory 207128 kb
Host smart-9f8e58a8-c47c-4849-9989-3e4f656d1db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20661
16719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2066116719
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2157787978
Short name T650
Test name
Test status
Simulation time 203954414 ps
CPU time 0.91 seconds
Started Jul 28 07:43:31 PM PDT 24
Finished Jul 28 07:43:32 PM PDT 24
Peak memory 207108 kb
Host smart-f41c0caa-ee51-4440-ba4f-b8d94f3f8ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21577
87978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2157787978
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.981166
Short name T592
Test name
Test status
Simulation time 177216541 ps
CPU time 0.88 seconds
Started Jul 28 07:43:15 PM PDT 24
Finished Jul 28 07:43:16 PM PDT 24
Peak memory 207180 kb
Host smart-535fd84a-311d-40c7-b062-7a763ce26dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98116
6 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.981166
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.1846623128
Short name T1229
Test name
Test status
Simulation time 155266119 ps
CPU time 0.86 seconds
Started Jul 28 07:43:23 PM PDT 24
Finished Jul 28 07:43:24 PM PDT 24
Peak memory 207108 kb
Host smart-7e422048-df1e-4406-87df-9aa1e2e346b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18466
23128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.1846623128
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.2640793304
Short name T2007
Test name
Test status
Simulation time 175812895 ps
CPU time 0.9 seconds
Started Jul 28 07:43:19 PM PDT 24
Finished Jul 28 07:43:20 PM PDT 24
Peak memory 207296 kb
Host smart-b1909125-31c2-42a9-9591-d3c06ac3aa5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26407
93304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.2640793304
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.2795317784
Short name T839
Test name
Test status
Simulation time 199140285 ps
CPU time 0.93 seconds
Started Jul 28 07:43:31 PM PDT 24
Finished Jul 28 07:43:32 PM PDT 24
Peak memory 207072 kb
Host smart-1bea6c08-ebfe-4c5f-8aa6-e8a5f7f14763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27953
17784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.2795317784
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.354383648
Short name T2813
Test name
Test status
Simulation time 183367123 ps
CPU time 0.89 seconds
Started Jul 28 07:43:31 PM PDT 24
Finished Jul 28 07:43:32 PM PDT 24
Peak memory 207144 kb
Host smart-db8d4c2f-cd61-4d7f-9024-f61b32f96ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35438
3648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.354383648
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.202459028
Short name T2040
Test name
Test status
Simulation time 217226553 ps
CPU time 0.99 seconds
Started Jul 28 07:43:16 PM PDT 24
Finished Jul 28 07:43:17 PM PDT 24
Peak memory 207148 kb
Host smart-f53a1175-5258-460d-a10e-1e0970978b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20245
9028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.202459028
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1378879394
Short name T1172
Test name
Test status
Simulation time 6098853087 ps
CPU time 62.1 seconds
Started Jul 28 07:43:15 PM PDT 24
Finished Jul 28 07:44:18 PM PDT 24
Peak memory 215552 kb
Host smart-351b8c63-8717-4946-a6bc-3686377c42bf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1378879394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1378879394
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.78156206
Short name T1556
Test name
Test status
Simulation time 211603390 ps
CPU time 0.91 seconds
Started Jul 28 07:43:31 PM PDT 24
Finished Jul 28 07:43:32 PM PDT 24
Peak memory 207104 kb
Host smart-7e8d160f-1e4b-407c-9ee8-50ec306c6fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78156
206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.78156206
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.443563191
Short name T1630
Test name
Test status
Simulation time 188851256 ps
CPU time 0.88 seconds
Started Jul 28 07:43:18 PM PDT 24
Finished Jul 28 07:43:19 PM PDT 24
Peak memory 207116 kb
Host smart-ae6d1266-14fa-40ca-a35d-4eb50e3eff4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44356
3191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.443563191
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.543374944
Short name T2864
Test name
Test status
Simulation time 627093241 ps
CPU time 1.76 seconds
Started Jul 28 07:43:15 PM PDT 24
Finished Jul 28 07:43:17 PM PDT 24
Peak memory 207048 kb
Host smart-c46cdc0e-6470-40f9-8df5-8fe9ded4577b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54337
4944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.543374944
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.368168111
Short name T2066
Test name
Test status
Simulation time 3250183014 ps
CPU time 24.57 seconds
Started Jul 28 07:43:24 PM PDT 24
Finished Jul 28 07:43:49 PM PDT 24
Peak memory 216980 kb
Host smart-4721c939-2f6b-4b80-bfe3-7e031395a908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36816
8111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.368168111
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.3432849361
Short name T1953
Test name
Test status
Simulation time 844304597 ps
CPU time 5.41 seconds
Started Jul 28 07:43:12 PM PDT 24
Finished Jul 28 07:43:18 PM PDT 24
Peak memory 207344 kb
Host smart-36190614-06ca-4b8c-8485-18f96f759dcd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432849361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos
t_handshake.3432849361
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.3600456314
Short name T2246
Test name
Test status
Simulation time 44288413 ps
CPU time 0.68 seconds
Started Jul 28 07:43:28 PM PDT 24
Finished Jul 28 07:43:31 PM PDT 24
Peak memory 207188 kb
Host smart-51daa84a-d01f-4e03-a4c8-42a692288bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3600456314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.3600456314
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.1107595121
Short name T1370
Test name
Test status
Simulation time 3989032492 ps
CPU time 5.93 seconds
Started Jul 28 07:43:18 PM PDT 24
Finished Jul 28 07:43:24 PM PDT 24
Peak memory 207404 kb
Host smart-403f472b-a0a7-4803-8fda-4bdfccae9582
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107595121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.1107595121
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2812363594
Short name T2839
Test name
Test status
Simulation time 13373951733 ps
CPU time 15.42 seconds
Started Jul 28 07:43:20 PM PDT 24
Finished Jul 28 07:43:35 PM PDT 24
Peak memory 207348 kb
Host smart-da5a68ba-1cbf-4194-bdba-87a424e3bbed
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812363594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2812363594
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3359871636
Short name T657
Test name
Test status
Simulation time 23436715972 ps
CPU time 35.41 seconds
Started Jul 28 07:43:20 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 207388 kb
Host smart-5300fb05-5861-4e00-9fe1-77589dbe1fee
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359871636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_resume.3359871636
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2392659684
Short name T2577
Test name
Test status
Simulation time 172187100 ps
CPU time 0.91 seconds
Started Jul 28 07:43:18 PM PDT 24
Finished Jul 28 07:43:19 PM PDT 24
Peak memory 207076 kb
Host smart-170f7b9e-f328-4571-99dc-b50a810af652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23926
59684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2392659684
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.943644620
Short name T1993
Test name
Test status
Simulation time 152221001 ps
CPU time 0.85 seconds
Started Jul 28 07:43:22 PM PDT 24
Finished Jul 28 07:43:22 PM PDT 24
Peak memory 207036 kb
Host smart-ba2702cc-a60a-49a1-b742-2ee7c5a79f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94364
4620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.943644620
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2208666929
Short name T2304
Test name
Test status
Simulation time 314442276 ps
CPU time 1.13 seconds
Started Jul 28 07:43:23 PM PDT 24
Finished Jul 28 07:43:25 PM PDT 24
Peak memory 207136 kb
Host smart-2e4c693c-3279-47da-9637-a2f8878f9b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22086
66929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2208666929
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.2363059425
Short name T2630
Test name
Test status
Simulation time 313370838 ps
CPU time 1.22 seconds
Started Jul 28 07:43:25 PM PDT 24
Finished Jul 28 07:43:27 PM PDT 24
Peak memory 207140 kb
Host smart-bfce6948-7295-414a-97d1-2b38b2a8ccec
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2363059425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.2363059425
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.2689165136
Short name T914
Test name
Test status
Simulation time 6586001720 ps
CPU time 14.08 seconds
Started Jul 28 07:43:27 PM PDT 24
Finished Jul 28 07:43:41 PM PDT 24
Peak memory 207392 kb
Host smart-bf00fd3c-5937-4eb0-bb91-239de5bbfc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26891
65136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.2689165136
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.2971682614
Short name T435
Test name
Test status
Simulation time 9765543582 ps
CPU time 65.81 seconds
Started Jul 28 07:43:20 PM PDT 24
Finished Jul 28 07:44:26 PM PDT 24
Peak memory 207364 kb
Host smart-ca73a5fa-1376-4d39-92ef-4a0d2da9cf12
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971682614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.2971682614
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.985599020
Short name T539
Test name
Test status
Simulation time 448525728 ps
CPU time 1.44 seconds
Started Jul 28 07:43:37 PM PDT 24
Finished Jul 28 07:43:38 PM PDT 24
Peak memory 207092 kb
Host smart-218c069a-621f-405d-9de7-faa3daf162a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98559
9020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.985599020
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.4089167979
Short name T951
Test name
Test status
Simulation time 150886631 ps
CPU time 0.81 seconds
Started Jul 28 07:43:22 PM PDT 24
Finished Jul 28 07:43:23 PM PDT 24
Peak memory 207096 kb
Host smart-4ac04c44-e81f-48d2-a536-17ed65321c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40891
67979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.4089167979
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3664065117
Short name T1758
Test name
Test status
Simulation time 36048625 ps
CPU time 0.7 seconds
Started Jul 28 07:43:21 PM PDT 24
Finished Jul 28 07:43:22 PM PDT 24
Peak memory 207104 kb
Host smart-25159475-0bde-4c75-baf8-9463ff94efa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36640
65117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3664065117
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.264786022
Short name T757
Test name
Test status
Simulation time 983887873 ps
CPU time 2.64 seconds
Started Jul 28 07:43:27 PM PDT 24
Finished Jul 28 07:43:30 PM PDT 24
Peak memory 207348 kb
Host smart-08702297-7804-470a-bb39-38450c5d2449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26478
6022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.264786022
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.965050529
Short name T1357
Test name
Test status
Simulation time 184557051 ps
CPU time 1.94 seconds
Started Jul 28 07:43:22 PM PDT 24
Finished Jul 28 07:43:24 PM PDT 24
Peak memory 207316 kb
Host smart-1043b380-7819-4579-b586-1200b5e6f8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96505
0529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.965050529
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2826528838
Short name T354
Test name
Test status
Simulation time 151592326 ps
CPU time 0.81 seconds
Started Jul 28 07:43:25 PM PDT 24
Finished Jul 28 07:43:26 PM PDT 24
Peak memory 207108 kb
Host smart-e477d9b6-4519-45bf-ab52-1e7d076eac24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28265
28838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2826528838
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2929242982
Short name T1769
Test name
Test status
Simulation time 241348466 ps
CPU time 1.06 seconds
Started Jul 28 07:43:26 PM PDT 24
Finished Jul 28 07:43:27 PM PDT 24
Peak memory 207172 kb
Host smart-f89d88c4-49b2-43c9-b16c-0cf0416095c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29292
42982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2929242982
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.3033004349
Short name T1347
Test name
Test status
Simulation time 7584100475 ps
CPU time 59.04 seconds
Started Jul 28 07:43:32 PM PDT 24
Finished Jul 28 07:44:31 PM PDT 24
Peak memory 217184 kb
Host smart-d7208d31-f519-4537-ae5d-155dd3fbe1f4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3033004349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.3033004349
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.3396024319
Short name T1197
Test name
Test status
Simulation time 12091906922 ps
CPU time 77.45 seconds
Started Jul 28 07:43:38 PM PDT 24
Finished Jul 28 07:44:56 PM PDT 24
Peak memory 207356 kb
Host smart-c58c858a-bf76-468a-ae9e-491e8152cc4b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3396024319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.3396024319
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1373681397
Short name T1893
Test name
Test status
Simulation time 229013968 ps
CPU time 0.92 seconds
Started Jul 28 07:43:26 PM PDT 24
Finished Jul 28 07:43:27 PM PDT 24
Peak memory 207120 kb
Host smart-55eae117-7e6f-47d5-ba74-fee8178bebe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13736
81397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1373681397
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.3797199537
Short name T1352
Test name
Test status
Simulation time 23301703851 ps
CPU time 29.97 seconds
Started Jul 28 07:43:34 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 207400 kb
Host smart-9a175dbc-fd81-4b80-9f0a-2d93915c5623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37971
99537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.3797199537
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1667282111
Short name T429
Test name
Test status
Simulation time 3299696574 ps
CPU time 5.67 seconds
Started Jul 28 07:43:33 PM PDT 24
Finished Jul 28 07:43:38 PM PDT 24
Peak memory 207320 kb
Host smart-551cd45e-aa11-41f9-b69e-0949cacd3a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16672
82111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1667282111
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.2908616950
Short name T1695
Test name
Test status
Simulation time 6064091374 ps
CPU time 58.93 seconds
Started Jul 28 07:43:32 PM PDT 24
Finished Jul 28 07:44:31 PM PDT 24
Peak memory 217048 kb
Host smart-dc92e2e7-eb9a-4e6b-b568-1890afcfa1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29086
16950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.2908616950
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2295956737
Short name T709
Test name
Test status
Simulation time 4311095536 ps
CPU time 126.46 seconds
Started Jul 28 07:43:42 PM PDT 24
Finished Jul 28 07:45:49 PM PDT 24
Peak memory 215524 kb
Host smart-1c479a15-dafe-4c32-8945-3a07e16685d5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2295956737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2295956737
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2239666032
Short name T342
Test name
Test status
Simulation time 264217422 ps
CPU time 0.99 seconds
Started Jul 28 07:43:25 PM PDT 24
Finished Jul 28 07:43:26 PM PDT 24
Peak memory 207144 kb
Host smart-cdb860e6-7687-4551-b21c-c88673fecf6d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2239666032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2239666032
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.197415295
Short name T1985
Test name
Test status
Simulation time 219927960 ps
CPU time 0.91 seconds
Started Jul 28 07:43:30 PM PDT 24
Finished Jul 28 07:43:31 PM PDT 24
Peak memory 207100 kb
Host smart-dfbc8af9-4951-4866-969b-5c2d485d0f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19741
5295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.197415295
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.3952206236
Short name T1595
Test name
Test status
Simulation time 4883695071 ps
CPU time 38.89 seconds
Started Jul 28 07:43:22 PM PDT 24
Finished Jul 28 07:44:01 PM PDT 24
Peak memory 217156 kb
Host smart-8e64b834-5288-4755-b9d5-4aac71fa4e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39522
06236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.3952206236
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.3345294874
Short name T1260
Test name
Test status
Simulation time 2828390177 ps
CPU time 83.89 seconds
Started Jul 28 07:43:39 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 215548 kb
Host smart-d77904b0-33fc-4c92-b608-05c1caa37ad4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3345294874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.3345294874
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3749858129
Short name T2558
Test name
Test status
Simulation time 172918678 ps
CPU time 0.91 seconds
Started Jul 28 07:43:30 PM PDT 24
Finished Jul 28 07:43:31 PM PDT 24
Peak memory 207200 kb
Host smart-834b2ab8-760b-48c0-ad34-f1e6481eea2c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3749858129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3749858129
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.112671458
Short name T777
Test name
Test status
Simulation time 137074208 ps
CPU time 0.79 seconds
Started Jul 28 07:43:25 PM PDT 24
Finished Jul 28 07:43:26 PM PDT 24
Peak memory 207144 kb
Host smart-44443ae0-ebb8-416c-9e43-5e499dd8c931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11267
1458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.112671458
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.302710723
Short name T133
Test name
Test status
Simulation time 216631071 ps
CPU time 0.92 seconds
Started Jul 28 07:43:41 PM PDT 24
Finished Jul 28 07:43:42 PM PDT 24
Peak memory 207044 kb
Host smart-b807766c-9164-4735-bfaf-a71faef70ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30271
0723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.302710723
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.811217799
Short name T470
Test name
Test status
Simulation time 227452660 ps
CPU time 0.94 seconds
Started Jul 28 07:43:24 PM PDT 24
Finished Jul 28 07:43:25 PM PDT 24
Peak memory 207112 kb
Host smart-66f05726-2e98-42ab-acc1-522cf7822121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81121
7799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.811217799
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1332205110
Short name T641
Test name
Test status
Simulation time 178655162 ps
CPU time 0.89 seconds
Started Jul 28 07:43:32 PM PDT 24
Finished Jul 28 07:43:33 PM PDT 24
Peak memory 207200 kb
Host smart-01d5c94f-b878-477e-aa54-5f8fed22ea32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13322
05110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1332205110
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2314184736
Short name T2099
Test name
Test status
Simulation time 169197486 ps
CPU time 0.86 seconds
Started Jul 28 07:43:26 PM PDT 24
Finished Jul 28 07:43:27 PM PDT 24
Peak memory 207128 kb
Host smart-3560fb9a-1cf4-4047-9a82-38f4cfb6d910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23141
84736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2314184736
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1715430156
Short name T2556
Test name
Test status
Simulation time 184010090 ps
CPU time 0.94 seconds
Started Jul 28 07:43:30 PM PDT 24
Finished Jul 28 07:43:31 PM PDT 24
Peak memory 207176 kb
Host smart-6c664064-0785-4627-9363-3f87989b225d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17154
30156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1715430156
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.2793922187
Short name T2396
Test name
Test status
Simulation time 250251650 ps
CPU time 1.05 seconds
Started Jul 28 07:43:24 PM PDT 24
Finished Jul 28 07:43:25 PM PDT 24
Peak memory 207144 kb
Host smart-a7864b6d-f098-4b8e-b3a8-9e2872ada3f1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2793922187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.2793922187
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.80806851
Short name T537
Test name
Test status
Simulation time 175776407 ps
CPU time 0.87 seconds
Started Jul 28 07:43:28 PM PDT 24
Finished Jul 28 07:43:29 PM PDT 24
Peak memory 207108 kb
Host smart-2c63bd71-7694-49a3-aa29-a534813fcbfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80806
851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.80806851
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1204073456
Short name T1
Test name
Test status
Simulation time 54915160 ps
CPU time 0.72 seconds
Started Jul 28 07:43:30 PM PDT 24
Finished Jul 28 07:43:31 PM PDT 24
Peak memory 207140 kb
Host smart-20f810ac-5df5-4b8e-ad07-338b11b0fc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12040
73456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1204073456
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.402332890
Short name T1398
Test name
Test status
Simulation time 14589042622 ps
CPU time 35.45 seconds
Started Jul 28 07:43:28 PM PDT 24
Finished Jul 28 07:44:03 PM PDT 24
Peak memory 215608 kb
Host smart-36116492-ea02-4375-ab0f-ae8e5f11746a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40233
2890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.402332890
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3446700755
Short name T2723
Test name
Test status
Simulation time 185802934 ps
CPU time 0.89 seconds
Started Jul 28 07:43:35 PM PDT 24
Finished Jul 28 07:43:36 PM PDT 24
Peak memory 207084 kb
Host smart-0dd39997-ccd5-42de-a307-824e02161cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34467
00755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3446700755
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.314720723
Short name T1990
Test name
Test status
Simulation time 223306531 ps
CPU time 0.95 seconds
Started Jul 28 07:43:27 PM PDT 24
Finished Jul 28 07:43:28 PM PDT 24
Peak memory 207092 kb
Host smart-8d241b9e-8f8e-4765-bd13-2d54f0dc1018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31472
0723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.314720723
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.2786778821
Short name T1288
Test name
Test status
Simulation time 208895560 ps
CPU time 0.95 seconds
Started Jul 28 07:43:35 PM PDT 24
Finished Jul 28 07:43:36 PM PDT 24
Peak memory 207132 kb
Host smart-e1a04e02-58c4-4bea-b23b-c3c793ad8895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
78821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2786778821
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3301569488
Short name T1006
Test name
Test status
Simulation time 234618254 ps
CPU time 0.94 seconds
Started Jul 28 07:43:25 PM PDT 24
Finished Jul 28 07:43:26 PM PDT 24
Peak memory 207096 kb
Host smart-8afc0031-695c-479e-8bf0-1a142a3732e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33015
69488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3301569488
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2015239309
Short name T1085
Test name
Test status
Simulation time 163874714 ps
CPU time 0.83 seconds
Started Jul 28 07:43:27 PM PDT 24
Finished Jul 28 07:43:31 PM PDT 24
Peak memory 207100 kb
Host smart-01dd574c-9164-4bfb-a882-1c132b125efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20152
39309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2015239309
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3510885794
Short name T1048
Test name
Test status
Simulation time 159609750 ps
CPU time 0.85 seconds
Started Jul 28 07:43:22 PM PDT 24
Finished Jul 28 07:43:23 PM PDT 24
Peak memory 207268 kb
Host smart-c27fc0f0-6fca-4146-b9d0-7343f56e801e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35108
85794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3510885794
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2632257868
Short name T2595
Test name
Test status
Simulation time 154503224 ps
CPU time 0.85 seconds
Started Jul 28 07:43:41 PM PDT 24
Finished Jul 28 07:43:42 PM PDT 24
Peak memory 207200 kb
Host smart-29894c7f-2e34-4c4a-b424-c52cd81e2d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26322
57868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2632257868
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.4260527038
Short name T48
Test name
Test status
Simulation time 210911818 ps
CPU time 0.98 seconds
Started Jul 28 07:43:36 PM PDT 24
Finished Jul 28 07:43:37 PM PDT 24
Peak memory 207068 kb
Host smart-8b85b60b-83ce-4e9b-9fa4-96e318c0c701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42605
27038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.4260527038
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.2516295484
Short name T2374
Test name
Test status
Simulation time 5353295769 ps
CPU time 53.04 seconds
Started Jul 28 07:43:39 PM PDT 24
Finished Jul 28 07:44:32 PM PDT 24
Peak memory 215632 kb
Host smart-2bcba9fd-3de1-4fea-81d0-2c0766c95e1d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2516295484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.2516295484
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2593629444
Short name T776
Test name
Test status
Simulation time 149869880 ps
CPU time 0.86 seconds
Started Jul 28 07:43:25 PM PDT 24
Finished Jul 28 07:43:25 PM PDT 24
Peak memory 207272 kb
Host smart-2daa3116-847c-4c3c-b2ff-63bbf4e8ffe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25936
29444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2593629444
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3150836967
Short name T1975
Test name
Test status
Simulation time 158946360 ps
CPU time 0.87 seconds
Started Jul 28 07:43:34 PM PDT 24
Finished Jul 28 07:43:35 PM PDT 24
Peak memory 207208 kb
Host smart-5ab359ea-e251-4598-ad23-f50e9b609989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31508
36967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3150836967
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.798287168
Short name T206
Test name
Test status
Simulation time 904184775 ps
CPU time 2.18 seconds
Started Jul 28 07:43:30 PM PDT 24
Finished Jul 28 07:43:37 PM PDT 24
Peak memory 207404 kb
Host smart-1b89a6ae-eff4-4044-b445-360c18d2b968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79828
7168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.798287168
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1266031398
Short name T1505
Test name
Test status
Simulation time 8139748132 ps
CPU time 246.45 seconds
Started Jul 28 07:43:34 PM PDT 24
Finished Jul 28 07:47:40 PM PDT 24
Peak memory 215524 kb
Host smart-e9817c42-30bd-411c-a8b4-d2a76f4b8ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12660
31398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1266031398
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.1588034190
Short name T1889
Test name
Test status
Simulation time 6369436326 ps
CPU time 41.25 seconds
Started Jul 28 07:43:25 PM PDT 24
Finished Jul 28 07:44:07 PM PDT 24
Peak memory 207424 kb
Host smart-12f0ef85-45a4-42cf-b1d7-5a42f8eb4279
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588034190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.1588034190
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.114855800
Short name T1241
Test name
Test status
Simulation time 45179488 ps
CPU time 0.69 seconds
Started Jul 28 07:43:50 PM PDT 24
Finished Jul 28 07:43:51 PM PDT 24
Peak memory 207164 kb
Host smart-6a622956-09ef-460c-8c4e-bc6ad262ad92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=114855800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.114855800
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.1589171077
Short name T1435
Test name
Test status
Simulation time 3883630905 ps
CPU time 5.87 seconds
Started Jul 28 07:43:33 PM PDT 24
Finished Jul 28 07:43:39 PM PDT 24
Peak memory 207444 kb
Host smart-cdd71374-d12f-408b-bdcd-b3d0945f605c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589171077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.1589171077
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3680823794
Short name T2793
Test name
Test status
Simulation time 13360355767 ps
CPU time 16.82 seconds
Started Jul 28 07:43:26 PM PDT 24
Finished Jul 28 07:43:42 PM PDT 24
Peak memory 207368 kb
Host smart-f9c5d79f-6159-4e82-ad9f-a8ee85730e3c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680823794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3680823794
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.1248945353
Short name T2032
Test name
Test status
Simulation time 23378149083 ps
CPU time 28.84 seconds
Started Jul 28 07:43:42 PM PDT 24
Finished Jul 28 07:44:11 PM PDT 24
Peak memory 207412 kb
Host smart-ef6ee85a-a121-41bc-8f11-2f6c1e1256e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248945353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.1248945353
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1982338337
Short name T2860
Test name
Test status
Simulation time 182414902 ps
CPU time 0.94 seconds
Started Jul 28 07:43:25 PM PDT 24
Finished Jul 28 07:43:26 PM PDT 24
Peak memory 207268 kb
Host smart-c57a9bf8-f447-4199-93cd-ca25812b6fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19823
38337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1982338337
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3551514536
Short name T2070
Test name
Test status
Simulation time 149917111 ps
CPU time 0.8 seconds
Started Jul 28 07:43:27 PM PDT 24
Finished Jul 28 07:43:28 PM PDT 24
Peak memory 207088 kb
Host smart-4cf6936a-4ccf-4233-8a21-0aa7dd002b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35515
14536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3551514536
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.606259727
Short name T1704
Test name
Test status
Simulation time 180275210 ps
CPU time 0.89 seconds
Started Jul 28 07:43:25 PM PDT 24
Finished Jul 28 07:43:26 PM PDT 24
Peak memory 207132 kb
Host smart-0c09aa32-d878-4bf5-8d64-5539c2b5cbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60625
9727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.606259727
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1406249587
Short name T2535
Test name
Test status
Simulation time 458682917 ps
CPU time 1.55 seconds
Started Jul 28 07:43:38 PM PDT 24
Finished Jul 28 07:43:40 PM PDT 24
Peak memory 207048 kb
Host smart-2bd95a00-1406-4025-a10d-aa0127d63ad8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1406249587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1406249587
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.3538653458
Short name T853
Test name
Test status
Simulation time 22224269057 ps
CPU time 42.2 seconds
Started Jul 28 07:43:27 PM PDT 24
Finished Jul 28 07:44:12 PM PDT 24
Peak memory 207348 kb
Host smart-3cb6bc42-ecf7-4799-95c2-47c2218968f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35386
53458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.3538653458
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.2742468346
Short name T1600
Test name
Test status
Simulation time 1121008240 ps
CPU time 9.25 seconds
Started Jul 28 07:43:28 PM PDT 24
Finished Jul 28 07:43:37 PM PDT 24
Peak memory 207316 kb
Host smart-a207a5ea-ffff-40c8-aef6-ddfaff4a7e27
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742468346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.2742468346
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.2245731639
Short name T109
Test name
Test status
Simulation time 341982761 ps
CPU time 1.29 seconds
Started Jul 28 07:43:29 PM PDT 24
Finished Jul 28 07:43:30 PM PDT 24
Peak memory 207108 kb
Host smart-91d07f3f-a57d-4676-8b08-663d1a511599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22457
31639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.2245731639
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2876696397
Short name T1420
Test name
Test status
Simulation time 140322069 ps
CPU time 0.9 seconds
Started Jul 28 07:43:44 PM PDT 24
Finished Jul 28 07:43:45 PM PDT 24
Peak memory 207052 kb
Host smart-0d15d2e6-06b3-40e2-a5d3-d860af5f90da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28766
96397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2876696397
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.501555224
Short name T1627
Test name
Test status
Simulation time 35015879 ps
CPU time 0.7 seconds
Started Jul 28 07:43:45 PM PDT 24
Finished Jul 28 07:43:46 PM PDT 24
Peak memory 207096 kb
Host smart-dbe7bfad-fce8-4a1b-a789-161e5f373b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50155
5224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.501555224
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.467862287
Short name T2267
Test name
Test status
Simulation time 908588132 ps
CPU time 2.38 seconds
Started Jul 28 07:43:35 PM PDT 24
Finished Jul 28 07:43:37 PM PDT 24
Peak memory 207284 kb
Host smart-22a22c53-f6cc-4c30-8cf8-07465826da22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46786
2287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.467862287
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2409743502
Short name T552
Test name
Test status
Simulation time 279185620 ps
CPU time 2.17 seconds
Started Jul 28 07:43:36 PM PDT 24
Finished Jul 28 07:43:38 PM PDT 24
Peak memory 207364 kb
Host smart-54efd6e8-0ded-4620-bc62-e3e2602c6e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24097
43502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2409743502
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2531177382
Short name T1179
Test name
Test status
Simulation time 245541566 ps
CPU time 1.08 seconds
Started Jul 28 07:43:40 PM PDT 24
Finished Jul 28 07:43:41 PM PDT 24
Peak memory 215596 kb
Host smart-da32ca71-194a-4d39-ab92-4e055898fe90
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2531177382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2531177382
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4263942226
Short name T2508
Test name
Test status
Simulation time 204822922 ps
CPU time 0.88 seconds
Started Jul 28 07:43:29 PM PDT 24
Finished Jul 28 07:43:30 PM PDT 24
Peak memory 207104 kb
Host smart-9948d453-c54d-4dd5-be48-7e7f9bcada9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42639
42226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4263942226
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3314388099
Short name T1581
Test name
Test status
Simulation time 167894869 ps
CPU time 0.9 seconds
Started Jul 28 07:43:28 PM PDT 24
Finished Jul 28 07:43:29 PM PDT 24
Peak memory 207168 kb
Host smart-d3837ba0-f38b-45e1-a1dd-c81200632ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33143
88099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3314388099
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.1579570317
Short name T1364
Test name
Test status
Simulation time 11897496137 ps
CPU time 83.73 seconds
Started Jul 28 07:43:44 PM PDT 24
Finished Jul 28 07:45:08 PM PDT 24
Peak memory 207424 kb
Host smart-9e901bb4-3e10-4658-a21a-e25365c66d99
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1579570317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.1579570317
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.271367140
Short name T374
Test name
Test status
Simulation time 259261207 ps
CPU time 1.02 seconds
Started Jul 28 07:43:28 PM PDT 24
Finished Jul 28 07:43:29 PM PDT 24
Peak memory 207136 kb
Host smart-4f8ce090-4b37-44b5-b3f9-b360131265b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27136
7140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.271367140
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.3693889558
Short name T1579
Test name
Test status
Simulation time 23314712578 ps
CPU time 30 seconds
Started Jul 28 07:43:44 PM PDT 24
Finished Jul 28 07:44:14 PM PDT 24
Peak memory 207272 kb
Host smart-f55bd953-ac43-480f-b465-883ead422b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36938
89558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.3693889558
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1816780351
Short name T2819
Test name
Test status
Simulation time 3322859829 ps
CPU time 4.7 seconds
Started Jul 28 07:43:30 PM PDT 24
Finished Jul 28 07:43:45 PM PDT 24
Peak memory 207424 kb
Host smart-2c958fa6-8d3b-4fe9-9271-31b23ce41d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18167
80351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1816780351
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2644021223
Short name T2700
Test name
Test status
Simulation time 7595681356 ps
CPU time 217.89 seconds
Started Jul 28 07:43:38 PM PDT 24
Finished Jul 28 07:47:17 PM PDT 24
Peak memory 215480 kb
Host smart-c6332e45-a5a3-4178-9b62-60661859774a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26440
21223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2644021223
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.1105671958
Short name T612
Test name
Test status
Simulation time 3100271026 ps
CPU time 88.01 seconds
Started Jul 28 07:43:35 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 215608 kb
Host smart-ff956a8c-cce2-48e5-b4e6-85b10a7fbbe2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1105671958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.1105671958
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2429406640
Short name T2504
Test name
Test status
Simulation time 280203365 ps
CPU time 1.03 seconds
Started Jul 28 07:43:36 PM PDT 24
Finished Jul 28 07:43:37 PM PDT 24
Peak memory 207144 kb
Host smart-b5a4c963-44c2-4932-b971-4114e23f560b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2429406640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2429406640
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1935128875
Short name T1202
Test name
Test status
Simulation time 230931397 ps
CPU time 0.95 seconds
Started Jul 28 07:43:27 PM PDT 24
Finished Jul 28 07:43:28 PM PDT 24
Peak memory 207100 kb
Host smart-c84e545c-3e11-4254-a3aa-8658c91cc93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19351
28875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1935128875
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.3528948685
Short name T1444
Test name
Test status
Simulation time 6470649270 ps
CPU time 186 seconds
Started Jul 28 07:43:29 PM PDT 24
Finished Jul 28 07:46:35 PM PDT 24
Peak memory 215552 kb
Host smart-7c9709fb-e660-4c78-82ff-f4abd68e328f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35289
48685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.3528948685
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.2304531204
Short name T1402
Test name
Test status
Simulation time 4355220380 ps
CPU time 130.06 seconds
Started Jul 28 07:43:40 PM PDT 24
Finished Jul 28 07:45:50 PM PDT 24
Peak memory 215500 kb
Host smart-70bc27e5-a2de-45a0-a70d-37e29ff12e4b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2304531204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.2304531204
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.3340622481
Short name T821
Test name
Test status
Simulation time 164610781 ps
CPU time 0.87 seconds
Started Jul 28 07:43:30 PM PDT 24
Finished Jul 28 07:43:31 PM PDT 24
Peak memory 207140 kb
Host smart-cdcf262b-4400-4075-b20c-e545ed03b8b8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3340622481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.3340622481
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2640102271
Short name T723
Test name
Test status
Simulation time 166005770 ps
CPU time 0.83 seconds
Started Jul 28 07:43:27 PM PDT 24
Finished Jul 28 07:43:28 PM PDT 24
Peak memory 207272 kb
Host smart-2b5c8fe3-161f-40ed-b290-c1b8cc797361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26401
02271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2640102271
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1945312173
Short name T115
Test name
Test status
Simulation time 179450801 ps
CPU time 0.9 seconds
Started Jul 28 07:43:52 PM PDT 24
Finished Jul 28 07:43:53 PM PDT 24
Peak memory 207184 kb
Host smart-4302dff3-7bb2-4f0d-8770-edf4ef3cd56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453
12173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1945312173
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.484367073
Short name T656
Test name
Test status
Simulation time 138307511 ps
CPU time 0.88 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:43:55 PM PDT 24
Peak memory 207072 kb
Host smart-96273d59-aeee-4eff-ab3a-ee5122cdd751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48436
7073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.484367073
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2957700412
Short name T2599
Test name
Test status
Simulation time 174252055 ps
CPU time 0.99 seconds
Started Jul 28 07:43:51 PM PDT 24
Finished Jul 28 07:43:52 PM PDT 24
Peak memory 207088 kb
Host smart-ec325248-d152-45e8-babb-93e1a8cf0057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29577
00412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2957700412
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1342907672
Short name T614
Test name
Test status
Simulation time 199027033 ps
CPU time 0.95 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:43:55 PM PDT 24
Peak memory 207132 kb
Host smart-5427bcee-4940-4af3-ba47-6a71cc9ac306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13429
07672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1342907672
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2284693591
Short name T712
Test name
Test status
Simulation time 149472007 ps
CPU time 0.91 seconds
Started Jul 28 07:43:46 PM PDT 24
Finished Jul 28 07:43:47 PM PDT 24
Peak memory 207168 kb
Host smart-9613993c-56b2-48a7-b12b-ccf791da21d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22846
93591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2284693591
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1702878404
Short name T1685
Test name
Test status
Simulation time 222529206 ps
CPU time 1.11 seconds
Started Jul 28 07:43:50 PM PDT 24
Finished Jul 28 07:43:52 PM PDT 24
Peak memory 207120 kb
Host smart-8b563e6e-e88e-4a5c-b9f9-5da1c4cdf95a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1702878404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1702878404
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3800311566
Short name T2709
Test name
Test status
Simulation time 141856102 ps
CPU time 0.83 seconds
Started Jul 28 07:43:38 PM PDT 24
Finished Jul 28 07:43:39 PM PDT 24
Peak memory 207132 kb
Host smart-abe84e4a-1eb8-4bff-adc8-35a25ade72d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38003
11566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3800311566
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3170170729
Short name T1408
Test name
Test status
Simulation time 31276850 ps
CPU time 0.69 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 207120 kb
Host smart-50cff53b-963b-466e-8a97-e902ab845c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31701
70729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3170170729
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.150512429
Short name T1022
Test name
Test status
Simulation time 16761578087 ps
CPU time 43.12 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:44:38 PM PDT 24
Peak memory 215644 kb
Host smart-c3b8bee9-bee0-4195-8e9c-02368b7cc657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15051
2429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.150512429
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.1751196986
Short name T2161
Test name
Test status
Simulation time 201105287 ps
CPU time 0.96 seconds
Started Jul 28 07:43:51 PM PDT 24
Finished Jul 28 07:43:52 PM PDT 24
Peak memory 207136 kb
Host smart-6e526649-60b7-4626-808b-d1c89def90f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17511
96986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1751196986
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.627802629
Short name T2603
Test name
Test status
Simulation time 226522751 ps
CPU time 1 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:43:55 PM PDT 24
Peak memory 207108 kb
Host smart-5b767fbf-f8f9-4b38-9e1a-75f686f43d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62780
2629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.627802629
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.4036411014
Short name T145
Test name
Test status
Simulation time 268821459 ps
CPU time 1.07 seconds
Started Jul 28 07:43:31 PM PDT 24
Finished Jul 28 07:43:32 PM PDT 24
Peak memory 207168 kb
Host smart-64f4ae5a-058d-4746-9ab8-5a85adeda11e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40364
11014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.4036411014
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.4143018814
Short name T691
Test name
Test status
Simulation time 174898520 ps
CPU time 1.01 seconds
Started Jul 28 07:43:32 PM PDT 24
Finished Jul 28 07:43:36 PM PDT 24
Peak memory 207112 kb
Host smart-895a1733-44db-4d86-b79b-26a679c211cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41430
18814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.4143018814
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.4037426506
Short name T2287
Test name
Test status
Simulation time 204073313 ps
CPU time 0.91 seconds
Started Jul 28 07:43:49 PM PDT 24
Finished Jul 28 07:43:50 PM PDT 24
Peak memory 207144 kb
Host smart-0ba1ff7f-9761-4683-a614-d35c9eadf54d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40374
26506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.4037426506
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.3684038097
Short name T1980
Test name
Test status
Simulation time 156804472 ps
CPU time 0.84 seconds
Started Jul 28 07:43:50 PM PDT 24
Finished Jul 28 07:43:51 PM PDT 24
Peak memory 207176 kb
Host smart-7eb61af3-cfe8-44a9-9bef-a69bb464b275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36840
38097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3684038097
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.342151064
Short name T2280
Test name
Test status
Simulation time 198262498 ps
CPU time 0.93 seconds
Started Jul 28 07:43:45 PM PDT 24
Finished Jul 28 07:43:46 PM PDT 24
Peak memory 207136 kb
Host smart-504e9923-2efd-41c7-ad3c-76721d7d7294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34215
1064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.342151064
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2083827515
Short name T448
Test name
Test status
Simulation time 211383053 ps
CPU time 0.97 seconds
Started Jul 28 07:43:32 PM PDT 24
Finished Jul 28 07:43:33 PM PDT 24
Peak memory 207116 kb
Host smart-4d19d8ac-6e13-49a8-a308-d4f63002cf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20838
27515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2083827515
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2048504060
Short name T1264
Test name
Test status
Simulation time 5228064692 ps
CPU time 51.7 seconds
Started Jul 28 07:43:32 PM PDT 24
Finished Jul 28 07:44:24 PM PDT 24
Peak memory 215524 kb
Host smart-2a9fceb6-e257-489e-bfd6-235ea19e41d8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2048504060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2048504060
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3196655749
Short name T440
Test name
Test status
Simulation time 251636626 ps
CPU time 0.93 seconds
Started Jul 28 07:43:53 PM PDT 24
Finished Jul 28 07:43:54 PM PDT 24
Peak memory 207128 kb
Host smart-2d2458f0-a874-4d52-a320-b9240b2902df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31966
55749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3196655749
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3531277155
Short name T2196
Test name
Test status
Simulation time 210936829 ps
CPU time 1.01 seconds
Started Jul 28 07:43:32 PM PDT 24
Finished Jul 28 07:43:33 PM PDT 24
Peak memory 207128 kb
Host smart-631b9add-d726-411d-9a88-9b2d9ea8b322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35312
77155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3531277155
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.2635847312
Short name T1088
Test name
Test status
Simulation time 781502946 ps
CPU time 2.14 seconds
Started Jul 28 07:43:46 PM PDT 24
Finished Jul 28 07:43:48 PM PDT 24
Peak memory 207156 kb
Host smart-6e575c0a-b3b6-4d07-aa9a-3fb6357795f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26358
47312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.2635847312
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.2004492191
Short name T1615
Test name
Test status
Simulation time 3894182845 ps
CPU time 112.11 seconds
Started Jul 28 07:43:49 PM PDT 24
Finished Jul 28 07:45:41 PM PDT 24
Peak memory 215536 kb
Host smart-e5d03420-8f55-40c3-aeab-c702eb40ca2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20044
92191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.2004492191
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.3683295169
Short name T2258
Test name
Test status
Simulation time 342843594 ps
CPU time 4.62 seconds
Started Jul 28 07:43:26 PM PDT 24
Finished Jul 28 07:43:31 PM PDT 24
Peak memory 207372 kb
Host smart-dbeac47e-ed20-4b90-aec8-9f77897c141d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683295169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.3683295169
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.3023425203
Short name T2011
Test name
Test status
Simulation time 45388931 ps
CPU time 0.67 seconds
Started Jul 28 07:43:57 PM PDT 24
Finished Jul 28 07:43:58 PM PDT 24
Peak memory 207184 kb
Host smart-54047393-5fe2-4688-8bec-69c10a4b8e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3023425203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.3023425203
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3089682302
Short name T1567
Test name
Test status
Simulation time 4032695684 ps
CPU time 6.26 seconds
Started Jul 28 07:43:52 PM PDT 24
Finished Jul 28 07:43:58 PM PDT 24
Peak memory 207292 kb
Host smart-22cd93ee-c768-4668-bb71-670ad8bacc5d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089682302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.3089682302
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.4128054047
Short name T1757
Test name
Test status
Simulation time 13426557814 ps
CPU time 15.71 seconds
Started Jul 28 07:43:51 PM PDT 24
Finished Jul 28 07:44:07 PM PDT 24
Peak memory 207412 kb
Host smart-b84bb339-085d-4a76-a6ef-fd191ed587bc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128054047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.4128054047
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.773858076
Short name T2050
Test name
Test status
Simulation time 23407523324 ps
CPU time 27.57 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:44:23 PM PDT 24
Peak memory 207304 kb
Host smart-8a267d56-e42f-4d27-bca3-8539d98fc0b0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773858076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ao
n_wake_resume.773858076
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.73936933
Short name T1238
Test name
Test status
Simulation time 153524331 ps
CPU time 0.86 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:43:55 PM PDT 24
Peak memory 207076 kb
Host smart-8877f40a-bd48-4f1a-8fd0-afcfb72dba87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73936
933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.73936933
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1119466439
Short name T1862
Test name
Test status
Simulation time 173128561 ps
CPU time 0.85 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 207084 kb
Host smart-a4332235-0e98-4634-bd2f-7c04bdc25951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11194
66439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1119466439
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.1707392605
Short name T2540
Test name
Test status
Simulation time 164493992 ps
CPU time 0.93 seconds
Started Jul 28 07:43:57 PM PDT 24
Finished Jul 28 07:43:58 PM PDT 24
Peak memory 207116 kb
Host smart-63ba61f4-ed8d-4565-9a70-0faacece29d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17073
92605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.1707392605
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3394228131
Short name T1717
Test name
Test status
Simulation time 855089086 ps
CPU time 2.28 seconds
Started Jul 28 07:43:56 PM PDT 24
Finished Jul 28 07:43:58 PM PDT 24
Peak memory 207484 kb
Host smart-b1600b67-110e-4323-835d-7cb9f0d70db9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3394228131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3394228131
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.178186266
Short name T852
Test name
Test status
Simulation time 14730164360 ps
CPU time 30.77 seconds
Started Jul 28 07:43:50 PM PDT 24
Finished Jul 28 07:44:21 PM PDT 24
Peak memory 207320 kb
Host smart-bd03e86c-1f06-46bc-9b99-448935f59337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17818
6266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.178186266
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.2655093776
Short name T2569
Test name
Test status
Simulation time 807864382 ps
CPU time 15.22 seconds
Started Jul 28 07:43:49 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 207360 kb
Host smart-88113fc6-f01c-44fb-a370-e5ac9dbcc74f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655093776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.2655093776
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.4119300793
Short name T2475
Test name
Test status
Simulation time 354636455 ps
CPU time 1.38 seconds
Started Jul 28 07:43:57 PM PDT 24
Finished Jul 28 07:43:58 PM PDT 24
Peak memory 207088 kb
Host smart-e2d3d535-1e9c-420f-bd9a-6e8a17f71ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41193
00793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.4119300793
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3967571402
Short name T323
Test name
Test status
Simulation time 195680086 ps
CPU time 0.94 seconds
Started Jul 28 07:43:51 PM PDT 24
Finished Jul 28 07:43:52 PM PDT 24
Peak memory 207120 kb
Host smart-a40b0968-703b-4c16-a5f5-82a8be3da826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39675
71402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3967571402
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.3040630532
Short name T2531
Test name
Test status
Simulation time 47033887 ps
CPU time 0.7 seconds
Started Jul 28 07:43:57 PM PDT 24
Finished Jul 28 07:43:57 PM PDT 24
Peak memory 207080 kb
Host smart-dc9a6f4e-00c2-4d59-a441-b3ff1f04290b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30406
30532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3040630532
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.1928970582
Short name T1865
Test name
Test status
Simulation time 1053734839 ps
CPU time 2.78 seconds
Started Jul 28 07:43:57 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 207356 kb
Host smart-ae914654-fbf5-4731-aace-40985be915ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19289
70582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.1928970582
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.451609220
Short name T2740
Test name
Test status
Simulation time 180351600 ps
CPU time 2.46 seconds
Started Jul 28 07:43:51 PM PDT 24
Finished Jul 28 07:43:54 PM PDT 24
Peak memory 207288 kb
Host smart-6cd720b7-8a43-4ef7-ba83-aedf5e6ca58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45160
9220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.451609220
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.200284147
Short name T2335
Test name
Test status
Simulation time 206010315 ps
CPU time 0.92 seconds
Started Jul 28 07:43:59 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 207048 kb
Host smart-2e258155-1849-477a-856e-eb68e05af1f9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=200284147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.200284147
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.735226975
Short name T996
Test name
Test status
Simulation time 140345148 ps
CPU time 0.78 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 207016 kb
Host smart-2c43af0b-e765-4690-8995-308d5cb40d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73522
6975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.735226975
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.2791142127
Short name T1407
Test name
Test status
Simulation time 207742140 ps
CPU time 0.99 seconds
Started Jul 28 07:43:59 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 207052 kb
Host smart-27119212-8b9e-4bb4-b18a-dbe41e80a041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27911
42127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.2791142127
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.2470070301
Short name T1915
Test name
Test status
Simulation time 9357625194 ps
CPU time 272.31 seconds
Started Jul 28 07:43:48 PM PDT 24
Finished Jul 28 07:48:21 PM PDT 24
Peak memory 215492 kb
Host smart-7c9aebd6-b681-47d3-91ab-890f6f947f9b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2470070301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.2470070301
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.2993849863
Short name T107
Test name
Test status
Simulation time 7836026487 ps
CPU time 56.47 seconds
Started Jul 28 07:43:53 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 207408 kb
Host smart-100b54e7-4cdb-4dc3-99ed-37cb70e38f4f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2993849863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.2993849863
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3907421024
Short name T2008
Test name
Test status
Simulation time 250262389 ps
CPU time 0.97 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 207116 kb
Host smart-9a6b6ac1-b55b-4440-ac56-f4a1b7284830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39074
21024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3907421024
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.1810160046
Short name T1681
Test name
Test status
Simulation time 23284216169 ps
CPU time 36 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:44:31 PM PDT 24
Peak memory 207400 kb
Host smart-10c6498d-0c65-4c31-8692-d000352eb0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18101
60046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1810160046
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.1432489724
Short name T2142
Test name
Test status
Simulation time 3306375143 ps
CPU time 5.44 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:43:59 PM PDT 24
Peak memory 207356 kb
Host smart-f62576f2-f069-4e42-ab97-d3192fbbd183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14324
89724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.1432489724
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.4223124433
Short name T715
Test name
Test status
Simulation time 8894528534 ps
CPU time 87.9 seconds
Started Jul 28 07:43:58 PM PDT 24
Finished Jul 28 07:45:26 PM PDT 24
Peak memory 223748 kb
Host smart-70a2d9a4-463a-49d1-b2a4-5f378a71ede3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42231
24433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.4223124433
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.1038307594
Short name T1967
Test name
Test status
Simulation time 3532095261 ps
CPU time 35.41 seconds
Started Jul 28 07:43:46 PM PDT 24
Finished Jul 28 07:44:22 PM PDT 24
Peak memory 215560 kb
Host smart-90db230d-fde8-4e12-8a9a-73fc3033ff25
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1038307594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.1038307594
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.2865365163
Short name T1098
Test name
Test status
Simulation time 244087309 ps
CPU time 1.08 seconds
Started Jul 28 07:43:56 PM PDT 24
Finished Jul 28 07:43:57 PM PDT 24
Peak memory 207168 kb
Host smart-9057c4e9-2860-4b25-9cf7-8cc6dfbcb1e7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2865365163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.2865365163
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.4155004529
Short name T387
Test name
Test status
Simulation time 191025406 ps
CPU time 0.96 seconds
Started Jul 28 07:43:52 PM PDT 24
Finished Jul 28 07:43:53 PM PDT 24
Peak memory 207156 kb
Host smart-203cc0e1-1a36-47da-85f0-c91750876371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41550
04529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.4155004529
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.190819858
Short name T1690
Test name
Test status
Simulation time 5108686473 ps
CPU time 49.7 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 216900 kb
Host smart-e1b85b6a-f314-4f8a-85e1-f579a57c66c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19081
9858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.190819858
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1567944258
Short name T2575
Test name
Test status
Simulation time 5561322598 ps
CPU time 44.93 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:44:39 PM PDT 24
Peak memory 207288 kb
Host smart-97eb9019-67c0-4761-a795-c6779d4c7eb6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1567944258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1567944258
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.3020282281
Short name T1708
Test name
Test status
Simulation time 150012294 ps
CPU time 0.88 seconds
Started Jul 28 07:43:52 PM PDT 24
Finished Jul 28 07:43:53 PM PDT 24
Peak memory 207140 kb
Host smart-4a74e2f6-1141-4d88-957b-a5c017516cc6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3020282281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.3020282281
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3644870031
Short name T1584
Test name
Test status
Simulation time 138262332 ps
CPU time 0.8 seconds
Started Jul 28 07:43:48 PM PDT 24
Finished Jul 28 07:43:49 PM PDT 24
Peak memory 207104 kb
Host smart-10604fb7-4407-4b29-81da-c98d574256fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36448
70031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3644870031
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.154683641
Short name T113
Test name
Test status
Simulation time 227466651 ps
CPU time 0.96 seconds
Started Jul 28 07:43:51 PM PDT 24
Finished Jul 28 07:43:53 PM PDT 24
Peak memory 207104 kb
Host smart-9b609c46-c801-4edf-8137-4d8500d981f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15468
3641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.154683641
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1506025336
Short name T2235
Test name
Test status
Simulation time 238454328 ps
CPU time 1.02 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 207124 kb
Host smart-ba53bb60-f737-4812-a56d-c10f067a9805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15060
25336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1506025336
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3814564183
Short name T2316
Test name
Test status
Simulation time 158641764 ps
CPU time 0.86 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:01 PM PDT 24
Peak memory 207076 kb
Host smart-0a65d103-c507-4e72-a016-7668cf0d43c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38145
64183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3814564183
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1297822732
Short name T2431
Test name
Test status
Simulation time 180502723 ps
CPU time 0.9 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 207116 kb
Host smart-702098f2-63f3-4e26-8f21-a62ac549ba7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12978
22732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1297822732
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3328682330
Short name T2408
Test name
Test status
Simulation time 172699943 ps
CPU time 0.92 seconds
Started Jul 28 07:43:56 PM PDT 24
Finished Jul 28 07:43:57 PM PDT 24
Peak memory 207056 kb
Host smart-f88a8b47-607e-4b69-a3f2-7bd5362ccd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33286
82330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3328682330
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.937538302
Short name T1614
Test name
Test status
Simulation time 190196878 ps
CPU time 0.93 seconds
Started Jul 28 07:44:01 PM PDT 24
Finished Jul 28 07:44:02 PM PDT 24
Peak memory 207136 kb
Host smart-c5561b28-ceff-4d79-8f95-79a43c051bcf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=937538302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.937538302
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.283002062
Short name T1678
Test name
Test status
Simulation time 174706863 ps
CPU time 0.9 seconds
Started Jul 28 07:43:50 PM PDT 24
Finished Jul 28 07:43:51 PM PDT 24
Peak memory 207008 kb
Host smart-62496393-fa00-47bc-9cc8-26be48c59c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28300
2062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.283002062
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1403481505
Short name T1867
Test name
Test status
Simulation time 36230785 ps
CPU time 0.7 seconds
Started Jul 28 07:43:59 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 207072 kb
Host smart-e0d43d09-5f2c-45de-bc23-445be14ba852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14034
81505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1403481505
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1300862692
Short name T2739
Test name
Test status
Simulation time 22578684214 ps
CPU time 56.11 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 215472 kb
Host smart-3d149115-858e-41a6-aba4-1c78e066a022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13008
62692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1300862692
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3593857022
Short name T2592
Test name
Test status
Simulation time 169994427 ps
CPU time 0.89 seconds
Started Jul 28 07:43:45 PM PDT 24
Finished Jul 28 07:43:46 PM PDT 24
Peak memory 207084 kb
Host smart-13ec9ce6-8ddd-4294-a8fd-c918b7063422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35938
57022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3593857022
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.909626055
Short name T865
Test name
Test status
Simulation time 175958647 ps
CPU time 0.9 seconds
Started Jul 28 07:44:03 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 207112 kb
Host smart-fca842b6-2295-4d29-b5d6-df3ad5da3158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90962
6055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.909626055
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2650778152
Short name T649
Test name
Test status
Simulation time 197465915 ps
CPU time 0.91 seconds
Started Jul 28 07:43:49 PM PDT 24
Finished Jul 28 07:43:50 PM PDT 24
Peak memory 206552 kb
Host smart-241b20b5-1238-4656-9d08-bad1df85a04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26507
78152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2650778152
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.2011964259
Short name T1267
Test name
Test status
Simulation time 179586728 ps
CPU time 0.91 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:43:55 PM PDT 24
Peak memory 207060 kb
Host smart-11fdeed9-92df-4668-a135-5b7e65a66c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20119
64259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.2011964259
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2090429882
Short name T1095
Test name
Test status
Simulation time 188872832 ps
CPU time 0.93 seconds
Started Jul 28 07:44:01 PM PDT 24
Finished Jul 28 07:44:02 PM PDT 24
Peak memory 207136 kb
Host smart-0b068f8a-93e4-47e7-a710-5882e39005e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20904
29882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2090429882
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2087471221
Short name T2623
Test name
Test status
Simulation time 170103577 ps
CPU time 0.97 seconds
Started Jul 28 07:44:04 PM PDT 24
Finished Jul 28 07:44:05 PM PDT 24
Peak memory 207088 kb
Host smart-f6ced714-d11e-4468-8cd3-4ceafd8593df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20874
71221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2087471221
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.591516054
Short name T1325
Test name
Test status
Simulation time 148563780 ps
CPU time 0.85 seconds
Started Jul 28 07:44:01 PM PDT 24
Finished Jul 28 07:44:02 PM PDT 24
Peak memory 207128 kb
Host smart-b13db310-6e03-4307-b284-99eb0ea00f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59151
6054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.591516054
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3589977094
Short name T1896
Test name
Test status
Simulation time 212137264 ps
CPU time 1 seconds
Started Jul 28 07:43:58 PM PDT 24
Finished Jul 28 07:43:59 PM PDT 24
Peak memory 207128 kb
Host smart-d0de0705-05ea-417f-a236-d9b3d433a459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35899
77094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3589977094
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.4656426
Short name T2134
Test name
Test status
Simulation time 4074245247 ps
CPU time 40.73 seconds
Started Jul 28 07:43:57 PM PDT 24
Finished Jul 28 07:44:38 PM PDT 24
Peak memory 215592 kb
Host smart-f2e804af-1b51-49f0-923f-9f1915b5a284
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4656426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.4656426
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.41212179
Short name T693
Test name
Test status
Simulation time 167817201 ps
CPU time 0.85 seconds
Started Jul 28 07:43:51 PM PDT 24
Finished Jul 28 07:43:52 PM PDT 24
Peak memory 207076 kb
Host smart-26502024-b14c-40e4-bc35-793c864822a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41212
179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.41212179
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.4249347891
Short name T2051
Test name
Test status
Simulation time 170415666 ps
CPU time 0.86 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 207128 kb
Host smart-1a2b5a62-73e2-4502-8fb2-c270a5ff62b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42493
47891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.4249347891
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.1936044803
Short name T2389
Test name
Test status
Simulation time 397854253 ps
CPU time 1.36 seconds
Started Jul 28 07:43:56 PM PDT 24
Finished Jul 28 07:43:58 PM PDT 24
Peak memory 207016 kb
Host smart-6547445b-398b-436c-8161-1d6297d02bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19360
44803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.1936044803
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3482309497
Short name T1361
Test name
Test status
Simulation time 5931495531 ps
CPU time 166.62 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:46:42 PM PDT 24
Peak memory 215600 kb
Host smart-a0dbf4b6-cb87-4e4f-8e66-6f022497b77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34823
09497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3482309497
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.2866072899
Short name T2298
Test name
Test status
Simulation time 2306723268 ps
CPU time 14.29 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207404 kb
Host smart-548c56a9-5c07-4945-9421-d091f26af13d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866072899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_hos
t_handshake.2866072899
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.1554506509
Short name T676
Test name
Test status
Simulation time 38614214 ps
CPU time 0.68 seconds
Started Jul 28 07:43:50 PM PDT 24
Finished Jul 28 07:43:51 PM PDT 24
Peak memory 207144 kb
Host smart-ecfb1a12-5c5b-4271-878c-10eb6de0895d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1554506509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.1554506509
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2947823987
Short name T41
Test name
Test status
Simulation time 4523155408 ps
CPU time 7.59 seconds
Started Jul 28 07:43:52 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 207328 kb
Host smart-bb0ee9e4-c68b-4ead-9054-941b754459a4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947823987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.2947823987
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.3493019864
Short name T2386
Test name
Test status
Simulation time 13381115680 ps
CPU time 16.6 seconds
Started Jul 28 07:43:56 PM PDT 24
Finished Jul 28 07:44:13 PM PDT 24
Peak memory 207364 kb
Host smart-fca576bd-dabb-48b1-8b93-fbd9455ca76c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493019864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.3493019864
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.537489019
Short name T1587
Test name
Test status
Simulation time 23290213537 ps
CPU time 27.22 seconds
Started Jul 28 07:43:50 PM PDT 24
Finished Jul 28 07:44:17 PM PDT 24
Peak memory 207340 kb
Host smart-2ed225b9-600f-4ea3-8105-a4ef89196aed
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537489019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ao
n_wake_resume.537489019
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1833656574
Short name T2242
Test name
Test status
Simulation time 175084497 ps
CPU time 0.89 seconds
Started Jul 28 07:44:02 PM PDT 24
Finished Jul 28 07:44:03 PM PDT 24
Peak memory 207156 kb
Host smart-bf64ff1d-9e52-4837-b110-7b1fd7a5a63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18336
56574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1833656574
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1584412320
Short name T726
Test name
Test status
Simulation time 139747129 ps
CPU time 0.8 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 207108 kb
Host smart-28a5f096-7896-424e-ab62-0edaa2961f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15844
12320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1584412320
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2673190351
Short name T2037
Test name
Test status
Simulation time 231206657 ps
CPU time 1.16 seconds
Started Jul 28 07:43:58 PM PDT 24
Finished Jul 28 07:43:59 PM PDT 24
Peak memory 207136 kb
Host smart-9d0d7be1-1169-4d7c-8a8d-9f258dc07615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26731
90351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2673190351
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.2706204565
Short name T1023
Test name
Test status
Simulation time 605218313 ps
CPU time 1.72 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 207088 kb
Host smart-eef73d3e-85f3-4b4c-bedb-b720a3dec90a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2706204565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.2706204565
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3072447478
Short name T844
Test name
Test status
Simulation time 13049026606 ps
CPU time 26.01 seconds
Started Jul 28 07:43:58 PM PDT 24
Finished Jul 28 07:44:25 PM PDT 24
Peak memory 207372 kb
Host smart-dcd3163d-bdcc-4daa-8552-5d41660e94a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30724
47478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3072447478
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.3951847001
Short name T1228
Test name
Test status
Simulation time 3906061795 ps
CPU time 34.23 seconds
Started Jul 28 07:43:47 PM PDT 24
Finished Jul 28 07:44:21 PM PDT 24
Peak memory 207264 kb
Host smart-4c591ff5-e4fc-4cc7-8c9f-2dccca61f767
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951847001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.3951847001
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2809611891
Short name T1994
Test name
Test status
Simulation time 426966805 ps
CPU time 1.4 seconds
Started Jul 28 07:43:49 PM PDT 24
Finished Jul 28 07:43:51 PM PDT 24
Peak memory 206572 kb
Host smart-90e6e9dd-7db1-4841-a830-df7c8bc155e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28096
11891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2809611891
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3694268038
Short name T1638
Test name
Test status
Simulation time 146782948 ps
CPU time 0.92 seconds
Started Jul 28 07:44:02 PM PDT 24
Finished Jul 28 07:44:03 PM PDT 24
Peak memory 207096 kb
Host smart-0badcc3e-2e9d-4232-a637-c45ac118650f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36942
68038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3694268038
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.4202157992
Short name T2179
Test name
Test status
Simulation time 31726267 ps
CPU time 0.74 seconds
Started Jul 28 07:44:01 PM PDT 24
Finished Jul 28 07:44:01 PM PDT 24
Peak memory 207044 kb
Host smart-888f9a13-b413-4251-b2ae-d7df80e5464c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42021
57992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.4202157992
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2692615543
Short name T640
Test name
Test status
Simulation time 712744980 ps
CPU time 2.01 seconds
Started Jul 28 07:43:48 PM PDT 24
Finished Jul 28 07:43:50 PM PDT 24
Peak memory 207444 kb
Host smart-f066362a-b81d-46c8-8e96-a96b50b5f4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26926
15543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2692615543
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3344751710
Short name T501
Test name
Test status
Simulation time 353521188 ps
CPU time 2.74 seconds
Started Jul 28 07:43:59 PM PDT 24
Finished Jul 28 07:44:02 PM PDT 24
Peak memory 207312 kb
Host smart-9b6ecb19-4805-40a7-8373-bca2bf9ad9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33447
51710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3344751710
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.789591017
Short name T2771
Test name
Test status
Simulation time 149207077 ps
CPU time 0.83 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207048 kb
Host smart-21b71c8e-4776-4e0d-8dfb-2d8c9914d13f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=789591017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.789591017
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1176000956
Short name T1369
Test name
Test status
Simulation time 146065498 ps
CPU time 0.84 seconds
Started Jul 28 07:43:56 PM PDT 24
Finished Jul 28 07:43:57 PM PDT 24
Peak memory 207172 kb
Host smart-170888c3-9176-4de4-a8a4-1bebe42ae00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11760
00956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1176000956
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3336381403
Short name T2092
Test name
Test status
Simulation time 207900212 ps
CPU time 1.02 seconds
Started Jul 28 07:44:06 PM PDT 24
Finished Jul 28 07:44:07 PM PDT 24
Peak memory 207116 kb
Host smart-49a59a7d-ba83-497f-b925-a5d16cf878b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33363
81403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3336381403
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.318658068
Short name T1829
Test name
Test status
Simulation time 6972945926 ps
CPU time 70.93 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:45:07 PM PDT 24
Peak memory 217092 kb
Host smart-ce7bda52-7266-4a7e-b139-39104c678baa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=318658068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.318658068
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.1935423764
Short name T722
Test name
Test status
Simulation time 12097780747 ps
CPU time 163.16 seconds
Started Jul 28 07:43:52 PM PDT 24
Finished Jul 28 07:46:35 PM PDT 24
Peak memory 207404 kb
Host smart-4efaeccf-2ff3-4fbf-8f28-8172053fa93e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1935423764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.1935423764
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.2556047757
Short name T82
Test name
Test status
Simulation time 185995434 ps
CPU time 0.99 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207116 kb
Host smart-9e04c58b-f284-43e5-a77b-fe0a91445661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25560
47757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.2556047757
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.2823062429
Short name T1255
Test name
Test status
Simulation time 23341600284 ps
CPU time 27.61 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:34 PM PDT 24
Peak memory 207388 kb
Host smart-a47c6515-7cad-47ac-ac11-b8be4372e6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28230
62429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.2823062429
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3333705841
Short name T1185
Test name
Test status
Simulation time 3297152332 ps
CPU time 6.16 seconds
Started Jul 28 07:43:57 PM PDT 24
Finished Jul 28 07:44:03 PM PDT 24
Peak memory 207372 kb
Host smart-eb8e5565-52ad-4c6f-a45b-b6a2aee3f3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33337
05841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3333705841
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.70131580
Short name T1782
Test name
Test status
Simulation time 5584695619 ps
CPU time 56.27 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 217456 kb
Host smart-d61b9f40-61db-40bc-93f4-727505bd0b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70131
580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.70131580
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3424774026
Short name T1589
Test name
Test status
Simulation time 3415268189 ps
CPU time 33.98 seconds
Started Jul 28 07:44:06 PM PDT 24
Finished Jul 28 07:44:40 PM PDT 24
Peak memory 216852 kb
Host smart-e4fd85ea-656d-4e37-97a3-466012c1126b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3424774026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3424774026
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1226007120
Short name T2399
Test name
Test status
Simulation time 234273358 ps
CPU time 1.04 seconds
Started Jul 28 07:44:10 PM PDT 24
Finished Jul 28 07:44:12 PM PDT 24
Peak memory 207140 kb
Host smart-966d3cbd-c46c-4cf9-96d0-fb6ce05427b0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1226007120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1226007120
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3065106151
Short name T369
Test name
Test status
Simulation time 235713987 ps
CPU time 1.02 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:43:55 PM PDT 24
Peak memory 207064 kb
Host smart-f08b14e3-5a85-4e1e-b977-41bcff5586b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30651
06151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3065106151
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1183057462
Short name T1337
Test name
Test status
Simulation time 4752337412 ps
CPU time 34.97 seconds
Started Jul 28 07:44:11 PM PDT 24
Finished Jul 28 07:44:46 PM PDT 24
Peak memory 215572 kb
Host smart-dd6b6740-2ef0-499a-bc4e-37792f5a1cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11830
57462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1183057462
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2676374910
Short name T832
Test name
Test status
Simulation time 3021401338 ps
CPU time 29.68 seconds
Started Jul 28 07:44:02 PM PDT 24
Finished Jul 28 07:44:32 PM PDT 24
Peak memory 215748 kb
Host smart-38a8f65c-c32f-4752-8d56-f50c20799555
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2676374910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2676374910
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.888653370
Short name T2049
Test name
Test status
Simulation time 148699178 ps
CPU time 0.86 seconds
Started Jul 28 07:44:05 PM PDT 24
Finished Jul 28 07:44:06 PM PDT 24
Peak memory 207112 kb
Host smart-abd325f2-cc61-443e-bafd-99277db1173d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=888653370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.888653370
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3370710372
Short name T509
Test name
Test status
Simulation time 144352359 ps
CPU time 0.86 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207140 kb
Host smart-d557b5ea-56f0-4e13-9ddd-c200f4675d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33707
10372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3370710372
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3685476234
Short name T1913
Test name
Test status
Simulation time 205056865 ps
CPU time 0.92 seconds
Started Jul 28 07:44:05 PM PDT 24
Finished Jul 28 07:44:06 PM PDT 24
Peak memory 207044 kb
Host smart-9095f2f6-83a5-41b0-8115-7936b6a99c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36854
76234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3685476234
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.3943845828
Short name T1742
Test name
Test status
Simulation time 229452017 ps
CPU time 0.96 seconds
Started Jul 28 07:44:04 PM PDT 24
Finished Jul 28 07:44:05 PM PDT 24
Peak memory 207264 kb
Host smart-f3d4578c-b8c1-4c84-a036-4c5ed193d6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39438
45828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3943845828
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2260494935
Short name T1531
Test name
Test status
Simulation time 150575344 ps
CPU time 0.84 seconds
Started Jul 28 07:44:04 PM PDT 24
Finished Jul 28 07:44:05 PM PDT 24
Peak memory 207136 kb
Host smart-818f760a-b8b1-4185-84db-b101b3d9b915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22604
94935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2260494935
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1463761174
Short name T1233
Test name
Test status
Simulation time 201121065 ps
CPU time 0.93 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:08 PM PDT 24
Peak memory 207120 kb
Host smart-9f0c9b69-0b58-428d-a042-077786a4b61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14637
61174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1463761174
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1077186363
Short name T1141
Test name
Test status
Simulation time 154506631 ps
CPU time 0.89 seconds
Started Jul 28 07:43:51 PM PDT 24
Finished Jul 28 07:43:52 PM PDT 24
Peak memory 207156 kb
Host smart-a63eb9be-1224-4e27-9c20-9139318f71b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10771
86363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1077186363
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2900342881
Short name T2583
Test name
Test status
Simulation time 220683081 ps
CPU time 1.01 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:02 PM PDT 24
Peak memory 207300 kb
Host smart-32885b94-43d2-44fb-9af6-48c1f3aef440
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2900342881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2900342881
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.607632207
Short name T689
Test name
Test status
Simulation time 139507805 ps
CPU time 0.83 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:01 PM PDT 24
Peak memory 207036 kb
Host smart-77d693d1-c2f0-42d0-aacd-a8e8653c93e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60763
2207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.607632207
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2792349394
Short name T31
Test name
Test status
Simulation time 77462127 ps
CPU time 0.76 seconds
Started Jul 28 07:44:01 PM PDT 24
Finished Jul 28 07:44:02 PM PDT 24
Peak memory 207064 kb
Host smart-f37d16ca-14cd-49fc-9dcb-ec58a719d1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27923
49394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2792349394
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.3211687534
Short name T2137
Test name
Test status
Simulation time 15331383139 ps
CPU time 42.24 seconds
Started Jul 28 07:44:04 PM PDT 24
Finished Jul 28 07:44:46 PM PDT 24
Peak memory 215616 kb
Host smart-69a29bbb-b2c8-4d53-976d-047f7a3b459d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32116
87534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.3211687534
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3134479493
Short name T2576
Test name
Test status
Simulation time 173098429 ps
CPU time 0.88 seconds
Started Jul 28 07:43:49 PM PDT 24
Finished Jul 28 07:43:50 PM PDT 24
Peak memory 207152 kb
Host smart-81a3e243-4b18-47a6-b780-c90f111b77c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31344
79493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3134479493
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.4196296507
Short name T743
Test name
Test status
Simulation time 224545165 ps
CPU time 0.96 seconds
Started Jul 28 07:43:51 PM PDT 24
Finished Jul 28 07:43:52 PM PDT 24
Peak memory 207124 kb
Host smart-e491b954-2bd4-44b3-a57c-7feab521d8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41962
96507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.4196296507
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2396957185
Short name T2005
Test name
Test status
Simulation time 205056285 ps
CPU time 0.94 seconds
Started Jul 28 07:44:04 PM PDT 24
Finished Jul 28 07:44:05 PM PDT 24
Peak memory 207128 kb
Host smart-71e408c9-498a-4291-bb8a-888bcfe39483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23969
57185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2396957185
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.384373471
Short name T1773
Test name
Test status
Simulation time 197716585 ps
CPU time 0.96 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:08 PM PDT 24
Peak memory 207128 kb
Host smart-50896665-2966-40fd-8ab4-3b9a30e6e25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38437
3471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.384373471
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1106289869
Short name T841
Test name
Test status
Simulation time 149730053 ps
CPU time 0.85 seconds
Started Jul 28 07:43:51 PM PDT 24
Finished Jul 28 07:43:52 PM PDT 24
Peak memory 207136 kb
Host smart-bb7840d0-25b8-4228-8fd7-708f79fd5f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11062
89869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1106289869
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1360171365
Short name T2425
Test name
Test status
Simulation time 147899860 ps
CPU time 0.82 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:10 PM PDT 24
Peak memory 207128 kb
Host smart-abcebea8-a157-426c-b19d-78350d595e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13601
71365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1360171365
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2760026116
Short name T1907
Test name
Test status
Simulation time 184626646 ps
CPU time 0.9 seconds
Started Jul 28 07:43:59 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 207136 kb
Host smart-11dd76af-831d-41bf-b468-cc5e7c250f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27600
26116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2760026116
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.4188479298
Short name T1721
Test name
Test status
Simulation time 201450156 ps
CPU time 1 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:43:55 PM PDT 24
Peak memory 207024 kb
Host smart-80b21f6d-18b1-4db7-8851-e80320da2fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41884
79298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.4188479298
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.931494028
Short name T1790
Test name
Test status
Simulation time 6296192233 ps
CPU time 66.4 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:45:14 PM PDT 24
Peak memory 216980 kb
Host smart-a8d69202-e6e3-45c7-82d9-c4336211dbc9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=931494028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.931494028
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2215409436
Short name T1545
Test name
Test status
Simulation time 168067663 ps
CPU time 0.87 seconds
Started Jul 28 07:43:56 PM PDT 24
Finished Jul 28 07:43:57 PM PDT 24
Peak memory 207164 kb
Host smart-78074d2d-ec84-4624-bcf1-cdc85db54d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22154
09436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2215409436
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2940561423
Short name T1645
Test name
Test status
Simulation time 203522703 ps
CPU time 0.97 seconds
Started Jul 28 07:44:03 PM PDT 24
Finished Jul 28 07:44:05 PM PDT 24
Peak memory 207160 kb
Host smart-1b4f8cdb-75e3-49ec-9869-b63914df4064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29405
61423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2940561423
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.1705153026
Short name T1604
Test name
Test status
Simulation time 557064698 ps
CPU time 1.56 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:43:57 PM PDT 24
Peak memory 207172 kb
Host smart-0aed05e8-d74e-490f-901d-9f3d48ee0ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17051
53026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.1705153026
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.2686381193
Short name T2202
Test name
Test status
Simulation time 5159040138 ps
CPU time 39.41 seconds
Started Jul 28 07:44:01 PM PDT 24
Finished Jul 28 07:44:40 PM PDT 24
Peak memory 216752 kb
Host smart-306f40ec-7b37-4453-b229-58fef11fb9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26863
81193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2686381193
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.3950021880
Short name T2177
Test name
Test status
Simulation time 5745799398 ps
CPU time 36.51 seconds
Started Jul 28 07:43:54 PM PDT 24
Finished Jul 28 07:44:31 PM PDT 24
Peak memory 207400 kb
Host smart-7040d6b8-ec21-4674-91ce-c9b4f7aa0722
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950021880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.3950021880
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.2325042564
Short name T728
Test name
Test status
Simulation time 39847452 ps
CPU time 0.7 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:08 PM PDT 24
Peak memory 207204 kb
Host smart-d948cffc-7c83-403f-ac52-107ee8df40e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2325042564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.2325042564
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.3259621822
Short name T1120
Test name
Test status
Simulation time 4157484940 ps
CPU time 6.18 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:14 PM PDT 24
Peak memory 207424 kb
Host smart-cc4d654f-a384-44d2-bb94-793529f99c7e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259621822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.3259621822
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1425955385
Short name T1059
Test name
Test status
Simulation time 13319228446 ps
CPU time 16.79 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:44:12 PM PDT 24
Peak memory 207348 kb
Host smart-69444d86-a904-4372-a4c2-75b9dbdb5e17
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425955385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1425955385
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.407513064
Short name T2863
Test name
Test status
Simulation time 23391057993 ps
CPU time 29.86 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:44:39 PM PDT 24
Peak memory 207288 kb
Host smart-bfd8f06b-0388-4e05-af5d-54c67a9d9a48
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407513064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_ao
n_wake_resume.407513064
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3221794455
Short name T2014
Test name
Test status
Simulation time 148250702 ps
CPU time 0.88 seconds
Started Jul 28 07:44:03 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 207296 kb
Host smart-bff8762e-2a7f-4e34-ae38-2c9eb1f7df99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32217
94455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3221794455
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.1907633109
Short name T1065
Test name
Test status
Simulation time 149413399 ps
CPU time 0.84 seconds
Started Jul 28 07:43:56 PM PDT 24
Finished Jul 28 07:43:57 PM PDT 24
Peak memory 207120 kb
Host smart-d3d4ebd9-f527-4212-8afe-390bbf752d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19076
33109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.1907633109
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.3340529790
Short name T1400
Test name
Test status
Simulation time 400852727 ps
CPU time 1.41 seconds
Started Jul 28 07:44:03 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 207304 kb
Host smart-f669cf89-7b44-4575-b851-eebd6336d3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33405
29790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.3340529790
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_device_address.3187700680
Short name T1639
Test name
Test status
Simulation time 20732775519 ps
CPU time 52.74 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:44:48 PM PDT 24
Peak memory 207392 kb
Host smart-70b691a3-f09b-4e56-b3b5-472f2ff3290b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31877
00680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.3187700680
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.1158064330
Short name T2580
Test name
Test status
Simulation time 2198162092 ps
CPU time 14.76 seconds
Started Jul 28 07:44:04 PM PDT 24
Finished Jul 28 07:44:19 PM PDT 24
Peak memory 207420 kb
Host smart-8d120e78-6f24-4ea0-a381-0b98059bc284
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158064330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.1158064330
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1099203385
Short name T1249
Test name
Test status
Simulation time 446449957 ps
CPU time 1.59 seconds
Started Jul 28 07:43:49 PM PDT 24
Finished Jul 28 07:43:50 PM PDT 24
Peak memory 207128 kb
Host smart-66ec2b1b-de42-40cc-a1aa-0267c783a436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10992
03385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1099203385
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3773689980
Short name T1470
Test name
Test status
Simulation time 148256056 ps
CPU time 0.79 seconds
Started Jul 28 07:43:55 PM PDT 24
Finished Jul 28 07:43:56 PM PDT 24
Peak memory 207096 kb
Host smart-e71f6b5a-995e-4cfc-bb90-51f844232024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37736
89980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3773689980
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.2412811094
Short name T2261
Test name
Test status
Simulation time 29474557 ps
CPU time 0.71 seconds
Started Jul 28 07:43:53 PM PDT 24
Finished Jul 28 07:43:54 PM PDT 24
Peak memory 207032 kb
Host smart-1067459c-3841-4e03-b3f4-eec8141b52f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24128
11094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2412811094
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.757052808
Short name T2048
Test name
Test status
Simulation time 838718289 ps
CPU time 2.36 seconds
Started Jul 28 07:44:03 PM PDT 24
Finished Jul 28 07:44:06 PM PDT 24
Peak memory 207344 kb
Host smart-04a15474-cfff-48a5-92f2-142d3fe803d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75705
2808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.757052808
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.846109763
Short name T2360
Test name
Test status
Simulation time 209052367 ps
CPU time 2.33 seconds
Started Jul 28 07:43:57 PM PDT 24
Finished Jul 28 07:43:59 PM PDT 24
Peak memory 207308 kb
Host smart-0664b80c-55aa-44b8-acaa-5d1cb381ee29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84610
9763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.846109763
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1665089486
Short name T207
Test name
Test status
Simulation time 194410182 ps
CPU time 0.9 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:10 PM PDT 24
Peak memory 207052 kb
Host smart-6f8efee6-e7da-40e6-a5bc-6bfae06457ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1665089486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1665089486
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3785221408
Short name T399
Test name
Test status
Simulation time 140583360 ps
CPU time 0.82 seconds
Started Jul 28 07:43:57 PM PDT 24
Finished Jul 28 07:43:58 PM PDT 24
Peak memory 207172 kb
Host smart-01cfa6d1-c63e-48f0-8b08-49b38c8d431f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37852
21408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3785221408
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.1673494816
Short name T1133
Test name
Test status
Simulation time 193429894 ps
CPU time 0.94 seconds
Started Jul 28 07:44:06 PM PDT 24
Finished Jul 28 07:44:07 PM PDT 24
Peak memory 207056 kb
Host smart-36aa7b34-c47e-40f0-b482-d02b812eb8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16734
94816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.1673494816
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.3611228884
Short name T87
Test name
Test status
Simulation time 8285839445 ps
CPU time 239.83 seconds
Started Jul 28 07:43:58 PM PDT 24
Finished Jul 28 07:47:58 PM PDT 24
Peak memory 215580 kb
Host smart-75f7300b-945a-4372-af9e-d219f1ae2ca6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3611228884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.3611228884
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.2277249015
Short name T1413
Test name
Test status
Simulation time 12634686741 ps
CPU time 81.31 seconds
Started Jul 28 07:44:11 PM PDT 24
Finished Jul 28 07:45:33 PM PDT 24
Peak memory 207296 kb
Host smart-1734ae6c-5d4b-40ec-b8b9-2d7ed0f63551
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2277249015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.2277249015
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.3514146161
Short name T767
Test name
Test status
Simulation time 192465770 ps
CPU time 0.95 seconds
Started Jul 28 07:44:03 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 207096 kb
Host smart-1e4e2ca6-dc51-4321-b0a7-fbcb37370da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35141
46161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.3514146161
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.1391650824
Short name T1152
Test name
Test status
Simulation time 23293361797 ps
CPU time 29.36 seconds
Started Jul 28 07:43:58 PM PDT 24
Finished Jul 28 07:44:28 PM PDT 24
Peak memory 207352 kb
Host smart-ca916f1b-aa50-40a2-ab7e-3342198d226a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13916
50824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.1391650824
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1602458973
Short name T147
Test name
Test status
Simulation time 3306052556 ps
CPU time 5.15 seconds
Started Jul 28 07:44:03 PM PDT 24
Finished Jul 28 07:44:08 PM PDT 24
Peak memory 207368 kb
Host smart-4e2b0422-96ac-497b-aa66-bca176704117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16024
58973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1602458973
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.3299833918
Short name T628
Test name
Test status
Simulation time 4960598023 ps
CPU time 36.3 seconds
Started Jul 28 07:44:11 PM PDT 24
Finished Jul 28 07:44:47 PM PDT 24
Peak memory 217016 kb
Host smart-08f2117a-b4da-4895-90e1-d78db8dfec08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32998
33918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.3299833918
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.2226371773
Short name T1178
Test name
Test status
Simulation time 5171325840 ps
CPU time 146.19 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:46:26 PM PDT 24
Peak memory 215520 kb
Host smart-81e5cdbd-ffa0-45e5-8356-2895b70bfa63
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2226371773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2226371773
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2373706025
Short name T1189
Test name
Test status
Simulation time 241261844 ps
CPU time 1.03 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:01 PM PDT 24
Peak memory 207092 kb
Host smart-5d1393de-e5a0-44a6-89b2-b8387c43fe80
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2373706025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2373706025
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2004747414
Short name T1072
Test name
Test status
Simulation time 211916278 ps
CPU time 0.96 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:08 PM PDT 24
Peak memory 207168 kb
Host smart-947aca06-4ae9-4849-a531-8266d7c2bcdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20047
47414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2004747414
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.5763585
Short name T846
Test name
Test status
Simulation time 5549264824 ps
CPU time 157.53 seconds
Started Jul 28 07:43:59 PM PDT 24
Finished Jul 28 07:46:37 PM PDT 24
Peak memory 215548 kb
Host smart-82d19606-de7b-459f-8026-452abede8ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57635
85 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.5763585
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1800627507
Short name T1668
Test name
Test status
Simulation time 6158918454 ps
CPU time 47.38 seconds
Started Jul 28 07:43:56 PM PDT 24
Finished Jul 28 07:44:43 PM PDT 24
Peak memory 207392 kb
Host smart-3ca94413-a05f-4bb0-b5aa-08ea4c141581
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1800627507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1800627507
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2459181089
Short name T24
Test name
Test status
Simulation time 154039685 ps
CPU time 0.86 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:44:10 PM PDT 24
Peak memory 207076 kb
Host smart-7957328c-c24e-482c-9a43-869733db0eef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2459181089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2459181089
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1407539626
Short name T2492
Test name
Test status
Simulation time 146410470 ps
CPU time 0.83 seconds
Started Jul 28 07:44:06 PM PDT 24
Finished Jul 28 07:44:07 PM PDT 24
Peak memory 207132 kb
Host smart-0e7cd306-d7d1-4db2-b08d-479ffe584f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14075
39626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1407539626
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2970549574
Short name T134
Test name
Test status
Simulation time 260806497 ps
CPU time 0.98 seconds
Started Jul 28 07:43:59 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 207088 kb
Host smart-5516e104-7957-49cc-8c54-60af73c36708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29705
49574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2970549574
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.4022330808
Short name T2026
Test name
Test status
Simulation time 175650548 ps
CPU time 0.94 seconds
Started Jul 28 07:44:02 PM PDT 24
Finished Jul 28 07:44:03 PM PDT 24
Peak memory 207288 kb
Host smart-0484b427-d82c-4473-9bbe-9d4603977bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40223
30808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.4022330808
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.237865663
Short name T1498
Test name
Test status
Simulation time 152412075 ps
CPU time 0.86 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:01 PM PDT 24
Peak memory 207028 kb
Host smart-89d42e30-30bb-4fd5-9029-6283cc85ca6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23786
5663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.237865663
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1600957856
Short name T1259
Test name
Test status
Simulation time 187540459 ps
CPU time 0.97 seconds
Started Jul 28 07:44:03 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 207296 kb
Host smart-361eca41-4deb-4201-b2af-1d79f4cca35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16009
57856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1600957856
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3370510879
Short name T2778
Test name
Test status
Simulation time 152962383 ps
CPU time 0.83 seconds
Started Jul 28 07:44:05 PM PDT 24
Finished Jul 28 07:44:06 PM PDT 24
Peak memory 207148 kb
Host smart-c71ae316-1848-4488-9554-e2fa6257ad0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33705
10879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3370510879
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.965029574
Short name T2767
Test name
Test status
Simulation time 256958881 ps
CPU time 1.18 seconds
Started Jul 28 07:44:05 PM PDT 24
Finished Jul 28 07:44:06 PM PDT 24
Peak memory 207076 kb
Host smart-097becb2-4b6c-49e6-b365-31b793a68e84
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=965029574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.965029574
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3365315864
Short name T2112
Test name
Test status
Simulation time 140698592 ps
CPU time 0.82 seconds
Started Jul 28 07:44:04 PM PDT 24
Finished Jul 28 07:44:05 PM PDT 24
Peak memory 207132 kb
Host smart-79c840c6-865b-4af2-b478-6e916a2927fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33653
15864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3365315864
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2785488205
Short name T1010
Test name
Test status
Simulation time 53752760 ps
CPU time 0.74 seconds
Started Jul 28 07:43:59 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 207152 kb
Host smart-2ef18f14-4068-4d94-b8c0-78115d939695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27854
88205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2785488205
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1931850061
Short name T2613
Test name
Test status
Simulation time 16759703117 ps
CPU time 41.09 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 215564 kb
Host smart-582b8572-0c42-42e3-b1a6-80bd6438ad77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19318
50061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1931850061
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2366398429
Short name T1443
Test name
Test status
Simulation time 194142214 ps
CPU time 1.01 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:44:11 PM PDT 24
Peak memory 207052 kb
Host smart-12910a9f-7455-437c-832c-6a9172fe4ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23663
98429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2366398429
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1598523724
Short name T327
Test name
Test status
Simulation time 203773528 ps
CPU time 0.9 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:10 PM PDT 24
Peak memory 207108 kb
Host smart-be04a11a-0347-45cc-a31b-3638a6660e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15985
23724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1598523724
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.1479483082
Short name T1563
Test name
Test status
Simulation time 237717326 ps
CPU time 1.02 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:06 PM PDT 24
Peak memory 207164 kb
Host smart-e941725c-6e81-4095-9d0d-046fda841808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14794
83082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.1479483082
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.491085210
Short name T103
Test name
Test status
Simulation time 168435024 ps
CPU time 0.9 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:01 PM PDT 24
Peak memory 207140 kb
Host smart-beef7f74-c72f-4812-a2fc-95b75263cc68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49108
5210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.491085210
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3620880223
Short name T2127
Test name
Test status
Simulation time 141357227 ps
CPU time 0.8 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:08 PM PDT 24
Peak memory 207096 kb
Host smart-38e224d0-0d51-4b7d-b439-d6a27a079f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36208
80223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3620880223
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.4289546762
Short name T1390
Test name
Test status
Simulation time 153202011 ps
CPU time 0.85 seconds
Started Jul 28 07:44:03 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 207036 kb
Host smart-d675f645-f3f6-4616-8daf-780e41471a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42895
46762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.4289546762
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2385642388
Short name T1895
Test name
Test status
Simulation time 153380489 ps
CPU time 0.85 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207148 kb
Host smart-7bc070a5-1ae9-425b-857d-80f4d547e49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23856
42388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2385642388
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.4283399451
Short name T2312
Test name
Test status
Simulation time 194416784 ps
CPU time 0.97 seconds
Started Jul 28 07:43:58 PM PDT 24
Finished Jul 28 07:43:59 PM PDT 24
Peak memory 207128 kb
Host smart-cfae53c0-7d96-414d-951f-3dd11e9d0139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42833
99451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.4283399451
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.3908561245
Short name T1999
Test name
Test status
Simulation time 4424943194 ps
CPU time 42.66 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:44:52 PM PDT 24
Peak memory 217064 kb
Host smart-0dc51568-1aa3-4467-a198-70afbbe9f265
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3908561245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.3908561245
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2712247421
Short name T2565
Test name
Test status
Simulation time 222210784 ps
CPU time 0.94 seconds
Started Jul 28 07:44:05 PM PDT 24
Finished Jul 28 07:44:06 PM PDT 24
Peak memory 206992 kb
Host smart-7e6d5f3e-9232-4d65-9395-cf8ea2d0ea9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27122
47421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2712247421
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3376279454
Short name T2828
Test name
Test status
Simulation time 168644444 ps
CPU time 0.9 seconds
Started Jul 28 07:44:05 PM PDT 24
Finished Jul 28 07:44:06 PM PDT 24
Peak memory 207052 kb
Host smart-af961df2-472d-4e9a-afa1-0267115606cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33762
79454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3376279454
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3702616569
Short name T1061
Test name
Test status
Simulation time 1055704778 ps
CPU time 2.7 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:11 PM PDT 24
Peak memory 207280 kb
Host smart-dd18492a-d9d6-43a4-9104-06663535aa34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37026
16569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3702616569
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.3277373328
Short name T792
Test name
Test status
Simulation time 6928374174 ps
CPU time 213.91 seconds
Started Jul 28 07:44:10 PM PDT 24
Finished Jul 28 07:47:44 PM PDT 24
Peak memory 215548 kb
Host smart-a0ba995e-b238-414c-a6cd-0d76bf109403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32773
73328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.3277373328
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.945946137
Short name T1972
Test name
Test status
Simulation time 1295161022 ps
CPU time 28.32 seconds
Started Jul 28 07:43:59 PM PDT 24
Finished Jul 28 07:44:28 PM PDT 24
Peak memory 207336 kb
Host smart-0e79ff5b-ac2f-41df-a41b-37b11034b9b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945946137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_host
_handshake.945946137
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.1933384152
Short name T1651
Test name
Test status
Simulation time 48342734 ps
CPU time 0.68 seconds
Started Jul 28 07:38:44 PM PDT 24
Finished Jul 28 07:38:45 PM PDT 24
Peak memory 207208 kb
Host smart-84186c7a-a2fd-4c1c-a7f5-09f260f2317f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1933384152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1933384152
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.1907594242
Short name T2204
Test name
Test status
Simulation time 3680937053 ps
CPU time 5.49 seconds
Started Jul 28 07:38:50 PM PDT 24
Finished Jul 28 07:38:56 PM PDT 24
Peak memory 207344 kb
Host smart-9b5a1b6d-8359-49d9-a49d-682a3d6a73d3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907594242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.1907594242
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2230043992
Short name T9
Test name
Test status
Simulation time 13398113456 ps
CPU time 15.52 seconds
Started Jul 28 07:38:43 PM PDT 24
Finished Jul 28 07:38:58 PM PDT 24
Peak memory 207380 kb
Host smart-58b4dfd0-ff93-44ad-a81d-f6aa13972b01
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230043992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2230043992
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3318496507
Short name T1966
Test name
Test status
Simulation time 23317050285 ps
CPU time 27.68 seconds
Started Jul 28 07:38:38 PM PDT 24
Finished Jul 28 07:39:06 PM PDT 24
Peak memory 207356 kb
Host smart-05b4461b-3165-49c3-8b01-33d62c1d4052
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318496507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.3318496507
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.134538416
Short name T2047
Test name
Test status
Simulation time 201481069 ps
CPU time 1.04 seconds
Started Jul 28 07:38:47 PM PDT 24
Finished Jul 28 07:38:48 PM PDT 24
Peak memory 207088 kb
Host smart-f1587c34-ea6c-46ea-88cc-30cb0b281206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13453
8416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.134538416
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.1156436128
Short name T50
Test name
Test status
Simulation time 158170718 ps
CPU time 0.86 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:38:42 PM PDT 24
Peak memory 207168 kb
Host smart-90b002e6-4126-40f6-9c12-6db7b6cff3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11564
36128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.1156436128
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.1055464213
Short name T105
Test name
Test status
Simulation time 170952437 ps
CPU time 0.85 seconds
Started Jul 28 07:38:45 PM PDT 24
Finished Jul 28 07:38:46 PM PDT 24
Peak memory 206992 kb
Host smart-212be4fb-5654-4fd3-9aa3-7baeeec7775a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10554
64213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.1055464213
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.1461168495
Short name T2616
Test name
Test status
Simulation time 162350885 ps
CPU time 0.83 seconds
Started Jul 28 07:38:40 PM PDT 24
Finished Jul 28 07:38:40 PM PDT 24
Peak memory 207048 kb
Host smart-3063e209-50d3-46f3-95f6-509e737511bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14611
68495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.1461168495
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2449031954
Short name T2582
Test name
Test status
Simulation time 628075490 ps
CPU time 1.81 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 207312 kb
Host smart-6ccdad37-5629-4c3a-bdc7-547978ce84c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24490
31954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2449031954
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2802012218
Short name T2432
Test name
Test status
Simulation time 1200562141 ps
CPU time 3.36 seconds
Started Jul 28 07:38:40 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 207328 kb
Host smart-f88c2e39-5cac-4659-a1e7-a401c6745ab9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2802012218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2802012218
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.4204317086
Short name T2358
Test name
Test status
Simulation time 7775019951 ps
CPU time 18.06 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:39:00 PM PDT 24
Peak memory 207332 kb
Host smart-3acb0797-9ef8-44a6-ab1c-14ad60b1e6e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42043
17086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.4204317086
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.3645175278
Short name T940
Test name
Test status
Simulation time 1153483133 ps
CPU time 26.61 seconds
Started Jul 28 07:38:37 PM PDT 24
Finished Jul 28 07:39:04 PM PDT 24
Peak memory 207272 kb
Host smart-c146d735-0a6e-4d58-b787-74f47e0f8933
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645175278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.3645175278
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.2091467716
Short name T2436
Test name
Test status
Simulation time 368367886 ps
CPU time 1.39 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 207024 kb
Host smart-1b86e55e-6ebc-4fbe-a1ba-d7a582c54996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20914
67716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.2091467716
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1257706955
Short name T1593
Test name
Test status
Simulation time 186316475 ps
CPU time 0.84 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:38:42 PM PDT 24
Peak memory 207120 kb
Host smart-f30d4737-f4b5-4d73-97c8-13a272f2f11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12577
06955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1257706955
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.2584775624
Short name T568
Test name
Test status
Simulation time 42926653 ps
CPU time 0.67 seconds
Started Jul 28 07:38:46 PM PDT 24
Finished Jul 28 07:38:46 PM PDT 24
Peak memory 207116 kb
Host smart-4ef4c6a6-460f-481d-89e4-b0bad8a119a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25847
75624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2584775624
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3795879436
Short name T383
Test name
Test status
Simulation time 986742317 ps
CPU time 2.64 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 207440 kb
Host smart-b6c5a314-b672-4967-a6a1-231488af53f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37958
79436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3795879436
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.495696370
Short name T679
Test name
Test status
Simulation time 292571847 ps
CPU time 1.98 seconds
Started Jul 28 07:38:44 PM PDT 24
Finished Jul 28 07:38:46 PM PDT 24
Peak memory 207324 kb
Host smart-a191ad13-15e6-4317-ab64-c8e1b0dda6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49569
6370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.495696370
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.3173339885
Short name T2165
Test name
Test status
Simulation time 97188286345 ps
CPU time 168.08 seconds
Started Jul 28 07:38:44 PM PDT 24
Finished Jul 28 07:41:32 PM PDT 24
Peak memory 207392 kb
Host smart-649d0219-8a2a-495c-9749-d593dce00ef6
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3173339885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.3173339885
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.2350354792
Short name T1519
Test name
Test status
Simulation time 102050465142 ps
CPU time 165.42 seconds
Started Jul 28 07:38:42 PM PDT 24
Finished Jul 28 07:41:27 PM PDT 24
Peak memory 207340 kb
Host smart-daff8247-81dc-43df-948a-4601cc0eecb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350354792 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.2350354792
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.321727695
Short name T1389
Test name
Test status
Simulation time 120155171824 ps
CPU time 186.01 seconds
Started Jul 28 07:38:43 PM PDT 24
Finished Jul 28 07:41:50 PM PDT 24
Peak memory 207368 kb
Host smart-b5c0b323-409c-48b0-adb2-1191e61d2b24
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=321727695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.321727695
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.2457958279
Short name T773
Test name
Test status
Simulation time 81031882422 ps
CPU time 137.69 seconds
Started Jul 28 07:38:42 PM PDT 24
Finished Jul 28 07:41:00 PM PDT 24
Peak memory 207328 kb
Host smart-7ddb76ab-ddc7-4c98-83a9-b3c1bbf1bda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457958279 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.2457958279
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.4290595062
Short name T2228
Test name
Test status
Simulation time 106157524049 ps
CPU time 168.29 seconds
Started Jul 28 07:38:45 PM PDT 24
Finished Jul 28 07:41:34 PM PDT 24
Peak memory 207392 kb
Host smart-f27e5260-3aa0-46d0-8e52-f3b7d051c6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42905
95062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.4290595062
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1568108993
Short name T1643
Test name
Test status
Simulation time 200745510 ps
CPU time 1.09 seconds
Started Jul 28 07:38:45 PM PDT 24
Finished Jul 28 07:38:46 PM PDT 24
Peak memory 215544 kb
Host smart-d6d63d35-5d8e-441f-82e1-c9021207355e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1568108993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1568108993
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1500826780
Short name T1949
Test name
Test status
Simulation time 212132390 ps
CPU time 0.94 seconds
Started Jul 28 07:38:44 PM PDT 24
Finished Jul 28 07:38:45 PM PDT 24
Peak memory 207120 kb
Host smart-1f7c7bd6-9dac-4f09-820e-e5beb77cd742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15008
26780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1500826780
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1916215181
Short name T957
Test name
Test status
Simulation time 184135002 ps
CPU time 0.93 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:38:42 PM PDT 24
Peak memory 207200 kb
Host smart-b2b4c84a-fe1d-4859-af0c-95fea50ff0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19162
15181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1916215181
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.558026330
Short name T1888
Test name
Test status
Simulation time 9332848756 ps
CPU time 74.87 seconds
Started Jul 28 07:38:42 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 217260 kb
Host smart-0d84d1f3-1851-41e3-b917-4839e0d2ae3a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=558026330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.558026330
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.2817270593
Short name T2281
Test name
Test status
Simulation time 12074498616 ps
CPU time 148.99 seconds
Started Jul 28 07:38:45 PM PDT 24
Finished Jul 28 07:41:14 PM PDT 24
Peak memory 207308 kb
Host smart-7a1d3d42-c754-4e40-bb0a-242e61be89ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2817270593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.2817270593
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3323576246
Short name T1577
Test name
Test status
Simulation time 202195248 ps
CPU time 0.89 seconds
Started Jul 28 07:38:42 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 207168 kb
Host smart-b45e0a2b-bb1d-4739-a9b0-bccb7b697942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33235
76246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3323576246
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.4184238271
Short name T978
Test name
Test status
Simulation time 23374829884 ps
CPU time 26.78 seconds
Started Jul 28 07:38:53 PM PDT 24
Finished Jul 28 07:39:20 PM PDT 24
Peak memory 207356 kb
Host smart-3a8dc2df-31f7-422c-9467-ba180022b414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41842
38271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.4184238271
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2337162264
Short name T946
Test name
Test status
Simulation time 3300357768 ps
CPU time 5.08 seconds
Started Jul 28 07:38:43 PM PDT 24
Finished Jul 28 07:38:48 PM PDT 24
Peak memory 207284 kb
Host smart-3ecdc153-5e35-4d6a-85f7-1188a4a7b0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23371
62264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2337162264
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.852294278
Short name T2738
Test name
Test status
Simulation time 8298468821 ps
CPU time 61.83 seconds
Started Jul 28 07:38:59 PM PDT 24
Finished Jul 28 07:40:01 PM PDT 24
Peak memory 217524 kb
Host smart-30a6dd09-2f5e-4ed4-9181-89ae39052726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85229
4278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.852294278
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.3770795662
Short name T2215
Test name
Test status
Simulation time 3987745146 ps
CPU time 116.1 seconds
Started Jul 28 07:38:58 PM PDT 24
Finished Jul 28 07:40:54 PM PDT 24
Peak memory 215680 kb
Host smart-218f35be-0524-4490-9abb-5cd6488f493c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3770795662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.3770795662
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.1794315669
Short name T884
Test name
Test status
Simulation time 240571756 ps
CPU time 0.96 seconds
Started Jul 28 07:38:40 PM PDT 24
Finished Jul 28 07:38:41 PM PDT 24
Peak memory 207172 kb
Host smart-1c40a6c6-822e-48ba-9937-a40a108cb0fd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1794315669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.1794315669
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1676760536
Short name T621
Test name
Test status
Simulation time 184866234 ps
CPU time 0.97 seconds
Started Jul 28 07:38:47 PM PDT 24
Finished Jul 28 07:38:48 PM PDT 24
Peak memory 207148 kb
Host smart-ea8924a3-159d-4bb2-8676-8bd79fba09bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16767
60536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1676760536
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3427564672
Short name T1881
Test name
Test status
Simulation time 3819815984 ps
CPU time 113.45 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:40:35 PM PDT 24
Peak memory 215508 kb
Host smart-df91a915-e446-443f-9621-ebf428f3c0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34275
64672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3427564672
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.936428136
Short name T2549
Test name
Test status
Simulation time 3050353728 ps
CPU time 87.69 seconds
Started Jul 28 07:38:40 PM PDT 24
Finished Jul 28 07:40:08 PM PDT 24
Peak memory 215636 kb
Host smart-8bc338fc-f9a8-4cfe-9333-a229af10e6c9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=936428136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.936428136
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.460444143
Short name T1183
Test name
Test status
Simulation time 157730750 ps
CPU time 0.85 seconds
Started Jul 28 07:38:42 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 207072 kb
Host smart-67f5d265-727c-4191-9461-998876a91efc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=460444143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.460444143
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.360292523
Short name T803
Test name
Test status
Simulation time 144327316 ps
CPU time 0.82 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:38:42 PM PDT 24
Peak memory 207120 kb
Host smart-3d235b2d-798f-4ad8-819e-a5ac3bbee2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36029
2523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.360292523
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.627369439
Short name T126
Test name
Test status
Simulation time 169149684 ps
CPU time 0.84 seconds
Started Jul 28 07:38:46 PM PDT 24
Finished Jul 28 07:38:47 PM PDT 24
Peak memory 207116 kb
Host smart-0aec2119-1ffe-4e6d-b5c4-d5aeff35f408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62736
9439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.627369439
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.395857510
Short name T2188
Test name
Test status
Simulation time 164775218 ps
CPU time 0.9 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:38:42 PM PDT 24
Peak memory 207264 kb
Host smart-51a56f0c-76ce-4de9-80f5-4b6ac4e5bacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
7510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.395857510
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3570329622
Short name T2027
Test name
Test status
Simulation time 169840431 ps
CPU time 0.85 seconds
Started Jul 28 07:38:47 PM PDT 24
Finished Jul 28 07:38:48 PM PDT 24
Peak memory 207128 kb
Host smart-ac983869-014f-4111-aff4-efcdf4240e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35703
29622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3570329622
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3923871292
Short name T1382
Test name
Test status
Simulation time 176040164 ps
CPU time 0.86 seconds
Started Jul 28 07:38:42 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 207112 kb
Host smart-697ae654-a02c-414e-93f0-c9303ca1f8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39238
71292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3923871292
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1284162387
Short name T1959
Test name
Test status
Simulation time 157317172 ps
CPU time 0.87 seconds
Started Jul 28 07:38:42 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 207120 kb
Host smart-7da917e7-1a84-448e-b39b-9c0dcadbe4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12841
62387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1284162387
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.1280450776
Short name T1409
Test name
Test status
Simulation time 218390780 ps
CPU time 1.05 seconds
Started Jul 28 07:38:44 PM PDT 24
Finished Jul 28 07:38:45 PM PDT 24
Peak memory 207120 kb
Host smart-54fd9e06-f916-4114-aa4a-eb094b619033
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1280450776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.1280450776
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.678594161
Short name T195
Test name
Test status
Simulation time 196510232 ps
CPU time 0.94 seconds
Started Jul 28 07:38:42 PM PDT 24
Finished Jul 28 07:38:44 PM PDT 24
Peak memory 207144 kb
Host smart-edbc1310-9e63-4559-a6d4-a769cc249a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67859
4161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.678594161
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1782992092
Short name T823
Test name
Test status
Simulation time 146705758 ps
CPU time 0.84 seconds
Started Jul 28 07:38:46 PM PDT 24
Finished Jul 28 07:38:47 PM PDT 24
Peak memory 207048 kb
Host smart-9f2bc787-1d42-48d3-abb7-c7405a613454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17829
92092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.1782992092
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3645664208
Short name T1944
Test name
Test status
Simulation time 57554490 ps
CPU time 0.72 seconds
Started Jul 28 07:38:44 PM PDT 24
Finished Jul 28 07:38:45 PM PDT 24
Peak memory 207016 kb
Host smart-72cbd5ff-1acc-4c73-ba7e-a9abeb9b413f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36456
64208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3645664208
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.2975714834
Short name T2502
Test name
Test status
Simulation time 13011532151 ps
CPU time 33.64 seconds
Started Jul 28 07:38:45 PM PDT 24
Finished Jul 28 07:39:19 PM PDT 24
Peak memory 219232 kb
Host smart-70800232-d2f6-4632-9d88-7ec524b673f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29757
14834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.2975714834
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.4108587278
Short name T1687
Test name
Test status
Simulation time 168240264 ps
CPU time 0.87 seconds
Started Jul 28 07:38:41 PM PDT 24
Finished Jul 28 07:38:42 PM PDT 24
Peak memory 207132 kb
Host smart-ed18e6cc-6bfd-4bb4-89cb-ef873604bcce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41085
87278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.4108587278
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3198756515
Short name T1191
Test name
Test status
Simulation time 219352918 ps
CPU time 0.99 seconds
Started Jul 28 07:38:53 PM PDT 24
Finished Jul 28 07:38:55 PM PDT 24
Peak memory 207144 kb
Host smart-222bc4f5-d3bf-42a3-b820-2e7ba576587a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31987
56515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3198756515
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1906583362
Short name T156
Test name
Test status
Simulation time 9938263717 ps
CPU time 71.3 seconds
Started Jul 28 07:38:48 PM PDT 24
Finished Jul 28 07:40:00 PM PDT 24
Peak memory 218808 kb
Host smart-98337786-d117-4a2a-b5f9-940567b9b1d9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906583362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1906583362
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.3280073423
Short name T298
Test name
Test status
Simulation time 8039946082 ps
CPU time 41.13 seconds
Started Jul 28 07:39:07 PM PDT 24
Finished Jul 28 07:39:48 PM PDT 24
Peak memory 218708 kb
Host smart-f9297a1e-e2ea-40b4-bd6f-0147e6a18eab
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280073423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.3280073423
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1833383737
Short name T1836
Test name
Test status
Simulation time 233183811 ps
CPU time 0.95 seconds
Started Jul 28 07:38:57 PM PDT 24
Finished Jul 28 07:38:58 PM PDT 24
Peak memory 207128 kb
Host smart-3957479a-28d1-40d0-aa6f-f6e8c04d06c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18333
83737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1833383737
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1355949841
Short name T1586
Test name
Test status
Simulation time 190768837 ps
CPU time 0.9 seconds
Started Jul 28 07:38:50 PM PDT 24
Finished Jul 28 07:38:51 PM PDT 24
Peak memory 207052 kb
Host smart-f97778bd-0101-4e0e-bf37-427c618534af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13559
49841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1355949841
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.976330033
Short name T1740
Test name
Test status
Simulation time 193359088 ps
CPU time 0.88 seconds
Started Jul 28 07:38:47 PM PDT 24
Finished Jul 28 07:38:48 PM PDT 24
Peak memory 207124 kb
Host smart-1fbf8be9-b436-47e7-b01b-185e7645373b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97633
0033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.976330033
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.3914853568
Short name T74
Test name
Test status
Simulation time 173586942 ps
CPU time 0.88 seconds
Started Jul 28 07:38:47 PM PDT 24
Finished Jul 28 07:38:48 PM PDT 24
Peak memory 207128 kb
Host smart-e8c99aa7-c0e6-45a8-a3a7-c9ff65af8b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39148
53568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.3914853568
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2737977840
Short name T203
Test name
Test status
Simulation time 1652367456 ps
CPU time 2.42 seconds
Started Jul 28 07:38:50 PM PDT 24
Finished Jul 28 07:38:52 PM PDT 24
Peak memory 224116 kb
Host smart-92bb2d3d-7501-4898-b3a6-4475070f99c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2737977840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2737977840
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.463805554
Short name T51
Test name
Test status
Simulation time 400686250 ps
CPU time 1.32 seconds
Started Jul 28 07:38:49 PM PDT 24
Finished Jul 28 07:38:51 PM PDT 24
Peak memory 207092 kb
Host smart-9caa6204-b78e-4fac-97e3-c2128f76ef15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46380
5554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.463805554
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.1980840843
Short name T100
Test name
Test status
Simulation time 203294823 ps
CPU time 0.99 seconds
Started Jul 28 07:38:47 PM PDT 24
Finished Jul 28 07:38:48 PM PDT 24
Peak memory 207192 kb
Host smart-1567ce52-2523-483f-8e1f-97a77f01139f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19808
40843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.1980840843
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.821960023
Short name T381
Test name
Test status
Simulation time 162929008 ps
CPU time 0.87 seconds
Started Jul 28 07:39:05 PM PDT 24
Finished Jul 28 07:39:06 PM PDT 24
Peak memory 207252 kb
Host smart-d98037eb-3aa9-4a48-9083-853ede02e9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82196
0023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.821960023
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.749765033
Short name T1573
Test name
Test status
Simulation time 151209487 ps
CPU time 0.82 seconds
Started Jul 28 07:38:50 PM PDT 24
Finished Jul 28 07:38:50 PM PDT 24
Peak memory 207080 kb
Host smart-ed6e1fd6-29af-4c68-b1a8-a615b3c022ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74976
5033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.749765033
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.4247863464
Short name T1882
Test name
Test status
Simulation time 220884167 ps
CPU time 0.99 seconds
Started Jul 28 07:38:48 PM PDT 24
Finished Jul 28 07:38:49 PM PDT 24
Peak memory 207136 kb
Host smart-7d226bb2-88dd-4971-a80e-13dcab9f1e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42478
63464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.4247863464
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.2048176227
Short name T2486
Test name
Test status
Simulation time 5051713381 ps
CPU time 50.15 seconds
Started Jul 28 07:38:49 PM PDT 24
Finished Jul 28 07:39:39 PM PDT 24
Peak memory 215612 kb
Host smart-ffede384-8c1e-42b5-a7e2-209eed3b5aa1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2048176227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.2048176227
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.196223968
Short name T2075
Test name
Test status
Simulation time 183454857 ps
CPU time 0.89 seconds
Started Jul 28 07:39:01 PM PDT 24
Finished Jul 28 07:39:02 PM PDT 24
Peak memory 207184 kb
Host smart-e825ce18-c31e-4861-b5f0-36677574fe0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19622
3968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.196223968
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1490986722
Short name T2118
Test name
Test status
Simulation time 164462136 ps
CPU time 0.87 seconds
Started Jul 28 07:38:51 PM PDT 24
Finished Jul 28 07:38:52 PM PDT 24
Peak memory 207112 kb
Host smart-0d5224d7-0f61-4f16-9823-fe37a25b29d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14909
86722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1490986722
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.3157170982
Short name T17
Test name
Test status
Simulation time 971457671 ps
CPU time 2.65 seconds
Started Jul 28 07:38:52 PM PDT 24
Finished Jul 28 07:38:55 PM PDT 24
Peak memory 207320 kb
Host smart-90b8f9f1-7343-4108-9148-b9f9da13d509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31571
70982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.3157170982
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.3174020736
Short name T1083
Test name
Test status
Simulation time 7300926041 ps
CPU time 72.87 seconds
Started Jul 28 07:39:00 PM PDT 24
Finished Jul 28 07:40:13 PM PDT 24
Peak memory 207348 kb
Host smart-8b0d500a-d9e7-470e-88d9-129e2337ce55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31740
20736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.3174020736
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.486886145
Short name T170
Test name
Test status
Simulation time 10033263071 ps
CPU time 296.86 seconds
Started Jul 28 07:38:48 PM PDT 24
Finished Jul 28 07:43:45 PM PDT 24
Peak memory 217928 kb
Host smart-00da24c4-db28-4a2e-9ad9-01b9ce5f9766
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486886145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.486886145
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.3054738989
Short name T929
Test name
Test status
Simulation time 821633781 ps
CPU time 16.12 seconds
Started Jul 28 07:38:40 PM PDT 24
Finished Jul 28 07:38:57 PM PDT 24
Peak memory 207392 kb
Host smart-a1b7aaf4-1e05-40cf-ad58-d477192a568b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054738989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.3054738989
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.2180272970
Short name T464
Test name
Test status
Simulation time 34643070 ps
CPU time 0.65 seconds
Started Jul 28 07:44:04 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 207136 kb
Host smart-396724a1-63d4-4f40-b12c-a3c1b86f9e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2180272970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.2180272970
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1911481959
Short name T2441
Test name
Test status
Simulation time 4092147002 ps
CPU time 6.53 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:14 PM PDT 24
Peak memory 207408 kb
Host smart-d231320f-9d1e-44ec-a6a7-536e8da10b1c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911481959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.1911481959
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.3028716530
Short name T10
Test name
Test status
Simulation time 13325180631 ps
CPU time 15.51 seconds
Started Jul 28 07:44:16 PM PDT 24
Finished Jul 28 07:44:33 PM PDT 24
Peak memory 207436 kb
Host smart-097d4b7d-79c5-4565-99a4-48d28a6ea121
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028716530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.3028716530
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3080012485
Short name T2398
Test name
Test status
Simulation time 23347739449 ps
CPU time 27.3 seconds
Started Jul 28 07:43:58 PM PDT 24
Finished Jul 28 07:44:25 PM PDT 24
Peak memory 207304 kb
Host smart-ca218804-70e1-4401-9836-c1d63606c221
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080012485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.3080012485
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3414223888
Short name T1676
Test name
Test status
Simulation time 168393487 ps
CPU time 0.87 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:44:10 PM PDT 24
Peak memory 207200 kb
Host smart-77252d7e-b035-400b-a151-603529df36e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34142
23888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3414223888
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.3411395922
Short name T2351
Test name
Test status
Simulation time 154750717 ps
CPU time 0.88 seconds
Started Jul 28 07:44:01 PM PDT 24
Finished Jul 28 07:44:02 PM PDT 24
Peak memory 206996 kb
Host smart-723a9cf0-35f9-4e1a-9115-563f17b464e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34113
95922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3411395922
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.466781804
Short name T1830
Test name
Test status
Simulation time 219227791 ps
CPU time 1.03 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207132 kb
Host smart-3b266d4c-b2b5-4a91-8b31-bed62c2e762f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46678
1804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.466781804
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.86281142
Short name T2660
Test name
Test status
Simulation time 1069791465 ps
CPU time 2.55 seconds
Started Jul 28 07:44:13 PM PDT 24
Finished Jul 28 07:44:16 PM PDT 24
Peak memory 207508 kb
Host smart-70813edb-2a57-4501-a785-9ee57716f7e5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=86281142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.86281142
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1634654058
Short name T741
Test name
Test status
Simulation time 8821061915 ps
CPU time 18.25 seconds
Started Jul 28 07:44:15 PM PDT 24
Finished Jul 28 07:44:33 PM PDT 24
Peak memory 207500 kb
Host smart-a11aa6ca-e0ba-4b94-9dfe-0f709b85322d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16346
54058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1634654058
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.3888811568
Short name T547
Test name
Test status
Simulation time 681632767 ps
CPU time 15.13 seconds
Started Jul 28 07:43:59 PM PDT 24
Finished Jul 28 07:44:14 PM PDT 24
Peak memory 207292 kb
Host smart-bb4da650-c8e4-4a61-a3f8-55f2183046d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888811568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.3888811568
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2756206211
Short name T1034
Test name
Test status
Simulation time 503268682 ps
CPU time 1.76 seconds
Started Jul 28 07:44:11 PM PDT 24
Finished Jul 28 07:44:12 PM PDT 24
Peak memory 207080 kb
Host smart-ac55388c-9fd5-4d72-b3cf-7f19eebd4036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27562
06211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2756206211
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.771753601
Short name T1142
Test name
Test status
Simulation time 177267461 ps
CPU time 0.91 seconds
Started Jul 28 07:44:05 PM PDT 24
Finished Jul 28 07:44:06 PM PDT 24
Peak memory 207096 kb
Host smart-29f34a17-d60f-441b-996b-b69a7b32508d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77175
3601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.771753601
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.287008994
Short name T2612
Test name
Test status
Simulation time 43897504 ps
CPU time 0.71 seconds
Started Jul 28 07:44:01 PM PDT 24
Finished Jul 28 07:44:02 PM PDT 24
Peak memory 207004 kb
Host smart-bc811583-b77f-4418-adc4-9b4de8553360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28700
8994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.287008994
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3460826788
Short name T2624
Test name
Test status
Simulation time 860911782 ps
CPU time 2.32 seconds
Started Jul 28 07:43:58 PM PDT 24
Finished Jul 28 07:44:01 PM PDT 24
Peak memory 207308 kb
Host smart-355756e1-354a-43d7-a1c7-74bfa0e2833a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34608
26788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3460826788
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.845727374
Short name T406
Test name
Test status
Simulation time 175276046 ps
CPU time 1.35 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:11 PM PDT 24
Peak memory 207316 kb
Host smart-e31f0a62-36e1-44bc-a3a4-483f759fc10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84572
7374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.845727374
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3314036356
Short name T1501
Test name
Test status
Simulation time 221182981 ps
CPU time 1.05 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:01 PM PDT 24
Peak memory 215552 kb
Host smart-e87d8615-2a86-40d9-b1cb-be9ec4ed0a3c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3314036356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3314036356
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2432464238
Short name T2415
Test name
Test status
Simulation time 141372268 ps
CPU time 0.87 seconds
Started Jul 28 07:43:59 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 207172 kb
Host smart-61085d87-8b7d-4ff0-b495-f946c6d95319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24324
64238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2432464238
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2073755251
Short name T1170
Test name
Test status
Simulation time 210076751 ps
CPU time 0.98 seconds
Started Jul 28 07:44:14 PM PDT 24
Finished Jul 28 07:44:15 PM PDT 24
Peak memory 207096 kb
Host smart-d05267de-f70f-400e-a9cf-26b5a419c8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20737
55251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2073755251
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.4219254717
Short name T366
Test name
Test status
Simulation time 6179631495 ps
CPU time 65.19 seconds
Started Jul 28 07:44:01 PM PDT 24
Finished Jul 28 07:45:06 PM PDT 24
Peak memory 215660 kb
Host smart-43c23b74-6578-4377-8a01-39cf1176ab9a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4219254717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.4219254717
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.1805818281
Short name T943
Test name
Test status
Simulation time 6951544747 ps
CPU time 44.86 seconds
Started Jul 28 07:44:10 PM PDT 24
Finished Jul 28 07:44:56 PM PDT 24
Peak memory 207488 kb
Host smart-32f96f7c-4530-4731-b119-ec108f8bcd3d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1805818281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.1805818281
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.4105837307
Short name T2622
Test name
Test status
Simulation time 181899801 ps
CPU time 0.93 seconds
Started Jul 28 07:44:11 PM PDT 24
Finished Jul 28 07:44:12 PM PDT 24
Peak memory 207276 kb
Host smart-51530c15-c06e-4d1e-b047-caff1e5ecc84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41058
37307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.4105837307
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.2130350626
Short name T1838
Test name
Test status
Simulation time 23336855651 ps
CPU time 30.97 seconds
Started Jul 28 07:44:02 PM PDT 24
Finished Jul 28 07:44:33 PM PDT 24
Peak memory 207288 kb
Host smart-d2ed9c61-ee19-485f-9551-ba70c18bfedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21303
50626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.2130350626
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.959942525
Short name T629
Test name
Test status
Simulation time 3335537552 ps
CPU time 5.21 seconds
Started Jul 28 07:43:57 PM PDT 24
Finished Jul 28 07:44:02 PM PDT 24
Peak memory 207412 kb
Host smart-086d5047-8414-4468-b873-64810d4e05b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95994
2525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.959942525
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1757487790
Short name T1136
Test name
Test status
Simulation time 4911842362 ps
CPU time 142.33 seconds
Started Jul 28 07:44:03 PM PDT 24
Finished Jul 28 07:46:25 PM PDT 24
Peak memory 215544 kb
Host smart-2064cf4b-cae6-41a9-bd6b-078db0979a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17574
87790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1757487790
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1929948051
Short name T2183
Test name
Test status
Simulation time 4872028812 ps
CPU time 143.19 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:46:23 PM PDT 24
Peak memory 215596 kb
Host smart-3a39a5d3-8413-4a36-88cf-4841993c814c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1929948051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.1929948051
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.1029884355
Short name T2087
Test name
Test status
Simulation time 238442124 ps
CPU time 1.02 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207132 kb
Host smart-c12b194f-2b68-4510-a25f-eee2aebe6898
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1029884355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.1029884355
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2160935743
Short name T1618
Test name
Test status
Simulation time 196288131 ps
CPU time 1.06 seconds
Started Jul 28 07:43:58 PM PDT 24
Finished Jul 28 07:44:00 PM PDT 24
Peak memory 207076 kb
Host smart-76072f32-5795-44ee-b6ff-8f6a0df58574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21609
35743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2160935743
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.2445702661
Short name T1591
Test name
Test status
Simulation time 5583821024 ps
CPU time 55.02 seconds
Started Jul 28 07:44:16 PM PDT 24
Finished Jul 28 07:45:12 PM PDT 24
Peak memory 215556 kb
Host smart-d02b461f-b36a-4611-9013-d51b0c3c032b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24457
02661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.2445702661
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.2814461616
Short name T512
Test name
Test status
Simulation time 6879727425 ps
CPU time 71.06 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:45:21 PM PDT 24
Peak memory 207416 kb
Host smart-59552572-4488-4bb3-b6aa-2a8f1ed18e03
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2814461616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.2814461616
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3697576912
Short name T2754
Test name
Test status
Simulation time 185794099 ps
CPU time 0.9 seconds
Started Jul 28 07:44:16 PM PDT 24
Finished Jul 28 07:44:17 PM PDT 24
Peak memory 207124 kb
Host smart-4d90fad9-e472-4627-bcf4-b46bf1d059ef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3697576912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3697576912
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.4209002469
Short name T1025
Test name
Test status
Simulation time 151870581 ps
CPU time 0.9 seconds
Started Jul 28 07:44:06 PM PDT 24
Finished Jul 28 07:44:07 PM PDT 24
Peak memory 207168 kb
Host smart-e09b7f85-5a5c-4c60-b744-7ebd3520a058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42090
02469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.4209002469
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2585643334
Short name T1239
Test name
Test status
Simulation time 214800205 ps
CPU time 1.03 seconds
Started Jul 28 07:44:01 PM PDT 24
Finished Jul 28 07:44:02 PM PDT 24
Peak memory 207180 kb
Host smart-fe0133ea-96b1-4223-9ea4-1c36a2d91148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25856
43334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2585643334
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3677345294
Short name T2858
Test name
Test status
Simulation time 168842245 ps
CPU time 0.89 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207068 kb
Host smart-84a4eae7-3694-4d39-9244-e71e45b84ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36773
45294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3677345294
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3369379899
Short name T2596
Test name
Test status
Simulation time 156120553 ps
CPU time 0.84 seconds
Started Jul 28 07:44:18 PM PDT 24
Finished Jul 28 07:44:19 PM PDT 24
Peak memory 207144 kb
Host smart-98ccafe1-0562-419f-8b0c-45d45b1e7e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33693
79899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3369379899
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3034600212
Short name T1657
Test name
Test status
Simulation time 143699036 ps
CPU time 0.83 seconds
Started Jul 28 07:44:13 PM PDT 24
Finished Jul 28 07:44:14 PM PDT 24
Peak memory 207128 kb
Host smart-4928710b-2c5d-418a-9462-3bf7fdf4ba9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30346
00212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3034600212
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.608328145
Short name T2115
Test name
Test status
Simulation time 204273786 ps
CPU time 0.92 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:01 PM PDT 24
Peak memory 207200 kb
Host smart-9ae74efa-81c5-497b-9f46-05747f1d4f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60832
8145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.608328145
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.2581077902
Short name T2456
Test name
Test status
Simulation time 228342868 ps
CPU time 0.97 seconds
Started Jul 28 07:44:19 PM PDT 24
Finished Jul 28 07:44:20 PM PDT 24
Peak memory 207076 kb
Host smart-3091397f-a452-4eb5-b73a-ec70da6800e4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2581077902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.2581077902
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2697389813
Short name T651
Test name
Test status
Simulation time 153764801 ps
CPU time 0.83 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:01 PM PDT 24
Peak memory 207132 kb
Host smart-0cf4b06c-0a73-473d-b60a-e1925c4153d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26973
89813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2697389813
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1447245177
Short name T1552
Test name
Test status
Simulation time 50688947 ps
CPU time 0.71 seconds
Started Jul 28 07:44:18 PM PDT 24
Finished Jul 28 07:44:19 PM PDT 24
Peak memory 207104 kb
Host smart-00cf2127-baff-420e-b903-fb3dea9babb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14472
45177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1447245177
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3892379063
Short name T1301
Test name
Test status
Simulation time 6621595241 ps
CPU time 17.72 seconds
Started Jul 28 07:44:11 PM PDT 24
Finished Jul 28 07:44:29 PM PDT 24
Peak memory 215760 kb
Host smart-c74354a2-1494-4d6a-a678-f6e8ee9a609f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38923
79063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3892379063
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3291862347
Short name T2283
Test name
Test status
Simulation time 193510049 ps
CPU time 0.95 seconds
Started Jul 28 07:44:15 PM PDT 24
Finished Jul 28 07:44:16 PM PDT 24
Peak memory 207128 kb
Host smart-89a70d51-7492-4a96-b557-ed2c3c033a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32918
62347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3291862347
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2921783803
Short name T1310
Test name
Test status
Simulation time 237660448 ps
CPU time 1 seconds
Started Jul 28 07:44:06 PM PDT 24
Finished Jul 28 07:44:08 PM PDT 24
Peak memory 207028 kb
Host smart-28afafe6-eace-45fc-b323-0290ab68b0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29217
83803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2921783803
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.4182455546
Short name T1279
Test name
Test status
Simulation time 234215777 ps
CPU time 1.04 seconds
Started Jul 28 07:44:04 PM PDT 24
Finished Jul 28 07:44:05 PM PDT 24
Peak memory 207116 kb
Host smart-504d7dfb-0bec-4e28-a906-e51dc793d61a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41824
55546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.4182455546
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1245963402
Short name T2775
Test name
Test status
Simulation time 185963779 ps
CPU time 0.95 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:10 PM PDT 24
Peak memory 207200 kb
Host smart-02eaa8e4-4e3d-47ff-94f6-f3ff0fa67fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12459
63402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1245963402
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.1881837300
Short name T1493
Test name
Test status
Simulation time 159362110 ps
CPU time 0.81 seconds
Started Jul 28 07:44:12 PM PDT 24
Finished Jul 28 07:44:13 PM PDT 24
Peak memory 207020 kb
Host smart-6fa5e761-69de-4ead-aa4d-f6c7b52060a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18818
37300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.1881837300
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.3369278436
Short name T2321
Test name
Test status
Simulation time 149835980 ps
CPU time 0.84 seconds
Started Jul 28 07:44:03 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 207036 kb
Host smart-8fd1c189-06ec-4b33-ba2a-c5433e8249ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33692
78436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.3369278436
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.311174343
Short name T2170
Test name
Test status
Simulation time 155744935 ps
CPU time 0.82 seconds
Started Jul 28 07:44:13 PM PDT 24
Finished Jul 28 07:44:14 PM PDT 24
Peak memory 207296 kb
Host smart-c70fabac-7fdf-457f-af70-3f4b16db9200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31117
4343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.311174343
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1225263149
Short name T1885
Test name
Test status
Simulation time 202652061 ps
CPU time 0.99 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:44:11 PM PDT 24
Peak memory 207084 kb
Host smart-863657fa-1952-417f-959a-23dbaa899323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12252
63149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1225263149
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.483270341
Short name T572
Test name
Test status
Simulation time 6227783499 ps
CPU time 173.46 seconds
Started Jul 28 07:44:05 PM PDT 24
Finished Jul 28 07:46:58 PM PDT 24
Peak memory 215652 kb
Host smart-4a8eb7fc-640a-406f-8a80-e7ce1073e039
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=483270341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.483270341
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.725481707
Short name T802
Test name
Test status
Simulation time 168572008 ps
CPU time 0.83 seconds
Started Jul 28 07:44:05 PM PDT 24
Finished Jul 28 07:44:06 PM PDT 24
Peak memory 207104 kb
Host smart-2819ab07-05e2-490a-89d7-223eb56e24ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72548
1707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.725481707
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.4171410642
Short name T1923
Test name
Test status
Simulation time 159705021 ps
CPU time 0.84 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207168 kb
Host smart-892aee80-77b1-4945-bf2f-3d0a2286a9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41714
10642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.4171410642
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.3440059187
Short name T2790
Test name
Test status
Simulation time 452957881 ps
CPU time 1.4 seconds
Started Jul 28 07:44:12 PM PDT 24
Finished Jul 28 07:44:13 PM PDT 24
Peak memory 207096 kb
Host smart-8245dd38-48e0-420b-ba03-f48e55f91714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34400
59187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.3440059187
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.1103665390
Short name T2429
Test name
Test status
Simulation time 7846340169 ps
CPU time 228.11 seconds
Started Jul 28 07:44:04 PM PDT 24
Finished Jul 28 07:47:52 PM PDT 24
Peak memory 215596 kb
Host smart-dbd5031c-4802-4ea4-b6df-16bc0e5042bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11036
65390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1103665390
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.3784174741
Short name T907
Test name
Test status
Simulation time 2464079167 ps
CPU time 22.63 seconds
Started Jul 28 07:43:56 PM PDT 24
Finished Jul 28 07:44:19 PM PDT 24
Peak memory 207376 kb
Host smart-d690d6bc-0fe3-49d1-924f-d8c54535572f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784174741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.3784174741
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.153994885
Short name T403
Test name
Test status
Simulation time 40003927 ps
CPU time 0.65 seconds
Started Jul 28 07:44:17 PM PDT 24
Finished Jul 28 07:44:18 PM PDT 24
Peak memory 207180 kb
Host smart-67a022c9-152e-4ec3-b943-45f867f9fc2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=153994885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.153994885
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3708855491
Short name T933
Test name
Test status
Simulation time 4043496902 ps
CPU time 5.72 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:44:15 PM PDT 24
Peak memory 207348 kb
Host smart-916173cf-3cbb-480d-8e44-77ed12550abc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708855491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.3708855491
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.4266244383
Short name T877
Test name
Test status
Simulation time 13489023360 ps
CPU time 16.49 seconds
Started Jul 28 07:44:15 PM PDT 24
Finished Jul 28 07:44:31 PM PDT 24
Peak memory 207388 kb
Host smart-1cd06052-020c-4776-8d81-6bd8e6ef76fe
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266244383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.4266244383
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.908250296
Short name T2789
Test name
Test status
Simulation time 23297970675 ps
CPU time 28.87 seconds
Started Jul 28 07:44:10 PM PDT 24
Finished Jul 28 07:44:39 PM PDT 24
Peak memory 207400 kb
Host smart-59ddd063-be3a-4cea-bb3b-7ca3d4f71189
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908250296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_ao
n_wake_resume.908250296
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.251227200
Short name T1399
Test name
Test status
Simulation time 191536703 ps
CPU time 0.88 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:08 PM PDT 24
Peak memory 207072 kb
Host smart-233df37c-76cd-4eb2-a356-51c81315ceba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25122
7200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.251227200
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2635484042
Short name T72
Test name
Test status
Simulation time 210425529 ps
CPU time 0.88 seconds
Started Jul 28 07:44:00 PM PDT 24
Finished Jul 28 07:44:01 PM PDT 24
Peak memory 207132 kb
Host smart-51d32c4b-f6c7-4e38-b66c-c6f7b2e74c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26354
84042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2635484042
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.383659720
Short name T1817
Test name
Test status
Simulation time 280865170 ps
CPU time 1.16 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:44:10 PM PDT 24
Peak memory 207132 kb
Host smart-078b10ea-1cca-4afe-b29f-02cee16919d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38365
9720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.383659720
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1800523650
Short name T2403
Test name
Test status
Simulation time 1063381519 ps
CPU time 2.74 seconds
Started Jul 28 07:44:10 PM PDT 24
Finished Jul 28 07:44:13 PM PDT 24
Peak memory 207244 kb
Host smart-6e6300b0-7093-43ae-bc7f-fd05ef59d9f2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1800523650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1800523650
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.4232269613
Short name T2749
Test name
Test status
Simulation time 10293346521 ps
CPU time 22.36 seconds
Started Jul 28 07:44:16 PM PDT 24
Finished Jul 28 07:44:39 PM PDT 24
Peak memory 207404 kb
Host smart-fa0f5bc3-c15b-4192-8697-fa38eb30e768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42322
69613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.4232269613
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.426626302
Short name T1257
Test name
Test status
Simulation time 783211707 ps
CPU time 15.61 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:23 PM PDT 24
Peak memory 207264 kb
Host smart-e416d621-b181-4819-9e25-9556601c7470
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426626302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.426626302
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.2262364995
Short name T20
Test name
Test status
Simulation time 457955194 ps
CPU time 1.45 seconds
Started Jul 28 07:44:12 PM PDT 24
Finished Jul 28 07:44:14 PM PDT 24
Peak memory 207100 kb
Host smart-14d27104-6d68-4510-9841-3e6418a9b6ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22623
64995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.2262364995
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.2979316224
Short name T2200
Test name
Test status
Simulation time 151116303 ps
CPU time 0.83 seconds
Started Jul 28 07:44:17 PM PDT 24
Finished Jul 28 07:44:18 PM PDT 24
Peak memory 207100 kb
Host smart-9595dd6e-8d3f-49f3-95e0-dd0a2d36e353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29793
16224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.2979316224
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3389985976
Short name T1175
Test name
Test status
Simulation time 76365644 ps
CPU time 0.74 seconds
Started Jul 28 07:44:15 PM PDT 24
Finished Jul 28 07:44:16 PM PDT 24
Peak memory 207040 kb
Host smart-09d43796-7ae7-4e38-8969-04d2eb25f859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33899
85976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3389985976
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.4195193586
Short name T1342
Test name
Test status
Simulation time 871599173 ps
CPU time 2.46 seconds
Started Jul 28 07:44:15 PM PDT 24
Finished Jul 28 07:44:19 PM PDT 24
Peak memory 207320 kb
Host smart-2a5a46e3-2a1e-4368-ae5c-aee05eba034a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41951
93586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.4195193586
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.692290893
Short name T180
Test name
Test status
Simulation time 386940056 ps
CPU time 2.53 seconds
Started Jul 28 07:44:17 PM PDT 24
Finished Jul 28 07:44:20 PM PDT 24
Peak memory 207280 kb
Host smart-85ac5a0f-8fc6-49b5-9272-d33c6de15919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69229
0893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.692290893
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3806797691
Short name T740
Test name
Test status
Simulation time 155428132 ps
CPU time 0.88 seconds
Started Jul 28 07:44:13 PM PDT 24
Finished Jul 28 07:44:14 PM PDT 24
Peak memory 207188 kb
Host smart-1943b987-a119-4364-8c0a-fa2b7ed82f5f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3806797691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3806797691
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.889354130
Short name T95
Test name
Test status
Simulation time 136331551 ps
CPU time 0.82 seconds
Started Jul 28 07:44:15 PM PDT 24
Finished Jul 28 07:44:16 PM PDT 24
Peak memory 207136 kb
Host smart-22afc6de-e662-4912-91b9-14ba79a5995d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88935
4130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.889354130
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2048965496
Short name T1546
Test name
Test status
Simulation time 275902513 ps
CPU time 1.1 seconds
Started Jul 28 07:44:13 PM PDT 24
Finished Jul 28 07:44:14 PM PDT 24
Peak memory 207300 kb
Host smart-83aa481e-f247-4f42-9973-67227ba74042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20489
65496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2048965496
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.4078257816
Short name T89
Test name
Test status
Simulation time 5286040374 ps
CPU time 53.6 seconds
Started Jul 28 07:44:03 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 217120 kb
Host smart-8b1e005f-62ee-4da0-bc1f-d2fc18157853
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4078257816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.4078257816
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.2389014279
Short name T1929
Test name
Test status
Simulation time 10963564540 ps
CPU time 129.65 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:46:18 PM PDT 24
Peak memory 207324 kb
Host smart-c28100c0-dfa2-4357-894f-fcfe1052931a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2389014279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.2389014279
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.3617636316
Short name T2476
Test name
Test status
Simulation time 202505278 ps
CPU time 0.93 seconds
Started Jul 28 07:44:14 PM PDT 24
Finished Jul 28 07:44:18 PM PDT 24
Peak memory 207080 kb
Host smart-68daae5d-9a79-42b9-95ee-03cefb14d149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36176
36316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.3617636316
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3044672599
Short name T977
Test name
Test status
Simulation time 23320917186 ps
CPU time 29.8 seconds
Started Jul 28 07:44:40 PM PDT 24
Finished Jul 28 07:45:10 PM PDT 24
Peak memory 207300 kb
Host smart-7d265b4e-e5b5-4475-842d-e8e126fb5bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30446
72599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3044672599
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.4180062028
Short name T571
Test name
Test status
Simulation time 3326510173 ps
CPU time 5.42 seconds
Started Jul 28 07:44:10 PM PDT 24
Finished Jul 28 07:44:15 PM PDT 24
Peak memory 207356 kb
Host smart-0e92cc6f-2ce9-4e2e-a6fc-33d156891971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41800
62028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.4180062028
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.624743252
Short name T108
Test name
Test status
Simulation time 5272593192 ps
CPU time 144.47 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:46:32 PM PDT 24
Peak memory 215596 kb
Host smart-486a6a95-76a6-4f18-a607-2c088dd1b1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62474
3252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.624743252
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3760967856
Short name T2352
Test name
Test status
Simulation time 5559401530 ps
CPU time 159.83 seconds
Started Jul 28 07:44:12 PM PDT 24
Finished Jul 28 07:46:52 PM PDT 24
Peak memory 215572 kb
Host smart-3182fa1b-c158-40c7-9d02-22f87b9fd4d3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3760967856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3760967856
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.917839092
Short name T702
Test name
Test status
Simulation time 272874952 ps
CPU time 0.97 seconds
Started Jul 28 07:44:12 PM PDT 24
Finished Jul 28 07:44:13 PM PDT 24
Peak memory 207160 kb
Host smart-ab4d72a3-e9f8-477a-8d8c-307b23464704
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=917839092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.917839092
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2135506005
Short name T2109
Test name
Test status
Simulation time 196072827 ps
CPU time 0.99 seconds
Started Jul 28 07:44:11 PM PDT 24
Finished Jul 28 07:44:12 PM PDT 24
Peak memory 207124 kb
Host smart-9d760437-4f67-4fc7-b8fc-33aeb2a8dd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21355
06005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2135506005
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.664839349
Short name T37
Test name
Test status
Simulation time 6480453564 ps
CPU time 193.4 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:47:22 PM PDT 24
Peak memory 215568 kb
Host smart-c9ef758e-a5ac-49ab-a2a8-e78e4fc88e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66483
9349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.664839349
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.868353336
Short name T636
Test name
Test status
Simulation time 5391866314 ps
CPU time 161.55 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:46:51 PM PDT 24
Peak memory 215608 kb
Host smart-d5b71f19-b59e-4231-8338-be3528ce7997
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=868353336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.868353336
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.1554413251
Short name T1770
Test name
Test status
Simulation time 156630566 ps
CPU time 0.85 seconds
Started Jul 28 07:44:16 PM PDT 24
Finished Jul 28 07:44:17 PM PDT 24
Peak memory 207148 kb
Host smart-ed166c0d-2592-40cb-92c4-2fb3585f7b93
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1554413251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.1554413251
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.4187523974
Short name T579
Test name
Test status
Simulation time 151167473 ps
CPU time 0.83 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207204 kb
Host smart-1c4c3331-b31b-4253-9f68-b648c00450ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41875
23974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.4187523974
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.643842912
Short name T1099
Test name
Test status
Simulation time 177340684 ps
CPU time 0.87 seconds
Started Jul 28 07:44:17 PM PDT 24
Finished Jul 28 07:44:18 PM PDT 24
Peak memory 207148 kb
Host smart-e4b47940-04d5-45b1-b113-06a6af7fabc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64384
2912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.643842912
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3240210942
Short name T1904
Test name
Test status
Simulation time 172940897 ps
CPU time 0.87 seconds
Started Jul 28 07:44:13 PM PDT 24
Finished Jul 28 07:44:14 PM PDT 24
Peak memory 207136 kb
Host smart-0acef57b-7d6b-4c4b-b57b-049fde0ebe9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32402
10942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3240210942
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3512595306
Short name T698
Test name
Test status
Simulation time 192493263 ps
CPU time 0.92 seconds
Started Jul 28 07:44:20 PM PDT 24
Finished Jul 28 07:44:21 PM PDT 24
Peak memory 207168 kb
Host smart-61a92f81-99bd-4d00-972d-9f8a3f0cc12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35125
95306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3512595306
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1290633286
Short name T1858
Test name
Test status
Simulation time 161162249 ps
CPU time 0.84 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:10 PM PDT 24
Peak memory 207124 kb
Host smart-8d4b3dd1-aa7e-4d8a-af60-1ab1bab87ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12906
33286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1290633286
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.1315517612
Short name T2601
Test name
Test status
Simulation time 264651794 ps
CPU time 1.08 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:08 PM PDT 24
Peak memory 207128 kb
Host smart-3541f4b2-c464-41b7-a88c-52f9a37d3a58
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1315517612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.1315517612
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2782269936
Short name T2160
Test name
Test status
Simulation time 143849700 ps
CPU time 0.83 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207008 kb
Host smart-c6665ede-e552-4e2c-adda-1d5842ca74da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27822
69936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2782269936
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2437520026
Short name T2371
Test name
Test status
Simulation time 43159072 ps
CPU time 0.68 seconds
Started Jul 28 07:44:12 PM PDT 24
Finished Jul 28 07:44:13 PM PDT 24
Peak memory 207096 kb
Host smart-2b8eb980-c032-4273-b78f-95f10c350ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24375
20026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2437520026
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.3768870560
Short name T1406
Test name
Test status
Simulation time 190147923 ps
CPU time 0.92 seconds
Started Jul 28 07:44:11 PM PDT 24
Finished Jul 28 07:44:12 PM PDT 24
Peak memory 207152 kb
Host smart-a98b6bf0-07a1-46c0-baf8-9f7cf2fbb6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37688
70560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.3768870560
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3120728901
Short name T317
Test name
Test status
Simulation time 180541724 ps
CPU time 0.92 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207132 kb
Host smart-6521821f-ccaa-40d1-9e52-c068f842d95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31207
28901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3120728901
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1777530506
Short name T1622
Test name
Test status
Simulation time 229856220 ps
CPU time 0.96 seconds
Started Jul 28 07:44:13 PM PDT 24
Finished Jul 28 07:44:14 PM PDT 24
Peak memory 207152 kb
Host smart-1dbe994e-950d-4538-bba7-c2c4ec43ecc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17775
30506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1777530506
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.757330261
Short name T2107
Test name
Test status
Simulation time 151912610 ps
CPU time 0.82 seconds
Started Jul 28 07:44:13 PM PDT 24
Finished Jul 28 07:44:14 PM PDT 24
Peak memory 207144 kb
Host smart-7ff69bf5-2240-4386-b96a-287abb75bc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75733
0261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.757330261
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.3988846641
Short name T1906
Test name
Test status
Simulation time 195855749 ps
CPU time 0.88 seconds
Started Jul 28 07:44:08 PM PDT 24
Finished Jul 28 07:44:09 PM PDT 24
Peak memory 207040 kb
Host smart-e221ff0b-d668-4d9a-a89f-aa8009fb7b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39888
46641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.3988846641
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.541942812
Short name T2570
Test name
Test status
Simulation time 159610225 ps
CPU time 0.85 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:08 PM PDT 24
Peak memory 207136 kb
Host smart-acd35d30-57ad-40cf-abc2-370b023be58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54194
2812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.541942812
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3778748798
Short name T1663
Test name
Test status
Simulation time 158924460 ps
CPU time 0.83 seconds
Started Jul 28 07:44:15 PM PDT 24
Finished Jul 28 07:44:16 PM PDT 24
Peak memory 207144 kb
Host smart-4d241ee1-45b7-45e8-b20a-5627c2ad49c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37787
48798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3778748798
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3313097099
Short name T862
Test name
Test status
Simulation time 187143504 ps
CPU time 0.95 seconds
Started Jul 28 07:44:11 PM PDT 24
Finished Jul 28 07:44:12 PM PDT 24
Peak memory 207152 kb
Host smart-be780bd3-7b85-44a7-8775-251eab64e122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33130
97099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3313097099
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2766344872
Short name T2150
Test name
Test status
Simulation time 6723755743 ps
CPU time 70.85 seconds
Started Jul 28 07:44:17 PM PDT 24
Finished Jul 28 07:45:28 PM PDT 24
Peak memory 215584 kb
Host smart-0d14ef55-54c9-4c38-9382-5d75881de43d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2766344872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2766344872
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2811935186
Short name T549
Test name
Test status
Simulation time 167720527 ps
CPU time 0.86 seconds
Started Jul 28 07:44:07 PM PDT 24
Finished Jul 28 07:44:08 PM PDT 24
Peak memory 207088 kb
Host smart-62c82660-5bf0-4d15-8f61-2b19b5cce555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28119
35186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2811935186
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3704530045
Short name T345
Test name
Test status
Simulation time 150475473 ps
CPU time 0.8 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:44:10 PM PDT 24
Peak memory 207112 kb
Host smart-b8ff292c-206b-42bd-b645-67499d0e7394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37045
30045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3704530045
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.290652140
Short name T322
Test name
Test status
Simulation time 1393520290 ps
CPU time 3.23 seconds
Started Jul 28 07:44:21 PM PDT 24
Finished Jul 28 07:44:24 PM PDT 24
Peak memory 207388 kb
Host smart-e9ed9f8c-aacc-46ba-b45b-84d6710c9645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29065
2140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.290652140
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.3535078147
Short name T848
Test name
Test status
Simulation time 5269325928 ps
CPU time 41.72 seconds
Started Jul 28 07:44:15 PM PDT 24
Finished Jul 28 07:44:56 PM PDT 24
Peak memory 216920 kb
Host smart-86dccbde-6c8f-4ca8-8233-0fdd3578832a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35350
78147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.3535078147
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.3223301371
Short name T2263
Test name
Test status
Simulation time 1694926306 ps
CPU time 40.67 seconds
Started Jul 28 07:44:10 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 207344 kb
Host smart-2f0178ee-7174-46ba-945a-6cdd3add8100
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223301371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.3223301371
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.2567945183
Short name T2776
Test name
Test status
Simulation time 41227146 ps
CPU time 0.65 seconds
Started Jul 28 07:44:35 PM PDT 24
Finished Jul 28 07:44:36 PM PDT 24
Peak memory 207120 kb
Host smart-683e884a-744a-4997-a9e8-45862285516d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2567945183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.2567945183
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2007246376
Short name T1880
Test name
Test status
Simulation time 3936062522 ps
CPU time 6.18 seconds
Started Jul 28 07:44:18 PM PDT 24
Finished Jul 28 07:44:24 PM PDT 24
Peak memory 207428 kb
Host smart-95441128-a651-4bf9-ae58-41b7d81a19d3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007246376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.2007246376
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.183937596
Short name T993
Test name
Test status
Simulation time 13447885852 ps
CPU time 17.1 seconds
Started Jul 28 07:44:18 PM PDT 24
Finished Jul 28 07:44:35 PM PDT 24
Peak memory 207420 kb
Host smart-850b469a-ef76-41b4-bec5-74f91be0f0d2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=183937596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.183937596
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.243900219
Short name T2764
Test name
Test status
Simulation time 23346715483 ps
CPU time 35.41 seconds
Started Jul 28 07:44:17 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 207356 kb
Host smart-e54e1414-040c-49b4-a7de-e3063f27758d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243900219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_ao
n_wake_resume.243900219
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.771359667
Short name T1731
Test name
Test status
Simulation time 175177731 ps
CPU time 0.89 seconds
Started Jul 28 07:44:15 PM PDT 24
Finished Jul 28 07:44:16 PM PDT 24
Peak memory 207116 kb
Host smart-b92c4ed9-1a5c-40d3-931d-7ce34fe89b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77135
9667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.771359667
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.1910330072
Short name T1654
Test name
Test status
Simulation time 187717169 ps
CPU time 0.87 seconds
Started Jul 28 07:44:14 PM PDT 24
Finished Jul 28 07:44:15 PM PDT 24
Peak memory 207096 kb
Host smart-e5b0a018-4897-47ed-b054-e56ed2003368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19103
30072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.1910330072
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.4190590015
Short name T2524
Test name
Test status
Simulation time 172643661 ps
CPU time 0.93 seconds
Started Jul 28 07:44:09 PM PDT 24
Finished Jul 28 07:44:10 PM PDT 24
Peak memory 207160 kb
Host smart-6994801b-b6e4-4e93-beb8-dbe52a179862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41905
90015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.4190590015
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3637902624
Short name T496
Test name
Test status
Simulation time 342604867 ps
CPU time 1.16 seconds
Started Jul 28 07:44:14 PM PDT 24
Finished Jul 28 07:44:16 PM PDT 24
Peak memory 207120 kb
Host smart-34acc952-f4db-46d4-9347-85b2f8dfc550
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3637902624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3637902624
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.57394494
Short name T2604
Test name
Test status
Simulation time 8964369845 ps
CPU time 20.04 seconds
Started Jul 28 07:44:18 PM PDT 24
Finished Jul 28 07:44:39 PM PDT 24
Peak memory 207324 kb
Host smart-c4c48c86-6b00-4e09-9423-801e8c1f3c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57394
494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.57394494
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.701389735
Short name T204
Test name
Test status
Simulation time 745726745 ps
CPU time 15 seconds
Started Jul 28 07:44:14 PM PDT 24
Finished Jul 28 07:44:29 PM PDT 24
Peak memory 207296 kb
Host smart-f06f971c-1203-4cde-b370-813e9c05c336
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701389735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.701389735
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3181210935
Short name T1304
Test name
Test status
Simulation time 332935266 ps
CPU time 1.22 seconds
Started Jul 28 07:44:19 PM PDT 24
Finished Jul 28 07:44:20 PM PDT 24
Peak memory 207124 kb
Host smart-b3d3d1f5-7ece-442c-bca4-e1d032104e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31812
10935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3181210935
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.521169109
Short name T1268
Test name
Test status
Simulation time 146407762 ps
CPU time 0.83 seconds
Started Jul 28 07:44:17 PM PDT 24
Finished Jul 28 07:44:18 PM PDT 24
Peak memory 207088 kb
Host smart-84c51b59-0cad-43d8-a8cd-c5e9a2b94d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52116
9109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.521169109
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1666761588
Short name T2606
Test name
Test status
Simulation time 32555117 ps
CPU time 0.73 seconds
Started Jul 28 07:44:28 PM PDT 24
Finished Jul 28 07:44:29 PM PDT 24
Peak memory 207172 kb
Host smart-c1b6ac08-78d4-4d3b-a308-881f732fd1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16667
61588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1666761588
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2390928077
Short name T2224
Test name
Test status
Simulation time 917754755 ps
CPU time 2.42 seconds
Started Jul 28 07:44:13 PM PDT 24
Finished Jul 28 07:44:16 PM PDT 24
Peak memory 207384 kb
Host smart-f90508a8-78b3-4d60-8693-03877b9e2a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23909
28077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2390928077
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3078751007
Short name T2370
Test name
Test status
Simulation time 202019654 ps
CPU time 2.41 seconds
Started Jul 28 07:44:16 PM PDT 24
Finished Jul 28 07:44:18 PM PDT 24
Peak memory 207320 kb
Host smart-7d8908fb-04b5-4ef7-b581-b05473ba05b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30787
51007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3078751007
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.2551594132
Short name T1689
Test name
Test status
Simulation time 206679841 ps
CPU time 1.14 seconds
Started Jul 28 07:44:17 PM PDT 24
Finished Jul 28 07:44:18 PM PDT 24
Peak memory 215520 kb
Host smart-81ed8547-e4ef-4ef0-a6e2-557736326667
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2551594132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.2551594132
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1184137359
Short name T343
Test name
Test status
Simulation time 172663294 ps
CPU time 0.84 seconds
Started Jul 28 07:44:27 PM PDT 24
Finished Jul 28 07:44:28 PM PDT 24
Peak memory 207052 kb
Host smart-ce4ddc8c-af09-45b9-8035-07d873164f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11841
37359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1184137359
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1589939782
Short name T2694
Test name
Test status
Simulation time 174190952 ps
CPU time 0.88 seconds
Started Jul 28 07:44:41 PM PDT 24
Finished Jul 28 07:44:42 PM PDT 24
Peak memory 207140 kb
Host smart-4b0d836b-3be1-49b4-bdbd-60555e536344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15899
39782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1589939782
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1078407406
Short name T774
Test name
Test status
Simulation time 7145735063 ps
CPU time 70.52 seconds
Started Jul 28 07:44:15 PM PDT 24
Finished Jul 28 07:45:25 PM PDT 24
Peak memory 216980 kb
Host smart-160d9540-fe51-4d1e-a63f-a5d3c8ed41bc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1078407406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1078407406
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.653009273
Short name T1489
Test name
Test status
Simulation time 3849568579 ps
CPU time 41.55 seconds
Started Jul 28 07:44:19 PM PDT 24
Finished Jul 28 07:45:01 PM PDT 24
Peak memory 207324 kb
Host smart-5ee97548-f3f6-4c58-b571-576698dd47cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=653009273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.653009273
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.4180955796
Short name T1205
Test name
Test status
Simulation time 200471665 ps
CPU time 0.97 seconds
Started Jul 28 07:44:32 PM PDT 24
Finished Jul 28 07:44:33 PM PDT 24
Peak memory 207168 kb
Host smart-5453a625-0eda-4459-8b58-a3d0da974d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41809
55796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.4180955796
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1060981353
Short name T2626
Test name
Test status
Simulation time 23308274834 ps
CPU time 28.59 seconds
Started Jul 28 07:44:13 PM PDT 24
Finished Jul 28 07:44:42 PM PDT 24
Peak memory 207376 kb
Host smart-ab5c4ac8-cdf9-4ea0-88fa-0f7f39b681c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10609
81353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1060981353
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.41697725
Short name T906
Test name
Test status
Simulation time 3334170869 ps
CPU time 5.09 seconds
Started Jul 28 07:44:27 PM PDT 24
Finished Jul 28 07:44:33 PM PDT 24
Peak memory 207388 kb
Host smart-6ebe4214-db3a-4d69-adcd-203a3bc151ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41697
725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.41697725
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.1312149487
Short name T2324
Test name
Test status
Simulation time 6530798209 ps
CPU time 63.49 seconds
Started Jul 28 07:44:18 PM PDT 24
Finished Jul 28 07:45:22 PM PDT 24
Peak memory 217704 kb
Host smart-2a480a35-68ac-4626-9777-c6c0cf1767c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13121
49487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.1312149487
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.135770195
Short name T1045
Test name
Test status
Simulation time 4676840282 ps
CPU time 143.91 seconds
Started Jul 28 07:44:17 PM PDT 24
Finished Jul 28 07:46:41 PM PDT 24
Peak memory 215576 kb
Host smart-140a8188-c4b8-4eab-a7dd-6eabc4428ea4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=135770195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.135770195
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2804773478
Short name T1705
Test name
Test status
Simulation time 264464596 ps
CPU time 1.01 seconds
Started Jul 28 07:44:33 PM PDT 24
Finished Jul 28 07:44:34 PM PDT 24
Peak memory 207076 kb
Host smart-c62276dc-260b-48a3-94ec-65e192d1d25f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2804773478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2804773478
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2158683928
Short name T1343
Test name
Test status
Simulation time 211409159 ps
CPU time 0.97 seconds
Started Jul 28 07:44:19 PM PDT 24
Finished Jul 28 07:44:20 PM PDT 24
Peak memory 207076 kb
Host smart-504b79f8-04d6-4da5-b12e-f8fe77b0ae86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21586
83928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2158683928
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.2194096294
Short name T954
Test name
Test status
Simulation time 4692025180 ps
CPU time 139.96 seconds
Started Jul 28 07:44:18 PM PDT 24
Finished Jul 28 07:46:43 PM PDT 24
Peak memory 215536 kb
Host smart-c2434c52-37a0-4b51-b6f7-7ec243bd22ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21940
96294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.2194096294
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3603375483
Short name T1883
Test name
Test status
Simulation time 5540429944 ps
CPU time 44.96 seconds
Started Jul 28 07:44:17 PM PDT 24
Finished Jul 28 07:45:02 PM PDT 24
Peak memory 217128 kb
Host smart-b7a62e6b-ba51-4498-9f74-b0e34755d2cb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3603375483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3603375483
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3960284283
Short name T1262
Test name
Test status
Simulation time 240673259 ps
CPU time 0.93 seconds
Started Jul 28 07:44:17 PM PDT 24
Finished Jul 28 07:44:18 PM PDT 24
Peak memory 207152 kb
Host smart-de1966ad-9e46-4172-9278-526dbb63b8f7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3960284283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3960284283
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2059623637
Short name T1807
Test name
Test status
Simulation time 147916348 ps
CPU time 0.9 seconds
Started Jul 28 07:44:28 PM PDT 24
Finished Jul 28 07:44:34 PM PDT 24
Peak memory 207204 kb
Host smart-ecdbc2cd-c669-4423-be75-94ac9bec7046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20596
23637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2059623637
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3543523528
Short name T2602
Test name
Test status
Simulation time 214593875 ps
CPU time 1.01 seconds
Started Jul 28 07:44:28 PM PDT 24
Finished Jul 28 07:44:29 PM PDT 24
Peak memory 207132 kb
Host smart-9e26ad55-0c38-4ca4-80d4-c09ec350bfbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35435
23528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3543523528
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.626465909
Short name T1208
Test name
Test status
Simulation time 176775038 ps
CPU time 0.89 seconds
Started Jul 28 07:44:30 PM PDT 24
Finished Jul 28 07:44:31 PM PDT 24
Peak memory 207128 kb
Host smart-c063b755-2ba4-4d95-a058-037983b30abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62646
5909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.626465909
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3118581370
Short name T1422
Test name
Test status
Simulation time 193801049 ps
CPU time 0.89 seconds
Started Jul 28 07:44:21 PM PDT 24
Finished Jul 28 07:44:22 PM PDT 24
Peak memory 207072 kb
Host smart-1a7c7deb-2180-4f09-a529-32a6df53081c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31185
81370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3118581370
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1283458522
Short name T1467
Test name
Test status
Simulation time 156780622 ps
CPU time 0.83 seconds
Started Jul 28 07:44:39 PM PDT 24
Finished Jul 28 07:44:40 PM PDT 24
Peak memory 207168 kb
Host smart-ecb00859-c102-486c-8192-cb6540f292e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12834
58522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1283458522
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.201892614
Short name T2715
Test name
Test status
Simulation time 177042284 ps
CPU time 0.93 seconds
Started Jul 28 07:44:40 PM PDT 24
Finished Jul 28 07:44:41 PM PDT 24
Peak memory 207148 kb
Host smart-a918267a-4790-40e4-8699-20c386f8a45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20189
2614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.201892614
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.268074601
Short name T2608
Test name
Test status
Simulation time 274818879 ps
CPU time 1.03 seconds
Started Jul 28 07:44:31 PM PDT 24
Finished Jul 28 07:44:32 PM PDT 24
Peak memory 207092 kb
Host smart-0f74f598-1908-4252-a06a-d0e7947051b7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=268074601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.268074601
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.669001227
Short name T1813
Test name
Test status
Simulation time 154812574 ps
CPU time 0.82 seconds
Started Jul 28 07:44:30 PM PDT 24
Finished Jul 28 07:44:31 PM PDT 24
Peak memory 207044 kb
Host smart-ca692198-cc7c-46e3-925e-3bae94fd7374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66900
1227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.669001227
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1900307270
Short name T1130
Test name
Test status
Simulation time 86515103 ps
CPU time 0.75 seconds
Started Jul 28 07:44:28 PM PDT 24
Finished Jul 28 07:44:29 PM PDT 24
Peak memory 207168 kb
Host smart-c5a99147-94a1-4dfa-a7b2-7d6ebc3b11d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19003
07270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1900307270
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1513481921
Short name T2095
Test name
Test status
Simulation time 15730898856 ps
CPU time 39.45 seconds
Started Jul 28 07:44:34 PM PDT 24
Finished Jul 28 07:45:14 PM PDT 24
Peak memory 215592 kb
Host smart-3f2e2f8d-7d25-4a10-baaf-fafcfff89bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15134
81921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1513481921
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2615672257
Short name T1706
Test name
Test status
Simulation time 180016162 ps
CPU time 0.94 seconds
Started Jul 28 07:44:33 PM PDT 24
Finished Jul 28 07:44:34 PM PDT 24
Peak memory 207176 kb
Host smart-7744c646-216d-46e9-bc39-9d3bc77f12b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26156
72257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2615672257
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1819963350
Short name T1924
Test name
Test status
Simulation time 226218687 ps
CPU time 1.04 seconds
Started Jul 28 07:44:22 PM PDT 24
Finished Jul 28 07:44:23 PM PDT 24
Peak memory 207088 kb
Host smart-56403bf8-f715-47b7-96d9-b6980dccc7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18199
63350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1819963350
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.677431774
Short name T1619
Test name
Test status
Simulation time 201045429 ps
CPU time 0.93 seconds
Started Jul 28 07:44:31 PM PDT 24
Finished Jul 28 07:44:32 PM PDT 24
Peak memory 207028 kb
Host smart-e3180eef-f649-45bf-8f45-1e2ff96def0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67743
1774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.677431774
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.1336646557
Short name T1392
Test name
Test status
Simulation time 147525126 ps
CPU time 0.85 seconds
Started Jul 28 07:44:23 PM PDT 24
Finished Jul 28 07:44:23 PM PDT 24
Peak memory 207120 kb
Host smart-49d859e6-b0dd-4f0d-99d3-67150f6a00d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13366
46557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.1336646557
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.384126635
Short name T913
Test name
Test status
Simulation time 142089401 ps
CPU time 0.78 seconds
Started Jul 28 07:44:22 PM PDT 24
Finished Jul 28 07:44:23 PM PDT 24
Peak memory 207076 kb
Host smart-86aa4e33-2012-4da6-b7ae-e7b6f418bc9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38412
6635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.384126635
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.1386026100
Short name T1515
Test name
Test status
Simulation time 155808440 ps
CPU time 0.84 seconds
Started Jul 28 07:44:31 PM PDT 24
Finished Jul 28 07:44:32 PM PDT 24
Peak memory 207128 kb
Host smart-d7593c45-e0c6-4403-b232-d43952586dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13860
26100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1386026100
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.491192111
Short name T727
Test name
Test status
Simulation time 146164428 ps
CPU time 0.83 seconds
Started Jul 28 07:44:40 PM PDT 24
Finished Jul 28 07:44:41 PM PDT 24
Peak memory 206996 kb
Host smart-9a9dd231-f21c-4253-8671-be415361da83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49119
2111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.491192111
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2591969275
Short name T1778
Test name
Test status
Simulation time 222834965 ps
CPU time 0.97 seconds
Started Jul 28 07:44:42 PM PDT 24
Finished Jul 28 07:44:43 PM PDT 24
Peak memory 207176 kb
Host smart-7969c472-b71a-4638-8c8f-0802fb3791a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25919
69275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2591969275
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1744157681
Short name T2836
Test name
Test status
Simulation time 6157080060 ps
CPU time 50 seconds
Started Jul 28 07:44:27 PM PDT 24
Finished Jul 28 07:45:17 PM PDT 24
Peak memory 217104 kb
Host smart-ab93670f-6224-4a17-868b-66b847cb76da
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1744157681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1744157681
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.486966349
Short name T1250
Test name
Test status
Simulation time 160224733 ps
CPU time 0.9 seconds
Started Jul 28 07:44:20 PM PDT 24
Finished Jul 28 07:44:21 PM PDT 24
Peak memory 207096 kb
Host smart-78d7d155-01d6-4683-b2eb-fb14a172c5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48696
6349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.486966349
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3642394276
Short name T2369
Test name
Test status
Simulation time 160704973 ps
CPU time 0.82 seconds
Started Jul 28 07:44:42 PM PDT 24
Finished Jul 28 07:44:43 PM PDT 24
Peak memory 207208 kb
Host smart-1ca61df5-b53a-47a4-969e-fbadb0be0f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36423
94276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3642394276
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.3955631028
Short name T2156
Test name
Test status
Simulation time 595325021 ps
CPU time 1.75 seconds
Started Jul 28 07:44:22 PM PDT 24
Finished Jul 28 07:44:24 PM PDT 24
Peak memory 207056 kb
Host smart-c1506d8d-40ec-44bd-a1b8-24cb4a3837df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39556
31028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.3955631028
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.1883482072
Short name T1502
Test name
Test status
Simulation time 4669376110 ps
CPU time 39.62 seconds
Started Jul 28 07:44:29 PM PDT 24
Finished Jul 28 07:45:09 PM PDT 24
Peak memory 207316 kb
Host smart-4f425613-1eca-440d-8d0f-bab8fc147f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18834
82072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1883482072
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.2588513357
Short name T829
Test name
Test status
Simulation time 2518344321 ps
CPU time 21.53 seconds
Started Jul 28 07:44:13 PM PDT 24
Finished Jul 28 07:44:35 PM PDT 24
Peak memory 207376 kb
Host smart-9350ae08-ee03-4d27-99bc-d01461f7f3e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588513357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.2588513357
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.2996440333
Short name T888
Test name
Test status
Simulation time 41286829 ps
CPU time 0.65 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 207148 kb
Host smart-facceb41-d561-41f2-8828-487f366ccaf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2996440333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.2996440333
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1118630600
Short name T2833
Test name
Test status
Simulation time 3979855468 ps
CPU time 5.47 seconds
Started Jul 28 07:44:45 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 207356 kb
Host smart-01c0ac8c-3747-486b-b4c5-bde58d4dd1f0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118630600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.1118630600
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.3291472868
Short name T2247
Test name
Test status
Simulation time 13321717423 ps
CPU time 14.34 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:45:00 PM PDT 24
Peak memory 207396 kb
Host smart-41132866-d527-4f86-8265-67070c259683
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291472868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.3291472868
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1692628369
Short name T969
Test name
Test status
Simulation time 23366999588 ps
CPU time 33.84 seconds
Started Jul 28 07:44:40 PM PDT 24
Finished Jul 28 07:45:14 PM PDT 24
Peak memory 207284 kb
Host smart-db0db5ea-acc4-4382-bf01-7cd81a751343
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692628369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.1692628369
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.409201895
Short name T328
Test name
Test status
Simulation time 149276054 ps
CPU time 0.84 seconds
Started Jul 28 07:44:49 PM PDT 24
Finished Jul 28 07:44:50 PM PDT 24
Peak memory 207104 kb
Host smart-7361b2ea-0e67-4280-9867-8570f4a48cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40920
1895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.409201895
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.2092147310
Short name T872
Test name
Test status
Simulation time 143286806 ps
CPU time 0.84 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:44:48 PM PDT 24
Peak memory 207012 kb
Host smart-91c2da87-55b2-43a7-94c6-7d9fdb070806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20921
47310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.2092147310
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.1577319586
Short name T98
Test name
Test status
Simulation time 530161903 ps
CPU time 1.88 seconds
Started Jul 28 07:44:49 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 207152 kb
Host smart-faccb800-2c39-469a-920b-c4f560808bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15773
19586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.1577319586
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3707154724
Short name T2664
Test name
Test status
Simulation time 1310051485 ps
CPU time 3.05 seconds
Started Jul 28 07:44:34 PM PDT 24
Finished Jul 28 07:44:37 PM PDT 24
Peak memory 207320 kb
Host smart-50aede96-3688-45f9-9c98-038bc0f000f1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3707154724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3707154724
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.931033212
Short name T2536
Test name
Test status
Simulation time 13728925150 ps
CPU time 29.4 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:45:18 PM PDT 24
Peak memory 207392 kb
Host smart-f487b65d-4c0e-4ba0-802e-c7875f57e2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93103
3212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.931033212
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.1065412769
Short name T581
Test name
Test status
Simulation time 2956996464 ps
CPU time 21.84 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:45:08 PM PDT 24
Peak memory 207316 kb
Host smart-e0b62578-6878-4445-a1e7-1a561cec4ffa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065412769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.1065412769
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.57446645
Short name T1319
Test name
Test status
Simulation time 497199601 ps
CPU time 1.56 seconds
Started Jul 28 07:44:34 PM PDT 24
Finished Jul 28 07:44:35 PM PDT 24
Peak memory 207148 kb
Host smart-bf222659-174b-4182-b3bd-b8532f693976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57446
645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.57446645
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.2121674926
Short name T339
Test name
Test status
Simulation time 134969495 ps
CPU time 0.81 seconds
Started Jul 28 07:44:51 PM PDT 24
Finished Jul 28 07:44:52 PM PDT 24
Peak memory 207132 kb
Host smart-e3e017a3-31d4-4d23-a391-e19daa734045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21216
74926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.2121674926
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.2450460645
Short name T1298
Test name
Test status
Simulation time 60023256 ps
CPU time 0.76 seconds
Started Jul 28 07:44:49 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 207044 kb
Host smart-052b2236-76fb-4a4b-8724-c98e4148f2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24504
60645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2450460645
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1785683396
Short name T385
Test name
Test status
Simulation time 927773078 ps
CPU time 2.45 seconds
Started Jul 28 07:44:41 PM PDT 24
Finished Jul 28 07:44:44 PM PDT 24
Peak memory 207292 kb
Host smart-c55ae5b8-239b-476c-94bc-96ec217a161a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17856
83396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1785683396
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3811531510
Short name T1582
Test name
Test status
Simulation time 178715662 ps
CPU time 2.43 seconds
Started Jul 28 07:44:33 PM PDT 24
Finished Jul 28 07:44:36 PM PDT 24
Peak memory 207356 kb
Host smart-814aa353-40f8-4740-88fa-ef546d0d7366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38115
31510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3811531510
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.4051049461
Short name T695
Test name
Test status
Simulation time 195968459 ps
CPU time 1.01 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:44:47 PM PDT 24
Peak memory 207304 kb
Host smart-35fbdcda-b7ad-4ba4-9d5e-cf2cfc13444c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4051049461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.4051049461
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3427910985
Short name T615
Test name
Test status
Simulation time 145421947 ps
CPU time 0.81 seconds
Started Jul 28 07:44:43 PM PDT 24
Finished Jul 28 07:44:44 PM PDT 24
Peak memory 207144 kb
Host smart-c2c9563a-d5a3-4942-9b03-f7f19020f38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34279
10985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3427910985
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.850664806
Short name T485
Test name
Test status
Simulation time 232802695 ps
CPU time 0.98 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 207120 kb
Host smart-291964c7-4956-4dc7-a45a-0781e9abc4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85066
4806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.850664806
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.1601020529
Short name T2211
Test name
Test status
Simulation time 6751375419 ps
CPU time 200.17 seconds
Started Jul 28 07:44:35 PM PDT 24
Finished Jul 28 07:47:55 PM PDT 24
Peak memory 215636 kb
Host smart-707e0273-bfd1-4e3f-9739-33d1170a74c0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1601020529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.1601020529
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.3706738342
Short name T2642
Test name
Test status
Simulation time 12466811263 ps
CPU time 91.24 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:46:18 PM PDT 24
Peak memory 207332 kb
Host smart-bb60ec73-bc11-4d14-8b6f-71c255b91088
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3706738342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.3706738342
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.2236718505
Short name T1664
Test name
Test status
Simulation time 226449520 ps
CPU time 1.02 seconds
Started Jul 28 07:44:38 PM PDT 24
Finished Jul 28 07:44:39 PM PDT 24
Peak memory 207208 kb
Host smart-b8803258-2b82-4514-95b7-248803b9fb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22367
18505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2236718505
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1214108659
Short name T2491
Test name
Test status
Simulation time 23270061078 ps
CPU time 30.86 seconds
Started Jul 28 07:44:38 PM PDT 24
Finished Jul 28 07:45:09 PM PDT 24
Peak memory 207456 kb
Host smart-d82db0c0-38a9-407d-9647-476d173b1416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12141
08659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1214108659
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3689202641
Short name T2424
Test name
Test status
Simulation time 3299155114 ps
CPU time 4.74 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 207328 kb
Host smart-ae4134b5-d56e-4641-a45c-fdca032b4048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36892
02641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3689202641
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.180492478
Short name T945
Test name
Test status
Simulation time 5838132005 ps
CPU time 46.54 seconds
Started Jul 28 07:44:33 PM PDT 24
Finished Jul 28 07:45:20 PM PDT 24
Peak memory 217268 kb
Host smart-77e3bbf9-d9c9-477f-bc28-4db321fe22ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18049
2478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.180492478
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.3584471300
Short name T1848
Test name
Test status
Simulation time 4262261458 ps
CPU time 31.16 seconds
Started Jul 28 07:44:39 PM PDT 24
Finished Jul 28 07:45:10 PM PDT 24
Peak memory 216972 kb
Host smart-afb5c904-3e24-4a2e-9f9f-8c38c73e97aa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3584471300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.3584471300
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.344185490
Short name T338
Test name
Test status
Simulation time 235703411 ps
CPU time 1.03 seconds
Started Jul 28 07:44:45 PM PDT 24
Finished Jul 28 07:44:46 PM PDT 24
Peak memory 207324 kb
Host smart-bc296e59-1b94-4878-9a71-4916015b6993
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=344185490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.344185490
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.627156137
Short name T2801
Test name
Test status
Simulation time 215068624 ps
CPU time 0.96 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:44:48 PM PDT 24
Peak memory 207132 kb
Host smart-a2fec8c9-d984-43f3-a330-38920b699cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62715
6137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.627156137
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.1912523283
Short name T1108
Test name
Test status
Simulation time 3252844248 ps
CPU time 32.51 seconds
Started Jul 28 07:44:38 PM PDT 24
Finished Jul 28 07:45:10 PM PDT 24
Peak memory 216944 kb
Host smart-6fb08deb-06ef-4e2f-b1f4-5366097e7976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19125
23283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.1912523283
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.707414320
Short name T2400
Test name
Test status
Simulation time 7702669012 ps
CPU time 224.35 seconds
Started Jul 28 07:44:33 PM PDT 24
Finished Jul 28 07:48:17 PM PDT 24
Peak memory 215624 kb
Host smart-95123dcf-de6b-42f8-9776-40ae74fdbab9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=707414320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.707414320
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.1915052882
Short name T498
Test name
Test status
Simulation time 152997170 ps
CPU time 0.86 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:44:47 PM PDT 24
Peak memory 207140 kb
Host smart-0a09da18-8d30-4a4e-8e32-da2cafb9e025
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1915052882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1915052882
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2165831080
Short name T1159
Test name
Test status
Simulation time 160003041 ps
CPU time 0.86 seconds
Started Jul 28 07:44:44 PM PDT 24
Finished Jul 28 07:44:45 PM PDT 24
Peak memory 207204 kb
Host smart-08314131-23f9-441b-a4a4-637ea0d4f82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21658
31080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2165831080
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.4379214
Short name T114
Test name
Test status
Simulation time 209427309 ps
CPU time 0.91 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 207080 kb
Host smart-d203f9f2-7079-42d5-8c01-5722c343ad11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43792
14 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.4379214
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.3942930008
Short name T1583
Test name
Test status
Simulation time 191617189 ps
CPU time 0.97 seconds
Started Jul 28 07:44:42 PM PDT 24
Finished Jul 28 07:44:43 PM PDT 24
Peak memory 207164 kb
Host smart-482997cd-394a-41c1-b0d8-21ccb99a4256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39429
30008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.3942930008
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1144501379
Short name T1253
Test name
Test status
Simulation time 148786353 ps
CPU time 0.85 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:44:48 PM PDT 24
Peak memory 207064 kb
Host smart-4f9f5787-7b17-4f7c-a30e-89fbb473a579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11445
01379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1144501379
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.4205063674
Short name T1284
Test name
Test status
Simulation time 189160857 ps
CPU time 0.87 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:44:48 PM PDT 24
Peak memory 207088 kb
Host smart-af5b33c7-aeb1-4d50-84c8-5cc6e661da75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42050
63674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.4205063674
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1523925963
Short name T645
Test name
Test status
Simulation time 193459513 ps
CPU time 0.88 seconds
Started Jul 28 07:44:41 PM PDT 24
Finished Jul 28 07:44:42 PM PDT 24
Peak memory 207048 kb
Host smart-6d855671-ae70-4fc0-82d9-fc3f48395f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15239
25963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1523925963
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.1797719875
Short name T1274
Test name
Test status
Simulation time 235877378 ps
CPU time 1.04 seconds
Started Jul 28 07:44:41 PM PDT 24
Finished Jul 28 07:44:42 PM PDT 24
Peak memory 207184 kb
Host smart-b2c10251-d4e0-45ee-8b27-445d8dc4831a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1797719875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.1797719875
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3369315669
Short name T816
Test name
Test status
Simulation time 152978255 ps
CPU time 0.83 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 207032 kb
Host smart-e5b6889a-9082-4867-9525-11a2a5aee276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33693
15669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3369315669
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.923107882
Short name T359
Test name
Test status
Simulation time 57395248 ps
CPU time 0.73 seconds
Started Jul 28 07:44:36 PM PDT 24
Finished Jul 28 07:44:37 PM PDT 24
Peak memory 207024 kb
Host smart-65265798-312e-4a3e-81e1-05f097629117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92310
7882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.923107882
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.3857761637
Short name T1377
Test name
Test status
Simulation time 21486518460 ps
CPU time 53.09 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:45:42 PM PDT 24
Peak memory 223808 kb
Host smart-17e7289d-6430-48ab-8720-687ab53a280f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38577
61637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.3857761637
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1586183001
Short name T973
Test name
Test status
Simulation time 196183395 ps
CPU time 0.98 seconds
Started Jul 28 07:44:58 PM PDT 24
Finished Jul 28 07:44:59 PM PDT 24
Peak memory 207056 kb
Host smart-a724991c-c071-4bc9-861f-bd379b2b57c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15861
83001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1586183001
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.1352090502
Short name T1017
Test name
Test status
Simulation time 229674427 ps
CPU time 1 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:44:47 PM PDT 24
Peak memory 207144 kb
Host smart-4b1a076e-80b6-4a90-ace8-47f0bd1ac4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13520
90502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.1352090502
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.250411373
Short name T22
Test name
Test status
Simulation time 202625852 ps
CPU time 0.94 seconds
Started Jul 28 07:44:45 PM PDT 24
Finished Jul 28 07:44:46 PM PDT 24
Peak memory 207128 kb
Host smart-4c735d2d-6b13-4154-9a11-84313446b6cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25041
1373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.250411373
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.4047712935
Short name T905
Test name
Test status
Simulation time 205554109 ps
CPU time 0.98 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:02 PM PDT 24
Peak memory 207084 kb
Host smart-4bbbe7ae-dc61-4f09-b108-4764cd06f62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40477
12935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.4047712935
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1481002179
Short name T2645
Test name
Test status
Simulation time 146642973 ps
CPU time 0.84 seconds
Started Jul 28 07:44:54 PM PDT 24
Finished Jul 28 07:44:55 PM PDT 24
Peak memory 207072 kb
Host smart-21569272-2274-446c-bb51-f6642c765a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14810
02179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1481002179
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2300484414
Short name T275
Test name
Test status
Simulation time 161184982 ps
CPU time 0.86 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:44:48 PM PDT 24
Peak memory 207084 kb
Host smart-4a171369-2663-4dc8-b60c-38f56cb72a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23004
84414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2300484414
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2694835044
Short name T2512
Test name
Test status
Simulation time 184094469 ps
CPU time 0.89 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:44:47 PM PDT 24
Peak memory 207148 kb
Host smart-a8dea9f6-50a0-449f-a534-c635add9ed85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26948
35044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2694835044
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3361736115
Short name T1195
Test name
Test status
Simulation time 219954139 ps
CPU time 1.04 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:44:50 PM PDT 24
Peak memory 207116 kb
Host smart-59edf0a6-0e70-422f-a4e1-d0e20fd32d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33617
36115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3361736115
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.1401026788
Short name T1411
Test name
Test status
Simulation time 4551519020 ps
CPU time 38.69 seconds
Started Jul 28 07:44:59 PM PDT 24
Finished Jul 28 07:45:37 PM PDT 24
Peak memory 215488 kb
Host smart-589be49c-6dc5-4144-b3af-273fd8654d3f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1401026788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.1401026788
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1790910607
Short name T1041
Test name
Test status
Simulation time 146712326 ps
CPU time 0.82 seconds
Started Jul 28 07:44:42 PM PDT 24
Finished Jul 28 07:44:43 PM PDT 24
Peak memory 207148 kb
Host smart-ea1a78e3-b857-4654-a4f1-3cd1d81d61db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17909
10607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1790910607
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.98003885
Short name T1030
Test name
Test status
Simulation time 164285058 ps
CPU time 0.84 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 207128 kb
Host smart-a0faa5ab-f962-448d-b458-ca919f5d8b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98003
885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.98003885
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.3242273394
Short name T336
Test name
Test status
Simulation time 546995410 ps
CPU time 1.64 seconds
Started Jul 28 07:44:53 PM PDT 24
Finished Jul 28 07:44:55 PM PDT 24
Peak memory 207088 kb
Host smart-55d8cb10-158d-4237-94b1-61a3beb04af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32422
73394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.3242273394
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.2792349287
Short name T1126
Test name
Test status
Simulation time 3108305700 ps
CPU time 23.14 seconds
Started Jul 28 07:44:51 PM PDT 24
Finished Jul 28 07:45:14 PM PDT 24
Peak memory 216964 kb
Host smart-9c1b2ecc-830d-4a9e-b6ed-9420f3ddde8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27923
49287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.2792349287
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.1434019716
Short name T1660
Test name
Test status
Simulation time 2532310518 ps
CPU time 21.01 seconds
Started Jul 28 07:44:32 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 207484 kb
Host smart-c3da1ad6-9655-4a52-81a4-ab7f6a6df609
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434019716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.1434019716
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.2361748730
Short name T1125
Test name
Test status
Simulation time 33488733 ps
CPU time 0.69 seconds
Started Jul 28 07:44:59 PM PDT 24
Finished Jul 28 07:45:00 PM PDT 24
Peak memory 207324 kb
Host smart-59009499-633a-4304-be59-f8fe473dc85d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2361748730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.2361748730
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3326015643
Short name T1346
Test name
Test status
Simulation time 3932444966 ps
CPU time 6.13 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207384 kb
Host smart-f362b49e-09fb-48f7-ae02-5d75e677fa7b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326015643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.3326015643
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.2237641588
Short name T2414
Test name
Test status
Simulation time 13383589255 ps
CPU time 18.74 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:45:07 PM PDT 24
Peak memory 207312 kb
Host smart-2a20995b-fcd4-4e2c-b0ba-b0833bdab7e4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237641588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2237641588
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.938849304
Short name T1803
Test name
Test status
Simulation time 23409766562 ps
CPU time 28.08 seconds
Started Jul 28 07:44:51 PM PDT 24
Finished Jul 28 07:45:20 PM PDT 24
Peak memory 207312 kb
Host smart-54ab6ade-0e1c-4908-a351-05df32fbdcaf
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938849304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_ao
n_wake_resume.938849304
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2028455169
Short name T523
Test name
Test status
Simulation time 177462122 ps
CPU time 0.93 seconds
Started Jul 28 07:44:54 PM PDT 24
Finished Jul 28 07:44:55 PM PDT 24
Peak memory 207064 kb
Host smart-454e5422-f97d-4158-936d-a210084de1d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20284
55169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2028455169
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.2860713769
Short name T2249
Test name
Test status
Simulation time 169011803 ps
CPU time 0.9 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 207088 kb
Host smart-799fccf9-7587-400f-a073-358d62b42fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28607
13769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.2860713769
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.368400309
Short name T2268
Test name
Test status
Simulation time 284223400 ps
CPU time 1.12 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:44:48 PM PDT 24
Peak memory 207152 kb
Host smart-ca79011f-12f5-421b-b56f-13b0dea3e37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36840
0309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.368400309
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.4266678988
Short name T84
Test name
Test status
Simulation time 480780078 ps
CPU time 1.56 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:52 PM PDT 24
Peak memory 207156 kb
Host smart-20a6c4bc-6373-4883-b4d7-57ff3ee788ac
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4266678988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.4266678988
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.3185532211
Short name T92
Test name
Test status
Simulation time 15228875577 ps
CPU time 32.84 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:45:20 PM PDT 24
Peak memory 207360 kb
Host smart-9e704f2c-ba1c-4596-ac50-3c614353185a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31855
32211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.3185532211
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.1683264222
Short name T1508
Test name
Test status
Simulation time 1543062628 ps
CPU time 9.67 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:44:56 PM PDT 24
Peak memory 207228 kb
Host smart-3ddb4306-c317-4167-8af1-411e403885bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683264222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.1683264222
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.1863635779
Short name T1312
Test name
Test status
Simulation time 454855838 ps
CPU time 1.53 seconds
Started Jul 28 07:45:03 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207064 kb
Host smart-1d82f9dd-719b-4dda-bee6-e80fbb167602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18636
35779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.1863635779
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3383098433
Short name T2073
Test name
Test status
Simulation time 141474475 ps
CPU time 0.89 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 207048 kb
Host smart-b2bfe5af-7f01-4e0d-a5f1-26f3e1eba93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33830
98433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3383098433
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3089425482
Short name T1212
Test name
Test status
Simulation time 31330772 ps
CPU time 0.67 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:44:48 PM PDT 24
Peak memory 207036 kb
Host smart-2b83e692-3b27-42d6-94ff-d4bb4612b934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30894
25482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3089425482
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.92051006
Short name T2205
Test name
Test status
Simulation time 801537132 ps
CPU time 2.2 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:52 PM PDT 24
Peak memory 207332 kb
Host smart-95892fe2-d547-4838-b272-23da10dcbcb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92051
006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.92051006
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.467123785
Short name T178
Test name
Test status
Simulation time 282666593 ps
CPU time 1.4 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:54 PM PDT 24
Peak memory 207260 kb
Host smart-fe9b84cf-de33-45c2-915c-d146c4fc2688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46712
3785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.467123785
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.1546665073
Short name T477
Test name
Test status
Simulation time 247409827 ps
CPU time 1.2 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 215516 kb
Host smart-54824b75-93c9-4ccb-b87b-0502721614cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1546665073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.1546665073
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.4184448199
Short name T2443
Test name
Test status
Simulation time 163126776 ps
CPU time 0.86 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 207104 kb
Host smart-d59f6af2-acf2-45a2-a953-b5cc899fa74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41844
48199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.4184448199
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2800687936
Short name T1368
Test name
Test status
Simulation time 159364669 ps
CPU time 0.87 seconds
Started Jul 28 07:44:49 PM PDT 24
Finished Jul 28 07:44:50 PM PDT 24
Peak memory 207060 kb
Host smart-0442aced-47db-47bc-9905-2e05a8962eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28006
87936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2800687936
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.2339805503
Short name T2081
Test name
Test status
Simulation time 4042764567 ps
CPU time 116.52 seconds
Started Jul 28 07:44:49 PM PDT 24
Finished Jul 28 07:46:46 PM PDT 24
Peak memory 215628 kb
Host smart-6255c7ff-2c9a-4e4c-9ac8-d41dacee5acd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2339805503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.2339805503
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.1930635697
Short name T2079
Test name
Test status
Simulation time 6509013826 ps
CPU time 72.33 seconds
Started Jul 28 07:44:59 PM PDT 24
Finished Jul 28 07:46:11 PM PDT 24
Peak memory 207320 kb
Host smart-89fb3ee8-e8b9-44ae-bbd9-3a79e2a89958
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1930635697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.1930635697
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.3733929516
Short name T2698
Test name
Test status
Simulation time 201704381 ps
CPU time 0.91 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:44:47 PM PDT 24
Peak memory 207120 kb
Host smart-f279d27c-6bbb-41a6-b379-93242c9bd1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37339
29516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.3733929516
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.2598379561
Short name T377
Test name
Test status
Simulation time 23315378388 ps
CPU time 28.05 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:45:18 PM PDT 24
Peak memory 207376 kb
Host smart-91fb4ca3-ed42-445b-9d8e-6e722e10a116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25983
79561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2598379561
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2870750464
Short name T2101
Test name
Test status
Simulation time 3298184941 ps
CPU time 5.6 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:56 PM PDT 24
Peak memory 207288 kb
Host smart-cd1a4885-b208-4d86-9b9e-870c4254c9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28707
50464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2870750464
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.2713908728
Short name T154
Test name
Test status
Simulation time 6581485451 ps
CPU time 63.41 seconds
Started Jul 28 07:44:40 PM PDT 24
Finished Jul 28 07:45:43 PM PDT 24
Peak memory 217256 kb
Host smart-0b90295f-0d75-47bc-ae6a-aa6cf808f3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27139
08728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.2713908728
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.2424341157
Short name T2533
Test name
Test status
Simulation time 3455249912 ps
CPU time 99.62 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:46:30 PM PDT 24
Peak memory 215544 kb
Host smart-a53f336f-18b3-4e68-ad88-d8e4901923b1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2424341157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.2424341157
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.331765939
Short name T2713
Test name
Test status
Simulation time 247798569 ps
CPU time 0.99 seconds
Started Jul 28 07:44:53 PM PDT 24
Finished Jul 28 07:44:54 PM PDT 24
Peak memory 207144 kb
Host smart-e9efc3cb-d14f-4d3c-9b5f-1832fe0965d7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=331765939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.331765939
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1306004787
Short name T790
Test name
Test status
Simulation time 200188323 ps
CPU time 0.97 seconds
Started Jul 28 07:44:54 PM PDT 24
Finished Jul 28 07:44:55 PM PDT 24
Peak memory 207156 kb
Host smart-801c3453-3b2b-4b0d-85e2-48f24c8b3aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13060
04787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1306004787
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.17188230
Short name T909
Test name
Test status
Simulation time 6074766888 ps
CPU time 62.59 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:45:53 PM PDT 24
Peak memory 217232 kb
Host smart-1c4fe956-db84-4fd7-b308-f5b4429c7175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17188
230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.17188230
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.938686892
Short name T1076
Test name
Test status
Simulation time 4709237071 ps
CPU time 139.57 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:47:07 PM PDT 24
Peak memory 215588 kb
Host smart-92fc46ed-f7d6-4ea1-bc8e-6860906bec8f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=938686892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.938686892
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.3366023756
Short name T347
Test name
Test status
Simulation time 198975247 ps
CPU time 0.9 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:44:48 PM PDT 24
Peak memory 207208 kb
Host smart-5504fc0c-2770-4242-bda7-d77b877b5de7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3366023756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.3366023756
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3823399457
Short name T2515
Test name
Test status
Simulation time 196501781 ps
CPU time 0.88 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:44:47 PM PDT 24
Peak memory 207108 kb
Host smart-061b59df-50c0-4b57-850d-bc7b49a89bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38233
99457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3823399457
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.541010518
Short name T131
Test name
Test status
Simulation time 215225209 ps
CPU time 1.11 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:44:58 PM PDT 24
Peak memory 207292 kb
Host smart-fbf563bc-6884-423e-8366-55d7d62dbd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54101
0518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.541010518
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.62759447
Short name T1901
Test name
Test status
Simulation time 207046498 ps
CPU time 1.01 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 207044 kb
Host smart-3ada3bb5-08cd-4d88-97ec-b43fe2e8b07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62759
447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.62759447
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2021898882
Short name T1092
Test name
Test status
Simulation time 262291822 ps
CPU time 0.99 seconds
Started Jul 28 07:44:49 PM PDT 24
Finished Jul 28 07:44:50 PM PDT 24
Peak memory 207152 kb
Host smart-1ac09f4c-e1d0-415a-9833-a5403798e553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20218
98882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2021898882
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3929217447
Short name T1321
Test name
Test status
Simulation time 172420641 ps
CPU time 0.85 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 207204 kb
Host smart-cfad345b-e473-4d13-9edb-9b3ef37c65bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39292
17447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3929217447
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1173310594
Short name T1833
Test name
Test status
Simulation time 149449564 ps
CPU time 0.82 seconds
Started Jul 28 07:44:51 PM PDT 24
Finished Jul 28 07:44:52 PM PDT 24
Peak memory 207112 kb
Host smart-e92d49c3-a0a0-4e86-9e80-d3b0a3d4cb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11733
10594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1173310594
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.880702615
Short name T2100
Test name
Test status
Simulation time 244011813 ps
CPU time 1.05 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 207288 kb
Host smart-b83da622-5199-4f58-b8ee-c290db34a11d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=880702615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.880702615
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1335426053
Short name T489
Test name
Test status
Simulation time 157526285 ps
CPU time 0.85 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:02 PM PDT 24
Peak memory 207264 kb
Host smart-64d18bca-bd4f-4c25-9118-9249d62df21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13354
26053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1335426053
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.15429194
Short name T2401
Test name
Test status
Simulation time 41076794 ps
CPU time 0.75 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:44:58 PM PDT 24
Peak memory 207084 kb
Host smart-b858b0bf-6081-4c36-8d76-ce31d00405ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15429
194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.15429194
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1914972578
Short name T1559
Test name
Test status
Simulation time 23455897233 ps
CPU time 59.07 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:45:51 PM PDT 24
Peak memory 215584 kb
Host smart-c7c07f32-872d-4225-8c94-6760bdd14b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19149
72578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1914972578
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.4033599556
Short name T1295
Test name
Test status
Simulation time 184278125 ps
CPU time 0.96 seconds
Started Jul 28 07:44:44 PM PDT 24
Finished Jul 28 07:44:45 PM PDT 24
Peak memory 207104 kb
Host smart-c0fe8c9a-c137-4ba3-895e-4c3a40792748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40335
99556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.4033599556
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3340855487
Short name T1916
Test name
Test status
Simulation time 187693604 ps
CPU time 0.89 seconds
Started Jul 28 07:45:07 PM PDT 24
Finished Jul 28 07:45:08 PM PDT 24
Peak memory 207132 kb
Host smart-c888b853-5a7e-4f19-8830-25966f4c3068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33408
55487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3340855487
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.3439749712
Short name T2666
Test name
Test status
Simulation time 240443720 ps
CPU time 1 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 207108 kb
Host smart-7905d486-1ad8-4967-ab0c-4f9e7913b6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34397
49712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.3439749712
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.2049791052
Short name T981
Test name
Test status
Simulation time 166509717 ps
CPU time 0.92 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:44:48 PM PDT 24
Peak memory 207156 kb
Host smart-229273f3-9037-4190-90ce-738e923249f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20497
91052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.2049791052
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.2219864053
Short name T2318
Test name
Test status
Simulation time 141417956 ps
CPU time 0.85 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 207128 kb
Host smart-a4b5a980-cd2f-45b7-86ac-0bced4903e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22198
64053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2219864053
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.962921722
Short name T1047
Test name
Test status
Simulation time 150407399 ps
CPU time 0.83 seconds
Started Jul 28 07:45:05 PM PDT 24
Finished Jul 28 07:45:06 PM PDT 24
Peak memory 207048 kb
Host smart-7a13089f-ae01-414a-b0f0-a62f4c9aef30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96292
1722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.962921722
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2667056256
Short name T601
Test name
Test status
Simulation time 182411444 ps
CPU time 0.83 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 207124 kb
Host smart-7744e75a-6399-44c0-a60a-88475b58ffba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26670
56256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2667056256
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.390735129
Short name T2563
Test name
Test status
Simulation time 227680762 ps
CPU time 0.97 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 207184 kb
Host smart-c6394d81-6722-4f1b-886d-2b8634353dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39073
5129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.390735129
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.2242906836
Short name T2658
Test name
Test status
Simulation time 3245294900 ps
CPU time 33.77 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:45:21 PM PDT 24
Peak memory 217196 kb
Host smart-77ee4f98-f679-4fe8-873b-dca8a74f3315
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2242906836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.2242906836
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3928571077
Short name T2232
Test name
Test status
Simulation time 179910759 ps
CPU time 0.9 seconds
Started Jul 28 07:44:59 PM PDT 24
Finished Jul 28 07:45:00 PM PDT 24
Peak memory 207296 kb
Host smart-b685f8b7-0fd1-4ad7-a23c-a1545d429b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39285
71077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3928571077
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2502025177
Short name T1165
Test name
Test status
Simulation time 197315423 ps
CPU time 0.92 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:02 PM PDT 24
Peak memory 207056 kb
Host smart-7b2c9e0b-00a3-4615-82b6-cbb20fb50fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25020
25177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2502025177
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2287917765
Short name T2705
Test name
Test status
Simulation time 1199145461 ps
CPU time 2.75 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 207272 kb
Host smart-4f575b99-08f8-471d-9c89-597638c8291c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22879
17765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2287917765
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.3943180959
Short name T2245
Test name
Test status
Simulation time 4684108768 ps
CPU time 35.28 seconds
Started Jul 28 07:45:05 PM PDT 24
Finished Jul 28 07:45:40 PM PDT 24
Peak memory 207272 kb
Host smart-9ed71a0a-2b96-4d6b-99e7-0ed204e07822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39431
80959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.3943180959
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.3480699539
Short name T2841
Test name
Test status
Simulation time 1047715487 ps
CPU time 8.69 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207288 kb
Host smart-d174b3e1-0e38-420b-a6f9-f231a3e31368
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480699539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_hos
t_handshake.3480699539
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.42256274
Short name T2402
Test name
Test status
Simulation time 39492795 ps
CPU time 0.67 seconds
Started Jul 28 07:44:51 PM PDT 24
Finished Jul 28 07:44:52 PM PDT 24
Peak memory 207192 kb
Host smart-94d07547-e212-45ef-88f5-a48b2ea20e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=42256274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.42256274
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.3276618689
Short name T1309
Test name
Test status
Simulation time 3560930687 ps
CPU time 5.37 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:45:01 PM PDT 24
Peak memory 207344 kb
Host smart-c9d2deb4-1650-4c54-9719-62cf7c2e830d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276618689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.3276618689
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.286248639
Short name T2217
Test name
Test status
Simulation time 13365807753 ps
CPU time 16.86 seconds
Started Jul 28 07:44:41 PM PDT 24
Finished Jul 28 07:44:58 PM PDT 24
Peak memory 207320 kb
Host smart-43e31b6e-2c42-4afa-9b0c-40ee15aa322f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=286248639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.286248639
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3945310219
Short name T643
Test name
Test status
Simulation time 23398812967 ps
CPU time 27.33 seconds
Started Jul 28 07:44:55 PM PDT 24
Finished Jul 28 07:45:22 PM PDT 24
Peak memory 207336 kb
Host smart-0f014e59-3ed4-4fa4-9d8d-21729bcb5338
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945310219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.3945310219
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2772366740
Short name T2594
Test name
Test status
Simulation time 152725369 ps
CPU time 0.89 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:44:50 PM PDT 24
Peak memory 207060 kb
Host smart-78e060da-1f1d-4777-bb2e-e920bafbb16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27723
66740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2772366740
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.2166036362
Short name T1476
Test name
Test status
Simulation time 171352072 ps
CPU time 0.84 seconds
Started Jul 28 07:44:54 PM PDT 24
Finished Jul 28 07:44:55 PM PDT 24
Peak memory 206996 kb
Host smart-d0141cd9-91dc-45c5-b538-00eb01d1fdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21660
36362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.2166036362
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.1541559409
Short name T834
Test name
Test status
Simulation time 428618324 ps
CPU time 1.69 seconds
Started Jul 28 07:45:03 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207304 kb
Host smart-b77dc4bc-6e55-472d-b1b4-270ef15a76e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15415
59409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.1541559409
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2975099196
Short name T748
Test name
Test status
Simulation time 327845186 ps
CPU time 1.11 seconds
Started Jul 28 07:44:53 PM PDT 24
Finished Jul 28 07:44:54 PM PDT 24
Peak memory 207172 kb
Host smart-4b8a3bb1-dfc4-40ed-b54b-c748dec23d79
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2975099196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2975099196
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.3394426290
Short name T1140
Test name
Test status
Simulation time 10063209097 ps
CPU time 24.23 seconds
Started Jul 28 07:44:58 PM PDT 24
Finished Jul 28 07:45:22 PM PDT 24
Peak memory 207408 kb
Host smart-e800daed-6fb7-4894-bd60-bbade8d3ac75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33944
26290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.3394426290
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.2600286412
Short name T2295
Test name
Test status
Simulation time 294960188 ps
CPU time 4.48 seconds
Started Jul 28 07:44:51 PM PDT 24
Finished Jul 28 07:44:56 PM PDT 24
Peak memory 207320 kb
Host smart-fcf59e73-d8de-4e16-96be-cf8f25672c3e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600286412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.2600286412
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.709028562
Short name T690
Test name
Test status
Simulation time 498444036 ps
CPU time 1.66 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:04 PM PDT 24
Peak memory 207024 kb
Host smart-68143eef-2294-4865-8793-d5f86a71470f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70902
8562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.709028562
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2942355632
Short name T35
Test name
Test status
Simulation time 213480151 ps
CPU time 0.92 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 207120 kb
Host smart-8436a602-f941-4bda-8a8a-c4d9e73192e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29423
55632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2942355632
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2193465378
Short name T1247
Test name
Test status
Simulation time 39406594 ps
CPU time 0.7 seconds
Started Jul 28 07:44:49 PM PDT 24
Finished Jul 28 07:44:50 PM PDT 24
Peak memory 207060 kb
Host smart-eeccf3e1-8e06-4cff-abb4-40e30dbd025e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21934
65378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2193465378
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1501760969
Short name T1827
Test name
Test status
Simulation time 883295172 ps
CPU time 2.66 seconds
Started Jul 28 07:45:07 PM PDT 24
Finished Jul 28 07:45:10 PM PDT 24
Peak memory 207368 kb
Host smart-00029aa6-a030-402d-8171-66abaabf4ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15017
60969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1501760969
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3857857361
Short name T1738
Test name
Test status
Simulation time 193155241 ps
CPU time 2.36 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:59 PM PDT 24
Peak memory 207404 kb
Host smart-82665b43-a9aa-4cb7-8543-a49c3928f9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38578
57361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3857857361
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2779642736
Short name T1375
Test name
Test status
Simulation time 163919047 ps
CPU time 0.89 seconds
Started Jul 28 07:44:53 PM PDT 24
Finished Jul 28 07:44:54 PM PDT 24
Peak memory 207048 kb
Host smart-4d1100e2-ed61-4bcf-9bfd-047699890236
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2779642736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2779642736
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2754765017
Short name T337
Test name
Test status
Simulation time 152204084 ps
CPU time 0.82 seconds
Started Jul 28 07:44:54 PM PDT 24
Finished Jul 28 07:44:55 PM PDT 24
Peak memory 207076 kb
Host smart-e2e617e2-6fe6-4696-841e-2034853aebac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27547
65017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2754765017
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.981405940
Short name T1472
Test name
Test status
Simulation time 228297081 ps
CPU time 1 seconds
Started Jul 28 07:45:06 PM PDT 24
Finished Jul 28 07:45:07 PM PDT 24
Peak memory 207044 kb
Host smart-b02774d9-fd51-4149-b1ae-b3fa176eed04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98140
5940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.981405940
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.335388361
Short name T2830
Test name
Test status
Simulation time 9498530805 ps
CPU time 101.03 seconds
Started Jul 28 07:44:45 PM PDT 24
Finished Jul 28 07:46:26 PM PDT 24
Peak memory 217268 kb
Host smart-4d13297a-806f-4c51-a02e-e29dfd11c19d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=335388361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.335388361
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.1667816417
Short name T540
Test name
Test status
Simulation time 3762630788 ps
CPU time 27.05 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:45:16 PM PDT 24
Peak memory 207388 kb
Host smart-34f7e378-fcbb-47d9-af6d-9e56d8851a66
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1667816417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.1667816417
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2503492311
Short name T373
Test name
Test status
Simulation time 227390520 ps
CPU time 0.96 seconds
Started Jul 28 07:44:51 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 207208 kb
Host smart-959b5056-9004-42b2-9a52-7aa28d81f955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25034
92311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2503492311
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.3282585589
Short name T1246
Test name
Test status
Simulation time 23289384129 ps
CPU time 26.74 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:45:17 PM PDT 24
Peak memory 207404 kb
Host smart-1d98e8c6-6b1a-4be8-ad94-0682b2f64751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32825
85589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.3282585589
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.2688617720
Short name T2067
Test name
Test status
Simulation time 3330977334 ps
CPU time 4.79 seconds
Started Jul 28 07:44:49 PM PDT 24
Finished Jul 28 07:44:54 PM PDT 24
Peak memory 207288 kb
Host smart-c538aeb9-2c67-469d-bef1-fe642d7ab324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26886
17720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2688617720
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.2749827123
Short name T433
Test name
Test status
Simulation time 5872536816 ps
CPU time 42.38 seconds
Started Jul 28 07:44:58 PM PDT 24
Finished Jul 28 07:45:41 PM PDT 24
Peak memory 223856 kb
Host smart-38dd0762-8ef5-4818-935a-eefa85129707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27498
27123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.2749827123
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3075254181
Short name T1074
Test name
Test status
Simulation time 3492581775 ps
CPU time 26.13 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:45:14 PM PDT 24
Peak memory 216736 kb
Host smart-e059ef0e-ddd8-45fe-9685-764d9338f9f5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3075254181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3075254181
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3218233857
Short name T2769
Test name
Test status
Simulation time 237893535 ps
CPU time 0.96 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:44:58 PM PDT 24
Peak memory 207200 kb
Host smart-13cf2a85-6b6c-4d8b-8af0-372455a42bb7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3218233857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3218233857
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.695285017
Short name T1775
Test name
Test status
Simulation time 220920439 ps
CPU time 0.95 seconds
Started Jul 28 07:44:47 PM PDT 24
Finished Jul 28 07:44:48 PM PDT 24
Peak memory 207100 kb
Host smart-fe1672c3-8088-4047-92c9-51f41e4cec99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69528
5017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.695285017
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.636716996
Short name T2773
Test name
Test status
Simulation time 4634727012 ps
CPU time 35.46 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:45:33 PM PDT 24
Peak memory 217292 kb
Host smart-ecb88b92-e429-4ee1-b0b8-5ae3e42e26c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63671
6996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.636716996
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.798929640
Short name T900
Test name
Test status
Simulation time 5161019376 ps
CPU time 37.47 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:39 PM PDT 24
Peak memory 207392 kb
Host smart-5530960e-41a6-4847-af58-ddd3bbd3ad5e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=798929640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.798929640
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.715686930
Short name T545
Test name
Test status
Simulation time 145648693 ps
CPU time 0.91 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:02 PM PDT 24
Peak memory 207128 kb
Host smart-3e892de0-ebb6-43bb-b5fb-82e3f9ab8b68
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=715686930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.715686930
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.995984322
Short name T2180
Test name
Test status
Simulation time 164692347 ps
CPU time 0.88 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 207148 kb
Host smart-974cfb1a-b8e9-4f43-b90c-5b6f051060c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99598
4322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.995984322
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.247321548
Short name T2233
Test name
Test status
Simulation time 227814882 ps
CPU time 0.94 seconds
Started Jul 28 07:44:46 PM PDT 24
Finished Jul 28 07:44:47 PM PDT 24
Peak memory 207140 kb
Host smart-81b6696a-ad11-4872-957d-b098c0efa8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24732
1548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.247321548
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3005593021
Short name T2121
Test name
Test status
Simulation time 184594815 ps
CPU time 0.89 seconds
Started Jul 28 07:44:51 PM PDT 24
Finished Jul 28 07:44:52 PM PDT 24
Peak memory 207112 kb
Host smart-aec5b3ab-37c0-469e-bd85-13995db2feea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30055
93021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3005593021
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1780756898
Short name T1603
Test name
Test status
Simulation time 159104970 ps
CPU time 0.93 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 207136 kb
Host smart-77420e6f-63b4-413b-aaf1-c6fd168c9d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17807
56898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1780756898
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3891866668
Short name T2104
Test name
Test status
Simulation time 265174349 ps
CPU time 1 seconds
Started Jul 28 07:45:04 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207144 kb
Host smart-9179d8a2-d635-4c27-bf72-42d3f2df8dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38918
66668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3891866668
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2601308326
Short name T173
Test name
Test status
Simulation time 158540315 ps
CPU time 0.89 seconds
Started Jul 28 07:44:59 PM PDT 24
Finished Jul 28 07:45:00 PM PDT 24
Peak memory 207156 kb
Host smart-e7d09d6d-4645-4e78-9f66-bd76a2ba08f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26013
08326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2601308326
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.889667194
Short name T2804
Test name
Test status
Simulation time 213471304 ps
CPU time 0.97 seconds
Started Jul 28 07:44:51 PM PDT 24
Finished Jul 28 07:44:54 PM PDT 24
Peak memory 207152 kb
Host smart-fbd75d20-a4fd-4192-9eb8-b153e05b2b5a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=889667194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.889667194
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2952126610
Short name T2850
Test name
Test status
Simulation time 153624918 ps
CPU time 0.79 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 207032 kb
Host smart-9890644a-c4d5-4802-a67d-70010d5e2311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29521
26610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2952126610
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3273632530
Short name T1652
Test name
Test status
Simulation time 42388340 ps
CPU time 0.7 seconds
Started Jul 28 07:44:53 PM PDT 24
Finished Jul 28 07:44:54 PM PDT 24
Peak memory 207048 kb
Host smart-7e4e5aff-65c5-478a-b7ff-9cea31a7a0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32736
32530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3273632530
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2976054898
Short name T235
Test name
Test status
Simulation time 6056814832 ps
CPU time 15.43 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:16 PM PDT 24
Peak memory 215556 kb
Host smart-a159d6c8-a1fe-4c65-b677-f4bf1b5d5c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29760
54898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2976054898
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3886849867
Short name T2644
Test name
Test status
Simulation time 150971231 ps
CPU time 0.88 seconds
Started Jul 28 07:44:56 PM PDT 24
Finished Jul 28 07:44:58 PM PDT 24
Peak memory 207144 kb
Host smart-027440e5-7575-480a-aa15-68731041c266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38868
49867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3886849867
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1127871691
Short name T1362
Test name
Test status
Simulation time 231568411 ps
CPU time 1.04 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207156 kb
Host smart-02d330de-525f-4af1-828e-924ec299199c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11278
71691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1127871691
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.831132821
Short name T955
Test name
Test status
Simulation time 220420012 ps
CPU time 0.95 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:52 PM PDT 24
Peak memory 207104 kb
Host smart-4c0df0a3-4f27-4024-ba99-5e8a2a9524b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83113
2821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.831132821
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.165054780
Short name T326
Test name
Test status
Simulation time 163954946 ps
CPU time 0.85 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 207036 kb
Host smart-bb7a7fe7-ff31-4269-bf15-9ec5a7ae32ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16505
4780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.165054780
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.957954731
Short name T729
Test name
Test status
Simulation time 171720165 ps
CPU time 0.85 seconds
Started Jul 28 07:44:49 PM PDT 24
Finished Jul 28 07:44:50 PM PDT 24
Peak memory 207084 kb
Host smart-464ba984-b2ba-49e1-913a-a7a5e7499002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95795
4731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.957954731
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2569693517
Short name T2167
Test name
Test status
Simulation time 152618032 ps
CPU time 0.84 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:44:49 PM PDT 24
Peak memory 207176 kb
Host smart-0497fb2a-ac3d-4425-bdf8-e98663948fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25696
93517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2569693517
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3236095742
Short name T268
Test name
Test status
Simulation time 151088310 ps
CPU time 0.83 seconds
Started Jul 28 07:45:03 PM PDT 24
Finished Jul 28 07:45:04 PM PDT 24
Peak memory 207124 kb
Host smart-02f08fa9-f976-47b0-a223-d71069d99b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32360
95742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3236095742
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2956399218
Short name T1900
Test name
Test status
Simulation time 238569282 ps
CPU time 1.01 seconds
Started Jul 28 07:44:51 PM PDT 24
Finished Jul 28 07:44:52 PM PDT 24
Peak memory 207128 kb
Host smart-07ac3fee-6b73-4ea2-afed-7e2daa28dff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29563
99218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2956399218
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3001511360
Short name T1538
Test name
Test status
Simulation time 160552900 ps
CPU time 0.85 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207152 kb
Host smart-d87417ea-08c0-4d87-aebf-c340a98c1f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30015
11360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3001511360
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3240403228
Short name T2413
Test name
Test status
Simulation time 282704385 ps
CPU time 1.05 seconds
Started Jul 28 07:44:55 PM PDT 24
Finished Jul 28 07:44:56 PM PDT 24
Peak memory 207152 kb
Host smart-82836bd8-489a-4116-962c-5b3fb084ef63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32404
03228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3240403228
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.668580040
Short name T1935
Test name
Test status
Simulation time 1207625614 ps
CPU time 2.76 seconds
Started Jul 28 07:44:54 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207344 kb
Host smart-83886d2a-c5b7-433d-8ecc-d80ae789bd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66858
0040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.668580040
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.2079989110
Short name T2584
Test name
Test status
Simulation time 4954319400 ps
CPU time 147.26 seconds
Started Jul 28 07:45:04 PM PDT 24
Finished Jul 28 07:47:31 PM PDT 24
Peak memory 215632 kb
Host smart-2987e605-0fa3-4231-bc3c-ef53d73c5f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20799
89110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.2079989110
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.396404747
Short name T1903
Test name
Test status
Simulation time 2915951261 ps
CPU time 25.58 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:45:16 PM PDT 24
Peak memory 207444 kb
Host smart-b555c0f3-7e46-4dd1-8bf9-b80ef108baa5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396404747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_host
_handshake.396404747
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.936757300
Short name T1432
Test name
Test status
Simulation time 28066019 ps
CPU time 0.64 seconds
Started Jul 28 07:45:05 PM PDT 24
Finished Jul 28 07:45:06 PM PDT 24
Peak memory 207184 kb
Host smart-bf8cc5ed-902e-4a59-a834-b5f6f118ab6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=936757300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.936757300
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3530351232
Short name T1930
Test name
Test status
Simulation time 3647336464 ps
CPU time 5.27 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:07 PM PDT 24
Peak memory 207376 kb
Host smart-d13b0a76-f2cd-45f3-8e64-07f7103bd1b3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530351232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.3530351232
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2780074518
Short name T1173
Test name
Test status
Simulation time 13394640141 ps
CPU time 15.49 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:45:04 PM PDT 24
Peak memory 207384 kb
Host smart-346930a0-b278-4633-8d3d-44caa8ebf482
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780074518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2780074518
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.2156488888
Short name T556
Test name
Test status
Simulation time 23441945617 ps
CPU time 33.17 seconds
Started Jul 28 07:45:08 PM PDT 24
Finished Jul 28 07:45:41 PM PDT 24
Peak memory 207352 kb
Host smart-fb8eac11-c2d8-4444-b845-550eabbf44ea
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156488888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.2156488888
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.258047298
Short name T2132
Test name
Test status
Simulation time 220202878 ps
CPU time 0.91 seconds
Started Jul 28 07:45:03 PM PDT 24
Finished Jul 28 07:45:04 PM PDT 24
Peak memory 207156 kb
Host smart-65d0ea7e-bc61-4b9d-906f-d0b5ab8aeae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25804
7298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.258047298
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.129490946
Short name T78
Test name
Test status
Simulation time 217427197 ps
CPU time 0.88 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:04 PM PDT 24
Peak memory 207084 kb
Host smart-05b7ac70-8a8e-4da6-8f0b-e36282202ab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12949
0946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.129490946
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3510113142
Short name T1694
Test name
Test status
Simulation time 324820765 ps
CPU time 1.23 seconds
Started Jul 28 07:44:53 PM PDT 24
Finished Jul 28 07:44:54 PM PDT 24
Peak memory 207020 kb
Host smart-83f28782-a16c-48b8-aac4-83afd92342cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35101
13142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3510113142
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3970768211
Short name T2554
Test name
Test status
Simulation time 331445075 ps
CPU time 1.13 seconds
Started Jul 28 07:44:51 PM PDT 24
Finished Jul 28 07:44:52 PM PDT 24
Peak memory 207164 kb
Host smart-fe245869-c46e-4e79-94e7-75a2f37a8888
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3970768211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3970768211
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2972374042
Short name T1015
Test name
Test status
Simulation time 22414996381 ps
CPU time 47.55 seconds
Started Jul 28 07:44:53 PM PDT 24
Finished Jul 28 07:45:40 PM PDT 24
Peak memory 207368 kb
Host smart-dfc1edc1-f235-4ba6-bf07-c9be1d0c962d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29723
74042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2972374042
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.2545663566
Short name T937
Test name
Test status
Simulation time 1650658873 ps
CPU time 41.21 seconds
Started Jul 28 07:44:55 PM PDT 24
Finished Jul 28 07:45:36 PM PDT 24
Peak memory 207340 kb
Host smart-38f39151-9e05-4b3f-9642-bb908867123b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545663566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.2545663566
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.4077698288
Short name T1418
Test name
Test status
Simulation time 306692287 ps
CPU time 1.18 seconds
Started Jul 28 07:45:03 PM PDT 24
Finished Jul 28 07:45:04 PM PDT 24
Peak memory 207136 kb
Host smart-290b9a3e-1636-4939-82e7-626157fd7eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40776
98288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.4077698288
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.667867220
Short name T1425
Test name
Test status
Simulation time 139318100 ps
CPU time 0.81 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 206992 kb
Host smart-53dc566e-9e65-4b46-ae61-92d13f1f863b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66786
7220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.667867220
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2323182059
Short name T310
Test name
Test status
Simulation time 34655429 ps
CPU time 0.7 seconds
Started Jul 28 07:45:00 PM PDT 24
Finished Jul 28 07:45:01 PM PDT 24
Peak memory 207080 kb
Host smart-83772efe-b798-4489-9708-b289ae734746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23231
82059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2323182059
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3511392061
Short name T1798
Test name
Test status
Simulation time 814149937 ps
CPU time 2.1 seconds
Started Jul 28 07:44:48 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 207440 kb
Host smart-f30b1f42-ae7e-416b-adcc-60dbcccd333c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35113
92061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3511392061
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3501623065
Short name T1003
Test name
Test status
Simulation time 211119289 ps
CPU time 1.57 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 207208 kb
Host smart-e108c094-69a9-4dbe-9a86-ff0eaeb6ab18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35016
23065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3501623065
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3229977210
Short name T511
Test name
Test status
Simulation time 239942408 ps
CPU time 1.18 seconds
Started Jul 28 07:44:54 PM PDT 24
Finished Jul 28 07:44:55 PM PDT 24
Peak memory 215432 kb
Host smart-c4ae71d4-9f1a-486e-a520-6a3212fd1c8f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3229977210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3229977210
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1480904921
Short name T1454
Test name
Test status
Simulation time 160915563 ps
CPU time 0.92 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 207020 kb
Host smart-b298084c-4ea8-4e4c-b09d-35b06ccdfb12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14809
04921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1480904921
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2531408459
Short name T588
Test name
Test status
Simulation time 219080676 ps
CPU time 0.98 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:53 PM PDT 24
Peak memory 207048 kb
Host smart-833d5b75-6052-4d3e-904e-5f33e2b693d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25314
08459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2531408459
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.2091118745
Short name T1799
Test name
Test status
Simulation time 8859474471 ps
CPU time 91.2 seconds
Started Jul 28 07:45:03 PM PDT 24
Finished Jul 28 07:46:35 PM PDT 24
Peak memory 215540 kb
Host smart-72a2489f-3e9c-46ec-ac9c-bd532eb91519
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2091118745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.2091118745
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.1944550174
Short name T2482
Test name
Test status
Simulation time 8815028385 ps
CPU time 55.55 seconds
Started Jul 28 07:44:53 PM PDT 24
Finished Jul 28 07:45:51 PM PDT 24
Peak memory 207376 kb
Host smart-36866da6-b5d7-4725-aceb-233ba85984c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1944550174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.1944550174
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.4051805696
Short name T2719
Test name
Test status
Simulation time 251875286 ps
CPU time 0.99 seconds
Started Jul 28 07:44:53 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207152 kb
Host smart-a4acc295-e561-4b82-8b36-bf7ec80faecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40518
05696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.4051805696
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.644740145
Short name T2747
Test name
Test status
Simulation time 23295534637 ps
CPU time 27.76 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:45:25 PM PDT 24
Peak memory 207368 kb
Host smart-cc650fd2-8ae1-4e3d-9dc6-8ca618468abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64474
0145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.644740145
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.1115713141
Short name T1427
Test name
Test status
Simulation time 3307438811 ps
CPU time 5.36 seconds
Started Jul 28 07:45:10 PM PDT 24
Finished Jul 28 07:45:15 PM PDT 24
Peak memory 207392 kb
Host smart-9fa3a93f-8265-43cd-bbd8-ce294d2dd88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11157
13141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1115713141
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.1334047807
Short name T423
Test name
Test status
Simulation time 7524341733 ps
CPU time 55.09 seconds
Started Jul 28 07:44:55 PM PDT 24
Finished Jul 28 07:45:52 PM PDT 24
Peak memory 223748 kb
Host smart-445ee1e4-5e2f-4bb3-afbc-da6eba8c788b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13340
47807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.1334047807
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.4182945927
Short name T1449
Test name
Test status
Simulation time 7843308561 ps
CPU time 82.37 seconds
Started Jul 28 07:45:08 PM PDT 24
Finished Jul 28 07:46:31 PM PDT 24
Peak memory 207576 kb
Host smart-2d2c36a9-aeba-4854-b8d8-cc30c08fa5fa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4182945927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.4182945927
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3799157985
Short name T583
Test name
Test status
Simulation time 258957185 ps
CPU time 1.03 seconds
Started Jul 28 07:44:49 PM PDT 24
Finished Jul 28 07:44:50 PM PDT 24
Peak memory 207176 kb
Host smart-ac88dd36-10e6-4235-b5fb-82774a5b222a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3799157985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3799157985
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.745956384
Short name T2055
Test name
Test status
Simulation time 189596407 ps
CPU time 0.97 seconds
Started Jul 28 07:44:59 PM PDT 24
Finished Jul 28 07:45:00 PM PDT 24
Peak memory 207148 kb
Host smart-6f88c070-db0b-48e2-b4a4-898d59b902d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74595
6384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.745956384
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.2937767128
Short name T1415
Test name
Test status
Simulation time 3490676845 ps
CPU time 102.61 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:46:32 PM PDT 24
Peak memory 215640 kb
Host smart-9dd21b9e-e9f3-4dd7-9201-3ef86a7684da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29377
67128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.2937767128
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.608159649
Short name T2159
Test name
Test status
Simulation time 7014009354 ps
CPU time 66.35 seconds
Started Jul 28 07:45:09 PM PDT 24
Finished Jul 28 07:46:15 PM PDT 24
Peak memory 207360 kb
Host smart-96204059-d90c-47d3-92dc-e3dcea5684b8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=608159649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.608159649
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.234862104
Short name T2717
Test name
Test status
Simulation time 146747085 ps
CPU time 0.82 seconds
Started Jul 28 07:44:56 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207096 kb
Host smart-f7a6925d-cddc-43ec-ad5c-453fc78c6f6b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=234862104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.234862104
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1616290158
Short name T1682
Test name
Test status
Simulation time 169368595 ps
CPU time 0.89 seconds
Started Jul 28 07:44:56 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207148 kb
Host smart-9b8567e3-a787-457e-b4d1-32d242396964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16162
90158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1616290158
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2272291454
Short name T141
Test name
Test status
Simulation time 199065919 ps
CPU time 0.91 seconds
Started Jul 28 07:45:10 PM PDT 24
Finished Jul 28 07:45:11 PM PDT 24
Peak memory 207128 kb
Host smart-fa0cc51f-0a6c-4212-b0fe-bf7aa40aa387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22722
91454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2272291454
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2499018726
Short name T1000
Test name
Test status
Simulation time 158484725 ps
CPU time 0.92 seconds
Started Jul 28 07:44:53 PM PDT 24
Finished Jul 28 07:44:54 PM PDT 24
Peak memory 207112 kb
Host smart-36aaba3e-fc91-4c40-bb93-45fe952edd08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24990
18726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2499018726
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1384667398
Short name T1379
Test name
Test status
Simulation time 157404167 ps
CPU time 0.87 seconds
Started Jul 28 07:45:04 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207048 kb
Host smart-cfb51cfe-dd5d-4922-b77a-e26c318fdf05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13846
67398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1384667398
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.95351204
Short name T1647
Test name
Test status
Simulation time 243864505 ps
CPU time 1 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 207152 kb
Host smart-22b76944-07f7-4a15-b4e3-d635097ffddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95351
204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.95351204
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3942537440
Short name T1765
Test name
Test status
Simulation time 182319486 ps
CPU time 0.87 seconds
Started Jul 28 07:44:56 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207100 kb
Host smart-59824c77-cd8c-4536-a205-e4eb9c8f1522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39425
37440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3942537440
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.1006317076
Short name T409
Test name
Test status
Simulation time 219943496 ps
CPU time 1.03 seconds
Started Jul 28 07:44:55 PM PDT 24
Finished Jul 28 07:44:56 PM PDT 24
Peak memory 207192 kb
Host smart-e5bcd64d-cb0e-4176-affd-c73f87f649e0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1006317076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.1006317076
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2256401377
Short name T1662
Test name
Test status
Simulation time 167622782 ps
CPU time 0.85 seconds
Started Jul 28 07:44:53 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207132 kb
Host smart-e16e5e0e-3be6-4369-8184-d899d385c4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22564
01377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2256401377
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1050530127
Short name T446
Test name
Test status
Simulation time 113063280 ps
CPU time 0.85 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 207092 kb
Host smart-5271b441-000e-4c67-bfdc-c8746693f821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10505
30127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1050530127
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.380672253
Short name T262
Test name
Test status
Simulation time 8236185008 ps
CPU time 19.03 seconds
Started Jul 28 07:44:55 PM PDT 24
Finished Jul 28 07:45:15 PM PDT 24
Peak memory 215636 kb
Host smart-cfd633a5-9dae-47d6-85e0-c346a75384c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38067
2253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.380672253
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.758418961
Short name T2347
Test name
Test status
Simulation time 143502675 ps
CPU time 0.82 seconds
Started Jul 28 07:45:06 PM PDT 24
Finished Jul 28 07:45:07 PM PDT 24
Peak memory 207104 kb
Host smart-aee4e5fb-5f8c-43b8-8878-e45b064df1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75841
8961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.758418961
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.991492624
Short name T2034
Test name
Test status
Simulation time 202588623 ps
CPU time 0.92 seconds
Started Jul 28 07:44:54 PM PDT 24
Finished Jul 28 07:44:55 PM PDT 24
Peak memory 207148 kb
Host smart-7db8e6b3-27c5-4e64-8104-caefc4078828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99149
2624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.991492624
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.2836880460
Short name T2139
Test name
Test status
Simulation time 244037796 ps
CPU time 0.94 seconds
Started Jul 28 07:45:07 PM PDT 24
Finished Jul 28 07:45:08 PM PDT 24
Peak memory 207140 kb
Host smart-cd773647-6bef-4c62-9f1c-afa65c597ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28368
80460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.2836880460
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.3514980710
Short name T1684
Test name
Test status
Simulation time 178084212 ps
CPU time 0.91 seconds
Started Jul 28 07:44:55 PM PDT 24
Finished Jul 28 07:44:56 PM PDT 24
Peak memory 207172 kb
Host smart-1319b9e4-bd7f-4fe5-82cd-7d42d1f75270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35149
80710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3514980710
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2959527769
Short name T1318
Test name
Test status
Simulation time 164904013 ps
CPU time 0.87 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 207144 kb
Host smart-5ae8cb57-3d84-4480-9ffc-ad2550df57cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29595
27769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2959527769
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3627054392
Short name T1726
Test name
Test status
Simulation time 156899947 ps
CPU time 0.82 seconds
Started Jul 28 07:45:04 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207136 kb
Host smart-53e8e7a8-f65c-46c0-bb2d-96804e8d5280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36270
54392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3627054392
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.248785869
Short name T2802
Test name
Test status
Simulation time 155690528 ps
CPU time 0.85 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:52 PM PDT 24
Peak memory 207104 kb
Host smart-d8415c23-2bee-41d0-820b-9fe27f0b49bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24878
5869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.248785869
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.520309457
Short name T942
Test name
Test status
Simulation time 203223349 ps
CPU time 0.97 seconds
Started Jul 28 07:45:00 PM PDT 24
Finished Jul 28 07:45:01 PM PDT 24
Peak memory 207104 kb
Host smart-fde0302e-4c29-48bb-b9e5-27c04cdc70f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52030
9457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.520309457
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.3848995420
Short name T2091
Test name
Test status
Simulation time 3634665364 ps
CPU time 107.44 seconds
Started Jul 28 07:45:05 PM PDT 24
Finished Jul 28 07:46:53 PM PDT 24
Peak memory 215576 kb
Host smart-aa9f996d-e067-4741-a890-49b3403ed462
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3848995420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.3848995420
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3304011910
Short name T2194
Test name
Test status
Simulation time 188968523 ps
CPU time 0.96 seconds
Started Jul 28 07:44:49 PM PDT 24
Finished Jul 28 07:44:51 PM PDT 24
Peak memory 207172 kb
Host smart-110412c6-2749-48de-a6d9-91693a529b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33040
11910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3304011910
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2108208467
Short name T2378
Test name
Test status
Simulation time 158538010 ps
CPU time 0.85 seconds
Started Jul 28 07:44:56 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207104 kb
Host smart-a158ad27-fa07-4f28-9d47-b551af474714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21082
08467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2108208467
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.226251041
Short name T1973
Test name
Test status
Simulation time 702329037 ps
CPU time 1.83 seconds
Started Jul 28 07:44:58 PM PDT 24
Finished Jul 28 07:45:00 PM PDT 24
Peak memory 207052 kb
Host smart-18b24e3b-bfe9-4199-89ec-1e0a4455c174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22625
1041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.226251041
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.3106514438
Short name T1795
Test name
Test status
Simulation time 4072997825 ps
CPU time 120.65 seconds
Started Jul 28 07:45:05 PM PDT 24
Finished Jul 28 07:47:06 PM PDT 24
Peak memory 215588 kb
Host smart-7631789b-8ce7-48b7-b07f-30ad0990900f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31065
14438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3106514438
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.3673810837
Short name T1383
Test name
Test status
Simulation time 355285668 ps
CPU time 4.75 seconds
Started Jul 28 07:44:50 PM PDT 24
Finished Jul 28 07:44:56 PM PDT 24
Peak memory 207324 kb
Host smart-79c4a181-f6e6-45ae-8aca-a654e62ee0ab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673810837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos
t_handshake.3673810837
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.2537266275
Short name T1772
Test name
Test status
Simulation time 69029521 ps
CPU time 0.67 seconds
Started Jul 28 07:45:00 PM PDT 24
Finished Jul 28 07:45:01 PM PDT 24
Peak memory 207140 kb
Host smart-f7b5ce77-daeb-42a9-ba82-8724333cbf75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2537266275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.2537266275
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3500040418
Short name T2831
Test name
Test status
Simulation time 4287416386 ps
CPU time 7.29 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207380 kb
Host smart-5a08431d-02e3-46fa-b1b6-de7b1c24b68b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500040418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_disconnect.3500040418
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1666961976
Short name T2800
Test name
Test status
Simulation time 13396542703 ps
CPU time 15.62 seconds
Started Jul 28 07:45:07 PM PDT 24
Finished Jul 28 07:45:22 PM PDT 24
Peak memory 207432 kb
Host smart-6e6fbb36-b2e2-4f34-8605-9d17a5e24362
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666961976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1666961976
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1770166238
Short name T2098
Test name
Test status
Simulation time 23336290584 ps
CPU time 29.3 seconds
Started Jul 28 07:45:16 PM PDT 24
Finished Jul 28 07:45:50 PM PDT 24
Peak memory 207364 kb
Host smart-da09b442-2f85-46f3-b609-c050269ec701
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770166238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.1770166238
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3555996925
Short name T847
Test name
Test status
Simulation time 163207162 ps
CPU time 0.86 seconds
Started Jul 28 07:45:13 PM PDT 24
Finished Jul 28 07:45:14 PM PDT 24
Peak memory 207120 kb
Host smart-97d31536-8f18-4693-b2d4-3c2fed30fcf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35559
96925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3555996925
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.947115256
Short name T736
Test name
Test status
Simulation time 150561620 ps
CPU time 0.86 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:02 PM PDT 24
Peak memory 206996 kb
Host smart-ae82792c-5f87-4f42-910e-8e1bf0cf8ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94711
5256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.947115256
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.2404514568
Short name T886
Test name
Test status
Simulation time 164848148 ps
CPU time 0.92 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:44:58 PM PDT 24
Peak memory 207032 kb
Host smart-0e91fadd-ccfb-464e-88aa-dc618967a76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24045
14568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.2404514568
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.316948979
Short name T2393
Test name
Test status
Simulation time 424521559 ps
CPU time 1.35 seconds
Started Jul 28 07:45:09 PM PDT 24
Finished Jul 28 07:45:10 PM PDT 24
Peak memory 207040 kb
Host smart-68dc83c3-4749-412c-9371-448f67404910
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=316948979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.316948979
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.4221718420
Short name T1771
Test name
Test status
Simulation time 17970581268 ps
CPU time 36.84 seconds
Started Jul 28 07:45:10 PM PDT 24
Finished Jul 28 07:45:47 PM PDT 24
Peak memory 207352 kb
Host smart-999c2ee7-4e28-48b9-9307-e3b9a16e5792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42217
18420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.4221718420
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.3125743749
Short name T2090
Test name
Test status
Simulation time 909588524 ps
CPU time 5.79 seconds
Started Jul 28 07:45:07 PM PDT 24
Finished Jul 28 07:45:13 PM PDT 24
Peak memory 207292 kb
Host smart-2dfde5dc-dc43-47a0-906d-35c34b4a7a99
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125743749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.3125743749
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.2516167901
Short name T266
Test name
Test status
Simulation time 395624390 ps
CPU time 1.38 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:44:59 PM PDT 24
Peak memory 207076 kb
Host smart-0cb75757-2cc9-45f8-9f4e-c12655199c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25161
67901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.2516167901
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.777845257
Short name T2662
Test name
Test status
Simulation time 167374809 ps
CPU time 0.9 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:44:58 PM PDT 24
Peak memory 206992 kb
Host smart-3ffaeca7-812e-4ffd-940b-e1be05adf60f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77784
5257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.777845257
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.930505744
Short name T2605
Test name
Test status
Simulation time 33826148 ps
CPU time 0.68 seconds
Started Jul 28 07:44:51 PM PDT 24
Finished Jul 28 07:44:52 PM PDT 24
Peak memory 207076 kb
Host smart-0f481a91-263a-4780-bc7f-2b8484dc3172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93050
5744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.930505744
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.188360481
Short name T1320
Test name
Test status
Simulation time 848099388 ps
CPU time 2.09 seconds
Started Jul 28 07:44:56 PM PDT 24
Finished Jul 28 07:44:59 PM PDT 24
Peak memory 207424 kb
Host smart-691bfd79-afe8-48e8-8a99-1a5a3f137b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18836
0481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.188360481
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.187355953
Short name T1987
Test name
Test status
Simulation time 170227678 ps
CPU time 1.34 seconds
Started Jul 28 07:44:56 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207268 kb
Host smart-d67425a4-63b6-4d73-bb1b-c80d1a0f6f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18735
5953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.187355953
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2349406719
Short name T2420
Test name
Test status
Simulation time 221893295 ps
CPU time 1.14 seconds
Started Jul 28 07:44:56 PM PDT 24
Finished Jul 28 07:44:58 PM PDT 24
Peak memory 207372 kb
Host smart-c201d530-93e4-434c-ab41-2e8e99b31108
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2349406719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2349406719
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.911916093
Short name T618
Test name
Test status
Simulation time 200130093 ps
CPU time 0.88 seconds
Started Jul 28 07:45:00 PM PDT 24
Finished Jul 28 07:45:01 PM PDT 24
Peak memory 206996 kb
Host smart-5523c93a-60bd-4193-b474-9d6851d72533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91191
6093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.911916093
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.466712467
Short name T2262
Test name
Test status
Simulation time 248703605 ps
CPU time 1.01 seconds
Started Jul 28 07:45:13 PM PDT 24
Finished Jul 28 07:45:15 PM PDT 24
Peak memory 207096 kb
Host smart-77df6990-e700-4f59-a814-05f123138543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46671
2467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.466712467
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.1149440440
Short name T2223
Test name
Test status
Simulation time 5073377069 ps
CPU time 147.75 seconds
Started Jul 28 07:44:58 PM PDT 24
Finished Jul 28 07:47:26 PM PDT 24
Peak memory 215608 kb
Host smart-98c92aa0-d0eb-4fe2-a456-c36312ceef29
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1149440440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.1149440440
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.706741553
Short name T432
Test name
Test status
Simulation time 5489194103 ps
CPU time 64.83 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:46:07 PM PDT 24
Peak memory 207348 kb
Host smart-9e44a3f4-1b04-4bc6-9a12-2186971999a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=706741553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.706741553
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.2122415088
Short name T911
Test name
Test status
Simulation time 215768655 ps
CPU time 0.97 seconds
Started Jul 28 07:44:56 PM PDT 24
Finished Jul 28 07:44:57 PM PDT 24
Peak memory 207056 kb
Host smart-410ba01f-12d6-4c95-a351-81a71c62adcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21224
15088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.2122415088
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.758222916
Short name T2755
Test name
Test status
Simulation time 23302533028 ps
CPU time 34.09 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:45:26 PM PDT 24
Peak memory 207380 kb
Host smart-fb678cd5-4d32-444e-8233-a2d0690e0eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75822
2916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.758222916
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.2021871732
Short name T1611
Test name
Test status
Simulation time 3322149554 ps
CPU time 4.75 seconds
Started Jul 28 07:44:52 PM PDT 24
Finished Jul 28 07:45:01 PM PDT 24
Peak memory 207452 kb
Host smart-9cb43eb7-223d-4208-9c6f-d2997d2a85a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20218
71732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2021871732
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3276313038
Short name T1451
Test name
Test status
Simulation time 6968197718 ps
CPU time 71.6 seconds
Started Jul 28 07:44:54 PM PDT 24
Finished Jul 28 07:46:06 PM PDT 24
Peak memory 217424 kb
Host smart-5aa19ded-07a0-4c39-8b9c-5568e4f4de1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32763
13038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3276313038
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.3427352664
Short name T2635
Test name
Test status
Simulation time 3633372738 ps
CPU time 26.49 seconds
Started Jul 28 07:45:14 PM PDT 24
Finished Jul 28 07:45:41 PM PDT 24
Peak memory 215508 kb
Host smart-02813554-6182-4fe0-a32a-fd139a891b4a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3427352664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.3427352664
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3787997569
Short name T1590
Test name
Test status
Simulation time 307742620 ps
CPU time 1.12 seconds
Started Jul 28 07:45:14 PM PDT 24
Finished Jul 28 07:45:15 PM PDT 24
Peak memory 207100 kb
Host smart-3cf960c7-0502-4c27-bbf3-353f81b833fa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3787997569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3787997569
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1055695901
Short name T2480
Test name
Test status
Simulation time 186912013 ps
CPU time 1.02 seconds
Started Jul 28 07:44:59 PM PDT 24
Finished Jul 28 07:45:00 PM PDT 24
Peak memory 207108 kb
Host smart-91dc39f0-190c-41c3-918b-190f11a396f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10556
95901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1055695901
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.2130960312
Short name T1679
Test name
Test status
Simulation time 3929046129 ps
CPU time 31.04 seconds
Started Jul 28 07:45:03 PM PDT 24
Finished Jul 28 07:45:34 PM PDT 24
Peak memory 216740 kb
Host smart-141e6962-8ef3-4996-a7a9-af411fa818a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21309
60312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.2130960312
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.2937518196
Short name T826
Test name
Test status
Simulation time 5371366460 ps
CPU time 55.51 seconds
Started Jul 28 07:44:56 PM PDT 24
Finished Jul 28 07:45:51 PM PDT 24
Peak memory 216664 kb
Host smart-57aaf2b8-cdbf-4489-8fe3-97da7ee35e25
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2937518196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.2937518196
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2340084806
Short name T459
Test name
Test status
Simulation time 183913427 ps
CPU time 0.9 seconds
Started Jul 28 07:45:12 PM PDT 24
Finished Jul 28 07:45:13 PM PDT 24
Peak memory 207036 kb
Host smart-307024db-3d47-44b4-85cf-d875aa5a0a49
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2340084806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2340084806
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1013613002
Short name T358
Test name
Test status
Simulation time 142072188 ps
CPU time 0.8 seconds
Started Jul 28 07:44:59 PM PDT 24
Finished Jul 28 07:44:59 PM PDT 24
Peak memory 207124 kb
Host smart-bddd6f1c-5d4c-435a-9860-7ab4e386a92e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10136
13002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1013613002
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.233382104
Short name T2120
Test name
Test status
Simulation time 229504657 ps
CPU time 0.9 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 207100 kb
Host smart-5c89b704-5f5e-4eb2-9991-1c8577b32d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23338
2104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.233382104
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3983140266
Short name T1543
Test name
Test status
Simulation time 188284446 ps
CPU time 0.91 seconds
Started Jul 28 07:45:04 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207264 kb
Host smart-4d626e39-efbe-4ff6-a138-e7c6e1709838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39831
40266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3983140266
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1577544160
Short name T1317
Test name
Test status
Simulation time 176476685 ps
CPU time 0.94 seconds
Started Jul 28 07:45:04 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207136 kb
Host smart-c6e42ac9-f7ad-4dcb-b9bc-ebe70dbea5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15775
44160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1577544160
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1200143124
Short name T2466
Test name
Test status
Simulation time 178671543 ps
CPU time 0.89 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 207080 kb
Host smart-3ea31059-ba73-4b6c-8db4-e88dd90beff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12001
43124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1200143124
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2888887250
Short name T1537
Test name
Test status
Simulation time 159680147 ps
CPU time 0.95 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:44:58 PM PDT 24
Peak memory 207148 kb
Host smart-3d1aaefe-462a-4112-88ce-915efa0edf05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28888
87250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2888887250
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.3425368330
Short name T1843
Test name
Test status
Simulation time 220443011 ps
CPU time 1.03 seconds
Started Jul 28 07:45:04 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207056 kb
Host smart-b09be803-e3bd-4fe7-8af2-60fd307790af
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3425368330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.3425368330
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1287277618
Short name T462
Test name
Test status
Simulation time 175729422 ps
CPU time 0.89 seconds
Started Jul 28 07:44:59 PM PDT 24
Finished Jul 28 07:45:00 PM PDT 24
Peak memory 207048 kb
Host smart-86b7a8a6-9a90-4c75-bb29-f4ceb8c432bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12872
77618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1287277618
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2416316460
Short name T1636
Test name
Test status
Simulation time 59960938 ps
CPU time 0.73 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 207096 kb
Host smart-dd1ea151-bb66-456d-9d53-b565d8c2bf70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24163
16460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2416316460
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3846613953
Short name T208
Test name
Test status
Simulation time 6831578626 ps
CPU time 16.48 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:45:13 PM PDT 24
Peak memory 223760 kb
Host smart-1a20bc00-ece5-4b5c-bfae-c6b2405c4cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38466
13953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3846613953
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1854012116
Short name T553
Test name
Test status
Simulation time 181051880 ps
CPU time 0.92 seconds
Started Jul 28 07:45:00 PM PDT 24
Finished Jul 28 07:45:01 PM PDT 24
Peak memory 207152 kb
Host smart-2f3a4785-d47f-4857-9bcb-58a5722ad93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18540
12116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1854012116
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.422618885
Short name T735
Test name
Test status
Simulation time 174796939 ps
CPU time 0.9 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:44:58 PM PDT 24
Peak memory 207068 kb
Host smart-5204331d-0afd-4dd5-bfab-3235a89e5759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42261
8885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.422618885
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.4267488037
Short name T1359
Test name
Test status
Simulation time 187209303 ps
CPU time 0.95 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 207112 kb
Host smart-3dfafc1e-83b2-456f-9bac-3877c3cf1e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42674
88037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.4267488037
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.3127177186
Short name T2058
Test name
Test status
Simulation time 192555749 ps
CPU time 0.98 seconds
Started Jul 28 07:45:07 PM PDT 24
Finished Jul 28 07:45:08 PM PDT 24
Peak memory 207156 kb
Host smart-58bb853b-4691-46d4-bba5-764e079f6c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31271
77186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.3127177186
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1508141284
Short name T806
Test name
Test status
Simulation time 199334420 ps
CPU time 0.92 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:44:58 PM PDT 24
Peak memory 207088 kb
Host smart-eb788738-c309-45ce-a8c9-cb2d51853480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15081
41284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1508141284
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1006026333
Short name T1134
Test name
Test status
Simulation time 152823875 ps
CPU time 0.93 seconds
Started Jul 28 07:44:58 PM PDT 24
Finished Jul 28 07:44:59 PM PDT 24
Peak memory 207132 kb
Host smart-1f43aadc-97a9-41c6-8d97-8bec22c1265d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10060
26333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1006026333
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.913500281
Short name T2822
Test name
Test status
Simulation time 153969145 ps
CPU time 0.87 seconds
Started Jul 28 07:44:57 PM PDT 24
Finished Jul 28 07:44:58 PM PDT 24
Peak memory 207168 kb
Host smart-f22369df-6dc0-4b85-b61d-063f671fda86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91350
0281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.913500281
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3902633711
Short name T1804
Test name
Test status
Simulation time 266314827 ps
CPU time 1.05 seconds
Started Jul 28 07:45:06 PM PDT 24
Finished Jul 28 07:45:07 PM PDT 24
Peak memory 207100 kb
Host smart-44ca3726-917b-4414-a85b-c37238258c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39026
33711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3902633711
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.3741037133
Short name T1276
Test name
Test status
Simulation time 3957612314 ps
CPU time 117.56 seconds
Started Jul 28 07:45:05 PM PDT 24
Finished Jul 28 07:47:02 PM PDT 24
Peak memory 215596 kb
Host smart-f548f08e-2ac7-4849-b5f9-d9a7b7de8ab9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3741037133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.3741037133
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3165174559
Short name T2141
Test name
Test status
Simulation time 149536127 ps
CPU time 0.89 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:02 PM PDT 24
Peak memory 207144 kb
Host smart-e3dfd23b-5f33-4000-83df-1e31d6ce40a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31651
74559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3165174559
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.291563629
Short name T2252
Test name
Test status
Simulation time 154724112 ps
CPU time 0.93 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 207132 kb
Host smart-f4dd1977-3287-4f8a-b606-d0a32c80a7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29156
3629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.291563629
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.3430893900
Short name T2550
Test name
Test status
Simulation time 615380573 ps
CPU time 1.78 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 207100 kb
Host smart-8fb342f0-b7f9-499e-85be-c12045da246d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34308
93900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.3430893900
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.2736160077
Short name T1144
Test name
Test status
Simulation time 6886342738 ps
CPU time 209.57 seconds
Started Jul 28 07:45:03 PM PDT 24
Finished Jul 28 07:48:33 PM PDT 24
Peak memory 215624 kb
Host smart-6c7e8ccb-a57d-4c4d-89dd-dfa73143dc56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27361
60077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2736160077
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.953106200
Short name T2638
Test name
Test status
Simulation time 721917279 ps
CPU time 15.19 seconds
Started Jul 28 07:45:00 PM PDT 24
Finished Jul 28 07:45:15 PM PDT 24
Peak memory 207344 kb
Host smart-ae3bf630-afe3-47be-9f22-b0e31418760d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953106200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_host
_handshake.953106200
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.529568004
Short name T1511
Test name
Test status
Simulation time 42157015 ps
CPU time 0.66 seconds
Started Jul 28 07:45:16 PM PDT 24
Finished Jul 28 07:45:17 PM PDT 24
Peak memory 207152 kb
Host smart-ef7e8da3-54ac-4713-bbb8-c0b64be0068f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=529568004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.529568004
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3272417974
Short name T2208
Test name
Test status
Simulation time 3599135912 ps
CPU time 5.18 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:08 PM PDT 24
Peak memory 207312 kb
Host smart-22547a79-ab91-4316-b60b-b841f1fbbf34
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272417974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.3272417974
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.2182797668
Short name T1094
Test name
Test status
Simulation time 13451416107 ps
CPU time 16.28 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:18 PM PDT 24
Peak memory 207404 kb
Host smart-78ffc221-34b4-4cf0-8934-8d4403bbe6bc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182797668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.2182797668
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3006257808
Short name T2661
Test name
Test status
Simulation time 23390208900 ps
CPU time 31.47 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:34 PM PDT 24
Peak memory 207368 kb
Host smart-2034f77a-eee9-4d49-8716-a4fa8eddb296
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006257808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_resume.3006257808
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3369898041
Short name T2296
Test name
Test status
Simulation time 219728415 ps
CPU time 0.93 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:02 PM PDT 24
Peak memory 207088 kb
Host smart-160839f6-3325-4ac9-a035-e3ba1c131a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33698
98041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3369898041
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.776318232
Short name T2641
Test name
Test status
Simulation time 181556908 ps
CPU time 0.97 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:03 PM PDT 24
Peak memory 207096 kb
Host smart-21ea23b5-00de-4ee8-97b5-0aa0e17d1f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77631
8232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.776318232
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.1710407066
Short name T2181
Test name
Test status
Simulation time 263348753 ps
CPU time 1.04 seconds
Started Jul 28 07:45:00 PM PDT 24
Finished Jul 28 07:45:01 PM PDT 24
Peak memory 207108 kb
Host smart-303b7380-3074-4319-92ba-407671f72f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17104
07066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1710407066
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.4197188934
Short name T2030
Test name
Test status
Simulation time 1083940747 ps
CPU time 2.55 seconds
Started Jul 28 07:45:05 PM PDT 24
Finished Jul 28 07:45:08 PM PDT 24
Peak memory 207376 kb
Host smart-74893c10-d8cd-4e01-94f5-3797d9a4ad8b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4197188934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.4197188934
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.248031996
Short name T1692
Test name
Test status
Simulation time 3619163239 ps
CPU time 23.12 seconds
Started Jul 28 07:44:58 PM PDT 24
Finished Jul 28 07:45:21 PM PDT 24
Peak memory 207464 kb
Host smart-2fab41c0-4476-4289-ad36-94580ea49a68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248031996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.248031996
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1281383306
Short name T871
Test name
Test status
Simulation time 487516214 ps
CPU time 1.58 seconds
Started Jul 28 07:45:03 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207124 kb
Host smart-d740ba81-9796-4d72-a75b-a8b26f449d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12813
83306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1281383306
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3527186755
Short name T1166
Test name
Test status
Simulation time 142671583 ps
CPU time 0.81 seconds
Started Jul 28 07:45:04 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207172 kb
Host smart-22a60860-f080-4189-813c-d0985ad33cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35271
86755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3527186755
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.2023794640
Short name T1113
Test name
Test status
Simulation time 41180749 ps
CPU time 0.72 seconds
Started Jul 28 07:45:04 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207252 kb
Host smart-541133ea-6a47-427c-82c2-beb909551fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20237
94640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2023794640
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.2525358946
Short name T1053
Test name
Test status
Simulation time 896308903 ps
CPU time 2.57 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207300 kb
Host smart-af79373f-186f-43d9-928d-0f358114f701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25253
58946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.2525358946
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.420576983
Short name T1128
Test name
Test status
Simulation time 262059245 ps
CPU time 2.08 seconds
Started Jul 28 07:45:03 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207288 kb
Host smart-3c152425-2af9-4d74-a98c-d55d3d259671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42057
6983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.420576983
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2387260393
Short name T2442
Test name
Test status
Simulation time 196349734 ps
CPU time 1.09 seconds
Started Jul 28 07:45:01 PM PDT 24
Finished Jul 28 07:45:02 PM PDT 24
Peak memory 207288 kb
Host smart-e5d5c7a9-1193-421a-b2cd-b70b080aa88f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2387260393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2387260393
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.903577060
Short name T2
Test name
Test status
Simulation time 147241057 ps
CPU time 0.85 seconds
Started Jul 28 07:45:03 PM PDT 24
Finished Jul 28 07:45:04 PM PDT 24
Peak memory 207100 kb
Host smart-6e8e11c2-d142-45b0-a8ff-941905bd1c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90357
7060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.903577060
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1985294138
Short name T939
Test name
Test status
Simulation time 175187910 ps
CPU time 0.9 seconds
Started Jul 28 07:45:14 PM PDT 24
Finished Jul 28 07:45:15 PM PDT 24
Peak memory 207160 kb
Host smart-2fe3169b-91df-4b16-a189-2392574ba833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19852
94138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1985294138
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.2823277373
Short name T2325
Test name
Test status
Simulation time 7225688652 ps
CPU time 73.28 seconds
Started Jul 28 07:45:07 PM PDT 24
Finished Jul 28 07:46:21 PM PDT 24
Peak memory 215556 kb
Host smart-36a94ef7-bcf6-42f6-9b5f-9cc31bc20fd3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2823277373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.2823277373
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.818476876
Short name T2356
Test name
Test status
Simulation time 6942964880 ps
CPU time 43.09 seconds
Started Jul 28 07:44:58 PM PDT 24
Finished Jul 28 07:45:41 PM PDT 24
Peak memory 207348 kb
Host smart-f55efb62-0867-4acb-8136-dd197402a642
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=818476876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.818476876
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.58237595
Short name T1447
Test name
Test status
Simulation time 205668055 ps
CPU time 0.91 seconds
Started Jul 28 07:45:04 PM PDT 24
Finished Jul 28 07:45:05 PM PDT 24
Peak memory 207136 kb
Host smart-c6a03f2c-0834-4fbe-83d3-44318528a341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58237
595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.58237595
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3312187064
Short name T555
Test name
Test status
Simulation time 23343547691 ps
CPU time 29.08 seconds
Started Jul 28 07:45:02 PM PDT 24
Finished Jul 28 07:45:31 PM PDT 24
Peak memory 207364 kb
Host smart-e0cbf383-7efe-4e2a-9c81-e2dcefae0ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33121
87064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3312187064
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.999953252
Short name T1484
Test name
Test status
Simulation time 3315205956 ps
CPU time 4.63 seconds
Started Jul 28 07:45:12 PM PDT 24
Finished Jul 28 07:45:16 PM PDT 24
Peak memory 207380 kb
Host smart-32d193c0-910b-4688-a2cb-f12860df7c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99995
3252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.999953252
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.4092749509
Short name T751
Test name
Test status
Simulation time 5841411043 ps
CPU time 165.67 seconds
Started Jul 28 07:45:12 PM PDT 24
Finished Jul 28 07:47:57 PM PDT 24
Peak memory 215628 kb
Host smart-4e98057a-d4cc-4498-bdbb-c3603ca88058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40927
49509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.4092749509
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2204366971
Short name T859
Test name
Test status
Simulation time 4930578142 ps
CPU time 149.44 seconds
Started Jul 28 07:45:11 PM PDT 24
Finished Jul 28 07:47:41 PM PDT 24
Peak memory 215488 kb
Host smart-deb0d428-08b5-482f-8122-c1aac3d06e52
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2204366971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2204366971
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.2087520453
Short name T2410
Test name
Test status
Simulation time 263956735 ps
CPU time 0.98 seconds
Started Jul 28 07:45:23 PM PDT 24
Finished Jul 28 07:45:25 PM PDT 24
Peak memory 207052 kb
Host smart-9069bbaa-32bd-41dd-9c02-5fb976e68e08
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2087520453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.2087520453
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.944865307
Short name T990
Test name
Test status
Simulation time 208665830 ps
CPU time 0.99 seconds
Started Jul 28 07:45:10 PM PDT 24
Finished Jul 28 07:45:11 PM PDT 24
Peak memory 207168 kb
Host smart-5b528f9e-7672-4496-a7fc-1c08dfaf9603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94486
5307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.944865307
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.909723868
Short name T546
Test name
Test status
Simulation time 6805384259 ps
CPU time 195.38 seconds
Started Jul 28 07:45:11 PM PDT 24
Finished Jul 28 07:48:26 PM PDT 24
Peak memory 215572 kb
Host smart-3119c0bd-e312-4cde-90c4-f7a2b2112368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90972
3868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.909723868
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.1135761967
Short name T1372
Test name
Test status
Simulation time 3223868669 ps
CPU time 27.43 seconds
Started Jul 28 07:45:07 PM PDT 24
Finished Jul 28 07:45:35 PM PDT 24
Peak memory 215508 kb
Host smart-68faa2bd-2a3c-4c72-afff-b7ec95f9683e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1135761967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.1135761967
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2312344624
Short name T321
Test name
Test status
Simulation time 152460645 ps
CPU time 0.85 seconds
Started Jul 28 07:45:15 PM PDT 24
Finished Jul 28 07:45:16 PM PDT 24
Peak memory 207152 kb
Host smart-e6dc4b05-0676-402c-b129-e22fda8b5c7e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2312344624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2312344624
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3197839908
Short name T1068
Test name
Test status
Simulation time 165389817 ps
CPU time 0.86 seconds
Started Jul 28 07:45:06 PM PDT 24
Finished Jul 28 07:45:07 PM PDT 24
Peak memory 207160 kb
Host smart-af78ae96-baf2-4559-91e6-ec87532cea8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31978
39908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3197839908
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1245314545
Short name T1336
Test name
Test status
Simulation time 207637712 ps
CPU time 1.02 seconds
Started Jul 28 07:45:24 PM PDT 24
Finished Jul 28 07:45:25 PM PDT 24
Peak memory 207180 kb
Host smart-449b8632-597f-44df-a625-8cfc721f1d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12453
14545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1245314545
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2063154199
Short name T1616
Test name
Test status
Simulation time 179281872 ps
CPU time 0.94 seconds
Started Jul 28 07:45:12 PM PDT 24
Finished Jul 28 07:45:13 PM PDT 24
Peak memory 207152 kb
Host smart-a7b62e99-02f4-483d-a33f-97d9f2212b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20631
54199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2063154199
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1427619576
Short name T700
Test name
Test status
Simulation time 203779091 ps
CPU time 0.9 seconds
Started Jul 28 07:45:05 PM PDT 24
Finished Jul 28 07:45:06 PM PDT 24
Peak memory 207144 kb
Host smart-336f24db-8b2e-43ff-937e-14d24664f10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14276
19576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1427619576
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1340907342
Short name T1366
Test name
Test status
Simulation time 219257687 ps
CPU time 0.93 seconds
Started Jul 28 07:45:09 PM PDT 24
Finished Jul 28 07:45:10 PM PDT 24
Peak memory 207144 kb
Host smart-9cf2966e-1d65-4a03-85e5-0aa5701b2153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13409
07342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1340907342
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2764896469
Short name T1853
Test name
Test status
Simulation time 154952393 ps
CPU time 0.8 seconds
Started Jul 28 07:45:22 PM PDT 24
Finished Jul 28 07:45:23 PM PDT 24
Peak memory 207076 kb
Host smart-b9fedb1a-fbb2-46b9-ab77-c6932f263593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27648
96469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2764896469
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3676197179
Short name T1754
Test name
Test status
Simulation time 226272397 ps
CPU time 1.06 seconds
Started Jul 28 07:45:22 PM PDT 24
Finished Jul 28 07:45:23 PM PDT 24
Peak memory 207092 kb
Host smart-29e59c7e-6b88-4ac8-a5a5-d71e3c48514d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3676197179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3676197179
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1140050705
Short name T1934
Test name
Test status
Simulation time 188323761 ps
CPU time 0.93 seconds
Started Jul 28 07:45:13 PM PDT 24
Finished Jul 28 07:45:14 PM PDT 24
Peak memory 207108 kb
Host smart-1615f020-f7e5-4459-8072-7b572224b1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11400
50705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1140050705
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1019270010
Short name T2675
Test name
Test status
Simulation time 48089829 ps
CPU time 0.7 seconds
Started Jul 28 07:45:12 PM PDT 24
Finished Jul 28 07:45:13 PM PDT 24
Peak memory 207084 kb
Host smart-69d0cfd7-ca07-433d-adf0-75f624e55307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10192
70010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1019270010
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.4052805721
Short name T1490
Test name
Test status
Simulation time 13720982199 ps
CPU time 35.28 seconds
Started Jul 28 07:45:09 PM PDT 24
Finished Jul 28 07:45:45 PM PDT 24
Peak memory 219660 kb
Host smart-c3281f31-fa6b-49c2-8864-dd11b0a13af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40528
05721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.4052805721
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3642435015
Short name T1822
Test name
Test status
Simulation time 166162987 ps
CPU time 0.89 seconds
Started Jul 28 07:45:15 PM PDT 24
Finished Jul 28 07:45:16 PM PDT 24
Peak memory 207116 kb
Host smart-e0757cbe-9a78-40cf-b909-f11e15f9cf78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36424
35015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3642435015
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1557676782
Short name T2637
Test name
Test status
Simulation time 236155030 ps
CPU time 0.95 seconds
Started Jul 28 07:45:14 PM PDT 24
Finished Jul 28 07:45:15 PM PDT 24
Peak memory 207036 kb
Host smart-0669b536-9074-4db0-a5fb-d2eaf5346f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15576
76782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1557676782
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1031011983
Short name T1410
Test name
Test status
Simulation time 216376214 ps
CPU time 0.96 seconds
Started Jul 28 07:45:21 PM PDT 24
Finished Jul 28 07:45:22 PM PDT 24
Peak memory 207104 kb
Host smart-7895c46b-8f56-4758-922f-8cb15764f080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10310
11983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1031011983
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.2114822174
Short name T1266
Test name
Test status
Simulation time 180046015 ps
CPU time 0.93 seconds
Started Jul 28 07:45:12 PM PDT 24
Finished Jul 28 07:45:13 PM PDT 24
Peak memory 207164 kb
Host smart-802e436a-ed9c-4e4d-bf71-e75b9059c172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21148
22174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2114822174
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2608159773
Short name T928
Test name
Test status
Simulation time 180173968 ps
CPU time 0.84 seconds
Started Jul 28 07:45:11 PM PDT 24
Finished Jul 28 07:45:17 PM PDT 24
Peak memory 207076 kb
Host smart-3cf92985-5e8d-45f9-abb2-c8e3306d821b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26081
59773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2608159773
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3402162935
Short name T1844
Test name
Test status
Simulation time 149331377 ps
CPU time 0.83 seconds
Started Jul 28 07:45:28 PM PDT 24
Finished Jul 28 07:45:29 PM PDT 24
Peak memory 207048 kb
Host smart-52c685fe-8302-4271-8855-81973f3a8504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34021
62935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3402162935
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1357906475
Short name T2621
Test name
Test status
Simulation time 148904567 ps
CPU time 0.79 seconds
Started Jul 28 07:45:15 PM PDT 24
Finished Jul 28 07:45:15 PM PDT 24
Peak memory 207136 kb
Host smart-56140280-62b0-4065-beb3-dbd4a439fd2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13579
06475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1357906475
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1093700722
Short name T1540
Test name
Test status
Simulation time 208380684 ps
CPU time 0.96 seconds
Started Jul 28 07:45:23 PM PDT 24
Finished Jul 28 07:45:24 PM PDT 24
Peak memory 207040 kb
Host smart-dbf18dfb-2ab5-403d-8616-4da259063b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10937
00722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1093700722
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.3251038174
Short name T149
Test name
Test status
Simulation time 4184694151 ps
CPU time 45.46 seconds
Started Jul 28 07:45:27 PM PDT 24
Finished Jul 28 07:46:12 PM PDT 24
Peak memory 216912 kb
Host smart-c3ae9c2d-60d4-4335-8f25-a3f6078a2eaf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3251038174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.3251038174
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3595635687
Short name T2439
Test name
Test status
Simulation time 173219597 ps
CPU time 0.92 seconds
Started Jul 28 07:45:27 PM PDT 24
Finished Jul 28 07:45:28 PM PDT 24
Peak memory 207088 kb
Host smart-ed231786-965c-498d-a3c5-c8075c85e406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35956
35687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3595635687
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.3882716613
Short name T1081
Test name
Test status
Simulation time 177965318 ps
CPU time 0.88 seconds
Started Jul 28 07:45:19 PM PDT 24
Finished Jul 28 07:45:25 PM PDT 24
Peak memory 207044 kb
Host smart-e7d9b660-73b4-486f-92c9-9841c31b145b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38827
16613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3882716613
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.232827485
Short name T1979
Test name
Test status
Simulation time 314331276 ps
CPU time 1.12 seconds
Started Jul 28 07:45:13 PM PDT 24
Finished Jul 28 07:45:14 PM PDT 24
Peak memory 207088 kb
Host smart-68b01014-ff9c-4a1f-9506-59861bc2987d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23282
7485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.232827485
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.1926957907
Short name T1421
Test name
Test status
Simulation time 3229408499 ps
CPU time 24.71 seconds
Started Jul 28 07:45:13 PM PDT 24
Finished Jul 28 07:45:38 PM PDT 24
Peak memory 216852 kb
Host smart-30c1b31d-37a6-4283-ae2f-5ac1ca04d9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19269
57907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.1926957907
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.2060364167
Short name T1814
Test name
Test status
Simulation time 546245928 ps
CPU time 11.14 seconds
Started Jul 28 07:45:00 PM PDT 24
Finished Jul 28 07:45:11 PM PDT 24
Peak memory 207396 kb
Host smart-9b449262-29ff-4af5-b01e-b05a47f0b223
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060364167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.2060364167
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.2947648239
Short name T705
Test name
Test status
Simulation time 27741129 ps
CPU time 0.64 seconds
Started Jul 28 07:45:37 PM PDT 24
Finished Jul 28 07:45:38 PM PDT 24
Peak memory 207192 kb
Host smart-a6d5ae68-d2d5-4b85-b1be-19987eceb1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2947648239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.2947648239
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1014519284
Short name T1323
Test name
Test status
Simulation time 3896639551 ps
CPU time 6.49 seconds
Started Jul 28 07:45:12 PM PDT 24
Finished Jul 28 07:45:19 PM PDT 24
Peak memory 207360 kb
Host smart-90bb4068-f40d-4fb2-b72b-65a72039e118
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014519284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_disconnect.1014519284
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.838862404
Short name T1290
Test name
Test status
Simulation time 13345860756 ps
CPU time 14.63 seconds
Started Jul 28 07:45:19 PM PDT 24
Finished Jul 28 07:45:34 PM PDT 24
Peak memory 207308 kb
Host smart-c2a4d30e-76e7-4496-8768-1d28865e3760
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=838862404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.838862404
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1023641203
Short name T1801
Test name
Test status
Simulation time 23332615729 ps
CPU time 29.51 seconds
Started Jul 28 07:45:21 PM PDT 24
Finished Jul 28 07:45:51 PM PDT 24
Peak memory 207412 kb
Host smart-4a143fe2-aa49-4f5e-aea9-13a7fea0c0dd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023641203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.1023641203
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1078425723
Short name T2855
Test name
Test status
Simulation time 221041011 ps
CPU time 0.93 seconds
Started Jul 28 07:45:14 PM PDT 24
Finished Jul 28 07:45:20 PM PDT 24
Peak memory 207140 kb
Host smart-ee8d2519-5119-4ede-b39b-a673e142c24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10784
25723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1078425723
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.3275120678
Short name T77
Test name
Test status
Simulation time 173272512 ps
CPU time 0.84 seconds
Started Jul 28 07:45:13 PM PDT 24
Finished Jul 28 07:45:14 PM PDT 24
Peak memory 207048 kb
Host smart-6f596cee-67d7-4216-8d11-a4effc98e119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32751
20678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.3275120678
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.2307652049
Short name T2655
Test name
Test status
Simulation time 513912977 ps
CPU time 1.72 seconds
Started Jul 28 07:45:29 PM PDT 24
Finished Jul 28 07:45:31 PM PDT 24
Peak memory 207108 kb
Host smart-428dfbaa-5214-406a-a3df-68eb8eb8fd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23076
52049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.2307652049
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2593132964
Short name T2559
Test name
Test status
Simulation time 702510442 ps
CPU time 1.87 seconds
Started Jul 28 07:45:24 PM PDT 24
Finished Jul 28 07:45:26 PM PDT 24
Peak memory 207136 kb
Host smart-a696f18f-fb33-4561-aa42-7fa823106f11
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2593132964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2593132964
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.2756869829
Short name T1014
Test name
Test status
Simulation time 20421237838 ps
CPU time 46.72 seconds
Started Jul 28 07:45:26 PM PDT 24
Finished Jul 28 07:46:13 PM PDT 24
Peak memory 207456 kb
Host smart-bbd61af9-39be-477a-b030-b95bd30c284d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27568
69829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2756869829
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.3438279483
Short name T2186
Test name
Test status
Simulation time 4303607093 ps
CPU time 37.86 seconds
Started Jul 28 07:45:35 PM PDT 24
Finished Jul 28 07:46:13 PM PDT 24
Peak memory 207244 kb
Host smart-1df36ee8-95ad-40b4-8a2b-01bbfcda6c75
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438279483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.3438279483
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.772324413
Short name T1124
Test name
Test status
Simulation time 475150187 ps
CPU time 1.62 seconds
Started Jul 28 07:45:45 PM PDT 24
Finished Jul 28 07:45:46 PM PDT 24
Peak memory 207116 kb
Host smart-a9a58421-8577-42b8-8cc5-88ec7a823de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77232
4413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.772324413
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.405939302
Short name T2513
Test name
Test status
Simulation time 140552051 ps
CPU time 0.79 seconds
Started Jul 28 07:45:15 PM PDT 24
Finished Jul 28 07:45:15 PM PDT 24
Peak memory 207120 kb
Host smart-43619065-f3e0-4811-ad33-a9a0c323366f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40593
9302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.405939302
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2381080472
Short name T1734
Test name
Test status
Simulation time 79503438 ps
CPU time 0.78 seconds
Started Jul 28 07:45:30 PM PDT 24
Finished Jul 28 07:45:31 PM PDT 24
Peak memory 207032 kb
Host smart-2ab7c0f7-778f-44ae-b390-f0f9c06642ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23810
80472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2381080472
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.360295412
Short name T2796
Test name
Test status
Simulation time 863485176 ps
CPU time 2.59 seconds
Started Jul 28 07:45:29 PM PDT 24
Finished Jul 28 07:45:31 PM PDT 24
Peak memory 207288 kb
Host smart-98b3bf4a-4aad-4192-b784-fd3c3f97f158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36029
5412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.360295412
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1551130712
Short name T1385
Test name
Test status
Simulation time 441627952 ps
CPU time 2.5 seconds
Started Jul 28 07:45:15 PM PDT 24
Finished Jul 28 07:45:17 PM PDT 24
Peak memory 207284 kb
Host smart-28e2c006-2f60-44d4-914e-8c57930a7cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15511
30712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1551130712
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.3551131764
Short name T858
Test name
Test status
Simulation time 195557495 ps
CPU time 1.01 seconds
Started Jul 28 07:45:26 PM PDT 24
Finished Jul 28 07:45:27 PM PDT 24
Peak memory 207244 kb
Host smart-d410813d-95f8-4f06-9203-063bda861f07
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3551131764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3551131764
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2124249126
Short name T753
Test name
Test status
Simulation time 153796417 ps
CPU time 0.8 seconds
Started Jul 28 07:45:35 PM PDT 24
Finished Jul 28 07:45:36 PM PDT 24
Peak memory 207096 kb
Host smart-ee6eb232-6731-4db8-ade1-9c9f4475b78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21242
49126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2124249126
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3143934589
Short name T2254
Test name
Test status
Simulation time 247335835 ps
CPU time 1.02 seconds
Started Jul 28 07:45:24 PM PDT 24
Finished Jul 28 07:45:25 PM PDT 24
Peak memory 207140 kb
Host smart-28acf278-25c2-4ac0-b7ad-ba2b3a3cd065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31439
34589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3143934589
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.1110972183
Short name T1527
Test name
Test status
Simulation time 9214253768 ps
CPU time 259.09 seconds
Started Jul 28 07:45:15 PM PDT 24
Finished Jul 28 07:49:34 PM PDT 24
Peak memory 215604 kb
Host smart-20a91760-e14c-4b97-9e47-1d5b1ed7e46a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1110972183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1110972183
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.531895214
Short name T1244
Test name
Test status
Simulation time 12487625291 ps
CPU time 85.4 seconds
Started Jul 28 07:45:11 PM PDT 24
Finished Jul 28 07:46:37 PM PDT 24
Peak memory 207532 kb
Host smart-f9574a17-1f79-4b53-b039-43570d815569
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=531895214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.531895214
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3788668709
Short name T365
Test name
Test status
Simulation time 251105003 ps
CPU time 1.06 seconds
Started Jul 28 07:45:14 PM PDT 24
Finished Jul 28 07:45:15 PM PDT 24
Peak memory 207160 kb
Host smart-dcb002a6-4461-4b41-987a-61c6cb164c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37886
68709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3788668709
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.3093472267
Short name T2619
Test name
Test status
Simulation time 23291831936 ps
CPU time 27.22 seconds
Started Jul 28 07:45:31 PM PDT 24
Finished Jul 28 07:45:58 PM PDT 24
Peak memory 207420 kb
Host smart-6f8b4d43-5d79-4db4-806b-c6ad61af5260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30934
72267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3093472267
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.4264571503
Short name T34
Test name
Test status
Simulation time 3340805212 ps
CPU time 5.03 seconds
Started Jul 28 07:45:18 PM PDT 24
Finished Jul 28 07:45:23 PM PDT 24
Peak memory 207376 kb
Host smart-f8433441-4f54-48d7-a947-793ebe1ac573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42645
71503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.4264571503
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.1555263288
Short name T898
Test name
Test status
Simulation time 8122111591 ps
CPU time 66.4 seconds
Started Jul 28 07:45:38 PM PDT 24
Finished Jul 28 07:46:45 PM PDT 24
Peak memory 217756 kb
Host smart-0c884b3d-8d10-4682-9966-7cbfc28560ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15552
63288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.1555263288
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.1715381056
Short name T1956
Test name
Test status
Simulation time 6896695155 ps
CPU time 72.89 seconds
Started Jul 28 07:45:44 PM PDT 24
Finished Jul 28 07:46:57 PM PDT 24
Peak memory 207444 kb
Host smart-0eaf967a-6264-40e8-8f23-d0834c57b251
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1715381056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.1715381056
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.1736783160
Short name T989
Test name
Test status
Simulation time 239821536 ps
CPU time 1.04 seconds
Started Jul 28 07:45:32 PM PDT 24
Finished Jul 28 07:45:33 PM PDT 24
Peak memory 207148 kb
Host smart-7447b707-af5b-40c9-96c4-a0e569519294
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1736783160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.1736783160
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2747024107
Short name T315
Test name
Test status
Simulation time 194791458 ps
CPU time 0.93 seconds
Started Jul 28 07:45:41 PM PDT 24
Finished Jul 28 07:45:42 PM PDT 24
Peak memory 207064 kb
Host smart-43818486-0508-4de6-8f16-81ae2390c234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27470
24107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2747024107
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.3714425536
Short name T1412
Test name
Test status
Simulation time 5106056022 ps
CPU time 51.34 seconds
Started Jul 28 07:45:18 PM PDT 24
Finished Jul 28 07:46:10 PM PDT 24
Peak memory 215504 kb
Host smart-38b976ab-3113-4fac-b8e1-13a32d477102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37144
25536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.3714425536
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.2620306647
Short name T445
Test name
Test status
Simulation time 3323668638 ps
CPU time 25.13 seconds
Started Jul 28 07:45:34 PM PDT 24
Finished Jul 28 07:45:59 PM PDT 24
Peak memory 217084 kb
Host smart-a3e11f52-003e-4e9b-bf94-398b9a38b612
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2620306647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.2620306647
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1943399810
Short name T1193
Test name
Test status
Simulation time 148185542 ps
CPU time 0.86 seconds
Started Jul 28 07:45:35 PM PDT 24
Finished Jul 28 07:45:36 PM PDT 24
Peak memory 207088 kb
Host smart-fb89c1cb-8808-4abd-827a-07f0c3f9054e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1943399810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1943399810
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1773979569
Short name T2795
Test name
Test status
Simulation time 149529113 ps
CPU time 0.85 seconds
Started Jul 28 07:45:19 PM PDT 24
Finished Jul 28 07:45:20 PM PDT 24
Peak memory 207140 kb
Host smart-63a87270-c481-4d0f-a0b1-61ea91f55f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17739
79569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1773979569
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1399342985
Short name T2797
Test name
Test status
Simulation time 206636532 ps
CPU time 0.99 seconds
Started Jul 28 07:45:25 PM PDT 24
Finished Jul 28 07:45:32 PM PDT 24
Peak memory 207172 kb
Host smart-c59ab035-0dfb-4fa1-8b3e-7b568bec2036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13993
42985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1399342985
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1589239371
Short name T2781
Test name
Test status
Simulation time 194610411 ps
CPU time 0.99 seconds
Started Jul 28 07:45:36 PM PDT 24
Finished Jul 28 07:45:37 PM PDT 24
Peak memory 207124 kb
Host smart-c927e996-bac6-4f0b-a1f5-b1389371a142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15892
39371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1589239371
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3762653263
Short name T1190
Test name
Test status
Simulation time 183848458 ps
CPU time 0.87 seconds
Started Jul 28 07:45:23 PM PDT 24
Finished Jul 28 07:45:24 PM PDT 24
Peak memory 207136 kb
Host smart-2b2dcd96-a1ec-451a-adaf-19f58a6f31fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37626
53263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3762653263
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.4130700139
Short name T1635
Test name
Test status
Simulation time 177665856 ps
CPU time 0.88 seconds
Started Jul 28 07:45:42 PM PDT 24
Finished Jul 28 07:45:43 PM PDT 24
Peak memory 207204 kb
Host smart-32b8ef8b-4a2f-4874-98f6-fe1401d631f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41307
00139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.4130700139
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.798034544
Short name T171
Test name
Test status
Simulation time 211651102 ps
CPU time 0.93 seconds
Started Jul 28 07:45:18 PM PDT 24
Finished Jul 28 07:45:19 PM PDT 24
Peak memory 207140 kb
Host smart-75e2952f-c752-46ee-a784-33b4f1dd5f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79803
4544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.798034544
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.4065052845
Short name T1463
Test name
Test status
Simulation time 244188561 ps
CPU time 1.1 seconds
Started Jul 28 07:45:32 PM PDT 24
Finished Jul 28 07:45:34 PM PDT 24
Peak memory 207152 kb
Host smart-66da2c05-97fb-494e-ac34-6a3cb5e4cd96
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4065052845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.4065052845
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2834800691
Short name T21
Test name
Test status
Simulation time 141108865 ps
CPU time 0.84 seconds
Started Jul 28 07:45:35 PM PDT 24
Finished Jul 28 07:45:36 PM PDT 24
Peak memory 207124 kb
Host smart-48605eeb-3220-4a33-b21a-663ef7f3ad7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28348
00691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2834800691
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2468177487
Short name T2124
Test name
Test status
Simulation time 50507909 ps
CPU time 0.7 seconds
Started Jul 28 07:45:43 PM PDT 24
Finished Jul 28 07:45:43 PM PDT 24
Peak memory 207084 kb
Host smart-85fc0811-5867-4d5b-a547-a7e8e79933ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24681
77487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2468177487
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.4200778446
Short name T2867
Test name
Test status
Simulation time 11634740193 ps
CPU time 29.13 seconds
Started Jul 28 07:45:19 PM PDT 24
Finished Jul 28 07:45:48 PM PDT 24
Peak memory 215628 kb
Host smart-c387dcc2-ec57-49ff-aaac-7f0f18659ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42007
78446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.4200778446
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2737924311
Short name T644
Test name
Test status
Simulation time 199365545 ps
CPU time 0.91 seconds
Started Jul 28 07:45:16 PM PDT 24
Finished Jul 28 07:45:17 PM PDT 24
Peak memory 207136 kb
Host smart-df17b628-61d1-4b22-a3c3-84e72a42ac4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27379
24311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2737924311
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.322541708
Short name T1779
Test name
Test status
Simulation time 193868646 ps
CPU time 0.9 seconds
Started Jul 28 07:45:39 PM PDT 24
Finished Jul 28 07:45:40 PM PDT 24
Peak memory 207060 kb
Host smart-4eff2a57-700e-4ebf-a814-4e3ef4fab7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32254
1708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.322541708
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.4195647984
Short name T1948
Test name
Test status
Simulation time 204257851 ps
CPU time 0.95 seconds
Started Jul 28 07:45:44 PM PDT 24
Finished Jul 28 07:45:45 PM PDT 24
Peak memory 207152 kb
Host smart-20c9654e-b738-492f-a916-205f11842e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41956
47984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.4195647984
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.949037054
Short name T1561
Test name
Test status
Simulation time 194384231 ps
CPU time 0.98 seconds
Started Jul 28 07:45:38 PM PDT 24
Finished Jul 28 07:45:40 PM PDT 24
Peak memory 207164 kb
Host smart-6004c5e4-ec32-42f8-9c8b-3126d8b224a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94903
7054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.949037054
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3330043953
Short name T1177
Test name
Test status
Simulation time 227221670 ps
CPU time 1.01 seconds
Started Jul 28 07:45:39 PM PDT 24
Finished Jul 28 07:45:40 PM PDT 24
Peak memory 207044 kb
Host smart-c76bda17-2c60-42f6-9648-611ef20a18cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33300
43953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3330043953
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.699446554
Short name T465
Test name
Test status
Simulation time 150949816 ps
CPU time 0.87 seconds
Started Jul 28 07:45:37 PM PDT 24
Finished Jul 28 07:45:38 PM PDT 24
Peak memory 207248 kb
Host smart-8b5f965e-046a-44dd-9a20-cac8ca412b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69944
6554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.699446554
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2362880879
Short name T542
Test name
Test status
Simulation time 151742041 ps
CPU time 0.8 seconds
Started Jul 28 07:45:39 PM PDT 24
Finished Jul 28 07:45:40 PM PDT 24
Peak memory 207100 kb
Host smart-d44a82e8-3748-4a02-964b-32c14bc60cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23628
80879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2362880879
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1484190676
Short name T1091
Test name
Test status
Simulation time 210556747 ps
CPU time 0.99 seconds
Started Jul 28 07:45:43 PM PDT 24
Finished Jul 28 07:45:44 PM PDT 24
Peak memory 207128 kb
Host smart-d945bcf5-d704-4792-a3e6-14a1edfbd3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14841
90676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1484190676
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1003054765
Short name T620
Test name
Test status
Simulation time 3810422959 ps
CPU time 112.14 seconds
Started Jul 28 07:45:37 PM PDT 24
Finished Jul 28 07:47:29 PM PDT 24
Peak memory 215580 kb
Host smart-e0f57266-134b-4fb1-90a7-e44f9a61aa3a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1003054765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1003054765
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2709956133
Short name T1132
Test name
Test status
Simulation time 193423115 ps
CPU time 0.95 seconds
Started Jul 28 07:45:39 PM PDT 24
Finished Jul 28 07:45:45 PM PDT 24
Peak memory 207124 kb
Host smart-b32e36fd-7ebc-4903-8f82-84890b3851f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27099
56133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2709956133
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.823872007
Short name T1448
Test name
Test status
Simulation time 217717081 ps
CPU time 0.95 seconds
Started Jul 28 07:45:38 PM PDT 24
Finished Jul 28 07:45:39 PM PDT 24
Peak memory 207204 kb
Host smart-2788891b-fb03-435c-ab03-ff943aa0f1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82387
2007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.823872007
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.2280207249
Short name T2448
Test name
Test status
Simulation time 724333477 ps
CPU time 1.88 seconds
Started Jul 28 07:45:37 PM PDT 24
Finished Jul 28 07:45:39 PM PDT 24
Peak memory 207088 kb
Host smart-3316fd54-57e8-4e0f-ad4e-0b668c9dba97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22802
07249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2280207249
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.729997968
Short name T2419
Test name
Test status
Simulation time 4855718758 ps
CPU time 134.83 seconds
Started Jul 28 07:45:40 PM PDT 24
Finished Jul 28 07:47:56 PM PDT 24
Peak memory 223548 kb
Host smart-b39e5889-384e-49e8-8ebf-edca67a5affb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72999
7968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.729997968
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.55389068
Short name T1698
Test name
Test status
Simulation time 763730548 ps
CPU time 15.82 seconds
Started Jul 28 07:45:15 PM PDT 24
Finished Jul 28 07:45:31 PM PDT 24
Peak memory 207296 kb
Host smart-9f0a2f5e-50d0-453c-a26a-fd95a24ce05c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55389068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_host_
handshake.55389068
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.2860933372
Short name T1609
Test name
Test status
Simulation time 36621529 ps
CPU time 0.66 seconds
Started Jul 28 07:39:00 PM PDT 24
Finished Jul 28 07:39:01 PM PDT 24
Peak memory 207148 kb
Host smart-0b8d81a5-620d-4435-bb5f-83deeb3a29ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2860933372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2860933372
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.4162955686
Short name T947
Test name
Test status
Simulation time 4102790912 ps
CPU time 5.89 seconds
Started Jul 28 07:38:49 PM PDT 24
Finished Jul 28 07:38:55 PM PDT 24
Peak memory 207316 kb
Host smart-78d0df8a-f832-4022-9fbe-af187475b0b5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162955686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.4162955686
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2393409018
Short name T799
Test name
Test status
Simulation time 13397511984 ps
CPU time 14.55 seconds
Started Jul 28 07:38:48 PM PDT 24
Finished Jul 28 07:39:03 PM PDT 24
Peak memory 207440 kb
Host smart-0fcadc36-689d-4542-ae42-1137635fe874
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393409018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2393409018
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3386527406
Short name T1905
Test name
Test status
Simulation time 23347590627 ps
CPU time 26.29 seconds
Started Jul 28 07:38:48 PM PDT 24
Finished Jul 28 07:39:15 PM PDT 24
Peak memory 207372 kb
Host smart-4c14a7fd-154b-478d-97a2-4f4d93ee46e7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386527406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.3386527406
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1168950927
Short name T2405
Test name
Test status
Simulation time 155102668 ps
CPU time 0.84 seconds
Started Jul 28 07:39:09 PM PDT 24
Finished Jul 28 07:39:10 PM PDT 24
Peak memory 207136 kb
Host smart-44ed410d-87ea-4bc9-b9b0-87a3454e4268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11689
50927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1168950927
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3173706068
Short name T469
Test name
Test status
Simulation time 195306821 ps
CPU time 0.9 seconds
Started Jul 28 07:38:56 PM PDT 24
Finished Jul 28 07:38:57 PM PDT 24
Peak memory 207080 kb
Host smart-97b7b38c-3fa5-4adc-b99d-38d160ba9cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31737
06068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3173706068
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.4161150850
Short name T2097
Test name
Test status
Simulation time 482020241 ps
CPU time 1.62 seconds
Started Jul 28 07:38:53 PM PDT 24
Finished Jul 28 07:38:55 PM PDT 24
Peak memory 207132 kb
Host smart-6a95b57f-3b9f-4682-81e4-c480a78929df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41611
50850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.4161150850
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.3291825513
Short name T2028
Test name
Test status
Simulation time 1249602402 ps
CPU time 3.18 seconds
Started Jul 28 07:39:07 PM PDT 24
Finished Jul 28 07:39:10 PM PDT 24
Peak memory 207244 kb
Host smart-19a2ad7b-f127-4583-89c7-c343549689a8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3291825513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.3291825513
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.3345604182
Short name T1512
Test name
Test status
Simulation time 1267174339 ps
CPU time 29.28 seconds
Started Jul 28 07:39:07 PM PDT 24
Finished Jul 28 07:39:37 PM PDT 24
Peak memory 207304 kb
Host smart-869593ac-7f9b-4a0a-bc90-cd307d55821e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345604182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.3345604182
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.1859585419
Short name T1106
Test name
Test status
Simulation time 506430965 ps
CPU time 1.64 seconds
Started Jul 28 07:38:55 PM PDT 24
Finished Jul 28 07:38:57 PM PDT 24
Peak memory 207080 kb
Host smart-0216abb3-50ad-47b8-8c2c-a860402312a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18595
85419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.1859585419
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2174594961
Short name T800
Test name
Test status
Simulation time 140093273 ps
CPU time 0.88 seconds
Started Jul 28 07:39:05 PM PDT 24
Finished Jul 28 07:39:08 PM PDT 24
Peak memory 207204 kb
Host smart-ab4294c8-0865-4a7a-bd23-35801a28f4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21745
94961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2174594961
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.1098740115
Short name T444
Test name
Test status
Simulation time 84772573 ps
CPU time 0.72 seconds
Started Jul 28 07:39:13 PM PDT 24
Finished Jul 28 07:39:14 PM PDT 24
Peak memory 207064 kb
Host smart-58ce9f3b-1452-498d-9451-a63555d82c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10987
40115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1098740115
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.3223902232
Short name T1812
Test name
Test status
Simulation time 901537098 ps
CPU time 2.4 seconds
Started Jul 28 07:38:52 PM PDT 24
Finished Jul 28 07:38:55 PM PDT 24
Peak memory 207400 kb
Host smart-ccedeef2-b75f-4315-8ea5-34fce58d73a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32239
02232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3223902232
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3948775502
Short name T1658
Test name
Test status
Simulation time 290481394 ps
CPU time 2.01 seconds
Started Jul 28 07:38:51 PM PDT 24
Finished Jul 28 07:38:53 PM PDT 24
Peak memory 207412 kb
Host smart-c9d15ed9-f1d3-4fe8-8743-ca06da683b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39487
75502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3948775502
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2522765737
Short name T1080
Test name
Test status
Simulation time 224502264 ps
CPU time 1.13 seconds
Started Jul 28 07:38:54 PM PDT 24
Finished Jul 28 07:38:56 PM PDT 24
Peak memory 207304 kb
Host smart-149fa6bb-0118-44d4-86f4-d1ef74e2f752
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2522765737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2522765737
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3780325184
Short name T420
Test name
Test status
Simulation time 151282468 ps
CPU time 0.85 seconds
Started Jul 28 07:39:13 PM PDT 24
Finished Jul 28 07:39:14 PM PDT 24
Peak memory 207096 kb
Host smart-715075d2-ba90-4652-a0ea-194c91caf9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37803
25184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3780325184
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1798740935
Short name T1613
Test name
Test status
Simulation time 182542779 ps
CPU time 0.91 seconds
Started Jul 28 07:38:57 PM PDT 24
Finished Jul 28 07:38:58 PM PDT 24
Peak memory 207136 kb
Host smart-49073a62-d1b6-4ec9-817e-b4ec667162e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17987
40935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1798740935
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.761855318
Short name T893
Test name
Test status
Simulation time 5519725357 ps
CPU time 40.78 seconds
Started Jul 28 07:38:54 PM PDT 24
Finished Jul 28 07:39:35 PM PDT 24
Peak memory 217056 kb
Host smart-82427dc6-1ecb-4359-b462-318062a17595
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=761855318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.761855318
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.3789791731
Short name T2710
Test name
Test status
Simulation time 11128481981 ps
CPU time 70.25 seconds
Started Jul 28 07:39:06 PM PDT 24
Finished Jul 28 07:40:17 PM PDT 24
Peak memory 207376 kb
Host smart-b3729382-3e26-49a6-93ba-231cfdebf2f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3789791731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.3789791731
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.2819050165
Short name T1725
Test name
Test status
Simulation time 217124807 ps
CPU time 1 seconds
Started Jul 28 07:39:06 PM PDT 24
Finished Jul 28 07:39:07 PM PDT 24
Peak memory 207112 kb
Host smart-0567b33b-248f-4156-b0bd-2c6c323da0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28190
50165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2819050165
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.54773561
Short name T2530
Test name
Test status
Simulation time 23334240877 ps
CPU time 32.64 seconds
Started Jul 28 07:38:55 PM PDT 24
Finished Jul 28 07:39:28 PM PDT 24
Peak memory 207352 kb
Host smart-50525269-721f-498f-8993-0a337c85b5ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54773
561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.54773561
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.994006068
Short name T603
Test name
Test status
Simulation time 3317698936 ps
CPU time 4.93 seconds
Started Jul 28 07:38:57 PM PDT 24
Finished Jul 28 07:39:02 PM PDT 24
Peak memory 207376 kb
Host smart-ca1c6fce-552c-40d3-959c-f6dd0ad45d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99400
6068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.994006068
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.1592855974
Short name T595
Test name
Test status
Simulation time 6539567061 ps
CPU time 49.59 seconds
Started Jul 28 07:39:08 PM PDT 24
Finished Jul 28 07:39:58 PM PDT 24
Peak memory 223684 kb
Host smart-0b5fedf4-1910-481b-b183-05c1f2deb2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15928
55974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1592855974
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3853252721
Short name T2525
Test name
Test status
Simulation time 4549513545 ps
CPU time 129.74 seconds
Started Jul 28 07:38:51 PM PDT 24
Finished Jul 28 07:41:01 PM PDT 24
Peak memory 215552 kb
Host smart-b68b205a-9d91-4c6d-9cca-620dfcb7bf3d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3853252721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3853252721
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.1403986179
Short name T1231
Test name
Test status
Simulation time 257536611 ps
CPU time 1.04 seconds
Started Jul 28 07:39:08 PM PDT 24
Finished Jul 28 07:39:09 PM PDT 24
Peak memory 207088 kb
Host smart-cc6bc86b-12ed-44a0-9bef-23760dca1f46
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1403986179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.1403986179
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1307471107
Short name T2103
Test name
Test status
Simulation time 195197052 ps
CPU time 0.94 seconds
Started Jul 28 07:38:53 PM PDT 24
Finished Jul 28 07:38:55 PM PDT 24
Peak memory 207196 kb
Host smart-26c870c0-6998-416e-b976-d666b704b6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13074
71107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1307471107
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1617003784
Short name T1480
Test name
Test status
Simulation time 4462688416 ps
CPU time 125.33 seconds
Started Jul 28 07:38:55 PM PDT 24
Finished Jul 28 07:41:00 PM PDT 24
Peak memory 215592 kb
Host smart-6d81da5c-364c-4cee-8ca0-f8995c6e5b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16170
03784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1617003784
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.1817821001
Short name T2464
Test name
Test status
Simulation time 5001438110 ps
CPU time 49.24 seconds
Started Jul 28 07:39:10 PM PDT 24
Finished Jul 28 07:40:00 PM PDT 24
Peak memory 207368 kb
Host smart-4c82fb5c-fd55-4213-a0e5-c5ad799ebd73
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1817821001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.1817821001
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.3102295732
Short name T1338
Test name
Test status
Simulation time 170259745 ps
CPU time 0.87 seconds
Started Jul 28 07:38:56 PM PDT 24
Finished Jul 28 07:38:57 PM PDT 24
Peak memory 207116 kb
Host smart-2af0d3d7-5f73-4b8c-b63d-1c137ddddfa7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3102295732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.3102295732
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.94170970
Short name T910
Test name
Test status
Simulation time 167458110 ps
CPU time 0.87 seconds
Started Jul 28 07:38:53 PM PDT 24
Finished Jul 28 07:38:54 PM PDT 24
Peak memory 207132 kb
Host smart-b623e9cd-d6d6-4615-9b3e-d00d8bf32c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94170
970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.94170970
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1739618483
Short name T143
Test name
Test status
Simulation time 222435295 ps
CPU time 0.96 seconds
Started Jul 28 07:38:53 PM PDT 24
Finished Jul 28 07:38:55 PM PDT 24
Peak memory 207140 kb
Host smart-2db79437-2fb0-4865-837e-898fdd56e7d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17396
18483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1739618483
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.453027702
Short name T708
Test name
Test status
Simulation time 168906086 ps
CPU time 0.9 seconds
Started Jul 28 07:38:54 PM PDT 24
Finished Jul 28 07:38:55 PM PDT 24
Peak memory 207172 kb
Host smart-859196b6-6d20-41bd-8b8d-08110504d8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45302
7702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.453027702
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3600257459
Short name T682
Test name
Test status
Simulation time 183517129 ps
CPU time 0.96 seconds
Started Jul 28 07:38:56 PM PDT 24
Finished Jul 28 07:38:57 PM PDT 24
Peak memory 207060 kb
Host smart-028fbf1a-1789-49ef-828b-e17af7086d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36002
57459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3600257459
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.928414311
Short name T2686
Test name
Test status
Simulation time 168024833 ps
CPU time 0.89 seconds
Started Jul 28 07:39:10 PM PDT 24
Finished Jul 28 07:39:11 PM PDT 24
Peak memory 207068 kb
Host smart-272b4a92-4aa9-476d-be36-48db1a2d2f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92841
4311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.928414311
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3121216916
Short name T1332
Test name
Test status
Simulation time 162558847 ps
CPU time 0.87 seconds
Started Jul 28 07:38:52 PM PDT 24
Finished Jul 28 07:38:53 PM PDT 24
Peak memory 207304 kb
Host smart-ef1c9d83-70b2-4b1a-bdad-7c4e211ced43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31212
16916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3121216916
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.301975489
Short name T2172
Test name
Test status
Simulation time 227129129 ps
CPU time 1.03 seconds
Started Jul 28 07:39:11 PM PDT 24
Finished Jul 28 07:39:12 PM PDT 24
Peak memory 207208 kb
Host smart-4a1519ee-80fe-47f8-9816-cb33d588e2ec
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=301975489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.301975489
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.288812361
Short name T833
Test name
Test status
Simulation time 142880120 ps
CPU time 0.85 seconds
Started Jul 28 07:39:14 PM PDT 24
Finished Jul 28 07:39:15 PM PDT 24
Peak memory 207112 kb
Host smart-02ac5da0-3f04-4839-94d5-c75666680d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28881
2361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.288812361
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3918510002
Short name T1086
Test name
Test status
Simulation time 43232874 ps
CPU time 0.69 seconds
Started Jul 28 07:39:13 PM PDT 24
Finished Jul 28 07:39:14 PM PDT 24
Peak memory 207052 kb
Host smart-19f6d566-d346-49fe-8e43-b1eb96933db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39185
10002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3918510002
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.4268842211
Short name T1940
Test name
Test status
Simulation time 20158365021 ps
CPU time 54.37 seconds
Started Jul 28 07:38:58 PM PDT 24
Finished Jul 28 07:39:53 PM PDT 24
Peak memory 215496 kb
Host smart-fbaa7c4c-fb0c-4be8-bb90-9535d3f9e1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42688
42211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.4268842211
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.447503355
Short name T1886
Test name
Test status
Simulation time 245938988 ps
CPU time 1.03 seconds
Started Jul 28 07:38:58 PM PDT 24
Finished Jul 28 07:38:59 PM PDT 24
Peak memory 207124 kb
Host smart-af2a7f8e-7d0f-48e4-a2d8-0f3e279a0221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44750
3355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.447503355
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3327465252
Short name T1252
Test name
Test status
Simulation time 249277843 ps
CPU time 1.01 seconds
Started Jul 28 07:39:18 PM PDT 24
Finished Jul 28 07:39:19 PM PDT 24
Peak memory 207136 kb
Host smart-e417307c-de99-4f8f-89e7-5066cee9af07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33274
65252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3327465252
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.3538167128
Short name T164
Test name
Test status
Simulation time 6442887560 ps
CPU time 47.61 seconds
Started Jul 28 07:39:08 PM PDT 24
Finished Jul 28 07:39:55 PM PDT 24
Peak memory 217308 kb
Host smart-ab7133fe-e4b4-4610-9931-632465889f57
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538167128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.3538167128
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.1377506631
Short name T2063
Test name
Test status
Simulation time 3652454163 ps
CPU time 99.5 seconds
Started Jul 28 07:38:56 PM PDT 24
Finished Jul 28 07:40:36 PM PDT 24
Peak memory 215708 kb
Host smart-01f4acf9-2e6d-4b5b-ac8a-d01e0c5f45fa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1377506631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.1377506631
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.898244614
Short name T395
Test name
Test status
Simulation time 20613556291 ps
CPU time 169.59 seconds
Started Jul 28 07:38:59 PM PDT 24
Finished Jul 28 07:41:48 PM PDT 24
Peak memory 217680 kb
Host smart-1daff2c8-8a2a-4ba6-86ec-0a9f4a292783
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=898244614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.898244614
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.69490099
Short name T329
Test name
Test status
Simulation time 230130028 ps
CPU time 1.03 seconds
Started Jul 28 07:39:00 PM PDT 24
Finished Jul 28 07:39:01 PM PDT 24
Peak memory 207172 kb
Host smart-43c1429a-676d-4a3d-a004-db61d06bc9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69490
099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.69490099
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1225908848
Short name T1933
Test name
Test status
Simulation time 201314816 ps
CPU time 0.99 seconds
Started Jul 28 07:39:11 PM PDT 24
Finished Jul 28 07:39:12 PM PDT 24
Peak memory 207160 kb
Host smart-fc7d7070-f12a-42b1-bec0-f23c8df55514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12259
08848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1225908848
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1787743912
Short name T608
Test name
Test status
Simulation time 140641901 ps
CPU time 0.81 seconds
Started Jul 28 07:39:06 PM PDT 24
Finished Jul 28 07:39:07 PM PDT 24
Peak memory 207152 kb
Host smart-fe36ff4e-f931-4059-91c5-13dd86a4fd1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17877
43912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1787743912
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2968551855
Short name T1632
Test name
Test status
Simulation time 151038090 ps
CPU time 0.81 seconds
Started Jul 28 07:39:06 PM PDT 24
Finished Jul 28 07:39:08 PM PDT 24
Peak memory 207176 kb
Host smart-ce4cec5c-df7d-422d-9809-32434ebe4c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29685
51855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2968551855
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.2737930792
Short name T2459
Test name
Test status
Simulation time 200103549 ps
CPU time 0.9 seconds
Started Jul 28 07:39:11 PM PDT 24
Finished Jul 28 07:39:12 PM PDT 24
Peak memory 207116 kb
Host smart-008da045-a0e5-42ad-ac37-039516bfc466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27379
30792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.2737930792
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2918520137
Short name T2057
Test name
Test status
Simulation time 249044239 ps
CPU time 1.11 seconds
Started Jul 28 07:39:13 PM PDT 24
Finished Jul 28 07:39:14 PM PDT 24
Peak memory 207180 kb
Host smart-82fb1eaa-57d1-4635-bbfa-9d1024c3f176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29185
20137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2918520137
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.2343517325
Short name T1129
Test name
Test status
Simulation time 4436869447 ps
CPU time 33.72 seconds
Started Jul 28 07:39:01 PM PDT 24
Finished Jul 28 07:39:35 PM PDT 24
Peak memory 217100 kb
Host smart-a6a65f9c-c335-4d3e-9ae1-cd6b827f47b8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2343517325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.2343517325
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2623228003
Short name T653
Test name
Test status
Simulation time 172065897 ps
CPU time 0.91 seconds
Started Jul 28 07:39:16 PM PDT 24
Finished Jul 28 07:39:17 PM PDT 24
Peak memory 207100 kb
Host smart-ea400045-cd47-4593-a08e-76d61727ceec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26232
28003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2623228003
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3986877437
Short name T427
Test name
Test status
Simulation time 184039268 ps
CPU time 0.84 seconds
Started Jul 28 07:39:11 PM PDT 24
Finished Jul 28 07:39:12 PM PDT 24
Peak memory 207084 kb
Host smart-a978eec8-3f9a-4bf1-a8ec-bfa303662a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39868
77437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3986877437
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.4006572106
Short name T102
Test name
Test status
Simulation time 383697007 ps
CPU time 1.37 seconds
Started Jul 28 07:39:09 PM PDT 24
Finished Jul 28 07:39:10 PM PDT 24
Peak memory 207056 kb
Host smart-aaba78a3-4170-48ef-8ee7-999782c022c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40065
72106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.4006572106
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1987006534
Short name T1256
Test name
Test status
Simulation time 4502538521 ps
CPU time 133.94 seconds
Started Jul 28 07:39:10 PM PDT 24
Finished Jul 28 07:41:24 PM PDT 24
Peak memory 215664 kb
Host smart-53fc0eda-9d92-4781-b7e0-d4ab47e1e59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19870
06534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1987006534
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.1865011432
Short name T482
Test name
Test status
Simulation time 4331920173 ps
CPU time 39.69 seconds
Started Jul 28 07:38:53 PM PDT 24
Finished Jul 28 07:39:33 PM PDT 24
Peak memory 207428 kb
Host smart-f76d0c25-86f4-48de-adcb-9539b66ab187
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865011432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.1865011432
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.438984897
Short name T1333
Test name
Test status
Simulation time 75770866 ps
CPU time 0.7 seconds
Started Jul 28 07:39:23 PM PDT 24
Finished Jul 28 07:39:24 PM PDT 24
Peak memory 207184 kb
Host smart-ae92d584-ccd4-4965-8ba5-2118fe154d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=438984897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.438984897
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.2778244391
Short name T1248
Test name
Test status
Simulation time 4149880020 ps
CPU time 6.06 seconds
Started Jul 28 07:38:59 PM PDT 24
Finished Jul 28 07:39:05 PM PDT 24
Peak memory 207376 kb
Host smart-63ebe8fc-d003-43bc-8e0a-38ead7f88182
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778244391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.2778244391
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.2925147587
Short name T881
Test name
Test status
Simulation time 13334511232 ps
CPU time 15.41 seconds
Started Jul 28 07:39:08 PM PDT 24
Finished Jul 28 07:39:24 PM PDT 24
Peak memory 207352 kb
Host smart-b102241c-bf09-4aff-a171-d00aba68697c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925147587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.2925147587
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.204314836
Short name T1494
Test name
Test status
Simulation time 23299380933 ps
CPU time 28.35 seconds
Started Jul 28 07:39:13 PM PDT 24
Finished Jul 28 07:39:42 PM PDT 24
Peak memory 207364 kb
Host smart-b2416395-1b2e-4b47-b416-88ac8ddbed4d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204314836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon
_wake_resume.204314836
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.7388154
Short name T895
Test name
Test status
Simulation time 224499205 ps
CPU time 0.97 seconds
Started Jul 28 07:38:59 PM PDT 24
Finished Jul 28 07:39:00 PM PDT 24
Peak memory 207168 kb
Host smart-ffe32f3c-98fd-45f8-b6e2-949c68a1175f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73881
54 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.7388154
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1640494368
Short name T1496
Test name
Test status
Simulation time 192496932 ps
CPU time 0.89 seconds
Started Jul 28 07:39:15 PM PDT 24
Finished Jul 28 07:39:16 PM PDT 24
Peak memory 207120 kb
Host smart-941aa782-83c7-4bd1-bc3f-de15b7e7659f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16404
94368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1640494368
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.3813050886
Short name T1969
Test name
Test status
Simulation time 523785934 ps
CPU time 1.59 seconds
Started Jul 28 07:38:59 PM PDT 24
Finished Jul 28 07:39:01 PM PDT 24
Peak memory 207112 kb
Host smart-f22c6936-4d15-4950-be6e-485ed3a1c9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38130
50886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.3813050886
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3741015057
Short name T2528
Test name
Test status
Simulation time 805434992 ps
CPU time 2.23 seconds
Started Jul 28 07:38:58 PM PDT 24
Finished Jul 28 07:39:00 PM PDT 24
Peak memory 207328 kb
Host smart-be80cb31-55bb-4f6f-9515-c6f267ea5bb4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3741015057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3741015057
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.2335911653
Short name T2777
Test name
Test status
Simulation time 7202091678 ps
CPU time 17.64 seconds
Started Jul 28 07:39:18 PM PDT 24
Finished Jul 28 07:39:36 PM PDT 24
Peak memory 207380 kb
Host smart-f95ed8d1-5023-48f0-9ad2-aa71f90b6659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23359
11653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.2335911653
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.4234970515
Short name T1021
Test name
Test status
Simulation time 841234268 ps
CPU time 5.74 seconds
Started Jul 28 07:38:58 PM PDT 24
Finished Jul 28 07:39:04 PM PDT 24
Peak memory 207304 kb
Host smart-21a83543-20ee-44ee-8838-c14ceda143e5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234970515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.4234970515
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.2518021633
Short name T2489
Test name
Test status
Simulation time 442189408 ps
CPU time 1.55 seconds
Started Jul 28 07:39:06 PM PDT 24
Finished Jul 28 07:39:08 PM PDT 24
Peak memory 207088 kb
Host smart-1f336438-9790-415d-8ab1-71e6ba813d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25180
21633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.2518021633
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2761701592
Short name T2671
Test name
Test status
Simulation time 161242955 ps
CPU time 0.86 seconds
Started Jul 28 07:39:09 PM PDT 24
Finished Jul 28 07:39:10 PM PDT 24
Peak memory 207080 kb
Host smart-2be1bf0e-3813-46cf-b78f-c74e6098c100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27617
01592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2761701592
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.151031770
Short name T1151
Test name
Test status
Simulation time 103118358 ps
CPU time 0.75 seconds
Started Jul 28 07:39:05 PM PDT 24
Finished Jul 28 07:39:06 PM PDT 24
Peak memory 207084 kb
Host smart-4f9aab2a-c41b-46c7-81bf-6dcae8d9aebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15103
1770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.151031770
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3622918995
Short name T1054
Test name
Test status
Simulation time 858127399 ps
CPU time 2.63 seconds
Started Jul 28 07:39:04 PM PDT 24
Finished Jul 28 07:39:07 PM PDT 24
Peak memory 207288 kb
Host smart-9552ad46-58eb-4853-8943-6b26440b65fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36229
18995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3622918995
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2529464640
Short name T2544
Test name
Test status
Simulation time 180630895 ps
CPU time 1.76 seconds
Started Jul 28 07:39:13 PM PDT 24
Finished Jul 28 07:39:15 PM PDT 24
Peak memory 207284 kb
Host smart-0a64e819-18fe-4d91-ae85-8179812388b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25294
64640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2529464640
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2406396145
Short name T2308
Test name
Test status
Simulation time 155623732 ps
CPU time 0.89 seconds
Started Jul 28 07:39:05 PM PDT 24
Finished Jul 28 07:39:06 PM PDT 24
Peak memory 207048 kb
Host smart-943ceaa8-10c1-4ae9-b1d3-be8117e79a96
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2406396145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2406396145
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1047958617
Short name T610
Test name
Test status
Simulation time 136272065 ps
CPU time 0.82 seconds
Started Jul 28 07:39:03 PM PDT 24
Finished Jul 28 07:39:04 PM PDT 24
Peak memory 207108 kb
Host smart-2b3d03ca-d79d-4167-9c7d-6f2082a34261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10479
58617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1047958617
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2684249806
Short name T1291
Test name
Test status
Simulation time 220570613 ps
CPU time 1 seconds
Started Jul 28 07:39:17 PM PDT 24
Finished Jul 28 07:39:18 PM PDT 24
Peak memory 207088 kb
Host smart-6d2e068f-9f99-4f6d-a6a6-84c60a358dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26842
49806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2684249806
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.640243709
Short name T994
Test name
Test status
Simulation time 7837139099 ps
CPU time 243.04 seconds
Started Jul 28 07:39:15 PM PDT 24
Finished Jul 28 07:43:18 PM PDT 24
Peak memory 215636 kb
Host smart-0221d705-03ac-4c2f-88db-ab8a28acbeb9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=640243709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.640243709
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.2069169580
Short name T1840
Test name
Test status
Simulation time 4831166468 ps
CPU time 34.07 seconds
Started Jul 28 07:39:15 PM PDT 24
Finished Jul 28 07:39:49 PM PDT 24
Peak memory 207360 kb
Host smart-923ab984-79a6-4da1-b067-966986018458
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2069169580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.2069169580
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.4077068692
Short name T386
Test name
Test status
Simulation time 292804818 ps
CPU time 1.04 seconds
Started Jul 28 07:39:06 PM PDT 24
Finished Jul 28 07:39:07 PM PDT 24
Peak memory 207080 kb
Host smart-89c91b7c-4e7d-41c3-a1e7-4dab890a4c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40770
68692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.4077068692
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2358187303
Short name T2538
Test name
Test status
Simulation time 23312852560 ps
CPU time 25.77 seconds
Started Jul 28 07:39:05 PM PDT 24
Finished Jul 28 07:39:31 PM PDT 24
Peak memory 207400 kb
Host smart-abf844b3-e923-4b64-9e6d-2f0a2034af57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23581
87303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2358187303
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.2605089598
Short name T987
Test name
Test status
Simulation time 3320201853 ps
CPU time 5.1 seconds
Started Jul 28 07:39:10 PM PDT 24
Finished Jul 28 07:39:16 PM PDT 24
Peak memory 207272 kb
Host smart-d1913855-5bce-45ad-a76e-a6689cd4c373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26050
89598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.2605089598
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.1086269826
Short name T1234
Test name
Test status
Simulation time 8687507378 ps
CPU time 258.05 seconds
Started Jul 28 07:39:06 PM PDT 24
Finished Jul 28 07:43:24 PM PDT 24
Peak memory 215580 kb
Host smart-fbea267e-39f5-44c0-b162-fa96fd88ce81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10862
69826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1086269826
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.119099425
Short name T1766
Test name
Test status
Simulation time 5447907865 ps
CPU time 43.28 seconds
Started Jul 28 07:39:07 PM PDT 24
Finished Jul 28 07:39:51 PM PDT 24
Peak memory 217020 kb
Host smart-78b628e1-3256-4fc0-ad9f-93640448fd46
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=119099425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.119099425
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.843994325
Short name T300
Test name
Test status
Simulation time 241132629 ps
CPU time 1.09 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:30 PM PDT 24
Peak memory 207052 kb
Host smart-f10a58a5-ef8b-4154-825b-26fae902d00d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=843994325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.843994325
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1720140446
Short name T2607
Test name
Test status
Simulation time 197801228 ps
CPU time 0.93 seconds
Started Jul 28 07:39:06 PM PDT 24
Finished Jul 28 07:39:07 PM PDT 24
Peak memory 207160 kb
Host smart-a4714309-ddb4-4765-a17a-cce21f11cb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17201
40446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1720140446
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3802626729
Short name T2695
Test name
Test status
Simulation time 4681105511 ps
CPU time 37.94 seconds
Started Jul 28 07:39:07 PM PDT 24
Finished Jul 28 07:39:45 PM PDT 24
Peak memory 215536 kb
Host smart-00252917-0b89-4d3a-a016-36d3a7074f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38026
26729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3802626729
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3847935053
Short name T2294
Test name
Test status
Simulation time 4397133877 ps
CPU time 32.28 seconds
Started Jul 28 07:39:24 PM PDT 24
Finished Jul 28 07:39:56 PM PDT 24
Peak memory 207392 kb
Host smart-365f2a2e-00f3-4d0e-b79c-9ff83ff595a2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3847935053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3847935053
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2179111543
Short name T2628
Test name
Test status
Simulation time 176035272 ps
CPU time 0.87 seconds
Started Jul 28 07:39:14 PM PDT 24
Finished Jul 28 07:39:15 PM PDT 24
Peak memory 207136 kb
Host smart-b398a715-908c-4d7d-9cf9-e69dc73dae17
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2179111543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2179111543
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.4106875333
Short name T341
Test name
Test status
Simulation time 144226664 ps
CPU time 0.87 seconds
Started Jul 28 07:39:18 PM PDT 24
Finished Jul 28 07:39:19 PM PDT 24
Peak memory 207112 kb
Host smart-39dd20c2-0afe-4aa4-8d81-49c5de4a7259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41068
75333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.4106875333
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.938910144
Short name T2497
Test name
Test status
Simulation time 213737886 ps
CPU time 0.96 seconds
Started Jul 28 07:39:06 PM PDT 24
Finished Jul 28 07:39:07 PM PDT 24
Peak memory 207144 kb
Host smart-5e2d170f-eb70-45ad-8313-15d05e464b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93891
0144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.938910144
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1105886418
Short name T111
Test name
Test status
Simulation time 172743906 ps
CPU time 0.93 seconds
Started Jul 28 07:39:24 PM PDT 24
Finished Jul 28 07:39:25 PM PDT 24
Peak memory 207200 kb
Host smart-5c3f2b29-baef-4253-a5b6-475ade7e02f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11058
86418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1105886418
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3644507912
Short name T1024
Test name
Test status
Simulation time 179586320 ps
CPU time 0.96 seconds
Started Jul 28 07:39:25 PM PDT 24
Finished Jul 28 07:39:26 PM PDT 24
Peak memory 207048 kb
Host smart-610a056a-2435-4098-90ee-01b98765809e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36445
07912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3644507912
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1926253701
Short name T2222
Test name
Test status
Simulation time 167515633 ps
CPU time 0.88 seconds
Started Jul 28 07:39:31 PM PDT 24
Finished Jul 28 07:39:32 PM PDT 24
Peak memory 207128 kb
Host smart-96a1d002-d4a3-4940-851a-7802bd62e300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19262
53701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1926253701
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3479877951
Short name T718
Test name
Test status
Simulation time 189447135 ps
CPU time 0.92 seconds
Started Jul 28 07:39:16 PM PDT 24
Finished Jul 28 07:39:17 PM PDT 24
Peak memory 207144 kb
Host smart-4868948b-fa5e-48ed-a09d-6157933b574c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34798
77951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3479877951
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.4144671361
Short name T2665
Test name
Test status
Simulation time 223829846 ps
CPU time 0.98 seconds
Started Jul 28 07:39:14 PM PDT 24
Finished Jul 28 07:39:15 PM PDT 24
Peak memory 207140 kb
Host smart-70fccf51-6e81-4ede-9bc3-ed67261d7746
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4144671361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.4144671361
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.454908452
Short name T186
Test name
Test status
Simulation time 151763132 ps
CPU time 0.86 seconds
Started Jul 28 07:39:09 PM PDT 24
Finished Jul 28 07:39:10 PM PDT 24
Peak memory 207248 kb
Host smart-560052ba-b90a-49c9-8415-48dab5fd0e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45490
8452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.454908452
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.465497442
Short name T2260
Test name
Test status
Simulation time 34738633 ps
CPU time 0.69 seconds
Started Jul 28 07:39:12 PM PDT 24
Finished Jul 28 07:39:12 PM PDT 24
Peak memory 207076 kb
Host smart-e176e4d6-f675-4e97-b9ce-6551370f4347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46549
7442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.465497442
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1604111213
Short name T228
Test name
Test status
Simulation time 18633661296 ps
CPU time 54.1 seconds
Started Jul 28 07:39:16 PM PDT 24
Finished Jul 28 07:40:10 PM PDT 24
Peak memory 215588 kb
Host smart-b8fc9f37-224b-4c85-bd81-ddb8a29b4004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16041
11213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1604111213
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3534005118
Short name T288
Test name
Test status
Simulation time 163360374 ps
CPU time 0.89 seconds
Started Jul 28 07:39:23 PM PDT 24
Finished Jul 28 07:39:24 PM PDT 24
Peak memory 207164 kb
Host smart-1e24fa6c-d73b-4998-9736-22483aa3b42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35340
05118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3534005118
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.708796757
Short name T1957
Test name
Test status
Simulation time 229747391 ps
CPU time 0.96 seconds
Started Jul 28 07:39:09 PM PDT 24
Finished Jul 28 07:39:10 PM PDT 24
Peak memory 207124 kb
Host smart-72a48526-1e9a-4ff5-9e63-263531cf9604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70879
6757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.708796757
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.4014740463
Short name T2458
Test name
Test status
Simulation time 14512056823 ps
CPU time 105.05 seconds
Started Jul 28 07:39:16 PM PDT 24
Finished Jul 28 07:41:01 PM PDT 24
Peak memory 217396 kb
Host smart-f9e21e21-5d70-49cc-aca2-08f40e67c7f0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014740463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.4014740463
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2548890561
Short name T794
Test name
Test status
Simulation time 15999483989 ps
CPU time 123.04 seconds
Started Jul 28 07:39:12 PM PDT 24
Finished Jul 28 07:41:15 PM PDT 24
Peak memory 223672 kb
Host smart-0298fb9b-f6a7-45c3-9093-d7341bf38190
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2548890561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2548890561
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2978824582
Short name T368
Test name
Test status
Simulation time 12092222573 ps
CPU time 252.88 seconds
Started Jul 28 07:39:11 PM PDT 24
Finished Jul 28 07:43:24 PM PDT 24
Peak memory 215488 kb
Host smart-807a6f6a-4824-4731-b618-f404e9c08e07
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978824582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2978824582
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2147759796
Short name T332
Test name
Test status
Simulation time 224656065 ps
CPU time 0.95 seconds
Started Jul 28 07:39:17 PM PDT 24
Finished Jul 28 07:39:18 PM PDT 24
Peak memory 207120 kb
Host smart-e1034e94-704a-42d5-92a2-d19d5f326bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21477
59796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2147759796
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.2070251258
Short name T1555
Test name
Test status
Simulation time 171396344 ps
CPU time 0.86 seconds
Started Jul 28 07:39:10 PM PDT 24
Finished Jul 28 07:39:11 PM PDT 24
Peak memory 207116 kb
Host smart-b01136ff-fe4f-4241-a36c-d385c7320811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20702
51258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.2070251258
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.2094988189
Short name T944
Test name
Test status
Simulation time 175609971 ps
CPU time 0.87 seconds
Started Jul 28 07:39:10 PM PDT 24
Finished Jul 28 07:39:11 PM PDT 24
Peak memory 207116 kb
Host smart-9425381e-83af-4bc9-a19b-e1f4ae05d54d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20949
88189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.2094988189
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1507555083
Short name T950
Test name
Test status
Simulation time 157518076 ps
CPU time 0.85 seconds
Started Jul 28 07:39:17 PM PDT 24
Finished Jul 28 07:39:18 PM PDT 24
Peak memory 207096 kb
Host smart-59ba6044-6d7d-4f78-9141-8c34a765fb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15075
55083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1507555083
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1029884924
Short name T1711
Test name
Test status
Simulation time 148656241 ps
CPU time 0.89 seconds
Started Jul 28 07:39:08 PM PDT 24
Finished Jul 28 07:39:09 PM PDT 24
Peak memory 207128 kb
Host smart-2ca80333-5b32-4f1e-b16a-d3078cd4a0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10298
84924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1029884924
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3212152750
Short name T1198
Test name
Test status
Simulation time 228921818 ps
CPU time 1.01 seconds
Started Jul 28 07:39:15 PM PDT 24
Finished Jul 28 07:39:16 PM PDT 24
Peak memory 207148 kb
Host smart-b5f2e9ef-4098-4f1e-8447-6bec34013fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32121
52750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3212152750
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.998497010
Short name T2313
Test name
Test status
Simulation time 3513213624 ps
CPU time 34.02 seconds
Started Jul 28 07:39:11 PM PDT 24
Finished Jul 28 07:39:45 PM PDT 24
Peak memory 215588 kb
Host smart-42f05c87-a779-4dcd-bfdf-f3d2e5336037
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=998497010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.998497010
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.175403504
Short name T1855
Test name
Test status
Simulation time 201409526 ps
CPU time 0.92 seconds
Started Jul 28 07:39:26 PM PDT 24
Finished Jul 28 07:39:27 PM PDT 24
Peak memory 207060 kb
Host smart-b9f7ae3b-73ca-4c99-9c8c-86672aa74673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17540
3504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.175403504
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2292563271
Short name T1182
Test name
Test status
Simulation time 249343171 ps
CPU time 0.96 seconds
Started Jul 28 07:39:08 PM PDT 24
Finished Jul 28 07:39:09 PM PDT 24
Peak memory 207296 kb
Host smart-de3df8f8-caff-41bc-8a6b-a05608611742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22925
63271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2292563271
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.1268896145
Short name T701
Test name
Test status
Simulation time 1380788542 ps
CPU time 3.47 seconds
Started Jul 28 07:39:10 PM PDT 24
Finished Jul 28 07:39:14 PM PDT 24
Peak memory 207508 kb
Host smart-ce52c02c-db92-4dc0-a2c0-cb5fe41fb6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12688
96145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.1268896145
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.2037739125
Short name T2818
Test name
Test status
Simulation time 3499071659 ps
CPU time 34.07 seconds
Started Jul 28 07:39:23 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 216736 kb
Host smart-b60144d0-8fb9-4245-9b3c-c337302526f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20377
39125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.2037739125
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.402328302
Short name T1961
Test name
Test status
Simulation time 1285225685 ps
CPU time 28.18 seconds
Started Jul 28 07:39:02 PM PDT 24
Finished Jul 28 07:39:30 PM PDT 24
Peak memory 207336 kb
Host smart-7da9ce4e-2eb7-45e4-9b56-b2900b0b71fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402328302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host_
handshake.402328302
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.3647451148
Short name T1931
Test name
Test status
Simulation time 83263472 ps
CPU time 0.7 seconds
Started Jul 28 07:39:28 PM PDT 24
Finished Jul 28 07:39:29 PM PDT 24
Peak memory 207192 kb
Host smart-d165bdaa-e4fc-40f2-81d8-e0927d1ea153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3647451148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.3647451148
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.580504193
Short name T13
Test name
Test status
Simulation time 4013561284 ps
CPU time 6.45 seconds
Started Jul 28 07:39:27 PM PDT 24
Finished Jul 28 07:39:34 PM PDT 24
Peak memory 207304 kb
Host smart-9d795dd2-516b-441e-a045-4ab024fc14ba
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580504193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon
_wake_disconnect.580504193
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1445335738
Short name T2191
Test name
Test status
Simulation time 13396076009 ps
CPU time 14.3 seconds
Started Jul 28 07:39:12 PM PDT 24
Finished Jul 28 07:39:27 PM PDT 24
Peak memory 207408 kb
Host smart-f57b3287-f420-478d-9f48-dae9c73f43cb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445335738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1445335738
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3317408746
Short name T2003
Test name
Test status
Simulation time 23338578168 ps
CPU time 25.86 seconds
Started Jul 28 07:39:21 PM PDT 24
Finished Jul 28 07:39:47 PM PDT 24
Peak memory 207284 kb
Host smart-e46cdbca-396e-4a2f-bfd4-caa9df0efda5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317408746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.3317408746
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3862534867
Short name T758
Test name
Test status
Simulation time 157871727 ps
CPU time 0.86 seconds
Started Jul 28 07:39:20 PM PDT 24
Finished Jul 28 07:39:21 PM PDT 24
Peak memory 207076 kb
Host smart-7daa2c11-d419-4c3f-adac-80937943d69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38625
34867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3862534867
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1266346717
Short name T1984
Test name
Test status
Simulation time 177725842 ps
CPU time 0.91 seconds
Started Jul 28 07:39:15 PM PDT 24
Finished Jul 28 07:39:16 PM PDT 24
Peak memory 207132 kb
Host smart-cb67c186-ba2b-4f13-b29c-4fc30efd3cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12663
46717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1266346717
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.2538538202
Short name T1215
Test name
Test status
Simulation time 243562227 ps
CPU time 1.08 seconds
Started Jul 28 07:39:14 PM PDT 24
Finished Jul 28 07:39:15 PM PDT 24
Peak memory 207140 kb
Host smart-c4d3ec39-9fb1-42bb-9514-d8ef2e8cee37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25385
38202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.2538538202
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.359570155
Short name T660
Test name
Test status
Simulation time 1086520617 ps
CPU time 2.71 seconds
Started Jul 28 07:39:18 PM PDT 24
Finished Jul 28 07:39:21 PM PDT 24
Peak memory 207344 kb
Host smart-32b82777-b60c-4495-96ba-f2ae96ea484c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=359570155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.359570155
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2943901196
Short name T949
Test name
Test status
Simulation time 21049999659 ps
CPU time 43.68 seconds
Started Jul 28 07:39:14 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 207392 kb
Host smart-7d5e6e8f-b644-4ee4-a854-ffa5f8bede15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29439
01196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2943901196
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.3889867539
Short name T2061
Test name
Test status
Simulation time 1576567448 ps
CPU time 37.15 seconds
Started Jul 28 07:39:21 PM PDT 24
Finished Jul 28 07:39:59 PM PDT 24
Peak memory 207272 kb
Host smart-46b09e32-ed3d-4a36-8a15-585fe87d48f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889867539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.3889867539
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.3533449898
Short name T1523
Test name
Test status
Simulation time 409129444 ps
CPU time 1.26 seconds
Started Jul 28 07:39:23 PM PDT 24
Finished Jul 28 07:39:24 PM PDT 24
Peak memory 207096 kb
Host smart-ac475abc-ade0-486b-b435-3f29f9677dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35334
49898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.3533449898
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.160876453
Short name T1938
Test name
Test status
Simulation time 169932611 ps
CPU time 0.84 seconds
Started Jul 28 07:39:19 PM PDT 24
Finished Jul 28 07:39:20 PM PDT 24
Peak memory 207044 kb
Host smart-db92fbc9-c439-4a7c-83d3-58c7ed44de23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16087
6453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.160876453
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3479827544
Short name T2357
Test name
Test status
Simulation time 45270590 ps
CPU time 0.69 seconds
Started Jul 28 07:39:14 PM PDT 24
Finished Jul 28 07:39:15 PM PDT 24
Peak memory 207056 kb
Host smart-ffb85105-71a2-425c-bfb5-ec1c7347cce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34798
27544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3479827544
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.3664394378
Short name T2071
Test name
Test status
Simulation time 880939681 ps
CPU time 2.27 seconds
Started Jul 28 07:39:28 PM PDT 24
Finished Jul 28 07:39:30 PM PDT 24
Peak memory 207232 kb
Host smart-870ac905-1573-4dc1-9f3c-c98ccb264dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36643
94378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.3664394378
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1013909384
Short name T425
Test name
Test status
Simulation time 199179937 ps
CPU time 2.52 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:31 PM PDT 24
Peak memory 207196 kb
Host smart-0c7d21c7-15bb-4d51-b167-223a11fa28e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10139
09384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1013909384
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.1426250161
Short name T982
Test name
Test status
Simulation time 223923378 ps
CPU time 1.17 seconds
Started Jul 28 07:39:20 PM PDT 24
Finished Jul 28 07:39:22 PM PDT 24
Peak memory 215468 kb
Host smart-a099879e-e888-4461-bd14-d1948053dc86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1426250161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.1426250161
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.4280454283
Short name T2865
Test name
Test status
Simulation time 142186803 ps
CPU time 0.82 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:30 PM PDT 24
Peak memory 206996 kb
Host smart-15ebdba0-267a-47c4-b64a-8a3e98e6b31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42804
54283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.4280454283
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3752050466
Short name T2784
Test name
Test status
Simulation time 257832501 ps
CPU time 0.99 seconds
Started Jul 28 07:39:13 PM PDT 24
Finished Jul 28 07:39:14 PM PDT 24
Peak memory 207264 kb
Host smart-9c5c1551-c5f9-419a-b720-824b81368c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37520
50466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3752050466
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.1954344346
Short name T2147
Test name
Test status
Simulation time 7166268267 ps
CPU time 52.37 seconds
Started Jul 28 07:39:28 PM PDT 24
Finished Jul 28 07:40:21 PM PDT 24
Peak memory 215512 kb
Host smart-6cd34c08-d830-41b9-8393-99c0ef505cd8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1954344346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.1954344346
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.3974495465
Short name T1691
Test name
Test status
Simulation time 10893915051 ps
CPU time 80.78 seconds
Started Jul 28 07:39:28 PM PDT 24
Finished Jul 28 07:40:49 PM PDT 24
Peak memory 207312 kb
Host smart-321502b4-f441-4f47-b69d-3ec047caf099
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3974495465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.3974495465
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.3154257934
Short name T984
Test name
Test status
Simulation time 201599751 ps
CPU time 0.95 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:31 PM PDT 24
Peak memory 207108 kb
Host smart-2e03fe5b-9a7d-44df-972c-5c9ba9f4d634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31542
57934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3154257934
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.516878249
Short name T1223
Test name
Test status
Simulation time 23323431882 ps
CPU time 27.25 seconds
Started Jul 28 07:39:11 PM PDT 24
Finished Jul 28 07:39:38 PM PDT 24
Peak memory 207512 kb
Host smart-cfa2aea8-1198-4cec-8d34-fe36852b21b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51687
8249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.516878249
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1699054991
Short name T2703
Test name
Test status
Simulation time 3261934797 ps
CPU time 5.01 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:34 PM PDT 24
Peak memory 207368 kb
Host smart-f921d8b8-97d0-4efd-a398-d5222c4daf64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16990
54991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1699054991
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.797342618
Short name T472
Test name
Test status
Simulation time 6499059270 ps
CPU time 65.7 seconds
Started Jul 28 07:39:21 PM PDT 24
Finished Jul 28 07:40:26 PM PDT 24
Peak memory 217464 kb
Host smart-b54eda7a-1c7d-4174-a72a-7952c78a7f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79734
2618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.797342618
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.456850773
Short name T478
Test name
Test status
Simulation time 5845411415 ps
CPU time 58.99 seconds
Started Jul 28 07:39:14 PM PDT 24
Finished Jul 28 07:40:13 PM PDT 24
Peak memory 207368 kb
Host smart-64ea03aa-65a0-4d4c-9ad1-6537752f3eb8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=456850773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.456850773
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.425348555
Short name T2327
Test name
Test status
Simulation time 278710653 ps
CPU time 1.1 seconds
Started Jul 28 07:39:19 PM PDT 24
Finished Jul 28 07:39:20 PM PDT 24
Peak memory 207208 kb
Host smart-ecd6fcbb-97eb-47a3-a536-16e3b9ada60d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=425348555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.425348555
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3688166497
Short name T1741
Test name
Test status
Simulation time 192281095 ps
CPU time 0.91 seconds
Started Jul 28 07:39:18 PM PDT 24
Finished Jul 28 07:39:19 PM PDT 24
Peak memory 207284 kb
Host smart-92b5c258-4ece-4017-862a-010194c0c797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36881
66497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3688166497
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.2520081041
Short name T1551
Test name
Test status
Simulation time 5786367995 ps
CPU time 44.48 seconds
Started Jul 28 07:39:19 PM PDT 24
Finished Jul 28 07:40:03 PM PDT 24
Peak memory 215528 kb
Host smart-5a334ca3-a124-48bc-b71c-86092a7b375f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25200
81041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.2520081041
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.3501793861
Short name T1349
Test name
Test status
Simulation time 4701080269 ps
CPU time 35.04 seconds
Started Jul 28 07:39:22 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 216828 kb
Host smart-a1c64895-6bbb-4cf3-87ec-fc2e34385475
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3501793861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.3501793861
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.1163453956
Short name T2231
Test name
Test status
Simulation time 157734114 ps
CPU time 0.94 seconds
Started Jul 28 07:39:15 PM PDT 24
Finished Jul 28 07:39:16 PM PDT 24
Peak memory 207188 kb
Host smart-0db7a338-c872-4f04-afa5-2fbee420a8fd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1163453956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.1163453956
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2417392641
Short name T1675
Test name
Test status
Simulation time 193103293 ps
CPU time 0.9 seconds
Started Jul 28 07:39:23 PM PDT 24
Finished Jul 28 07:39:24 PM PDT 24
Peak memory 207080 kb
Host smart-c9e864f7-b0d6-4962-96e2-1bd75ae44115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24173
92641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2417392641
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.2617385675
Short name T140
Test name
Test status
Simulation time 224272786 ps
CPU time 0.96 seconds
Started Jul 28 07:39:16 PM PDT 24
Finished Jul 28 07:39:17 PM PDT 24
Peak memory 206996 kb
Host smart-d52894b3-36a4-4228-96eb-f25512759e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26173
85675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2617385675
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1302365924
Short name T2470
Test name
Test status
Simulation time 151973752 ps
CPU time 0.82 seconds
Started Jul 28 07:39:15 PM PDT 24
Finished Jul 28 07:39:16 PM PDT 24
Peak memory 207072 kb
Host smart-6e1ba05f-ae48-49c0-a05d-723f63cc3b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13023
65924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1302365924
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2003083552
Short name T659
Test name
Test status
Simulation time 167311385 ps
CPU time 0.88 seconds
Started Jul 28 07:39:18 PM PDT 24
Finished Jul 28 07:39:19 PM PDT 24
Peak memory 207120 kb
Host smart-a352f1c1-eb53-47c9-894c-7a565c3321a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20030
83552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2003083552
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3686972172
Short name T1891
Test name
Test status
Simulation time 150336783 ps
CPU time 0.81 seconds
Started Jul 28 07:39:21 PM PDT 24
Finished Jul 28 07:39:22 PM PDT 24
Peak memory 207048 kb
Host smart-8d18afb2-2dc9-4f56-9342-afffb5fd6524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36869
72172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3686972172
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1596299454
Short name T151
Test name
Test status
Simulation time 155156831 ps
CPU time 0.86 seconds
Started Jul 28 07:39:24 PM PDT 24
Finished Jul 28 07:39:25 PM PDT 24
Peak memory 207048 kb
Host smart-1b86751b-0911-438d-bcd2-04ae42a7b8d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15962
99454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1596299454
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1232445445
Short name T2270
Test name
Test status
Simulation time 195873324 ps
CPU time 0.96 seconds
Started Jul 28 07:39:24 PM PDT 24
Finished Jul 28 07:39:25 PM PDT 24
Peak memory 207120 kb
Host smart-8c908da7-c55f-4e6f-a90b-dc9a65f7203e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1232445445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1232445445
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.3437512100
Short name T2792
Test name
Test status
Simulation time 144107703 ps
CPU time 0.86 seconds
Started Jul 28 07:39:19 PM PDT 24
Finished Jul 28 07:39:20 PM PDT 24
Peak memory 207064 kb
Host smart-5c2192be-606f-42ad-a16f-82d7ba28f5ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34375
12100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.3437512100
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3581727053
Short name T2317
Test name
Test status
Simulation time 42186751 ps
CPU time 0.69 seconds
Started Jul 28 07:39:30 PM PDT 24
Finished Jul 28 07:39:31 PM PDT 24
Peak memory 207024 kb
Host smart-72e391be-999f-4206-bc1b-cf4255b7b3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35817
27053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3581727053
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3974099371
Short name T237
Test name
Test status
Simulation time 13875231839 ps
CPU time 35.25 seconds
Started Jul 28 07:39:20 PM PDT 24
Finished Jul 28 07:39:56 PM PDT 24
Peak memory 223716 kb
Host smart-1cf51584-57b6-4d88-bc9a-62a16d500ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39740
99371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3974099371
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3315031940
Short name T1510
Test name
Test status
Simulation time 160979730 ps
CPU time 0.87 seconds
Started Jul 28 07:39:25 PM PDT 24
Finished Jul 28 07:39:26 PM PDT 24
Peak memory 207044 kb
Host smart-9b14ff1f-d536-4119-b00d-a85f777b852a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33150
31940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3315031940
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.172787191
Short name T904
Test name
Test status
Simulation time 248380743 ps
CPU time 0.99 seconds
Started Jul 28 07:39:18 PM PDT 24
Finished Jul 28 07:39:19 PM PDT 24
Peak memory 207092 kb
Host smart-3df61ddd-5f1f-4e1a-8a4f-7fd914128de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17278
7191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.172787191
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.349254042
Short name T809
Test name
Test status
Simulation time 11929158960 ps
CPU time 89.32 seconds
Started Jul 28 07:39:21 PM PDT 24
Finished Jul 28 07:40:50 PM PDT 24
Peak memory 217588 kb
Host smart-6a2b6b7c-b9ab-494d-9fae-aef8af98f315
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=349254042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.349254042
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.3954410263
Short name T2404
Test name
Test status
Simulation time 5549572981 ps
CPU time 137.04 seconds
Started Jul 28 07:39:27 PM PDT 24
Finished Jul 28 07:41:44 PM PDT 24
Peak memory 215516 kb
Host smart-e39c7605-cf19-4181-b33a-b6170e91f5c4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3954410263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.3954410263
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.4285739728
Short name T2516
Test name
Test status
Simulation time 14602154979 ps
CPU time 119.31 seconds
Started Jul 28 07:39:23 PM PDT 24
Finished Jul 28 07:41:23 PM PDT 24
Peak memory 217176 kb
Host smart-cf32932f-21e3-48ef-978f-ddfe3ff9853e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285739728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.4285739728
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.169487137
Short name T2706
Test name
Test status
Simulation time 245951010 ps
CPU time 1.05 seconds
Started Jul 28 07:39:20 PM PDT 24
Finished Jul 28 07:39:21 PM PDT 24
Peak memory 207080 kb
Host smart-1a78fcee-b756-47fe-a006-d73dc855aca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16948
7137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.169487137
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.3332363784
Short name T927
Test name
Test status
Simulation time 163779753 ps
CPU time 0.86 seconds
Started Jul 28 07:39:28 PM PDT 24
Finished Jul 28 07:39:29 PM PDT 24
Peak memory 207164 kb
Host smart-61aa0b4f-1f5c-4abf-8f57-4e8c1cceb3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33323
63784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.3332363784
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2704049466
Short name T70
Test name
Test status
Simulation time 210050790 ps
CPU time 0.91 seconds
Started Jul 28 07:39:21 PM PDT 24
Finished Jul 28 07:39:22 PM PDT 24
Peak memory 207168 kb
Host smart-8fe9a3a2-161b-4852-9ebc-262ab947bc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27040
49466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2704049466
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3479718300
Short name T2303
Test name
Test status
Simulation time 241409777 ps
CPU time 0.92 seconds
Started Jul 28 07:39:21 PM PDT 24
Finished Jul 28 07:39:23 PM PDT 24
Peak memory 207044 kb
Host smart-209ebf39-ca8c-4798-96a8-57f8c3a0af84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34797
18300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3479718300
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.480123278
Short name T330
Test name
Test status
Simulation time 191115915 ps
CPU time 0.86 seconds
Started Jul 28 07:39:27 PM PDT 24
Finished Jul 28 07:39:28 PM PDT 24
Peak memory 207136 kb
Host smart-26c32f98-d8fe-485b-b18a-4f145ebf8dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48012
3278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.480123278
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.37147126
Short name T639
Test name
Test status
Simulation time 246807238 ps
CPU time 1.02 seconds
Started Jul 28 07:39:21 PM PDT 24
Finished Jul 28 07:39:23 PM PDT 24
Peak memory 207076 kb
Host smart-7bcd88b8-9c51-4459-a6a8-ea0b29af9bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37147
126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.37147126
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.3361296245
Short name T873
Test name
Test status
Simulation time 4570738368 ps
CPU time 47.24 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:40:16 PM PDT 24
Peak memory 217024 kb
Host smart-faf5b07f-1b34-440d-922d-651906e6f7d1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3361296245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3361296245
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2102577296
Short name T2238
Test name
Test status
Simulation time 185399101 ps
CPU time 0.92 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:31 PM PDT 24
Peak memory 207156 kb
Host smart-8c2039e6-7ac3-4597-a105-946173783596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21025
77296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2102577296
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2710449662
Short name T334
Test name
Test status
Simulation time 166870278 ps
CPU time 0.86 seconds
Started Jul 28 07:39:16 PM PDT 24
Finished Jul 28 07:39:17 PM PDT 24
Peak memory 207168 kb
Host smart-24df93a3-725d-47ef-a871-47e6fea3f94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27104
49662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2710449662
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.2973813802
Short name T665
Test name
Test status
Simulation time 902912867 ps
CPU time 2.31 seconds
Started Jul 28 07:39:26 PM PDT 24
Finished Jul 28 07:39:29 PM PDT 24
Peak memory 207296 kb
Host smart-20e5c36f-4681-4ff5-9aca-5c38a7bf2a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29738
13802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2973813802
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.2616797181
Short name T1912
Test name
Test status
Simulation time 7911474661 ps
CPU time 231.54 seconds
Started Jul 28 07:39:21 PM PDT 24
Finished Jul 28 07:43:13 PM PDT 24
Peak memory 215576 kb
Host smart-c55d3aa0-4aa5-4b51-b5c1-cfc8bd54c3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26167
97181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.2616797181
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.3830871818
Short name T295
Test name
Test status
Simulation time 3842276590 ps
CPU time 33.16 seconds
Started Jul 28 07:39:30 PM PDT 24
Finished Jul 28 07:40:04 PM PDT 24
Peak memory 207360 kb
Host smart-9034baa8-b7ce-42c6-a3ec-38119b212328
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830871818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.3830871818
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.2472501649
Short name T491
Test name
Test status
Simulation time 69330088 ps
CPU time 0.72 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:29 PM PDT 24
Peak memory 207112 kb
Host smart-d712643d-602b-4255-afc5-c4380a890ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2472501649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.2472501649
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3486351292
Short name T2588
Test name
Test status
Simulation time 3732887788 ps
CPU time 6.18 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:36 PM PDT 24
Peak memory 207284 kb
Host smart-a00f88ca-7abd-4a34-ad95-b4fa1c5799da
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486351292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.3486351292
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.4242640191
Short name T1727
Test name
Test status
Simulation time 13349864500 ps
CPU time 15.44 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:45 PM PDT 24
Peak memory 207432 kb
Host smart-593c9477-b154-49db-bb37-50a52515020d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242640191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.4242640191
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.3495229356
Short name T2461
Test name
Test status
Simulation time 23462046147 ps
CPU time 28.78 seconds
Started Jul 28 07:39:31 PM PDT 24
Finished Jul 28 07:40:00 PM PDT 24
Peak memory 207336 kb
Host smart-1671b7d6-9b0d-47e5-98da-5577ee741f47
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495229356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.3495229356
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.24644045
Short name T1832
Test name
Test status
Simulation time 196957622 ps
CPU time 0.94 seconds
Started Jul 28 07:39:20 PM PDT 24
Finished Jul 28 07:39:21 PM PDT 24
Peak memory 207124 kb
Host smart-33b3510c-f81b-44a1-945f-54c91c3b5908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24644
045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.24644045
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1669534718
Short name T1167
Test name
Test status
Simulation time 151470274 ps
CPU time 0.85 seconds
Started Jul 28 07:39:18 PM PDT 24
Finished Jul 28 07:39:19 PM PDT 24
Peak memory 207240 kb
Host smart-9b2d497c-9a6c-4d90-a193-2f9e46458b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16695
34718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1669534718
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.254310355
Short name T600
Test name
Test status
Simulation time 332808021 ps
CPU time 1.27 seconds
Started Jul 28 07:39:22 PM PDT 24
Finished Jul 28 07:39:23 PM PDT 24
Peak memory 207076 kb
Host smart-51a8d326-7236-4dc8-bc27-f0a088549962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25431
0355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.254310355
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3823496145
Short name T2301
Test name
Test status
Simulation time 1348945438 ps
CPU time 3.34 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:32 PM PDT 24
Peak memory 207368 kb
Host smart-63a7f1cb-4d71-4ee9-a437-5fb0f02992d8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3823496145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3823496145
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2833860166
Short name T1455
Test name
Test status
Simulation time 17676086703 ps
CPU time 43.13 seconds
Started Jul 28 07:39:34 PM PDT 24
Finished Jul 28 07:40:17 PM PDT 24
Peak memory 207380 kb
Host smart-32e7863a-6e28-457f-90d2-1f9940236d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28338
60166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2833860166
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.1362302099
Short name T1004
Test name
Test status
Simulation time 1070109023 ps
CPU time 8.65 seconds
Started Jul 28 07:39:22 PM PDT 24
Finished Jul 28 07:39:31 PM PDT 24
Peak memory 207340 kb
Host smart-ac04eaab-6b9b-4e87-b8fb-f98977648a1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362302099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.1362302099
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.4194427629
Short name T101
Test name
Test status
Simulation time 434536572 ps
CPU time 1.48 seconds
Started Jul 28 07:39:33 PM PDT 24
Finished Jul 28 07:39:35 PM PDT 24
Peak memory 207008 kb
Host smart-e7ebb67f-b0f6-4a80-8f5c-71c9ec6e73eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41944
27629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.4194427629
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.750880907
Short name T1403
Test name
Test status
Simulation time 135896133 ps
CPU time 0.83 seconds
Started Jul 28 07:39:36 PM PDT 24
Finished Jul 28 07:39:37 PM PDT 24
Peak memory 207096 kb
Host smart-219fab18-5505-4b7c-855e-e9a7ccabfeca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75088
0907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.750880907
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3517478812
Short name T2785
Test name
Test status
Simulation time 44591841 ps
CPU time 0.71 seconds
Started Jul 28 07:39:19 PM PDT 24
Finished Jul 28 07:39:20 PM PDT 24
Peak memory 207012 kb
Host smart-a3613542-86ee-4a32-b851-7d49a8cb1ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35174
78812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3517478812
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.2804653976
Short name T2065
Test name
Test status
Simulation time 847511612 ps
CPU time 2.23 seconds
Started Jul 28 07:39:23 PM PDT 24
Finished Jul 28 07:39:25 PM PDT 24
Peak memory 207408 kb
Host smart-02a2c695-44c6-4049-896f-dfe6c05bd414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28046
53976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.2804653976
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2464639119
Short name T2815
Test name
Test status
Simulation time 173832743 ps
CPU time 2.12 seconds
Started Jul 28 07:39:21 PM PDT 24
Finished Jul 28 07:39:23 PM PDT 24
Peak memory 207212 kb
Host smart-0b255899-e221-4729-84f5-2f0b9247cf44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24646
39119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2464639119
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.956011610
Short name T1943
Test name
Test status
Simulation time 185594220 ps
CPU time 1 seconds
Started Jul 28 07:39:20 PM PDT 24
Finished Jul 28 07:39:21 PM PDT 24
Peak memory 207300 kb
Host smart-fcbc6411-e9cb-4918-ba12-1419da5b24d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=956011610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.956011610
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.622997691
Short name T738
Test name
Test status
Simulation time 191602173 ps
CPU time 0.88 seconds
Started Jul 28 07:39:20 PM PDT 24
Finished Jul 28 07:39:21 PM PDT 24
Peak memory 207072 kb
Host smart-10ed796a-cc0d-4f75-bfbb-03251efef1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62299
7691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.622997691
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2911390464
Short name T1464
Test name
Test status
Simulation time 167508550 ps
CPU time 0.86 seconds
Started Jul 28 07:39:28 PM PDT 24
Finished Jul 28 07:39:29 PM PDT 24
Peak memory 207044 kb
Host smart-abfdfc3f-e698-411f-aa44-6e431f5074ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29113
90464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2911390464
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.1060629012
Short name T1272
Test name
Test status
Simulation time 7775975679 ps
CPU time 57.96 seconds
Started Jul 28 07:39:30 PM PDT 24
Finished Jul 28 07:40:28 PM PDT 24
Peak memory 215640 kb
Host smart-1b2e2c9d-6298-4b20-b312-15ca31716b48
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1060629012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.1060629012
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.811419380
Short name T560
Test name
Test status
Simulation time 11271971607 ps
CPU time 82.99 seconds
Started Jul 28 07:39:19 PM PDT 24
Finished Jul 28 07:40:42 PM PDT 24
Peak memory 207352 kb
Host smart-83475b1d-7c98-45bf-b47b-2e3f85b0bb51
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=811419380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.811419380
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.2134027436
Short name T396
Test name
Test status
Simulation time 226101640 ps
CPU time 0.97 seconds
Started Jul 28 07:39:21 PM PDT 24
Finished Jul 28 07:39:22 PM PDT 24
Peak memory 207172 kb
Host smart-868b70ec-b6eb-4992-b168-6bc6338fac20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21340
27436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.2134027436
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.261525233
Short name T2474
Test name
Test status
Simulation time 23314106121 ps
CPU time 29.48 seconds
Started Jul 28 07:39:33 PM PDT 24
Finished Jul 28 07:40:03 PM PDT 24
Peak memory 207384 kb
Host smart-e3931348-29f6-4b80-84cf-1b0fb53a85ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26152
5233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.261525233
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1728978133
Short name T1070
Test name
Test status
Simulation time 3304305846 ps
CPU time 5.09 seconds
Started Jul 28 07:39:30 PM PDT 24
Finished Jul 28 07:39:35 PM PDT 24
Peak memory 207380 kb
Host smart-600f16be-b644-47a8-abb4-a1f47b94f483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17289
78133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1728978133
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3562717270
Short name T2651
Test name
Test status
Simulation time 7776532164 ps
CPU time 57.44 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:40:26 PM PDT 24
Peak memory 217292 kb
Host smart-d40ed707-3d54-4da9-940d-7e2280d575df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35627
17270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3562717270
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.4130281164
Short name T2750
Test name
Test status
Simulation time 5688212976 ps
CPU time 46.08 seconds
Started Jul 28 07:39:32 PM PDT 24
Finished Jul 28 07:40:18 PM PDT 24
Peak memory 215536 kb
Host smart-f051177d-88df-427f-a317-faaca58dd171
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4130281164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.4130281164
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.807457012
Short name T1753
Test name
Test status
Simulation time 240414562 ps
CPU time 0.98 seconds
Started Jul 28 07:39:27 PM PDT 24
Finished Jul 28 07:39:28 PM PDT 24
Peak memory 207096 kb
Host smart-b3cec638-11de-47f3-ae7b-914f91545e90
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=807457012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.807457012
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3653583253
Short name T2553
Test name
Test status
Simulation time 215316410 ps
CPU time 0.95 seconds
Started Jul 28 07:39:24 PM PDT 24
Finished Jul 28 07:39:25 PM PDT 24
Peak memory 207140 kb
Host smart-0c4e079d-7646-4f5e-9747-a514c455115b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36535
83253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3653583253
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.733772934
Short name T684
Test name
Test status
Simulation time 5301052362 ps
CPU time 153.12 seconds
Started Jul 28 07:39:30 PM PDT 24
Finished Jul 28 07:42:04 PM PDT 24
Peak memory 215604 kb
Host smart-3c71cb58-070b-4836-a6e3-87024ceed695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73377
2934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.733772934
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.222583786
Short name T598
Test name
Test status
Simulation time 5865575635 ps
CPU time 168.81 seconds
Started Jul 28 07:39:23 PM PDT 24
Finished Jul 28 07:42:12 PM PDT 24
Peak memory 215548 kb
Host smart-699d45e7-b035-428d-95de-18f5495de0ce
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=222583786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.222583786
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.2995812581
Short name T897
Test name
Test status
Simulation time 169040799 ps
CPU time 0.89 seconds
Started Jul 28 07:39:30 PM PDT 24
Finished Jul 28 07:39:31 PM PDT 24
Peak memory 207148 kb
Host smart-e2bd73bb-b38c-4e2b-bcc7-c2302ef5ce1b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2995812581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.2995812581
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3443813400
Short name T2397
Test name
Test status
Simulation time 214112861 ps
CPU time 0.94 seconds
Started Jul 28 07:39:25 PM PDT 24
Finished Jul 28 07:39:26 PM PDT 24
Peak memory 207168 kb
Host smart-6a84f8e7-2815-4287-9e22-cac440201e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34438
13400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3443813400
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1930449531
Short name T125
Test name
Test status
Simulation time 169987068 ps
CPU time 0.9 seconds
Started Jul 28 07:39:28 PM PDT 24
Finished Jul 28 07:39:29 PM PDT 24
Peak memory 207052 kb
Host smart-c75d3dff-65c0-47b0-8e8d-ccb630a2606b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19304
49531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1930449531
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1995607873
Short name T918
Test name
Test status
Simulation time 199756379 ps
CPU time 0.89 seconds
Started Jul 28 07:39:30 PM PDT 24
Finished Jul 28 07:39:31 PM PDT 24
Peak memory 207200 kb
Host smart-0e7f777c-81c9-4e21-ad37-1d5326a4b9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19956
07873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1995607873
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.4013711373
Short name T889
Test name
Test status
Simulation time 159034765 ps
CPU time 0.93 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:30 PM PDT 24
Peak memory 207160 kb
Host smart-c0036104-28b8-4582-a48e-2b594e9b35f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40137
11373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.4013711373
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3776801006
Short name T1153
Test name
Test status
Simulation time 188352584 ps
CPU time 0.88 seconds
Started Jul 28 07:39:24 PM PDT 24
Finished Jul 28 07:39:25 PM PDT 24
Peak memory 207116 kb
Host smart-be71bf8c-54bb-4101-b471-7235b85a10e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37768
01006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3776801006
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.2546561655
Short name T2053
Test name
Test status
Simulation time 200426092 ps
CPU time 0.92 seconds
Started Jul 28 07:39:22 PM PDT 24
Finished Jul 28 07:39:23 PM PDT 24
Peak memory 207140 kb
Host smart-86649841-f176-4db3-a2ef-7a49c0e681e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25465
61655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.2546561655
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.3947964749
Short name T2579
Test name
Test status
Simulation time 230918071 ps
CPU time 1.06 seconds
Started Jul 28 07:39:26 PM PDT 24
Finished Jul 28 07:39:27 PM PDT 24
Peak memory 207136 kb
Host smart-44d803a3-f987-47e3-9e5c-19beaf8f7e80
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3947964749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3947964749
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.4194399498
Short name T1841
Test name
Test status
Simulation time 200679272 ps
CPU time 0.95 seconds
Started Jul 28 07:39:26 PM PDT 24
Finished Jul 28 07:39:27 PM PDT 24
Peak memory 207044 kb
Host smart-c0b67885-205a-4345-aa18-7bf0b8263e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41943
99498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.4194399498
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3499392726
Short name T1774
Test name
Test status
Simulation time 35765715 ps
CPU time 0.66 seconds
Started Jul 28 07:39:28 PM PDT 24
Finished Jul 28 07:39:29 PM PDT 24
Peak memory 207052 kb
Host smart-46995453-fa61-41b1-baf0-ab1e6cd92c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34993
92726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3499392726
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1295730116
Short name T1071
Test name
Test status
Simulation time 7222105429 ps
CPU time 17.44 seconds
Started Jul 28 07:39:25 PM PDT 24
Finished Jul 28 07:39:42 PM PDT 24
Peak memory 215584 kb
Host smart-8a31b6eb-ade5-4fa9-9840-9a7e6ff244c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12957
30116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1295730116
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3880171661
Short name T961
Test name
Test status
Simulation time 230221015 ps
CPU time 0.99 seconds
Started Jul 28 07:39:21 PM PDT 24
Finished Jul 28 07:39:23 PM PDT 24
Peak memory 207164 kb
Host smart-dc6e60bb-6587-4d8d-aba9-5c92b32ea082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38801
71661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3880171661
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2062591722
Short name T2501
Test name
Test status
Simulation time 212633658 ps
CPU time 0.98 seconds
Started Jul 28 07:39:23 PM PDT 24
Finished Jul 28 07:39:24 PM PDT 24
Peak memory 207120 kb
Host smart-53a3bdf8-33ef-4f83-b19f-5133e78caa20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20625
91722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2062591722
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.4183045405
Short name T2729
Test name
Test status
Simulation time 14735679556 ps
CPU time 82.09 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:40:52 PM PDT 24
Peak memory 223732 kb
Host smart-84ba5dab-6e67-48d0-8409-7f8a5e01fc18
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183045405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.4183045405
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.3558345880
Short name T781
Test name
Test status
Simulation time 6623373916 ps
CPU time 37.96 seconds
Started Jul 28 07:39:32 PM PDT 24
Finished Jul 28 07:40:10 PM PDT 24
Peak memory 223556 kb
Host smart-0bdfc4d4-4180-4a5e-991b-796b4b9eaa1f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558345880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.3558345880
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.3669003904
Short name T654
Test name
Test status
Simulation time 164422518 ps
CPU time 0.87 seconds
Started Jul 28 07:39:25 PM PDT 24
Finished Jul 28 07:39:26 PM PDT 24
Peak memory 207056 kb
Host smart-8708e156-216e-4d82-98bc-0d22a9010dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36690
03904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.3669003904
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.2382047775
Short name T2239
Test name
Test status
Simulation time 229066988 ps
CPU time 1.01 seconds
Started Jul 28 07:39:35 PM PDT 24
Finished Jul 28 07:39:36 PM PDT 24
Peak memory 207152 kb
Host smart-42c5bab7-a558-4ba0-8f84-637e54cd4121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23820
47775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.2382047775
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.550712072
Short name T2682
Test name
Test status
Simulation time 188269014 ps
CPU time 0.93 seconds
Started Jul 28 07:39:34 PM PDT 24
Finished Jul 28 07:39:35 PM PDT 24
Peak memory 207072 kb
Host smart-ba1c346f-1107-4951-867b-602dcae5aeaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55071
2072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.550712072
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3877052999
Short name T1112
Test name
Test status
Simulation time 168325969 ps
CPU time 0.89 seconds
Started Jul 28 07:39:31 PM PDT 24
Finished Jul 28 07:39:32 PM PDT 24
Peak memory 207020 kb
Host smart-bc9be424-0de3-4f74-bc1e-6730bd206286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38770
52999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3877052999
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.4126869102
Short name T2203
Test name
Test status
Simulation time 220768857 ps
CPU time 0.91 seconds
Started Jul 28 07:39:39 PM PDT 24
Finished Jul 28 07:39:40 PM PDT 24
Peak memory 207108 kb
Host smart-661449ec-b582-494c-94b4-f23b3aaa9f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41268
69102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.4126869102
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3078277404
Short name T1482
Test name
Test status
Simulation time 218369349 ps
CPU time 1 seconds
Started Jul 28 07:39:31 PM PDT 24
Finished Jul 28 07:39:32 PM PDT 24
Peak memory 207044 kb
Host smart-e4af4169-5dd8-4715-86d4-e83d9651b445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30782
77404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3078277404
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1914896980
Short name T622
Test name
Test status
Simulation time 3354104139 ps
CPU time 95.97 seconds
Started Jul 28 07:39:34 PM PDT 24
Finished Jul 28 07:41:10 PM PDT 24
Peak memory 215612 kb
Host smart-ab035532-1d8d-44ba-a55b-30257c4f92bd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1914896980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1914896980
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1275191406
Short name T274
Test name
Test status
Simulation time 211243499 ps
CPU time 0.94 seconds
Started Jul 28 07:39:33 PM PDT 24
Finished Jul 28 07:39:34 PM PDT 24
Peak memory 207120 kb
Host smart-87a67c62-fbeb-46d0-800c-6b9b8fdbe028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12751
91406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1275191406
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2828100876
Short name T2422
Test name
Test status
Simulation time 191360979 ps
CPU time 0.9 seconds
Started Jul 28 07:39:38 PM PDT 24
Finished Jul 28 07:39:39 PM PDT 24
Peak memory 207124 kb
Host smart-3b04273e-6c8e-4831-9ac5-d393e5da42cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28281
00876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2828100876
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.3499194532
Short name T2373
Test name
Test status
Simulation time 1141312096 ps
CPU time 2.91 seconds
Started Jul 28 07:39:35 PM PDT 24
Finished Jul 28 07:39:38 PM PDT 24
Peak memory 207228 kb
Host smart-2b64f934-b38f-4fb1-9436-11831c9e963d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34991
94532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.3499194532
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.1133593671
Short name T543
Test name
Test status
Simulation time 6990455434 ps
CPU time 55.13 seconds
Started Jul 28 07:39:28 PM PDT 24
Finished Jul 28 07:40:23 PM PDT 24
Peak memory 207564 kb
Host smart-4055a443-0f18-475a-a29e-f73632dcdd97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11335
93671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.1133593671
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.2665202687
Short name T474
Test name
Test status
Simulation time 1839418232 ps
CPU time 41.85 seconds
Started Jul 28 07:39:23 PM PDT 24
Finished Jul 28 07:40:05 PM PDT 24
Peak memory 207424 kb
Host smart-579475c2-0d36-4c45-bea7-dd2e144433b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665202687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.2665202687
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.1452448610
Short name T1952
Test name
Test status
Simulation time 37760654 ps
CPU time 0.67 seconds
Started Jul 28 07:39:45 PM PDT 24
Finished Jul 28 07:39:46 PM PDT 24
Peak memory 207340 kb
Host smart-e99943a3-d723-4bfb-9c52-abf25e033971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1452448610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.1452448610
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1398671399
Short name T483
Test name
Test status
Simulation time 3969248507 ps
CPU time 5.81 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:35 PM PDT 24
Peak memory 207456 kb
Host smart-96d8f03b-0a1b-489d-a43a-71bdb065501e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398671399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.1398671399
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.2619279679
Short name T1110
Test name
Test status
Simulation time 13389615261 ps
CPU time 16.15 seconds
Started Jul 28 07:39:40 PM PDT 24
Finished Jul 28 07:39:56 PM PDT 24
Peak memory 207380 kb
Host smart-6428dd0c-5303-4818-9113-1b681360b0d5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619279679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.2619279679
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.15993602
Short name T1219
Test name
Test status
Simulation time 23389570441 ps
CPU time 32.01 seconds
Started Jul 28 07:39:31 PM PDT 24
Finished Jul 28 07:40:03 PM PDT 24
Peak memory 207420 kb
Host smart-f2f3f713-21e1-455d-9f20-b7790741aaec
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15993602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_
wake_resume.15993602
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2829996782
Short name T948
Test name
Test status
Simulation time 175478429 ps
CPU time 0.91 seconds
Started Jul 28 07:39:29 PM PDT 24
Finished Jul 28 07:39:30 PM PDT 24
Peak memory 207268 kb
Host smart-12ec7525-7c72-4912-8003-6bc1b3b4dcc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28299
96782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2829996782
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.4105868373
Short name T2237
Test name
Test status
Simulation time 177314146 ps
CPU time 0.86 seconds
Started Jul 28 07:39:31 PM PDT 24
Finished Jul 28 07:39:32 PM PDT 24
Peak memory 207084 kb
Host smart-6c762fb3-a6c4-4055-b103-7e87cdb75fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41058
68373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.4105868373
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.4117002480
Short name T513
Test name
Test status
Simulation time 439105069 ps
CPU time 1.53 seconds
Started Jul 28 07:39:32 PM PDT 24
Finished Jul 28 07:39:34 PM PDT 24
Peak memory 207160 kb
Host smart-6c41b723-0725-4720-9875-8045f2ba6d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41170
02480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.4117002480
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2311756181
Short name T2447
Test name
Test status
Simulation time 1061863026 ps
CPU time 2.74 seconds
Started Jul 28 07:39:33 PM PDT 24
Finished Jul 28 07:39:36 PM PDT 24
Peak memory 207308 kb
Host smart-a576c8f5-b123-4233-aec7-4e86b4d6f537
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2311756181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2311756181
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.3003633162
Short name T172
Test name
Test status
Simulation time 8436118070 ps
CPU time 19.5 seconds
Started Jul 28 07:39:35 PM PDT 24
Finished Jul 28 07:39:55 PM PDT 24
Peak memory 207444 kb
Host smart-30c3ff57-c86b-4324-b41b-7cf3b4bad85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30036
33162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.3003633162
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.524222130
Short name T1759
Test name
Test status
Simulation time 5257163931 ps
CPU time 45.79 seconds
Started Jul 28 07:39:31 PM PDT 24
Finished Jul 28 07:40:16 PM PDT 24
Peak memory 207428 kb
Host smart-0f36b738-56b1-44b3-8f1c-ee33f4120d82
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524222130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.524222130
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.2843840982
Short name T1646
Test name
Test status
Simulation time 480571683 ps
CPU time 1.48 seconds
Started Jul 28 07:39:32 PM PDT 24
Finished Jul 28 07:39:34 PM PDT 24
Peak memory 207096 kb
Host smart-20862784-aa89-46cb-bdda-08a7a5303ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28438
40982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.2843840982
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.3649998126
Short name T1373
Test name
Test status
Simulation time 148837289 ps
CPU time 0.82 seconds
Started Jul 28 07:39:35 PM PDT 24
Finished Jul 28 07:39:36 PM PDT 24
Peak memory 207136 kb
Host smart-3975a857-d2ea-4c68-b448-bfa1a58fe9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36499
98126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.3649998126
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.3433587594
Short name T2210
Test name
Test status
Simulation time 33684307 ps
CPU time 0.69 seconds
Started Jul 28 07:39:33 PM PDT 24
Finished Jul 28 07:39:34 PM PDT 24
Peak memory 207092 kb
Host smart-fbfa7a82-6396-4a7c-8108-dbcba5c98b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34335
87594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3433587594
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.381308421
Short name T479
Test name
Test status
Simulation time 864983609 ps
CPU time 2.62 seconds
Started Jul 28 07:39:36 PM PDT 24
Finished Jul 28 07:39:39 PM PDT 24
Peak memory 207364 kb
Host smart-7a2c3239-ee68-46c0-892b-d413b1aadb90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38130
8421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.381308421
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3534568349
Short name T476
Test name
Test status
Simulation time 303936534 ps
CPU time 2.02 seconds
Started Jul 28 07:39:39 PM PDT 24
Finished Jul 28 07:39:41 PM PDT 24
Peak memory 207196 kb
Host smart-3f18e118-5528-4f5b-8365-3042c2b65def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35345
68349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3534568349
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3655405365
Short name T407
Test name
Test status
Simulation time 216148165 ps
CPU time 1.2 seconds
Started Jul 28 07:39:32 PM PDT 24
Finished Jul 28 07:39:34 PM PDT 24
Peak memory 207332 kb
Host smart-e27cdffb-5ec3-4aab-9427-8f25635c05d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3655405365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3655405365
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1289058180
Short name T2511
Test name
Test status
Simulation time 149859577 ps
CPU time 0.84 seconds
Started Jul 28 07:39:32 PM PDT 24
Finished Jul 28 07:39:33 PM PDT 24
Peak memory 207056 kb
Host smart-a1e52be5-ad7f-4a7c-8352-269438c30945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12890
58180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1289058180
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.4218629585
Short name T2714
Test name
Test status
Simulation time 172409992 ps
CPU time 0.89 seconds
Started Jul 28 07:39:36 PM PDT 24
Finished Jul 28 07:39:37 PM PDT 24
Peak memory 207056 kb
Host smart-deef6c79-05ab-40d1-a391-064bc8d735cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42186
29585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.4218629585
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.1350436405
Short name T575
Test name
Test status
Simulation time 9001486114 ps
CPU time 268.09 seconds
Started Jul 28 07:39:36 PM PDT 24
Finished Jul 28 07:44:04 PM PDT 24
Peak memory 215668 kb
Host smart-d0de1526-ebdf-47cd-a74d-dba00019fd16
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1350436405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.1350436405
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.1603634465
Short name T2634
Test name
Test status
Simulation time 13039001587 ps
CPU time 92.69 seconds
Started Jul 28 07:39:33 PM PDT 24
Finished Jul 28 07:41:06 PM PDT 24
Peak memory 207348 kb
Host smart-7c96edc9-8569-4217-813f-b0eec5cb2a97
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1603634465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.1603634465
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2339001741
Short name T964
Test name
Test status
Simulation time 191050217 ps
CPU time 0.95 seconds
Started Jul 28 07:39:36 PM PDT 24
Finished Jul 28 07:39:37 PM PDT 24
Peak memory 207208 kb
Host smart-0f6268a6-c3bd-49f6-bc6f-05b278f5d14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23390
01741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2339001741
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3505809823
Short name T1996
Test name
Test status
Simulation time 23290164079 ps
CPU time 27.64 seconds
Started Jul 28 07:39:33 PM PDT 24
Finished Jul 28 07:40:00 PM PDT 24
Peak memory 207380 kb
Host smart-6cbdaf25-3bf1-4c34-8a40-4945849efece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35058
09823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3505809823
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.354712693
Short name T1308
Test name
Test status
Simulation time 3331357931 ps
CPU time 4.83 seconds
Started Jul 28 07:39:34 PM PDT 24
Finished Jul 28 07:39:38 PM PDT 24
Peak memory 207364 kb
Host smart-722d119d-8f42-4d0d-97a8-83db739e7b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35471
2693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.354712693
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.4022940362
Short name T1686
Test name
Test status
Simulation time 8393102456 ps
CPU time 61.4 seconds
Started Jul 28 07:39:36 PM PDT 24
Finished Jul 28 07:40:38 PM PDT 24
Peak memory 217592 kb
Host smart-7b0622f7-5c43-4d22-aa36-971f2a569900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40229
40362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.4022940362
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.2855250447
Short name T1013
Test name
Test status
Simulation time 4565477472 ps
CPU time 46.9 seconds
Started Jul 28 07:39:34 PM PDT 24
Finished Jul 28 07:40:21 PM PDT 24
Peak memory 216972 kb
Host smart-6762ebb1-93b6-46da-af5a-dd0d7b576b00
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2855250447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.2855250447
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2114815342
Short name T1283
Test name
Test status
Simulation time 246557989 ps
CPU time 1 seconds
Started Jul 28 07:39:36 PM PDT 24
Finished Jul 28 07:39:38 PM PDT 24
Peak memory 207200 kb
Host smart-a576636f-18f3-4072-ae1d-e5902e1fd2d5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2114815342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2114815342
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2057738248
Short name T566
Test name
Test status
Simulation time 242496217 ps
CPU time 0.98 seconds
Started Jul 28 07:39:31 PM PDT 24
Finished Jul 28 07:39:32 PM PDT 24
Peak memory 207296 kb
Host smart-b4a5843a-63b9-4beb-bf98-ddb777a7d6dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20577
38248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2057738248
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3830544360
Short name T577
Test name
Test status
Simulation time 4802971716 ps
CPU time 140.94 seconds
Started Jul 28 07:39:33 PM PDT 24
Finished Jul 28 07:41:54 PM PDT 24
Peak memory 215564 kb
Host smart-2d3dec3c-d5cd-4d90-b947-81f28a0b5404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38305
44360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3830544360
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3030559548
Short name T2766
Test name
Test status
Simulation time 4332492185 ps
CPU time 33.25 seconds
Started Jul 28 07:39:36 PM PDT 24
Finished Jul 28 07:40:09 PM PDT 24
Peak memory 207376 kb
Host smart-b6cead17-a9b3-4fdd-9157-c2834b8ee28f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3030559548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3030559548
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.708829213
Short name T2469
Test name
Test status
Simulation time 180536661 ps
CPU time 0.87 seconds
Started Jul 28 07:39:34 PM PDT 24
Finished Jul 28 07:39:35 PM PDT 24
Peak memory 207132 kb
Host smart-d45e8950-d70f-47fa-a2d9-0f04033a7d6a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=708829213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.708829213
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.221887268
Short name T1450
Test name
Test status
Simulation time 156688355 ps
CPU time 0.81 seconds
Started Jul 28 07:39:37 PM PDT 24
Finished Jul 28 07:39:38 PM PDT 24
Peak memory 207124 kb
Host smart-2c79af57-4aee-461d-8e31-8d06fe0cadc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22188
7268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.221887268
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1012705321
Short name T123
Test name
Test status
Simulation time 190965914 ps
CPU time 0.93 seconds
Started Jul 28 07:39:38 PM PDT 24
Finished Jul 28 07:39:39 PM PDT 24
Peak memory 207168 kb
Host smart-dc4721de-a89b-4721-a55c-9dec7d1e63fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10127
05321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1012705321
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.1963353551
Short name T2300
Test name
Test status
Simulation time 155167469 ps
CPU time 0.86 seconds
Started Jul 28 07:39:38 PM PDT 24
Finished Jul 28 07:39:39 PM PDT 24
Peak memory 207112 kb
Host smart-ef244ecc-0d54-4622-8e31-5ed0eddfea1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19633
53551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.1963353551
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3569577278
Short name T2711
Test name
Test status
Simulation time 181985981 ps
CPU time 0.85 seconds
Started Jul 28 07:39:43 PM PDT 24
Finished Jul 28 07:39:44 PM PDT 24
Peak memory 207120 kb
Host smart-6185bc55-b4a1-4fe9-ba0c-cfd142aed649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35695
77278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3569577278
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2779969389
Short name T1391
Test name
Test status
Simulation time 162399005 ps
CPU time 0.91 seconds
Started Jul 28 07:39:37 PM PDT 24
Finished Jul 28 07:39:38 PM PDT 24
Peak memory 207168 kb
Host smart-5c2193c7-daf6-4097-a791-0d01dbb96e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27799
69389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2779969389
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.894866880
Short name T1277
Test name
Test status
Simulation time 172142517 ps
CPU time 0.84 seconds
Started Jul 28 07:39:40 PM PDT 24
Finished Jul 28 07:39:41 PM PDT 24
Peak memory 207040 kb
Host smart-15ef6944-03cc-4603-a421-ec487ab7a64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89486
6880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.894866880
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.3146584497
Short name T2244
Test name
Test status
Simulation time 251840953 ps
CPU time 1.1 seconds
Started Jul 28 07:39:43 PM PDT 24
Finished Jul 28 07:39:44 PM PDT 24
Peak memory 207116 kb
Host smart-0345e5ad-55d1-4235-a28a-b7221d190fd8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3146584497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.3146584497
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.4046509163
Short name T2216
Test name
Test status
Simulation time 153794071 ps
CPU time 0.89 seconds
Started Jul 28 07:39:38 PM PDT 24
Finished Jul 28 07:39:39 PM PDT 24
Peak memory 207116 kb
Host smart-e98f79b8-de1d-4fcd-91fb-8c1d6ebbea2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40465
09163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.4046509163
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3383329612
Short name T380
Test name
Test status
Simulation time 45634978 ps
CPU time 0.72 seconds
Started Jul 28 07:39:39 PM PDT 24
Finished Jul 28 07:39:40 PM PDT 24
Peak memory 207020 kb
Host smart-fe3ac6f1-f391-4833-bb6c-0eb75987092a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33833
29612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3383329612
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2379233753
Short name T239
Test name
Test status
Simulation time 9374682499 ps
CPU time 23.72 seconds
Started Jul 28 07:39:46 PM PDT 24
Finished Jul 28 07:40:10 PM PDT 24
Peak memory 215588 kb
Host smart-960bdd11-44ef-4e7a-9328-de6b6d348a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23792
33753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2379233753
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3160390885
Short name T732
Test name
Test status
Simulation time 184365465 ps
CPU time 0.96 seconds
Started Jul 28 07:39:41 PM PDT 24
Finished Jul 28 07:39:42 PM PDT 24
Peak memory 207112 kb
Host smart-801b1e4e-d061-47d0-b847-d263c4c8df80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31603
90885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3160390885
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.739754133
Short name T2487
Test name
Test status
Simulation time 191375050 ps
CPU time 0.9 seconds
Started Jul 28 07:39:39 PM PDT 24
Finished Jul 28 07:39:40 PM PDT 24
Peak memory 207156 kb
Host smart-90fa0907-1fe7-483d-ab56-f46c2eb2d63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73975
4133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.739754133
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.3387792102
Short name T1328
Test name
Test status
Simulation time 9908937914 ps
CPU time 89.1 seconds
Started Jul 28 07:39:42 PM PDT 24
Finished Jul 28 07:41:12 PM PDT 24
Peak memory 223728 kb
Host smart-38b4fc87-5b04-4df2-b1a2-c986f2800c5f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387792102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.3387792102
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.4273213245
Short name T1809
Test name
Test status
Simulation time 9375891602 ps
CPU time 71.31 seconds
Started Jul 28 07:39:44 PM PDT 24
Finished Jul 28 07:40:55 PM PDT 24
Peak memory 223724 kb
Host smart-0d4aff78-a01f-4974-bfdd-4c2736ee4b89
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4273213245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.4273213245
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.661944228
Short name T184
Test name
Test status
Simulation time 11912626511 ps
CPU time 61.68 seconds
Started Jul 28 07:39:49 PM PDT 24
Finished Jul 28 07:40:51 PM PDT 24
Peak memory 217456 kb
Host smart-fd14fbfd-839f-4d77-8970-6c49439ab3fb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=661944228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.661944228
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.1639014199
Short name T734
Test name
Test status
Simulation time 226440482 ps
CPU time 1.04 seconds
Started Jul 28 07:39:43 PM PDT 24
Finished Jul 28 07:39:44 PM PDT 24
Peak memory 207112 kb
Host smart-61fbc3c7-d777-4143-8f27-f831ca837ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16390
14199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.1639014199
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.2500931040
Short name T1273
Test name
Test status
Simulation time 157526152 ps
CPU time 0.84 seconds
Started Jul 28 07:39:46 PM PDT 24
Finished Jul 28 07:39:47 PM PDT 24
Peak memory 207204 kb
Host smart-fa245ed7-5b81-4f0b-8097-5c30adb9f9ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25009
31040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.2500931040
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.2428142146
Short name T2701
Test name
Test status
Simulation time 136831891 ps
CPU time 0.77 seconds
Started Jul 28 07:39:41 PM PDT 24
Finished Jul 28 07:39:42 PM PDT 24
Peak memory 207044 kb
Host smart-cd0d5385-6a66-453d-9826-02b416040f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24281
42146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.2428142146
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1498692469
Short name T1187
Test name
Test status
Simulation time 143117582 ps
CPU time 0.82 seconds
Started Jul 28 07:39:43 PM PDT 24
Finished Jul 28 07:39:45 PM PDT 24
Peak memory 207108 kb
Host smart-18474761-9678-41d1-82bd-411bf0b8e662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14986
92469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1498692469
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2445539736
Short name T44
Test name
Test status
Simulation time 163956049 ps
CPU time 0.86 seconds
Started Jul 28 07:39:48 PM PDT 24
Finished Jul 28 07:39:49 PM PDT 24
Peak memory 207204 kb
Host smart-f9c8990a-ad58-4a1e-937b-2ff55cf29ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24455
39736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2445539736
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1288371502
Short name T2716
Test name
Test status
Simulation time 214942935 ps
CPU time 0.99 seconds
Started Jul 28 07:39:48 PM PDT 24
Finished Jul 28 07:39:49 PM PDT 24
Peak memory 207120 kb
Host smart-dfed3e44-4c11-47d2-b748-530c9449e344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12883
71502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1288371502
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.1054882914
Short name T2517
Test name
Test status
Simulation time 4945784978 ps
CPU time 48.1 seconds
Started Jul 28 07:39:47 PM PDT 24
Finished Jul 28 07:40:35 PM PDT 24
Peak memory 215528 kb
Host smart-820cc683-e74d-494e-a7a0-4d1d9fc52dc2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1054882914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.1054882914
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2031313564
Short name T428
Test name
Test status
Simulation time 178154440 ps
CPU time 0.88 seconds
Started Jul 28 07:39:42 PM PDT 24
Finished Jul 28 07:39:43 PM PDT 24
Peak memory 207148 kb
Host smart-3fbd5f13-154c-4d38-8fa4-9cf265e4fcc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20313
13564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2031313564
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3956480117
Short name T1927
Test name
Test status
Simulation time 176189049 ps
CPU time 0.95 seconds
Started Jul 28 07:39:49 PM PDT 24
Finished Jul 28 07:39:50 PM PDT 24
Peak memory 207120 kb
Host smart-dfed189f-b79e-4d26-af9b-91401df7bbd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39564
80117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3956480117
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.2342157259
Short name T404
Test name
Test status
Simulation time 849745408 ps
CPU time 2.18 seconds
Started Jul 28 07:39:46 PM PDT 24
Finished Jul 28 07:39:48 PM PDT 24
Peak memory 207096 kb
Host smart-953f3dea-8e69-4262-852d-46c7a6243127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23421
57259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.2342157259
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1217253877
Short name T2151
Test name
Test status
Simulation time 3815021534 ps
CPU time 38.65 seconds
Started Jul 28 07:39:48 PM PDT 24
Finished Jul 28 07:40:27 PM PDT 24
Peak memory 216968 kb
Host smart-9504ab08-e49c-4423-bc7f-23fb2087ab81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12172
53877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1217253877
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.3414354973
Short name T1184
Test name
Test status
Simulation time 2943466418 ps
CPU time 24.56 seconds
Started Jul 28 07:39:35 PM PDT 24
Finished Jul 28 07:39:59 PM PDT 24
Peak memory 207372 kb
Host smart-020a64dc-af89-4db0-a7b6-e3cb0d4f1dbb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414354973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host
_handshake.3414354973
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%