Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	74676	1		T1	2		T2	2		T3	3
all_values[1]	74676	1		T1	2		T2	2		T3	3
all_values[2]	74676	1		T1	2		T2	2		T3	3
all_values[3]	74676	1		T1	2		T2	2		T3	3
all_values[4]	74676	1		T1	2		T2	2		T3	3
all_values[5]	74676	1		T1	2		T2	2		T3	3
all_values[6]	74676	1		T1	2		T2	2		T3	3
all_values[7]	74676	1		T1	2		T2	2		T3	3
all_values[8]	74676	1		T1	2		T2	2		T3	3
all_values[9]	74676	1		T1	2		T2	2		T3	3
all_values[10]	74676	1		T1	2		T2	2		T3	3
all_values[11]	74676	1		T1	2		T2	2		T3	3
all_values[12]	74676	1		T1	2		T2	2		T3	3
all_values[13]	74676	1		T1	2		T2	2		T3	3
all_values[14]	74676	1		T1	2		T2	2		T3	3
all_values[15]	74676	1		T1	2		T2	2		T3	3
all_values[16]	74676	1		T1	2		T2	2		T3	3
all_values[17]	74676	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2382522	1		T1	62		T2	64		T3	96
auto[1]	7110	1		T1	2		T34	2		T32	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1981285	1		T1	57		T2	53		T3	78
auto[1]	408347	1		T1	7		T2	11		T3	18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	50627	1		T1	2		T2	2		T34	2
all_values[0]	auto[0]	auto[1]	23194	1		T3	3		T31	1		T24	1
all_values[0]	auto[1]	auto[0]	745	1		T52	3		T53	3		T54	3
all_values[0]	auto[1]	auto[1]	110	1		T283	1		T284	1		T285	1
all_values[1]	auto[0]	auto[0]	71410	1		T1	2		T34	2		T35	2
all_values[1]	auto[0]	auto[1]	1576	1		T2	2		T3	3		T28	2
all_values[1]	auto[1]	auto[0]	674	1		T32	2		T7	1		T56	2
all_values[1]	auto[1]	auto[1]	1016	1		T32	1		T7	1		T56	1
all_values[2]	auto[0]	auto[0]	2962	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	71456	1		T1	1		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	136	1		T43	1		T44	1		T50	1
all_values[2]	auto[1]	auto[1]	122	1		T43	1		T44	1		T50	1
all_values[3]	auto[0]	auto[0]	72496	1		T1	2		T2	1		T3	3
all_values[3]	auto[0]	auto[1]	533	1		T2	1		T4	1		T5	1
all_values[3]	auto[1]	auto[0]	1570	1		T70	1483		T205	1		T208	2
all_values[3]	auto[1]	auto[1]	77	1		T70	1		T208	2		T206	2
all_values[4]	auto[0]	auto[0]	2950	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	71569	1		T1	1		T2	1		T3	2
all_values[4]	auto[1]	auto[0]	92	1		T71	1		T205	1		T208	2
all_values[4]	auto[1]	auto[1]	65	1		T71	1		T205	3		T208	2
all_values[5]	auto[0]	auto[0]	74150	1		T1	2		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	349	1		T7	1		T41	1		T42	1
all_values[5]	auto[1]	auto[0]	93	1		T205	2		T208	3		T206	1
all_values[5]	auto[1]	auto[1]	84	1		T205	3		T207	3		T277	4
all_values[6]	auto[0]	auto[0]	74226	1		T1	2		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	281	1		T7	1		T41	1		T46	1
all_values[6]	auto[1]	auto[0]	86	1		T205	3		T208	4		T206	1
all_values[6]	auto[1]	auto[1]	83	1		T205	2		T208	1		T206	3
all_values[7]	auto[0]	auto[0]	23990	1		T1	2		T34	2		T35	2
all_values[7]	auto[0]	auto[1]	50501	1		T2	2		T3	3		T28	2
all_values[7]	auto[1]	auto[0]	111	1		T57	1		T205	1		T208	1
all_values[7]	auto[1]	auto[1]	74	1		T57	1		T205	1		T208	1
all_values[8]	auto[0]	auto[0]	74426	1		T1	2		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	63	1		T205	4		T208	1		T206	1
all_values[8]	auto[1]	auto[0]	126	1		T60	10		T205	4		T208	5
all_values[8]	auto[1]	auto[1]	61	1		T60	1		T208	1		T207	1
all_values[9]	auto[0]	auto[0]	74412	1		T1	2		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	62	1		T205	3		T208	1		T206	2
all_values[9]	auto[1]	auto[0]	120	1		T67	3		T68	3		T69	3
all_values[9]	auto[1]	auto[1]	82	1		T67	2		T68	2		T69	2
all_values[10]	auto[0]	auto[0]	74195	1		T1	2		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	314	1		T29	1		T65	2		T66	1
all_values[10]	auto[1]	auto[0]	101	1		T208	4		T206	2		T207	4
all_values[10]	auto[1]	auto[1]	66	1		T205	4		T208	1		T206	2
all_values[11]	auto[0]	auto[0]	74275	1		T2	2		T3	3		T35	2
all_values[11]	auto[0]	auto[1]	135	1		T77	1		T79	1		T46	1
all_values[11]	auto[1]	auto[0]	138	1		T1	1		T34	1		T78	1
all_values[11]	auto[1]	auto[1]	128	1		T1	1		T34	1		T78	1
all_values[12]	auto[0]	auto[0]	74436	1		T1	2		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	55	1		T46	1		T51	1		T83	1
all_values[12]	auto[1]	auto[0]	126	1		T80	2		T81	2		T82	2
all_values[12]	auto[1]	auto[1]	59	1		T80	1		T81	1		T82	1
all_values[13]	auto[0]	auto[0]	74326	1		T1	2		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	74	1		T46	1		T51	1		T83	1
all_values[13]	auto[1]	auto[0]	154	1		T77	1		T79	1		T84	1
all_values[13]	auto[1]	auto[1]	122	1		T77	1		T79	1		T84	1
all_values[14]	auto[0]	auto[0]	12336	1		T1	2		T2	1		T3	3
all_values[14]	auto[0]	auto[1]	62192	1		T2	1		T35	1		T4	1
all_values[14]	auto[1]	auto[0]	96	1		T208	4		T206	3		T278	1
all_values[14]	auto[1]	auto[1]	52	1		T207	3		T277	2		T278	2
all_values[15]	auto[0]	auto[0]	2981	1		T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	71531	1		T1	1		T2	1		T3	2
all_values[15]	auto[1]	auto[0]	108	1		T205	1		T208	4		T206	3
all_values[15]	auto[1]	auto[1]	56	1		T205	1		T206	2		T207	3
all_values[16]	auto[0]	auto[0]	74077	1		T1	1		T2	2		T3	3
all_values[16]	auto[0]	auto[1]	415	1		T1	1		T72	1		T73	1
all_values[16]	auto[1]	auto[0]	120	1		T74	4		T75	4		T76	4
all_values[16]	auto[1]	auto[1]	64	1		T74	4		T75	4		T76	4
all_values[17]	auto[0]	auto[0]	22828	1		T4	2		T5	2		T6	2
all_values[17]	auto[0]	auto[1]	51655	1		T1	2		T2	2		T3	3
all_values[17]	auto[1]	auto[0]	122	1		T62	1		T63	1		T64	1
all_values[17]	auto[1]	auto[1]	71	1		T62	1		T63	1		T64	1