Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	131706	1		T1	1		T2	147		T3	1
auto[1]	64097	1		T2	166		T3	1		T28	6

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixty_four	28095	1		T2	1		T30	1		T4	2
sixty_three	1228	1		T28	1		T4	4		T6	4
sixty_two	1199	1		T2	2		T30	1		T5	5
sixty_one	1228	1		T2	5		T5	7		T33	2
five	1621	1		T2	5		T4	2		T5	3
four	1585	1		T2	3		T28	1		T4	4
three	1651	1		T2	6		T4	7		T5	4
one	1774	1		T2	11		T5	6		T6	2
zero	12880	1		T2	94		T3	2		T28	6

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixty_four	auto[0]	22768	1		T2	1		T30	1		T4	1
sixty_four	auto[1]	5327	1		T4	1		T5	1		T6	1
sixty_three	auto[0]	787	1		T28	1		T4	2		T6	2
sixty_three	auto[1]	441	1		T4	2		T6	2		T33	2
sixty_two	auto[0]	766	1		T2	2		T30	1		T5	3
sixty_two	auto[1]	433	1		T5	2		T6	1		T33	1
sixty_one	auto[0]	797	1		T2	5		T5	5		T33	1
sixty_one	auto[1]	431	1		T5	2		T33	1		T17	2
five	auto[0]	862	1		T2	2		T4	2		T5	2
five	auto[1]	759	1		T2	3		T5	1		T33	2
four	auto[0]	830	1		T28	1		T4	2		T6	2
four	auto[1]	755	1		T2	3		T4	2		T6	2
three	auto[0]	857	1		T2	2		T4	4		T5	2
three	auto[1]	794	1		T2	4		T4	3		T5	2
one	auto[0]	832	1		T2	1		T5	4		T6	1
one	auto[1]	942	1		T2	10		T5	2		T6	1
zero	auto[0]	1020	1		T2	6		T3	1		T31	1
zero	auto[1]	11860	1		T2	88		T3	1		T28	6