Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
42.67	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	6	16	72.73
Crosses	128	80	48	37.50

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	16	4	12	75.00	100	1	1	16
cp_pid	4	2	2	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	128	80	48	37.50	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	88739	1		T1	1		T2	147		T3	1
auto[1]	58828	1		T2	166		T3	1		T28	6

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	16	4	12	75.00

Automatically Generated Bins for cp_endp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[12] - auto[15]]	--	--	4

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	12736	1		T2	32		T4	32		T33	24
auto[1]	14702	1		T2	16		T3	2		T33	24
auto[2]	11024	1		T2	30		T28	14		T5	72
auto[3]	9635	1		T1	1		T2	35		T33	24
auto[4]	15622	1		T2	24		T33	24		T17	20
auto[5]	13350	1		T2	18		T4	32		T24	1
auto[6]	10741	1		T2	29		T17	20		T25	24
auto[7]	9868	1		T2	20		T17	20		T25	24
auto[8]	14232	1		T2	30		T30	8		T4	32
auto[9]	12067	1		T2	33		T17	20		T45	48
auto[10]	11617	1		T2	22		T4	32		T33	24
auto[11]	11973	1		T2	24		T29	7		T31	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
nak	0	1	1
ack	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	69199	1		T2	151		T28	4		T29	2
data0	78340	1		T1	1		T2	162		T3	2

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	80	48	37.50	80

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER
[nak , ack]	*	*	--	--	64
[data1 , data0]	*	[auto[12] - auto[15]]	--	--	16

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	auto[0]	auto[0]	3244	1		T2	6		T4	5		T33	6
data1	auto[0]	auto[1]	4260	1		T2	4		T33	4		T17	5
data1	auto[0]	auto[2]	2313	1		T2	7		T28	3		T5	18
data1	auto[0]	auto[3]	2087	1		T2	10		T33	5		T23	34
data1	auto[0]	auto[4]	4560	1		T2	4		T33	6		T17	5
data1	auto[0]	auto[5]	3611	1		T2	5		T4	8		T25	6
data1	auto[0]	auto[6]	2661	1		T2	4		T17	5		T25	6
data1	auto[0]	auto[7]	2119	1		T2	4		T17	5		T25	6
data1	auto[0]	auto[8]	4015	1		T2	8		T30	1		T4	8
data1	auto[0]	auto[9]	2874	1		T2	7		T17	4		T45	5
data1	auto[0]	auto[10]	2821	1		T2	6		T4	3		T33	6
data1	auto[0]	auto[11]	3052	1		T2	6		T4	8		T5	18
data1	auto[1]	auto[0]	2677	1		T2	9		T4	11		T33	6
data1	auto[1]	auto[1]	2680	1		T2	4		T33	7		T17	5
data1	auto[1]	auto[2]	2729	1		T2	8		T28	1		T5	18
data1	auto[1]	auto[3]	2358	1		T2	7		T33	6		T23	71
data1	auto[1]	auto[4]	2863	1		T2	7		T33	6		T17	5
data1	auto[1]	auto[5]	2654	1		T2	4		T4	8		T25	6
data1	auto[1]	auto[6]	2317	1		T2	10		T17	5		T25	6
data1	auto[1]	auto[7]	2502	1		T2	5		T17	5		T25	6
data1	auto[1]	auto[8]	2775	1		T2	7		T30	1		T4	8
data1	auto[1]	auto[9]	2856	1		T2	9		T17	6		T45	19
data1	auto[1]	auto[10]	2605	1		T2	5		T4	12		T33	6
data1	auto[1]	auto[11]	2566	1		T2	5		T29	2		T4	8
data0	auto[0]	auto[0]	4501	1		T2	7		T4	11		T33	6
data0	auto[0]	auto[1]	5578	1		T2	4		T3	1		T33	8
data0	auto[0]	auto[2]	3640	1		T2	7		T28	5		T5	18
data0	auto[0]	auto[3]	3091	1		T1	1		T2	10		T33	7
data0	auto[0]	auto[4]	5807	1		T2	5		T33	6		T17	5
data0	auto[0]	auto[5]	4698	1		T2	5		T4	8		T24	1
data0	auto[0]	auto[6]	3731	1		T2	5		T17	5		T25	6
data0	auto[0]	auto[7]	3143	1		T2	5		T17	5		T25	6
data0	auto[0]	auto[8]	5082	1		T2	8		T30	2		T4	8
data0	auto[0]	auto[9]	3896	1		T2	7		T17	6		T45	19
data0	auto[0]	auto[10]	3917	1		T2	6		T4	13		T33	6
data0	auto[0]	auto[11]	4010	1		T2	7		T31	1		T32	1
data0	auto[1]	auto[0]	2309	1		T2	10		T4	5		T33	6
data0	auto[1]	auto[1]	2181	1		T2	4		T3	1		T33	5
data0	auto[1]	auto[2]	2342	1		T2	8		T28	5		T5	18
data0	auto[1]	auto[3]	2097	1		T2	8		T33	6		T23	34
data0	auto[1]	auto[4]	2390	1		T2	8		T33	6		T17	5
data0	auto[1]	auto[5]	2385	1		T2	4		T4	8		T25	6
data0	auto[1]	auto[6]	2031	1		T2	10		T17	5		T25	6
data0	auto[1]	auto[7]	2102	1		T2	6		T17	5		T25	6
data0	auto[1]	auto[8]	2356	1		T2	7		T30	4		T4	8
data0	auto[1]	auto[9]	2440	1		T2	10		T17	4		T45	5
data0	auto[1]	auto[10]	2270	1		T2	5		T4	4		T33	6
data0	auto[1]	auto[11]	2343	1		T2	6		T29	5		T32	1