Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50
Crosses	16	11	5	31.25

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	1	1	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	11	5	31.25	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6044	1		T4	5		T25	7		T89	4
auto[1]	70271	1		T2	166		T3	1		T28	6

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	71046	1		T2	166		T3	1		T28	6
auto[1]	5269	1		T21	65		T100	1		T101	1

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	71557	1		T2	166		T3	1		T28	6
auto[1]	4758	1		T102	1		T89	4		T103	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
ignore_pre[PidTypePre]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeInToken]	76315	1		T2	166		T3	1		T28	6

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	11	5	31.25	11

Automatically Generated Cross Bins for cr_pid_x_epconfig

Element holes

cp_pid	cp_in_enable	cp_in_iso	cp_in_stall	COUNT	AT LEAST	NUMBER
[ignore_pre[PidTypePre]]	*	*	*	--	--	8
[pkt_types[PidTypeInToken]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_pid	cp_in_enable	cp_in_iso	cp_in_stall	COUNT	AT LEAST	NUMBER
[pkt_types[PidTypeInToken]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

3513

1

T4

5

T25

7

T89

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2531

1

T89

3

T94

23

T268

6

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

62775

1

T2

166

T3

1

T28

6

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2227

1

T102

1

T89

1

T103

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

5269

1

T21

65

T100

1

T101

1