Group : usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
24.15 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 1 14 93.33
Crosses 192 156 36 18.75


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_out_enable 2 0 2 100.00 100 1 1 2
cp_out_iso 2 0 2 100.00 100 1 1 2
cp_out_stall 2 0 2 100.00 100 1 1 2
cp_pid 3 1 2 66.67 100 1 1 0
cp_rxenable_out 2 0 2 100.00 100 1 1 2
cp_rxenable_setup 2 0 2 100.00 100 1 1 2
cp_set_nak_out 2 0 2 100.00 100 1 1 2


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 192 156 36 18.75 100 1 1 0


Summary for Variable cp_out_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_out_enable

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 16977 1 T4 15 T77 1 T25 10
auto[1] 99298 1 T1 1 T2 147 T3 1



Summary for Variable cp_out_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_out_iso

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 116225 1 T1 1 T2 147 T3 1
auto[1] 50 1 T24 1 T115 1 T116 1



Summary for Variable cp_out_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_out_stall

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 103761 1 T1 1 T2 147 T3 1
auto[1] 12514 1 T52 1 T53 1 T89 5



Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 1 2 66.67


User Defined Bins for cp_pid

Uncovered bins
NAMECOUNTAT LEASTNUMBER
ignore_pre[PidTypePre] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
pkt_types[PidTypeSetupToken] 21874 1 T4 32 T6 48 T33 10
pkt_types[PidTypeOutToken] 94329 1 T1 1 T2 147 T3 1



Summary for Variable cp_rxenable_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rxenable_out

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 17799 1 T4 15 T77 1 T25 10
auto[1] 98476 1 T1 1 T2 147 T3 1



Summary for Variable cp_rxenable_setup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rxenable_setup

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 79442 1 T1 1 T2 147 T3 1
auto[1] 36833 1 T4 42 T6 109 T33 24



Summary for Variable cp_set_nak_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_set_nak_out

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 116125 1 T1 1 T2 147 T3 1
auto[1] 150 1 T120 1 T118 2 T119 2



Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_out_enable cp_rxenable_setup cp_rxenable_out cp_set_nak_out cp_out_iso cp_out_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 192 156 36 18.75 156


Automatically Generated Cross Bins for cr_pid_x_epconfig

Element holes
cp_pidcp_out_enablecp_rxenable_setupcp_rxenable_outcp_set_nak_outcp_out_isocp_out_stallCOUNTAT LEASTNUMBER
[ignore_pre[PidTypePre]] * * * * * * -- -- 64
[pkt_types[PidTypeSetupToken]] * * * [auto[0]] [auto[1]] * -- -- 16
[pkt_types[PidTypeSetupToken]] * * * [auto[1]] * * -- -- 32
[pkt_types[PidTypeOutToken]] [auto[0]] * * [auto[0]] [auto[1]] * -- -- 8
[pkt_types[PidTypeOutToken]] [auto[0]] * * [auto[1]] * * -- -- 16
[pkt_types[PidTypeOutToken]] [auto[1]] [auto[0]] [auto[0]] [auto[0]] [auto[1]] * -- -- 2
[pkt_types[PidTypeOutToken]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[1]] * -- -- 2
[pkt_types[PidTypeOutToken]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] [auto[1]] * -- -- 2
[pkt_types[PidTypeOutToken]] [auto[1]] [auto[1]] * [auto[0]] [auto[1]] * -- -- 4
[pkt_types[PidTypeOutToken]] [auto[1]] [auto[1]] * [auto[1]] * * -- -- 8


Uncovered bins
cp_pidcp_out_enablecp_rxenable_setupcp_rxenable_outcp_set_nak_outcp_out_isocp_out_stallCOUNTAT LEASTNUMBER
[pkt_types[PidTypeOutToken]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] 0 1 1
[pkt_types[PidTypeOutToken]] [auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] 0 1 1


Covered bins
cp_pidcp_out_enablecp_rxenable_setupcp_rxenable_outcp_set_nak_outcp_out_isocp_out_stallCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
pkt_types[PidTypeSetupToken] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 879 1 T4 6 T25 3 T153 2
pkt_types[PidTypeSetupToken] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 630 1 T94 49 T268 1 T269 26
pkt_types[PidTypeSetupToken] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 697 1 T94 43 T270 15 T176 32
pkt_types[PidTypeSetupToken] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 596 1 T95 24 T269 51 T270 21
pkt_types[PidTypeSetupToken] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 845 1 T4 5 T25 3 T153 2
pkt_types[PidTypeSetupToken] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 642 1 T92 16 T94 50 T95 25
pkt_types[PidTypeSetupToken] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 676 1 T89 2 T92 10 T94 16
pkt_types[PidTypeSetupToken] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 758 1 T89 1 T92 14 T268 3
pkt_types[PidTypeSetupToken] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 722 1 T54 1 T114 1 T92 25
pkt_types[PidTypeSetupToken] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 693 1 T92 15 T94 20 T95 38
pkt_types[PidTypeSetupToken] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1413 1 T25 4 T153 8 T172 7
pkt_types[PidTypeSetupToken] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 698 1 T94 27 T270 27 T176 42
pkt_types[PidTypeSetupToken] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1556 1 T98 1 T99 1 T157 1
pkt_types[PidTypeSetupToken] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 37 1 T92 1 T95 1 T269 1
pkt_types[PidTypeSetupToken] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 10887 1 T4 21 T6 48 T33 10
pkt_types[PidTypeSetupToken] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 145 1 T52 1 T53 1 T55 1
pkt_types[PidTypeOutToken] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1761 1 T4 2 T77 1 T153 1
pkt_types[PidTypeOutToken] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 1286 1 T94 76 T268 1 T269 63
pkt_types[PidTypeOutToken] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1319 1 T89 3 T94 83 T270 30
pkt_types[PidTypeOutToken] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 1168 1 T89 1 T95 53 T269 126
pkt_types[PidTypeOutToken] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1570 1 T4 2 T25 4 T153 2
pkt_types[PidTypeOutToken] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 1231 1 T92 28 T94 76 T95 59
pkt_types[PidTypeOutToken] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1386 1 T89 3 T92 37 T94 39
pkt_types[PidTypeOutToken] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 1500 1 T89 3 T92 34 T268 3
pkt_types[PidTypeOutToken] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1460 1 T92 55 T271 1 T272 1
pkt_types[PidTypeOutToken] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 1486 1 T92 24 T94 40 T95 99
pkt_types[PidTypeOutToken] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 50 1 T118 1 T119 1 T136 1
pkt_types[PidTypeOutToken] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 62975 1 T1 1 T2 147 T3 1
pkt_types[PidTypeOutToken] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 1429 1 T72 1 T73 1 T273 1
pkt_types[PidTypeOutToken] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 50 1 T24 1 T115 1 T116 1
pkt_types[PidTypeOutToken] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 50 1 T118 1 T119 1 T136 1
pkt_types[PidTypeOutToken] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 50 1 T120 1 T274 1 T275 1
pkt_types[PidTypeOutToken] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 2844 1 T92 32 T94 40 T95 49
pkt_types[PidTypeOutToken] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 74 1 T95 4 T269 2 T176 7
pkt_types[PidTypeOutToken] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 12549 1 T4 14 T6 61 T33 14
pkt_types[PidTypeOutToken] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 91 1 T155 1 T95 9 T269 5

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