Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	74676	1		T1	2		T2	2		T3	3
all_pins[1]	74676	1		T1	2		T2	2		T3	3
all_pins[2]	74676	1		T1	2		T2	2		T3	3
all_pins[3]	74676	1		T1	2		T2	2		T3	3
all_pins[4]	74676	1		T1	2		T2	2		T3	3
all_pins[5]	74676	1		T1	2		T2	2		T3	3
all_pins[6]	74676	1		T1	2		T2	2		T3	3
all_pins[7]	74676	1		T1	2		T2	2		T3	3
all_pins[8]	74676	1		T1	2		T2	2		T3	3
all_pins[9]	74676	1		T1	2		T2	2		T3	3
all_pins[10]	74676	1		T1	2		T2	2		T3	3
all_pins[11]	74676	1		T1	2		T2	2		T3	3
all_pins[12]	74676	1		T1	2		T2	2		T3	3
all_pins[13]	74676	1		T1	2		T2	2		T3	3
all_pins[14]	74676	1		T1	2		T2	2		T3	3
all_pins[15]	74676	1		T1	2		T2	2		T3	3
all_pins[16]	74676	1		T1	2		T2	2		T3	3
all_pins[17]	74676	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2387240	1		T1	63		T2	64		T3	96
values[0x1]	2392	1		T1	1		T34	1		T32	1
transitions[0x0=>0x1]	2116	1		T1	1		T34	1		T32	1
transitions[0x1=>0x0]	2116	1		T1	1		T34	1		T32	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	74566	1		T1	2		T2	2		T3	3
all_pins[0]	values[0x1]	110	1		T283	1		T284	1		T285	1
all_pins[0]	transitions[0x0=>0x1]	96	1		T283	1		T284	1		T285	1
all_pins[0]	transitions[0x1=>0x0]	1002	1		T32	1		T7	1		T56	1
all_pins[1]	values[0x0]	73660	1		T1	2		T2	2		T3	3
all_pins[1]	values[0x1]	1016	1		T32	1		T7	1		T56	1
all_pins[1]	transitions[0x0=>0x1]	999	1		T32	1		T7	1		T56	1
all_pins[1]	transitions[0x1=>0x0]	105	1		T43	1		T44	1		T50	1
all_pins[2]	values[0x0]	74554	1		T1	2		T2	2		T3	3
all_pins[2]	values[0x1]	122	1		T43	1		T44	1		T50	1
all_pins[2]	transitions[0x0=>0x1]	106	1		T43	1		T44	1		T50	1
all_pins[2]	transitions[0x1=>0x0]	61	1		T70	1		T208	2		T206	2
all_pins[3]	values[0x0]	74599	1		T1	2		T2	2		T3	3
all_pins[3]	values[0x1]	77	1		T70	1		T208	2		T206	2
all_pins[3]	transitions[0x0=>0x1]	59	1		T70	1		T208	2		T206	2
all_pins[3]	transitions[0x1=>0x0]	47	1		T71	1		T205	3		T208	2
all_pins[4]	values[0x0]	74611	1		T1	2		T2	2		T3	3
all_pins[4]	values[0x1]	65	1		T71	1		T205	3		T208	2
all_pins[4]	transitions[0x0=>0x1]	49	1		T71	1		T205	1		T208	2
all_pins[4]	transitions[0x1=>0x0]	68	1		T205	1		T207	1		T277	3
all_pins[5]	values[0x0]	74592	1		T1	2		T2	2		T3	3
all_pins[5]	values[0x1]	84	1		T205	3		T207	3		T277	4
all_pins[5]	transitions[0x0=>0x1]	53	1		T205	1		T207	3		T277	4
all_pins[5]	transitions[0x1=>0x0]	52	1		T208	1		T206	3		T279	2
all_pins[6]	values[0x0]	74593	1		T1	2		T2	2		T3	3
all_pins[6]	values[0x1]	83	1		T205	2		T208	1		T206	3
all_pins[6]	transitions[0x0=>0x1]	68	1		T205	2		T208	1		T206	3
all_pins[6]	transitions[0x1=>0x0]	59	1		T57	1		T205	1		T208	1
all_pins[7]	values[0x0]	74602	1		T1	2		T2	2		T3	3
all_pins[7]	values[0x1]	74	1		T57	1		T205	1		T208	1
all_pins[7]	transitions[0x0=>0x1]	59	1		T57	1		T205	1		T208	1
all_pins[7]	transitions[0x1=>0x0]	46	1		T60	1		T208	1		T207	1
all_pins[8]	values[0x0]	74615	1		T1	2		T2	2		T3	3
all_pins[8]	values[0x1]	61	1		T60	1		T208	1		T207	1
all_pins[8]	transitions[0x0=>0x1]	49	1		T60	1		T208	1		T207	1
all_pins[8]	transitions[0x1=>0x0]	70	1		T67	2		T68	2		T69	2
all_pins[9]	values[0x0]	74594	1		T1	2		T2	2		T3	3
all_pins[9]	values[0x1]	82	1		T67	2		T68	2		T69	2
all_pins[9]	transitions[0x0=>0x1]	66	1		T67	2		T68	2		T69	2
all_pins[9]	transitions[0x1=>0x0]	50	1		T205	3		T208	1		T206	2
all_pins[10]	values[0x0]	74610	1		T1	2		T2	2		T3	3
all_pins[10]	values[0x1]	66	1		T205	4		T208	1		T206	2
all_pins[10]	transitions[0x0=>0x1]	40	1		T205	3		T208	1		T206	2
all_pins[10]	transitions[0x1=>0x0]	102	1		T1	1		T34	1		T78	1
all_pins[11]	values[0x0]	74548	1		T1	1		T2	2		T3	3
all_pins[11]	values[0x1]	128	1		T1	1		T34	1		T78	1
all_pins[11]	transitions[0x0=>0x1]	114	1		T1	1		T34	1		T78	1
all_pins[11]	transitions[0x1=>0x0]	45	1		T80	1		T81	1		T82	1
all_pins[12]	values[0x0]	74617	1		T1	2		T2	2		T3	3
all_pins[12]	values[0x1]	59	1		T80	1		T81	1		T82	1
all_pins[12]	transitions[0x0=>0x1]	50	1		T80	1		T81	1		T82	1
all_pins[12]	transitions[0x1=>0x0]	113	1		T77	1		T79	1		T84	1
all_pins[13]	values[0x0]	74554	1		T1	2		T2	2		T3	3
all_pins[13]	values[0x1]	122	1		T77	1		T79	1		T84	1
all_pins[13]	transitions[0x0=>0x1]	108	1		T77	1		T79	1		T84	1
all_pins[13]	transitions[0x1=>0x0]	38	1		T207	3		T277	2		T280	2
all_pins[14]	values[0x0]	74624	1		T1	2		T2	2		T3	3
all_pins[14]	values[0x1]	52	1		T207	3		T277	2		T278	2
all_pins[14]	transitions[0x0=>0x1]	40	1		T207	2		T277	2		T278	2
all_pins[14]	transitions[0x1=>0x0]	44	1		T205	1		T206	2		T207	2
all_pins[15]	values[0x0]	74620	1		T1	2		T2	2		T3	3
all_pins[15]	values[0x1]	56	1		T205	1		T206	2		T207	3
all_pins[15]	transitions[0x0=>0x1]	41	1		T205	1		T206	2		T207	2
all_pins[15]	transitions[0x1=>0x0]	49	1		T74	4		T75	4		T76	4
all_pins[16]	values[0x0]	74612	1		T1	2		T2	2		T3	3
all_pins[16]	values[0x1]	64	1		T74	4		T75	4		T76	4
all_pins[16]	transitions[0x0=>0x1]	48	1		T74	4		T75	4		T76	4
all_pins[16]	transitions[0x1=>0x0]	55	1		T62	1		T63	1		T64	1
all_pins[17]	values[0x0]	74605	1		T1	2		T2	2		T3	3
all_pins[17]	values[0x1]	71	1		T62	1		T63	1		T64	1
all_pins[17]	transitions[0x0=>0x1]	71	1		T62	1		T63	1		T64	1