Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[12]	4872	1		T5	15		T17	17		T45	10
invalid_ep[13]	4819	1		T5	9		T17	27		T45	11
invalid_ep[14]	4825	1		T5	30		T17	26		T45	16
invalid_ep[15]	4836	1		T5	12		T17	13		T45	12
endpoints[0]	16401	1		T2	32		T4	34		T77	1
endpoints[1]	18266	1		T2	16		T3	2		T4	2
endpoints[2]	14745	1		T2	30		T28	14		T4	3
endpoints[3]	13334	1		T1	1		T2	35		T4	4
endpoints[4]	18962	1		T2	24		T33	25		T17	21
endpoints[5]	17566	1		T2	18		T4	33		T24	1
endpoints[6]	14227	1		T2	29		T4	3		T17	21
endpoints[7]	13537	1		T2	20		T34	1		T4	4
endpoints[8]	18466	1		T2	30		T30	8		T4	34
endpoints[9]	16468	1		T2	33		T4	4		T17	21
endpoints[10]	15228	1		T2	22		T4	35		T33	25
endpoints[11]	15390	1		T2	24		T29	7		T31	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	25667	1		T4	32		T6	48		T33	10
pkt_types[PidTypeOutToken]	105986	1		T1	1		T2	147		T3	1
pkt_types[PidTypeInToken]	80217	1		T2	166		T3	1		T28	6

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[12]	953	1		T92	13		T94	20		T95	29
pkt_types[PidTypeSetupToken]	invalid_ep[13]	909	1		T92	13		T94	15		T95	31
pkt_types[PidTypeSetupToken]	invalid_ep[14]	968	1		T92	21		T94	23		T95	30
pkt_types[PidTypeSetupToken]	invalid_ep[15]	963	1		T92	11		T94	20		T95	20
pkt_types[PidTypeSetupToken]	endpoints[0]	1878	1		T4	9		T17	5		T46	1
pkt_types[PidTypeSetupToken]	endpoints[1]	2055	1		T4	1		T33	6		T25	1
pkt_types[PidTypeSetupToken]	endpoints[2]	1965	1		T4	1		T18	52		T45	14
pkt_types[PidTypeSetupToken]	endpoints[3]	1619	1		T4	2		T33	4		T23	50
pkt_types[PidTypeSetupToken]	endpoints[4]	2015	1		T25	1		T153	5		T156	10
pkt_types[PidTypeSetupToken]	endpoints[5]	1695	1		T98	1		T157	1		T152	6
pkt_types[PidTypeSetupToken]	endpoints[6]	1618	1		T4	2		T25	4		T54	1
pkt_types[PidTypeSetupToken]	endpoints[7]	1777	1		T4	2		T153	2		T159	35
pkt_types[PidTypeSetupToken]	endpoints[8]	1878	1		T6	48		T17	5		T25	1
pkt_types[PidTypeSetupToken]	endpoints[9]	1899	1		T4	3		T17	4		T45	17
pkt_types[PidTypeSetupToken]	endpoints[10]	1783	1		T4	12		T20	45		T25	1
pkt_types[PidTypeSetupToken]	endpoints[11]	1692	1		T111	45		T17	7		T25	1
pkt_types[PidTypeOutToken]	invalid_ep[12]	2928	1		T5	15		T17	17		T45	10
pkt_types[PidTypeOutToken]	invalid_ep[13]	2970	1		T5	9		T17	27		T45	11
pkt_types[PidTypeOutToken]	invalid_ep[14]	2889	1		T5	30		T17	26		T45	16
pkt_types[PidTypeOutToken]	invalid_ep[15]	2870	1		T5	12		T17	13		T45	12
pkt_types[PidTypeOutToken]	endpoints[0]	8207	1		T2	13		T4	8		T77	1
pkt_types[PidTypeOutToken]	endpoints[1]	9999	1		T2	8		T3	1		T4	1
pkt_types[PidTypeOutToken]	endpoints[2]	6141	1		T2	14		T28	8		T4	1
pkt_types[PidTypeOutToken]	endpoints[3]	6060	1		T1	1		T2	20		T4	1
pkt_types[PidTypeOutToken]	endpoints[4]	10649	1		T2	9		T33	12		T17	10
pkt_types[PidTypeOutToken]	endpoints[5]	9008	1		T2	10		T4	16		T24	1
pkt_types[PidTypeOutToken]	endpoints[6]	7057	1		T2	9		T17	10		T25	12
pkt_types[PidTypeOutToken]	endpoints[7]	5775	1		T2	9		T34	1		T4	1
pkt_types[PidTypeOutToken]	endpoints[8]	9453	1		T2	16		T30	3		T4	17
pkt_types[PidTypeOutToken]	endpoints[9]	7313	1		T2	14		T17	6		T25	2
pkt_types[PidTypeOutToken]	endpoints[10]	7055	1		T2	12		T4	6		T33	12
pkt_types[PidTypeOutToken]	endpoints[11]	7612	1		T2	13		T31	1		T32	1
pkt_types[PidTypeInToken]	invalid_ep[12]	991	1		T92	16		T94	20		T95	26
pkt_types[PidTypeInToken]	invalid_ep[13]	940	1		T92	17		T94	15		T95	22
pkt_types[PidTypeInToken]	invalid_ep[14]	968	1		T92	22		T94	15		T95	33
pkt_types[PidTypeInToken]	invalid_ep[15]	1003	1		T92	18		T94	21		T95	39
pkt_types[PidTypeInToken]	endpoints[0]	6315	1		T2	19		T4	17		T33	13
pkt_types[PidTypeInToken]	endpoints[1]	6208	1		T2	8		T3	1		T33	13
pkt_types[PidTypeInToken]	endpoints[2]	6636	1		T2	16		T28	6		T4	1
pkt_types[PidTypeInToken]	endpoints[3]	5646	1		T2	15		T4	1		T33	13
pkt_types[PidTypeInToken]	endpoints[4]	6284	1		T2	15		T33	13		T17	11
pkt_types[PidTypeInToken]	endpoints[5]	6856	1		T2	8		T4	17		T25	13
pkt_types[PidTypeInToken]	endpoints[6]	5546	1		T2	20		T4	1		T17	11
pkt_types[PidTypeInToken]	endpoints[7]	5977	1		T2	11		T4	1		T17	11
pkt_types[PidTypeInToken]	endpoints[8]	7129	1		T2	14		T30	5		T4	17
pkt_types[PidTypeInToken]	endpoints[9]	7250	1		T2	19		T4	1		T17	11
pkt_types[PidTypeInToken]	endpoints[10]	6387	1		T2	10		T4	17		T33	13
pkt_types[PidTypeInToken]	endpoints[11]	6081	1		T2	11		T29	7		T32	1