Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1		T205	7		T208	7		T206	4
all_values[1]	287	1		T205	7		T208	7		T206	4
all_values[2]	287	1		T205	7		T208	7		T206	4
all_values[3]	287	1		T205	7		T208	7		T206	4
all_values[4]	287	1		T205	7		T208	7		T206	4
all_values[5]	287	1		T205	7		T208	7		T206	4
all_values[6]	287	1		T205	7		T208	7		T206	4
all_values[7]	287	1		T205	7		T208	7		T206	4
all_values[8]	287	1		T205	7		T208	7		T206	4
all_values[9]	287	1		T205	7		T208	7		T206	4
all_values[10]	287	1		T205	7		T208	7		T206	4
all_values[11]	287	1		T205	7		T208	7		T206	4
all_values[12]	287	1		T205	7		T208	7		T206	4
all_values[13]	287	1		T205	7		T208	7		T206	4
all_values[14]	287	1		T205	7		T208	7		T206	4
all_values[15]	287	1		T205	7		T208	7		T206	4
all_values[16]	287	1		T205	7		T208	7		T206	4
all_values[17]	287	1		T205	7		T208	7		T206	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6765	1		T205	170		T208	158		T206	97
auto[1]	2419	1		T205	54		T208	66		T206	31

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6283	1		T205	152		T208	165		T206	86
auto[1]	2901	1		T205	72		T208	59		T206	42

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5399	1		T205	131		T208	130		T206	75
auto[1]	3785	1		T205	93		T208	94		T206	53

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	82	1		T205	2		T208	2		T277	3
all_values[0]	auto[0]	auto[1]	auto[0]	86	1		T205	1		T208	3		T206	1
all_values[0]	auto[1]	auto[0]	auto[1]	62	1		T207	2		T277	2		T278	2
all_values[0]	auto[1]	auto[1]	auto[1]	57	1		T205	4		T208	2		T206	3
all_values[1]	auto[0]	auto[0]	auto[0]	78	1		T205	1		T208	2		T206	2
all_values[1]	auto[0]	auto[1]	auto[0]	85	1		T205	4		T208	1		T207	3
all_values[1]	auto[1]	auto[0]	auto[1]	67	1		T205	1		T208	2		T206	2
all_values[1]	auto[1]	auto[1]	auto[1]	57	1		T205	1		T208	2		T207	2
all_values[2]	auto[0]	auto[0]	auto[0]	41	1		T208	2		T279	2		T266	3
all_values[2]	auto[0]	auto[0]	auto[1]	51	1		T205	1		T206	2		T207	1
all_values[2]	auto[0]	auto[1]	auto[0]	40	1		T205	2		T208	2		T207	2
all_values[2]	auto[0]	auto[1]	auto[1]	39	1		T205	1		T207	2		T277	1
all_values[2]	auto[1]	auto[0]	auto[1]	72	1		T205	1		T208	2		T207	2
all_values[2]	auto[1]	auto[1]	auto[1]	44	1		T205	2		T208	1		T206	2
all_values[3]	auto[0]	auto[0]	auto[0]	68	1		T205	5		T208	1		T207	2
all_values[3]	auto[0]	auto[0]	auto[1]	22	1		T277	1		T279	1		T280	1
all_values[3]	auto[0]	auto[1]	auto[0]	47	1		T205	1		T208	1		T206	1
all_values[3]	auto[0]	auto[1]	auto[1]	25	1		T206	1		T207	2		T279	1
all_values[3]	auto[1]	auto[0]	auto[1]	61	1		T205	1		T208	2		T206	1
all_values[3]	auto[1]	auto[1]	auto[1]	64	1		T208	3		T206	1		T207	3
all_values[4]	auto[0]	auto[0]	auto[0]	71	1		T205	1		T208	1		T206	3
all_values[4]	auto[0]	auto[0]	auto[1]	32	1		T208	1		T277	1		T279	4
all_values[4]	auto[0]	auto[1]	auto[0]	45	1		T208	1		T206	1		T207	1
all_values[4]	auto[0]	auto[1]	auto[1]	29	1		T205	1		T208	2		T207	2
all_values[4]	auto[1]	auto[0]	auto[1]	59	1		T205	3		T277	3		T266	2
all_values[4]	auto[1]	auto[1]	auto[1]	51	1		T205	2		T208	2		T207	4
all_values[5]	auto[0]	auto[0]	auto[0]	58	1		T205	1		T208	3		T207	1
all_values[5]	auto[0]	auto[0]	auto[1]	31	1		T205	1		T206	1		T279	2
all_values[5]	auto[0]	auto[1]	auto[0]	40	1		T205	1		T208	2		T206	1
all_values[5]	auto[0]	auto[1]	auto[1]	37	1		T205	1		T277	2		T280	1
all_values[5]	auto[1]	auto[0]	auto[1]	63	1		T206	2		T207	4		T278	3
all_values[5]	auto[1]	auto[1]	auto[1]	58	1		T205	3		T208	2		T207	2
all_values[6]	auto[0]	auto[0]	auto[0]	62	1		T205	3		T207	1		T277	4
all_values[6]	auto[0]	auto[0]	auto[1]	22	1		T207	1		T277	1		T278	1
all_values[6]	auto[0]	auto[1]	auto[0]	41	1		T205	1		T208	3		T207	3
all_values[6]	auto[0]	auto[1]	auto[1]	33	1		T205	1		T206	1		T279	2
all_values[6]	auto[1]	auto[0]	auto[1]	68	1		T205	1		T208	3		T206	1
all_values[6]	auto[1]	auto[1]	auto[1]	61	1		T205	1		T208	1		T206	2
all_values[7]	auto[0]	auto[0]	auto[0]	81	1		T205	3		T208	4		T206	1
all_values[7]	auto[0]	auto[1]	auto[0]	77	1		T205	1		T208	2		T206	2
all_values[7]	auto[1]	auto[0]	auto[1]	61	1		T205	2		T208	1		T206	1
all_values[7]	auto[1]	auto[1]	auto[1]	68	1		T205	1		T207	1		T277	2
all_values[8]	auto[0]	auto[0]	auto[0]	80	1		T205	1		T208	1		T206	2
all_values[8]	auto[0]	auto[1]	auto[0]	84	1		T205	2		T208	4		T206	1
all_values[8]	auto[1]	auto[0]	auto[1]	69	1		T205	3		T208	2		T206	1
all_values[8]	auto[1]	auto[1]	auto[1]	54	1		T205	1		T277	2		T278	2
all_values[9]	auto[0]	auto[0]	auto[0]	58	1		T205	2		T208	1		T206	1
all_values[9]	auto[0]	auto[0]	auto[1]	27	1		T205	1		T206	1		T207	1
all_values[9]	auto[0]	auto[1]	auto[0]	51	1		T208	1		T207	3		T277	1
all_values[9]	auto[0]	auto[1]	auto[1]	33	1		T205	1		T277	1		T278	2
all_values[9]	auto[1]	auto[0]	auto[1]	59	1		T205	2		T208	2		T206	1
all_values[9]	auto[1]	auto[1]	auto[1]	59	1		T205	1		T208	3		T206	1
all_values[10]	auto[0]	auto[0]	auto[0]	68	1		T207	1		T277	1		T278	1
all_values[10]	auto[0]	auto[0]	auto[1]	32	1		T205	3		T208	2		T279	2
all_values[10]	auto[0]	auto[1]	auto[0]	44	1		T208	1		T206	1		T207	2
all_values[10]	auto[0]	auto[1]	auto[1]	23	1		T205	1		T206	1		T277	1
all_values[10]	auto[1]	auto[0]	auto[1]	56	1		T208	1		T206	1		T207	1
all_values[10]	auto[1]	auto[1]	auto[1]	64	1		T205	3		T208	3		T206	1
all_values[11]	auto[0]	auto[0]	auto[0]	61	1		T205	3		T208	2		T207	1
all_values[11]	auto[0]	auto[0]	auto[1]	26	1		T205	1		T206	1		T207	2
all_values[11]	auto[0]	auto[1]	auto[0]	42	1		T208	5		T277	2		T279	1
all_values[11]	auto[0]	auto[1]	auto[1]	38	1		T207	1		T280	2		T281	1
all_values[11]	auto[1]	auto[0]	auto[1]	74	1		T205	1		T206	3		T207	2
all_values[11]	auto[1]	auto[1]	auto[1]	46	1		T205	2		T207	1		T279	2
all_values[12]	auto[0]	auto[0]	auto[0]	73	1		T205	1		T208	1		T206	1
all_values[12]	auto[0]	auto[0]	auto[1]	18	1		T206	2		T277	2		T281	2
all_values[12]	auto[0]	auto[1]	auto[0]	66	1		T205	2		T208	3		T207	1
all_values[12]	auto[0]	auto[1]	auto[1]	24	1		T205	1		T278	1		T279	2
all_values[12]	auto[1]	auto[0]	auto[1]	56	1		T205	1		T208	2		T206	1
all_values[12]	auto[1]	auto[1]	auto[1]	50	1		T205	2		T208	1		T207	3
all_values[13]	auto[0]	auto[0]	auto[0]	60	1		T205	2		T207	1		T279	1
all_values[13]	auto[0]	auto[0]	auto[1]	27	1		T208	2		T207	1		T277	1
all_values[13]	auto[0]	auto[1]	auto[0]	47	1		T205	2		T208	1		T206	3
all_values[13]	auto[0]	auto[1]	auto[1]	30	1		T277	2		T278	1		T266	1
all_values[13]	auto[1]	auto[0]	auto[1]	65	1		T205	3		T208	1		T206	1
all_values[13]	auto[1]	auto[1]	auto[1]	58	1		T208	3		T277	1		T278	1
all_values[14]	auto[0]	auto[0]	auto[0]	74	1		T205	5		T208	3		T206	1
all_values[14]	auto[0]	auto[0]	auto[1]	27	1		T205	1		T277	2		T278	1
all_values[14]	auto[0]	auto[1]	auto[0]	51	1		T208	2		T206	2		T279	1
all_values[14]	auto[0]	auto[1]	auto[1]	19	1		T277	2		T278	1		T280	1
all_values[14]	auto[1]	auto[0]	auto[1]	65	1		T205	1		T208	2		T206	1
all_values[14]	auto[1]	auto[1]	auto[1]	51	1		T207	4		T279	2		T280	2
all_values[15]	auto[0]	auto[0]	auto[0]	51	1		T208	1		T207	1		T277	2
all_values[15]	auto[0]	auto[0]	auto[1]	29	1		T205	1		T208	1		T277	1
all_values[15]	auto[0]	auto[1]	auto[0]	56	1		T208	2		T206	2		T207	1
all_values[15]	auto[0]	auto[1]	auto[1]	27	1		T206	1		T207	2		T282	1
all_values[15]	auto[1]	auto[0]	auto[1]	70	1		T205	4		T208	3		T207	1
all_values[15]	auto[1]	auto[1]	auto[1]	54	1		T205	2		T206	1		T207	2
all_values[16]	auto[0]	auto[0]	auto[0]	72	1		T205	2		T208	2		T206	1
all_values[16]	auto[0]	auto[0]	auto[1]	27	1		T206	1		T207	1		T266	1
all_values[16]	auto[0]	auto[1]	auto[0]	55	1		T205	2		T208	3		T207	2
all_values[16]	auto[0]	auto[1]	auto[1]	19	1		T207	2		T280	1		T282	1
all_values[16]	auto[1]	auto[0]	auto[1]	66	1		T205	1		T208	1		T206	2
all_values[16]	auto[1]	auto[1]	auto[1]	48	1		T205	2		T208	1		T207	2
all_values[17]	auto[0]	auto[0]	auto[0]	89	1		T205	3		T208	2		T206	2
all_values[17]	auto[0]	auto[1]	auto[0]	81	1		T208	2		T206	1		T207	4
all_values[17]	auto[1]	auto[0]	auto[1]	56	1		T205	3		T208	2		T206	1
all_values[17]	auto[1]	auto[1]	auto[1]	61	1		T205	1		T208	1		T207	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal