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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.01 97.82 93.74 97.44 75.00 96.26 98.17 71.64


Total test records in report: 2977
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T210 /workspace/coverage/default/0.usbdev_sec_cm.932954905 Jul 29 06:10:31 PM PDT 24 Jul 29 06:10:33 PM PDT 24 403689211 ps
T2811 /workspace/coverage/default/20.usbdev_max_length_in_transaction.2377435226 Jul 29 06:14:50 PM PDT 24 Jul 29 06:14:51 PM PDT 24 258370465 ps
T2812 /workspace/coverage/default/3.usbdev_device_timeout.1005526759 Jul 29 06:11:12 PM PDT 24 Jul 29 06:11:32 PM PDT 24 2910356357 ps
T2813 /workspace/coverage/default/49.usbdev_aon_wake_resume.52901077 Jul 29 06:19:30 PM PDT 24 Jul 29 06:19:58 PM PDT 24 23334242350 ps
T2814 /workspace/coverage/default/1.usbdev_smoke.3741664947 Jul 29 06:10:40 PM PDT 24 Jul 29 06:10:41 PM PDT 24 218838143 ps
T2815 /workspace/coverage/default/17.usbdev_stall_priority_over_nak.4152429830 Jul 29 06:14:26 PM PDT 24 Jul 29 06:14:27 PM PDT 24 150743148 ps
T2816 /workspace/coverage/default/47.usbdev_link_resume.500978832 Jul 29 06:19:03 PM PDT 24 Jul 29 06:19:36 PM PDT 24 23346454060 ps
T2817 /workspace/coverage/default/6.usbdev_device_address.319906781 Jul 29 06:12:02 PM PDT 24 Jul 29 06:12:40 PM PDT 24 15840441811 ps
T2818 /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.4155265663 Jul 29 06:11:40 PM PDT 24 Jul 29 06:11:41 PM PDT 24 214308593 ps
T2819 /workspace/coverage/default/14.usbdev_aon_wake_disconnect.2024527709 Jul 29 06:13:45 PM PDT 24 Jul 29 06:13:51 PM PDT 24 4198141980 ps
T2820 /workspace/coverage/default/0.usbdev_link_resume.1409561793 Jul 29 06:10:14 PM PDT 24 Jul 29 06:10:45 PM PDT 24 23356630096 ps
T2821 /workspace/coverage/default/45.usbdev_aon_wake_reset.368619390 Jul 29 06:18:45 PM PDT 24 Jul 29 06:19:01 PM PDT 24 13350843148 ps
T2822 /workspace/coverage/default/0.usbdev_aon_wake_reset.969484982 Jul 29 06:10:03 PM PDT 24 Jul 29 06:10:17 PM PDT 24 13372922325 ps
T2823 /workspace/coverage/default/12.usbdev_data_toggle_restore.2121270153 Jul 29 06:13:25 PM PDT 24 Jul 29 06:13:29 PM PDT 24 1340771262 ps
T2824 /workspace/coverage/default/2.usbdev_aon_wake_reset.1875189537 Jul 29 06:10:47 PM PDT 24 Jul 29 06:11:02 PM PDT 24 13438118271 ps
T2825 /workspace/coverage/default/36.usbdev_out_stall.2414117926 Jul 29 06:17:27 PM PDT 24 Jul 29 06:17:28 PM PDT 24 193025489 ps
T2826 /workspace/coverage/default/42.usbdev_invalid_sync.1492921918 Jul 29 06:18:19 PM PDT 24 Jul 29 06:22:40 PM PDT 24 9027476050 ps
T2827 /workspace/coverage/default/27.usbdev_min_length_out_transaction.2263374754 Jul 29 06:16:04 PM PDT 24 Jul 29 06:16:05 PM PDT 24 156272567 ps
T2828 /workspace/coverage/default/30.usbdev_low_speed_traffic.2844934973 Jul 29 06:16:36 PM PDT 24 Jul 29 06:20:55 PM PDT 24 8981207137 ps
T2829 /workspace/coverage/default/47.usbdev_disconnected.3941250254 Jul 29 06:19:03 PM PDT 24 Jul 29 06:19:04 PM PDT 24 142870971 ps
T2830 /workspace/coverage/default/20.usbdev_aon_wake_reset.2802781004 Jul 29 06:14:49 PM PDT 24 Jul 29 06:15:03 PM PDT 24 13337485130 ps
T2831 /workspace/coverage/default/41.usbdev_aon_wake_reset.3251169369 Jul 29 06:18:14 PM PDT 24 Jul 29 06:18:31 PM PDT 24 13392857629 ps
T2832 /workspace/coverage/default/48.usbdev_link_suspend.4225721968 Jul 29 06:19:11 PM PDT 24 Jul 29 06:19:16 PM PDT 24 3327289607 ps
T2833 /workspace/coverage/default/12.usbdev_iso_retraction.1297867306 Jul 29 06:13:23 PM PDT 24 Jul 29 06:15:02 PM PDT 24 15300860493 ps
T2834 /workspace/coverage/default/37.usbdev_aon_wake_reset.383517131 Jul 29 06:17:32 PM PDT 24 Jul 29 06:17:49 PM PDT 24 13376608318 ps
T2835 /workspace/coverage/default/37.usbdev_link_suspend.2732880541 Jul 29 06:17:38 PM PDT 24 Jul 29 06:17:43 PM PDT 24 3297362841 ps
T2836 /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2015355614 Jul 29 06:17:14 PM PDT 24 Jul 29 06:17:50 PM PDT 24 3553623325 ps
T2837 /workspace/coverage/default/22.usbdev_smoke.3179334344 Jul 29 06:15:20 PM PDT 24 Jul 29 06:15:21 PM PDT 24 214544672 ps
T2838 /workspace/coverage/default/42.usbdev_min_length_in_transaction.4056847015 Jul 29 06:18:25 PM PDT 24 Jul 29 06:18:26 PM PDT 24 157765166 ps
T2839 /workspace/coverage/default/44.usbdev_stream_len_max.4286586046 Jul 29 06:18:54 PM PDT 24 Jul 29 06:18:57 PM PDT 24 751357024 ps
T2840 /workspace/coverage/default/42.usbdev_data_toggle_restore.946426931 Jul 29 06:18:21 PM PDT 24 Jul 29 06:18:24 PM PDT 24 1475971304 ps
T2841 /workspace/coverage/default/39.usbdev_device_timeout.2260761326 Jul 29 06:17:47 PM PDT 24 Jul 29 06:18:28 PM PDT 24 5633854833 ps
T2842 /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3000962820 Jul 29 06:17:07 PM PDT 24 Jul 29 06:17:35 PM PDT 24 3698680160 ps
T2843 /workspace/coverage/default/26.usbdev_out_iso.888100104 Jul 29 06:15:59 PM PDT 24 Jul 29 06:16:00 PM PDT 24 157266216 ps
T2844 /workspace/coverage/default/44.usbdev_rx_crc_err.1858087963 Jul 29 06:18:57 PM PDT 24 Jul 29 06:18:59 PM PDT 24 144549381 ps
T2845 /workspace/coverage/default/20.usbdev_device_timeout.1704065987 Jul 29 06:14:52 PM PDT 24 Jul 29 06:15:04 PM PDT 24 569173193 ps
T2846 /workspace/coverage/default/4.usbdev_max_length_in_transaction.3936701929 Jul 29 06:11:30 PM PDT 24 Jul 29 06:11:31 PM PDT 24 261330400 ps
T2847 /workspace/coverage/default/26.usbdev_pending_in_trans.2872728319 Jul 29 06:15:55 PM PDT 24 Jul 29 06:15:56 PM PDT 24 171014460 ps
T2848 /workspace/coverage/default/17.usbdev_endpoint_access.990925552 Jul 29 06:14:28 PM PDT 24 Jul 29 06:14:31 PM PDT 24 877949368 ps
T2849 /workspace/coverage/default/44.usbdev_in_iso.662155700 Jul 29 06:18:39 PM PDT 24 Jul 29 06:18:40 PM PDT 24 179915397 ps
T2850 /workspace/coverage/default/25.usbdev_fifo_rst.1646815325 Jul 29 06:15:44 PM PDT 24 Jul 29 06:15:46 PM PDT 24 377141923 ps
T2851 /workspace/coverage/default/2.usbdev_setup_stage.3652546166 Jul 29 06:11:04 PM PDT 24 Jul 29 06:11:05 PM PDT 24 236580995 ps
T2852 /workspace/coverage/default/32.usbdev_low_speed_traffic.698402351 Jul 29 06:16:50 PM PDT 24 Jul 29 06:18:17 PM PDT 24 8442236471 ps
T2853 /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3373409430 Jul 29 06:14:26 PM PDT 24 Jul 29 06:14:27 PM PDT 24 150843762 ps
T2854 /workspace/coverage/default/10.usbdev_streaming_out.1754651939 Jul 29 06:13:11 PM PDT 24 Jul 29 06:16:35 PM PDT 24 6538865886 ps
T2855 /workspace/coverage/default/48.usbdev_invalid_sync.508617107 Jul 29 06:19:11 PM PDT 24 Jul 29 06:23:16 PM PDT 24 8187879720 ps
T2856 /workspace/coverage/default/28.usbdev_in_stall.854888859 Jul 29 06:16:08 PM PDT 24 Jul 29 06:16:09 PM PDT 24 167354834 ps
T2857 /workspace/coverage/default/39.usbdev_random_length_in_transaction.1380435304 Jul 29 06:17:54 PM PDT 24 Jul 29 06:17:56 PM PDT 24 200347452 ps
T2858 /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2489142218 Jul 29 06:16:40 PM PDT 24 Jul 29 06:17:36 PM PDT 24 5259470889 ps
T2859 /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.1236260531 Jul 29 06:13:41 PM PDT 24 Jul 29 06:13:46 PM PDT 24 359388054 ps
T2860 /workspace/coverage/default/12.usbdev_smoke.1303015655 Jul 29 06:13:31 PM PDT 24 Jul 29 06:13:33 PM PDT 24 303636524 ps
T2861 /workspace/coverage/default/30.usbdev_disconnected.4104664674 Jul 29 06:16:31 PM PDT 24 Jul 29 06:16:32 PM PDT 24 143018346 ps
T2862 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2116792780 Jul 29 05:13:16 PM PDT 24 Jul 29 05:13:21 PM PDT 24 744682555 ps
T216 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2334261617 Jul 29 05:13:40 PM PDT 24 Jul 29 05:13:41 PM PDT 24 56229586 ps
T205 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.682197251 Jul 29 05:13:58 PM PDT 24 Jul 29 05:13:59 PM PDT 24 54852676 ps
T194 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4137426942 Jul 29 05:13:45 PM PDT 24 Jul 29 05:13:46 PM PDT 24 103476656 ps
T208 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.376380755 Jul 29 05:13:48 PM PDT 24 Jul 29 05:13:49 PM PDT 24 87014614 ps
T206 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3216307557 Jul 29 05:13:22 PM PDT 24 Jul 29 05:13:23 PM PDT 24 41580108 ps
T195 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.790696516 Jul 29 05:13:52 PM PDT 24 Jul 29 05:13:57 PM PDT 24 1460959287 ps
T196 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1808257652 Jul 29 05:13:25 PM PDT 24 Jul 29 05:13:27 PM PDT 24 82222911 ps
T207 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2524307474 Jul 29 05:13:56 PM PDT 24 Jul 29 05:13:57 PM PDT 24 51290612 ps
T277 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4005472500 Jul 29 05:13:59 PM PDT 24 Jul 29 05:14:00 PM PDT 24 82822962 ps
T278 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1797467110 Jul 29 05:13:28 PM PDT 24 Jul 29 05:13:29 PM PDT 24 39790050 ps
T200 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1918746053 Jul 29 05:13:57 PM PDT 24 Jul 29 05:13:59 PM PDT 24 166003885 ps
T2863 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.128187452 Jul 29 05:13:27 PM PDT 24 Jul 29 05:13:30 PM PDT 24 410202513 ps
T279 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2094945676 Jul 29 05:13:52 PM PDT 24 Jul 29 05:13:53 PM PDT 24 30399487 ps
T254 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.434164312 Jul 29 05:13:52 PM PDT 24 Jul 29 05:13:53 PM PDT 24 110809873 ps
T266 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3790637355 Jul 29 05:14:08 PM PDT 24 Jul 29 05:14:09 PM PDT 24 56251859 ps
T215 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1684635401 Jul 29 05:13:51 PM PDT 24 Jul 29 05:13:53 PM PDT 24 96509727 ps
T242 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2329519324 Jul 29 05:13:18 PM PDT 24 Jul 29 05:13:19 PM PDT 24 42835990 ps
T280 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2408963931 Jul 29 05:13:52 PM PDT 24 Jul 29 05:13:53 PM PDT 24 78545527 ps
T255 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4193321639 Jul 29 05:13:34 PM PDT 24 Jul 29 05:13:34 PM PDT 24 69505983 ps
T243 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2552413606 Jul 29 05:13:29 PM PDT 24 Jul 29 05:13:33 PM PDT 24 354551249 ps
T201 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3224608243 Jul 29 05:13:57 PM PDT 24 Jul 29 05:13:59 PM PDT 24 221485053 ps
T256 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.223617257 Jul 29 05:13:51 PM PDT 24 Jul 29 05:13:52 PM PDT 24 72315122 ps
T2864 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1074313210 Jul 29 05:13:19 PM PDT 24 Jul 29 05:13:21 PM PDT 24 77734006 ps
T282 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2020308171 Jul 29 05:14:05 PM PDT 24 Jul 29 05:14:06 PM PDT 24 40322487 ps
T2865 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3644531012 Jul 29 05:13:23 PM PDT 24 Jul 29 05:13:26 PM PDT 24 260386565 ps
T257 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.384572387 Jul 29 05:13:47 PM PDT 24 Jul 29 05:13:49 PM PDT 24 212609366 ps
T258 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4063069861 Jul 29 05:13:47 PM PDT 24 Jul 29 05:13:49 PM PDT 24 148962029 ps
T281 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.803425258 Jul 29 05:14:02 PM PDT 24 Jul 29 05:14:03 PM PDT 24 55029858 ps
T244 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3136755702 Jul 29 05:13:21 PM PDT 24 Jul 29 05:13:25 PM PDT 24 308379613 ps
T267 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2235529187 Jul 29 05:13:55 PM PDT 24 Jul 29 05:13:56 PM PDT 24 38247277 ps
T2866 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4148878696 Jul 29 05:14:01 PM PDT 24 Jul 29 05:14:02 PM PDT 24 63499476 ps
T245 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2760586948 Jul 29 05:13:25 PM PDT 24 Jul 29 05:13:35 PM PDT 24 2001884022 ps
T259 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3389129603 Jul 29 05:13:45 PM PDT 24 Jul 29 05:13:47 PM PDT 24 147945078 ps
T221 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2453005175 Jul 29 05:13:24 PM PDT 24 Jul 29 05:13:25 PM PDT 24 45576557 ps
T220 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4102645379 Jul 29 05:13:28 PM PDT 24 Jul 29 05:13:32 PM PDT 24 504191438 ps
T2867 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2269217085 Jul 29 05:14:13 PM PDT 24 Jul 29 05:14:14 PM PDT 24 38864173 ps
T246 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2268869107 Jul 29 05:13:26 PM PDT 24 Jul 29 05:13:27 PM PDT 24 69188896 ps
T232 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.187871644 Jul 29 05:13:52 PM PDT 24 Jul 29 05:13:54 PM PDT 24 94325970 ps
T2868 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.323527371 Jul 29 05:14:02 PM PDT 24 Jul 29 05:14:02 PM PDT 24 79900241 ps
T2869 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2328484510 Jul 29 05:13:20 PM PDT 24 Jul 29 05:13:21 PM PDT 24 55367843 ps
T2870 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2952790033 Jul 29 05:13:17 PM PDT 24 Jul 29 05:13:22 PM PDT 24 533561114 ps
T222 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3309212872 Jul 29 05:13:36 PM PDT 24 Jul 29 05:13:42 PM PDT 24 1932938865 ps
T226 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1969622371 Jul 29 05:13:41 PM PDT 24 Jul 29 05:13:42 PM PDT 24 85179997 ps
T223 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.121141690 Jul 29 05:13:46 PM PDT 24 Jul 29 05:13:49 PM PDT 24 328447605 ps
T2871 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1974413142 Jul 29 05:13:57 PM PDT 24 Jul 29 05:13:58 PM PDT 24 40793310 ps
T264 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3943540358 Jul 29 05:13:44 PM PDT 24 Jul 29 05:13:47 PM PDT 24 421402683 ps
T225 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1942757546 Jul 29 05:13:25 PM PDT 24 Jul 29 05:13:27 PM PDT 24 187028840 ps
T260 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3316334158 Jul 29 05:13:17 PM PDT 24 Jul 29 05:13:19 PM PDT 24 279575481 ps
T224 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2374935073 Jul 29 05:13:29 PM PDT 24 Jul 29 05:13:32 PM PDT 24 282167962 ps
T231 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.594549904 Jul 29 05:13:44 PM PDT 24 Jul 29 05:13:46 PM PDT 24 162971781 ps
T2872 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3899031608 Jul 29 05:13:57 PM PDT 24 Jul 29 05:13:58 PM PDT 24 38278699 ps
T2873 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2410980146 Jul 29 05:13:57 PM PDT 24 Jul 29 05:13:58 PM PDT 24 42394753 ps
T2874 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3266778465 Jul 29 05:13:45 PM PDT 24 Jul 29 05:13:46 PM PDT 24 37873694 ps
T247 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2792206426 Jul 29 05:13:20 PM PDT 24 Jul 29 05:13:30 PM PDT 24 2001279706 ps
T227 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1335899630 Jul 29 05:13:35 PM PDT 24 Jul 29 05:13:38 PM PDT 24 250858738 ps
T2875 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1584214628 Jul 29 05:13:45 PM PDT 24 Jul 29 05:13:46 PM PDT 24 67779408 ps
T248 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2959167053 Jul 29 05:13:34 PM PDT 24 Jul 29 05:13:36 PM PDT 24 98085956 ps
T249 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2078110911 Jul 29 05:13:25 PM PDT 24 Jul 29 05:13:27 PM PDT 24 122104270 ps
T287 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1687047212 Jul 29 05:13:24 PM PDT 24 Jul 29 05:13:27 PM PDT 24 476794803 ps
T265 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1463632403 Jul 29 05:13:47 PM PDT 24 Jul 29 05:13:52 PM PDT 24 1289778062 ps
T250 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3952081772 Jul 29 05:13:29 PM PDT 24 Jul 29 05:13:30 PM PDT 24 123680288 ps
T2876 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1526798100 Jul 29 05:13:20 PM PDT 24 Jul 29 05:13:22 PM PDT 24 105669916 ps
T2877 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1949737492 Jul 29 05:13:51 PM PDT 24 Jul 29 05:13:53 PM PDT 24 84539251 ps
T2878 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.881537984 Jul 29 05:13:43 PM PDT 24 Jul 29 05:13:46 PM PDT 24 102653632 ps
T286 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2725660218 Jul 29 05:13:39 PM PDT 24 Jul 29 05:13:44 PM PDT 24 884458391 ps
T2879 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2765259802 Jul 29 05:13:47 PM PDT 24 Jul 29 05:13:47 PM PDT 24 55075913 ps
T2880 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3474058761 Jul 29 05:13:26 PM PDT 24 Jul 29 05:13:29 PM PDT 24 413206948 ps
T2881 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1211919384 Jul 29 05:13:25 PM PDT 24 Jul 29 05:13:27 PM PDT 24 171550893 ps
T2882 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2103907181 Jul 29 05:13:29 PM PDT 24 Jul 29 05:13:30 PM PDT 24 136547225 ps
T2883 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3204458934 Jul 29 05:13:42 PM PDT 24 Jul 29 05:13:43 PM PDT 24 110516280 ps
T2884 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3851827557 Jul 29 05:13:28 PM PDT 24 Jul 29 05:13:30 PM PDT 24 172801204 ps
T2885 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.671436437 Jul 29 05:13:51 PM PDT 24 Jul 29 05:13:53 PM PDT 24 109986247 ps
T2886 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1634535585 Jul 29 05:13:24 PM PDT 24 Jul 29 05:13:25 PM PDT 24 76911510 ps
T2887 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2041691064 Jul 29 05:13:28 PM PDT 24 Jul 29 05:13:30 PM PDT 24 124646087 ps
T2888 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3566158705 Jul 29 05:13:23 PM PDT 24 Jul 29 05:13:24 PM PDT 24 191138888 ps
T228 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1256557467 Jul 29 05:13:36 PM PDT 24 Jul 29 05:13:40 PM PDT 24 358086308 ps
T2889 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3871194372 Jul 29 05:13:53 PM PDT 24 Jul 29 05:13:54 PM PDT 24 37761706 ps
T2890 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.652116450 Jul 29 05:13:58 PM PDT 24 Jul 29 05:13:59 PM PDT 24 43321513 ps
T288 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.72302796 Jul 29 05:13:33 PM PDT 24 Jul 29 05:13:38 PM PDT 24 1029635997 ps
T2891 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1864979194 Jul 29 05:13:42 PM PDT 24 Jul 29 05:13:44 PM PDT 24 220311903 ps
T2892 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2839884937 Jul 29 05:13:34 PM PDT 24 Jul 29 05:13:36 PM PDT 24 247411411 ps
T2893 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3052152067 Jul 29 05:13:39 PM PDT 24 Jul 29 05:13:40 PM PDT 24 70016630 ps
T230 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.178669309 Jul 29 05:13:53 PM PDT 24 Jul 29 05:13:55 PM PDT 24 151749437 ps
T2894 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1364987301 Jul 29 05:13:44 PM PDT 24 Jul 29 05:13:45 PM PDT 24 40326062 ps
T2895 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2049485302 Jul 29 05:13:24 PM PDT 24 Jul 29 05:13:32 PM PDT 24 1656988270 ps
T2896 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.4284034551 Jul 29 05:13:34 PM PDT 24 Jul 29 05:13:35 PM PDT 24 52262130 ps
T251 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.461508504 Jul 29 05:13:44 PM PDT 24 Jul 29 05:13:45 PM PDT 24 43572435 ps
T229 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1314069446 Jul 29 05:13:44 PM PDT 24 Jul 29 05:13:48 PM PDT 24 321616822 ps
T2897 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1294982619 Jul 29 05:13:18 PM PDT 24 Jul 29 05:13:19 PM PDT 24 52038483 ps
T2898 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3551273916 Jul 29 05:13:40 PM PDT 24 Jul 29 05:13:42 PM PDT 24 116395148 ps
T2899 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.673199242 Jul 29 05:13:18 PM PDT 24 Jul 29 05:13:21 PM PDT 24 259634897 ps
T2900 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.795086435 Jul 29 05:14:00 PM PDT 24 Jul 29 05:14:00 PM PDT 24 46958100 ps
T2901 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3029223548 Jul 29 05:13:36 PM PDT 24 Jul 29 05:13:37 PM PDT 24 68602832 ps
T2902 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1575527754 Jul 29 05:13:56 PM PDT 24 Jul 29 05:13:57 PM PDT 24 47797691 ps
T2903 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3793126266 Jul 29 05:13:44 PM PDT 24 Jul 29 05:13:46 PM PDT 24 92099564 ps
T2904 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1417203614 Jul 29 05:13:58 PM PDT 24 Jul 29 05:13:59 PM PDT 24 128677741 ps
T2905 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.304766546 Jul 29 05:13:53 PM PDT 24 Jul 29 05:13:55 PM PDT 24 74979940 ps
T2906 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.438486470 Jul 29 05:13:34 PM PDT 24 Jul 29 05:13:36 PM PDT 24 115294219 ps
T2907 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4242630078 Jul 29 05:13:59 PM PDT 24 Jul 29 05:14:00 PM PDT 24 79623643 ps
T2908 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2426761641 Jul 29 05:13:54 PM PDT 24 Jul 29 05:13:56 PM PDT 24 88213521 ps
T2909 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1343278703 Jul 29 05:13:21 PM PDT 24 Jul 29 05:13:24 PM PDT 24 193987051 ps
T252 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1000732472 Jul 29 05:13:36 PM PDT 24 Jul 29 05:13:37 PM PDT 24 95500173 ps
T2910 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1640466602 Jul 29 05:13:59 PM PDT 24 Jul 29 05:14:00 PM PDT 24 52975723 ps
T2911 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4169808462 Jul 29 05:14:01 PM PDT 24 Jul 29 05:14:02 PM PDT 24 53804432 ps
T289 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.408273745 Jul 29 05:13:40 PM PDT 24 Jul 29 05:13:45 PM PDT 24 2042649013 ps
T2912 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3544584892 Jul 29 05:13:22 PM PDT 24 Jul 29 05:13:23 PM PDT 24 90316875 ps
T2913 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2957239399 Jul 29 05:13:40 PM PDT 24 Jul 29 05:13:42 PM PDT 24 61505217 ps
T2914 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.48296234 Jul 29 05:13:35 PM PDT 24 Jul 29 05:13:38 PM PDT 24 133116531 ps
T2915 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1407043976 Jul 29 05:13:52 PM PDT 24 Jul 29 05:13:56 PM PDT 24 758208977 ps
T2916 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1218558317 Jul 29 05:14:13 PM PDT 24 Jul 29 05:14:14 PM PDT 24 50904299 ps
T2917 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3393015360 Jul 29 05:13:24 PM PDT 24 Jul 29 05:13:25 PM PDT 24 95060893 ps
T2918 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.580220780 Jul 29 05:13:28 PM PDT 24 Jul 29 05:13:29 PM PDT 24 42027591 ps
T2919 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1588727751 Jul 29 05:13:56 PM PDT 24 Jul 29 05:13:57 PM PDT 24 108277181 ps
T2920 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1315190470 Jul 29 05:13:56 PM PDT 24 Jul 29 05:13:57 PM PDT 24 59347074 ps
T253 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1237887290 Jul 29 05:13:18 PM PDT 24 Jul 29 05:13:22 PM PDT 24 319062147 ps
T2921 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1812736733 Jul 29 05:13:44 PM PDT 24 Jul 29 05:13:45 PM PDT 24 43476679 ps
T2922 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3936420976 Jul 29 05:13:32 PM PDT 24 Jul 29 05:13:34 PM PDT 24 143755598 ps
T2923 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4271310329 Jul 29 05:13:39 PM PDT 24 Jul 29 05:13:40 PM PDT 24 97362214 ps
T290 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1668915564 Jul 29 05:13:44 PM PDT 24 Jul 29 05:13:49 PM PDT 24 876866055 ps
T291 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3650345681 Jul 29 05:13:51 PM PDT 24 Jul 29 05:13:56 PM PDT 24 937552264 ps
T2924 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3784314207 Jul 29 05:13:59 PM PDT 24 Jul 29 05:14:00 PM PDT 24 37241029 ps
T2925 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3519953203 Jul 29 05:13:52 PM PDT 24 Jul 29 05:13:53 PM PDT 24 61940003 ps
T2926 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.277128423 Jul 29 05:13:35 PM PDT 24 Jul 29 05:13:39 PM PDT 24 275234275 ps
T2927 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1379313990 Jul 29 05:13:20 PM PDT 24 Jul 29 05:13:20 PM PDT 24 50668563 ps
T2928 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3248393222 Jul 29 05:13:51 PM PDT 24 Jul 29 05:13:53 PM PDT 24 169230077 ps
T2929 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.260274522 Jul 29 05:13:57 PM PDT 24 Jul 29 05:13:58 PM PDT 24 42179081 ps
T2930 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.744589582 Jul 29 05:13:26 PM PDT 24 Jul 29 05:13:27 PM PDT 24 121899435 ps
T2931 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3666969397 Jul 29 05:13:45 PM PDT 24 Jul 29 05:13:46 PM PDT 24 159509080 ps
T2932 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3948750210 Jul 29 05:13:51 PM PDT 24 Jul 29 05:13:53 PM PDT 24 220274095 ps
T2933 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2361155471 Jul 29 05:13:15 PM PDT 24 Jul 29 05:13:18 PM PDT 24 917191051 ps
T2934 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1465696729 Jul 29 05:13:51 PM PDT 24 Jul 29 05:13:52 PM PDT 24 78045236 ps
T2935 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.272153809 Jul 29 05:13:29 PM PDT 24 Jul 29 05:13:30 PM PDT 24 66158252 ps
T2936 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.516570635 Jul 29 05:13:58 PM PDT 24 Jul 29 05:13:59 PM PDT 24 58107167 ps
T2937 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3748449283 Jul 29 05:13:34 PM PDT 24 Jul 29 05:13:35 PM PDT 24 101535513 ps
T2938 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3638408719 Jul 29 05:14:34 PM PDT 24 Jul 29 05:14:35 PM PDT 24 56360200 ps
T2939 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.607973090 Jul 29 05:13:52 PM PDT 24 Jul 29 05:13:53 PM PDT 24 96922442 ps
T2940 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3445396744 Jul 29 05:13:35 PM PDT 24 Jul 29 05:13:40 PM PDT 24 725703028 ps
T2941 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.4168897178 Jul 29 05:13:50 PM PDT 24 Jul 29 05:13:52 PM PDT 24 136475483 ps
T2942 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3186471797 Jul 29 05:14:02 PM PDT 24 Jul 29 05:14:03 PM PDT 24 41380117 ps
T2943 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2906614770 Jul 29 05:13:59 PM PDT 24 Jul 29 05:14:00 PM PDT 24 46052937 ps
T2944 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3080953403 Jul 29 05:13:33 PM PDT 24 Jul 29 05:13:36 PM PDT 24 424751809 ps
T2945 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3164940532 Jul 29 05:13:39 PM PDT 24 Jul 29 05:13:40 PM PDT 24 78895718 ps
T2946 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1000621606 Jul 29 05:13:33 PM PDT 24 Jul 29 05:13:35 PM PDT 24 149844276 ps
T2947 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3867782096 Jul 29 05:13:44 PM PDT 24 Jul 29 05:13:45 PM PDT 24 82782092 ps
T2948 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1793138293 Jul 29 05:13:56 PM PDT 24 Jul 29 05:13:57 PM PDT 24 50818117 ps
T2949 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2615508472 Jul 29 05:13:47 PM PDT 24 Jul 29 05:13:48 PM PDT 24 72391809 ps
T2950 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.278633085 Jul 29 05:13:40 PM PDT 24 Jul 29 05:13:41 PM PDT 24 210659040 ps
T2951 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2317731535 Jul 29 05:13:21 PM PDT 24 Jul 29 05:13:22 PM PDT 24 49956124 ps
T2952 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4278874481 Jul 29 05:13:41 PM PDT 24 Jul 29 05:13:42 PM PDT 24 40256918 ps
T2953 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1647313375 Jul 29 05:13:29 PM PDT 24 Jul 29 05:13:38 PM PDT 24 1332391118 ps
T2954 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3511173463 Jul 29 05:13:28 PM PDT 24 Jul 29 05:13:30 PM PDT 24 220212934 ps
T2955 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4044543614 Jul 29 05:13:47 PM PDT 24 Jul 29 05:13:53 PM PDT 24 1601596788 ps
T2956 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.441175698 Jul 29 05:13:21 PM PDT 24 Jul 29 05:13:23 PM PDT 24 211697256 ps
T2957 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.134563623 Jul 29 05:13:45 PM PDT 24 Jul 29 05:13:49 PM PDT 24 304798419 ps
T2958 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3070211226 Jul 29 05:13:34 PM PDT 24 Jul 29 05:13:36 PM PDT 24 214622977 ps
T2959 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3431241253 Jul 29 05:13:46 PM PDT 24 Jul 29 05:13:48 PM PDT 24 72160244 ps
T2960 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1957921440 Jul 29 05:13:58 PM PDT 24 Jul 29 05:13:59 PM PDT 24 42338532 ps
T2961 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3733256402 Jul 29 05:13:33 PM PDT 24 Jul 29 05:13:34 PM PDT 24 51941030 ps
T2962 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2945245158 Jul 29 05:13:52 PM PDT 24 Jul 29 05:13:58 PM PDT 24 1010468858 ps
T2963 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.839562893 Jul 29 05:13:38 PM PDT 24 Jul 29 05:13:40 PM PDT 24 246192035 ps
T2964 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.863451492 Jul 29 05:13:46 PM PDT 24 Jul 29 05:13:51 PM PDT 24 1429293581 ps
T2965 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.156642494 Jul 29 05:13:53 PM PDT 24 Jul 29 05:13:55 PM PDT 24 373627167 ps
T2966 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3078547879 Jul 29 05:13:39 PM PDT 24 Jul 29 05:13:42 PM PDT 24 115008135 ps
T2967 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1739240833 Jul 29 05:13:41 PM PDT 24 Jul 29 05:13:42 PM PDT 24 95916984 ps
T2968 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.209397123 Jul 29 05:13:19 PM PDT 24 Jul 29 05:13:22 PM PDT 24 515419399 ps
T2969 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4172114155 Jul 29 05:13:56 PM PDT 24 Jul 29 05:13:57 PM PDT 24 40265277 ps
T2970 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1062089631 Jul 29 05:13:29 PM PDT 24 Jul 29 05:13:31 PM PDT 24 249877782 ps
T2971 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3711724831 Jul 29 05:13:32 PM PDT 24 Jul 29 05:13:34 PM PDT 24 86027384 ps
T2972 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3764465842 Jul 29 05:13:19 PM PDT 24 Jul 29 05:13:23 PM PDT 24 317650531 ps
T2973 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.492388362 Jul 29 05:13:28 PM PDT 24 Jul 29 05:13:32 PM PDT 24 644366429 ps
T2974 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3072895060 Jul 29 05:13:34 PM PDT 24 Jul 29 05:13:39 PM PDT 24 715499471 ps
T2975 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1869047718 Jul 29 05:13:34 PM PDT 24 Jul 29 05:13:35 PM PDT 24 83355652 ps
T2976 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2691029662 Jul 29 05:13:23 PM PDT 24 Jul 29 05:13:24 PM PDT 24 106116827 ps
T2977 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.119645392 Jul 29 05:13:34 PM PDT 24 Jul 29 05:13:35 PM PDT 24 41874978 ps

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.812116327
Short name T2
Test name
Test status
Simulation time 7202788205 ps
CPU time 19.88 seconds
Started Jul 29 06:14:26 PM PDT 24
Finished Jul 29 06:14:46 PM PDT 24
Peak memory 220560 kb
Host smart-024078f5-f137-4cbc-87a5-f3003aecd348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81211
6327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.812116327
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.506172089
Short name T7
Test name
Test status
Simulation time 23399294015 ps
CPU time 27.18 seconds
Started Jul 29 06:13:44 PM PDT 24
Finished Jul 29 06:14:12 PM PDT 24
Peak memory 207396 kb
Host smart-1099cbd0-963d-4bfe-99bd-550081587f08
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506172089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_ao
n_wake_resume.506172089
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.682197251
Short name T205
Test name
Test status
Simulation time 54852676 ps
CPU time 0.75 seconds
Started Jul 29 05:13:58 PM PDT 24
Finished Jul 29 05:13:59 PM PDT 24
Peak memory 206496 kb
Host smart-22d38d83-96c4-41f4-81e3-6b897d2c0180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=682197251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.682197251
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.3963711630
Short name T17
Test name
Test status
Simulation time 7642715818 ps
CPU time 74.05 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:20:02 PM PDT 24
Peak memory 216912 kb
Host smart-b5529848-0a0a-43bc-9d69-a3677f41f5ef
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3963711630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.3963711630
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.407861878
Short name T46
Test name
Test status
Simulation time 12458530112 ps
CPU time 370.07 seconds
Started Jul 29 06:11:20 PM PDT 24
Finished Jul 29 06:17:31 PM PDT 24
Peak memory 215632 kb
Host smart-6c1f63c8-6772-433a-95fa-cc3cb702720d
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407861878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.407861878
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.790696516
Short name T195
Test name
Test status
Simulation time 1460959287 ps
CPU time 5.05 seconds
Started Jul 29 05:13:52 PM PDT 24
Finished Jul 29 05:13:57 PM PDT 24
Peak memory 206812 kb
Host smart-8ac1ede1-2df8-4ca9-87d4-4cc7cbe40a45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=790696516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.790696516
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1604768050
Short name T89
Test name
Test status
Simulation time 337958060 ps
CPU time 1.23 seconds
Started Jul 29 06:19:11 PM PDT 24
Finished Jul 29 06:19:13 PM PDT 24
Peak memory 207020 kb
Host smart-8523a631-88c2-445c-8bad-af24204dfdce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16047
68050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1604768050
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.772828132
Short name T115
Test name
Test status
Simulation time 194967022 ps
CPU time 0.97 seconds
Started Jul 29 06:15:57 PM PDT 24
Finished Jul 29 06:15:58 PM PDT 24
Peak memory 206996 kb
Host smart-ae2faa88-df3e-4fe0-9803-f65219dbe5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77282
8132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.772828132
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.4101369273
Short name T21
Test name
Test status
Simulation time 5014506096 ps
CPU time 61.9 seconds
Started Jul 29 06:13:21 PM PDT 24
Finished Jul 29 06:14:23 PM PDT 24
Peak memory 207368 kb
Host smart-1a48341d-f704-4b86-834c-103489f0c48d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4101369273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.4101369273
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1447588912
Short name T146
Test name
Test status
Simulation time 215267332 ps
CPU time 0.97 seconds
Started Jul 29 06:10:17 PM PDT 24
Finished Jul 29 06:10:18 PM PDT 24
Peak memory 207144 kb
Host smart-371d8d43-cd8c-422c-a828-2db508341025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14475
88912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1447588912
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3781620382
Short name T191
Test name
Test status
Simulation time 1069174100 ps
CPU time 1.9 seconds
Started Jul 29 06:11:19 PM PDT 24
Finished Jul 29 06:11:21 PM PDT 24
Peak memory 224152 kb
Host smart-e3c95142-5431-4ddd-b526-82f2f8397c27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3781620382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3781620382
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1147382059
Short name T14
Test name
Test status
Simulation time 3632421114 ps
CPU time 5.38 seconds
Started Jul 29 06:19:25 PM PDT 24
Finished Jul 29 06:19:30 PM PDT 24
Peak memory 207332 kb
Host smart-5adaadee-a381-4c8d-86f6-0cbf6670184d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147382059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_disconnect.1147382059
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2408963931
Short name T280
Test name
Test status
Simulation time 78545527 ps
CPU time 0.79 seconds
Started Jul 29 05:13:52 PM PDT 24
Finished Jul 29 05:13:53 PM PDT 24
Peak memory 206408 kb
Host smart-0e7b764a-a775-48d6-92b3-420a05dfd537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2408963931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2408963931
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1189372141
Short name T22
Test name
Test status
Simulation time 45964310 ps
CPU time 0.72 seconds
Started Jul 29 06:15:25 PM PDT 24
Finished Jul 29 06:15:26 PM PDT 24
Peak memory 207108 kb
Host smart-1eff3083-8c79-4a0c-bb69-5b8a5616349a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11893
72141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1189372141
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2792206426
Short name T247
Test name
Test status
Simulation time 2001279706 ps
CPU time 10.24 seconds
Started Jul 29 05:13:20 PM PDT 24
Finished Jul 29 05:13:30 PM PDT 24
Peak memory 206776 kb
Host smart-8dbc2085-daa8-4dca-89d1-595abeddd026
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2792206426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2792206426
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.3431845150
Short name T91
Test name
Test status
Simulation time 523632606 ps
CPU time 1.48 seconds
Started Jul 29 06:13:10 PM PDT 24
Finished Jul 29 06:13:12 PM PDT 24
Peak memory 207024 kb
Host smart-2ef837cb-3b61-44d3-9841-a03a332ef3b6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3431845150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.3431845150
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.4227292650
Short name T95
Test name
Test status
Simulation time 18306679308 ps
CPU time 40.12 seconds
Started Jul 29 06:18:33 PM PDT 24
Finished Jul 29 06:19:14 PM PDT 24
Peak memory 207392 kb
Host smart-b2c4cb98-47a0-4399-bd9f-f82192274cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42272
92650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.4227292650
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.643606960
Short name T43
Test name
Test status
Simulation time 148551439 ps
CPU time 0.84 seconds
Started Jul 29 06:10:07 PM PDT 24
Finished Jul 29 06:10:08 PM PDT 24
Peak memory 207052 kb
Host smart-4fc88c4c-916c-4277-acc3-0714889bfa6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64360
6960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.643606960
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2766687735
Short name T85
Test name
Test status
Simulation time 310337526 ps
CPU time 1.13 seconds
Started Jul 29 06:10:30 PM PDT 24
Finished Jul 29 06:10:32 PM PDT 24
Peak memory 207048 kb
Host smart-b5751e41-be65-413c-b469-6f9941f587ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27666
87735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.2766687735
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1278732059
Short name T51
Test name
Test status
Simulation time 12978886909 ps
CPU time 353.75 seconds
Started Jul 29 06:11:40 PM PDT 24
Finished Jul 29 06:17:34 PM PDT 24
Peak memory 215804 kb
Host smart-ace2cf7d-e389-441e-a5d7-ec9770375453
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278732059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.1278732059
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.1476122202
Short name T49
Test name
Test status
Simulation time 20160766424 ps
CPU time 25.6 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:10:54 PM PDT 24
Peak memory 207228 kb
Host smart-c6297815-5ee3-4042-beac-41432a8c2ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14761
22202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.1476122202
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.121141690
Short name T223
Test name
Test status
Simulation time 328447605 ps
CPU time 3.22 seconds
Started Jul 29 05:13:46 PM PDT 24
Finished Jul 29 05:13:49 PM PDT 24
Peak memory 219780 kb
Host smart-63be886b-9757-4ace-82fa-f93396da67cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=121141690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.121141690
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.3000149879
Short name T86
Test name
Test status
Simulation time 213480712 ps
CPU time 1.06 seconds
Started Jul 29 06:14:02 PM PDT 24
Finished Jul 29 06:14:04 PM PDT 24
Peak memory 207132 kb
Host smart-f59c0468-4a2f-4bf9-9e6e-c82bfbf69f5a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3000149879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.3000149879
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_device_address.434608506
Short name T181
Test name
Test status
Simulation time 19310976069 ps
CPU time 40 seconds
Started Jul 29 06:15:03 PM PDT 24
Finished Jul 29 06:15:43 PM PDT 24
Peak memory 207392 kb
Host smart-4654ef77-fa04-4c4d-8b60-70762e346a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43460
8506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.434608506
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.311632079
Short name T382
Test name
Test status
Simulation time 159449933 ps
CPU time 0.83 seconds
Started Jul 29 06:14:47 PM PDT 24
Finished Jul 29 06:14:48 PM PDT 24
Peak memory 206824 kb
Host smart-8e415858-ddb1-4aa1-8bc7-65f0c652fc4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31163
2079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.311632079
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.214134351
Short name T58
Test name
Test status
Simulation time 453577016 ps
CPU time 1.51 seconds
Started Jul 29 06:11:04 PM PDT 24
Finished Jul 29 06:11:06 PM PDT 24
Peak memory 206620 kb
Host smart-967f3550-31c2-4e84-94ca-31155de31aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21413
4351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.214134351
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.4198290118
Short name T293
Test name
Test status
Simulation time 142863147 ps
CPU time 0.86 seconds
Started Jul 29 06:13:15 PM PDT 24
Finished Jul 29 06:13:16 PM PDT 24
Peak memory 207056 kb
Host smart-4b5cbaf4-1f13-4915-a079-db1f9ce7fd8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41982
90118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.4198290118
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2524307474
Short name T207
Test name
Test status
Simulation time 51290612 ps
CPU time 0.75 seconds
Started Jul 29 05:13:56 PM PDT 24
Finished Jul 29 05:13:57 PM PDT 24
Peak memory 206408 kb
Host smart-548fce2a-5c84-49fa-8b09-efea403aba9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2524307474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2524307474
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3943540358
Short name T264
Test name
Test status
Simulation time 421402683 ps
CPU time 2.34 seconds
Started Jul 29 05:13:44 PM PDT 24
Finished Jul 29 05:13:47 PM PDT 24
Peak memory 206756 kb
Host smart-b11a0f1b-ad18-46b3-be25-194507619adc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3943540358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3943540358
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3972582930
Short name T675
Test name
Test status
Simulation time 13306869190 ps
CPU time 16.48 seconds
Started Jul 29 06:15:03 PM PDT 24
Finished Jul 29 06:15:20 PM PDT 24
Peak memory 207436 kb
Host smart-ab033988-9a9e-4536-9711-a3b393ececce
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972582930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3972582930
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.4101545672
Short name T76
Test name
Test status
Simulation time 473414685 ps
CPU time 1.43 seconds
Started Jul 29 06:10:07 PM PDT 24
Finished Jul 29 06:10:09 PM PDT 24
Peak memory 207068 kb
Host smart-5111c024-1d30-495c-9371-dbfa215d4347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41015
45672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.4101545672
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.3002015608
Short name T48
Test name
Test status
Simulation time 58469447 ps
CPU time 0.69 seconds
Started Jul 29 06:13:08 PM PDT 24
Finished Jul 29 06:13:09 PM PDT 24
Peak memory 207008 kb
Host smart-0984587e-db9a-44cf-8620-265d922ff4bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3002015608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.3002015608
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.606957772
Short name T23
Test name
Test status
Simulation time 4717236934 ps
CPU time 41.01 seconds
Started Jul 29 06:14:05 PM PDT 24
Finished Jul 29 06:14:47 PM PDT 24
Peak memory 217024 kb
Host smart-99ccb0fe-99bd-488c-817c-433897fd974c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=606957772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.606957772
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_device_address.3038228580
Short name T92
Test name
Test status
Simulation time 10665331828 ps
CPU time 22.38 seconds
Started Jul 29 06:18:19 PM PDT 24
Finished Jul 29 06:18:42 PM PDT 24
Peak memory 207260 kb
Host smart-eff7191a-e011-461f-ab20-d3164e70421a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30382
28580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.3038228580
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2410980146
Short name T2873
Test name
Test status
Simulation time 42394753 ps
CPU time 0.74 seconds
Started Jul 29 05:13:57 PM PDT 24
Finished Jul 29 05:13:58 PM PDT 24
Peak memory 206460 kb
Host smart-aaf41438-ed70-4b62-81c2-846e744edf86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2410980146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2410980146
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.466426611
Short name T283
Test name
Test status
Simulation time 240798060 ps
CPU time 0.97 seconds
Started Jul 29 06:14:13 PM PDT 24
Finished Jul 29 06:14:15 PM PDT 24
Peak memory 206996 kb
Host smart-882330f3-b87e-46c5-9580-9895c8a452b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46642
6611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.466426611
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.191666824
Short name T302
Test name
Test status
Simulation time 89257115368 ps
CPU time 151.5 seconds
Started Jul 29 06:10:52 PM PDT 24
Finished Jul 29 06:13:23 PM PDT 24
Peak memory 207384 kb
Host smart-7f5f0c13-5b6b-4305-99e4-538c5188d447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19166
6824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.191666824
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.190792873
Short name T152
Test name
Test status
Simulation time 5138779238 ps
CPU time 42.64 seconds
Started Jul 29 06:12:39 PM PDT 24
Finished Jul 29 06:13:22 PM PDT 24
Peak memory 217044 kb
Host smart-a8a2c1bc-72f5-4cfc-a111-1124b84dac69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19079
2873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.190792873
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3316334158
Short name T260
Test name
Test status
Simulation time 279575481 ps
CPU time 1.6 seconds
Started Jul 29 05:13:17 PM PDT 24
Finished Jul 29 05:13:19 PM PDT 24
Peak memory 206732 kb
Host smart-3d16c563-b201-4ab0-a25c-261a644d844d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3316334158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3316334158
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.4010278284
Short name T69
Test name
Test status
Simulation time 195421934 ps
CPU time 0.94 seconds
Started Jul 29 06:10:05 PM PDT 24
Finished Jul 29 06:10:06 PM PDT 24
Peak memory 207080 kb
Host smart-a64e1200-fed1-42d0-b0d2-a252bc8744c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40102
78284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.4010278284
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.3718837755
Short name T60
Test name
Test status
Simulation time 267554388 ps
CPU time 1.11 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:10:29 PM PDT 24
Peak memory 207052 kb
Host smart-ff21e8f5-20a5-4798-8370-52fb94e56e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37188
37755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.3718837755
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.673199242
Short name T2899
Test name
Test status
Simulation time 259634897 ps
CPU time 3.08 seconds
Started Jul 29 05:13:18 PM PDT 24
Finished Jul 29 05:13:21 PM PDT 24
Peak memory 222572 kb
Host smart-7723c1d4-a59f-4013-a527-eeda56034dc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=673199242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.673199242
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/40.usbdev_device_address.2711866991
Short name T298
Test name
Test status
Simulation time 14701616694 ps
CPU time 34.2 seconds
Started Jul 29 06:18:00 PM PDT 24
Finished Jul 29 06:18:34 PM PDT 24
Peak memory 207356 kb
Host smart-1b0f1980-153b-4efc-814c-f85729cf7434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27118
66991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.2711866991
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1826522726
Short name T530
Test name
Test status
Simulation time 132905108 ps
CPU time 0.81 seconds
Started Jul 29 06:10:45 PM PDT 24
Finished Jul 29 06:10:46 PM PDT 24
Peak memory 207032 kb
Host smart-9eed4cd1-d183-408a-a835-3ef171b83e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18265
22726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1826522726
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.209397123
Short name T2968
Test name
Test status
Simulation time 515419399 ps
CPU time 2.61 seconds
Started Jul 29 05:13:19 PM PDT 24
Finished Jul 29 05:13:22 PM PDT 24
Peak memory 206748 kb
Host smart-23cd8267-a1f0-4aa5-a222-2a693d34965c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=209397123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.209397123
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.502968234
Short name T308
Test name
Test status
Simulation time 5122393176 ps
CPU time 39.01 seconds
Started Jul 29 06:10:07 PM PDT 24
Finished Jul 29 06:10:46 PM PDT 24
Peak memory 207556 kb
Host smart-021ef3ab-9c2a-4dc4-b9db-e5393bfb7e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50296
8234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.502968234
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.3610715460
Short name T300
Test name
Test status
Simulation time 103037219121 ps
CPU time 155.46 seconds
Started Jul 29 06:10:08 PM PDT 24
Finished Jul 29 06:12:44 PM PDT 24
Peak memory 207392 kb
Host smart-97ac0adc-830b-47d3-a05c-61b1edf56961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610715460 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.3610715460
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1427764539
Short name T612
Test name
Test status
Simulation time 204733848 ps
CPU time 0.89 seconds
Started Jul 29 06:10:29 PM PDT 24
Finished Jul 29 06:10:30 PM PDT 24
Peak memory 207036 kb
Host smart-279a4a90-5e2c-47d2-9047-61506adf4acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14277
64539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1427764539
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3850245523
Short name T390
Test name
Test status
Simulation time 144129987 ps
CPU time 0.83 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:10:29 PM PDT 24
Peak memory 207108 kb
Host smart-5af03e0e-7e07-48ac-b427-a4a73e32ff9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38502
45523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3850245523
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.2042551644
Short name T309
Test name
Test status
Simulation time 87202150547 ps
CPU time 141.42 seconds
Started Jul 29 06:10:33 PM PDT 24
Finished Jul 29 06:12:55 PM PDT 24
Peak memory 207428 kb
Host smart-a8c8b3d0-4115-4ac6-8ba7-06a63fce6105
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2042551644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.2042551644
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.861646123
Short name T24
Test name
Test status
Simulation time 184522956 ps
CPU time 0.93 seconds
Started Jul 29 06:13:29 PM PDT 24
Finished Jul 29 06:13:30 PM PDT 24
Peak memory 207040 kb
Host smart-4a0abb74-930b-48f5-8e47-3ddf83750e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86164
6123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.861646123
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.399488629
Short name T114
Test name
Test status
Simulation time 151088742 ps
CPU time 0.84 seconds
Started Jul 29 06:13:32 PM PDT 24
Finished Jul 29 06:13:33 PM PDT 24
Peak memory 207108 kb
Host smart-df632d87-2bfe-41ee-8a96-77fa6c6647be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39948
8629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.399488629
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.979486547
Short name T199
Test name
Test status
Simulation time 3889024095 ps
CPU time 5.44 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:17:54 PM PDT 24
Peak memory 207276 kb
Host smart-4137086a-00df-4aa9-a923-ffd49b853143
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979486547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_ao
n_wake_disconnect.979486547
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1371478569
Short name T2014
Test name
Test status
Simulation time 13327852825 ps
CPU time 16.24 seconds
Started Jul 29 06:13:08 PM PDT 24
Finished Jul 29 06:13:25 PM PDT 24
Peak memory 207432 kb
Host smart-1cf08d78-394b-42c9-a1b1-08c0f8dfd502
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371478569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1371478569
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.381976110
Short name T636
Test name
Test status
Simulation time 187044835 ps
CPU time 2.3 seconds
Started Jul 29 06:10:06 PM PDT 24
Finished Jul 29 06:10:09 PM PDT 24
Peak memory 207224 kb
Host smart-29ba75ee-f8c3-4c47-bf6a-7295b6b7a328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38197
6110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.381976110
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.254414303
Short name T1913
Test name
Test status
Simulation time 9666025539 ps
CPU time 64.27 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:11:33 PM PDT 24
Peak memory 218988 kb
Host smart-6bde069e-a229-4b7d-8726-2da6f85d27b9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=254414303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.254414303
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2091748051
Short name T25
Test name
Test status
Simulation time 5421616232 ps
CPU time 58.73 seconds
Started Jul 29 06:13:28 PM PDT 24
Finished Jul 29 06:14:26 PM PDT 24
Peak memory 217232 kb
Host smart-de639ef4-0096-4f8f-be57-ef49406da273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20917
48051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2091748051
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2340996367
Short name T512
Test name
Test status
Simulation time 70864128 ps
CPU time 0.68 seconds
Started Jul 29 06:13:58 PM PDT 24
Finished Jul 29 06:13:59 PM PDT 24
Peak memory 207068 kb
Host smart-6bd6a950-08a6-42e0-ac6a-0324e6cc45c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23409
96367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2340996367
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.4172234952
Short name T112
Test name
Test status
Simulation time 168100810 ps
CPU time 0.82 seconds
Started Jul 29 06:10:46 PM PDT 24
Finished Jul 29 06:10:46 PM PDT 24
Peak memory 207040 kb
Host smart-57c1d86f-220f-4432-b67b-22c7741425be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41722
34952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.4172234952
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.1209874804
Short name T1943
Test name
Test status
Simulation time 204684149 ps
CPU time 0.93 seconds
Started Jul 29 06:10:01 PM PDT 24
Finished Jul 29 06:10:02 PM PDT 24
Peak memory 207256 kb
Host smart-5815c64c-9d03-40b5-8c5e-2cd20515164f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12098
74804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.1209874804
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3245927514
Short name T70
Test name
Test status
Simulation time 4186862013 ps
CPU time 9.87 seconds
Started Jul 29 06:10:08 PM PDT 24
Finished Jul 29 06:10:18 PM PDT 24
Peak memory 207348 kb
Host smart-0de8a04f-5eda-44df-b65f-ebe951f1e41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32459
27514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3245927514
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1173724901
Short name T71
Test name
Test status
Simulation time 163850514 ps
CPU time 0.82 seconds
Started Jul 29 06:10:15 PM PDT 24
Finished Jul 29 06:10:16 PM PDT 24
Peak memory 207068 kb
Host smart-6a16ef72-29a2-4029-bbd7-ca42f46ba32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11737
24901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1173724901
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.2061020313
Short name T80
Test name
Test status
Simulation time 173542344 ps
CPU time 0.88 seconds
Started Jul 29 06:10:31 PM PDT 24
Finished Jul 29 06:10:32 PM PDT 24
Peak memory 207104 kb
Host smart-b3ab5c9f-ea28-4c4a-b83b-e79f16c862be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20610
20313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2061020313
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.2678837747
Short name T57
Test name
Test status
Simulation time 173031331 ps
CPU time 0.91 seconds
Started Jul 29 06:11:07 PM PDT 24
Finished Jul 29 06:11:09 PM PDT 24
Peak memory 207116 kb
Host smart-1566842a-673b-4167-9cfa-4c77f48defaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26788
37747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2678837747
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.539004047
Short name T83
Test name
Test status
Simulation time 20996810512 ps
CPU time 535.3 seconds
Started Jul 29 06:10:30 PM PDT 24
Finished Jul 29 06:19:26 PM PDT 24
Peak memory 215584 kb
Host smart-bde014af-259e-4028-989e-883a024f4363
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539004047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.539004047
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1174538540
Short name T135
Test name
Test status
Simulation time 250080518 ps
CPU time 1.08 seconds
Started Jul 29 06:10:42 PM PDT 24
Finished Jul 29 06:10:43 PM PDT 24
Peak memory 207104 kb
Host smart-7257d7b9-046f-4e97-a890-efdeea4b6654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11745
38540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1174538540
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1532648310
Short name T263
Test name
Test status
Simulation time 17784732831 ps
CPU time 166.14 seconds
Started Jul 29 06:10:46 PM PDT 24
Finished Jul 29 06:13:32 PM PDT 24
Peak memory 223732 kb
Host smart-d975caae-1345-4422-96f7-e7b99659e15c
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532648310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.1532648310
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1389064005
Short name T2774
Test name
Test status
Simulation time 205157034 ps
CPU time 0.93 seconds
Started Jul 29 06:13:00 PM PDT 24
Finished Jul 29 06:13:01 PM PDT 24
Peak memory 207120 kb
Host smart-5e7c1157-6db9-4bf7-9cc3-6e918158fa6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13890
64005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1389064005
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.4049503194
Short name T150
Test name
Test status
Simulation time 168350553 ps
CPU time 0.85 seconds
Started Jul 29 06:13:20 PM PDT 24
Finished Jul 29 06:13:21 PM PDT 24
Peak memory 207116 kb
Host smart-cc9dca41-891d-44c8-9fe7-e41e7479cbe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40495
03194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.4049503194
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1949270029
Short name T140
Test name
Test status
Simulation time 189833383 ps
CPU time 0.9 seconds
Started Jul 29 06:13:57 PM PDT 24
Finished Jul 29 06:13:58 PM PDT 24
Peak memory 207124 kb
Host smart-427100cd-4059-4e40-8e23-6d4156a802d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19492
70029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1949270029
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.521275015
Short name T127
Test name
Test status
Simulation time 190730918 ps
CPU time 0.92 seconds
Started Jul 29 06:14:11 PM PDT 24
Finished Jul 29 06:14:12 PM PDT 24
Peak memory 207188 kb
Host smart-3307179f-2f67-4bbf-a716-272930cf8357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52127
5015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.521275015
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.66456049
Short name T133
Test name
Test status
Simulation time 216384660 ps
CPU time 0.95 seconds
Started Jul 29 06:14:22 PM PDT 24
Finished Jul 29 06:14:23 PM PDT 24
Peak memory 207124 kb
Host smart-801b7bdf-cda7-4ad7-a500-df568e8b4e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66456
049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.66456049
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2313699911
Short name T125
Test name
Test status
Simulation time 255688702 ps
CPU time 1.01 seconds
Started Jul 29 06:10:54 PM PDT 24
Finished Jul 29 06:10:55 PM PDT 24
Peak memory 206868 kb
Host smart-05201c7a-28c5-4585-99ab-c6062f6a36e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23136
99911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2313699911
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1090994500
Short name T144
Test name
Test status
Simulation time 171968661 ps
CPU time 0.92 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:15:11 PM PDT 24
Peak memory 207108 kb
Host smart-0d791310-5057-433c-95b9-4d2252ecca8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10909
94500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1090994500
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1805882333
Short name T129
Test name
Test status
Simulation time 199718827 ps
CPU time 1.01 seconds
Started Jul 29 06:15:11 PM PDT 24
Finished Jul 29 06:15:12 PM PDT 24
Peak memory 207080 kb
Host smart-df4ecfe3-dbff-4fa0-ad92-28e312de7def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18058
82333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1805882333
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2226306172
Short name T145
Test name
Test status
Simulation time 277146571 ps
CPU time 1.08 seconds
Started Jul 29 06:17:28 PM PDT 24
Finished Jul 29 06:17:29 PM PDT 24
Peak memory 207120 kb
Host smart-32da9dbf-9dd5-446d-a1e5-37ed8df08aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22263
06172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2226306172
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.785550087
Short name T122
Test name
Test status
Simulation time 210394626 ps
CPU time 0.96 seconds
Started Jul 29 06:18:53 PM PDT 24
Finished Jul 29 06:18:54 PM PDT 24
Peak memory 207088 kb
Host smart-ac80f9e6-3a96-44b3-8802-eb775f4ea492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78555
0087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.785550087
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1074313210
Short name T2864
Test name
Test status
Simulation time 77734006 ps
CPU time 1.95 seconds
Started Jul 29 05:13:19 PM PDT 24
Finished Jul 29 05:13:21 PM PDT 24
Peak memory 206832 kb
Host smart-87bbb6ed-b100-4a78-a189-e077e6d1d36c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1074313210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1074313210
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2760586948
Short name T245
Test name
Test status
Simulation time 2001884022 ps
CPU time 9.81 seconds
Started Jul 29 05:13:25 PM PDT 24
Finished Jul 29 05:13:35 PM PDT 24
Peak memory 206776 kb
Host smart-4215d836-e786-4cc9-9a87-886038b5fa3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2760586948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2760586948
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1379313990
Short name T2927
Test name
Test status
Simulation time 50668563 ps
CPU time 0.75 seconds
Started Jul 29 05:13:20 PM PDT 24
Finished Jul 29 05:13:20 PM PDT 24
Peak memory 206540 kb
Host smart-ded4b583-075e-4527-917c-af553f782b1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1379313990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1379313990
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1808257652
Short name T196
Test name
Test status
Simulation time 82222911 ps
CPU time 1.32 seconds
Started Jul 29 05:13:25 PM PDT 24
Finished Jul 29 05:13:27 PM PDT 24
Peak memory 216828 kb
Host smart-84704867-03f5-4e9c-bb8b-dc3be3acb192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808257652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1808257652
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1294982619
Short name T2897
Test name
Test status
Simulation time 52038483 ps
CPU time 0.85 seconds
Started Jul 29 05:13:18 PM PDT 24
Finished Jul 29 05:13:19 PM PDT 24
Peak memory 206464 kb
Host smart-a757fc96-35d0-4bc2-a54e-195c51c417f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1294982619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1294982619
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2328484510
Short name T2869
Test name
Test status
Simulation time 55367843 ps
CPU time 0.74 seconds
Started Jul 29 05:13:20 PM PDT 24
Finished Jul 29 05:13:21 PM PDT 24
Peak memory 206568 kb
Host smart-5074acdc-074d-4a83-9b5c-5d0d83efd0cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2328484510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2328484510
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2078110911
Short name T249
Test name
Test status
Simulation time 122104270 ps
CPU time 1.49 seconds
Started Jul 29 05:13:25 PM PDT 24
Finished Jul 29 05:13:27 PM PDT 24
Peak memory 206676 kb
Host smart-bda051de-7b49-4690-b4e2-f4bb00034ebc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2078110911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2078110911
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2116792780
Short name T2862
Test name
Test status
Simulation time 744682555 ps
CPU time 4.77 seconds
Started Jul 29 05:13:16 PM PDT 24
Finished Jul 29 05:13:21 PM PDT 24
Peak memory 206760 kb
Host smart-da52a0e9-0295-47af-bd02-a1bc32a15805
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2116792780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2116792780
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1237887290
Short name T253
Test name
Test status
Simulation time 319062147 ps
CPU time 3.31 seconds
Started Jul 29 05:13:18 PM PDT 24
Finished Jul 29 05:13:22 PM PDT 24
Peak memory 206724 kb
Host smart-9fa76885-a0c9-4167-b4c3-d3aef746c0fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1237887290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1237887290
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3566158705
Short name T2888
Test name
Test status
Simulation time 191138888 ps
CPU time 0.97 seconds
Started Jul 29 05:13:23 PM PDT 24
Finished Jul 29 05:13:24 PM PDT 24
Peak memory 206524 kb
Host smart-b23718c1-593b-4104-8b12-a62f21f4bf30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3566158705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3566158705
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1211919384
Short name T2881
Test name
Test status
Simulation time 171550893 ps
CPU time 1.96 seconds
Started Jul 29 05:13:25 PM PDT 24
Finished Jul 29 05:13:27 PM PDT 24
Peak memory 215116 kb
Host smart-d55992f3-e79c-4d60-a12b-ef3a2e1f8e71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211919384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1211919384
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2329519324
Short name T242
Test name
Test status
Simulation time 42835990 ps
CPU time 0.92 seconds
Started Jul 29 05:13:18 PM PDT 24
Finished Jul 29 05:13:19 PM PDT 24
Peak memory 206572 kb
Host smart-887c6783-5447-4dcd-8577-982930153359
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2329519324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2329519324
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2317731535
Short name T2951
Test name
Test status
Simulation time 49956124 ps
CPU time 0.78 seconds
Started Jul 29 05:13:21 PM PDT 24
Finished Jul 29 05:13:22 PM PDT 24
Peak memory 206548 kb
Host smart-fc879583-c7b1-4eef-8931-25157ecd948a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2317731535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2317731535
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.441175698
Short name T2956
Test name
Test status
Simulation time 211697256 ps
CPU time 2.36 seconds
Started Jul 29 05:13:21 PM PDT 24
Finished Jul 29 05:13:23 PM PDT 24
Peak memory 214940 kb
Host smart-25aa5395-60a6-41a2-ae43-d5539cf29e71
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=441175698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.441175698
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2952790033
Short name T2870
Test name
Test status
Simulation time 533561114 ps
CPU time 4.69 seconds
Started Jul 29 05:13:17 PM PDT 24
Finished Jul 29 05:13:22 PM PDT 24
Peak memory 206656 kb
Host smart-af791fa3-de20-49af-9b02-349fe5f04721
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2952790033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2952790033
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3544584892
Short name T2912
Test name
Test status
Simulation time 90316875 ps
CPU time 1.05 seconds
Started Jul 29 05:13:22 PM PDT 24
Finished Jul 29 05:13:23 PM PDT 24
Peak memory 206524 kb
Host smart-b6f3dbba-97c2-48d6-a802-af6f67abf431
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3544584892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3544584892
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3764465842
Short name T2972
Test name
Test status
Simulation time 317650531 ps
CPU time 3.43 seconds
Started Jul 29 05:13:19 PM PDT 24
Finished Jul 29 05:13:23 PM PDT 24
Peak memory 214888 kb
Host smart-f06d981c-4bdb-4b5f-97ef-de2f0a707e47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3764465842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3764465842
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2361155471
Short name T2933
Test name
Test status
Simulation time 917191051 ps
CPU time 3.47 seconds
Started Jul 29 05:13:15 PM PDT 24
Finished Jul 29 05:13:18 PM PDT 24
Peak memory 206728 kb
Host smart-500a427f-7a94-49e1-a4ca-e0c657bc6400
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2361155471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2361155471
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3078547879
Short name T2966
Test name
Test status
Simulation time 115008135 ps
CPU time 2.83 seconds
Started Jul 29 05:13:39 PM PDT 24
Finished Jul 29 05:13:42 PM PDT 24
Peak memory 215076 kb
Host smart-3ec00ec1-6c75-4bf0-828c-ebfbe29acf2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078547879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3078547879
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3052152067
Short name T2893
Test name
Test status
Simulation time 70016630 ps
CPU time 0.93 seconds
Started Jul 29 05:13:39 PM PDT 24
Finished Jul 29 05:13:40 PM PDT 24
Peak memory 206444 kb
Host smart-9bfa1a1d-369e-4a60-bcf9-734e710dd22b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3052152067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3052152067
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3164940532
Short name T2945
Test name
Test status
Simulation time 78895718 ps
CPU time 0.74 seconds
Started Jul 29 05:13:39 PM PDT 24
Finished Jul 29 05:13:40 PM PDT 24
Peak memory 206440 kb
Host smart-26b36681-20d9-4758-b108-c5c05f616b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3164940532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3164940532
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.839562893
Short name T2963
Test name
Test status
Simulation time 246192035 ps
CPU time 1.69 seconds
Started Jul 29 05:13:38 PM PDT 24
Finished Jul 29 05:13:40 PM PDT 24
Peak memory 206780 kb
Host smart-4b4f3690-0f27-43ab-ac46-6d9779dfa121
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=839562893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.839562893
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1739240833
Short name T2967
Test name
Test status
Simulation time 95916984 ps
CPU time 1.82 seconds
Started Jul 29 05:13:41 PM PDT 24
Finished Jul 29 05:13:42 PM PDT 24
Peak memory 206784 kb
Host smart-0af78d9b-245c-4055-b38e-ac8e79bade52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1739240833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1739240833
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2725660218
Short name T286
Test name
Test status
Simulation time 884458391 ps
CPU time 4.84 seconds
Started Jul 29 05:13:39 PM PDT 24
Finished Jul 29 05:13:44 PM PDT 24
Peak memory 206788 kb
Host smart-7702c584-2d95-471f-a5a5-8729243060bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2725660218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2725660218
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.594549904
Short name T231
Test name
Test status
Simulation time 162971781 ps
CPU time 1.77 seconds
Started Jul 29 05:13:44 PM PDT 24
Finished Jul 29 05:13:46 PM PDT 24
Peak memory 219420 kb
Host smart-e7292aae-9c15-4765-bc61-f6bcada7ccb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594549904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde
v_csr_mem_rw_with_rand_reset.594549904
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3867782096
Short name T2947
Test name
Test status
Simulation time 82782092 ps
CPU time 0.94 seconds
Started Jul 29 05:13:44 PM PDT 24
Finished Jul 29 05:13:45 PM PDT 24
Peak memory 206464 kb
Host smart-828c1eb5-8be3-4282-80ac-286877f5ad0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3867782096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3867782096
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3266778465
Short name T2874
Test name
Test status
Simulation time 37873694 ps
CPU time 0.71 seconds
Started Jul 29 05:13:45 PM PDT 24
Finished Jul 29 05:13:46 PM PDT 24
Peak memory 206440 kb
Host smart-1c077141-d28b-4a1d-81e4-1dac6c5bf439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3266778465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3266778465
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.384572387
Short name T257
Test name
Test status
Simulation time 212609366 ps
CPU time 1.65 seconds
Started Jul 29 05:13:47 PM PDT 24
Finished Jul 29 05:13:49 PM PDT 24
Peak memory 206756 kb
Host smart-79e35b6d-650a-47ac-b65c-bdefc3f5e2bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=384572387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.384572387
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1314069446
Short name T229
Test name
Test status
Simulation time 321616822 ps
CPU time 3.35 seconds
Started Jul 29 05:13:44 PM PDT 24
Finished Jul 29 05:13:48 PM PDT 24
Peak memory 223044 kb
Host smart-0bd5225e-cfdb-438e-a230-73551397a6ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1314069446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1314069446
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.863451492
Short name T2964
Test name
Test status
Simulation time 1429293581 ps
CPU time 5.01 seconds
Started Jul 29 05:13:46 PM PDT 24
Finished Jul 29 05:13:51 PM PDT 24
Peak memory 206784 kb
Host smart-9e00aec2-0530-4abd-ae1a-67c7f8268715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=863451492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.863451492
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.881537984
Short name T2878
Test name
Test status
Simulation time 102653632 ps
CPU time 2.3 seconds
Started Jul 29 05:13:43 PM PDT 24
Finished Jul 29 05:13:46 PM PDT 24
Peak memory 214972 kb
Host smart-d95c0104-238f-4f4f-97ae-d87e92aa4076
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881537984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.881537984
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.461508504
Short name T251
Test name
Test status
Simulation time 43572435 ps
CPU time 0.75 seconds
Started Jul 29 05:13:44 PM PDT 24
Finished Jul 29 05:13:45 PM PDT 24
Peak memory 206596 kb
Host smart-7029abd0-1302-471e-83bf-5fee9c5b6565
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=461508504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.461508504
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1364987301
Short name T2894
Test name
Test status
Simulation time 40326062 ps
CPU time 0.74 seconds
Started Jul 29 05:13:44 PM PDT 24
Finished Jul 29 05:13:45 PM PDT 24
Peak memory 206544 kb
Host smart-ff05aa41-9dc3-4b74-8849-82f3d9467c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1364987301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1364987301
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3389129603
Short name T259
Test name
Test status
Simulation time 147945078 ps
CPU time 1.21 seconds
Started Jul 29 05:13:45 PM PDT 24
Finished Jul 29 05:13:47 PM PDT 24
Peak memory 206844 kb
Host smart-fca3d64e-3415-4ca3-9e87-2ac3386f5bfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3389129603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3389129603
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3431241253
Short name T2959
Test name
Test status
Simulation time 72160244 ps
CPU time 1.81 seconds
Started Jul 29 05:13:46 PM PDT 24
Finished Jul 29 05:13:48 PM PDT 24
Peak memory 214932 kb
Host smart-efc4c295-5e40-4df4-bb03-3e676ea0727e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431241253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.3431241253
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2615508472
Short name T2949
Test name
Test status
Simulation time 72391809 ps
CPU time 1.02 seconds
Started Jul 29 05:13:47 PM PDT 24
Finished Jul 29 05:13:48 PM PDT 24
Peak memory 206528 kb
Host smart-92c971c7-59f2-4a51-bf07-2f7c9da8d2fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2615508472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2615508472
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1812736733
Short name T2921
Test name
Test status
Simulation time 43476679 ps
CPU time 0.71 seconds
Started Jul 29 05:13:44 PM PDT 24
Finished Jul 29 05:13:45 PM PDT 24
Peak memory 206508 kb
Host smart-52524141-f174-42b4-a481-4c12a729a2e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1812736733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1812736733
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1864979194
Short name T2891
Test name
Test status
Simulation time 220311903 ps
CPU time 1.77 seconds
Started Jul 29 05:13:42 PM PDT 24
Finished Jul 29 05:13:44 PM PDT 24
Peak memory 206948 kb
Host smart-185616a9-3b28-404e-8855-1bc177fe9987
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1864979194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1864979194
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4137426942
Short name T194
Test name
Test status
Simulation time 103476656 ps
CPU time 1.48 seconds
Started Jul 29 05:13:45 PM PDT 24
Finished Jul 29 05:13:46 PM PDT 24
Peak memory 206832 kb
Host smart-7855d996-a2a1-4ac6-8892-af7022aad5e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4137426942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4137426942
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4044543614
Short name T2955
Test name
Test status
Simulation time 1601596788 ps
CPU time 5.79 seconds
Started Jul 29 05:13:47 PM PDT 24
Finished Jul 29 05:13:53 PM PDT 24
Peak memory 206752 kb
Host smart-0278dd26-f76e-4c58-8f58-8747401e4969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4044543614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.4044543614
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3666969397
Short name T2931
Test name
Test status
Simulation time 159509080 ps
CPU time 1.22 seconds
Started Jul 29 05:13:45 PM PDT 24
Finished Jul 29 05:13:46 PM PDT 24
Peak memory 222832 kb
Host smart-ba620f52-b83f-4bed-bfd2-2db42e7189d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666969397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3666969397
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1584214628
Short name T2875
Test name
Test status
Simulation time 67779408 ps
CPU time 0.93 seconds
Started Jul 29 05:13:45 PM PDT 24
Finished Jul 29 05:13:46 PM PDT 24
Peak memory 206480 kb
Host smart-803427e7-917e-42c0-a3b3-b09fa321a5c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1584214628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1584214628
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2765259802
Short name T2879
Test name
Test status
Simulation time 55075913 ps
CPU time 0.7 seconds
Started Jul 29 05:13:47 PM PDT 24
Finished Jul 29 05:13:47 PM PDT 24
Peak memory 206440 kb
Host smart-ad95e3c5-7182-456d-ac3a-818f096ed470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2765259802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.2765259802
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4063069861
Short name T258
Test name
Test status
Simulation time 148962029 ps
CPU time 1.57 seconds
Started Jul 29 05:13:47 PM PDT 24
Finished Jul 29 05:13:49 PM PDT 24
Peak memory 206712 kb
Host smart-42209089-795c-4f57-a9ed-c25a4390ac3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4063069861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.4063069861
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3793126266
Short name T2903
Test name
Test status
Simulation time 92099564 ps
CPU time 2.23 seconds
Started Jul 29 05:13:44 PM PDT 24
Finished Jul 29 05:13:46 PM PDT 24
Peak memory 214964 kb
Host smart-c3085530-985f-4a65-bd83-0a3100c146df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3793126266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3793126266
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1668915564
Short name T290
Test name
Test status
Simulation time 876866055 ps
CPU time 5.07 seconds
Started Jul 29 05:13:44 PM PDT 24
Finished Jul 29 05:13:49 PM PDT 24
Peak memory 206776 kb
Host smart-0bc767cf-d023-4ba4-ba89-1f2195f62c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1668915564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1668915564
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.304766546
Short name T2905
Test name
Test status
Simulation time 74979940 ps
CPU time 1.19 seconds
Started Jul 29 05:13:53 PM PDT 24
Finished Jul 29 05:13:55 PM PDT 24
Peak memory 222964 kb
Host smart-0abe9075-add3-490d-b5fc-a72244808ba5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304766546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.304766546
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.223617257
Short name T256
Test name
Test status
Simulation time 72315122 ps
CPU time 0.85 seconds
Started Jul 29 05:13:51 PM PDT 24
Finished Jul 29 05:13:52 PM PDT 24
Peak memory 206424 kb
Host smart-5006c79e-f16d-42d7-9fa5-ba933d0b54e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=223617257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.223617257
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.376380755
Short name T208
Test name
Test status
Simulation time 87014614 ps
CPU time 0.78 seconds
Started Jul 29 05:13:48 PM PDT 24
Finished Jul 29 05:13:49 PM PDT 24
Peak memory 206548 kb
Host smart-10ae80b0-b260-4290-9131-9bbd04d1a949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=376380755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.376380755
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.156642494
Short name T2965
Test name
Test status
Simulation time 373627167 ps
CPU time 1.72 seconds
Started Jul 29 05:13:53 PM PDT 24
Finished Jul 29 05:13:55 PM PDT 24
Peak memory 206740 kb
Host smart-71e9cd02-6626-431d-8ec0-2622c442a9df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=156642494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.156642494
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.134563623
Short name T2957
Test name
Test status
Simulation time 304798419 ps
CPU time 3.6 seconds
Started Jul 29 05:13:45 PM PDT 24
Finished Jul 29 05:13:49 PM PDT 24
Peak memory 223040 kb
Host smart-b739053b-f888-44b6-9725-33714891a034
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=134563623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.134563623
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1463632403
Short name T265
Test name
Test status
Simulation time 1289778062 ps
CPU time 5.08 seconds
Started Jul 29 05:13:47 PM PDT 24
Finished Jul 29 05:13:52 PM PDT 24
Peak memory 206764 kb
Host smart-3d898dde-4d70-4291-aa6d-970df40d9e49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1463632403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1463632403
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.4168897178
Short name T2941
Test name
Test status
Simulation time 136475483 ps
CPU time 1.93 seconds
Started Jul 29 05:13:50 PM PDT 24
Finished Jul 29 05:13:52 PM PDT 24
Peak memory 215048 kb
Host smart-87151d79-222d-48f9-8194-5088bed8e906
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168897178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.4168897178
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.434164312
Short name T254
Test name
Test status
Simulation time 110809873 ps
CPU time 0.85 seconds
Started Jul 29 05:13:52 PM PDT 24
Finished Jul 29 05:13:53 PM PDT 24
Peak memory 206488 kb
Host smart-9cd102d0-4d5d-4f7b-8e35-bd423af4fc24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=434164312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.434164312
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2094945676
Short name T279
Test name
Test status
Simulation time 30399487 ps
CPU time 0.71 seconds
Started Jul 29 05:13:52 PM PDT 24
Finished Jul 29 05:13:53 PM PDT 24
Peak memory 206548 kb
Host smart-e4efed30-6ea0-48cf-a4bd-d464359d38e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2094945676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2094945676
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3248393222
Short name T2928
Test name
Test status
Simulation time 169230077 ps
CPU time 1.68 seconds
Started Jul 29 05:13:51 PM PDT 24
Finished Jul 29 05:13:53 PM PDT 24
Peak memory 207036 kb
Host smart-c1253349-b9d8-4156-a2b6-55491b2f815e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3248393222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3248393222
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3948750210
Short name T2932
Test name
Test status
Simulation time 220274095 ps
CPU time 2.18 seconds
Started Jul 29 05:13:51 PM PDT 24
Finished Jul 29 05:13:53 PM PDT 24
Peak memory 206852 kb
Host smart-abb3b88a-8dc1-4910-a8c7-db495721423e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3948750210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3948750210
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1407043976
Short name T2915
Test name
Test status
Simulation time 758208977 ps
CPU time 4.45 seconds
Started Jul 29 05:13:52 PM PDT 24
Finished Jul 29 05:13:56 PM PDT 24
Peak memory 206716 kb
Host smart-55a83dc5-1fb3-49c5-b049-384e418a45f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1407043976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1407043976
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1949737492
Short name T2877
Test name
Test status
Simulation time 84539251 ps
CPU time 1.67 seconds
Started Jul 29 05:13:51 PM PDT 24
Finished Jul 29 05:13:53 PM PDT 24
Peak memory 215076 kb
Host smart-374e3020-8b15-449b-bb95-d71c6f9d8ca7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949737492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1949737492
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3519953203
Short name T2925
Test name
Test status
Simulation time 61940003 ps
CPU time 0.96 seconds
Started Jul 29 05:13:52 PM PDT 24
Finished Jul 29 05:13:53 PM PDT 24
Peak memory 206584 kb
Host smart-b8221535-6c78-4769-b5c2-147e610d8635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3519953203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3519953203
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3871194372
Short name T2889
Test name
Test status
Simulation time 37761706 ps
CPU time 0.73 seconds
Started Jul 29 05:13:53 PM PDT 24
Finished Jul 29 05:13:54 PM PDT 24
Peak memory 206380 kb
Host smart-671c05df-d5c2-4cd1-a1f9-893e044f1313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3871194372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3871194372
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2426761641
Short name T2908
Test name
Test status
Simulation time 88213521 ps
CPU time 1.47 seconds
Started Jul 29 05:13:54 PM PDT 24
Finished Jul 29 05:13:56 PM PDT 24
Peak memory 206784 kb
Host smart-7a54d866-a828-4983-b0b8-76713d5fbcaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2426761641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2426761641
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.178669309
Short name T230
Test name
Test status
Simulation time 151749437 ps
CPU time 1.65 seconds
Started Jul 29 05:13:53 PM PDT 24
Finished Jul 29 05:13:55 PM PDT 24
Peak memory 206864 kb
Host smart-b842c325-95d4-4b31-a454-da0a57153b6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=178669309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.178669309
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.187871644
Short name T232
Test name
Test status
Simulation time 94325970 ps
CPU time 1.53 seconds
Started Jul 29 05:13:52 PM PDT 24
Finished Jul 29 05:13:54 PM PDT 24
Peak memory 214968 kb
Host smart-a78007f8-4270-4a9d-92ff-4311cc00536a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187871644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbde
v_csr_mem_rw_with_rand_reset.187871644
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1465696729
Short name T2934
Test name
Test status
Simulation time 78045236 ps
CPU time 1.03 seconds
Started Jul 29 05:13:51 PM PDT 24
Finished Jul 29 05:13:52 PM PDT 24
Peak memory 206624 kb
Host smart-88d80329-33bb-4fe6-a7fc-f77e5aad2abb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1465696729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1465696729
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.671436437
Short name T2885
Test name
Test status
Simulation time 109986247 ps
CPU time 1.58 seconds
Started Jul 29 05:13:51 PM PDT 24
Finished Jul 29 05:13:53 PM PDT 24
Peak memory 206776 kb
Host smart-943c8dc1-af53-47b7-90fe-44769b109520
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=671436437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.671436437
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1684635401
Short name T215
Test name
Test status
Simulation time 96509727 ps
CPU time 1.57 seconds
Started Jul 29 05:13:51 PM PDT 24
Finished Jul 29 05:13:53 PM PDT 24
Peak memory 206788 kb
Host smart-8a5d4f15-693f-4b38-a57a-cef375af0cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1684635401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1684635401
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2945245158
Short name T2962
Test name
Test status
Simulation time 1010468858 ps
CPU time 6.26 seconds
Started Jul 29 05:13:52 PM PDT 24
Finished Jul 29 05:13:58 PM PDT 24
Peak memory 206780 kb
Host smart-f80683b1-ee9b-4a54-a83c-151e01f6db35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2945245158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2945245158
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1918746053
Short name T200
Test name
Test status
Simulation time 166003885 ps
CPU time 1.97 seconds
Started Jul 29 05:13:57 PM PDT 24
Finished Jul 29 05:13:59 PM PDT 24
Peak memory 215160 kb
Host smart-e8b6de20-9145-4c0e-abb4-f13da45d219c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918746053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1918746053
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1417203614
Short name T2904
Test name
Test status
Simulation time 128677741 ps
CPU time 1.05 seconds
Started Jul 29 05:13:58 PM PDT 24
Finished Jul 29 05:13:59 PM PDT 24
Peak memory 206420 kb
Host smart-25ccc50c-9076-43d5-9114-56c199b5cabc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1417203614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1417203614
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4005472500
Short name T277
Test name
Test status
Simulation time 82822962 ps
CPU time 0.82 seconds
Started Jul 29 05:13:59 PM PDT 24
Finished Jul 29 05:14:00 PM PDT 24
Peak memory 206524 kb
Host smart-fff791ed-2e57-438d-a113-3495b66d9a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4005472500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.4005472500
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3224608243
Short name T201
Test name
Test status
Simulation time 221485053 ps
CPU time 1.42 seconds
Started Jul 29 05:13:57 PM PDT 24
Finished Jul 29 05:13:59 PM PDT 24
Peak memory 206736 kb
Host smart-de61f437-74ed-4675-81db-4b0ccb9f0b73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3224608243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3224608243
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.607973090
Short name T2939
Test name
Test status
Simulation time 96922442 ps
CPU time 1.59 seconds
Started Jul 29 05:13:52 PM PDT 24
Finished Jul 29 05:13:53 PM PDT 24
Peak memory 206792 kb
Host smart-2ab1ab2e-5179-4caf-82a5-0a88a4f9e526
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=607973090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.607973090
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3650345681
Short name T291
Test name
Test status
Simulation time 937552264 ps
CPU time 4.73 seconds
Started Jul 29 05:13:51 PM PDT 24
Finished Jul 29 05:13:56 PM PDT 24
Peak memory 206804 kb
Host smart-278c3721-bab8-4984-b20b-c719713d4cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3650345681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3650345681
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3136755702
Short name T244
Test name
Test status
Simulation time 308379613 ps
CPU time 3.49 seconds
Started Jul 29 05:13:21 PM PDT 24
Finished Jul 29 05:13:25 PM PDT 24
Peak memory 206808 kb
Host smart-0337e6d2-7d8f-4f92-85a9-a126f835b1b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3136755702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3136755702
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2049485302
Short name T2895
Test name
Test status
Simulation time 1656988270 ps
CPU time 8.49 seconds
Started Jul 29 05:13:24 PM PDT 24
Finished Jul 29 05:13:32 PM PDT 24
Peak memory 206868 kb
Host smart-030f96e9-d4e1-4752-9e5d-33be425cd319
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2049485302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2049485302
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2691029662
Short name T2976
Test name
Test status
Simulation time 106116827 ps
CPU time 0.83 seconds
Started Jul 29 05:13:23 PM PDT 24
Finished Jul 29 05:13:24 PM PDT 24
Peak memory 206424 kb
Host smart-291ece41-34e6-4b48-aeab-d17486a6ca98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2691029662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2691029662
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3393015360
Short name T2917
Test name
Test status
Simulation time 95060893 ps
CPU time 1.22 seconds
Started Jul 29 05:13:24 PM PDT 24
Finished Jul 29 05:13:25 PM PDT 24
Peak memory 214916 kb
Host smart-9c9f9fa4-ef0c-4953-a625-23f78566153c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393015360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3393015360
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1634535585
Short name T2886
Test name
Test status
Simulation time 76911510 ps
CPU time 0.99 seconds
Started Jul 29 05:13:24 PM PDT 24
Finished Jul 29 05:13:25 PM PDT 24
Peak memory 206620 kb
Host smart-93ac2f39-8340-4edb-bde9-ef26b52900b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1634535585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1634535585
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3216307557
Short name T206
Test name
Test status
Simulation time 41580108 ps
CPU time 0.69 seconds
Started Jul 29 05:13:22 PM PDT 24
Finished Jul 29 05:13:23 PM PDT 24
Peak memory 206428 kb
Host smart-8f985011-5f71-4cdf-9781-4656bc70c7a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3216307557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3216307557
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1343278703
Short name T2909
Test name
Test status
Simulation time 193987051 ps
CPU time 2.27 seconds
Started Jul 29 05:13:21 PM PDT 24
Finished Jul 29 05:13:24 PM PDT 24
Peak memory 206756 kb
Host smart-26498594-3417-473e-980d-ff96204256c6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1343278703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1343278703
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3644531012
Short name T2865
Test name
Test status
Simulation time 260386565 ps
CPU time 2.44 seconds
Started Jul 29 05:13:23 PM PDT 24
Finished Jul 29 05:13:26 PM PDT 24
Peak memory 206760 kb
Host smart-30c626f1-d132-4e81-bb9c-b3cb781ed4a8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3644531012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3644531012
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1526798100
Short name T2876
Test name
Test status
Simulation time 105669916 ps
CPU time 1.41 seconds
Started Jul 29 05:13:20 PM PDT 24
Finished Jul 29 05:13:22 PM PDT 24
Peak memory 206752 kb
Host smart-05e25c86-c81e-4955-8d24-49e0dee61d2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1526798100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1526798100
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1942757546
Short name T225
Test name
Test status
Simulation time 187028840 ps
CPU time 2.14 seconds
Started Jul 29 05:13:25 PM PDT 24
Finished Jul 29 05:13:27 PM PDT 24
Peak memory 214976 kb
Host smart-9156dbf0-5696-4602-83ac-be9564779865
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1942757546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1942757546
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1687047212
Short name T287
Test name
Test status
Simulation time 476794803 ps
CPU time 3.06 seconds
Started Jul 29 05:13:24 PM PDT 24
Finished Jul 29 05:13:27 PM PDT 24
Peak memory 206716 kb
Host smart-d0642cea-09ba-4bb1-905d-43820e3ac6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1687047212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1687047212
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.803425258
Short name T281
Test name
Test status
Simulation time 55029858 ps
CPU time 0.73 seconds
Started Jul 29 05:14:02 PM PDT 24
Finished Jul 29 05:14:03 PM PDT 24
Peak memory 206496 kb
Host smart-5c63cca4-41fc-4a64-b901-21b03a88ad7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=803425258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.803425258
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1315190470
Short name T2920
Test name
Test status
Simulation time 59347074 ps
CPU time 0.77 seconds
Started Jul 29 05:13:56 PM PDT 24
Finished Jul 29 05:13:57 PM PDT 24
Peak memory 206420 kb
Host smart-7f182aab-ace5-4162-9ae0-4adb39a6ff32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1315190470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1315190470
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3784314207
Short name T2924
Test name
Test status
Simulation time 37241029 ps
CPU time 0.71 seconds
Started Jul 29 05:13:59 PM PDT 24
Finished Jul 29 05:14:00 PM PDT 24
Peak memory 206412 kb
Host smart-832af3f0-1715-4374-b476-312bc791d73a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3784314207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3784314207
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1793138293
Short name T2948
Test name
Test status
Simulation time 50818117 ps
CPU time 0.72 seconds
Started Jul 29 05:13:56 PM PDT 24
Finished Jul 29 05:13:57 PM PDT 24
Peak memory 206460 kb
Host smart-f2b369a1-58a3-4873-86ec-f95d32a0cf7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1793138293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1793138293
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2906614770
Short name T2943
Test name
Test status
Simulation time 46052937 ps
CPU time 0.73 seconds
Started Jul 29 05:13:59 PM PDT 24
Finished Jul 29 05:14:00 PM PDT 24
Peak memory 206380 kb
Host smart-6da5fb58-ced6-4745-9c69-ade00328e4f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2906614770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2906614770
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.795086435
Short name T2900
Test name
Test status
Simulation time 46958100 ps
CPU time 0.74 seconds
Started Jul 29 05:14:00 PM PDT 24
Finished Jul 29 05:14:00 PM PDT 24
Peak memory 206412 kb
Host smart-1a059791-0ba4-4608-a220-4f7bb7134146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=795086435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.795086435
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1588727751
Short name T2919
Test name
Test status
Simulation time 108277181 ps
CPU time 0.8 seconds
Started Jul 29 05:13:56 PM PDT 24
Finished Jul 29 05:13:57 PM PDT 24
Peak memory 206560 kb
Host smart-3875b9f9-d3a8-43bf-b4a9-c14950fbeb72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1588727751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1588727751
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1974413142
Short name T2871
Test name
Test status
Simulation time 40793310 ps
CPU time 0.73 seconds
Started Jul 29 05:13:57 PM PDT 24
Finished Jul 29 05:13:58 PM PDT 24
Peak memory 206380 kb
Host smart-39d2f30e-6467-4c89-88d6-6a1e1fe74ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1974413142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1974413142
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2552413606
Short name T243
Test name
Test status
Simulation time 354551249 ps
CPU time 3.48 seconds
Started Jul 29 05:13:29 PM PDT 24
Finished Jul 29 05:13:33 PM PDT 24
Peak memory 206800 kb
Host smart-348c4e4b-b537-4f3d-9f4f-f2100a2e9628
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2552413606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2552413606
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1647313375
Short name T2953
Test name
Test status
Simulation time 1332391118 ps
CPU time 8.83 seconds
Started Jul 29 05:13:29 PM PDT 24
Finished Jul 29 05:13:38 PM PDT 24
Peak memory 206832 kb
Host smart-14539bb8-c572-48c6-a740-1a38cfbfaba3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1647313375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1647313375
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3748449283
Short name T2937
Test name
Test status
Simulation time 101535513 ps
CPU time 0.92 seconds
Started Jul 29 05:13:34 PM PDT 24
Finished Jul 29 05:13:35 PM PDT 24
Peak memory 206536 kb
Host smart-acc797ee-90f8-481f-8434-8d4ef4cdc423
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3748449283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3748449283
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2041691064
Short name T2887
Test name
Test status
Simulation time 124646087 ps
CPU time 1.47 seconds
Started Jul 29 05:13:28 PM PDT 24
Finished Jul 29 05:13:30 PM PDT 24
Peak memory 215036 kb
Host smart-d9e4913a-20ce-478e-9a70-a04f23b8c71d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041691064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2041691064
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3952081772
Short name T250
Test name
Test status
Simulation time 123680288 ps
CPU time 1.03 seconds
Started Jul 29 05:13:29 PM PDT 24
Finished Jul 29 05:13:30 PM PDT 24
Peak memory 206620 kb
Host smart-4e91e786-993e-481d-b275-bf18ff962baf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3952081772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3952081772
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.580220780
Short name T2918
Test name
Test status
Simulation time 42027591 ps
CPU time 0.7 seconds
Started Jul 29 05:13:28 PM PDT 24
Finished Jul 29 05:13:29 PM PDT 24
Peak memory 206700 kb
Host smart-6a3bffba-5ce2-473b-aa84-d8e3e0ec4c71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=580220780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.580220780
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1062089631
Short name T2970
Test name
Test status
Simulation time 249877782 ps
CPU time 2.59 seconds
Started Jul 29 05:13:29 PM PDT 24
Finished Jul 29 05:13:31 PM PDT 24
Peak memory 215068 kb
Host smart-247938ee-0ddb-4702-b81c-596309f60765
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1062089631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1062089631
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3072895060
Short name T2974
Test name
Test status
Simulation time 715499471 ps
CPU time 4.76 seconds
Started Jul 29 05:13:34 PM PDT 24
Finished Jul 29 05:13:39 PM PDT 24
Peak memory 206772 kb
Host smart-bc6ddb05-40af-42d2-a9f8-e85a511435c8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3072895060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3072895060
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3511173463
Short name T2954
Test name
Test status
Simulation time 220212934 ps
CPU time 1.21 seconds
Started Jul 29 05:13:28 PM PDT 24
Finished Jul 29 05:13:30 PM PDT 24
Peak memory 206772 kb
Host smart-fad84de2-559d-4ca6-9a33-0dc4a9cf7814
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3511173463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3511173463
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2453005175
Short name T221
Test name
Test status
Simulation time 45576557 ps
CPU time 1.29 seconds
Started Jul 29 05:13:24 PM PDT 24
Finished Jul 29 05:13:25 PM PDT 24
Peak memory 206668 kb
Host smart-e5743524-8a05-4fd3-bb0a-a270660e5adc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2453005175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2453005175
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4102645379
Short name T220
Test name
Test status
Simulation time 504191438 ps
CPU time 4.24 seconds
Started Jul 29 05:13:28 PM PDT 24
Finished Jul 29 05:13:32 PM PDT 24
Peak memory 206776 kb
Host smart-69fe72d8-9c0e-456e-a302-3a5771bdcc80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4102645379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.4102645379
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1957921440
Short name T2960
Test name
Test status
Simulation time 42338532 ps
CPU time 0.73 seconds
Started Jul 29 05:13:58 PM PDT 24
Finished Jul 29 05:13:59 PM PDT 24
Peak memory 206568 kb
Host smart-6972916f-73b7-4e31-9f42-afefa8f9119f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1957921440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1957921440
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.323527371
Short name T2868
Test name
Test status
Simulation time 79900241 ps
CPU time 0.77 seconds
Started Jul 29 05:14:02 PM PDT 24
Finished Jul 29 05:14:02 PM PDT 24
Peak memory 206440 kb
Host smart-e6e05dbc-b376-44cf-a4cf-c56132c99de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=323527371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.323527371
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.516570635
Short name T2936
Test name
Test status
Simulation time 58107167 ps
CPU time 0.7 seconds
Started Jul 29 05:13:58 PM PDT 24
Finished Jul 29 05:13:59 PM PDT 24
Peak memory 206564 kb
Host smart-af0aa74e-bc2e-4ead-b40a-3f432825a0d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=516570635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.516570635
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.260274522
Short name T2929
Test name
Test status
Simulation time 42179081 ps
CPU time 0.74 seconds
Started Jul 29 05:13:57 PM PDT 24
Finished Jul 29 05:13:58 PM PDT 24
Peak memory 206620 kb
Host smart-e9f23ff9-80bf-4ab1-9f52-afbc04554052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=260274522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.260274522
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.652116450
Short name T2890
Test name
Test status
Simulation time 43321513 ps
CPU time 0.73 seconds
Started Jul 29 05:13:58 PM PDT 24
Finished Jul 29 05:13:59 PM PDT 24
Peak memory 206428 kb
Host smart-741dcec9-37ed-4676-91de-226a05d9476a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=652116450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.652116450
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1575527754
Short name T2902
Test name
Test status
Simulation time 47797691 ps
CPU time 0.8 seconds
Started Jul 29 05:13:56 PM PDT 24
Finished Jul 29 05:13:57 PM PDT 24
Peak memory 206548 kb
Host smart-8bf3a9a4-b7d2-4c54-83a8-a47371ad2b1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1575527754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1575527754
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3899031608
Short name T2872
Test name
Test status
Simulation time 38278699 ps
CPU time 0.73 seconds
Started Jul 29 05:13:57 PM PDT 24
Finished Jul 29 05:13:58 PM PDT 24
Peak memory 206480 kb
Host smart-cfdddf09-7cbd-4b4f-8dff-56f391d864f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3899031608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3899031608
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4242630078
Short name T2907
Test name
Test status
Simulation time 79623643 ps
CPU time 0.78 seconds
Started Jul 29 05:13:59 PM PDT 24
Finished Jul 29 05:14:00 PM PDT 24
Peak memory 206528 kb
Host smart-03a8f73f-9522-4791-a254-32e9151ba316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4242630078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.4242630078
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1640466602
Short name T2910
Test name
Test status
Simulation time 52975723 ps
CPU time 0.71 seconds
Started Jul 29 05:13:59 PM PDT 24
Finished Jul 29 05:14:00 PM PDT 24
Peak memory 206424 kb
Host smart-6d75dd36-1dec-4a2c-a3c8-13613967f348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1640466602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1640466602
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2235529187
Short name T267
Test name
Test status
Simulation time 38247277 ps
CPU time 0.71 seconds
Started Jul 29 05:13:55 PM PDT 24
Finished Jul 29 05:13:56 PM PDT 24
Peak memory 206504 kb
Host smart-0ff59079-4d36-4e33-8d7f-2927485ba219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2235529187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2235529187
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2959167053
Short name T248
Test name
Test status
Simulation time 98085956 ps
CPU time 1.99 seconds
Started Jul 29 05:13:34 PM PDT 24
Finished Jul 29 05:13:36 PM PDT 24
Peak memory 206804 kb
Host smart-fef43d41-c850-4d9a-b211-79f749758196
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2959167053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2959167053
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.492388362
Short name T2973
Test name
Test status
Simulation time 644366429 ps
CPU time 4.22 seconds
Started Jul 29 05:13:28 PM PDT 24
Finished Jul 29 05:13:32 PM PDT 24
Peak memory 206812 kb
Host smart-51aaddaf-3f63-44b6-b396-7ff15ee6d773
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=492388362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.492388362
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2103907181
Short name T2882
Test name
Test status
Simulation time 136547225 ps
CPU time 0.91 seconds
Started Jul 29 05:13:29 PM PDT 24
Finished Jul 29 05:13:30 PM PDT 24
Peak memory 206512 kb
Host smart-7e80a281-8de6-4c4f-b0ac-63376c2063f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2103907181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2103907181
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3851827557
Short name T2884
Test name
Test status
Simulation time 172801204 ps
CPU time 1.79 seconds
Started Jul 29 05:13:28 PM PDT 24
Finished Jul 29 05:13:30 PM PDT 24
Peak memory 218488 kb
Host smart-3e4970db-ab1e-4e27-bfeb-64479977d5eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851827557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3851827557
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.272153809
Short name T2935
Test name
Test status
Simulation time 66158252 ps
CPU time 0.87 seconds
Started Jul 29 05:13:29 PM PDT 24
Finished Jul 29 05:13:30 PM PDT 24
Peak memory 206572 kb
Host smart-bc4b57ea-e709-46f5-a7b3-9ced8d2fdfa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=272153809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.272153809
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1797467110
Short name T278
Test name
Test status
Simulation time 39790050 ps
CPU time 0.72 seconds
Started Jul 29 05:13:28 PM PDT 24
Finished Jul 29 05:13:29 PM PDT 24
Peak memory 206700 kb
Host smart-9d60e4e6-8071-44ca-b66c-06056d858f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1797467110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1797467110
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2268869107
Short name T246
Test name
Test status
Simulation time 69188896 ps
CPU time 1.41 seconds
Started Jul 29 05:13:26 PM PDT 24
Finished Jul 29 05:13:27 PM PDT 24
Peak memory 214888 kb
Host smart-fb4643e1-8e7b-4555-9f19-24b3eb97a880
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2268869107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2268869107
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.128187452
Short name T2863
Test name
Test status
Simulation time 410202513 ps
CPU time 2.87 seconds
Started Jul 29 05:13:27 PM PDT 24
Finished Jul 29 05:13:30 PM PDT 24
Peak memory 206752 kb
Host smart-a2b0a6e3-d48e-446f-8ddb-573fd81bec14
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=128187452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.128187452
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.744589582
Short name T2930
Test name
Test status
Simulation time 121899435 ps
CPU time 1.17 seconds
Started Jul 29 05:13:26 PM PDT 24
Finished Jul 29 05:13:27 PM PDT 24
Peak memory 206652 kb
Host smart-28a99140-d99e-4387-9ecd-ed7623a94d5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=744589582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.744589582
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2374935073
Short name T224
Test name
Test status
Simulation time 282167962 ps
CPU time 3.05 seconds
Started Jul 29 05:13:29 PM PDT 24
Finished Jul 29 05:13:32 PM PDT 24
Peak memory 220380 kb
Host smart-4975a134-f398-40a4-9a0e-44ced3f0b889
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2374935073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2374935073
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3474058761
Short name T2880
Test name
Test status
Simulation time 413206948 ps
CPU time 3 seconds
Started Jul 29 05:13:26 PM PDT 24
Finished Jul 29 05:13:29 PM PDT 24
Peak memory 206780 kb
Host smart-81b5dd59-a336-4b06-9f40-fa1754881c67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3474058761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3474058761
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3186471797
Short name T2942
Test name
Test status
Simulation time 41380117 ps
CPU time 0.74 seconds
Started Jul 29 05:14:02 PM PDT 24
Finished Jul 29 05:14:03 PM PDT 24
Peak memory 206492 kb
Host smart-a01f032b-2099-4d01-968f-bd3368a710ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3186471797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3186471797
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4169808462
Short name T2911
Test name
Test status
Simulation time 53804432 ps
CPU time 0.78 seconds
Started Jul 29 05:14:01 PM PDT 24
Finished Jul 29 05:14:02 PM PDT 24
Peak memory 206436 kb
Host smart-0ca3930c-665c-440d-8c8c-f3e9e8f0c390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4169808462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.4169808462
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4148878696
Short name T2866
Test name
Test status
Simulation time 63499476 ps
CPU time 0.74 seconds
Started Jul 29 05:14:01 PM PDT 24
Finished Jul 29 05:14:02 PM PDT 24
Peak memory 206492 kb
Host smart-456cc0be-1cc5-4a75-ac08-951fde5ae3bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4148878696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.4148878696
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2020308171
Short name T282
Test name
Test status
Simulation time 40322487 ps
CPU time 0.7 seconds
Started Jul 29 05:14:05 PM PDT 24
Finished Jul 29 05:14:06 PM PDT 24
Peak memory 206488 kb
Host smart-a93838f7-2a88-422d-a7b9-5e07886ca947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2020308171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2020308171
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4172114155
Short name T2969
Test name
Test status
Simulation time 40265277 ps
CPU time 0.72 seconds
Started Jul 29 05:13:56 PM PDT 24
Finished Jul 29 05:13:57 PM PDT 24
Peak memory 206532 kb
Host smart-e12d9145-5edc-4570-bbd7-3e6f0c68cdfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4172114155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.4172114155
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2269217085
Short name T2867
Test name
Test status
Simulation time 38864173 ps
CPU time 0.7 seconds
Started Jul 29 05:14:13 PM PDT 24
Finished Jul 29 05:14:14 PM PDT 24
Peak memory 206424 kb
Host smart-09c23313-dff3-49a1-b37b-48588f40034d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2269217085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2269217085
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3638408719
Short name T2938
Test name
Test status
Simulation time 56360200 ps
CPU time 0.79 seconds
Started Jul 29 05:14:34 PM PDT 24
Finished Jul 29 05:14:35 PM PDT 24
Peak memory 206544 kb
Host smart-8c666d8f-ecb8-48f3-b54b-0ee2c535b161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3638408719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3638408719
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3790637355
Short name T266
Test name
Test status
Simulation time 56251859 ps
CPU time 0.7 seconds
Started Jul 29 05:14:08 PM PDT 24
Finished Jul 29 05:14:09 PM PDT 24
Peak memory 206476 kb
Host smart-2f7ed6bd-dc39-40d3-be9b-99178d54446a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3790637355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3790637355
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1218558317
Short name T2916
Test name
Test status
Simulation time 50904299 ps
CPU time 0.7 seconds
Started Jul 29 05:14:13 PM PDT 24
Finished Jul 29 05:14:14 PM PDT 24
Peak memory 206560 kb
Host smart-9a5df355-9a3a-49a0-9973-fe53e82c7e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1218558317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1218558317
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.438486470
Short name T2906
Test name
Test status
Simulation time 115294219 ps
CPU time 1.31 seconds
Started Jul 29 05:13:34 PM PDT 24
Finished Jul 29 05:13:36 PM PDT 24
Peak memory 215012 kb
Host smart-4ed4ebf5-df8b-4dc4-933b-6a32b12d594c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438486470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.438486470
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1000732472
Short name T252
Test name
Test status
Simulation time 95500173 ps
CPU time 1.02 seconds
Started Jul 29 05:13:36 PM PDT 24
Finished Jul 29 05:13:37 PM PDT 24
Peak memory 206556 kb
Host smart-7a48f5e9-c959-41a9-aa50-e5fc3d7d7ad2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1000732472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1000732472
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.4284034551
Short name T2896
Test name
Test status
Simulation time 52262130 ps
CPU time 0.74 seconds
Started Jul 29 05:13:34 PM PDT 24
Finished Jul 29 05:13:35 PM PDT 24
Peak memory 206484 kb
Host smart-2102758b-765a-4aa6-ae70-6681444e7f68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4284034551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.4284034551
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2839884937
Short name T2892
Test name
Test status
Simulation time 247411411 ps
CPU time 1.41 seconds
Started Jul 29 05:13:34 PM PDT 24
Finished Jul 29 05:13:36 PM PDT 24
Peak memory 206768 kb
Host smart-1ca11cea-bb5f-4044-8f34-f883066469a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2839884937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2839884937
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.277128423
Short name T2926
Test name
Test status
Simulation time 275234275 ps
CPU time 3.4 seconds
Started Jul 29 05:13:35 PM PDT 24
Finished Jul 29 05:13:39 PM PDT 24
Peak memory 215068 kb
Host smart-c60f0c7b-efbf-44d6-b579-1abf97407ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=277128423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.277128423
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.72302796
Short name T288
Test name
Test status
Simulation time 1029635997 ps
CPU time 4.52 seconds
Started Jul 29 05:13:33 PM PDT 24
Finished Jul 29 05:13:38 PM PDT 24
Peak memory 206712 kb
Host smart-48c77483-0470-4c9a-9b5d-e9c646a5b912
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=72302796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.72302796
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1000621606
Short name T2946
Test name
Test status
Simulation time 149844276 ps
CPU time 1.74 seconds
Started Jul 29 05:13:33 PM PDT 24
Finished Jul 29 05:13:35 PM PDT 24
Peak memory 215084 kb
Host smart-10d5f917-68a7-4604-ac75-a75ca5284669
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000621606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1000621606
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4193321639
Short name T255
Test name
Test status
Simulation time 69505983 ps
CPU time 0.81 seconds
Started Jul 29 05:13:34 PM PDT 24
Finished Jul 29 05:13:34 PM PDT 24
Peak memory 206436 kb
Host smart-058cd86e-c7cb-4c70-b9a4-b28ed34f420d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4193321639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4193321639
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3733256402
Short name T2961
Test name
Test status
Simulation time 51941030 ps
CPU time 0.73 seconds
Started Jul 29 05:13:33 PM PDT 24
Finished Jul 29 05:13:34 PM PDT 24
Peak memory 206544 kb
Host smart-2cc00a75-bf1d-4258-9ad6-381739b530ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3733256402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3733256402
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3711724831
Short name T2971
Test name
Test status
Simulation time 86027384 ps
CPU time 1.07 seconds
Started Jul 29 05:13:32 PM PDT 24
Finished Jul 29 05:13:34 PM PDT 24
Peak memory 206632 kb
Host smart-d4f4466f-0713-4adb-b19d-da53e69154a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3711724831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3711724831
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1256557467
Short name T228
Test name
Test status
Simulation time 358086308 ps
CPU time 3.93 seconds
Started Jul 29 05:13:36 PM PDT 24
Finished Jul 29 05:13:40 PM PDT 24
Peak memory 220056 kb
Host smart-2142aa84-e884-4e8b-b54c-037b49e577d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1256557467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1256557467
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3445396744
Short name T2940
Test name
Test status
Simulation time 725703028 ps
CPU time 4.95 seconds
Started Jul 29 05:13:35 PM PDT 24
Finished Jul 29 05:13:40 PM PDT 24
Peak memory 206896 kb
Host smart-a0e1a24d-d6da-4a1c-adcd-1c545835cdfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3445396744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3445396744
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.48296234
Short name T2914
Test name
Test status
Simulation time 133116531 ps
CPU time 2.94 seconds
Started Jul 29 05:13:35 PM PDT 24
Finished Jul 29 05:13:38 PM PDT 24
Peak memory 215060 kb
Host smart-898a8be0-3f44-4e47-b8d2-cf7d0337b31d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48296234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_
csr_mem_rw_with_rand_reset.48296234
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3029223548
Short name T2901
Test name
Test status
Simulation time 68602832 ps
CPU time 0.82 seconds
Started Jul 29 05:13:36 PM PDT 24
Finished Jul 29 05:13:37 PM PDT 24
Peak memory 206476 kb
Host smart-3d3122a1-3412-45e5-afc6-ebd776ec9637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3029223548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3029223548
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1869047718
Short name T2975
Test name
Test status
Simulation time 83355652 ps
CPU time 0.74 seconds
Started Jul 29 05:13:34 PM PDT 24
Finished Jul 29 05:13:35 PM PDT 24
Peak memory 206448 kb
Host smart-cc44717c-ebf8-45b0-9908-9eabfb72dd92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1869047718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1869047718
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3070211226
Short name T2958
Test name
Test status
Simulation time 214622977 ps
CPU time 1.88 seconds
Started Jul 29 05:13:34 PM PDT 24
Finished Jul 29 05:13:36 PM PDT 24
Peak memory 206784 kb
Host smart-9c8fd082-e4da-4d94-b2b2-6d50ed547179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3070211226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3070211226
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1335899630
Short name T227
Test name
Test status
Simulation time 250858738 ps
CPU time 2.76 seconds
Started Jul 29 05:13:35 PM PDT 24
Finished Jul 29 05:13:38 PM PDT 24
Peak memory 220084 kb
Host smart-a3bec904-e0b9-4d7a-8704-62fc2a2b27a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1335899630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1335899630
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3309212872
Short name T222
Test name
Test status
Simulation time 1932938865 ps
CPU time 6.53 seconds
Started Jul 29 05:13:36 PM PDT 24
Finished Jul 29 05:13:42 PM PDT 24
Peak memory 206772 kb
Host smart-c653c599-e280-4d80-b193-49c383e78a4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3309212872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3309212872
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2957239399
Short name T2913
Test name
Test status
Simulation time 61505217 ps
CPU time 1.57 seconds
Started Jul 29 05:13:40 PM PDT 24
Finished Jul 29 05:13:42 PM PDT 24
Peak memory 215112 kb
Host smart-6a7dca31-1408-4b12-81fd-d36f4ae17126
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957239399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2957239399
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4278874481
Short name T2952
Test name
Test status
Simulation time 40256918 ps
CPU time 1.01 seconds
Started Jul 29 05:13:41 PM PDT 24
Finished Jul 29 05:13:42 PM PDT 24
Peak memory 206576 kb
Host smart-005faeff-5978-43fa-bd86-3ad169f964a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4278874481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.4278874481
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.119645392
Short name T2977
Test name
Test status
Simulation time 41874978 ps
CPU time 0.72 seconds
Started Jul 29 05:13:34 PM PDT 24
Finished Jul 29 05:13:35 PM PDT 24
Peak memory 206448 kb
Host smart-2c293828-5688-4bf2-9be7-042b6d59bd05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=119645392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.119645392
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3204458934
Short name T2883
Test name
Test status
Simulation time 110516280 ps
CPU time 1.18 seconds
Started Jul 29 05:13:42 PM PDT 24
Finished Jul 29 05:13:43 PM PDT 24
Peak memory 206856 kb
Host smart-e5dd4968-5ec9-4c0d-a7fe-3f282816de2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3204458934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3204458934
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3936420976
Short name T2922
Test name
Test status
Simulation time 143755598 ps
CPU time 1.89 seconds
Started Jul 29 05:13:32 PM PDT 24
Finished Jul 29 05:13:34 PM PDT 24
Peak memory 222544 kb
Host smart-d5188568-0320-482b-bc92-30458b0b4172
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3936420976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3936420976
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3080953403
Short name T2944
Test name
Test status
Simulation time 424751809 ps
CPU time 2.66 seconds
Started Jul 29 05:13:33 PM PDT 24
Finished Jul 29 05:13:36 PM PDT 24
Peak memory 206816 kb
Host smart-a92bd3f8-80c3-45dc-a312-ed90954ecaa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3080953403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3080953403
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1969622371
Short name T226
Test name
Test status
Simulation time 85179997 ps
CPU time 1.29 seconds
Started Jul 29 05:13:41 PM PDT 24
Finished Jul 29 05:13:42 PM PDT 24
Peak memory 215020 kb
Host smart-f3b6d55a-ff09-4b66-bb72-9fe3dde1b710
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969622371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1969622371
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2334261617
Short name T216
Test name
Test status
Simulation time 56229586 ps
CPU time 0.94 seconds
Started Jul 29 05:13:40 PM PDT 24
Finished Jul 29 05:13:41 PM PDT 24
Peak memory 206552 kb
Host smart-cd6ae890-31ec-41bb-8e21-50ff0a863331
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2334261617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2334261617
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4271310329
Short name T2923
Test name
Test status
Simulation time 97362214 ps
CPU time 0.76 seconds
Started Jul 29 05:13:39 PM PDT 24
Finished Jul 29 05:13:40 PM PDT 24
Peak memory 206476 kb
Host smart-a86e369c-fef6-4a14-950b-bf6f95dc0c39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4271310329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.4271310329
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.278633085
Short name T2950
Test name
Test status
Simulation time 210659040 ps
CPU time 1.5 seconds
Started Jul 29 05:13:40 PM PDT 24
Finished Jul 29 05:13:41 PM PDT 24
Peak memory 206708 kb
Host smart-62ecdac3-36d8-4b51-911f-4e49dd68e395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=278633085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.278633085
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3551273916
Short name T2898
Test name
Test status
Simulation time 116395148 ps
CPU time 1.61 seconds
Started Jul 29 05:13:40 PM PDT 24
Finished Jul 29 05:13:42 PM PDT 24
Peak memory 206824 kb
Host smart-6d54ce34-928f-4394-a218-71e54a021a71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3551273916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3551273916
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.408273745
Short name T289
Test name
Test status
Simulation time 2042649013 ps
CPU time 5.41 seconds
Started Jul 29 05:13:40 PM PDT 24
Finished Jul 29 05:13:45 PM PDT 24
Peak memory 206816 kb
Host smart-776238ad-07b8-4f74-82bf-f3a6df6edaf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=408273745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.408273745
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.427066243
Short name T1058
Test name
Test status
Simulation time 74942588 ps
CPU time 0.7 seconds
Started Jul 29 06:10:30 PM PDT 24
Finished Jul 29 06:10:31 PM PDT 24
Peak memory 207120 kb
Host smart-970e25c5-0086-4bcd-ada3-7bbddb8920c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=427066243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.427066243
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2654213797
Short name T1343
Test name
Test status
Simulation time 3858233898 ps
CPU time 6.27 seconds
Started Jul 29 06:10:03 PM PDT 24
Finished Jul 29 06:10:09 PM PDT 24
Peak memory 207396 kb
Host smart-0b851b86-b7b6-45c2-8955-a2317498609c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654213797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.2654213797
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.969484982
Short name T2822
Test name
Test status
Simulation time 13372922325 ps
CPU time 14.73 seconds
Started Jul 29 06:10:03 PM PDT 24
Finished Jul 29 06:10:17 PM PDT 24
Peak memory 207532 kb
Host smart-8635d011-5aa7-45d7-924d-e43ee012bc9c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=969484982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.969484982
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.1299395900
Short name T2771
Test name
Test status
Simulation time 23446546733 ps
CPU time 28.45 seconds
Started Jul 29 06:10:02 PM PDT 24
Finished Jul 29 06:10:31 PM PDT 24
Peak memory 207412 kb
Host smart-377ec4c9-47ec-452a-a047-5edba1210cf9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299395900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.1299395900
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3904974363
Short name T799
Test name
Test status
Simulation time 233093538 ps
CPU time 0.97 seconds
Started Jul 29 06:10:03 PM PDT 24
Finished Jul 29 06:10:04 PM PDT 24
Peak memory 207136 kb
Host smart-cc84e1ce-668f-4198-bae2-e75d24ecd251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39049
74363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3904974363
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1831540537
Short name T482
Test name
Test status
Simulation time 144155000 ps
CPU time 0.87 seconds
Started Jul 29 06:10:09 PM PDT 24
Finished Jul 29 06:10:10 PM PDT 24
Peak memory 207072 kb
Host smart-fb5cef9b-abd3-4767-8cb2-ef333246ca09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18315
40537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1831540537
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.2144181191
Short name T1339
Test name
Test status
Simulation time 170122827 ps
CPU time 0.89 seconds
Started Jul 29 06:10:11 PM PDT 24
Finished Jul 29 06:10:12 PM PDT 24
Peak memory 207068 kb
Host smart-60653686-5412-4741-a1d7-4b5c6b30b236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21441
81191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.2144181191
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2015411877
Short name T2510
Test name
Test status
Simulation time 285544161 ps
CPU time 1.06 seconds
Started Jul 29 06:10:09 PM PDT 24
Finished Jul 29 06:10:10 PM PDT 24
Peak memory 207120 kb
Host smart-5364c85f-8fbd-43e9-a858-4af5f871e686
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2015411877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2015411877
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.854128015
Short name T988
Test name
Test status
Simulation time 7631869296 ps
CPU time 15.8 seconds
Started Jul 29 06:10:09 PM PDT 24
Finished Jul 29 06:10:25 PM PDT 24
Peak memory 207380 kb
Host smart-4655b306-0678-441f-8181-7cadd01df47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85412
8015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.854128015
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.4224634294
Short name T2289
Test name
Test status
Simulation time 855604622 ps
CPU time 18.5 seconds
Started Jul 29 06:10:14 PM PDT 24
Finished Jul 29 06:10:33 PM PDT 24
Peak memory 207192 kb
Host smart-cd7700f2-a9cd-4ea8-b3b2-7224cd5477d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224634294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.4224634294
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3798197612
Short name T1250
Test name
Test status
Simulation time 466572575 ps
CPU time 1.51 seconds
Started Jul 29 06:10:07 PM PDT 24
Finished Jul 29 06:10:09 PM PDT 24
Peak memory 207040 kb
Host smart-4e7f1ebd-e0a8-45b1-8626-9725336d53ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37981
97612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3798197612
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_enable.2047884213
Short name T1214
Test name
Test status
Simulation time 69004412 ps
CPU time 0.74 seconds
Started Jul 29 06:10:07 PM PDT 24
Finished Jul 29 06:10:08 PM PDT 24
Peak memory 207144 kb
Host smart-68a0710b-a97a-4f7c-b182-795b6679d5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20478
84213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2047884213
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3628636352
Short name T2797
Test name
Test status
Simulation time 823057012 ps
CPU time 2.24 seconds
Started Jul 29 06:10:13 PM PDT 24
Finished Jul 29 06:10:15 PM PDT 24
Peak memory 207208 kb
Host smart-78c186d0-b3bc-4193-9cd4-04cc366c6bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36286
36352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3628636352
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.551141161
Short name T305
Test name
Test status
Simulation time 116186082950 ps
CPU time 183.35 seconds
Started Jul 29 06:10:08 PM PDT 24
Finished Jul 29 06:13:11 PM PDT 24
Peak memory 207416 kb
Host smart-6f02b989-d846-4ba9-80d2-e4309fcab27b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=551141161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.551141161
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.586224832
Short name T1647
Test name
Test status
Simulation time 108187704368 ps
CPU time 194.17 seconds
Started Jul 29 06:10:08 PM PDT 24
Finished Jul 29 06:13:23 PM PDT 24
Peak memory 207380 kb
Host smart-47e8f5b5-e015-4a40-8a89-b59c3f4e3e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586224832 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.586224832
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.372930411
Short name T1404
Test name
Test status
Simulation time 84108442043 ps
CPU time 131.83 seconds
Started Jul 29 06:10:08 PM PDT 24
Finished Jul 29 06:12:20 PM PDT 24
Peak memory 207408 kb
Host smart-384995cc-ea27-4f0e-b6f2-3c07978c9867
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=372930411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.372930411
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.2501107368
Short name T2452
Test name
Test status
Simulation time 82164661155 ps
CPU time 137.18 seconds
Started Jul 29 06:10:09 PM PDT 24
Finished Jul 29 06:12:26 PM PDT 24
Peak memory 207436 kb
Host smart-8a6f203c-92c7-48f9-9b42-d37f0ac97f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25011
07368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.2501107368
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1816532418
Short name T1401
Test name
Test status
Simulation time 207526973 ps
CPU time 1.11 seconds
Started Jul 29 06:10:08 PM PDT 24
Finished Jul 29 06:10:09 PM PDT 24
Peak memory 207292 kb
Host smart-43ecbdd5-7370-4379-a2ee-4d8b049134ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1816532418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1816532418
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2717255796
Short name T2291
Test name
Test status
Simulation time 147855973 ps
CPU time 0.85 seconds
Started Jul 29 06:10:06 PM PDT 24
Finished Jul 29 06:10:07 PM PDT 24
Peak memory 207012 kb
Host smart-8924f3fd-0d2a-4096-84d5-5835017cbc04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27172
55796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2717255796
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1091725876
Short name T1787
Test name
Test status
Simulation time 220599711 ps
CPU time 1 seconds
Started Jul 29 06:10:17 PM PDT 24
Finished Jul 29 06:10:18 PM PDT 24
Peak memory 207060 kb
Host smart-93205c4b-3a37-47fa-b5c3-1b8658ba33ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10917
25876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1091725876
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1734389535
Short name T475
Test name
Test status
Simulation time 8352697950 ps
CPU time 62.69 seconds
Started Jul 29 06:10:07 PM PDT 24
Finished Jul 29 06:11:09 PM PDT 24
Peak memory 215612 kb
Host smart-de89e315-138f-4555-bca6-13bd4e289e0a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1734389535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1734389535
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.3083220612
Short name T869
Test name
Test status
Simulation time 10249072787 ps
CPU time 72.92 seconds
Started Jul 29 06:10:14 PM PDT 24
Finished Jul 29 06:11:27 PM PDT 24
Peak memory 207444 kb
Host smart-7e6a07c4-f1f3-4a56-987f-220cfeca16d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3083220612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.3083220612
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1292437078
Short name T848
Test name
Test status
Simulation time 155449183 ps
CPU time 0.85 seconds
Started Jul 29 06:10:16 PM PDT 24
Finished Jul 29 06:10:17 PM PDT 24
Peak memory 207096 kb
Host smart-a54c8019-8468-4923-b6eb-6b0cddd40ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12924
37078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1292437078
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.901449985
Short name T74
Test name
Test status
Simulation time 576315408 ps
CPU time 1.67 seconds
Started Jul 29 06:10:15 PM PDT 24
Finished Jul 29 06:10:16 PM PDT 24
Peak memory 207068 kb
Host smart-ccc288cf-426b-4435-8659-867f953e3549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90144
9985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.901449985
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.1409561793
Short name T2820
Test name
Test status
Simulation time 23356630096 ps
CPU time 30.81 seconds
Started Jul 29 06:10:14 PM PDT 24
Finished Jul 29 06:10:45 PM PDT 24
Peak memory 207496 kb
Host smart-dfab1a43-ddb7-4fb1-b873-67aa4bad4e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14095
61793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.1409561793
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1700761641
Short name T780
Test name
Test status
Simulation time 3314886975 ps
CPU time 5.05 seconds
Started Jul 29 06:10:17 PM PDT 24
Finished Jul 29 06:10:22 PM PDT 24
Peak memory 207364 kb
Host smart-09d05ece-3a7b-48b5-b800-e63587012018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17007
61641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1700761641
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.556828403
Short name T751
Test name
Test status
Simulation time 4831627263 ps
CPU time 46.56 seconds
Started Jul 29 06:10:20 PM PDT 24
Finished Jul 29 06:11:07 PM PDT 24
Peak memory 217156 kb
Host smart-def8db1c-b7b1-4470-940a-4e72d71f0e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55682
8403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.556828403
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2676779462
Short name T2146
Test name
Test status
Simulation time 4757393514 ps
CPU time 144.4 seconds
Started Jul 29 06:10:15 PM PDT 24
Finished Jul 29 06:12:39 PM PDT 24
Peak memory 215636 kb
Host smart-e63c4fcf-d976-4e43-9cdd-f5dfa961bd9f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2676779462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2676779462
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2985887170
Short name T1745
Test name
Test status
Simulation time 245361815 ps
CPU time 0.96 seconds
Started Jul 29 06:10:20 PM PDT 24
Finished Jul 29 06:10:21 PM PDT 24
Peak memory 207048 kb
Host smart-0aaae3e6-10d5-4994-a601-3fcb94796126
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2985887170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2985887170
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.4151766644
Short name T987
Test name
Test status
Simulation time 179569867 ps
CPU time 0.95 seconds
Started Jul 29 06:10:18 PM PDT 24
Finished Jul 29 06:10:19 PM PDT 24
Peak memory 207084 kb
Host smart-e6117b66-c0e6-4543-9944-a837990f8a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41517
66644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.4151766644
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.770905253
Short name T1253
Test name
Test status
Simulation time 5549513992 ps
CPU time 173.63 seconds
Started Jul 29 06:10:16 PM PDT 24
Finished Jul 29 06:13:10 PM PDT 24
Peak memory 215632 kb
Host smart-17e1628e-40c7-45b4-aa92-744ecce3dec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77090
5253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.770905253
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.1945632308
Short name T1532
Test name
Test status
Simulation time 4243252274 ps
CPU time 33.63 seconds
Started Jul 29 06:10:17 PM PDT 24
Finished Jul 29 06:10:51 PM PDT 24
Peak memory 207400 kb
Host smart-497618ef-5c0e-47b3-b324-e16fc7f6e90d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1945632308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.1945632308
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1742878362
Short name T1077
Test name
Test status
Simulation time 155981311 ps
CPU time 0.93 seconds
Started Jul 29 06:10:18 PM PDT 24
Finished Jul 29 06:10:19 PM PDT 24
Peak memory 207112 kb
Host smart-586bd328-0121-4354-a449-ed252f6f9fc9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1742878362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1742878362
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2117712003
Short name T2619
Test name
Test status
Simulation time 155557501 ps
CPU time 0.86 seconds
Started Jul 29 06:10:17 PM PDT 24
Finished Jul 29 06:10:18 PM PDT 24
Peak memory 207136 kb
Host smart-fbf95183-b20d-418b-b189-4c5a894b44bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21177
12003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2117712003
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2112158337
Short name T75
Test name
Test status
Simulation time 494354031 ps
CPU time 1.44 seconds
Started Jul 29 06:10:14 PM PDT 24
Finished Jul 29 06:10:16 PM PDT 24
Peak memory 207072 kb
Host smart-767844c2-263d-4a49-b45d-6994433a493e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21121
58337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2112158337
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.878145198
Short name T1607
Test name
Test status
Simulation time 175407059 ps
CPU time 0.9 seconds
Started Jul 29 06:10:14 PM PDT 24
Finished Jul 29 06:10:15 PM PDT 24
Peak memory 207044 kb
Host smart-27526c8b-939f-4767-9277-4e018836cb89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87814
5198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.878145198
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2008006899
Short name T1026
Test name
Test status
Simulation time 196353184 ps
CPU time 0.92 seconds
Started Jul 29 06:10:15 PM PDT 24
Finished Jul 29 06:10:16 PM PDT 24
Peak memory 207032 kb
Host smart-5c90be67-1fae-4149-9ce1-5f46768f7415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20080
06899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2008006899
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2840909263
Short name T1462
Test name
Test status
Simulation time 239304194 ps
CPU time 0.99 seconds
Started Jul 29 06:10:15 PM PDT 24
Finished Jul 29 06:10:16 PM PDT 24
Peak memory 207020 kb
Host smart-ef3a9790-fcca-4d27-8464-468fd8de7cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28409
09263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2840909263
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.486871303
Short name T2567
Test name
Test status
Simulation time 162653874 ps
CPU time 0.92 seconds
Started Jul 29 06:10:18 PM PDT 24
Finished Jul 29 06:10:19 PM PDT 24
Peak memory 207116 kb
Host smart-565756ac-b192-44be-b206-e02897964ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48687
1303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.486871303
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2680674568
Short name T1060
Test name
Test status
Simulation time 169570441 ps
CPU time 0.94 seconds
Started Jul 29 06:10:17 PM PDT 24
Finished Jul 29 06:10:19 PM PDT 24
Peak memory 207092 kb
Host smart-3b090b97-8cb1-4c10-90f5-449985635950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26806
74568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2680674568
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.2016107347
Short name T1336
Test name
Test status
Simulation time 249799359 ps
CPU time 1.03 seconds
Started Jul 29 06:10:17 PM PDT 24
Finished Jul 29 06:10:18 PM PDT 24
Peak memory 207080 kb
Host smart-19059dbf-5d47-441a-8168-f62947778c4b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2016107347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.2016107347
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1131813158
Short name T2465
Test name
Test status
Simulation time 215188745 ps
CPU time 1.03 seconds
Started Jul 29 06:10:15 PM PDT 24
Finished Jul 29 06:10:16 PM PDT 24
Peak memory 207264 kb
Host smart-c9d469e7-702e-44a6-9166-3f6039373f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11318
13158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1131813158
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.3074453214
Short name T1618
Test name
Test status
Simulation time 236516003 ps
CPU time 0.99 seconds
Started Jul 29 06:10:34 PM PDT 24
Finished Jul 29 06:10:35 PM PDT 24
Peak memory 207100 kb
Host smart-88870824-b5e9-4d70-bfb0-6b4299bb8692
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3074453214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.3074453214
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1132283659
Short name T2360
Test name
Test status
Simulation time 256323769 ps
CPU time 1.06 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:10:29 PM PDT 24
Peak memory 207076 kb
Host smart-07deeabe-4a15-4102-8ac2-6e85bbc45fe1
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1132283659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.1132283659
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3688710598
Short name T1018
Test name
Test status
Simulation time 134932662 ps
CPU time 0.83 seconds
Started Jul 29 06:10:27 PM PDT 24
Finished Jul 29 06:10:28 PM PDT 24
Peak memory 206984 kb
Host smart-ca58c9ba-c760-44f3-b917-32c31d711df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36887
10598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3688710598
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2079038489
Short name T39
Test name
Test status
Simulation time 34547955 ps
CPU time 0.7 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:10:29 PM PDT 24
Peak memory 206968 kb
Host smart-6fdcb92f-78d1-4e13-a4f0-bd3371740d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20790
38489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2079038489
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.4063574617
Short name T2177
Test name
Test status
Simulation time 16780219191 ps
CPU time 46.05 seconds
Started Jul 29 06:10:31 PM PDT 24
Finished Jul 29 06:11:17 PM PDT 24
Peak memory 215660 kb
Host smart-96ff6945-d38c-4fc0-ae0f-f3e829b6b49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40635
74617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.4063574617
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2930361208
Short name T2290
Test name
Test status
Simulation time 181188602 ps
CPU time 0.93 seconds
Started Jul 29 06:10:31 PM PDT 24
Finished Jul 29 06:10:32 PM PDT 24
Peak memory 207000 kb
Host smart-c2c6968d-daa2-4731-a223-bc85fe281e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29303
61208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2930361208
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1580041831
Short name T1161
Test name
Test status
Simulation time 216628111 ps
CPU time 0.95 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:10:29 PM PDT 24
Peak memory 207072 kb
Host smart-67cdafc9-b1cd-4bdc-9cb9-d4c2dc2b3a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15800
41831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1580041831
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2434202413
Short name T41
Test name
Test status
Simulation time 9886942973 ps
CPU time 72.99 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:11:41 PM PDT 24
Peak memory 219092 kb
Host smart-1cb6068c-009d-4036-a34f-8ce441c17041
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434202413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2434202413
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1409834333
Short name T2469
Test name
Test status
Simulation time 11842011539 ps
CPU time 236.73 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:14:25 PM PDT 24
Peak memory 215780 kb
Host smart-6de35519-c152-4949-8ba0-d619bbd1e74e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409834333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1409834333
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3984165169
Short name T609
Test name
Test status
Simulation time 195051354 ps
CPU time 0.97 seconds
Started Jul 29 06:10:29 PM PDT 24
Finished Jul 29 06:10:30 PM PDT 24
Peak memory 207040 kb
Host smart-b395e9d2-5a5d-44c1-8edc-bc27c56406d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39841
65169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3984165169
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.204465920
Short name T213
Test name
Test status
Simulation time 187970430 ps
CPU time 0.95 seconds
Started Jul 29 06:10:31 PM PDT 24
Finished Jul 29 06:10:32 PM PDT 24
Peak memory 207052 kb
Host smart-78326d0b-f16e-4d26-9a75-a38f3d0e8915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20446
5920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.204465920
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.3746340638
Short name T1792
Test name
Test status
Simulation time 192883079 ps
CPU time 0.9 seconds
Started Jul 29 06:10:30 PM PDT 24
Finished Jul 29 06:10:31 PM PDT 24
Peak memory 207000 kb
Host smart-7fb9f050-113f-44a3-9d0e-368a0d3da7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37463
40638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.3746340638
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.932954905
Short name T210
Test name
Test status
Simulation time 403689211 ps
CPU time 1.22 seconds
Started Jul 29 06:10:31 PM PDT 24
Finished Jul 29 06:10:33 PM PDT 24
Peak memory 223148 kb
Host smart-69aa08da-72ec-425c-b1cd-3d2822432472
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=932954905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.932954905
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1603621127
Short name T61
Test name
Test status
Simulation time 426402286 ps
CPU time 1.44 seconds
Started Jul 29 06:10:29 PM PDT 24
Finished Jul 29 06:10:31 PM PDT 24
Peak memory 207048 kb
Host smart-3c453c97-ed91-4717-872a-25cc2eee9482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16036
21127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1603621127
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.2420515226
Short name T155
Test name
Test status
Simulation time 190175191 ps
CPU time 0.92 seconds
Started Jul 29 06:10:30 PM PDT 24
Finished Jul 29 06:10:31 PM PDT 24
Peak memory 207076 kb
Host smart-b3346750-5e09-4446-b1ba-4974200f5ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24205
15226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.2420515226
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1161803098
Short name T710
Test name
Test status
Simulation time 163522309 ps
CPU time 0.84 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:10:29 PM PDT 24
Peak memory 207100 kb
Host smart-1a747214-0871-40fa-8348-db71e1f39124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11618
03098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1161803098
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.4096603478
Short name T2305
Test name
Test status
Simulation time 145265634 ps
CPU time 0.82 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:10:29 PM PDT 24
Peak memory 207060 kb
Host smart-88011d44-ac55-4a05-b7c1-b70f4b41eafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40966
03478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.4096603478
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.62770027
Short name T2281
Test name
Test status
Simulation time 230816735 ps
CPU time 0.98 seconds
Started Jul 29 06:10:30 PM PDT 24
Finished Jul 29 06:10:31 PM PDT 24
Peak memory 207068 kb
Host smart-3c4ccd8b-b990-4b65-8622-cc5f2f9000d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62770
027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.62770027
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.2859848022
Short name T743
Test name
Test status
Simulation time 6300872538 ps
CPU time 67.1 seconds
Started Jul 29 06:10:33 PM PDT 24
Finished Jul 29 06:11:40 PM PDT 24
Peak memory 217092 kb
Host smart-e7c2e02b-675d-45d9-9883-11a8c67c0b93
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2859848022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.2859848022
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1971336795
Short name T2189
Test name
Test status
Simulation time 794488303 ps
CPU time 2.36 seconds
Started Jul 29 06:10:30 PM PDT 24
Finished Jul 29 06:10:32 PM PDT 24
Peak memory 207072 kb
Host smart-db186028-2483-4940-80c4-042c50a08094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19713
36795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1971336795
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.2418722616
Short name T791
Test name
Test status
Simulation time 4912078694 ps
CPU time 137.27 seconds
Started Jul 29 06:10:31 PM PDT 24
Finished Jul 29 06:12:49 PM PDT 24
Peak memory 215584 kb
Host smart-bca1cd0b-7087-407e-8adb-3500a9f42f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24187
22616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.2418722616
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.715751033
Short name T1394
Test name
Test status
Simulation time 4258832319 ps
CPU time 28.97 seconds
Started Jul 29 06:10:07 PM PDT 24
Finished Jul 29 06:10:36 PM PDT 24
Peak memory 207316 kb
Host smart-a5941b00-cfb6-46d2-9395-7ec2dd70fc60
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715751033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host_
handshake.715751033
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.277519530
Short name T1033
Test name
Test status
Simulation time 60510017 ps
CPU time 0.7 seconds
Started Jul 29 06:10:48 PM PDT 24
Finished Jul 29 06:10:49 PM PDT 24
Peak memory 207120 kb
Host smart-d62e9599-9048-45bd-b1d0-db43887bfa4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=277519530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.277519530
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1621775002
Short name T2438
Test name
Test status
Simulation time 3731391687 ps
CPU time 5.47 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:10:33 PM PDT 24
Peak memory 207336 kb
Host smart-5ce1afa3-7766-4329-9d22-1c631ff0d4f5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621775002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.1621775002
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3822808908
Short name T2727
Test name
Test status
Simulation time 13346131707 ps
CPU time 14.11 seconds
Started Jul 29 06:10:30 PM PDT 24
Finished Jul 29 06:10:44 PM PDT 24
Peak memory 207444 kb
Host smart-40b09183-85fc-4d9e-be92-4c06fea40a5f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822808908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3822808908
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1174877218
Short name T537
Test name
Test status
Simulation time 23363741687 ps
CPU time 29.06 seconds
Started Jul 29 06:10:33 PM PDT 24
Finished Jul 29 06:11:03 PM PDT 24
Peak memory 207396 kb
Host smart-9812b5b6-a370-40d8-96ac-9a4daa1630d0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174877218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.1174877218
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2670847948
Short name T827
Test name
Test status
Simulation time 184216616 ps
CPU time 0.88 seconds
Started Jul 29 06:10:29 PM PDT 24
Finished Jul 29 06:10:30 PM PDT 24
Peak memory 207124 kb
Host smart-1f4cc454-23d6-42ea-a56e-6c045de2b906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26708
47948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2670847948
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.685701236
Short name T62
Test name
Test status
Simulation time 151589305 ps
CPU time 0.87 seconds
Started Jul 29 06:10:28 PM PDT 24
Finished Jul 29 06:10:29 PM PDT 24
Peak memory 207100 kb
Host smart-367f4629-1ced-4c73-9c5d-aa5a90460b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68570
1236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.685701236
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.3772124329
Short name T67
Test name
Test status
Simulation time 146739122 ps
CPU time 0.82 seconds
Started Jul 29 06:10:32 PM PDT 24
Finished Jul 29 06:10:33 PM PDT 24
Peak memory 207084 kb
Host smart-ba876614-9b17-4895-b563-5078b20bcc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37721
24329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.3772124329
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.3692304437
Short name T2410
Test name
Test status
Simulation time 137486298 ps
CPU time 0.87 seconds
Started Jul 29 06:10:30 PM PDT 24
Finished Jul 29 06:10:31 PM PDT 24
Peak memory 207068 kb
Host smart-19fc134e-9589-4bf6-ae41-685dd2bc5265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36923
04437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.3692304437
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.285553590
Short name T2240
Test name
Test status
Simulation time 191410372 ps
CPU time 0.93 seconds
Started Jul 29 06:10:30 PM PDT 24
Finished Jul 29 06:10:31 PM PDT 24
Peak memory 206944 kb
Host smart-862d6a21-2f7a-4ec4-a013-927a8b66b08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28555
3590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.285553590
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.3130378580
Short name T2154
Test name
Test status
Simulation time 1433638743 ps
CPU time 3.39 seconds
Started Jul 29 06:10:32 PM PDT 24
Finished Jul 29 06:10:35 PM PDT 24
Peak memory 207320 kb
Host smart-13a12e2c-98c1-4655-86ae-3566355db0af
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3130378580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.3130378580
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2919998170
Short name T2504
Test name
Test status
Simulation time 7206977056 ps
CPU time 17.25 seconds
Started Jul 29 06:10:34 PM PDT 24
Finished Jul 29 06:10:51 PM PDT 24
Peak memory 207424 kb
Host smart-cf6d1fa9-b191-4c02-8d17-48459460c4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29199
98170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2919998170
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.4068192396
Short name T2537
Test name
Test status
Simulation time 4270517434 ps
CPU time 29.16 seconds
Started Jul 29 06:10:30 PM PDT 24
Finished Jul 29 06:10:59 PM PDT 24
Peak memory 207320 kb
Host smart-324af1f9-3bc4-45e1-9f01-420da4f784d8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068192396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.4068192396
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.69142563
Short name T1468
Test name
Test status
Simulation time 320193053 ps
CPU time 1.24 seconds
Started Jul 29 06:10:29 PM PDT 24
Finished Jul 29 06:10:30 PM PDT 24
Peak memory 207084 kb
Host smart-fb1f6c20-ffb6-4cb6-b489-cdfafd1b5b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69142
563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.69142563
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.2803094584
Short name T2463
Test name
Test status
Simulation time 143232455 ps
CPU time 0.83 seconds
Started Jul 29 06:10:30 PM PDT 24
Finished Jul 29 06:10:31 PM PDT 24
Peak memory 207032 kb
Host smart-b9cb6158-76b1-4442-b21b-14bfd5299f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28030
94584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2803094584
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.601622989
Short name T930
Test name
Test status
Simulation time 44165494 ps
CPU time 0.72 seconds
Started Jul 29 06:10:33 PM PDT 24
Finished Jul 29 06:10:34 PM PDT 24
Peak memory 207040 kb
Host smart-b85e170e-7bc2-458a-81d2-1336dfed72d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60162
2989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.601622989
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.4081866845
Short name T471
Test name
Test status
Simulation time 766281237 ps
CPU time 2.11 seconds
Started Jul 29 06:10:35 PM PDT 24
Finished Jul 29 06:10:37 PM PDT 24
Peak memory 207280 kb
Host smart-0964b664-4952-41e4-9bd5-41ea08e96573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40818
66845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.4081866845
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.4016680815
Short name T486
Test name
Test status
Simulation time 204327577 ps
CPU time 2.47 seconds
Started Jul 29 06:10:38 PM PDT 24
Finished Jul 29 06:10:41 PM PDT 24
Peak memory 207300 kb
Host smart-46129393-711d-4566-aa13-db615e51b7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40166
80815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.4016680815
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.3450497273
Short name T2753
Test name
Test status
Simulation time 89338025936 ps
CPU time 131.88 seconds
Started Jul 29 06:10:33 PM PDT 24
Finished Jul 29 06:12:45 PM PDT 24
Peak memory 207564 kb
Host smart-4f33b610-367f-4bbb-b1a6-81425184f480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450497273 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.3450497273
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.2500446629
Short name T1381
Test name
Test status
Simulation time 88120559168 ps
CPU time 137.95 seconds
Started Jul 29 06:10:34 PM PDT 24
Finished Jul 29 06:12:53 PM PDT 24
Peak memory 207416 kb
Host smart-6254359b-bd21-40e0-87fc-eba4b3ec5389
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2500446629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.2500446629
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.14642964
Short name T1115
Test name
Test status
Simulation time 90144237047 ps
CPU time 148.76 seconds
Started Jul 29 06:10:35 PM PDT 24
Finished Jul 29 06:13:04 PM PDT 24
Peak memory 207408 kb
Host smart-fce8c226-a5a8-40fd-831d-4e74a71a7bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14642964 -assert nop
ostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.14642964
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.2260547893
Short name T1783
Test name
Test status
Simulation time 94177378240 ps
CPU time 137.19 seconds
Started Jul 29 06:10:36 PM PDT 24
Finished Jul 29 06:12:53 PM PDT 24
Peak memory 207408 kb
Host smart-8cf2a545-54fe-4b8d-881b-e98ef8abc7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22605
47893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.2260547893
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3503426272
Short name T941
Test name
Test status
Simulation time 248221030 ps
CPU time 1.05 seconds
Started Jul 29 06:10:34 PM PDT 24
Finished Jul 29 06:10:35 PM PDT 24
Peak memory 207260 kb
Host smart-5da80038-0e79-4c2e-8663-c178838d7611
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3503426272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3503426272
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.512437622
Short name T929
Test name
Test status
Simulation time 148084600 ps
CPU time 0.87 seconds
Started Jul 29 06:10:37 PM PDT 24
Finished Jul 29 06:10:38 PM PDT 24
Peak memory 207032 kb
Host smart-bb288f3b-95e0-48bd-8daa-e784b9918d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51243
7622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.512437622
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2996315044
Short name T2099
Test name
Test status
Simulation time 277324493 ps
CPU time 1.03 seconds
Started Jul 29 06:10:33 PM PDT 24
Finished Jul 29 06:10:34 PM PDT 24
Peak memory 207072 kb
Host smart-0ad3aa55-ef9d-4e99-8c59-a21dcd7c7b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29963
15044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2996315044
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.558151546
Short name T1666
Test name
Test status
Simulation time 7822830226 ps
CPU time 57.35 seconds
Started Jul 29 06:10:37 PM PDT 24
Finished Jul 29 06:11:34 PM PDT 24
Peak memory 207456 kb
Host smart-823d01fc-cc4b-4a43-b98d-2af94abf94ec
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=558151546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.558151546
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.1491310128
Short name T500
Test name
Test status
Simulation time 13328982394 ps
CPU time 90.38 seconds
Started Jul 29 06:10:36 PM PDT 24
Finished Jul 29 06:12:06 PM PDT 24
Peak memory 207356 kb
Host smart-1389dd6f-a932-4c28-b24b-9a8e3a2b85aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1491310128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.1491310128
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3271312863
Short name T1257
Test name
Test status
Simulation time 206437981 ps
CPU time 0.91 seconds
Started Jul 29 06:10:34 PM PDT 24
Finished Jul 29 06:10:36 PM PDT 24
Peak memory 207100 kb
Host smart-6d3a264b-dbdd-4545-a8fe-189de8f8cc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32713
12863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3271312863
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.2486638026
Short name T2038
Test name
Test status
Simulation time 23286125299 ps
CPU time 30.73 seconds
Started Jul 29 06:10:33 PM PDT 24
Finished Jul 29 06:11:04 PM PDT 24
Peak memory 207404 kb
Host smart-8a5b9eef-c88d-4887-b77c-f9c021290991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24866
38026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.2486638026
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1711628552
Short name T1629
Test name
Test status
Simulation time 3317171113 ps
CPU time 5.09 seconds
Started Jul 29 06:10:35 PM PDT 24
Finished Jul 29 06:10:40 PM PDT 24
Peak memory 207248 kb
Host smart-b87b1584-29fd-4ae4-a057-e58351a892a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17116
28552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1711628552
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.667574813
Short name T474
Test name
Test status
Simulation time 9465198090 ps
CPU time 73.98 seconds
Started Jul 29 06:10:36 PM PDT 24
Finished Jul 29 06:11:50 PM PDT 24
Peak memory 223808 kb
Host smart-e107942d-06f3-489c-a045-2ac6eb33ea3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66757
4813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.667574813
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.4078690416
Short name T1086
Test name
Test status
Simulation time 6512020964 ps
CPU time 65.63 seconds
Started Jul 29 06:10:34 PM PDT 24
Finished Jul 29 06:11:39 PM PDT 24
Peak memory 207508 kb
Host smart-117d3c14-2af4-4cdc-887b-0649a87a4357
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4078690416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.4078690416
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.3285549613
Short name T856
Test name
Test status
Simulation time 288282653 ps
CPU time 1.04 seconds
Started Jul 29 06:10:33 PM PDT 24
Finished Jul 29 06:10:34 PM PDT 24
Peak memory 207108 kb
Host smart-3d4dc99a-5b48-47ad-88cb-0ae701c7d5f3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3285549613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3285549613
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.351213840
Short name T493
Test name
Test status
Simulation time 201377677 ps
CPU time 0.94 seconds
Started Jul 29 06:10:41 PM PDT 24
Finished Jul 29 06:10:42 PM PDT 24
Peak memory 207072 kb
Host smart-fdcd3d57-343b-44de-ace1-377daa5a93f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35121
3840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.351213840
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.4025860444
Short name T233
Test name
Test status
Simulation time 4995021335 ps
CPU time 39.77 seconds
Started Jul 29 06:10:41 PM PDT 24
Finished Jul 29 06:11:21 PM PDT 24
Peak memory 207392 kb
Host smart-13cd3e5a-da6f-400c-9288-c6ccf49ff81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40258
60444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.4025860444
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2159069741
Short name T2155
Test name
Test status
Simulation time 5430346095 ps
CPU time 58.04 seconds
Started Jul 29 06:10:40 PM PDT 24
Finished Jul 29 06:11:38 PM PDT 24
Peak memory 217052 kb
Host smart-00c19499-363b-4e36-b93a-eaf4d17f1f8d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2159069741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2159069741
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.151024859
Short name T1818
Test name
Test status
Simulation time 154572024 ps
CPU time 0.93 seconds
Started Jul 29 06:10:42 PM PDT 24
Finished Jul 29 06:10:43 PM PDT 24
Peak memory 207096 kb
Host smart-0dd22a6b-3266-4dea-8220-2447df45f95d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=151024859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.151024859
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.840446112
Short name T2451
Test name
Test status
Simulation time 151329521 ps
CPU time 0.85 seconds
Started Jul 29 06:10:40 PM PDT 24
Finished Jul 29 06:10:41 PM PDT 24
Peak memory 207036 kb
Host smart-5d7e3087-1cc5-43a8-8cbe-7d647b5760ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84044
6112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.840446112
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1545374519
Short name T1248
Test name
Test status
Simulation time 205902832 ps
CPU time 0.95 seconds
Started Jul 29 06:10:43 PM PDT 24
Finished Jul 29 06:10:44 PM PDT 24
Peak memory 207132 kb
Host smart-a5b67233-2ae4-4b1a-930f-ca8f79d2bc45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15453
74519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1545374519
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2458833231
Short name T2208
Test name
Test status
Simulation time 160767200 ps
CPU time 0.89 seconds
Started Jul 29 06:10:42 PM PDT 24
Finished Jul 29 06:10:43 PM PDT 24
Peak memory 207072 kb
Host smart-f027e5e4-e721-4fb7-9b8e-f1973ea6741d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24588
33231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2458833231
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3541528599
Short name T902
Test name
Test status
Simulation time 176260680 ps
CPU time 0.87 seconds
Started Jul 29 06:10:41 PM PDT 24
Finished Jul 29 06:10:42 PM PDT 24
Peak memory 207116 kb
Host smart-b0ec7bf6-8769-4e96-b193-9894fc9973cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35415
28599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3541528599
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1305781622
Short name T1224
Test name
Test status
Simulation time 153136959 ps
CPU time 0.88 seconds
Started Jul 29 06:10:40 PM PDT 24
Finished Jul 29 06:10:41 PM PDT 24
Peak memory 207100 kb
Host smart-d8769e11-6c1e-4c32-8ce9-715a37a7aabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13057
81622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1305781622
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.3726149679
Short name T807
Test name
Test status
Simulation time 220798846 ps
CPU time 0.99 seconds
Started Jul 29 06:10:44 PM PDT 24
Finished Jul 29 06:10:45 PM PDT 24
Peak memory 207116 kb
Host smart-bb1bc129-dfa4-41af-9cfe-88a7787fd200
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3726149679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3726149679
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.2371256971
Short name T524
Test name
Test status
Simulation time 284438975 ps
CPU time 1.06 seconds
Started Jul 29 06:10:40 PM PDT 24
Finished Jul 29 06:10:41 PM PDT 24
Peak memory 207048 kb
Host smart-9156a2be-1b6c-4874-a15e-6eea2096178e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23712
56971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.2371256971
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.2402016346
Short name T708
Test name
Test status
Simulation time 115941896 ps
CPU time 0.75 seconds
Started Jul 29 06:10:40 PM PDT 24
Finished Jul 29 06:10:41 PM PDT 24
Peak memory 207080 kb
Host smart-df82ce7a-2d3a-45ab-8fc9-c113adb4a9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24020
16346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.2402016346
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1467206894
Short name T1782
Test name
Test status
Simulation time 16485619613 ps
CPU time 43.55 seconds
Started Jul 29 06:10:43 PM PDT 24
Finished Jul 29 06:11:27 PM PDT 24
Peak memory 215592 kb
Host smart-df6100a2-589f-4f54-ab70-84f1cc42e65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14672
06894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1467206894
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2847994495
Short name T1573
Test name
Test status
Simulation time 186873601 ps
CPU time 0.91 seconds
Started Jul 29 06:10:43 PM PDT 24
Finished Jul 29 06:10:45 PM PDT 24
Peak memory 207136 kb
Host smart-bbf22235-408d-40e5-bc47-7aec883f0758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28479
94495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2847994495
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1771777753
Short name T2505
Test name
Test status
Simulation time 239526399 ps
CPU time 0.96 seconds
Started Jul 29 06:10:43 PM PDT 24
Finished Jul 29 06:10:44 PM PDT 24
Peak memory 207036 kb
Host smart-1210ce10-0dde-4b58-9840-229c9309ff37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17717
77753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1771777753
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2141337000
Short name T178
Test name
Test status
Simulation time 6584364421 ps
CPU time 166.86 seconds
Started Jul 29 06:10:40 PM PDT 24
Finished Jul 29 06:13:27 PM PDT 24
Peak memory 215536 kb
Host smart-80a1ddff-bf86-4099-b739-a61f648734e3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141337000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2141337000
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.3661740646
Short name T1696
Test name
Test status
Simulation time 9301255226 ps
CPU time 85 seconds
Started Jul 29 06:10:43 PM PDT 24
Finished Jul 29 06:12:08 PM PDT 24
Peak memory 223788 kb
Host smart-bedeef3e-4b5e-4bfa-8327-caf29d55b41c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3661740646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.3661740646
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3397136238
Short name T2595
Test name
Test status
Simulation time 11995749636 ps
CPU time 87.82 seconds
Started Jul 29 06:10:42 PM PDT 24
Finished Jul 29 06:12:10 PM PDT 24
Peak memory 223748 kb
Host smart-de05cf32-5b0d-4bda-85c1-2686288a8d76
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397136238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3397136238
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.2224886508
Short name T410
Test name
Test status
Simulation time 197913097 ps
CPU time 0.94 seconds
Started Jul 29 06:10:43 PM PDT 24
Finished Jul 29 06:10:44 PM PDT 24
Peak memory 207076 kb
Host smart-d01911b2-4014-4d21-b72d-95dc90e5ca44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22248
86508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.2224886508
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.3574711531
Short name T1456
Test name
Test status
Simulation time 195261569 ps
CPU time 0.9 seconds
Started Jul 29 06:10:42 PM PDT 24
Finished Jul 29 06:10:43 PM PDT 24
Peak memory 207100 kb
Host smart-b8abae68-9087-4e8a-a720-692ea85195bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35747
11531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.3574711531
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.96769513
Short name T1536
Test name
Test status
Simulation time 227709553 ps
CPU time 0.94 seconds
Started Jul 29 06:10:40 PM PDT 24
Finished Jul 29 06:10:41 PM PDT 24
Peak memory 207272 kb
Host smart-10b967ac-6345-43b7-afe9-2a8a6397e914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96769
513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.96769513
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.3710056487
Short name T82
Test name
Test status
Simulation time 187702970 ps
CPU time 0.91 seconds
Started Jul 29 06:10:41 PM PDT 24
Finished Jul 29 06:10:42 PM PDT 24
Peak memory 207136 kb
Host smart-10415cc7-50b2-4c98-a672-a2e25c433aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37100
56487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.3710056487
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.546613458
Short name T193
Test name
Test status
Simulation time 549449364 ps
CPU time 1.42 seconds
Started Jul 29 06:10:48 PM PDT 24
Finished Jul 29 06:10:49 PM PDT 24
Peak memory 224028 kb
Host smart-27b2f57b-f32e-40ab-9d4a-4e1894815081
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=546613458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.546613458
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.788032641
Short name T1865
Test name
Test status
Simulation time 430045760 ps
CPU time 1.45 seconds
Started Jul 29 06:10:40 PM PDT 24
Finished Jul 29 06:10:42 PM PDT 24
Peak memory 207092 kb
Host smart-d21e2abb-e6b3-408e-9ac5-4c02a6074913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78803
2641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.788032641
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.3312473235
Short name T174
Test name
Test status
Simulation time 309735422 ps
CPU time 1.13 seconds
Started Jul 29 06:10:43 PM PDT 24
Finished Jul 29 06:10:44 PM PDT 24
Peak memory 207136 kb
Host smart-177978ca-d50d-4fde-901e-5b9e1c5dd83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33124
73235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.3312473235
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.1687831580
Short name T1875
Test name
Test status
Simulation time 152038301 ps
CPU time 0.84 seconds
Started Jul 29 06:10:39 PM PDT 24
Finished Jul 29 06:10:40 PM PDT 24
Peak memory 207048 kb
Host smart-fd5f7dac-4dbe-46a8-a0fc-2f9003fd1f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16878
31580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1687831580
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3362737924
Short name T1163
Test name
Test status
Simulation time 155159799 ps
CPU time 0.86 seconds
Started Jul 29 06:10:41 PM PDT 24
Finished Jul 29 06:10:42 PM PDT 24
Peak memory 207112 kb
Host smart-fd8932e4-133f-403c-a74c-c0c58072fd6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33627
37924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3362737924
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3741664947
Short name T2814
Test name
Test status
Simulation time 218838143 ps
CPU time 1.05 seconds
Started Jul 29 06:10:40 PM PDT 24
Finished Jul 29 06:10:41 PM PDT 24
Peak memory 207072 kb
Host smart-41a9cb83-32a4-4c5a-a4b5-4b9e6a8f710c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37416
64947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3741664947
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2604712270
Short name T1687
Test name
Test status
Simulation time 7465822506 ps
CPU time 210.61 seconds
Started Jul 29 06:10:48 PM PDT 24
Finished Jul 29 06:14:18 PM PDT 24
Peak memory 215580 kb
Host smart-c169d1c0-aa53-476a-b81d-38a468ce7dcc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2604712270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2604712270
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1687711486
Short name T274
Test name
Test status
Simulation time 239754649 ps
CPU time 1 seconds
Started Jul 29 06:10:46 PM PDT 24
Finished Jul 29 06:10:47 PM PDT 24
Peak memory 207184 kb
Host smart-59367849-5fd4-40fe-9a53-480bda317646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16877
11486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1687711486
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3079416052
Short name T2630
Test name
Test status
Simulation time 169440629 ps
CPU time 0.9 seconds
Started Jul 29 06:10:46 PM PDT 24
Finished Jul 29 06:10:47 PM PDT 24
Peak memory 207000 kb
Host smart-2f0f9ab2-27de-4487-8e46-032dd3aafdc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30794
16052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3079416052
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.132824655
Short name T593
Test name
Test status
Simulation time 879437961 ps
CPU time 2.32 seconds
Started Jul 29 06:10:46 PM PDT 24
Finished Jul 29 06:10:48 PM PDT 24
Peak memory 207336 kb
Host smart-5f2bad58-5188-427b-98cd-a86947ab0c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13282
4655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.132824655
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.19069290
Short name T1677
Test name
Test status
Simulation time 5235066811 ps
CPU time 162.5 seconds
Started Jul 29 06:10:49 PM PDT 24
Finished Jul 29 06:13:31 PM PDT 24
Peak memory 215616 kb
Host smart-e3feaf1c-86fe-4f55-a2dd-e446b9be8554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19069
290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.19069290
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.2910924103
Short name T1140
Test name
Test status
Simulation time 303043162 ps
CPU time 4.45 seconds
Started Jul 29 06:10:33 PM PDT 24
Finished Jul 29 06:10:37 PM PDT 24
Peak memory 207276 kb
Host smart-4c49d9b7-8bcf-4ea3-9385-4a7c42e12908
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910924103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.2910924103
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1584947652
Short name T2413
Test name
Test status
Simulation time 3654285847 ps
CPU time 5.49 seconds
Started Jul 29 06:12:54 PM PDT 24
Finished Jul 29 06:13:00 PM PDT 24
Peak memory 207400 kb
Host smart-8bc4d2ec-a7ad-487f-96de-4f1147b34d1f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584947652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.1584947652
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.84099842
Short name T2091
Test name
Test status
Simulation time 13356941131 ps
CPU time 17.28 seconds
Started Jul 29 06:12:56 PM PDT 24
Finished Jul 29 06:13:13 PM PDT 24
Peak memory 207360 kb
Host smart-072e5cfa-b66b-42c4-9432-3db3b4e90ad3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=84099842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.84099842
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1817032648
Short name T725
Test name
Test status
Simulation time 23332213485 ps
CPU time 28.06 seconds
Started Jul 29 06:12:57 PM PDT 24
Finished Jul 29 06:13:26 PM PDT 24
Peak memory 207404 kb
Host smart-71757364-6776-4eca-a0df-edcb3197611d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817032648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.1817032648
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3680299149
Short name T1182
Test name
Test status
Simulation time 151400247 ps
CPU time 0.87 seconds
Started Jul 29 06:12:57 PM PDT 24
Finished Jul 29 06:12:58 PM PDT 24
Peak memory 207072 kb
Host smart-b0283ee3-bdd8-49ce-8d36-95e2b2cbc1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36802
99149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3680299149
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.17473416
Short name T1048
Test name
Test status
Simulation time 138046991 ps
CPU time 0.82 seconds
Started Jul 29 06:12:55 PM PDT 24
Finished Jul 29 06:12:56 PM PDT 24
Peak memory 207080 kb
Host smart-042f502f-de5b-4b2d-99b6-08a70a81510b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17473
416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.17473416
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.1554486115
Short name T311
Test name
Test status
Simulation time 202159739 ps
CPU time 1.01 seconds
Started Jul 29 06:13:01 PM PDT 24
Finished Jul 29 06:13:02 PM PDT 24
Peak memory 207016 kb
Host smart-32de1a9a-8c1e-4b5f-97a1-0f521d617617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15544
86115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.1554486115
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1347662005
Short name T1708
Test name
Test status
Simulation time 1759795311 ps
CPU time 3.9 seconds
Started Jul 29 06:12:59 PM PDT 24
Finished Jul 29 06:13:03 PM PDT 24
Peak memory 207312 kb
Host smart-5589db60-ba1a-4c35-8b18-31411b481212
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1347662005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1347662005
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.348672716
Short name T1854
Test name
Test status
Simulation time 15706853096 ps
CPU time 38.52 seconds
Started Jul 29 06:12:59 PM PDT 24
Finished Jul 29 06:13:38 PM PDT 24
Peak memory 207384 kb
Host smart-82b38546-da7d-4619-bc92-10060953f9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34867
2716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.348672716
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.2088792705
Short name T29
Test name
Test status
Simulation time 588018953 ps
CPU time 11.83 seconds
Started Jul 29 06:13:02 PM PDT 24
Finished Jul 29 06:13:14 PM PDT 24
Peak memory 207236 kb
Host smart-05bfea8c-e79f-44d1-a622-ab89ab6a700e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088792705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.2088792705
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.4024408544
Short name T1104
Test name
Test status
Simulation time 485204237 ps
CPU time 1.55 seconds
Started Jul 29 06:13:04 PM PDT 24
Finished Jul 29 06:13:06 PM PDT 24
Peak memory 207060 kb
Host smart-5fa3837f-7e83-4faa-9b8a-8dd81e026682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40244
08544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.4024408544
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3329650483
Short name T901
Test name
Test status
Simulation time 186425993 ps
CPU time 0.84 seconds
Started Jul 29 06:13:01 PM PDT 24
Finished Jul 29 06:13:02 PM PDT 24
Peak memory 207080 kb
Host smart-ea6df49b-a59d-4bf8-a0d7-944327553dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33296
50483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3329650483
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3237539297
Short name T1712
Test name
Test status
Simulation time 96067221 ps
CPU time 0.77 seconds
Started Jul 29 06:13:03 PM PDT 24
Finished Jul 29 06:13:04 PM PDT 24
Peak memory 207064 kb
Host smart-123285d2-d211-42cb-9e34-02b8e901fda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32375
39297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3237539297
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.1660266509
Short name T383
Test name
Test status
Simulation time 1017318315 ps
CPU time 2.66 seconds
Started Jul 29 06:13:00 PM PDT 24
Finished Jul 29 06:13:03 PM PDT 24
Peak memory 207312 kb
Host smart-f952a378-a8ea-436b-9164-f3b05eb4c07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16602
66509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.1660266509
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3289222209
Short name T2307
Test name
Test status
Simulation time 191940600 ps
CPU time 1.8 seconds
Started Jul 29 06:13:02 PM PDT 24
Finished Jul 29 06:13:04 PM PDT 24
Peak memory 207296 kb
Host smart-4e4ff51a-e876-47a3-a7ba-b414f58987de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32892
22209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3289222209
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3931140544
Short name T318
Test name
Test status
Simulation time 218358858 ps
CPU time 1.18 seconds
Started Jul 29 06:13:02 PM PDT 24
Finished Jul 29 06:13:03 PM PDT 24
Peak memory 207260 kb
Host smart-172270fb-ffe4-493a-8dfa-fa82eb8c7876
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3931140544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3931140544
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1256954589
Short name T1099
Test name
Test status
Simulation time 144426452 ps
CPU time 0.83 seconds
Started Jul 29 06:13:01 PM PDT 24
Finished Jul 29 06:13:02 PM PDT 24
Peak memory 207068 kb
Host smart-bf0e6afc-b12b-4bf0-a8f7-e382afee1b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12569
54589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1256954589
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.969600747
Short name T2373
Test name
Test status
Simulation time 237713435 ps
CPU time 0.95 seconds
Started Jul 29 06:13:00 PM PDT 24
Finished Jul 29 06:13:01 PM PDT 24
Peak memory 207040 kb
Host smart-7b3ad15a-32f4-4fd3-a4b3-6700088d6a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96960
0747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.969600747
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.2265980753
Short name T1962
Test name
Test status
Simulation time 7857001752 ps
CPU time 60.36 seconds
Started Jul 29 06:13:02 PM PDT 24
Finished Jul 29 06:14:03 PM PDT 24
Peak memory 215588 kb
Host smart-5fa243ee-b523-4534-86e2-1ac5c00276b1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2265980753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.2265980753
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.2966720649
Short name T1524
Test name
Test status
Simulation time 12129634949 ps
CPU time 94.52 seconds
Started Jul 29 06:13:02 PM PDT 24
Finished Jul 29 06:14:37 PM PDT 24
Peak memory 207356 kb
Host smart-9f60c130-38dd-4b39-ab55-e6a4176676d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2966720649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.2966720649
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.445576012
Short name T2565
Test name
Test status
Simulation time 163728836 ps
CPU time 0.86 seconds
Started Jul 29 06:13:04 PM PDT 24
Finished Jul 29 06:13:05 PM PDT 24
Peak memory 207104 kb
Host smart-1c2effb5-0538-47e8-ae16-83161951a0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44557
6012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.445576012
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.409141481
Short name T582
Test name
Test status
Simulation time 23307087302 ps
CPU time 27.67 seconds
Started Jul 29 06:13:00 PM PDT 24
Finished Jul 29 06:13:28 PM PDT 24
Peak memory 207416 kb
Host smart-72e86591-10c2-41e3-a007-554c2c835c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40914
1481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.409141481
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1003093874
Short name T1710
Test name
Test status
Simulation time 3285664235 ps
CPU time 5.04 seconds
Started Jul 29 06:13:04 PM PDT 24
Finished Jul 29 06:13:09 PM PDT 24
Peak memory 207324 kb
Host smart-bcfed1f8-d185-4921-a189-b21e02c5937a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10030
93874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1003093874
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.490046853
Short name T1463
Test name
Test status
Simulation time 6327979222 ps
CPU time 49.26 seconds
Started Jul 29 06:13:04 PM PDT 24
Finished Jul 29 06:13:54 PM PDT 24
Peak memory 217696 kb
Host smart-2b7a9f4e-144a-4b5f-ab23-5c4a55467d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49004
6853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.490046853
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.1598863619
Short name T2083
Test name
Test status
Simulation time 5008916329 ps
CPU time 142.15 seconds
Started Jul 29 06:13:03 PM PDT 24
Finished Jul 29 06:15:26 PM PDT 24
Peak memory 215580 kb
Host smart-ceb70b97-e651-470d-849e-d471a62b9572
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1598863619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.1598863619
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2850175657
Short name T2607
Test name
Test status
Simulation time 245318492 ps
CPU time 1.03 seconds
Started Jul 29 06:13:00 PM PDT 24
Finished Jul 29 06:13:01 PM PDT 24
Peak memory 207064 kb
Host smart-1ee5346a-13e3-4ab6-81f4-9c0667efe05a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2850175657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2850175657
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.363155519
Short name T1936
Test name
Test status
Simulation time 234139638 ps
CPU time 0.98 seconds
Started Jul 29 06:12:59 PM PDT 24
Finished Jul 29 06:13:00 PM PDT 24
Peak memory 207084 kb
Host smart-24bc27d3-7242-4c00-b3e5-39f8cb10586d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36315
5519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.363155519
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1577756013
Short name T594
Test name
Test status
Simulation time 5239733131 ps
CPU time 52.05 seconds
Started Jul 29 06:12:59 PM PDT 24
Finished Jul 29 06:13:51 PM PDT 24
Peak memory 207600 kb
Host smart-1a4d89ec-280f-4775-a260-cce317175b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15777
56013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1577756013
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1074842072
Short name T2669
Test name
Test status
Simulation time 5012217313 ps
CPU time 149.58 seconds
Started Jul 29 06:13:03 PM PDT 24
Finished Jul 29 06:15:33 PM PDT 24
Peak memory 215580 kb
Host smart-69579c09-a2cc-430d-93a4-7a7f66b0fcab
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1074842072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1074842072
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.2357901326
Short name T1201
Test name
Test status
Simulation time 203725270 ps
CPU time 0.91 seconds
Started Jul 29 06:13:03 PM PDT 24
Finished Jul 29 06:13:04 PM PDT 24
Peak memory 207124 kb
Host smart-cac092af-13d4-4d52-b6b7-9b4ad429bb72
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2357901326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.2357901326
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2224415306
Short name T570
Test name
Test status
Simulation time 164589051 ps
CPU time 0.89 seconds
Started Jul 29 06:13:01 PM PDT 24
Finished Jul 29 06:13:02 PM PDT 24
Peak memory 207060 kb
Host smart-c348ac41-a10e-4804-8c04-b99bd6aaa9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22244
15306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2224415306
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2766617203
Short name T354
Test name
Test status
Simulation time 158893318 ps
CPU time 0.89 seconds
Started Jul 29 06:13:04 PM PDT 24
Finished Jul 29 06:13:05 PM PDT 24
Peak memory 207088 kb
Host smart-46bab47b-a5bf-4f79-84fb-ec09c0105818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27666
17203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2766617203
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.4284223564
Short name T1828
Test name
Test status
Simulation time 163717299 ps
CPU time 0.86 seconds
Started Jul 29 06:12:59 PM PDT 24
Finished Jul 29 06:13:00 PM PDT 24
Peak memory 207100 kb
Host smart-8dc0116c-c36b-4f10-bc80-26e1fee4ab2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42842
23564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.4284223564
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.4069112395
Short name T2303
Test name
Test status
Simulation time 170349054 ps
CPU time 0.93 seconds
Started Jul 29 06:13:01 PM PDT 24
Finished Jul 29 06:13:02 PM PDT 24
Peak memory 207124 kb
Host smart-0920dd57-ad2e-4776-84f5-412f8276d647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40691
12395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.4069112395
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1919225224
Short name T1835
Test name
Test status
Simulation time 185009820 ps
CPU time 0.87 seconds
Started Jul 29 06:13:07 PM PDT 24
Finished Jul 29 06:13:08 PM PDT 24
Peak memory 207096 kb
Host smart-471c2a18-e8bb-4238-8e6b-69c3efb07b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19192
25224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1919225224
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.1384929324
Short name T1628
Test name
Test status
Simulation time 213722694 ps
CPU time 1.03 seconds
Started Jul 29 06:13:09 PM PDT 24
Finished Jul 29 06:13:11 PM PDT 24
Peak memory 207120 kb
Host smart-30a17451-2d64-4c49-aa0e-a1d90ad8c3aa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1384929324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.1384929324
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3567026743
Short name T1950
Test name
Test status
Simulation time 181209252 ps
CPU time 0.89 seconds
Started Jul 29 06:13:06 PM PDT 24
Finished Jul 29 06:13:07 PM PDT 24
Peak memory 207016 kb
Host smart-ed68e893-b1df-4513-8e5b-4674d247573c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35670
26743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3567026743
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.4232544191
Short name T794
Test name
Test status
Simulation time 78302358 ps
CPU time 0.74 seconds
Started Jul 29 06:13:05 PM PDT 24
Finished Jul 29 06:13:06 PM PDT 24
Peak memory 207108 kb
Host smart-199c2d68-8941-4ed2-83cb-7010a72d58ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42325
44191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.4232544191
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2733892502
Short name T2578
Test name
Test status
Simulation time 11967930874 ps
CPU time 30.62 seconds
Started Jul 29 06:13:07 PM PDT 24
Finished Jul 29 06:13:37 PM PDT 24
Peak memory 215612 kb
Host smart-81adbc17-b89a-41be-a3f6-ca9718083f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27338
92502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2733892502
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2730325188
Short name T2445
Test name
Test status
Simulation time 181726733 ps
CPU time 0.89 seconds
Started Jul 29 06:13:05 PM PDT 24
Finished Jul 29 06:13:06 PM PDT 24
Peak memory 207032 kb
Host smart-a15a2b85-ca86-45c7-a2a2-74109ca546b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27303
25188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2730325188
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2051341024
Short name T331
Test name
Test status
Simulation time 220037531 ps
CPU time 1.02 seconds
Started Jul 29 06:13:08 PM PDT 24
Finished Jul 29 06:13:09 PM PDT 24
Peak memory 207228 kb
Host smart-e59d933b-708d-49bc-b28a-a6f76f990f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20513
41024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2051341024
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.1668809080
Short name T2263
Test name
Test status
Simulation time 172506194 ps
CPU time 0.9 seconds
Started Jul 29 06:13:08 PM PDT 24
Finished Jul 29 06:13:09 PM PDT 24
Peak memory 207080 kb
Host smart-f1b4367f-d0e7-4971-82cd-e924feea08bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16688
09080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1668809080
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.2962969336
Short name T2611
Test name
Test status
Simulation time 193125378 ps
CPU time 0.95 seconds
Started Jul 29 06:13:06 PM PDT 24
Finished Jul 29 06:13:07 PM PDT 24
Peak memory 207128 kb
Host smart-6098fe88-1a55-441f-8390-7c9e3536c81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29629
69336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.2962969336
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.96165350
Short name T1333
Test name
Test status
Simulation time 186124811 ps
CPU time 0.86 seconds
Started Jul 29 06:13:08 PM PDT 24
Finished Jul 29 06:13:09 PM PDT 24
Peak memory 207080 kb
Host smart-9ff436a1-b0d0-47d3-8927-3c66e2c10d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96165
350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.96165350
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.707851355
Short name T1142
Test name
Test status
Simulation time 156777945 ps
CPU time 0.91 seconds
Started Jul 29 06:13:07 PM PDT 24
Finished Jul 29 06:13:08 PM PDT 24
Peak memory 207096 kb
Host smart-952a627b-b5d0-4da5-9272-f4dcfc20ba25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70785
1355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.707851355
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1749962087
Short name T1836
Test name
Test status
Simulation time 156264922 ps
CPU time 0.82 seconds
Started Jul 29 06:13:06 PM PDT 24
Finished Jul 29 06:13:07 PM PDT 24
Peak memory 207120 kb
Host smart-095f3d9f-502a-42b7-9a71-7c416ca58d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17499
62087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1749962087
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.494934920
Short name T2580
Test name
Test status
Simulation time 250181395 ps
CPU time 1.05 seconds
Started Jul 29 06:13:07 PM PDT 24
Finished Jul 29 06:13:08 PM PDT 24
Peak memory 207220 kb
Host smart-b669d434-937e-4bc2-8d61-24e2a9fe5f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49493
4920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.494934920
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.3792233938
Short name T2422
Test name
Test status
Simulation time 5269205389 ps
CPU time 56.14 seconds
Started Jul 29 06:13:05 PM PDT 24
Finished Jul 29 06:14:01 PM PDT 24
Peak memory 207432 kb
Host smart-2f04342c-0b7a-41a9-b997-4001200a22ab
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3792233938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.3792233938
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.4235517323
Short name T846
Test name
Test status
Simulation time 183590060 ps
CPU time 0.96 seconds
Started Jul 29 06:13:05 PM PDT 24
Finished Jul 29 06:13:06 PM PDT 24
Peak memory 207084 kb
Host smart-2ab7d4d4-6201-4610-ad6c-167606edf364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42355
17323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.4235517323
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1478125763
Short name T273
Test name
Test status
Simulation time 173608264 ps
CPU time 0.86 seconds
Started Jul 29 06:13:04 PM PDT 24
Finished Jul 29 06:13:05 PM PDT 24
Peak memory 207108 kb
Host smart-714b6afb-ba87-45c3-8371-1aacd548ccc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14781
25763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1478125763
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.760015112
Short name T2704
Test name
Test status
Simulation time 574887640 ps
CPU time 1.78 seconds
Started Jul 29 06:13:06 PM PDT 24
Finished Jul 29 06:13:08 PM PDT 24
Peak memory 207104 kb
Host smart-68690d44-9167-4138-bfb7-0f0e24bbe0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76001
5112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.760015112
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.1754651939
Short name T2854
Test name
Test status
Simulation time 6538865886 ps
CPU time 203.99 seconds
Started Jul 29 06:13:11 PM PDT 24
Finished Jul 29 06:16:35 PM PDT 24
Peak memory 215564 kb
Host smart-6a2e5752-889d-4008-930e-c1b2b671d263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17546
51939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1754651939
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.27134775
Short name T955
Test name
Test status
Simulation time 2549711370 ps
CPU time 18.08 seconds
Started Jul 29 06:13:02 PM PDT 24
Finished Jul 29 06:13:20 PM PDT 24
Peak memory 207328 kb
Host smart-24b78029-92c1-4f67-88f8-796b4879e3ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27134775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_host_
handshake.27134775
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.96314273
Short name T1422
Test name
Test status
Simulation time 33288594 ps
CPU time 0.67 seconds
Started Jul 29 06:13:19 PM PDT 24
Finished Jul 29 06:13:20 PM PDT 24
Peak memory 207152 kb
Host smart-b9743097-13f7-4284-abf1-ad9a99238467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=96314273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.96314273
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1472493561
Short name T1152
Test name
Test status
Simulation time 3920829233 ps
CPU time 6.11 seconds
Started Jul 29 06:13:12 PM PDT 24
Finished Jul 29 06:13:18 PM PDT 24
Peak memory 207332 kb
Host smart-0591cdcb-6bb9-4e94-8647-a4b2d4330c89
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472493561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.1472493561
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.2718151529
Short name T2703
Test name
Test status
Simulation time 23422988976 ps
CPU time 26.35 seconds
Started Jul 29 06:13:11 PM PDT 24
Finished Jul 29 06:13:37 PM PDT 24
Peak memory 207420 kb
Host smart-5189afc1-47b6-4b70-8013-ea93fdea17c2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718151529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.2718151529
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.4042342967
Short name T2559
Test name
Test status
Simulation time 157723969 ps
CPU time 0.88 seconds
Started Jul 29 06:13:13 PM PDT 24
Finished Jul 29 06:13:14 PM PDT 24
Peak memory 207100 kb
Host smart-68b219bf-af61-47bb-b1d8-584c10c52f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40423
42967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.4042342967
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.3041931413
Short name T79
Test name
Test status
Simulation time 144903494 ps
CPU time 0.82 seconds
Started Jul 29 06:13:11 PM PDT 24
Finished Jul 29 06:13:12 PM PDT 24
Peak memory 207024 kb
Host smart-51b59b49-7c80-439d-a4f0-c18ed4eb3716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30419
31413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.3041931413
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.904153319
Short name T389
Test name
Test status
Simulation time 432228409 ps
CPU time 1.43 seconds
Started Jul 29 06:13:21 PM PDT 24
Finished Jul 29 06:13:22 PM PDT 24
Peak memory 207104 kb
Host smart-3bb7c8ef-9628-4cfa-9dd4-5318d001f73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90415
3319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.904153319
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_device_address.4100379033
Short name T1664
Test name
Test status
Simulation time 11901054347 ps
CPU time 28.71 seconds
Started Jul 29 06:13:11 PM PDT 24
Finished Jul 29 06:13:40 PM PDT 24
Peak memory 207384 kb
Host smart-76e5a30e-77ee-4c1d-808b-d84776b0f33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41003
79033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.4100379033
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.1644575928
Short name T1942
Test name
Test status
Simulation time 177120546 ps
CPU time 0.92 seconds
Started Jul 29 06:13:21 PM PDT 24
Finished Jul 29 06:13:22 PM PDT 24
Peak memory 207080 kb
Host smart-f06b6a4c-5787-4dd8-b40b-92b7d6f3fd40
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644575928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.1644575928
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.1185154153
Short name T1076
Test name
Test status
Simulation time 509236025 ps
CPU time 1.67 seconds
Started Jul 29 06:13:13 PM PDT 24
Finished Jul 29 06:13:15 PM PDT 24
Peak memory 207060 kb
Host smart-98ef2509-5a5d-4526-8705-1a989e79bcbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11851
54153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.1185154153
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.2077878739
Short name T1259
Test name
Test status
Simulation time 156111796 ps
CPU time 0.85 seconds
Started Jul 29 06:13:10 PM PDT 24
Finished Jul 29 06:13:11 PM PDT 24
Peak memory 207044 kb
Host smart-143c19a8-4b57-4f1d-a5de-0d66edd86307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20778
78739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2077878739
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3930685312
Short name T697
Test name
Test status
Simulation time 60032208 ps
CPU time 0.77 seconds
Started Jul 29 06:13:22 PM PDT 24
Finished Jul 29 06:13:22 PM PDT 24
Peak memory 207056 kb
Host smart-28c3bade-0f5c-4f8a-951a-478a61b3d4e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39306
85312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3930685312
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1709441589
Short name T1910
Test name
Test status
Simulation time 767276517 ps
CPU time 2.1 seconds
Started Jul 29 06:13:12 PM PDT 24
Finished Jul 29 06:13:15 PM PDT 24
Peak memory 207312 kb
Host smart-66c1100c-8371-43a0-bd38-e1fedd1a11ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17094
41589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1709441589
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3021336437
Short name T1756
Test name
Test status
Simulation time 231318567 ps
CPU time 1.48 seconds
Started Jul 29 06:13:12 PM PDT 24
Finished Jul 29 06:13:13 PM PDT 24
Peak memory 207220 kb
Host smart-3ad21f1e-ed1f-47e6-ba37-ea1e1ed62a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30213
36437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3021336437
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1519565641
Short name T790
Test name
Test status
Simulation time 176876799 ps
CPU time 0.95 seconds
Started Jul 29 06:13:11 PM PDT 24
Finished Jul 29 06:13:12 PM PDT 24
Peak memory 207292 kb
Host smart-cc16a9a9-288c-46d3-89ee-b7d20584baa7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1519565641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1519565641
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3169050573
Short name T990
Test name
Test status
Simulation time 138003494 ps
CPU time 0.92 seconds
Started Jul 29 06:13:11 PM PDT 24
Finished Jul 29 06:13:12 PM PDT 24
Peak memory 207008 kb
Host smart-e79645d4-b6a2-424b-94bc-3cf15cbe9491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31690
50573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3169050573
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2835434684
Short name T32
Test name
Test status
Simulation time 211190285 ps
CPU time 0.97 seconds
Started Jul 29 06:13:15 PM PDT 24
Finished Jul 29 06:13:16 PM PDT 24
Peak memory 207104 kb
Host smart-1803373f-0bac-40ac-a875-c7136d1a8a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28354
34684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2835434684
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.2264038748
Short name T2088
Test name
Test status
Simulation time 6479424037 ps
CPU time 48.47 seconds
Started Jul 29 06:13:11 PM PDT 24
Finished Jul 29 06:13:59 PM PDT 24
Peak memory 215620 kb
Host smart-6e557c88-6a0e-4b5d-a92a-9309b662acf2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2264038748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.2264038748
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1958095512
Short name T664
Test name
Test status
Simulation time 232839705 ps
CPU time 0.95 seconds
Started Jul 29 06:13:21 PM PDT 24
Finished Jul 29 06:13:22 PM PDT 24
Peak memory 207092 kb
Host smart-a938771e-7d1a-4ef2-b092-64282045c19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19580
95512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1958095512
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.3828872871
Short name T1042
Test name
Test status
Simulation time 23289177009 ps
CPU time 29.18 seconds
Started Jul 29 06:13:12 PM PDT 24
Finished Jul 29 06:13:41 PM PDT 24
Peak memory 207392 kb
Host smart-59ef3ffb-4422-4cf2-8a6b-394b9a9374e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38288
72871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.3828872871
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.3059031548
Short name T1288
Test name
Test status
Simulation time 3267953750 ps
CPU time 5.49 seconds
Started Jul 29 06:13:22 PM PDT 24
Finished Jul 29 06:13:27 PM PDT 24
Peak memory 207340 kb
Host smart-146d8f70-53b4-42b6-a5d7-ae15645dc129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30590
31548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.3059031548
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.3701423696
Short name T1128
Test name
Test status
Simulation time 5208173599 ps
CPU time 146.98 seconds
Started Jul 29 06:13:11 PM PDT 24
Finished Jul 29 06:15:38 PM PDT 24
Peak memory 215640 kb
Host smart-58280f2b-f6a3-4b59-8faa-5e918858f7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37014
23696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3701423696
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.748328182
Short name T1034
Test name
Test status
Simulation time 5028024551 ps
CPU time 49.65 seconds
Started Jul 29 06:13:09 PM PDT 24
Finished Jul 29 06:13:59 PM PDT 24
Peak memory 215524 kb
Host smart-75dda531-51fd-4c02-b8aa-05533f840415
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=748328182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.748328182
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1056329562
Short name T811
Test name
Test status
Simulation time 249740718 ps
CPU time 1.07 seconds
Started Jul 29 06:13:12 PM PDT 24
Finished Jul 29 06:13:14 PM PDT 24
Peak memory 207180 kb
Host smart-183943b0-ffa2-42a2-88c2-8b1e086d80f0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1056329562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1056329562
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.148964070
Short name T1298
Test name
Test status
Simulation time 209057499 ps
CPU time 0.96 seconds
Started Jul 29 06:13:17 PM PDT 24
Finished Jul 29 06:13:18 PM PDT 24
Peak memory 207080 kb
Host smart-49d14e35-c4a7-4d51-bd44-fc12916ea910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14896
4070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.148964070
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.493447617
Short name T2432
Test name
Test status
Simulation time 3137948059 ps
CPU time 95.16 seconds
Started Jul 29 06:13:18 PM PDT 24
Finished Jul 29 06:14:54 PM PDT 24
Peak memory 215600 kb
Host smart-9b17d915-28e3-4e3f-8038-a8e4652f089f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49344
7617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.493447617
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.3057117625
Short name T1798
Test name
Test status
Simulation time 7518868555 ps
CPU time 60.88 seconds
Started Jul 29 06:13:21 PM PDT 24
Finished Jul 29 06:14:22 PM PDT 24
Peak memory 207296 kb
Host smart-052929e1-77ee-4545-a0e3-b5d6935b0b23
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3057117625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.3057117625
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2657887984
Short name T925
Test name
Test status
Simulation time 158304753 ps
CPU time 0.87 seconds
Started Jul 29 06:13:20 PM PDT 24
Finished Jul 29 06:13:21 PM PDT 24
Peak memory 207152 kb
Host smart-d9ad8c48-a0d3-4780-8dc4-2861d05e2b90
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2657887984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2657887984
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2964584239
Short name T1535
Test name
Test status
Simulation time 146118439 ps
CPU time 0.88 seconds
Started Jul 29 06:13:16 PM PDT 24
Finished Jul 29 06:13:17 PM PDT 24
Peak memory 207096 kb
Host smart-1d66b9a1-cc93-4543-989c-62cc049ef1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29645
84239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2964584239
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.2413067218
Short name T1366
Test name
Test status
Simulation time 180046040 ps
CPU time 0.89 seconds
Started Jul 29 06:13:16 PM PDT 24
Finished Jul 29 06:13:17 PM PDT 24
Peak memory 207072 kb
Host smart-687cc0cc-05ac-49ad-8a05-6c34836b581f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24130
67218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2413067218
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2816922644
Short name T1066
Test name
Test status
Simulation time 187814133 ps
CPU time 0.87 seconds
Started Jul 29 06:13:19 PM PDT 24
Finished Jul 29 06:13:20 PM PDT 24
Peak memory 207000 kb
Host smart-2c55e648-3194-447d-ace8-1ad8850eb0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28169
22644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2816922644
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.732129924
Short name T2762
Test name
Test status
Simulation time 184288464 ps
CPU time 0.89 seconds
Started Jul 29 06:13:20 PM PDT 24
Finished Jul 29 06:13:21 PM PDT 24
Peak memory 207128 kb
Host smart-7803bffb-c437-43c6-adf9-c25159cecbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73212
9924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.732129924
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3935067419
Short name T2538
Test name
Test status
Simulation time 165309468 ps
CPU time 0.84 seconds
Started Jul 29 06:13:18 PM PDT 24
Finished Jul 29 06:13:19 PM PDT 24
Peak memory 207096 kb
Host smart-7087083b-159d-48fc-a016-110eea4c8057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39350
67419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3935067419
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.3068113671
Short name T533
Test name
Test status
Simulation time 192891009 ps
CPU time 0.99 seconds
Started Jul 29 06:13:16 PM PDT 24
Finished Jul 29 06:13:17 PM PDT 24
Peak memory 207128 kb
Host smart-ec13b32c-7628-4960-8927-6da537454fd1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3068113671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.3068113671
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.206941935
Short name T35
Test name
Test status
Simulation time 144446401 ps
CPU time 0.86 seconds
Started Jul 29 06:13:18 PM PDT 24
Finished Jul 29 06:13:19 PM PDT 24
Peak memory 207064 kb
Host smart-67ca271a-8b70-4e13-9839-536959535f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20694
1935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.206941935
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3717086184
Short name T2543
Test name
Test status
Simulation time 36090394 ps
CPU time 0.67 seconds
Started Jul 29 06:13:17 PM PDT 24
Finished Jul 29 06:13:17 PM PDT 24
Peak memory 207080 kb
Host smart-bbf55c7d-eb53-44ee-a6ca-b53b4de9cc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37170
86184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3717086184
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1545981106
Short name T1122
Test name
Test status
Simulation time 19211578617 ps
CPU time 48.85 seconds
Started Jul 29 06:13:17 PM PDT 24
Finished Jul 29 06:14:06 PM PDT 24
Peak memory 215708 kb
Host smart-94e10a64-22b6-486e-9aba-d4eb23363644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15459
81106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1545981106
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.84584882
Short name T1467
Test name
Test status
Simulation time 164965906 ps
CPU time 0.9 seconds
Started Jul 29 06:13:20 PM PDT 24
Finished Jul 29 06:13:21 PM PDT 24
Peak memory 207096 kb
Host smart-6920c710-db97-4d97-b10e-32652078e213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84584
882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.84584882
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3805338782
Short name T2054
Test name
Test status
Simulation time 211763659 ps
CPU time 0.92 seconds
Started Jul 29 06:13:18 PM PDT 24
Finished Jul 29 06:13:19 PM PDT 24
Peak memory 207068 kb
Host smart-1bae9a0c-453c-4398-92b0-8f058f4f76a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38053
38782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3805338782
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.4036618790
Short name T1453
Test name
Test status
Simulation time 192166952 ps
CPU time 0.94 seconds
Started Jul 29 06:13:21 PM PDT 24
Finished Jul 29 06:13:22 PM PDT 24
Peak memory 207000 kb
Host smart-351cf4e8-dfae-47d0-bb68-ed993e2645c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40366
18790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.4036618790
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.932046890
Short name T778
Test name
Test status
Simulation time 183213894 ps
CPU time 0.92 seconds
Started Jul 29 06:13:16 PM PDT 24
Finished Jul 29 06:13:17 PM PDT 24
Peak memory 207080 kb
Host smart-357bb9b8-aa64-44ca-84e7-577343e9bba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93204
6890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.932046890
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.173372275
Short name T2070
Test name
Test status
Simulation time 145801794 ps
CPU time 0.82 seconds
Started Jul 29 06:13:18 PM PDT 24
Finished Jul 29 06:13:19 PM PDT 24
Peak memory 207032 kb
Host smart-67f8bc0b-9d8a-41cc-bad1-c6841789bb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17337
2275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.173372275
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2835989963
Short name T2205
Test name
Test status
Simulation time 144067457 ps
CPU time 0.83 seconds
Started Jul 29 06:13:20 PM PDT 24
Finished Jul 29 06:13:21 PM PDT 24
Peak memory 207092 kb
Host smart-4c660fd1-0c6d-4064-b638-18878efe438d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28359
89963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2835989963
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2392572957
Short name T1465
Test name
Test status
Simulation time 228465528 ps
CPU time 1 seconds
Started Jul 29 06:13:17 PM PDT 24
Finished Jul 29 06:13:19 PM PDT 24
Peak memory 207060 kb
Host smart-a014d9f9-cce7-4e1b-832a-2edc5f78cdb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23925
72957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2392572957
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.4145631576
Short name T2645
Test name
Test status
Simulation time 4433685925 ps
CPU time 32.98 seconds
Started Jul 29 06:13:18 PM PDT 24
Finished Jul 29 06:13:51 PM PDT 24
Peak memory 215652 kb
Host smart-5cb0bfee-0198-411c-a64c-ab8faeb47df9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4145631576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.4145631576
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3238345955
Short name T649
Test name
Test status
Simulation time 184577480 ps
CPU time 0.88 seconds
Started Jul 29 06:13:18 PM PDT 24
Finished Jul 29 06:13:19 PM PDT 24
Peak memory 207120 kb
Host smart-69bc2bf3-9d50-4ca9-8a1b-6000f66683d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32383
45955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3238345955
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2237311448
Short name T1012
Test name
Test status
Simulation time 205442114 ps
CPU time 0.92 seconds
Started Jul 29 06:13:18 PM PDT 24
Finished Jul 29 06:13:19 PM PDT 24
Peak memory 207100 kb
Host smart-bf3aa100-3fac-4080-ad12-8e1c8c31e631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22373
11448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2237311448
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.3345744282
Short name T2069
Test name
Test status
Simulation time 1083199782 ps
CPU time 2.49 seconds
Started Jul 29 06:13:20 PM PDT 24
Finished Jul 29 06:13:23 PM PDT 24
Peak memory 207304 kb
Host smart-7e54db84-9f5d-4d75-b3c5-ff4c6e08dd0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33457
44282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.3345744282
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.2033882502
Short name T1009
Test name
Test status
Simulation time 7090225576 ps
CPU time 209.88 seconds
Started Jul 29 06:13:21 PM PDT 24
Finished Jul 29 06:16:51 PM PDT 24
Peak memory 215452 kb
Host smart-27c9bccf-01e0-4df7-bdec-c38105535686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20338
82502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2033882502
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.2280353250
Short name T1132
Test name
Test status
Simulation time 2877374483 ps
CPU time 20.39 seconds
Started Jul 29 06:13:13 PM PDT 24
Finished Jul 29 06:13:33 PM PDT 24
Peak memory 207368 kb
Host smart-aa2e8129-4d83-482d-a318-de2ab1daf12a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280353250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.2280353250
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.2348443856
Short name T736
Test name
Test status
Simulation time 52224625 ps
CPU time 0.68 seconds
Started Jul 29 06:13:39 PM PDT 24
Finished Jul 29 06:13:40 PM PDT 24
Peak memory 207104 kb
Host smart-a68364fe-6bdd-48f2-9d40-c42c926806be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2348443856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.2348443856
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1269715351
Short name T2513
Test name
Test status
Simulation time 4175430041 ps
CPU time 6.11 seconds
Started Jul 29 06:13:26 PM PDT 24
Finished Jul 29 06:13:32 PM PDT 24
Peak memory 207360 kb
Host smart-afd08450-3a91-42a2-a5a7-98a75ff1a822
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269715351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_disconnect.1269715351
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2492466478
Short name T1466
Test name
Test status
Simulation time 13407446766 ps
CPU time 18.07 seconds
Started Jul 29 06:13:30 PM PDT 24
Finished Jul 29 06:13:48 PM PDT 24
Peak memory 207424 kb
Host smart-f43c5d7c-50eb-41b9-be04-fb57493df27b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492466478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2492466478
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.692979502
Short name T1364
Test name
Test status
Simulation time 23405255023 ps
CPU time 31.79 seconds
Started Jul 29 06:13:23 PM PDT 24
Finished Jul 29 06:13:55 PM PDT 24
Peak memory 207372 kb
Host smart-9a3ef078-be55-48f5-afcb-8ad902e096b5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692979502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ao
n_wake_resume.692979502
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2823315695
Short name T1307
Test name
Test status
Simulation time 196306560 ps
CPU time 0.88 seconds
Started Jul 29 06:13:24 PM PDT 24
Finished Jul 29 06:13:25 PM PDT 24
Peak memory 207128 kb
Host smart-f71ace88-05a2-4103-b1e6-a0b739df99d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28233
15695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2823315695
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.101167827
Short name T1092
Test name
Test status
Simulation time 147387522 ps
CPU time 0.84 seconds
Started Jul 29 06:13:23 PM PDT 24
Finished Jul 29 06:13:24 PM PDT 24
Peak memory 207176 kb
Host smart-d490f5cc-24b8-4040-9cd6-95fa636680a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10116
7827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.101167827
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2771991815
Short name T315
Test name
Test status
Simulation time 610911240 ps
CPU time 1.95 seconds
Started Jul 29 06:13:22 PM PDT 24
Finished Jul 29 06:13:24 PM PDT 24
Peak memory 207016 kb
Host smart-366c76ea-9fcc-4777-9a3f-1d8d0b0ccc3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27719
91815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2771991815
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.2121270153
Short name T2823
Test name
Test status
Simulation time 1340771262 ps
CPU time 3.23 seconds
Started Jul 29 06:13:25 PM PDT 24
Finished Jul 29 06:13:29 PM PDT 24
Peak memory 207352 kb
Host smart-18e8beb0-2012-4418-bf16-3a64d2518c07
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2121270153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2121270153
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.3069505550
Short name T163
Test name
Test status
Simulation time 20317144686 ps
CPU time 42.27 seconds
Started Jul 29 06:13:27 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 207432 kb
Host smart-4cf4b07d-686c-46e5-b1e5-7fbbc50a384a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30695
05550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.3069505550
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.1054808896
Short name T850
Test name
Test status
Simulation time 4328809768 ps
CPU time 30.63 seconds
Started Jul 29 06:13:24 PM PDT 24
Finished Jul 29 06:13:55 PM PDT 24
Peak memory 207416 kb
Host smart-c1090b1a-b2be-45c8-8c0a-126b797d4b2a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054808896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.1054808896
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.4239368668
Short name T1718
Test name
Test status
Simulation time 321003687 ps
CPU time 1.22 seconds
Started Jul 29 06:13:24 PM PDT 24
Finished Jul 29 06:13:25 PM PDT 24
Peak memory 207096 kb
Host smart-9926655e-fb59-41d5-b6c7-6d4e522c835d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42393
68668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.4239368668
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.4169824942
Short name T2597
Test name
Test status
Simulation time 145025660 ps
CPU time 0.86 seconds
Started Jul 29 06:13:30 PM PDT 24
Finished Jul 29 06:13:31 PM PDT 24
Peak memory 206984 kb
Host smart-c5f4e0f2-95f9-4255-9583-446482dbf8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41698
24942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.4169824942
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1781403995
Short name T1992
Test name
Test status
Simulation time 68386792 ps
CPU time 0.74 seconds
Started Jul 29 06:13:22 PM PDT 24
Finished Jul 29 06:13:23 PM PDT 24
Peak memory 207032 kb
Host smart-74c783b2-ee7c-4f8e-8bcd-bb246c693680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17814
03995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1781403995
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1292702748
Short name T1095
Test name
Test status
Simulation time 929316437 ps
CPU time 2.53 seconds
Started Jul 29 06:13:23 PM PDT 24
Finished Jul 29 06:13:26 PM PDT 24
Peak memory 207228 kb
Host smart-e593ebe0-f970-42a2-976d-a683ac916cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12927
02748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1292702748
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1421973027
Short name T2644
Test name
Test status
Simulation time 160740562 ps
CPU time 1.62 seconds
Started Jul 29 06:13:23 PM PDT 24
Finished Jul 29 06:13:25 PM PDT 24
Peak memory 207328 kb
Host smart-25a5ffd4-1908-4439-a06c-b9a9d37bf9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219
73027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1421973027
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.4140429377
Short name T711
Test name
Test status
Simulation time 206348057 ps
CPU time 1.07 seconds
Started Jul 29 06:13:21 PM PDT 24
Finished Jul 29 06:13:22 PM PDT 24
Peak memory 207232 kb
Host smart-d40e32e2-5ab4-49da-911c-2f8a11d8a064
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4140429377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.4140429377
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2639906040
Short name T954
Test name
Test status
Simulation time 151739218 ps
CPU time 0.81 seconds
Started Jul 29 06:13:24 PM PDT 24
Finished Jul 29 06:13:25 PM PDT 24
Peak memory 207092 kb
Host smart-f388edde-7e47-4d0a-80bf-6df328120805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26399
06040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2639906040
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.665035423
Short name T543
Test name
Test status
Simulation time 243153995 ps
CPU time 1.01 seconds
Started Jul 29 06:13:23 PM PDT 24
Finished Jul 29 06:13:24 PM PDT 24
Peak memory 207024 kb
Host smart-df256436-53ae-4a84-bd5d-82cab2bd824b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66503
5423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.665035423
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.2513643728
Short name T45
Test name
Test status
Simulation time 4983402747 ps
CPU time 35.58 seconds
Started Jul 29 06:13:22 PM PDT 24
Finished Jul 29 06:13:57 PM PDT 24
Peak memory 215640 kb
Host smart-db62c0f5-8c2a-4b3c-ba6f-a5bea75f8260
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2513643728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.2513643728
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.1297867306
Short name T2833
Test name
Test status
Simulation time 15300860493 ps
CPU time 99.1 seconds
Started Jul 29 06:13:23 PM PDT 24
Finished Jul 29 06:15:02 PM PDT 24
Peak memory 207404 kb
Host smart-e2f69d7d-f091-4f4d-b87f-96338625fbff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1297867306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.1297867306
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1339510067
Short name T1240
Test name
Test status
Simulation time 243293615 ps
CPU time 0.98 seconds
Started Jul 29 06:13:22 PM PDT 24
Finished Jul 29 06:13:23 PM PDT 24
Peak memory 207076 kb
Host smart-4bfa76d5-460c-41c0-bde0-1205b67ab136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13395
10067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1339510067
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.1475139659
Short name T1534
Test name
Test status
Simulation time 23310650648 ps
CPU time 25.96 seconds
Started Jul 29 06:13:23 PM PDT 24
Finished Jul 29 06:13:49 PM PDT 24
Peak memory 207388 kb
Host smart-9bee42cd-c14f-432b-8588-088fad3ee034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14751
39659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.1475139659
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.1474291069
Short name T2643
Test name
Test status
Simulation time 3353429863 ps
CPU time 6.08 seconds
Started Jul 29 06:13:22 PM PDT 24
Finished Jul 29 06:13:28 PM PDT 24
Peak memory 207304 kb
Host smart-ce7c96b5-9f95-4409-8f98-2f575b3a72ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14742
91069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.1474291069
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.3566066102
Short name T2127
Test name
Test status
Simulation time 6213840108 ps
CPU time 52.62 seconds
Started Jul 29 06:13:31 PM PDT 24
Finished Jul 29 06:14:24 PM PDT 24
Peak memory 207376 kb
Host smart-7a6727f6-44cc-486c-b993-1011a4aca90a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3566066102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3566066102
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.836850615
Short name T861
Test name
Test status
Simulation time 234971015 ps
CPU time 1.01 seconds
Started Jul 29 06:13:30 PM PDT 24
Finished Jul 29 06:13:31 PM PDT 24
Peak memory 207116 kb
Host smart-e306d816-32d2-4ac5-beff-9945223a9e4c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=836850615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.836850615
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2828400629
Short name T2280
Test name
Test status
Simulation time 192874169 ps
CPU time 0.99 seconds
Started Jul 29 06:13:34 PM PDT 24
Finished Jul 29 06:13:35 PM PDT 24
Peak memory 207068 kb
Host smart-2f47d409-0457-4a95-a52c-fca0bebfd4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28284
00629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2828400629
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1120497697
Short name T1702
Test name
Test status
Simulation time 4572586824 ps
CPU time 143.69 seconds
Started Jul 29 06:13:28 PM PDT 24
Finished Jul 29 06:15:52 PM PDT 24
Peak memory 215596 kb
Host smart-0483cae8-3fed-45f0-9882-6ffeb5ec234a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11204
97697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1120497697
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.222802823
Short name T2115
Test name
Test status
Simulation time 3056105257 ps
CPU time 24.65 seconds
Started Jul 29 06:13:27 PM PDT 24
Finished Jul 29 06:13:51 PM PDT 24
Peak memory 216964 kb
Host smart-be304424-d68d-4835-9d5d-f7ba49c80b78
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=222802823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.222802823
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.2520197257
Short name T1856
Test name
Test status
Simulation time 192683623 ps
CPU time 0.94 seconds
Started Jul 29 06:13:29 PM PDT 24
Finished Jul 29 06:13:30 PM PDT 24
Peak memory 207076 kb
Host smart-b850edeb-ab0e-4252-9d26-c5484e5bb294
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2520197257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.2520197257
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.666776468
Short name T1674
Test name
Test status
Simulation time 172351740 ps
CPU time 0.86 seconds
Started Jul 29 06:13:28 PM PDT 24
Finished Jul 29 06:13:29 PM PDT 24
Peak memory 207060 kb
Host smart-eb83bb17-7914-4f12-8db6-4d3b03b3eb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66677
6468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.666776468
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3040800302
Short name T1909
Test name
Test status
Simulation time 180220688 ps
CPU time 0.93 seconds
Started Jul 29 06:13:28 PM PDT 24
Finished Jul 29 06:13:29 PM PDT 24
Peak memory 207056 kb
Host smart-fb8559be-8b61-46a7-a935-8ff69ccad713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30408
00302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3040800302
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2110407801
Short name T2338
Test name
Test status
Simulation time 182361967 ps
CPU time 0.89 seconds
Started Jul 29 06:13:28 PM PDT 24
Finished Jul 29 06:13:29 PM PDT 24
Peak memory 207100 kb
Host smart-286f79bc-f45c-4de9-99f3-77c78d18bf84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21104
07801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2110407801
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.269012797
Short name T1777
Test name
Test status
Simulation time 160235944 ps
CPU time 0.86 seconds
Started Jul 29 06:13:32 PM PDT 24
Finished Jul 29 06:13:33 PM PDT 24
Peak memory 207136 kb
Host smart-e5c7a851-747b-462f-9f98-b9841f893577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26901
2797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.269012797
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.192387269
Short name T1623
Test name
Test status
Simulation time 172434351 ps
CPU time 0.82 seconds
Started Jul 29 06:13:26 PM PDT 24
Finished Jul 29 06:13:27 PM PDT 24
Peak memory 207064 kb
Host smart-20697a98-64b0-4856-a41f-2cb866b2053e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19238
7269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.192387269
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.1388183774
Short name T423
Test name
Test status
Simulation time 237869851 ps
CPU time 0.98 seconds
Started Jul 29 06:13:30 PM PDT 24
Finished Jul 29 06:13:31 PM PDT 24
Peak memory 207100 kb
Host smart-241f8c3f-d66f-4d37-9951-fd29d06366da
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1388183774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.1388183774
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.4217355603
Short name T1912
Test name
Test status
Simulation time 142862352 ps
CPU time 0.82 seconds
Started Jul 29 06:13:30 PM PDT 24
Finished Jul 29 06:13:31 PM PDT 24
Peak memory 207040 kb
Host smart-a3c85548-519f-4a61-9fa0-0b4b6dfe56f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42173
55603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.4217355603
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3563429603
Short name T37
Test name
Test status
Simulation time 41491685 ps
CPU time 0.7 seconds
Started Jul 29 06:13:29 PM PDT 24
Finished Jul 29 06:13:30 PM PDT 24
Peak memory 207076 kb
Host smart-cd9b0f15-dadd-4cc1-8e22-c9130e65c59c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35634
29603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3563429603
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2293888957
Short name T1282
Test name
Test status
Simulation time 16087647334 ps
CPU time 42.08 seconds
Started Jul 29 06:13:27 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 215616 kb
Host smart-1e4f8829-21ea-4a3e-afa1-4467c80b8e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22938
88957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2293888957
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1205661982
Short name T1234
Test name
Test status
Simulation time 177474107 ps
CPU time 0.94 seconds
Started Jul 29 06:13:29 PM PDT 24
Finished Jul 29 06:13:30 PM PDT 24
Peak memory 207104 kb
Host smart-bfa374cb-70e3-46f1-a4e6-7b00ef01e511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12056
61982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1205661982
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2308644035
Short name T2210
Test name
Test status
Simulation time 197312857 ps
CPU time 1 seconds
Started Jul 29 06:13:29 PM PDT 24
Finished Jul 29 06:13:30 PM PDT 24
Peak memory 207108 kb
Host smart-61d023f6-5ca7-4daa-804b-d7705b7f5a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23086
44035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2308644035
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1091639795
Short name T2549
Test name
Test status
Simulation time 197649624 ps
CPU time 0.93 seconds
Started Jul 29 06:13:30 PM PDT 24
Finished Jul 29 06:13:31 PM PDT 24
Peak memory 207108 kb
Host smart-70ec577e-069a-4ac3-bab5-582c6aa970d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10916
39795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1091639795
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.135181255
Short name T1554
Test name
Test status
Simulation time 166762216 ps
CPU time 0.9 seconds
Started Jul 29 06:13:31 PM PDT 24
Finished Jul 29 06:13:32 PM PDT 24
Peak memory 207136 kb
Host smart-355a18c0-9a6e-4d77-8839-2fc890cbd9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13518
1255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.135181255
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.3783798379
Short name T34
Test name
Test status
Simulation time 158524885 ps
CPU time 0.86 seconds
Started Jul 29 06:13:27 PM PDT 24
Finished Jul 29 06:13:28 PM PDT 24
Peak memory 207044 kb
Host smart-dae71bf2-8df8-4e32-8c59-b1497e3de49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37837
98379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.3783798379
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3170233243
Short name T534
Test name
Test status
Simulation time 162935222 ps
CPU time 0.85 seconds
Started Jul 29 06:13:31 PM PDT 24
Finished Jul 29 06:13:32 PM PDT 24
Peak memory 207084 kb
Host smart-76821bda-6241-4366-ad7b-3d5c0b8eff38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31702
33243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3170233243
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1303015655
Short name T2860
Test name
Test status
Simulation time 303636524 ps
CPU time 1.09 seconds
Started Jul 29 06:13:31 PM PDT 24
Finished Jul 29 06:13:33 PM PDT 24
Peak memory 207084 kb
Host smart-5263e600-aaab-45d7-b8f6-08cee77538b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13030
15655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1303015655
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2013342658
Short name T2257
Test name
Test status
Simulation time 5043414499 ps
CPU time 155.43 seconds
Started Jul 29 06:13:32 PM PDT 24
Finished Jul 29 06:16:07 PM PDT 24
Peak memory 215544 kb
Host smart-b1b4f01b-a919-49f3-b952-7d8396f4b163
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2013342658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2013342658
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3534325079
Short name T120
Test name
Test status
Simulation time 167842944 ps
CPU time 0.9 seconds
Started Jul 29 06:13:34 PM PDT 24
Finished Jul 29 06:13:35 PM PDT 24
Peak memory 207188 kb
Host smart-db642e33-a8e2-4092-bd1b-64f024ae0416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35343
25079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3534325079
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2231547345
Short name T2583
Test name
Test status
Simulation time 165173059 ps
CPU time 0.94 seconds
Started Jul 29 06:13:32 PM PDT 24
Finished Jul 29 06:13:33 PM PDT 24
Peak memory 207136 kb
Host smart-cefc1cef-d99c-4851-be5c-99bc2b3fd2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22315
47345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2231547345
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.1343847237
Short name T1800
Test name
Test status
Simulation time 1206876217 ps
CPU time 2.72 seconds
Started Jul 29 06:13:33 PM PDT 24
Finished Jul 29 06:13:36 PM PDT 24
Peak memory 207152 kb
Host smart-0647c3bf-ca8c-45ab-b1f1-0689e75145c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13438
47237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.1343847237
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.4092408839
Short name T1144
Test name
Test status
Simulation time 5344159296 ps
CPU time 43.07 seconds
Started Jul 29 06:13:32 PM PDT 24
Finished Jul 29 06:14:15 PM PDT 24
Peak memory 207328 kb
Host smart-0eee2756-899b-4e3e-bd07-5c44bc695b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40924
08839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.4092408839
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.3014136994
Short name T904
Test name
Test status
Simulation time 220252660 ps
CPU time 0.92 seconds
Started Jul 29 06:13:23 PM PDT 24
Finished Jul 29 06:13:24 PM PDT 24
Peak memory 207104 kb
Host smart-dae0cb4a-582f-4fff-938b-de9f826d3133
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014136994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.3014136994
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.2828133755
Short name T1794
Test name
Test status
Simulation time 40265313 ps
CPU time 0.67 seconds
Started Jul 29 06:13:43 PM PDT 24
Finished Jul 29 06:13:43 PM PDT 24
Peak memory 207016 kb
Host smart-288f4731-752f-424a-804c-8a397796371a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2828133755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.2828133755
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3085930886
Short name T1788
Test name
Test status
Simulation time 3940038776 ps
CPU time 6.64 seconds
Started Jul 29 06:13:32 PM PDT 24
Finished Jul 29 06:13:39 PM PDT 24
Peak memory 207272 kb
Host smart-8142af29-6fb9-45ef-a753-8852389caf8d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085930886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.3085930886
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.1179363928
Short name T2157
Test name
Test status
Simulation time 13397811955 ps
CPU time 15.05 seconds
Started Jul 29 06:13:34 PM PDT 24
Finished Jul 29 06:13:49 PM PDT 24
Peak memory 207392 kb
Host smart-8c19a8c0-b47c-438e-b36e-f9c667879205
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179363928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1179363928
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.3763562457
Short name T2168
Test name
Test status
Simulation time 23479137270 ps
CPU time 28.21 seconds
Started Jul 29 06:13:32 PM PDT 24
Finished Jul 29 06:14:00 PM PDT 24
Peak memory 207408 kb
Host smart-7238c8d7-ef75-495b-aa43-fc264b15ecce
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763562457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.3763562457
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.4137955329
Short name T2682
Test name
Test status
Simulation time 202301023 ps
CPU time 0.92 seconds
Started Jul 29 06:13:41 PM PDT 24
Finished Jul 29 06:13:42 PM PDT 24
Peak memory 206836 kb
Host smart-5ecf0fd3-4ca1-45f8-a920-7ee65447f778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41379
55329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.4137955329
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.698161890
Short name T2512
Test name
Test status
Simulation time 156565817 ps
CPU time 0.83 seconds
Started Jul 29 06:13:33 PM PDT 24
Finished Jul 29 06:13:34 PM PDT 24
Peak memory 207072 kb
Host smart-98074818-1e53-475b-974f-34841b6912db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69816
1890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.698161890
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3672300315
Short name T2489
Test name
Test status
Simulation time 555971475 ps
CPU time 1.75 seconds
Started Jul 29 06:13:41 PM PDT 24
Finished Jul 29 06:13:43 PM PDT 24
Peak memory 206872 kb
Host smart-89ebeeff-ddf9-485e-9549-ed5f8c3358f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36723
00315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3672300315
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.1895103236
Short name T899
Test name
Test status
Simulation time 475801074 ps
CPU time 1.42 seconds
Started Jul 29 06:13:41 PM PDT 24
Finished Jul 29 06:13:43 PM PDT 24
Peak memory 207076 kb
Host smart-282b3a8d-a494-4837-8920-a686e10d3966
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1895103236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.1895103236
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.4269525532
Short name T269
Test name
Test status
Simulation time 21869230482 ps
CPU time 47.4 seconds
Started Jul 29 06:13:34 PM PDT 24
Finished Jul 29 06:14:21 PM PDT 24
Peak memory 207516 kb
Host smart-8def585d-2307-428d-aff4-554cc921fb92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42695
25532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.4269525532
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.3731119295
Short name T685
Test name
Test status
Simulation time 1163893808 ps
CPU time 26.9 seconds
Started Jul 29 06:13:32 PM PDT 24
Finished Jul 29 06:13:59 PM PDT 24
Peak memory 207512 kb
Host smart-ce94501a-71c2-4e1c-b64f-33ef5f024e59
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731119295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.3731119295
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2817814417
Short name T268
Test name
Test status
Simulation time 474576893 ps
CPU time 1.56 seconds
Started Jul 29 06:13:33 PM PDT 24
Finished Jul 29 06:13:34 PM PDT 24
Peak memory 207080 kb
Host smart-4e1aba32-ee2e-4b9a-8a3a-eac58dc53050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28178
14417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2817814417
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.4251139349
Short name T2160
Test name
Test status
Simulation time 143135587 ps
CPU time 0.82 seconds
Started Jul 29 06:13:39 PM PDT 24
Finished Jul 29 06:13:40 PM PDT 24
Peak memory 207028 kb
Host smart-7851c028-794e-432d-a5f3-3456cb59a124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42511
39349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.4251139349
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.744681229
Short name T1552
Test name
Test status
Simulation time 59176608 ps
CPU time 0.73 seconds
Started Jul 29 06:13:33 PM PDT 24
Finished Jul 29 06:13:34 PM PDT 24
Peak memory 207004 kb
Host smart-45ac17b9-648b-49bb-9cdc-d6b8a00721cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74468
1229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.744681229
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.4248959920
Short name T1372
Test name
Test status
Simulation time 938382259 ps
CPU time 2.61 seconds
Started Jul 29 06:13:34 PM PDT 24
Finished Jul 29 06:13:37 PM PDT 24
Peak memory 207316 kb
Host smart-a8fade65-d754-4d7c-a26a-9b246d37d201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42489
59920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.4248959920
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.136418973
Short name T629
Test name
Test status
Simulation time 385889070 ps
CPU time 2.74 seconds
Started Jul 29 06:13:41 PM PDT 24
Finished Jul 29 06:13:44 PM PDT 24
Peak memory 207224 kb
Host smart-1689782a-7243-462e-abba-e66294e34a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13641
8973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.136418973
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2604698732
Short name T1353
Test name
Test status
Simulation time 204249843 ps
CPU time 1.03 seconds
Started Jul 29 06:13:40 PM PDT 24
Finished Jul 29 06:13:41 PM PDT 24
Peak memory 207292 kb
Host smart-eed51e2b-a133-4423-87b5-fd250da66e62
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2604698732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2604698732
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.684068754
Short name T580
Test name
Test status
Simulation time 154292360 ps
CPU time 0.84 seconds
Started Jul 29 06:13:39 PM PDT 24
Finished Jul 29 06:13:40 PM PDT 24
Peak memory 207064 kb
Host smart-2b6d2122-bc3e-4e41-a7df-195189d244d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68406
8754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.684068754
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.265525389
Short name T522
Test name
Test status
Simulation time 209553930 ps
CPU time 0.99 seconds
Started Jul 29 06:13:40 PM PDT 24
Finished Jul 29 06:13:41 PM PDT 24
Peak memory 207056 kb
Host smart-abd00c53-f280-413f-bf38-71912aadf224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26552
5389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.265525389
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.3602305102
Short name T1323
Test name
Test status
Simulation time 6437879588 ps
CPU time 181.38 seconds
Started Jul 29 06:13:43 PM PDT 24
Finished Jul 29 06:16:44 PM PDT 24
Peak memory 215592 kb
Host smart-cd5c78ce-aa26-4dfb-b7fb-58defcb4ffa3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3602305102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.3602305102
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.2255987374
Short name T1655
Test name
Test status
Simulation time 6563232375 ps
CPU time 45.98 seconds
Started Jul 29 06:13:41 PM PDT 24
Finished Jul 29 06:14:27 PM PDT 24
Peak memory 207404 kb
Host smart-9801804f-fd00-45cd-9836-6221253d8cff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2255987374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.2255987374
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2648028269
Short name T1948
Test name
Test status
Simulation time 169908807 ps
CPU time 0.89 seconds
Started Jul 29 06:13:36 PM PDT 24
Finished Jul 29 06:13:37 PM PDT 24
Peak memory 207100 kb
Host smart-c8731027-c95b-4c07-81af-eeea2f29d1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26480
28269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2648028269
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.1428590108
Short name T478
Test name
Test status
Simulation time 23299330158 ps
CPU time 26.41 seconds
Started Jul 29 06:13:41 PM PDT 24
Finished Jul 29 06:14:07 PM PDT 24
Peak memory 207348 kb
Host smart-ba8c7d56-2b55-4195-be40-2f5375885664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14285
90108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.1428590108
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.4060308222
Short name T823
Test name
Test status
Simulation time 3373310327 ps
CPU time 4.95 seconds
Started Jul 29 06:13:39 PM PDT 24
Finished Jul 29 06:13:44 PM PDT 24
Peak memory 207336 kb
Host smart-9bc0d0a4-067f-4acf-906f-cab24bcc253a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40603
08222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.4060308222
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.3260267613
Short name T789
Test name
Test status
Simulation time 9140088874 ps
CPU time 89.98 seconds
Started Jul 29 06:13:38 PM PDT 24
Finished Jul 29 06:15:08 PM PDT 24
Peak memory 217476 kb
Host smart-1a26f763-a153-4166-8457-22656d419a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32602
67613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.3260267613
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.453400654
Short name T349
Test name
Test status
Simulation time 3567105274 ps
CPU time 36.85 seconds
Started Jul 29 06:13:39 PM PDT 24
Finished Jul 29 06:14:16 PM PDT 24
Peak memory 215528 kb
Host smart-17eacfc5-e1a2-4c30-b1d7-a8b5084563f5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=453400654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.453400654
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1536783082
Short name T1016
Test name
Test status
Simulation time 249221323 ps
CPU time 1 seconds
Started Jul 29 06:13:38 PM PDT 24
Finished Jul 29 06:13:40 PM PDT 24
Peak memory 207108 kb
Host smart-5b5473f1-0872-4e7b-8e52-90409fd8cda7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1536783082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1536783082
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2343547103
Short name T1314
Test name
Test status
Simulation time 196994464 ps
CPU time 0.94 seconds
Started Jul 29 06:13:37 PM PDT 24
Finished Jul 29 06:13:38 PM PDT 24
Peak memory 207144 kb
Host smart-7bcec6bf-359e-4d2b-8a65-c7b9d6652948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23435
47103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2343547103
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.1070675227
Short name T1523
Test name
Test status
Simulation time 5595725639 ps
CPU time 154.79 seconds
Started Jul 29 06:13:43 PM PDT 24
Finished Jul 29 06:16:18 PM PDT 24
Peak memory 215576 kb
Host smart-b8a7be86-25ee-41c5-a76b-3899256f7119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10706
75227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.1070675227
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.195556399
Short name T511
Test name
Test status
Simulation time 5159598912 ps
CPU time 159.09 seconds
Started Jul 29 06:13:39 PM PDT 24
Finished Jul 29 06:16:18 PM PDT 24
Peak memory 215608 kb
Host smart-4f1d12aa-9d9c-4326-ae77-a4d9b62033e2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=195556399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.195556399
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.1244623994
Short name T1971
Test name
Test status
Simulation time 170693577 ps
CPU time 0.88 seconds
Started Jul 29 06:13:38 PM PDT 24
Finished Jul 29 06:13:39 PM PDT 24
Peak memory 207088 kb
Host smart-6cdf4bcf-bd09-4ada-abc1-c328e54f7f33
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1244623994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.1244623994
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.449014363
Short name T658
Test name
Test status
Simulation time 180181664 ps
CPU time 0.86 seconds
Started Jul 29 06:13:38 PM PDT 24
Finished Jul 29 06:13:39 PM PDT 24
Peak memory 207060 kb
Host smart-fce25a6e-8605-482e-8aa8-d9c43525df31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44901
4363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.449014363
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1094428792
Short name T2123
Test name
Test status
Simulation time 221922847 ps
CPU time 1.02 seconds
Started Jul 29 06:13:39 PM PDT 24
Finished Jul 29 06:13:40 PM PDT 24
Peak memory 207000 kb
Host smart-a86edf32-17f6-498e-a73a-539e8c3c01cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10944
28792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1094428792
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.162534913
Short name T2389
Test name
Test status
Simulation time 163846611 ps
CPU time 0.89 seconds
Started Jul 29 06:13:38 PM PDT 24
Finished Jul 29 06:13:39 PM PDT 24
Peak memory 207132 kb
Host smart-88a926c5-482f-416e-9689-b232cd1f7bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16253
4913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.162534913
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.164501506
Short name T1606
Test name
Test status
Simulation time 201309500 ps
CPU time 0.94 seconds
Started Jul 29 06:13:38 PM PDT 24
Finished Jul 29 06:13:39 PM PDT 24
Peak memory 207088 kb
Host smart-ee949219-5915-4d26-8b6d-3edc859a0783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16450
1506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.164501506
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.165020171
Short name T859
Test name
Test status
Simulation time 208255664 ps
CPU time 0.97 seconds
Started Jul 29 06:13:40 PM PDT 24
Finished Jul 29 06:13:41 PM PDT 24
Peak memory 207096 kb
Host smart-744391dd-19bf-42cb-8b68-992db0a8d486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16502
0171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.165020171
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.249221474
Short name T1978
Test name
Test status
Simulation time 154809308 ps
CPU time 0.84 seconds
Started Jul 29 06:13:37 PM PDT 24
Finished Jul 29 06:13:38 PM PDT 24
Peak memory 207080 kb
Host smart-d42e7acc-2e37-40a1-aad3-08b3f9dcbc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24922
1474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.249221474
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3488146508
Short name T2026
Test name
Test status
Simulation time 206709464 ps
CPU time 0.99 seconds
Started Jul 29 06:13:41 PM PDT 24
Finished Jul 29 06:13:42 PM PDT 24
Peak memory 207104 kb
Host smart-0534c891-3c49-49c2-b1ab-344a4024f2d4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3488146508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3488146508
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1423337935
Short name T189
Test name
Test status
Simulation time 156931015 ps
CPU time 0.82 seconds
Started Jul 29 06:13:39 PM PDT 24
Finished Jul 29 06:13:40 PM PDT 24
Peak memory 207064 kb
Host smart-6d70bad3-1bec-4348-a3db-11a617b75d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14233
37935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1423337935
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.4072784375
Short name T707
Test name
Test status
Simulation time 91112183 ps
CPU time 0.73 seconds
Started Jul 29 06:13:40 PM PDT 24
Finished Jul 29 06:13:41 PM PDT 24
Peak memory 207072 kb
Host smart-db357a70-1bfb-45f6-9f45-4cef03a2ce63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40727
84375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.4072784375
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2254433472
Short name T2784
Test name
Test status
Simulation time 18718260443 ps
CPU time 48.18 seconds
Started Jul 29 06:13:47 PM PDT 24
Finished Jul 29 06:14:35 PM PDT 24
Peak memory 215640 kb
Host smart-6a76fe65-0a78-4524-8572-4f52b47c69f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22544
33472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2254433472
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.524540189
Short name T666
Test name
Test status
Simulation time 160739865 ps
CPU time 1 seconds
Started Jul 29 06:13:44 PM PDT 24
Finished Jul 29 06:13:45 PM PDT 24
Peak memory 207076 kb
Host smart-0e075575-2d7b-4a44-ba12-4c0f73186b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52454
0189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.524540189
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2171642718
Short name T2117
Test name
Test status
Simulation time 216563904 ps
CPU time 0.94 seconds
Started Jul 29 06:13:42 PM PDT 24
Finished Jul 29 06:13:43 PM PDT 24
Peak memory 207144 kb
Host smart-1c8611bb-d061-4591-9931-448f3c64ffbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21716
42718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2171642718
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.4038044230
Short name T1730
Test name
Test status
Simulation time 214780800 ps
CPU time 1 seconds
Started Jul 29 06:13:52 PM PDT 24
Finished Jul 29 06:13:53 PM PDT 24
Peak memory 207100 kb
Host smart-8d24e861-2f6f-418c-8b07-4c56099d6ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40380
44230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.4038044230
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.721927715
Short name T2728
Test name
Test status
Simulation time 170643341 ps
CPU time 0.86 seconds
Started Jul 29 06:13:47 PM PDT 24
Finished Jul 29 06:13:48 PM PDT 24
Peak memory 207092 kb
Host smart-74ebe6e4-d93b-47cd-a826-04ebb5db7f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72192
7715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.721927715
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.1171374232
Short name T1680
Test name
Test status
Simulation time 145477267 ps
CPU time 0.88 seconds
Started Jul 29 06:13:48 PM PDT 24
Finished Jul 29 06:13:49 PM PDT 24
Peak memory 207048 kb
Host smart-26fbe7c3-b846-4295-80ac-96d0fc3382aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11713
74232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.1171374232
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.31266553
Short name T2408
Test name
Test status
Simulation time 153372234 ps
CPU time 0.87 seconds
Started Jul 29 06:13:52 PM PDT 24
Finished Jul 29 06:13:53 PM PDT 24
Peak memory 207088 kb
Host smart-80d5bce5-cc2b-4e01-bce9-e7774dab8331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31266
553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.31266553
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3857559251
Short name T2650
Test name
Test status
Simulation time 164319995 ps
CPU time 0.86 seconds
Started Jul 29 06:13:43 PM PDT 24
Finished Jul 29 06:13:44 PM PDT 24
Peak memory 207128 kb
Host smart-b6148a10-82a4-42b2-9014-48367e02be0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38575
59251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3857559251
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1565629106
Short name T578
Test name
Test status
Simulation time 220590255 ps
CPU time 1.01 seconds
Started Jul 29 06:13:51 PM PDT 24
Finished Jul 29 06:13:52 PM PDT 24
Peak memory 207100 kb
Host smart-01dff392-bd3f-4191-8c43-a27a1295443c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15656
29106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1565629106
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.1551531505
Short name T2078
Test name
Test status
Simulation time 5207294991 ps
CPU time 55.04 seconds
Started Jul 29 06:13:47 PM PDT 24
Finished Jul 29 06:14:42 PM PDT 24
Peak memory 217076 kb
Host smart-e6e91cac-2d2d-4db5-af15-bdb5de050774
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1551531505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.1551531505
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1846461698
Short name T2350
Test name
Test status
Simulation time 175393561 ps
CPU time 0.88 seconds
Started Jul 29 06:13:47 PM PDT 24
Finished Jul 29 06:13:48 PM PDT 24
Peak memory 207136 kb
Host smart-aab8155a-0301-448f-8dca-b553483d000a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18464
61698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1846461698
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.4099180097
Short name T2641
Test name
Test status
Simulation time 183805742 ps
CPU time 0.92 seconds
Started Jul 29 06:13:43 PM PDT 24
Finished Jul 29 06:13:45 PM PDT 24
Peak memory 207100 kb
Host smart-8660ee90-4923-4e78-864a-ad3ca7a2f3c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40991
80097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.4099180097
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1698483032
Short name T2342
Test name
Test status
Simulation time 847704927 ps
CPU time 2.03 seconds
Started Jul 29 06:13:43 PM PDT 24
Finished Jul 29 06:13:46 PM PDT 24
Peak memory 207256 kb
Host smart-4cfc226f-dc46-4762-99c4-211ca289c55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16984
83032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1698483032
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2583523447
Short name T656
Test name
Test status
Simulation time 4110333687 ps
CPU time 121.57 seconds
Started Jul 29 06:13:46 PM PDT 24
Finished Jul 29 06:15:47 PM PDT 24
Peak memory 215444 kb
Host smart-df067ac0-7779-4853-b24b-123dd837f153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25835
23447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2583523447
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.1236260531
Short name T2859
Test name
Test status
Simulation time 359388054 ps
CPU time 4.5 seconds
Started Jul 29 06:13:41 PM PDT 24
Finished Jul 29 06:13:46 PM PDT 24
Peak memory 207256 kb
Host smart-11074a79-a570-4ec2-8f38-5475c7e68996
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236260531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.1236260531
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.3007506339
Short name T2064
Test name
Test status
Simulation time 59869172 ps
CPU time 0.74 seconds
Started Jul 29 06:13:55 PM PDT 24
Finished Jul 29 06:13:56 PM PDT 24
Peak memory 207112 kb
Host smart-50ce3ff3-dbff-45d0-b2e1-362a54a39065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3007506339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.3007506339
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.2024527709
Short name T2819
Test name
Test status
Simulation time 4198141980 ps
CPU time 6.06 seconds
Started Jul 29 06:13:45 PM PDT 24
Finished Jul 29 06:13:51 PM PDT 24
Peak memory 207256 kb
Host smart-efcfae6d-755c-4522-997c-361b19b68ecc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024527709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.2024527709
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3357197001
Short name T219
Test name
Test status
Simulation time 13455533682 ps
CPU time 15.85 seconds
Started Jul 29 06:13:52 PM PDT 24
Finished Jul 29 06:14:08 PM PDT 24
Peak memory 207428 kb
Host smart-69152bf3-5e7a-4f09-8b60-a0b7223da774
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357197001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3357197001
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.272051848
Short name T1598
Test name
Test status
Simulation time 151660635 ps
CPU time 0.91 seconds
Started Jul 29 06:13:46 PM PDT 24
Finished Jul 29 06:13:47 PM PDT 24
Peak memory 207080 kb
Host smart-4a2f66d2-d0c5-43e1-aef6-912df5ef2c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27205
1848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.272051848
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.1716391671
Short name T2399
Test name
Test status
Simulation time 171853032 ps
CPU time 0.87 seconds
Started Jul 29 06:13:47 PM PDT 24
Finished Jul 29 06:13:48 PM PDT 24
Peak memory 207084 kb
Host smart-7b1541f9-7adb-4d5e-81a7-a9c19b6e0fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17163
91671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.1716391671
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.3752131061
Short name T1650
Test name
Test status
Simulation time 201719709 ps
CPU time 1.01 seconds
Started Jul 29 06:13:44 PM PDT 24
Finished Jul 29 06:13:45 PM PDT 24
Peak memory 207064 kb
Host smart-a0f59299-e45a-4214-9854-150fcbf98685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37521
31061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.3752131061
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.1722674132
Short name T2297
Test name
Test status
Simulation time 1024468319 ps
CPU time 2.51 seconds
Started Jul 29 06:13:42 PM PDT 24
Finished Jul 29 06:13:45 PM PDT 24
Peak memory 207296 kb
Host smart-a8aaecab-3fb3-4366-85fe-21678c7dfa4d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1722674132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.1722674132
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.1959827889
Short name T2631
Test name
Test status
Simulation time 10344575215 ps
CPU time 22 seconds
Started Jul 29 06:13:42 PM PDT 24
Finished Jul 29 06:14:04 PM PDT 24
Peak memory 207420 kb
Host smart-6aee8c14-8d6b-4fbd-9409-74a2afa1262c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19598
27889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.1959827889
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.2880525673
Short name T1290
Test name
Test status
Simulation time 3576543543 ps
CPU time 24.14 seconds
Started Jul 29 06:13:46 PM PDT 24
Finished Jul 29 06:14:10 PM PDT 24
Peak memory 207352 kb
Host smart-079ad5b4-ae21-41a4-b96e-560427350241
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880525673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.2880525673
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3460205397
Short name T1727
Test name
Test status
Simulation time 475872978 ps
CPU time 1.53 seconds
Started Jul 29 06:13:43 PM PDT 24
Finished Jul 29 06:13:44 PM PDT 24
Peak memory 207012 kb
Host smart-8e877115-91dc-405d-b9c9-a28109a22644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34602
05397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3460205397
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.4255246859
Short name T1452
Test name
Test status
Simulation time 167244934 ps
CPU time 0.85 seconds
Started Jul 29 06:13:52 PM PDT 24
Finished Jul 29 06:13:53 PM PDT 24
Peak memory 207068 kb
Host smart-1d0c4493-fbd9-4410-aad5-de2083739cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42552
46859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.4255246859
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.2409550982
Short name T2490
Test name
Test status
Simulation time 44220830 ps
CPU time 0.74 seconds
Started Jul 29 06:13:49 PM PDT 24
Finished Jul 29 06:13:50 PM PDT 24
Peak memory 207004 kb
Host smart-a750a0fa-1a4f-44f3-a940-db460421361d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24095
50982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2409550982
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1603230335
Short name T2348
Test name
Test status
Simulation time 969335110 ps
CPU time 2.5 seconds
Started Jul 29 06:13:49 PM PDT 24
Finished Jul 29 06:13:51 PM PDT 24
Peak memory 207216 kb
Host smart-49771eff-2574-4dfc-800d-776fcaae04e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16032
30335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1603230335
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.122941680
Short name T1472
Test name
Test status
Simulation time 160769517 ps
CPU time 1.56 seconds
Started Jul 29 06:13:48 PM PDT 24
Finished Jul 29 06:13:49 PM PDT 24
Peak memory 207268 kb
Host smart-c0cc5917-2135-4ce2-9000-591dfc02d586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12294
1680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.122941680
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2595795042
Short name T1965
Test name
Test status
Simulation time 267985287 ps
CPU time 1.19 seconds
Started Jul 29 06:13:49 PM PDT 24
Finished Jul 29 06:13:50 PM PDT 24
Peak memory 207288 kb
Host smart-aaee324b-3ba2-4bed-b766-f5133f7703d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2595795042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2595795042
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1886541104
Short name T2284
Test name
Test status
Simulation time 223342413 ps
CPU time 0.94 seconds
Started Jul 29 06:13:51 PM PDT 24
Finished Jul 29 06:13:52 PM PDT 24
Peak memory 207044 kb
Host smart-9ec9f857-c46d-4d85-9fa8-a6afb040fb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18865
41104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1886541104
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.4232261830
Short name T694
Test name
Test status
Simulation time 172952930 ps
CPU time 0.99 seconds
Started Jul 29 06:13:53 PM PDT 24
Finished Jul 29 06:13:54 PM PDT 24
Peak memory 207080 kb
Host smart-6919230c-e983-4704-a51f-3a153aabc333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42322
61830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.4232261830
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.4178810015
Short name T462
Test name
Test status
Simulation time 7937620084 ps
CPU time 71.45 seconds
Started Jul 29 06:13:52 PM PDT 24
Finished Jul 29 06:15:03 PM PDT 24
Peak memory 217120 kb
Host smart-9cf5ecdd-daea-4874-99ce-60ca7f22c34f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4178810015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.4178810015
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.2673268723
Short name T1038
Test name
Test status
Simulation time 6749262035 ps
CPU time 50.87 seconds
Started Jul 29 06:13:48 PM PDT 24
Finished Jul 29 06:14:39 PM PDT 24
Peak memory 207380 kb
Host smart-119ef5a4-81e5-4009-bb5b-2098762a1dc3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2673268723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.2673268723
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.1386386299
Short name T752
Test name
Test status
Simulation time 230082124 ps
CPU time 0.98 seconds
Started Jul 29 06:13:48 PM PDT 24
Finished Jul 29 06:13:50 PM PDT 24
Peak memory 207044 kb
Host smart-4037b65d-c696-484a-a564-ff547af24e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13863
86299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.1386386299
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.2195991053
Short name T1613
Test name
Test status
Simulation time 23365923303 ps
CPU time 29.24 seconds
Started Jul 29 06:13:49 PM PDT 24
Finished Jul 29 06:14:19 PM PDT 24
Peak memory 207416 kb
Host smart-c2dcfb85-f2b5-44aa-93fe-7a92ed7359d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21959
91053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.2195991053
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.2063206619
Short name T1563
Test name
Test status
Simulation time 3414816936 ps
CPU time 4.55 seconds
Started Jul 29 06:13:49 PM PDT 24
Finished Jul 29 06:13:53 PM PDT 24
Peak memory 207340 kb
Host smart-289697b0-9fa9-4c2b-aea0-f716ccf33924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20632
06619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2063206619
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.4288783913
Short name T2613
Test name
Test status
Simulation time 7713630509 ps
CPU time 223.92 seconds
Started Jul 29 06:13:52 PM PDT 24
Finished Jul 29 06:17:36 PM PDT 24
Peak memory 215656 kb
Host smart-e0819658-53ff-4a06-9555-b29c038019c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42887
83913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.4288783913
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.3061914550
Short name T2616
Test name
Test status
Simulation time 4917140364 ps
CPU time 144.53 seconds
Started Jul 29 06:13:52 PM PDT 24
Finished Jul 29 06:16:16 PM PDT 24
Peak memory 223488 kb
Host smart-97c0ab08-46f0-44d1-b049-30d400b1ad90
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3061914550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3061914550
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.3846167714
Short name T385
Test name
Test status
Simulation time 258348828 ps
CPU time 1 seconds
Started Jul 29 06:13:50 PM PDT 24
Finished Jul 29 06:13:51 PM PDT 24
Peak memory 207100 kb
Host smart-3e0d013c-816e-42d6-b515-0ca3845d488b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3846167714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.3846167714
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1356572381
Short name T1299
Test name
Test status
Simulation time 204530469 ps
CPU time 1 seconds
Started Jul 29 06:13:47 PM PDT 24
Finished Jul 29 06:13:49 PM PDT 24
Peak memory 207224 kb
Host smart-963df337-d3b3-4bb5-a059-8b3cdb943a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13565
72381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1356572381
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.1188754641
Short name T2104
Test name
Test status
Simulation time 6089278723 ps
CPU time 189.98 seconds
Started Jul 29 06:13:52 PM PDT 24
Finished Jul 29 06:17:02 PM PDT 24
Peak memory 215564 kb
Host smart-98936a40-480c-4566-b1cb-3d606eeaab0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11887
54641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.1188754641
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.3593675455
Short name T2622
Test name
Test status
Simulation time 5946338422 ps
CPU time 49.82 seconds
Started Jul 29 06:13:52 PM PDT 24
Finished Jul 29 06:14:43 PM PDT 24
Peak memory 207420 kb
Host smart-fb9395b6-9cfa-4502-97cc-8e35179485b3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3593675455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.3593675455
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.1024179017
Short name T456
Test name
Test status
Simulation time 200561523 ps
CPU time 0.91 seconds
Started Jul 29 06:13:51 PM PDT 24
Finished Jul 29 06:13:52 PM PDT 24
Peak memory 207252 kb
Host smart-6ff44aae-d4ee-4df7-a491-fe38ed453d8c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1024179017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.1024179017
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2421478853
Short name T1489
Test name
Test status
Simulation time 153544085 ps
CPU time 0.84 seconds
Started Jul 29 06:13:54 PM PDT 24
Finished Jul 29 06:13:55 PM PDT 24
Peak memory 207084 kb
Host smart-11ee7e99-bbd8-41fc-a3f2-272582babb07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24214
78853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2421478853
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1038226081
Short name T138
Test name
Test status
Simulation time 215776591 ps
CPU time 1.04 seconds
Started Jul 29 06:13:55 PM PDT 24
Finished Jul 29 06:13:57 PM PDT 24
Peak memory 207080 kb
Host smart-af89359b-10a3-4060-82e0-01a9ebc31bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10382
26081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1038226081
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.883428943
Short name T2380
Test name
Test status
Simulation time 160082112 ps
CPU time 0.89 seconds
Started Jul 29 06:13:56 PM PDT 24
Finished Jul 29 06:13:57 PM PDT 24
Peak memory 207056 kb
Host smart-7077eaca-6143-48bd-a09f-e20fddf37fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88342
8943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.883428943
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.532078401
Short name T1306
Test name
Test status
Simulation time 183378023 ps
CPU time 0.92 seconds
Started Jul 29 06:13:54 PM PDT 24
Finished Jul 29 06:13:55 PM PDT 24
Peak memory 207136 kb
Host smart-bc0311f3-edaf-4c6d-83ae-561ab873bffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53207
8401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.532078401
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1687810858
Short name T1354
Test name
Test status
Simulation time 168129385 ps
CPU time 0.88 seconds
Started Jul 29 06:13:56 PM PDT 24
Finished Jul 29 06:13:57 PM PDT 24
Peak memory 207104 kb
Host smart-c3d0ace2-c85d-4069-bb18-f0a5066c137e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16878
10858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1687810858
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.721617100
Short name T2174
Test name
Test status
Simulation time 157999260 ps
CPU time 0.86 seconds
Started Jul 29 06:13:56 PM PDT 24
Finished Jul 29 06:13:57 PM PDT 24
Peak memory 207076 kb
Host smart-614b778a-4e04-4d8e-92ee-99c5a265dac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72161
7100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.721617100
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.1640283367
Short name T2033
Test name
Test status
Simulation time 264629810 ps
CPU time 1.05 seconds
Started Jul 29 06:13:57 PM PDT 24
Finished Jul 29 06:13:58 PM PDT 24
Peak memory 207060 kb
Host smart-c4e8fe11-548c-402b-91c3-f3e19ea1ce7d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1640283367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1640283367
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2188999081
Short name T1724
Test name
Test status
Simulation time 184035557 ps
CPU time 0.88 seconds
Started Jul 29 06:13:56 PM PDT 24
Finished Jul 29 06:13:57 PM PDT 24
Peak memory 207080 kb
Host smart-4653a6e7-dc3b-4f2d-b352-96c38b534b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21889
99081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2188999081
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3040131410
Short name T2009
Test name
Test status
Simulation time 21629584664 ps
CPU time 52.62 seconds
Started Jul 29 06:13:55 PM PDT 24
Finished Jul 29 06:14:48 PM PDT 24
Peak memory 219992 kb
Host smart-33c6a7b9-9523-4f07-8d3e-61638acbce6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30401
31410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3040131410
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3254156012
Short name T716
Test name
Test status
Simulation time 201609380 ps
CPU time 1.02 seconds
Started Jul 29 06:13:55 PM PDT 24
Finished Jul 29 06:13:57 PM PDT 24
Peak memory 207048 kb
Host smart-0eeefe06-a424-467b-bc00-75bbe19d16fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32541
56012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3254156012
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3769921226
Short name T1917
Test name
Test status
Simulation time 183266754 ps
CPU time 0.95 seconds
Started Jul 29 06:13:54 PM PDT 24
Finished Jul 29 06:13:55 PM PDT 24
Peak memory 207072 kb
Host smart-a36434cb-9b8d-43af-a163-52f34ae2932b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37699
21226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3769921226
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.4292344578
Short name T816
Test name
Test status
Simulation time 278874845 ps
CPU time 0.96 seconds
Started Jul 29 06:13:53 PM PDT 24
Finished Jul 29 06:13:54 PM PDT 24
Peak memory 207092 kb
Host smart-d5d25a76-46d3-4bdb-9dcf-4b5b5cb09d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42923
44578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.4292344578
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.3164518872
Short name T2072
Test name
Test status
Simulation time 167804663 ps
CPU time 0.9 seconds
Started Jul 29 06:13:55 PM PDT 24
Finished Jul 29 06:13:56 PM PDT 24
Peak memory 207072 kb
Host smart-9bbe48d3-f891-4f6a-b10e-09091d21072e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31645
18872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.3164518872
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.1482293230
Short name T2767
Test name
Test status
Simulation time 153493691 ps
CPU time 0.86 seconds
Started Jul 29 06:13:56 PM PDT 24
Finished Jul 29 06:13:57 PM PDT 24
Peak memory 207044 kb
Host smart-97226481-bb3a-46d7-b758-496486159b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14822
93230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.1482293230
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1032074166
Short name T529
Test name
Test status
Simulation time 148767055 ps
CPU time 0.9 seconds
Started Jul 29 06:13:55 PM PDT 24
Finished Jul 29 06:13:56 PM PDT 24
Peak memory 207072 kb
Host smart-5396c309-c901-4a44-a87f-5782649d683e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10320
74166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1032074166
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.871038496
Short name T1377
Test name
Test status
Simulation time 146825384 ps
CPU time 0.83 seconds
Started Jul 29 06:13:56 PM PDT 24
Finished Jul 29 06:13:57 PM PDT 24
Peak memory 207060 kb
Host smart-70311ecc-9e11-4838-a359-72105a75f752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87103
8496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.871038496
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2963282025
Short name T1402
Test name
Test status
Simulation time 233028822 ps
CPU time 1.05 seconds
Started Jul 29 06:13:56 PM PDT 24
Finished Jul 29 06:13:57 PM PDT 24
Peak memory 207124 kb
Host smart-2bff3f90-5eac-44d5-a5ed-0c346ff29bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29632
82025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2963282025
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.3985430951
Short name T1261
Test name
Test status
Simulation time 5556014409 ps
CPU time 171.77 seconds
Started Jul 29 06:13:53 PM PDT 24
Finished Jul 29 06:16:45 PM PDT 24
Peak memory 215580 kb
Host smart-bfab38b3-ad0b-4b9c-b9b3-143cbc63ae08
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3985430951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.3985430951
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.329322262
Short name T944
Test name
Test status
Simulation time 190996618 ps
CPU time 0.99 seconds
Started Jul 29 06:13:58 PM PDT 24
Finished Jul 29 06:13:59 PM PDT 24
Peak memory 207048 kb
Host smart-39ef570b-362d-46eb-9b80-f753c2cba561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32932
2262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.329322262
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3500055103
Short name T2701
Test name
Test status
Simulation time 210190633 ps
CPU time 0.94 seconds
Started Jul 29 06:13:58 PM PDT 24
Finished Jul 29 06:13:59 PM PDT 24
Peak memory 207104 kb
Host smart-f1fd15b9-f20e-48c9-baa1-554fb0539570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35000
55103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3500055103
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2715506095
Short name T363
Test name
Test status
Simulation time 716314985 ps
CPU time 1.78 seconds
Started Jul 29 06:13:55 PM PDT 24
Finished Jul 29 06:13:57 PM PDT 24
Peak memory 207028 kb
Host smart-99b6bc96-e857-4552-a0e5-b636ec9bb9ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27155
06095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2715506095
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.1491437673
Short name T2532
Test name
Test status
Simulation time 5579384455 ps
CPU time 42.26 seconds
Started Jul 29 06:13:56 PM PDT 24
Finished Jul 29 06:14:38 PM PDT 24
Peak memory 207496 kb
Host smart-f8c2c9ce-50bd-48d9-8d35-b60d02696483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14914
37673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1491437673
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.2878320689
Short name T463
Test name
Test status
Simulation time 1044641661 ps
CPU time 22.93 seconds
Started Jul 29 06:13:47 PM PDT 24
Finished Jul 29 06:14:10 PM PDT 24
Peak memory 207332 kb
Host smart-1517dbac-5555-4ba6-a028-3febc3851ed4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878320689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.2878320689
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.3466893074
Short name T592
Test name
Test status
Simulation time 37019149 ps
CPU time 0.68 seconds
Started Jul 29 06:14:06 PM PDT 24
Finished Jul 29 06:14:07 PM PDT 24
Peak memory 207032 kb
Host smart-fd70b0c1-6a91-45ba-8d1d-f62e0e5b3625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3466893074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.3466893074
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2517860745
Short name T2019
Test name
Test status
Simulation time 4080929354 ps
CPU time 6.42 seconds
Started Jul 29 06:13:55 PM PDT 24
Finished Jul 29 06:14:01 PM PDT 24
Peak memory 207328 kb
Host smart-ba913374-2916-409a-b5b5-7f6f79468504
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517860745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.2517860745
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.3358066544
Short name T188
Test name
Test status
Simulation time 13310225707 ps
CPU time 16.28 seconds
Started Jul 29 06:13:55 PM PDT 24
Finished Jul 29 06:14:12 PM PDT 24
Peak memory 207292 kb
Host smart-d4d72e86-af01-4d8f-8818-eb8de2c3e088
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358066544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.3358066544
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2191944956
Short name T8
Test name
Test status
Simulation time 23323391769 ps
CPU time 29.39 seconds
Started Jul 29 06:13:58 PM PDT 24
Finished Jul 29 06:14:28 PM PDT 24
Peak memory 207400 kb
Host smart-ec5e1373-a0f2-4be3-b8f0-0565b8e21b00
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191944956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.2191944956
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1144931068
Short name T1966
Test name
Test status
Simulation time 143319591 ps
CPU time 0.92 seconds
Started Jul 29 06:13:58 PM PDT 24
Finished Jul 29 06:13:59 PM PDT 24
Peak memory 207084 kb
Host smart-c2a781ae-c5bd-46b0-b06c-061728e88905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11449
31068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1144931068
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.2580704886
Short name T1324
Test name
Test status
Simulation time 150871609 ps
CPU time 0.84 seconds
Started Jul 29 06:13:54 PM PDT 24
Finished Jul 29 06:13:55 PM PDT 24
Peak memory 207096 kb
Host smart-bb3891be-1a6a-4cb4-b683-63cd64050d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25807
04886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.2580704886
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1580767306
Short name T2028
Test name
Test status
Simulation time 344711899 ps
CPU time 1.33 seconds
Started Jul 29 06:13:58 PM PDT 24
Finished Jul 29 06:14:00 PM PDT 24
Peak memory 207024 kb
Host smart-28e7667d-dd71-4f88-a713-b4eabe04e14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15807
67306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1580767306
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2343012899
Short name T1812
Test name
Test status
Simulation time 806596858 ps
CPU time 2.21 seconds
Started Jul 29 06:14:01 PM PDT 24
Finished Jul 29 06:14:03 PM PDT 24
Peak memory 207280 kb
Host smart-7bbab04f-f09a-4644-beef-4725f8aea8c1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2343012899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2343012899
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3032085229
Short name T2231
Test name
Test status
Simulation time 6187145515 ps
CPU time 13.83 seconds
Started Jul 29 06:14:00 PM PDT 24
Finished Jul 29 06:14:14 PM PDT 24
Peak memory 207452 kb
Host smart-184acd19-68ea-43a4-b8a7-77e0dda70b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30320
85229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3032085229
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.3351029166
Short name T1332
Test name
Test status
Simulation time 298021049 ps
CPU time 4.64 seconds
Started Jul 29 06:14:05 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 207300 kb
Host smart-72dc564c-ad57-41c9-b158-45ee0427e2c6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351029166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.3351029166
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.2701744082
Short name T1293
Test name
Test status
Simulation time 441482251 ps
CPU time 1.5 seconds
Started Jul 29 06:14:00 PM PDT 24
Finished Jul 29 06:14:02 PM PDT 24
Peak memory 207008 kb
Host smart-0de0691e-6267-4343-845b-52e1840e3ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27017
44082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.2701744082
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.3651866855
Short name T719
Test name
Test status
Simulation time 160120088 ps
CPU time 0.81 seconds
Started Jul 29 06:14:05 PM PDT 24
Finished Jul 29 06:14:06 PM PDT 24
Peak memory 206948 kb
Host smart-fdc15d47-e798-4d1c-8403-a5eb99af4289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36518
66855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3651866855
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.3106267894
Short name T1537
Test name
Test status
Simulation time 99332810 ps
CPU time 0.83 seconds
Started Jul 29 06:14:00 PM PDT 24
Finished Jul 29 06:14:01 PM PDT 24
Peak memory 207064 kb
Host smart-0b43f1c1-02fc-4053-a33a-0129def7f826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31062
67894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3106267894
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.7618886
Short name T819
Test name
Test status
Simulation time 742705279 ps
CPU time 2.23 seconds
Started Jul 29 06:14:02 PM PDT 24
Finished Jul 29 06:14:04 PM PDT 24
Peak memory 207288 kb
Host smart-c634d031-86ea-47c3-b9ec-b5abbc6bd49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76188
86 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.7618886
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.695062046
Short name T1265
Test name
Test status
Simulation time 301642502 ps
CPU time 2.48 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:14:11 PM PDT 24
Peak memory 207236 kb
Host smart-a34bc148-f0cb-46e3-a911-4231dd4ece8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69506
2046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.695062046
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.284651714
Short name T771
Test name
Test status
Simulation time 208146735 ps
CPU time 1.1 seconds
Started Jul 29 06:14:02 PM PDT 24
Finished Jul 29 06:14:03 PM PDT 24
Peak memory 215464 kb
Host smart-f6e9d913-2889-4ab9-9156-26e024183b0b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=284651714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.284651714
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.289568596
Short name T1700
Test name
Test status
Simulation time 167641376 ps
CPU time 0.89 seconds
Started Jul 29 06:14:02 PM PDT 24
Finished Jul 29 06:14:03 PM PDT 24
Peak memory 207080 kb
Host smart-440809e3-7215-454a-908c-0a3536faf8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28956
8596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.289568596
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3854100846
Short name T618
Test name
Test status
Simulation time 202665682 ps
CPU time 0.93 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 207100 kb
Host smart-e6e60c2a-35c5-4426-b873-2c503c4382a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38541
00846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3854100846
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.240077374
Short name T113
Test name
Test status
Simulation time 9623113794 ps
CPU time 83.49 seconds
Started Jul 29 06:14:02 PM PDT 24
Finished Jul 29 06:15:26 PM PDT 24
Peak memory 215652 kb
Host smart-e26ac55b-012f-485c-9c7d-0569b5218926
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=240077374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.240077374
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.1794567865
Short name T1359
Test name
Test status
Simulation time 4333778176 ps
CPU time 53.09 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:15:01 PM PDT 24
Peak memory 207320 kb
Host smart-6da6e3f9-4257-4bf8-ac1a-5f59e52e3a2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1794567865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.1794567865
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1945260484
Short name T1737
Test name
Test status
Simulation time 232146937 ps
CPU time 1.03 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 207048 kb
Host smart-a64ad121-bfa7-43b8-9fd4-c874a74ab5b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19452
60484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1945260484
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.179587318
Short name T2195
Test name
Test status
Simulation time 23282864485 ps
CPU time 25.64 seconds
Started Jul 29 06:14:05 PM PDT 24
Finished Jul 29 06:14:30 PM PDT 24
Peak memory 207392 kb
Host smart-1524b3e7-5776-4a83-85e1-c94a3f0646a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17958
7318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.179587318
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.4072580946
Short name T1803
Test name
Test status
Simulation time 3315994449 ps
CPU time 5.62 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:14:13 PM PDT 24
Peak memory 207304 kb
Host smart-e9ded12b-950f-4d51-a1e5-9862ba3ececd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40725
80946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.4072580946
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.1543958423
Short name T943
Test name
Test status
Simulation time 6658132588 ps
CPU time 69.15 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:15:18 PM PDT 24
Peak memory 217232 kb
Host smart-39802cc6-5164-44dd-9c01-46752df9c21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15439
58423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.1543958423
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3401145905
Short name T1063
Test name
Test status
Simulation time 4500058038 ps
CPU time 36.73 seconds
Started Jul 29 06:14:00 PM PDT 24
Finished Jul 29 06:14:37 PM PDT 24
Peak memory 217100 kb
Host smart-c5a995c9-b314-492d-9f30-5038351c6736
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3401145905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3401145905
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.2434630553
Short name T2600
Test name
Test status
Simulation time 329255315 ps
CPU time 1.06 seconds
Started Jul 29 06:14:01 PM PDT 24
Finished Jul 29 06:14:02 PM PDT 24
Peak memory 207084 kb
Host smart-b9c2c36b-8674-48b0-b298-cc339ad15a5a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2434630553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.2434630553
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3520083514
Short name T110
Test name
Test status
Simulation time 205609756 ps
CPU time 1 seconds
Started Jul 29 06:14:07 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 207076 kb
Host smart-75059dac-ddc5-4371-b3ae-1cfbd7a33296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35200
83514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3520083514
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.771397313
Short name T1365
Test name
Test status
Simulation time 3280659432 ps
CPU time 33.37 seconds
Started Jul 29 06:14:09 PM PDT 24
Finished Jul 29 06:14:43 PM PDT 24
Peak memory 217080 kb
Host smart-ba4c67f8-68df-4d5a-96a3-d9fe42011362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77139
7313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.771397313
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.2894908040
Short name T429
Test name
Test status
Simulation time 158614633 ps
CPU time 0.88 seconds
Started Jul 29 06:14:06 PM PDT 24
Finished Jul 29 06:14:07 PM PDT 24
Peak memory 207136 kb
Host smart-a1537365-9dec-4497-83dc-ee34cd968c13
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2894908040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.2894908040
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3664331523
Short name T2075
Test name
Test status
Simulation time 144533940 ps
CPU time 0.81 seconds
Started Jul 29 06:14:01 PM PDT 24
Finished Jul 29 06:14:02 PM PDT 24
Peak memory 207072 kb
Host smart-eaa27664-10b7-4356-9ee5-0315c589bae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36643
31523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3664331523
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.4247243144
Short name T1374
Test name
Test status
Simulation time 172658156 ps
CPU time 0.89 seconds
Started Jul 29 06:14:00 PM PDT 24
Finished Jul 29 06:14:01 PM PDT 24
Peak memory 207096 kb
Host smart-cd374d2e-cc50-41ae-91a5-910cee36c3f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42472
43144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.4247243144
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3623698045
Short name T583
Test name
Test status
Simulation time 205816702 ps
CPU time 0.94 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 207104 kb
Host smart-42bee262-95f6-4dbb-88d7-978b4707820a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36236
98045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3623698045
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1065115708
Short name T435
Test name
Test status
Simulation time 152527849 ps
CPU time 0.93 seconds
Started Jul 29 06:14:03 PM PDT 24
Finished Jul 29 06:14:04 PM PDT 24
Peak memory 207104 kb
Host smart-83d0a3fe-9575-4237-8811-510c7142fa9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10651
15708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1065115708
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1160658337
Short name T2450
Test name
Test status
Simulation time 218974776 ps
CPU time 0.93 seconds
Started Jul 29 06:14:05 PM PDT 24
Finished Jul 29 06:14:06 PM PDT 24
Peak memory 207108 kb
Host smart-ec7cf2aa-114b-4f9b-a33e-20f4208de0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11606
58337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1160658337
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3725008920
Short name T891
Test name
Test status
Simulation time 134645502 ps
CPU time 0.85 seconds
Started Jul 29 06:14:01 PM PDT 24
Finished Jul 29 06:14:01 PM PDT 24
Peak memory 207096 kb
Host smart-f74d3972-573d-4316-ac77-db51874fbcaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37250
08920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3725008920
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2670629145
Short name T982
Test name
Test status
Simulation time 66145680 ps
CPU time 0.75 seconds
Started Jul 29 06:14:00 PM PDT 24
Finished Jul 29 06:14:01 PM PDT 24
Peak memory 207044 kb
Host smart-aec58ed0-6e6f-4191-ac4a-e77ddeb59b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26706
29145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2670629145
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3668631540
Short name T1557
Test name
Test status
Simulation time 18220292563 ps
CPU time 48.26 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:58 PM PDT 24
Peak memory 215544 kb
Host smart-4302476d-a6d2-40fa-a3ed-d7a116472240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36686
31540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3668631540
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1303981733
Short name T1007
Test name
Test status
Simulation time 173313611 ps
CPU time 0.9 seconds
Started Jul 29 06:14:13 PM PDT 24
Finished Jul 29 06:14:14 PM PDT 24
Peak memory 207076 kb
Host smart-88c5bf8c-1cf8-45c2-a732-5dd5bbbcc585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13039
81733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1303981733
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1888879405
Short name T843
Test name
Test status
Simulation time 203168580 ps
CPU time 0.96 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 207160 kb
Host smart-402b185b-baf9-4132-8d6b-1a0927c1d65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18888
79405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1888879405
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.2932374603
Short name T421
Test name
Test status
Simulation time 282328858 ps
CPU time 1.08 seconds
Started Jul 29 06:14:06 PM PDT 24
Finished Jul 29 06:14:07 PM PDT 24
Peak memory 207104 kb
Host smart-3f2578f7-8fa3-4711-8f4c-843fe6e0c423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29323
74603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.2932374603
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1859362068
Short name T913
Test name
Test status
Simulation time 234232119 ps
CPU time 0.99 seconds
Started Jul 29 06:14:07 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 207112 kb
Host smart-955d3ca1-3dcb-4b9c-8e07-2be29c185996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18593
62068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1859362068
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3977288287
Short name T972
Test name
Test status
Simulation time 149927489 ps
CPU time 0.83 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 207100 kb
Host smart-87bf1973-ab4a-43cd-a8cc-e5013eb8e557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39772
88287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3977288287
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3065129076
Short name T2548
Test name
Test status
Simulation time 150734973 ps
CPU time 0.84 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:11 PM PDT 24
Peak memory 207044 kb
Host smart-d6d66bec-c32b-43bc-bad9-91ad9ff315c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30651
29076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3065129076
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.631928167
Short name T1385
Test name
Test status
Simulation time 174368859 ps
CPU time 0.88 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 207136 kb
Host smart-879e1ad8-044d-491b-a0d8-9bc08014839f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63192
8167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.631928167
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3076360441
Short name T55
Test name
Test status
Simulation time 214410303 ps
CPU time 0.97 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:11 PM PDT 24
Peak memory 207020 kb
Host smart-6dcf9278-32e4-4629-bc25-f5d2b3f6cc2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30763
60441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3076360441
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2133451755
Short name T2661
Test name
Test status
Simulation time 6538066590 ps
CPU time 198.11 seconds
Started Jul 29 06:14:14 PM PDT 24
Finished Jul 29 06:17:33 PM PDT 24
Peak memory 215576 kb
Host smart-4875d4e5-8b46-4dfa-9694-f432523896e9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2133451755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2133451755
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3375254141
Short name T1488
Test name
Test status
Simulation time 157963684 ps
CPU time 0.85 seconds
Started Jul 29 06:14:07 PM PDT 24
Finished Jul 29 06:14:08 PM PDT 24
Peak memory 207088 kb
Host smart-bfa7cdf1-6607-4619-94dc-98dc17ee22d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33752
54141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3375254141
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.2739212589
Short name T1847
Test name
Test status
Simulation time 172055599 ps
CPU time 0.87 seconds
Started Jul 29 06:14:07 PM PDT 24
Finished Jul 29 06:14:08 PM PDT 24
Peak memory 207044 kb
Host smart-7702b6ca-6ef3-456e-a74a-5686750657e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27392
12589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2739212589
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.2218241011
Short name T1515
Test name
Test status
Simulation time 652382810 ps
CPU time 1.89 seconds
Started Jul 29 06:14:07 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 207048 kb
Host smart-b1dd2ac4-fec0-4745-9bc0-671d64da2165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22182
41011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2218241011
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3752124036
Short name T2125
Test name
Test status
Simulation time 5531622836 ps
CPU time 44.36 seconds
Started Jul 29 06:14:06 PM PDT 24
Finished Jul 29 06:14:50 PM PDT 24
Peak memory 216816 kb
Host smart-910c5844-4ee4-4d90-8a60-3bceffff1f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37521
24036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3752124036
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.3242858012
Short name T1985
Test name
Test status
Simulation time 627791934 ps
CPU time 5.39 seconds
Started Jul 29 06:14:00 PM PDT 24
Finished Jul 29 06:14:06 PM PDT 24
Peak memory 207284 kb
Host smart-37c47610-625b-4269-a5b1-32ce193b4a32
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242858012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.3242858012
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.8233903
Short name T2354
Test name
Test status
Simulation time 37511440 ps
CPU time 0.65 seconds
Started Jul 29 06:14:16 PM PDT 24
Finished Jul 29 06:14:17 PM PDT 24
Peak memory 207144 kb
Host smart-b9cd6c72-81ec-4771-88d7-4fd94e04ac04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=8233903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.8233903
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.4112437812
Short name T1605
Test name
Test status
Simulation time 4332414632 ps
CPU time 5.84 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:14:14 PM PDT 24
Peak memory 207300 kb
Host smart-689a7ed0-df60-4377-bf08-ad3afc99cc04
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112437812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.4112437812
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2139419273
Short name T2335
Test name
Test status
Simulation time 13340980309 ps
CPU time 15.08 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:25 PM PDT 24
Peak memory 207420 kb
Host smart-8b1bc0c6-c109-438a-b789-e1af2d61c85d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139419273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2139419273
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.325791094
Short name T1073
Test name
Test status
Simulation time 23303068758 ps
CPU time 29.7 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:40 PM PDT 24
Peak memory 207424 kb
Host smart-26965752-846c-4cdb-8be8-565964a96d80
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325791094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_ao
n_wake_resume.325791094
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3212987879
Short name T2149
Test name
Test status
Simulation time 229752416 ps
CPU time 1.03 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:11 PM PDT 24
Peak memory 207120 kb
Host smart-50936dfa-5ce0-46c6-ba50-165725361065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32129
87879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3212987879
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.456562824
Short name T2724
Test name
Test status
Simulation time 143848342 ps
CPU time 0.83 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:11 PM PDT 24
Peak memory 206948 kb
Host smart-a4bb1904-fd43-455e-b3ec-b94061b3b706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45656
2824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.456562824
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.3072485118
Short name T484
Test name
Test status
Simulation time 522251080 ps
CPU time 1.74 seconds
Started Jul 29 06:14:09 PM PDT 24
Finished Jul 29 06:14:11 PM PDT 24
Peak memory 207016 kb
Host smart-7459b553-f149-4a21-a3a5-b3674bba8e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30724
85118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.3072485118
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3275442813
Short name T1167
Test name
Test status
Simulation time 1091977708 ps
CPU time 2.64 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:13 PM PDT 24
Peak memory 207316 kb
Host smart-8b9dae6a-ff5e-49e4-8b82-e139f1d8e052
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3275442813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3275442813
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3853972361
Short name T1008
Test name
Test status
Simulation time 14918143882 ps
CPU time 33.83 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:44 PM PDT 24
Peak memory 207388 kb
Host smart-270293a6-7186-4ed7-909a-a9200a5b7d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38539
72361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3853972361
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.2258628651
Short name T1409
Test name
Test status
Simulation time 7266995946 ps
CPU time 53 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:15:01 PM PDT 24
Peak memory 207484 kb
Host smart-132b84bf-5a56-4006-b8bc-ce22e1c7fb6c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258628651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.2258628651
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3882690796
Short name T1701
Test name
Test status
Simulation time 383733948 ps
CPU time 1.34 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:14:10 PM PDT 24
Peak memory 207040 kb
Host smart-534bf35d-e0db-401d-9092-3ab6024ef136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38826
90796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3882690796
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.498857781
Short name T897
Test name
Test status
Simulation time 155284499 ps
CPU time 0.83 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:11 PM PDT 24
Peak memory 207092 kb
Host smart-37bd223a-8a91-434c-ac46-7bbde3a88092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49885
7781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.498857781
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3780630468
Short name T1895
Test name
Test status
Simulation time 53151282 ps
CPU time 0.72 seconds
Started Jul 29 06:14:09 PM PDT 24
Finished Jul 29 06:14:10 PM PDT 24
Peak memory 207048 kb
Host smart-7933fd6c-877c-4904-80eb-5d4c51aef2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37806
30468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3780630468
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.682702548
Short name T1363
Test name
Test status
Simulation time 1077347950 ps
CPU time 2.74 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:13 PM PDT 24
Peak memory 207344 kb
Host smart-0a29d404-acec-4379-b430-229a64f6e268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68270
2548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.682702548
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3028271548
Short name T727
Test name
Test status
Simulation time 156606305 ps
CPU time 1.56 seconds
Started Jul 29 06:14:08 PM PDT 24
Finished Jul 29 06:14:10 PM PDT 24
Peak memory 207152 kb
Host smart-3747b97d-fc64-4bd2-af84-4692f5250941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30282
71548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3028271548
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.2175890255
Short name T581
Test name
Test status
Simulation time 218006988 ps
CPU time 1.1 seconds
Started Jul 29 06:14:09 PM PDT 24
Finished Jul 29 06:14:10 PM PDT 24
Peak memory 207272 kb
Host smart-ad2a99ed-22dd-4eae-9cd9-b06cc969208d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2175890255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.2175890255
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3290691014
Short name T1141
Test name
Test status
Simulation time 150364333 ps
CPU time 0.81 seconds
Started Jul 29 06:14:06 PM PDT 24
Finished Jul 29 06:14:07 PM PDT 24
Peak memory 207076 kb
Host smart-df356546-5e97-4785-9ce6-9cedbdc732e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32906
91014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3290691014
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2889659926
Short name T2454
Test name
Test status
Simulation time 235783509 ps
CPU time 1.03 seconds
Started Jul 29 06:14:09 PM PDT 24
Finished Jul 29 06:14:10 PM PDT 24
Peak memory 206984 kb
Host smart-329f16f8-1c27-402d-90b2-760e015797eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28896
59926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2889659926
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.3906505444
Short name T2294
Test name
Test status
Simulation time 7566641041 ps
CPU time 76.81 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:15:27 PM PDT 24
Peak memory 217232 kb
Host smart-7a80abe4-bdec-4c59-ba06-9c01e62b56b0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3906505444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.3906505444
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.1547352180
Short name T2403
Test name
Test status
Simulation time 6463285086 ps
CPU time 80.87 seconds
Started Jul 29 06:14:09 PM PDT 24
Finished Jul 29 06:15:30 PM PDT 24
Peak memory 207360 kb
Host smart-15d75cb6-08fb-4fbe-9471-f35cc707a5db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1547352180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.1547352180
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2586367270
Short name T1109
Test name
Test status
Simulation time 234381332 ps
CPU time 1.05 seconds
Started Jul 29 06:14:14 PM PDT 24
Finished Jul 29 06:14:16 PM PDT 24
Peak memory 207228 kb
Host smart-1337e5c3-008e-4ea0-abeb-cb32f59e3f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25863
67270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2586367270
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.310777637
Short name T1692
Test name
Test status
Simulation time 23289729286 ps
CPU time 28.97 seconds
Started Jul 29 06:14:09 PM PDT 24
Finished Jul 29 06:14:38 PM PDT 24
Peak memory 207412 kb
Host smart-ba648b82-9910-43be-8bb9-494b2cfdffaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31077
7637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.310777637
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1296665739
Short name T2007
Test name
Test status
Simulation time 3359837567 ps
CPU time 4.58 seconds
Started Jul 29 06:14:15 PM PDT 24
Finished Jul 29 06:14:20 PM PDT 24
Peak memory 207324 kb
Host smart-a71cdb40-1235-49bd-a9ce-e54bf151bd31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12966
65739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1296665739
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.1948174925
Short name T487
Test name
Test status
Simulation time 6396056697 ps
CPU time 48.76 seconds
Started Jul 29 06:14:14 PM PDT 24
Finished Jul 29 06:15:02 PM PDT 24
Peak memory 217044 kb
Host smart-a85cb6a3-2a33-4d32-bd4f-18a8611e6d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19481
74925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.1948174925
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.2570556693
Short name T2646
Test name
Test status
Simulation time 4733129517 ps
CPU time 142.37 seconds
Started Jul 29 06:14:17 PM PDT 24
Finished Jul 29 06:16:40 PM PDT 24
Peak memory 215576 kb
Host smart-7a4c1eca-8900-4754-8f6e-3b153d8bcbdc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2570556693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.2570556693
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.301448641
Short name T2201
Test name
Test status
Simulation time 244325030 ps
CPU time 1 seconds
Started Jul 29 06:14:13 PM PDT 24
Finished Jul 29 06:14:14 PM PDT 24
Peak memory 207124 kb
Host smart-bab025f1-4e87-4d05-9cfa-4e5e29df02fd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=301448641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.301448641
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.34540251
Short name T920
Test name
Test status
Simulation time 235499414 ps
CPU time 1.03 seconds
Started Jul 29 06:14:16 PM PDT 24
Finished Jul 29 06:14:17 PM PDT 24
Peak memory 207060 kb
Host smart-e4675b4b-2b22-45f2-aaf8-94075fbdb41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34540
251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.34540251
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.4175902282
Short name T681
Test name
Test status
Simulation time 5227568276 ps
CPU time 152.67 seconds
Started Jul 29 06:14:11 PM PDT 24
Finished Jul 29 06:16:44 PM PDT 24
Peak memory 215560 kb
Host smart-040d3ec6-805a-4c3e-9885-304b37389213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41759
02282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.4175902282
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.645422466
Short name T1103
Test name
Test status
Simulation time 3373389973 ps
CPU time 28.16 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:39 PM PDT 24
Peak memory 215580 kb
Host smart-98517960-5dca-4328-9a04-b744ec1c9c0b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=645422466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.645422466
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.808331547
Short name T1686
Test name
Test status
Simulation time 197006624 ps
CPU time 0.89 seconds
Started Jul 29 06:14:15 PM PDT 24
Finished Jul 29 06:14:16 PM PDT 24
Peak memory 207072 kb
Host smart-6d554f47-d9ae-49f8-877a-ac1a862fdf1d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=808331547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.808331547
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1267269216
Short name T2326
Test name
Test status
Simulation time 164463021 ps
CPU time 0.83 seconds
Started Jul 29 06:14:10 PM PDT 24
Finished Jul 29 06:14:11 PM PDT 24
Peak memory 207096 kb
Host smart-0ef040d6-1e0c-4430-8bad-09c07c0488c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12672
69216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1267269216
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1656116564
Short name T1848
Test name
Test status
Simulation time 167760111 ps
CPU time 0.93 seconds
Started Jul 29 06:14:14 PM PDT 24
Finished Jul 29 06:14:15 PM PDT 24
Peak memory 207216 kb
Host smart-95301879-3c80-4921-a887-e8fd05fa4cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16561
16564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1656116564
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2251770790
Short name T2412
Test name
Test status
Simulation time 149476482 ps
CPU time 0.82 seconds
Started Jul 29 06:14:12 PM PDT 24
Finished Jul 29 06:14:13 PM PDT 24
Peak memory 207136 kb
Host smart-a750d579-88c2-4c69-ae7e-e00bd293b8a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22517
70790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2251770790
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2952916460
Short name T1957
Test name
Test status
Simulation time 157206960 ps
CPU time 0.83 seconds
Started Jul 29 06:14:15 PM PDT 24
Finished Jul 29 06:14:16 PM PDT 24
Peak memory 207076 kb
Host smart-aa5b515a-67ec-4687-b9e4-8b919895409e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29529
16460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2952916460
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2764001923
Short name T2346
Test name
Test status
Simulation time 163105020 ps
CPU time 0.94 seconds
Started Jul 29 06:14:13 PM PDT 24
Finished Jul 29 06:14:14 PM PDT 24
Peak memory 207112 kb
Host smart-8edba210-86d1-42c2-b006-31ab7cee213d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27640
01923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2764001923
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.2683875675
Short name T2562
Test name
Test status
Simulation time 217748399 ps
CPU time 1.04 seconds
Started Jul 29 06:14:16 PM PDT 24
Finished Jul 29 06:14:17 PM PDT 24
Peak memory 207120 kb
Host smart-418c55d8-c591-4175-ae2e-2d0003335126
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2683875675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.2683875675
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.613820503
Short name T1530
Test name
Test status
Simulation time 140632828 ps
CPU time 0.83 seconds
Started Jul 29 06:14:13 PM PDT 24
Finished Jul 29 06:14:14 PM PDT 24
Peak memory 207020 kb
Host smart-4c592a2a-6b72-4814-9c48-6f5082fd0f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61382
0503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.613820503
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3358278744
Short name T1202
Test name
Test status
Simulation time 59880249 ps
CPU time 0.73 seconds
Started Jul 29 06:14:16 PM PDT 24
Finished Jul 29 06:14:17 PM PDT 24
Peak memory 207032 kb
Host smart-746260b5-2f7d-4255-a50b-0c12d32a7daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33582
78744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3358278744
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2701490103
Short name T1121
Test name
Test status
Simulation time 21425377070 ps
CPU time 54.49 seconds
Started Jul 29 06:14:11 PM PDT 24
Finished Jul 29 06:15:06 PM PDT 24
Peak memory 215568 kb
Host smart-04fbf453-6b61-43b7-9c65-a698a93f9d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27014
90103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2701490103
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1421173439
Short name T948
Test name
Test status
Simulation time 215786093 ps
CPU time 1 seconds
Started Jul 29 06:14:15 PM PDT 24
Finished Jul 29 06:14:16 PM PDT 24
Peak memory 207060 kb
Host smart-66aec513-3b4c-48e9-b3c1-d8aba2df7b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14211
73439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1421173439
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.3552300596
Short name T639
Test name
Test status
Simulation time 250575126 ps
CPU time 1.06 seconds
Started Jul 29 06:14:19 PM PDT 24
Finished Jul 29 06:14:20 PM PDT 24
Peak memory 207064 kb
Host smart-47bed75b-881d-4066-b927-b44d690e4c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35523
00596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.3552300596
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.2740784022
Short name T2113
Test name
Test status
Simulation time 191999408 ps
CPU time 0.94 seconds
Started Jul 29 06:14:15 PM PDT 24
Finished Jul 29 06:14:17 PM PDT 24
Peak memory 207100 kb
Host smart-8b805436-fe9c-480f-a187-0f99f54c8558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27407
84022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.2740784022
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3782652625
Short name T1751
Test name
Test status
Simulation time 221020090 ps
CPU time 0.94 seconds
Started Jul 29 06:14:15 PM PDT 24
Finished Jul 29 06:14:16 PM PDT 24
Peak memory 207084 kb
Host smart-cb767833-a62a-4da3-a482-08bf21ce47b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37826
52625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3782652625
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.462412080
Short name T1679
Test name
Test status
Simulation time 163095042 ps
CPU time 0.9 seconds
Started Jul 29 06:14:13 PM PDT 24
Finished Jul 29 06:14:14 PM PDT 24
Peak memory 207048 kb
Host smart-13f52f88-0b1e-433d-a155-c9fc8960abaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46241
2080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.462412080
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2551086925
Short name T1270
Test name
Test status
Simulation time 145386820 ps
CPU time 0.88 seconds
Started Jul 29 06:14:12 PM PDT 24
Finished Jul 29 06:14:13 PM PDT 24
Peak memory 207044 kb
Host smart-3c70baba-0368-4551-b858-a71c3e89d14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25510
86925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2551086925
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2630266902
Short name T1181
Test name
Test status
Simulation time 206793908 ps
CPU time 1.06 seconds
Started Jul 29 06:14:20 PM PDT 24
Finished Jul 29 06:14:21 PM PDT 24
Peak memory 207064 kb
Host smart-250b9c66-4db8-4b1a-aeeb-3c04bfc18094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26302
66902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2630266902
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.2389973545
Short name T297
Test name
Test status
Simulation time 4818454934 ps
CPU time 145.92 seconds
Started Jul 29 06:14:16 PM PDT 24
Finished Jul 29 06:16:42 PM PDT 24
Peak memory 215588 kb
Host smart-295ec461-efa6-4981-9c0e-b91c8eab05de
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2389973545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.2389973545
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1084300544
Short name T1019
Test name
Test status
Simulation time 199558993 ps
CPU time 0.9 seconds
Started Jul 29 06:14:14 PM PDT 24
Finished Jul 29 06:14:16 PM PDT 24
Peak memory 207072 kb
Host smart-9362f6e1-bfbf-4859-8e9e-e00169c3a526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10843
00544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1084300544
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.867532937
Short name T2092
Test name
Test status
Simulation time 199790019 ps
CPU time 0.92 seconds
Started Jul 29 06:14:18 PM PDT 24
Finished Jul 29 06:14:19 PM PDT 24
Peak memory 207052 kb
Host smart-f3aff698-5f71-4c45-a93e-095ca1637af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86753
2937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.867532937
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3651296015
Short name T1123
Test name
Test status
Simulation time 989553687 ps
CPU time 2.46 seconds
Started Jul 29 06:14:17 PM PDT 24
Finished Jul 29 06:14:20 PM PDT 24
Peak memory 207264 kb
Host smart-dea8ce94-aab0-466e-b0c6-a605161045f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36512
96015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3651296015
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.1551414380
Short name T1203
Test name
Test status
Simulation time 5574383294 ps
CPU time 43.11 seconds
Started Jul 29 06:14:14 PM PDT 24
Finished Jul 29 06:14:57 PM PDT 24
Peak memory 207384 kb
Host smart-9e660a90-1ed7-48c8-b249-743ba5f88a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15514
14380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.1551414380
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.3559645885
Short name T2722
Test name
Test status
Simulation time 7020473208 ps
CPU time 47.85 seconds
Started Jul 29 06:14:07 PM PDT 24
Finished Jul 29 06:14:55 PM PDT 24
Peak memory 207420 kb
Host smart-32a59480-2912-4a70-a348-9e95edbff321
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559645885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_hos
t_handshake.3559645885
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.3075524134
Short name T2717
Test name
Test status
Simulation time 39409707 ps
CPU time 0.8 seconds
Started Jul 29 06:14:32 PM PDT 24
Finished Jul 29 06:14:33 PM PDT 24
Peak memory 207148 kb
Host smart-ad02ed69-8f92-4d32-afdd-8bd4c27223de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3075524134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3075524134
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1086880208
Short name T1229
Test name
Test status
Simulation time 4199508432 ps
CPU time 6.12 seconds
Started Jul 29 06:14:14 PM PDT 24
Finished Jul 29 06:14:20 PM PDT 24
Peak memory 207356 kb
Host smart-c7cb91b7-2d97-4829-bd27-23b9a0e8874b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086880208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.1086880208
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3512047446
Short name T1743
Test name
Test status
Simulation time 13380675630 ps
CPU time 15.35 seconds
Started Jul 29 06:14:15 PM PDT 24
Finished Jul 29 06:14:30 PM PDT 24
Peak memory 207432 kb
Host smart-aa42d2df-977f-4953-81e8-d9fda58030bf
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512047446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3512047446
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.1526034365
Short name T1312
Test name
Test status
Simulation time 23363239817 ps
CPU time 31.94 seconds
Started Jul 29 06:14:14 PM PDT 24
Finished Jul 29 06:14:46 PM PDT 24
Peak memory 207456 kb
Host smart-14873b79-1b84-4a4c-9103-6bf1c10f777a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526034365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_resume.1526034365
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.368591288
Short name T1413
Test name
Test status
Simulation time 151253916 ps
CPU time 0.84 seconds
Started Jul 29 06:14:21 PM PDT 24
Finished Jul 29 06:14:22 PM PDT 24
Peak memory 207100 kb
Host smart-7433d493-5874-41b2-abe4-df999259980b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859
1288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.368591288
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.390720173
Short name T2678
Test name
Test status
Simulation time 156636176 ps
CPU time 0.86 seconds
Started Jul 29 06:14:23 PM PDT 24
Finished Jul 29 06:14:24 PM PDT 24
Peak memory 207064 kb
Host smart-d78382ed-416f-4cdf-a84e-9b84298af3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39072
0173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.390720173
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.254660529
Short name T1630
Test name
Test status
Simulation time 446404903 ps
CPU time 1.52 seconds
Started Jul 29 06:14:18 PM PDT 24
Finished Jul 29 06:14:20 PM PDT 24
Peak memory 207012 kb
Host smart-8f8bac95-ec3b-4dc7-959b-4544df82e718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25466
0529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.254660529
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1093548590
Short name T371
Test name
Test status
Simulation time 1484730387 ps
CPU time 3.52 seconds
Started Jul 29 06:14:21 PM PDT 24
Finished Jul 29 06:14:25 PM PDT 24
Peak memory 207340 kb
Host smart-33afcf0e-b20c-4dd9-a224-4cbcac495d28
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1093548590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1093548590
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.1705114948
Short name T294
Test name
Test status
Simulation time 8487814330 ps
CPU time 19.64 seconds
Started Jul 29 06:14:17 PM PDT 24
Finished Jul 29 06:14:37 PM PDT 24
Peak memory 207420 kb
Host smart-cdf0d219-4de8-41f2-8b1a-ff36c0145063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17051
14948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.1705114948
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.3378786729
Short name T591
Test name
Test status
Simulation time 1548650769 ps
CPU time 14.17 seconds
Started Jul 29 06:14:16 PM PDT 24
Finished Jul 29 06:14:31 PM PDT 24
Peak memory 207292 kb
Host smart-55c935ae-947b-472f-95c9-8e5f51791c43
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378786729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.3378786729
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.2824461591
Short name T896
Test name
Test status
Simulation time 500031565 ps
CPU time 1.67 seconds
Started Jul 29 06:14:17 PM PDT 24
Finished Jul 29 06:14:19 PM PDT 24
Peak memory 207064 kb
Host smart-e5803d04-13ea-48ba-911a-4d51ed5b0ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28244
61591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.2824461591
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.801290483
Short name T2673
Test name
Test status
Simulation time 222494062 ps
CPU time 1.01 seconds
Started Jul 29 06:14:17 PM PDT 24
Finished Jul 29 06:14:19 PM PDT 24
Peak memory 207100 kb
Host smart-86f45c77-7a7d-417c-ae29-7b6b024d7c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80129
0483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.801290483
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.3452294369
Short name T1274
Test name
Test status
Simulation time 36632521 ps
CPU time 0.68 seconds
Started Jul 29 06:14:19 PM PDT 24
Finished Jul 29 06:14:20 PM PDT 24
Peak memory 207044 kb
Host smart-38be6b44-b34a-44e9-b167-09df24d22716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34522
94369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3452294369
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.990925552
Short name T2848
Test name
Test status
Simulation time 877949368 ps
CPU time 2.52 seconds
Started Jul 29 06:14:28 PM PDT 24
Finished Jul 29 06:14:31 PM PDT 24
Peak memory 207328 kb
Host smart-fa90d00d-c54c-4e49-a465-49d12ac5711f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99092
5552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.990925552
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.747312412
Short name T2055
Test name
Test status
Simulation time 231739255 ps
CPU time 1.79 seconds
Started Jul 29 06:14:28 PM PDT 24
Finished Jul 29 06:14:30 PM PDT 24
Peak memory 207224 kb
Host smart-de0e6bff-2922-4c22-acff-77d9bde8783f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74731
2412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.747312412
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1801512472
Short name T1799
Test name
Test status
Simulation time 252903280 ps
CPU time 1.19 seconds
Started Jul 29 06:14:28 PM PDT 24
Finished Jul 29 06:14:30 PM PDT 24
Peak memory 207284 kb
Host smart-1b25bc2b-02ba-4500-8a79-85e0182e301c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1801512472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1801512472
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3051305089
Short name T1954
Test name
Test status
Simulation time 137085935 ps
CPU time 0.8 seconds
Started Jul 29 06:14:23 PM PDT 24
Finished Jul 29 06:14:24 PM PDT 24
Peak memory 207088 kb
Host smart-d538e4e7-a427-4db4-a0d0-032bb2a5a4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30513
05089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3051305089
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2517748772
Short name T2648
Test name
Test status
Simulation time 214096501 ps
CPU time 0.96 seconds
Started Jul 29 06:14:28 PM PDT 24
Finished Jul 29 06:14:29 PM PDT 24
Peak memory 207076 kb
Host smart-4f44fc76-c68f-4761-9bc7-f5d2958d7539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25177
48772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2517748772
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.3473282458
Short name T1427
Test name
Test status
Simulation time 5738875077 ps
CPU time 59.91 seconds
Started Jul 29 06:14:23 PM PDT 24
Finished Jul 29 06:15:23 PM PDT 24
Peak memory 216960 kb
Host smart-9d8d6982-4125-4a02-8e34-02067cd59aba
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3473282458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.3473282458
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.3892047732
Short name T1842
Test name
Test status
Simulation time 14180298766 ps
CPU time 87.67 seconds
Started Jul 29 06:14:19 PM PDT 24
Finished Jul 29 06:15:47 PM PDT 24
Peak memory 207316 kb
Host smart-61298db2-68c4-4f7a-8e59-cede7767e1f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3892047732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.3892047732
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.368774257
Short name T1878
Test name
Test status
Simulation time 214261781 ps
CPU time 1 seconds
Started Jul 29 06:14:20 PM PDT 24
Finished Jul 29 06:14:21 PM PDT 24
Peak memory 207124 kb
Host smart-2e32dc5e-1048-4a08-be9c-64545d4a3e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36877
4257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.368774257
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.2513135229
Short name T1823
Test name
Test status
Simulation time 23307678356 ps
CPU time 34.95 seconds
Started Jul 29 06:14:28 PM PDT 24
Finished Jul 29 06:15:03 PM PDT 24
Peak memory 207412 kb
Host smart-7c4a0cca-f700-4969-9192-192a04bafd40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25131
35229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.2513135229
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.3214891176
Short name T1902
Test name
Test status
Simulation time 3335480877 ps
CPU time 5.12 seconds
Started Jul 29 06:14:18 PM PDT 24
Finished Jul 29 06:14:24 PM PDT 24
Peak memory 207392 kb
Host smart-0dc52945-2698-4794-971f-a44281fa122e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32148
91176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3214891176
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.1970963797
Short name T494
Test name
Test status
Simulation time 6225579415 ps
CPU time 47.28 seconds
Started Jul 29 06:14:26 PM PDT 24
Finished Jul 29 06:15:13 PM PDT 24
Peak memory 218156 kb
Host smart-a516a4b7-f36f-4d73-9594-ef7916cb42f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19709
63797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.1970963797
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1348694295
Short name T1277
Test name
Test status
Simulation time 5406622493 ps
CPU time 164.37 seconds
Started Jul 29 06:14:22 PM PDT 24
Finished Jul 29 06:17:07 PM PDT 24
Peak memory 215532 kb
Host smart-f8ce5fcc-06ab-4509-a2af-3b8beea33914
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1348694295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1348694295
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3291024475
Short name T715
Test name
Test status
Simulation time 233162907 ps
CPU time 0.96 seconds
Started Jul 29 06:14:26 PM PDT 24
Finished Jul 29 06:14:27 PM PDT 24
Peak memory 206868 kb
Host smart-8ce325a4-d691-41b4-ba4d-55335a45799f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3291024475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3291024475
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1052512172
Short name T2245
Test name
Test status
Simulation time 196113598 ps
CPU time 0.99 seconds
Started Jul 29 06:14:21 PM PDT 24
Finished Jul 29 06:14:22 PM PDT 24
Peak memory 207084 kb
Host smart-fd9804fb-9fb4-4b61-8ca6-978444be199a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10525
12172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1052512172
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.3699395094
Short name T852
Test name
Test status
Simulation time 4743503368 ps
CPU time 37.32 seconds
Started Jul 29 06:14:21 PM PDT 24
Finished Jul 29 06:14:58 PM PDT 24
Peak memory 217016 kb
Host smart-abb4eac5-a10d-48f3-8211-abc38d9944c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36993
95094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.3699395094
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1143146645
Short name T659
Test name
Test status
Simulation time 4056741674 ps
CPU time 111.51 seconds
Started Jul 29 06:14:21 PM PDT 24
Finished Jul 29 06:16:12 PM PDT 24
Peak memory 215528 kb
Host smart-70b5ef2c-5304-4e6f-85ad-023785b859cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1143146645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1143146645
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.3267169110
Short name T950
Test name
Test status
Simulation time 198120828 ps
CPU time 0.86 seconds
Started Jul 29 06:14:28 PM PDT 24
Finished Jul 29 06:14:29 PM PDT 24
Peak memory 207080 kb
Host smart-0b7abafe-31b1-4d02-9ef1-4f7ca08cd729
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3267169110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.3267169110
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.964539089
Short name T1857
Test name
Test status
Simulation time 190877856 ps
CPU time 0.94 seconds
Started Jul 29 06:14:24 PM PDT 24
Finished Jul 29 06:14:25 PM PDT 24
Peak memory 207048 kb
Host smart-8b267f84-e104-4e9d-83b6-99389a81737e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96453
9089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.964539089
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1160501784
Short name T1714
Test name
Test status
Simulation time 196465009 ps
CPU time 0.96 seconds
Started Jul 29 06:14:25 PM PDT 24
Finished Jul 29 06:14:26 PM PDT 24
Peak memory 207080 kb
Host smart-a211eda2-7eb1-4aa0-9114-bb93b912139a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11605
01784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1160501784
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.434417749
Short name T1329
Test name
Test status
Simulation time 236038260 ps
CPU time 0.98 seconds
Started Jul 29 06:14:26 PM PDT 24
Finished Jul 29 06:14:27 PM PDT 24
Peak memory 206868 kb
Host smart-14887309-fe1f-484b-98fc-e205860e273f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43441
7749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.434417749
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3815522251
Short name T1347
Test name
Test status
Simulation time 200009807 ps
CPU time 0.96 seconds
Started Jul 29 06:14:25 PM PDT 24
Finished Jul 29 06:14:26 PM PDT 24
Peak memory 206852 kb
Host smart-9bb2266c-da5b-4f76-a991-3113182bdf65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38155
22251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3815522251
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1830756590
Short name T2228
Test name
Test status
Simulation time 152495766 ps
CPU time 0.93 seconds
Started Jul 29 06:14:26 PM PDT 24
Finished Jul 29 06:14:27 PM PDT 24
Peak memory 207096 kb
Host smart-dc6bee1a-2efb-49f2-beea-d8915ca37196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18307
56590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1830756590
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.3487830187
Short name T2692
Test name
Test status
Simulation time 195802860 ps
CPU time 1 seconds
Started Jul 29 06:14:30 PM PDT 24
Finished Jul 29 06:14:31 PM PDT 24
Peak memory 207096 kb
Host smart-7ee8b7d7-cf12-44a1-be9c-a01278ce2ea3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3487830187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.3487830187
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3373409430
Short name T2853
Test name
Test status
Simulation time 150843762 ps
CPU time 0.81 seconds
Started Jul 29 06:14:26 PM PDT 24
Finished Jul 29 06:14:27 PM PDT 24
Peak memory 207080 kb
Host smart-5ed136b8-0bc5-4d48-8da4-410470606f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33734
09430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3373409430
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2502740155
Short name T38
Test name
Test status
Simulation time 39707055 ps
CPU time 0.68 seconds
Started Jul 29 06:14:28 PM PDT 24
Finished Jul 29 06:14:29 PM PDT 24
Peak memory 206996 kb
Host smart-98a301c9-1fa5-4060-9dac-acb68815681d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25027
40155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2502740155
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.3979738427
Short name T2738
Test name
Test status
Simulation time 225852439 ps
CPU time 1.04 seconds
Started Jul 29 06:14:32 PM PDT 24
Finished Jul 29 06:14:33 PM PDT 24
Peak memory 207120 kb
Host smart-90fe126e-7757-4136-be87-0efab16ccb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39797
38427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.3979738427
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2478293461
Short name T2001
Test name
Test status
Simulation time 177179420 ps
CPU time 0.87 seconds
Started Jul 29 06:14:28 PM PDT 24
Finished Jul 29 06:14:29 PM PDT 24
Peak memory 207108 kb
Host smart-d758cd12-7e92-45da-af23-b287e5879eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24782
93461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2478293461
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1473113255
Short name T2587
Test name
Test status
Simulation time 251023288 ps
CPU time 0.99 seconds
Started Jul 29 06:14:25 PM PDT 24
Finished Jul 29 06:14:26 PM PDT 24
Peak memory 207044 kb
Host smart-f7ad55fe-bda8-4b99-884e-7b6cfd78cbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14731
13255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1473113255
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.365944769
Short name T2694
Test name
Test status
Simulation time 199313782 ps
CPU time 0.97 seconds
Started Jul 29 06:14:25 PM PDT 24
Finished Jul 29 06:14:26 PM PDT 24
Peak memory 207264 kb
Host smart-83a810ec-96ef-4bfc-9726-53b237e021d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36594
4769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.365944769
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.4169257335
Short name T2658
Test name
Test status
Simulation time 190607573 ps
CPU time 0.89 seconds
Started Jul 29 06:14:27 PM PDT 24
Finished Jul 29 06:14:28 PM PDT 24
Peak memory 207028 kb
Host smart-6fc71302-c291-4b01-8828-acd70a19b52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41692
57335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.4169257335
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2910817391
Short name T994
Test name
Test status
Simulation time 166503548 ps
CPU time 0.93 seconds
Started Jul 29 06:14:32 PM PDT 24
Finished Jul 29 06:14:33 PM PDT 24
Peak memory 207088 kb
Host smart-49d4e36c-990b-4b02-a930-5fb75c9e225e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29108
17391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2910817391
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2588568202
Short name T1649
Test name
Test status
Simulation time 184242473 ps
CPU time 0.89 seconds
Started Jul 29 06:14:30 PM PDT 24
Finished Jul 29 06:14:31 PM PDT 24
Peak memory 207232 kb
Host smart-aa2aed79-8450-48e5-98ff-eb22b1184130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25885
68202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2588568202
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.536932101
Short name T1636
Test name
Test status
Simulation time 214682078 ps
CPU time 0.96 seconds
Started Jul 29 06:14:28 PM PDT 24
Finished Jul 29 06:14:29 PM PDT 24
Peak memory 207028 kb
Host smart-97d9b6b9-696b-43ba-99ab-384e929808d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53693
2101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.536932101
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2361609181
Short name T1444
Test name
Test status
Simulation time 3450220301 ps
CPU time 106.45 seconds
Started Jul 29 06:14:26 PM PDT 24
Finished Jul 29 06:16:13 PM PDT 24
Peak memory 215448 kb
Host smart-73ed1c91-140f-4cba-9ce4-14276033d05d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2361609181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2361609181
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.4152429830
Short name T2815
Test name
Test status
Simulation time 150743148 ps
CPU time 0.87 seconds
Started Jul 29 06:14:26 PM PDT 24
Finished Jul 29 06:14:27 PM PDT 24
Peak memory 207136 kb
Host smart-98d25d15-5771-4fc3-92ca-04059fb80a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41524
29830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.4152429830
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2347108546
Short name T2387
Test name
Test status
Simulation time 181293579 ps
CPU time 0.89 seconds
Started Jul 29 06:14:26 PM PDT 24
Finished Jul 29 06:14:27 PM PDT 24
Peak memory 207080 kb
Host smart-2ffcb589-13df-48de-9d1b-0b40fc5bb7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23471
08546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2347108546
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.1504939116
Short name T980
Test name
Test status
Simulation time 944938094 ps
CPU time 2.51 seconds
Started Jul 29 06:14:27 PM PDT 24
Finished Jul 29 06:14:30 PM PDT 24
Peak memory 207296 kb
Host smart-07d87628-d17a-4bef-b24a-9ff29786a257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15049
39116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.1504939116
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2033279665
Short name T2049
Test name
Test status
Simulation time 5915786642 ps
CPU time 169.49 seconds
Started Jul 29 06:14:25 PM PDT 24
Finished Jul 29 06:17:14 PM PDT 24
Peak memory 215540 kb
Host smart-007da5dc-4d96-49e6-a50a-05c2b8635a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20332
79665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2033279665
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.135274450
Short name T2040
Test name
Test status
Simulation time 298105677 ps
CPU time 4.46 seconds
Started Jul 29 06:14:19 PM PDT 24
Finished Jul 29 06:14:23 PM PDT 24
Peak memory 207300 kb
Host smart-b6452678-4843-49d0-9ecd-c3e2603b4b14
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135274450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_host
_handshake.135274450
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.2833354933
Short name T2301
Test name
Test status
Simulation time 57058673 ps
CPU time 0.7 seconds
Started Jul 29 06:14:39 PM PDT 24
Finished Jul 29 06:14:40 PM PDT 24
Peak memory 207104 kb
Host smart-b0b0c5d2-6436-4faf-9009-3a583fbfb9f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2833354933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.2833354933
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3076083398
Short name T1412
Test name
Test status
Simulation time 3933863293 ps
CPU time 6.32 seconds
Started Jul 29 06:14:25 PM PDT 24
Finished Jul 29 06:14:32 PM PDT 24
Peak memory 207340 kb
Host smart-89f3a48d-eb4a-4ff3-bc97-20e1d024b4ea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076083398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_disconnect.3076083398
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.4092712734
Short name T769
Test name
Test status
Simulation time 13494045752 ps
CPU time 16.63 seconds
Started Jul 29 06:14:26 PM PDT 24
Finished Jul 29 06:14:43 PM PDT 24
Peak memory 207436 kb
Host smart-9b4fb28c-34b5-4c0d-973a-89ec1692e18b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092712734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.4092712734
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.867612750
Short name T1637
Test name
Test status
Simulation time 23332614014 ps
CPU time 28.91 seconds
Started Jul 29 06:14:29 PM PDT 24
Finished Jul 29 06:14:58 PM PDT 24
Peak memory 207396 kb
Host smart-a2ec00f3-994c-40d5-8d86-98e66c34af66
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867612750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_ao
n_wake_resume.867612750
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1169120257
Short name T1567
Test name
Test status
Simulation time 169940568 ps
CPU time 0.99 seconds
Started Jul 29 06:14:32 PM PDT 24
Finished Jul 29 06:14:33 PM PDT 24
Peak memory 207140 kb
Host smart-4cc22de8-46f7-4054-97bf-4a00546b70da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11691
20257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1169120257
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3733914184
Short name T783
Test name
Test status
Simulation time 159179938 ps
CPU time 0.87 seconds
Started Jul 29 06:14:28 PM PDT 24
Finished Jul 29 06:14:29 PM PDT 24
Peak memory 207000 kb
Host smart-3d01be07-5e07-4601-ae19-99decaa6bc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37339
14184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3733914184
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.1443827757
Short name T2553
Test name
Test status
Simulation time 179831810 ps
CPU time 0.89 seconds
Started Jul 29 06:14:31 PM PDT 24
Finished Jul 29 06:14:32 PM PDT 24
Peak memory 207120 kb
Host smart-a788577a-699f-479f-bac2-c0484ad5bae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14438
27757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.1443827757
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3603328618
Short name T2073
Test name
Test status
Simulation time 1488655561 ps
CPU time 3.75 seconds
Started Jul 29 06:14:30 PM PDT 24
Finished Jul 29 06:14:34 PM PDT 24
Peak memory 207224 kb
Host smart-3495fa97-aab9-432b-989e-f6297ac1c9ed
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3603328618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3603328618
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.2456545875
Short name T1642
Test name
Test status
Simulation time 20139366680 ps
CPU time 49.57 seconds
Started Jul 29 06:14:31 PM PDT 24
Finished Jul 29 06:15:21 PM PDT 24
Peak memory 207356 kb
Host smart-cd4abe44-4a19-4334-8d41-0dc089b57482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24565
45875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.2456545875
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.1275045763
Short name T1492
Test name
Test status
Simulation time 7068406586 ps
CPU time 70.38 seconds
Started Jul 29 06:14:31 PM PDT 24
Finished Jul 29 06:15:42 PM PDT 24
Peak memory 207400 kb
Host smart-12a8cd7d-6e32-4486-adb6-e07e393d2e66
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275045763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.1275045763
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1438109354
Short name T985
Test name
Test status
Simulation time 500043742 ps
CPU time 1.63 seconds
Started Jul 29 06:14:32 PM PDT 24
Finished Jul 29 06:14:34 PM PDT 24
Peak memory 207192 kb
Host smart-d9a1ea5a-6fa7-40b1-84ab-a6181d94c53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14381
09354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1438109354
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.340967885
Short name T2689
Test name
Test status
Simulation time 179400061 ps
CPU time 0.87 seconds
Started Jul 29 06:14:31 PM PDT 24
Finished Jul 29 06:14:32 PM PDT 24
Peak memory 206948 kb
Host smart-f632aaab-0132-4241-92e2-23cfc4250a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34096
7885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.340967885
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2072750347
Short name T2121
Test name
Test status
Simulation time 32687145 ps
CPU time 0.72 seconds
Started Jul 29 06:14:32 PM PDT 24
Finished Jul 29 06:14:33 PM PDT 24
Peak memory 207044 kb
Host smart-ca4df8b3-8f31-4099-a4b2-23b251f07c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20727
50347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2072750347
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.3499667399
Short name T1894
Test name
Test status
Simulation time 959880506 ps
CPU time 2.81 seconds
Started Jul 29 06:14:32 PM PDT 24
Finished Jul 29 06:14:35 PM PDT 24
Peak memory 207208 kb
Host smart-84a5fefc-20db-452d-bffb-9d0eb9390210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34996
67399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.3499667399
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1274991491
Short name T443
Test name
Test status
Simulation time 176243512 ps
CPU time 1.82 seconds
Started Jul 29 06:14:31 PM PDT 24
Finished Jul 29 06:14:33 PM PDT 24
Peak memory 207328 kb
Host smart-35284292-3b52-4266-b9d7-3ef40fc1ea6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12749
91491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1274991491
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3053705623
Short name T2501
Test name
Test status
Simulation time 206744284 ps
CPU time 1.01 seconds
Started Jul 29 06:14:31 PM PDT 24
Finished Jul 29 06:14:33 PM PDT 24
Peak memory 207316 kb
Host smart-d0217c8b-1f3f-450e-b060-15fe05639a98
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3053705623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3053705623
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3802080255
Short name T2571
Test name
Test status
Simulation time 135425523 ps
CPU time 0.84 seconds
Started Jul 29 06:14:37 PM PDT 24
Finished Jul 29 06:14:39 PM PDT 24
Peak memory 207092 kb
Host smart-fdad98e1-9c31-4dd8-a094-d69992ef8e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38020
80255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3802080255
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2377762749
Short name T1526
Test name
Test status
Simulation time 206438394 ps
CPU time 1.04 seconds
Started Jul 29 06:14:31 PM PDT 24
Finished Jul 29 06:14:32 PM PDT 24
Peak memory 207080 kb
Host smart-f210cded-182a-4c58-8b41-80073839040c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23777
62749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2377762749
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.233348860
Short name T2374
Test name
Test status
Simulation time 6824642597 ps
CPU time 207.31 seconds
Started Jul 29 06:14:31 PM PDT 24
Finished Jul 29 06:17:58 PM PDT 24
Peak memory 215596 kb
Host smart-aebf2f84-e3b3-4d19-a8a2-0cb017f0aa9c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=233348860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.233348860
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.1667168207
Short name T2031
Test name
Test status
Simulation time 3932799284 ps
CPU time 49.62 seconds
Started Jul 29 06:14:32 PM PDT 24
Finished Jul 29 06:15:22 PM PDT 24
Peak memory 207348 kb
Host smart-e40acf1b-a1bc-462b-8aed-e56e29621114
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1667168207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.1667168207
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3493177974
Short name T1085
Test name
Test status
Simulation time 222937668 ps
CPU time 0.93 seconds
Started Jul 29 06:14:31 PM PDT 24
Finished Jul 29 06:14:32 PM PDT 24
Peak memory 207076 kb
Host smart-2a09feb6-aae5-4712-9e6e-a49ec07d3fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34931
77974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3493177974
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.2582415581
Short name T2732
Test name
Test status
Simulation time 23289351556 ps
CPU time 35.57 seconds
Started Jul 29 06:14:35 PM PDT 24
Finished Jul 29 06:15:11 PM PDT 24
Peak memory 207356 kb
Host smart-6c8d810c-d9e4-4a5e-9c72-2d6ad8bccfec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25824
15581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.2582415581
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.614410244
Short name T753
Test name
Test status
Simulation time 3361504537 ps
CPU time 5.51 seconds
Started Jul 29 06:14:36 PM PDT 24
Finished Jul 29 06:14:41 PM PDT 24
Peak memory 207344 kb
Host smart-a57d95a6-7f62-4cba-ae12-54009192c04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61441
0244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.614410244
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3537546984
Short name T1119
Test name
Test status
Simulation time 7232627004 ps
CPU time 73.21 seconds
Started Jul 29 06:14:32 PM PDT 24
Finished Jul 29 06:15:45 PM PDT 24
Peak memory 217532 kb
Host smart-71252f11-4ad0-4b06-8939-42378d9e5ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35375
46984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3537546984
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1887616103
Short name T1776
Test name
Test status
Simulation time 6929481541 ps
CPU time 72.51 seconds
Started Jul 29 06:14:30 PM PDT 24
Finished Jul 29 06:15:43 PM PDT 24
Peak memory 207436 kb
Host smart-3382d648-8e80-484a-a320-f6368ef725b1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1887616103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1887616103
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.852187588
Short name T2336
Test name
Test status
Simulation time 240606493 ps
CPU time 0.99 seconds
Started Jul 29 06:14:35 PM PDT 24
Finished Jul 29 06:14:36 PM PDT 24
Peak memory 207108 kb
Host smart-f25f29e8-49de-4ad3-b89e-155813414421
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=852187588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.852187588
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1801828231
Short name T1621
Test name
Test status
Simulation time 197816801 ps
CPU time 0.98 seconds
Started Jul 29 06:14:31 PM PDT 24
Finished Jul 29 06:14:32 PM PDT 24
Peak memory 207064 kb
Host smart-e3ad31a4-fbe7-4c76-8cfc-ea4641438578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18018
28231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1801828231
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.12581550
Short name T1574
Test name
Test status
Simulation time 5838974580 ps
CPU time 44.52 seconds
Started Jul 29 06:14:35 PM PDT 24
Finished Jul 29 06:15:20 PM PDT 24
Peak memory 215568 kb
Host smart-553099b1-8c33-4703-ba56-6f479287bd6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12581
550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.12581550
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1384848883
Short name T810
Test name
Test status
Simulation time 2628419180 ps
CPU time 19.45 seconds
Started Jul 29 06:14:29 PM PDT 24
Finished Jul 29 06:14:49 PM PDT 24
Peak memory 215588 kb
Host smart-4a123b6a-de1b-4929-8c9e-d8da9848a7e8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1384848883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1384848883
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.833601372
Short name T1855
Test name
Test status
Simulation time 150861431 ps
CPU time 0.89 seconds
Started Jul 29 06:14:36 PM PDT 24
Finished Jul 29 06:14:37 PM PDT 24
Peak memory 207108 kb
Host smart-99a64d1f-d7bd-4243-8bbd-8c1934da09b5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=833601372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.833601372
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1995698712
Short name T2406
Test name
Test status
Simulation time 162141923 ps
CPU time 0.84 seconds
Started Jul 29 06:14:34 PM PDT 24
Finished Jul 29 06:14:35 PM PDT 24
Peak memory 207048 kb
Host smart-6ddc1152-e26b-426f-bf82-714b569562ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19956
98712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1995698712
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.156491664
Short name T136
Test name
Test status
Simulation time 180462477 ps
CPU time 0.94 seconds
Started Jul 29 06:14:36 PM PDT 24
Finished Jul 29 06:14:37 PM PDT 24
Peak memory 207104 kb
Host smart-6a5e703f-c285-408d-a61d-5421a352f964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15649
1664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.156491664
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2500052186
Short name T1736
Test name
Test status
Simulation time 160679425 ps
CPU time 0.86 seconds
Started Jul 29 06:14:35 PM PDT 24
Finished Jul 29 06:14:36 PM PDT 24
Peak memory 206980 kb
Host smart-f705ef1c-7291-4751-9c53-349dee8f94e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25000
52186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2500052186
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2467989247
Short name T1342
Test name
Test status
Simulation time 182015155 ps
CPU time 0.94 seconds
Started Jul 29 06:14:38 PM PDT 24
Finished Jul 29 06:14:39 PM PDT 24
Peak memory 207136 kb
Host smart-2afc8341-d627-4142-b1fc-47acf96b4147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24679
89247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2467989247
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.698983262
Short name T481
Test name
Test status
Simulation time 187013556 ps
CPU time 0.91 seconds
Started Jul 29 06:14:36 PM PDT 24
Finished Jul 29 06:14:37 PM PDT 24
Peak memory 207052 kb
Host smart-563d834e-8e40-4f9e-bcfa-1a7eb18ab5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69898
3262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.698983262
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2202542013
Short name T2124
Test name
Test status
Simulation time 154061799 ps
CPU time 0.87 seconds
Started Jul 29 06:14:35 PM PDT 24
Finished Jul 29 06:14:36 PM PDT 24
Peak memory 207116 kb
Host smart-93d6d1d1-67b0-400a-ba9c-985c1ba6b18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22025
42013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2202542013
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.1943447380
Short name T2229
Test name
Test status
Simulation time 232945422 ps
CPU time 1.03 seconds
Started Jul 29 06:14:36 PM PDT 24
Finished Jul 29 06:14:37 PM PDT 24
Peak memory 207104 kb
Host smart-4e70a7da-3971-4fcd-ab01-4ca687a9159b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1943447380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1943447380
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.66960485
Short name T1669
Test name
Test status
Simulation time 142454907 ps
CPU time 0.83 seconds
Started Jul 29 06:14:38 PM PDT 24
Finished Jul 29 06:14:38 PM PDT 24
Peak memory 207060 kb
Host smart-0b12bf74-9e8b-4a39-b565-6f5ca2fd252d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66960
485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.66960485
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.847941138
Short name T1688
Test name
Test status
Simulation time 39589415 ps
CPU time 0.71 seconds
Started Jul 29 06:14:35 PM PDT 24
Finished Jul 29 06:14:36 PM PDT 24
Peak memory 207012 kb
Host smart-35ab7275-39bb-4c09-8d33-be445e3d089a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84794
1138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.847941138
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1342408132
Short name T1150
Test name
Test status
Simulation time 16768418541 ps
CPU time 40.63 seconds
Started Jul 29 06:14:37 PM PDT 24
Finished Jul 29 06:15:18 PM PDT 24
Peak memory 220484 kb
Host smart-e9343c8c-faa0-44aa-97ef-a0db6aa8f995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13424
08132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1342408132
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.850469398
Short name T2467
Test name
Test status
Simulation time 183038883 ps
CPU time 0.94 seconds
Started Jul 29 06:14:41 PM PDT 24
Finished Jul 29 06:14:42 PM PDT 24
Peak memory 207060 kb
Host smart-b178ab07-1e9b-43b9-8be1-2fb5e630b0ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85046
9398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.850469398
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.895276902
Short name T2310
Test name
Test status
Simulation time 246515984 ps
CPU time 0.99 seconds
Started Jul 29 06:14:40 PM PDT 24
Finished Jul 29 06:14:41 PM PDT 24
Peak memory 207084 kb
Host smart-6e711986-9f16-48f5-a342-139d18382643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89527
6902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.895276902
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2236814277
Short name T1738
Test name
Test status
Simulation time 249126613 ps
CPU time 1 seconds
Started Jul 29 06:14:48 PM PDT 24
Finished Jul 29 06:14:49 PM PDT 24
Peak memory 207120 kb
Host smart-f62196a6-4bc5-4049-beb7-22d39e1b801e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22368
14277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2236814277
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.87500909
Short name T430
Test name
Test status
Simulation time 220910029 ps
CPU time 1.01 seconds
Started Jul 29 06:14:35 PM PDT 24
Finished Jul 29 06:14:36 PM PDT 24
Peak memory 207096 kb
Host smart-228dfc24-744e-4fbc-ad01-c8c8d19d1858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87500
909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.87500909
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2142961607
Short name T1698
Test name
Test status
Simulation time 146106248 ps
CPU time 0.8 seconds
Started Jul 29 06:14:36 PM PDT 24
Finished Jul 29 06:14:37 PM PDT 24
Peak memory 207044 kb
Host smart-1891f024-9d16-4fe1-ba65-a6826a6566c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21429
61607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2142961607
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2508401921
Short name T669
Test name
Test status
Simulation time 141771698 ps
CPU time 0.8 seconds
Started Jul 29 06:14:35 PM PDT 24
Finished Jul 29 06:14:36 PM PDT 24
Peak memory 207024 kb
Host smart-81f11561-2a75-4e36-b0f5-d227ff92c6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084
01921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2508401921
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1557537824
Short name T2122
Test name
Test status
Simulation time 147426232 ps
CPU time 0.89 seconds
Started Jul 29 06:14:35 PM PDT 24
Finished Jul 29 06:14:36 PM PDT 24
Peak memory 207080 kb
Host smart-f73ae57d-1648-446b-bfe8-d495d41d59ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15575
37824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1557537824
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1776126879
Short name T2431
Test name
Test status
Simulation time 208233918 ps
CPU time 0.97 seconds
Started Jul 29 06:14:37 PM PDT 24
Finished Jul 29 06:14:38 PM PDT 24
Peak memory 207104 kb
Host smart-c82e6e4e-f101-4784-926c-159845af4839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17761
26879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1776126879
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.2275667093
Short name T1164
Test name
Test status
Simulation time 4715963545 ps
CPU time 133.05 seconds
Started Jul 29 06:14:47 PM PDT 24
Finished Jul 29 06:17:00 PM PDT 24
Peak memory 215652 kb
Host smart-411989ea-5567-4d64-8143-3152c50bbc52
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2275667093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.2275667093
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2694354281
Short name T1075
Test name
Test status
Simulation time 164701401 ps
CPU time 0.89 seconds
Started Jul 29 06:14:37 PM PDT 24
Finished Jul 29 06:14:38 PM PDT 24
Peak memory 207108 kb
Host smart-5bf7df5f-4032-4f89-84ce-786088d33d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26943
54281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2694354281
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.84130328
Short name T1753
Test name
Test status
Simulation time 174450182 ps
CPU time 0.86 seconds
Started Jul 29 06:14:37 PM PDT 24
Finished Jul 29 06:14:38 PM PDT 24
Peak memory 207124 kb
Host smart-0b466e39-2770-4566-ae1e-701a3783f0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84130
328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.84130328
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.3401100004
Short name T2081
Test name
Test status
Simulation time 1362413981 ps
CPU time 3.29 seconds
Started Jul 29 06:14:34 PM PDT 24
Finished Jul 29 06:14:38 PM PDT 24
Peak memory 207216 kb
Host smart-53bdf8f7-9fc2-4ea5-af2f-4f8a8056dd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34011
00004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.3401100004
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1038526733
Short name T978
Test name
Test status
Simulation time 6306422808 ps
CPU time 187.76 seconds
Started Jul 29 06:14:36 PM PDT 24
Finished Jul 29 06:17:44 PM PDT 24
Peak memory 215580 kb
Host smart-fdcc8aac-e0b8-4c21-b180-fdf7849b19a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10385
26733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1038526733
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.3708544578
Short name T1146
Test name
Test status
Simulation time 612823954 ps
CPU time 5.25 seconds
Started Jul 29 06:14:30 PM PDT 24
Finished Jul 29 06:14:35 PM PDT 24
Peak memory 207292 kb
Host smart-4502f02b-3120-4b99-937d-74a06b1c7acc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708544578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_hos
t_handshake.3708544578
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.4122912725
Short name T510
Test name
Test status
Simulation time 54761567 ps
CPU time 0.69 seconds
Started Jul 29 06:14:46 PM PDT 24
Finished Jul 29 06:14:47 PM PDT 24
Peak memory 207148 kb
Host smart-f279869d-d86d-49d6-b097-339cdeb8efc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4122912725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.4122912725
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.3489897351
Short name T1311
Test name
Test status
Simulation time 4096352164 ps
CPU time 5.69 seconds
Started Jul 29 06:14:47 PM PDT 24
Finished Jul 29 06:14:53 PM PDT 24
Peak memory 207160 kb
Host smart-81ae8c13-4a06-4b58-8ecf-7568e630ed90
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489897351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.3489897351
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.677792734
Short name T2086
Test name
Test status
Simulation time 13446502129 ps
CPU time 14.99 seconds
Started Jul 29 06:14:34 PM PDT 24
Finished Jul 29 06:14:50 PM PDT 24
Peak memory 207444 kb
Host smart-2dc8c558-9b65-4771-8fa1-2330da3eb892
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=677792734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.677792734
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2746968289
Short name T1795
Test name
Test status
Simulation time 23420284183 ps
CPU time 26.94 seconds
Started Jul 29 06:14:34 PM PDT 24
Finished Jul 29 06:15:01 PM PDT 24
Peak memory 207424 kb
Host smart-7d2be2dd-8491-425e-a006-a2c88c85d166
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746968289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_resume.2746968289
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3381955205
Short name T2434
Test name
Test status
Simulation time 182733579 ps
CPU time 0.91 seconds
Started Jul 29 06:14:48 PM PDT 24
Finished Jul 29 06:14:49 PM PDT 24
Peak memory 207124 kb
Host smart-b74e31ae-25cf-4ca4-bf28-423fdbef043d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33819
55205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3381955205
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.2423700064
Short name T1770
Test name
Test status
Simulation time 356878530 ps
CPU time 1.32 seconds
Started Jul 29 06:14:42 PM PDT 24
Finished Jul 29 06:14:43 PM PDT 24
Peak memory 207120 kb
Host smart-4b8779d0-1aa9-4470-8235-16899780e9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24237
00064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.2423700064
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3118459709
Short name T2810
Test name
Test status
Simulation time 584540160 ps
CPU time 1.51 seconds
Started Jul 29 06:14:42 PM PDT 24
Finished Jul 29 06:14:43 PM PDT 24
Peak memory 207100 kb
Host smart-1358319b-208e-4d71-9c6e-72de75cd1e64
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3118459709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3118459709
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2721975148
Short name T176
Test name
Test status
Simulation time 18563703602 ps
CPU time 38.88 seconds
Started Jul 29 06:14:39 PM PDT 24
Finished Jul 29 06:15:18 PM PDT 24
Peak memory 207396 kb
Host smart-6a348b2f-120a-4ceb-a19f-496f548eb881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27219
75148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2721975148
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.1808545873
Short name T602
Test name
Test status
Simulation time 1276967655 ps
CPU time 29.1 seconds
Started Jul 29 06:14:39 PM PDT 24
Finished Jul 29 06:15:08 PM PDT 24
Peak memory 207332 kb
Host smart-3db2cc4f-dca4-4c71-b038-19fc3a96aac5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808545873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.1808545873
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3620931777
Short name T2503
Test name
Test status
Simulation time 316277183 ps
CPU time 1.22 seconds
Started Jul 29 06:14:42 PM PDT 24
Finished Jul 29 06:14:43 PM PDT 24
Peak memory 207092 kb
Host smart-44c51c71-8748-4e23-a101-6bbb02637676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36209
31777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3620931777
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.4114433212
Short name T2207
Test name
Test status
Simulation time 147740353 ps
CPU time 0.83 seconds
Started Jul 29 06:14:40 PM PDT 24
Finished Jul 29 06:14:41 PM PDT 24
Peak memory 207092 kb
Host smart-11511dad-4c89-4e89-9472-de0e15ef79fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41144
33212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.4114433212
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.4188665400
Short name T866
Test name
Test status
Simulation time 42648800 ps
CPU time 0.72 seconds
Started Jul 29 06:14:41 PM PDT 24
Finished Jul 29 06:14:42 PM PDT 24
Peak memory 207024 kb
Host smart-3e75fd6a-fffe-4674-9ac7-9af20106ca3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41886
65400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.4188665400
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3477409687
Short name T438
Test name
Test status
Simulation time 968128622 ps
CPU time 2.53 seconds
Started Jul 29 06:14:41 PM PDT 24
Finished Jul 29 06:14:44 PM PDT 24
Peak memory 207320 kb
Host smart-a50cbb0c-4064-41ff-9a21-beedc41abbd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34774
09687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3477409687
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.4028585986
Short name T1145
Test name
Test status
Simulation time 295182207 ps
CPU time 2.1 seconds
Started Jul 29 06:14:40 PM PDT 24
Finished Jul 29 06:14:43 PM PDT 24
Peak memory 207240 kb
Host smart-9a68a570-3c4d-4b31-94a0-3faab304d116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40285
85986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.4028585986
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.205308389
Short name T1166
Test name
Test status
Simulation time 210057053 ps
CPU time 1.1 seconds
Started Jul 29 06:14:42 PM PDT 24
Finished Jul 29 06:14:43 PM PDT 24
Peak memory 215484 kb
Host smart-a2ae9d41-2c86-4a7e-8aa5-627547b69924
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=205308389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.205308389
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.972693197
Short name T1039
Test name
Test status
Simulation time 134993886 ps
CPU time 0.83 seconds
Started Jul 29 06:14:41 PM PDT 24
Finished Jul 29 06:14:42 PM PDT 24
Peak memory 206952 kb
Host smart-4fbce20f-8e71-4f33-bcb7-74e667d9985f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97269
3197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.972693197
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3032973861
Short name T1337
Test name
Test status
Simulation time 200423635 ps
CPU time 0.93 seconds
Started Jul 29 06:14:42 PM PDT 24
Finished Jul 29 06:14:43 PM PDT 24
Peak memory 207080 kb
Host smart-4aafdcd2-3562-4524-bcce-c1b4527a3c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30329
73861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3032973861
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.4055336242
Short name T1604
Test name
Test status
Simulation time 5962185387 ps
CPU time 62.35 seconds
Started Jul 29 06:14:40 PM PDT 24
Finished Jul 29 06:15:42 PM PDT 24
Peak memory 216756 kb
Host smart-781de0b4-52c2-453a-8e87-d2c1bc3bf6eb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4055336242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.4055336242
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.266434626
Short name T1022
Test name
Test status
Simulation time 4142505538 ps
CPU time 27.13 seconds
Started Jul 29 06:14:46 PM PDT 24
Finished Jul 29 06:15:14 PM PDT 24
Peak memory 207356 kb
Host smart-4166f298-5ad8-460e-85fc-b596a3e87301
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=266434626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.266434626
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.2373016961
Short name T350
Test name
Test status
Simulation time 223733330 ps
CPU time 0.94 seconds
Started Jul 29 06:14:45 PM PDT 24
Finished Jul 29 06:14:46 PM PDT 24
Peak memory 207056 kb
Host smart-f0b19b24-a6a0-4a64-aad4-2948bc370e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23730
16961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.2373016961
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.1028381929
Short name T1032
Test name
Test status
Simulation time 23353990519 ps
CPU time 26.21 seconds
Started Jul 29 06:14:45 PM PDT 24
Finished Jul 29 06:15:11 PM PDT 24
Peak memory 207324 kb
Host smart-c7e1b740-d486-4802-a6dc-5e11aae3b0bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10283
81929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.1028381929
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.3677057130
Short name T1260
Test name
Test status
Simulation time 3381800999 ps
CPU time 5.35 seconds
Started Jul 29 06:14:48 PM PDT 24
Finished Jul 29 06:14:53 PM PDT 24
Peak memory 207332 kb
Host smart-4befc4d3-eab9-4d06-b628-037898ddb9ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36770
57130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.3677057130
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.416856367
Short name T1591
Test name
Test status
Simulation time 7994211444 ps
CPU time 242.42 seconds
Started Jul 29 06:14:44 PM PDT 24
Finished Jul 29 06:18:46 PM PDT 24
Peak memory 215656 kb
Host smart-471c94fc-f742-4cfe-8af1-f39ed8b51190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41685
6367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.416856367
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.278391051
Short name T1176
Test name
Test status
Simulation time 5648312631 ps
CPU time 178.23 seconds
Started Jul 29 06:14:45 PM PDT 24
Finished Jul 29 06:17:44 PM PDT 24
Peak memory 215584 kb
Host smart-14916c09-b9f2-44dc-ad40-dd1dd4ce1a3d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=278391051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.278391051
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.123671248
Short name T1487
Test name
Test status
Simulation time 241244289 ps
CPU time 0.97 seconds
Started Jul 29 06:14:44 PM PDT 24
Finished Jul 29 06:14:45 PM PDT 24
Peak memory 207136 kb
Host smart-3607d983-30d6-4b67-8454-15086ba42287
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=123671248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.123671248
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1779953670
Short name T701
Test name
Test status
Simulation time 219391186 ps
CPU time 0.99 seconds
Started Jul 29 06:14:44 PM PDT 24
Finished Jul 29 06:14:45 PM PDT 24
Peak memory 207100 kb
Host smart-ecb1f0c0-6ca7-4d2e-a999-af2dff975c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17799
53670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1779953670
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2979548269
Short name T860
Test name
Test status
Simulation time 3970752009 ps
CPU time 28.84 seconds
Started Jul 29 06:14:44 PM PDT 24
Finished Jul 29 06:15:13 PM PDT 24
Peak memory 215452 kb
Host smart-93648dac-4a94-480e-a241-a2475890993f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29795
48269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2979548269
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1905899016
Short name T1399
Test name
Test status
Simulation time 6953960801 ps
CPU time 56.61 seconds
Started Jul 29 06:14:45 PM PDT 24
Finished Jul 29 06:15:42 PM PDT 24
Peak memory 207424 kb
Host smart-f9e83d98-6ba2-4f53-b1d2-aa930436fd0e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1905899016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1905899016
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.764090974
Short name T399
Test name
Test status
Simulation time 166486044 ps
CPU time 0.86 seconds
Started Jul 29 06:14:45 PM PDT 24
Finished Jul 29 06:14:46 PM PDT 24
Peak memory 207084 kb
Host smart-359eeb5f-8693-4e6f-a8bd-237dc1e7a159
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=764090974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.764090974
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1392980579
Short name T947
Test name
Test status
Simulation time 151476483 ps
CPU time 0.84 seconds
Started Jul 29 06:14:48 PM PDT 24
Finished Jul 29 06:14:49 PM PDT 24
Peak memory 207072 kb
Host smart-ce8ce13c-70b7-4c55-8202-286791235c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13929
80579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1392980579
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.4274833707
Short name T2516
Test name
Test status
Simulation time 303247616 ps
CPU time 1.05 seconds
Started Jul 29 06:14:43 PM PDT 24
Finished Jul 29 06:14:44 PM PDT 24
Peak memory 207112 kb
Host smart-44fc8efe-e388-4965-a7be-018d15aead75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42748
33707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.4274833707
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2866875343
Short name T714
Test name
Test status
Simulation time 153223428 ps
CPU time 0.82 seconds
Started Jul 29 06:14:48 PM PDT 24
Finished Jul 29 06:14:49 PM PDT 24
Peak memory 207100 kb
Host smart-90be0350-bb05-47fd-b52a-2c98b4f3abdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28668
75343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2866875343
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3209037355
Short name T611
Test name
Test status
Simulation time 205863763 ps
CPU time 0.94 seconds
Started Jul 29 06:14:46 PM PDT 24
Finished Jul 29 06:14:47 PM PDT 24
Peak memory 207088 kb
Host smart-a6032269-cf16-437d-afc8-dc6b856c1804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32090
37355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3209037355
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.4169556279
Short name T1841
Test name
Test status
Simulation time 199494080 ps
CPU time 0.93 seconds
Started Jul 29 06:14:45 PM PDT 24
Finished Jul 29 06:14:46 PM PDT 24
Peak memory 207096 kb
Host smart-da76cfb0-0959-4710-943e-22738a6df9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41695
56279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.4169556279
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1022680741
Short name T643
Test name
Test status
Simulation time 171795265 ps
CPU time 0.87 seconds
Started Jul 29 06:14:49 PM PDT 24
Finished Jul 29 06:14:50 PM PDT 24
Peak memory 207000 kb
Host smart-35e87e24-74f3-458d-a8d1-6fa4d77dbcb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10226
80741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1022680741
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.3967585348
Short name T87
Test name
Test status
Simulation time 218117805 ps
CPU time 0.92 seconds
Started Jul 29 06:14:46 PM PDT 24
Finished Jul 29 06:14:47 PM PDT 24
Peak memory 207004 kb
Host smart-d069a647-9e0f-4e3a-a849-910bb9622f4c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3967585348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3967585348
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.4063861997
Short name T1967
Test name
Test status
Simulation time 149042998 ps
CPU time 0.84 seconds
Started Jul 29 06:14:46 PM PDT 24
Finished Jul 29 06:14:47 PM PDT 24
Peak memory 207088 kb
Host smart-bca6b947-240c-446d-b70b-1ff1ea188407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40638
61997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.4063861997
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2065219179
Short name T1116
Test name
Test status
Simulation time 35698095 ps
CPU time 0.72 seconds
Started Jul 29 06:14:44 PM PDT 24
Finished Jul 29 06:14:45 PM PDT 24
Peak memory 207036 kb
Host smart-66f764b8-a6c2-48e9-b63f-62a813719cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20652
19179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2065219179
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2080682607
Short name T1951
Test name
Test status
Simulation time 8693934429 ps
CPU time 22.3 seconds
Started Jul 29 06:14:45 PM PDT 24
Finished Jul 29 06:15:07 PM PDT 24
Peak memory 219720 kb
Host smart-d6f07ccf-dc4b-46ec-ab8c-461be4f0c698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20806
82607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2080682607
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.402702058
Short name T1508
Test name
Test status
Simulation time 217702479 ps
CPU time 1 seconds
Started Jul 29 06:14:47 PM PDT 24
Finished Jul 29 06:14:48 PM PDT 24
Peak memory 207208 kb
Host smart-34f818c8-8dd7-4b7d-9ab7-b99e5e330c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40270
2058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.402702058
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3673943795
Short name T886
Test name
Test status
Simulation time 311490146 ps
CPU time 1.04 seconds
Started Jul 29 06:14:50 PM PDT 24
Finished Jul 29 06:14:51 PM PDT 24
Peak memory 206984 kb
Host smart-247202f1-4a1b-4c89-8782-1e1632057af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36739
43795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3673943795
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.2763410835
Short name T2178
Test name
Test status
Simulation time 167433376 ps
CPU time 0.91 seconds
Started Jul 29 06:14:48 PM PDT 24
Finished Jul 29 06:14:49 PM PDT 24
Peak memory 207076 kb
Host smart-234e5d7c-c8a7-428c-bada-78c16fd01191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27634
10835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.2763410835
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.1873308918
Short name T1357
Test name
Test status
Simulation time 191098980 ps
CPU time 0.92 seconds
Started Jul 29 06:14:44 PM PDT 24
Finished Jul 29 06:14:45 PM PDT 24
Peak memory 207044 kb
Host smart-361c0bce-097f-4de2-bc5c-e7e7bfc34267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18733
08918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1873308918
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3228790432
Short name T78
Test name
Test status
Simulation time 192269083 ps
CPU time 0.85 seconds
Started Jul 29 06:14:44 PM PDT 24
Finished Jul 29 06:14:45 PM PDT 24
Peak memory 207048 kb
Host smart-d4c0277f-d9ea-4e6c-a116-c1d9a25999bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32287
90432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3228790432
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3085104088
Short name T1704
Test name
Test status
Simulation time 184000561 ps
CPU time 0.91 seconds
Started Jul 29 06:14:47 PM PDT 24
Finished Jul 29 06:14:48 PM PDT 24
Peak memory 207044 kb
Host smart-f3a57805-225f-4bb2-952b-00cfc22092bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30851
04088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3085104088
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3201246370
Short name T1159
Test name
Test status
Simulation time 217718419 ps
CPU time 0.97 seconds
Started Jul 29 06:14:49 PM PDT 24
Finished Jul 29 06:14:50 PM PDT 24
Peak memory 207072 kb
Host smart-ce6eabf1-27cb-4f90-b2e1-e232f14b3399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32012
46370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3201246370
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.240073848
Short name T2638
Test name
Test status
Simulation time 269831765 ps
CPU time 1.03 seconds
Started Jul 29 06:14:47 PM PDT 24
Finished Jul 29 06:14:49 PM PDT 24
Peak memory 207072 kb
Host smart-75e30d75-4bfc-4be1-a132-ea4f76066440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24007
3848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.240073848
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.1847233388
Short name T1215
Test name
Test status
Simulation time 3532561955 ps
CPU time 108.46 seconds
Started Jul 29 06:14:47 PM PDT 24
Finished Jul 29 06:16:36 PM PDT 24
Peak memory 215528 kb
Host smart-5ac13573-a792-48bc-a89d-a10cfe4609b9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1847233388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.1847233388
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2490959819
Short name T742
Test name
Test status
Simulation time 217540501 ps
CPU time 0.9 seconds
Started Jul 29 06:14:49 PM PDT 24
Finished Jul 29 06:14:50 PM PDT 24
Peak memory 207096 kb
Host smart-045dabc2-efff-48e5-9ee3-0b82ae12afe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24909
59819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2490959819
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1749954107
Short name T388
Test name
Test status
Simulation time 188925465 ps
CPU time 0.92 seconds
Started Jul 29 06:14:50 PM PDT 24
Finished Jul 29 06:14:51 PM PDT 24
Peak memory 207228 kb
Host smart-2743939e-7575-4e05-8dfd-898dc4a76fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17499
54107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1749954107
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.1665833595
Short name T1940
Test name
Test status
Simulation time 1162284243 ps
CPU time 2.91 seconds
Started Jul 29 06:14:45 PM PDT 24
Finished Jul 29 06:14:48 PM PDT 24
Peak memory 207292 kb
Host smart-d4c9a535-bcea-441c-9160-809fff2f8b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16658
33595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.1665833595
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.134394151
Short name T1934
Test name
Test status
Simulation time 3819345466 ps
CPU time 111.66 seconds
Started Jul 29 06:14:48 PM PDT 24
Finished Jul 29 06:16:39 PM PDT 24
Peak memory 223360 kb
Host smart-4f87e053-860b-4ac1-bc92-078712b67fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13439
4151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.134394151
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.2434793847
Short name T1416
Test name
Test status
Simulation time 848408884 ps
CPU time 19.82 seconds
Started Jul 29 06:14:40 PM PDT 24
Finished Jul 29 06:15:00 PM PDT 24
Peak memory 207304 kb
Host smart-da841a00-d501-4228-a625-81a525625485
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434793847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.2434793847
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.4134822436
Short name T1671
Test name
Test status
Simulation time 112810404 ps
CPU time 0.73 seconds
Started Jul 29 06:11:07 PM PDT 24
Finished Jul 29 06:11:08 PM PDT 24
Peak memory 207156 kb
Host smart-4e8d6438-8cfa-463c-b478-f9b70c4e0131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4134822436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.4134822436
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.2483101593
Short name T2264
Test name
Test status
Simulation time 4012845238 ps
CPU time 6.96 seconds
Started Jul 29 06:10:50 PM PDT 24
Finished Jul 29 06:10:57 PM PDT 24
Peak memory 207296 kb
Host smart-605a6339-6ca1-4531-b7f8-8820728295c0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483101593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.2483101593
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1875189537
Short name T2824
Test name
Test status
Simulation time 13438118271 ps
CPU time 15.56 seconds
Started Jul 29 06:10:47 PM PDT 24
Finished Jul 29 06:11:02 PM PDT 24
Peak memory 207424 kb
Host smart-cb464f5e-fff1-4959-bf0d-af021d209abf
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875189537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1875189537
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1326421041
Short name T1195
Test name
Test status
Simulation time 23524628804 ps
CPU time 30.08 seconds
Started Jul 29 06:10:44 PM PDT 24
Finished Jul 29 06:11:14 PM PDT 24
Peak memory 207364 kb
Host smart-148bd203-c894-48b4-94a1-c571121e9128
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326421041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.1326421041
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3944085648
Short name T952
Test name
Test status
Simulation time 153946630 ps
CPU time 0.89 seconds
Started Jul 29 06:10:48 PM PDT 24
Finished Jul 29 06:10:49 PM PDT 24
Peak memory 206768 kb
Host smart-a8dde780-62d6-44ec-b018-34973498431a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39440
85648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3944085648
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.48775529
Short name T64
Test name
Test status
Simulation time 150631565 ps
CPU time 0.87 seconds
Started Jul 29 06:10:46 PM PDT 24
Finished Jul 29 06:10:47 PM PDT 24
Peak memory 207036 kb
Host smart-dee6e2cb-2c23-4339-a851-fc17d73088b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48775
529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.48775529
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1237639144
Short name T2460
Test name
Test status
Simulation time 145977197 ps
CPU time 0.88 seconds
Started Jul 29 06:10:46 PM PDT 24
Finished Jul 29 06:10:47 PM PDT 24
Peak memory 207112 kb
Host smart-028470d5-a80e-4ab3-bd11-c8e4dbb3dbd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12376
39144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1237639144
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.3559598552
Short name T844
Test name
Test status
Simulation time 367824797 ps
CPU time 1.35 seconds
Started Jul 29 06:10:48 PM PDT 24
Finished Jul 29 06:10:49 PM PDT 24
Peak memory 206976 kb
Host smart-4b51bcd8-ebba-4c54-9307-fa1605e9f320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35595
98552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.3559598552
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.344507940
Short name T1160
Test name
Test status
Simulation time 624925732 ps
CPU time 1.85 seconds
Started Jul 29 06:10:50 PM PDT 24
Finished Jul 29 06:10:52 PM PDT 24
Peak memory 207060 kb
Host smart-297f7b25-de05-403a-9d58-5dd8076ab1a2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=344507940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.344507940
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3889578450
Short name T2714
Test name
Test status
Simulation time 16640842860 ps
CPU time 42.38 seconds
Started Jul 29 06:10:46 PM PDT 24
Finished Jul 29 06:11:29 PM PDT 24
Peak memory 207352 kb
Host smart-23f8a3e9-30b8-400b-8efd-e9ff53c7be4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38895
78450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3889578450
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.4040029049
Short name T772
Test name
Test status
Simulation time 2539161974 ps
CPU time 21.51 seconds
Started Jul 29 06:10:48 PM PDT 24
Finished Jul 29 06:11:10 PM PDT 24
Peak memory 207380 kb
Host smart-be49ac50-1759-4907-8099-0b149395b090
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040029049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.4040029049
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.1426328441
Short name T1619
Test name
Test status
Simulation time 490300852 ps
CPU time 1.68 seconds
Started Jul 29 06:10:45 PM PDT 24
Finished Jul 29 06:10:47 PM PDT 24
Peak memory 206984 kb
Host smart-24298fa6-89ee-49a9-a7f8-fb32c4ad98eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14263
28441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.1426328441
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.1692293280
Short name T718
Test name
Test status
Simulation time 142697407 ps
CPU time 0.88 seconds
Started Jul 29 06:10:45 PM PDT 24
Finished Jul 29 06:10:46 PM PDT 24
Peak memory 207048 kb
Host smart-a6d62307-12d5-4d6e-9458-7fa4540f3c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16922
93280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.1692293280
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.1156033584
Short name T387
Test name
Test status
Simulation time 70269401 ps
CPU time 0.73 seconds
Started Jul 29 06:10:48 PM PDT 24
Finished Jul 29 06:10:49 PM PDT 24
Peak memory 207068 kb
Host smart-20fdc87b-2eec-4ca5-b053-b6a17691e46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11560
33584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1156033584
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.479768549
Short name T1959
Test name
Test status
Simulation time 684179769 ps
CPU time 2.04 seconds
Started Jul 29 06:10:45 PM PDT 24
Finished Jul 29 06:10:48 PM PDT 24
Peak memory 207304 kb
Host smart-0fdc9351-ac07-4b9a-a73a-8e884233d692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47976
8549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.479768549
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.504103550
Short name T2142
Test name
Test status
Simulation time 298634562 ps
CPU time 2.1 seconds
Started Jul 29 06:10:46 PM PDT 24
Finished Jul 29 06:10:48 PM PDT 24
Peak memory 207304 kb
Host smart-11636263-f606-470e-9323-fdcbaac8b847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50410
3550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.504103550
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1815160790
Short name T1583
Test name
Test status
Simulation time 90179978686 ps
CPU time 151.69 seconds
Started Jul 29 06:10:54 PM PDT 24
Finished Jul 29 06:13:26 PM PDT 24
Peak memory 207308 kb
Host smart-12fd0941-0b31-4272-8a35-336d3add6d48
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1815160790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1815160790
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.3009329815
Short name T1015
Test name
Test status
Simulation time 87218952270 ps
CPU time 160.61 seconds
Started Jul 29 06:10:50 PM PDT 24
Finished Jul 29 06:13:31 PM PDT 24
Peak memory 207336 kb
Host smart-5048d39d-cd57-41ed-ba4a-61d46cd1df55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009329815 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.3009329815
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.2788042383
Short name T2531
Test name
Test status
Simulation time 106118990909 ps
CPU time 191.35 seconds
Started Jul 29 06:10:51 PM PDT 24
Finished Jul 29 06:14:02 PM PDT 24
Peak memory 207380 kb
Host smart-d1622114-330d-4648-a7b4-dc69612aed13
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2788042383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.2788042383
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.4138996412
Short name T303
Test name
Test status
Simulation time 89118523570 ps
CPU time 130.68 seconds
Started Jul 29 06:10:51 PM PDT 24
Finished Jul 29 06:13:02 PM PDT 24
Peak memory 207368 kb
Host smart-6d383656-642b-4801-a23b-1d225b5534ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138996412 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.4138996412
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.4195359181
Short name T1614
Test name
Test status
Simulation time 217203582 ps
CPU time 1.07 seconds
Started Jul 29 06:10:50 PM PDT 24
Finished Jul 29 06:10:51 PM PDT 24
Peak memory 215432 kb
Host smart-0d0959f9-002c-49a7-835b-c750170ef822
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4195359181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.4195359181
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2202535073
Short name T1428
Test name
Test status
Simulation time 151152549 ps
CPU time 0.85 seconds
Started Jul 29 06:10:57 PM PDT 24
Finished Jul 29 06:10:58 PM PDT 24
Peak memory 207044 kb
Host smart-95cb09a3-5d8e-4613-a90a-7f9f4428fbb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22025
35073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2202535073
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2693412557
Short name T2165
Test name
Test status
Simulation time 179882230 ps
CPU time 0.92 seconds
Started Jul 29 06:10:50 PM PDT 24
Finished Jul 29 06:10:51 PM PDT 24
Peak memory 206996 kb
Host smart-fc68d7d1-e4c2-4733-ace9-023de566cf4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26934
12557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2693412557
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.3713420540
Short name T911
Test name
Test status
Simulation time 6964928090 ps
CPU time 69.36 seconds
Started Jul 29 06:10:50 PM PDT 24
Finished Jul 29 06:11:59 PM PDT 24
Peak memory 215576 kb
Host smart-a774179d-d762-470a-9e98-6b2d714fbed3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3713420540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.3713420540
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.4124562706
Short name T616
Test name
Test status
Simulation time 8847156072 ps
CPU time 113.79 seconds
Started Jul 29 06:10:50 PM PDT 24
Finished Jul 29 06:12:43 PM PDT 24
Peak memory 207404 kb
Host smart-6ecd793e-d585-4a57-804b-d19b333db76f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4124562706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.4124562706
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1865567769
Short name T2466
Test name
Test status
Simulation time 243013492 ps
CPU time 1.02 seconds
Started Jul 29 06:11:03 PM PDT 24
Finished Jul 29 06:11:04 PM PDT 24
Peak memory 207072 kb
Host smart-0d8553fa-b7bd-499e-81b0-b516cce3d0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18655
67769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1865567769
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.4167456970
Short name T2726
Test name
Test status
Simulation time 23304660418 ps
CPU time 31.87 seconds
Started Jul 29 06:10:52 PM PDT 24
Finished Jul 29 06:11:24 PM PDT 24
Peak memory 207348 kb
Host smart-6a191393-45fc-4304-9a56-33777794a4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41674
56970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.4167456970
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.4247612127
Short name T1188
Test name
Test status
Simulation time 3284197428 ps
CPU time 4.93 seconds
Started Jul 29 06:10:56 PM PDT 24
Finished Jul 29 06:11:01 PM PDT 24
Peak memory 207312 kb
Host smart-85976d71-a691-42f3-bd8c-0761b403735a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42476
12127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.4247612127
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2908713191
Short name T2765
Test name
Test status
Simulation time 8556106163 ps
CPU time 263.3 seconds
Started Jul 29 06:10:54 PM PDT 24
Finished Jul 29 06:15:17 PM PDT 24
Peak memory 215536 kb
Host smart-6c0f3396-da50-44eb-8312-9f4103b701ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29087
13191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2908713191
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.2989020432
Short name T343
Test name
Test status
Simulation time 3923797505 ps
CPU time 39.88 seconds
Started Jul 29 06:10:52 PM PDT 24
Finished Jul 29 06:11:32 PM PDT 24
Peak memory 215588 kb
Host smart-7dbc3674-62db-45ab-9d0a-69508ff5e7f3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2989020432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.2989020432
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.4283677968
Short name T356
Test name
Test status
Simulation time 241589052 ps
CPU time 1.02 seconds
Started Jul 29 06:10:56 PM PDT 24
Finished Jul 29 06:10:57 PM PDT 24
Peak memory 207084 kb
Host smart-6362ffac-79af-4781-b475-2c638899814f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4283677968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.4283677968
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3819121321
Short name T411
Test name
Test status
Simulation time 190729685 ps
CPU time 0.97 seconds
Started Jul 29 06:10:51 PM PDT 24
Finished Jul 29 06:10:52 PM PDT 24
Peak memory 207148 kb
Host smart-e56e2202-a732-4983-ac56-679a007d72d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38191
21321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3819121321
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1213167052
Short name T970
Test name
Test status
Simulation time 3850864096 ps
CPU time 31.4 seconds
Started Jul 29 06:10:54 PM PDT 24
Finished Jul 29 06:11:25 PM PDT 24
Peak memory 217056 kb
Host smart-b77ec965-04dd-486c-bf25-58108a0c8bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12131
67052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1213167052
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.2640330814
Short name T1439
Test name
Test status
Simulation time 6870373978 ps
CPU time 52.51 seconds
Started Jul 29 06:10:53 PM PDT 24
Finished Jul 29 06:11:46 PM PDT 24
Peak memory 207420 kb
Host smart-dee7d379-6ad9-49d3-9eca-fce4b546dec8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2640330814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.2640330814
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3029390452
Short name T2044
Test name
Test status
Simulation time 156824461 ps
CPU time 0.92 seconds
Started Jul 29 06:10:57 PM PDT 24
Finished Jul 29 06:10:58 PM PDT 24
Peak memory 207080 kb
Host smart-2a5be996-f056-4a5e-9c5f-422587ea0fc3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3029390452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3029390452
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.733352923
Short name T900
Test name
Test status
Simulation time 145124935 ps
CPU time 0.87 seconds
Started Jul 29 06:10:57 PM PDT 24
Finished Jul 29 06:10:58 PM PDT 24
Peak memory 207064 kb
Host smart-397f0390-acd6-4de5-b82f-b01c39e69885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73335
2923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.733352923
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.128866585
Short name T337
Test name
Test status
Simulation time 233505377 ps
CPU time 1 seconds
Started Jul 29 06:10:56 PM PDT 24
Finished Jul 29 06:10:57 PM PDT 24
Peak memory 207076 kb
Host smart-2f958db2-22fa-458d-b9f5-864afdf44e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12886
6585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.128866585
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.4015480711
Short name T2561
Test name
Test status
Simulation time 167758444 ps
CPU time 0.84 seconds
Started Jul 29 06:10:54 PM PDT 24
Finished Jul 29 06:10:55 PM PDT 24
Peak memory 206868 kb
Host smart-28cb487d-ef04-4924-8271-bde9bf79061e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40154
80711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.4015480711
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2962319360
Short name T912
Test name
Test status
Simulation time 169296420 ps
CPU time 0.88 seconds
Started Jul 29 06:10:54 PM PDT 24
Finished Jul 29 06:10:55 PM PDT 24
Peak memory 206848 kb
Host smart-6fe897f5-22f5-4146-a5bc-28cafb6cd960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29623
19360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2962319360
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2334126563
Short name T2725
Test name
Test status
Simulation time 143146228 ps
CPU time 0.87 seconds
Started Jul 29 06:10:51 PM PDT 24
Finished Jul 29 06:10:52 PM PDT 24
Peak memory 207084 kb
Host smart-abc8c859-6e7d-4b63-8219-4ae933b7bd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23341
26563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2334126563
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2443202101
Short name T822
Test name
Test status
Simulation time 245423885 ps
CPU time 0.98 seconds
Started Jul 29 06:10:55 PM PDT 24
Finished Jul 29 06:10:56 PM PDT 24
Peak memory 207092 kb
Host smart-cca8f39e-91ec-421e-9e90-3bb9edc6b782
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2443202101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2443202101
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.396137180
Short name T202
Test name
Test status
Simulation time 218243387 ps
CPU time 0.98 seconds
Started Jul 29 06:10:56 PM PDT 24
Finished Jul 29 06:10:57 PM PDT 24
Peak memory 207096 kb
Host smart-476f1038-d445-426d-8ced-6b13a25e6210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39613
7180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.396137180
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2792983295
Short name T1838
Test name
Test status
Simulation time 145285708 ps
CPU time 0.81 seconds
Started Jul 29 06:10:56 PM PDT 24
Finished Jul 29 06:10:57 PM PDT 24
Peak memory 207020 kb
Host smart-924af438-a324-4712-9ef9-41a16d8786a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27929
83295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2792983295
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2823239742
Short name T1511
Test name
Test status
Simulation time 51061680 ps
CPU time 0.71 seconds
Started Jul 29 06:10:57 PM PDT 24
Finished Jul 29 06:10:57 PM PDT 24
Peak memory 207020 kb
Host smart-ef8b2eba-1f74-4dfb-bf8e-6623816fce5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28232
39742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2823239742
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3289872795
Short name T241
Test name
Test status
Simulation time 7565112232 ps
CPU time 19.06 seconds
Started Jul 29 06:10:58 PM PDT 24
Finished Jul 29 06:11:17 PM PDT 24
Peak memory 215596 kb
Host smart-665663c2-6ca4-43ed-9de8-34225bc70fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32898
72795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3289872795
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.222845020
Short name T345
Test name
Test status
Simulation time 195326392 ps
CPU time 0.94 seconds
Started Jul 29 06:10:57 PM PDT 24
Finished Jul 29 06:10:58 PM PDT 24
Peak memory 207096 kb
Host smart-473ac0a5-9dcf-4287-b387-7de96eb934a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22284
5020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.222845020
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1424441841
Short name T1286
Test name
Test status
Simulation time 195295616 ps
CPU time 0.95 seconds
Started Jul 29 06:11:03 PM PDT 24
Finished Jul 29 06:11:04 PM PDT 24
Peak memory 207076 kb
Host smart-7920d287-72b4-43f7-ac0f-2b49b3590511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14244
41841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1424441841
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.2624764758
Short name T179
Test name
Test status
Simulation time 11316033770 ps
CPU time 348.24 seconds
Started Jul 29 06:11:02 PM PDT 24
Finished Jul 29 06:16:51 PM PDT 24
Peak memory 215588 kb
Host smart-3b9d3299-ea8d-4a4d-819c-6065ea1a3a3c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624764758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.2624764758
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3690161683
Short name T168
Test name
Test status
Simulation time 11177770363 ps
CPU time 320.57 seconds
Started Jul 29 06:11:03 PM PDT 24
Finished Jul 29 06:16:24 PM PDT 24
Peak memory 215568 kb
Host smart-a29ab13b-2e67-4d2c-94cc-214bdf0c184c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3690161683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3690161683
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2176800212
Short name T906
Test name
Test status
Simulation time 16243858271 ps
CPU time 144.28 seconds
Started Jul 29 06:11:02 PM PDT 24
Finished Jul 29 06:13:26 PM PDT 24
Peak memory 223888 kb
Host smart-d0c8cf46-cb9a-49c7-b7fd-95176f42dd69
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176800212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2176800212
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3002585395
Short name T1506
Test name
Test status
Simulation time 198592823 ps
CPU time 0.98 seconds
Started Jul 29 06:11:06 PM PDT 24
Finished Jul 29 06:11:07 PM PDT 24
Peak memory 207068 kb
Host smart-151a0f63-6eec-4d25-93a7-8c4fa75773c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30025
85395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3002585395
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.1657071269
Short name T2651
Test name
Test status
Simulation time 187780065 ps
CPU time 1 seconds
Started Jul 29 06:11:03 PM PDT 24
Finished Jul 29 06:11:04 PM PDT 24
Peak memory 207084 kb
Host smart-66a862d3-b829-48ae-9e69-5d85918a968d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16570
71269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.1657071269
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1537215271
Short name T2311
Test name
Test status
Simulation time 155263682 ps
CPU time 0.85 seconds
Started Jul 29 06:11:01 PM PDT 24
Finished Jul 29 06:11:02 PM PDT 24
Peak memory 207076 kb
Host smart-3986b012-8542-4b90-a60b-54c744e04c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15372
15271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1537215271
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.3582093230
Short name T81
Test name
Test status
Simulation time 168990528 ps
CPU time 0.87 seconds
Started Jul 29 06:11:04 PM PDT 24
Finished Jul 29 06:11:05 PM PDT 24
Peak memory 207128 kb
Host smart-57677e97-c283-4b09-bbae-4b8efef9d87c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35820
93230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.3582093230
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3912699533
Short name T209
Test name
Test status
Simulation time 686218684 ps
CPU time 1.52 seconds
Started Jul 29 06:11:08 PM PDT 24
Finished Jul 29 06:11:09 PM PDT 24
Peak memory 224048 kb
Host smart-ca46003f-6217-4600-ab39-8c9beaade382
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3912699533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3912699533
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.2096711756
Short name T1113
Test name
Test status
Simulation time 251078681 ps
CPU time 1.04 seconds
Started Jul 29 06:11:04 PM PDT 24
Finished Jul 29 06:11:05 PM PDT 24
Peak memory 207004 kb
Host smart-be92d4f4-70f8-4cc5-b797-0727c8965fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20967
11756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.2096711756
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3652546166
Short name T2851
Test name
Test status
Simulation time 236580995 ps
CPU time 0.88 seconds
Started Jul 29 06:11:04 PM PDT 24
Finished Jul 29 06:11:05 PM PDT 24
Peak memory 207048 kb
Host smart-51ae9f05-b16b-4774-ace1-dfafb8a39181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36525
46166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3652546166
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3359546910
Short name T2153
Test name
Test status
Simulation time 205865306 ps
CPU time 0.96 seconds
Started Jul 29 06:11:05 PM PDT 24
Finished Jul 29 06:11:06 PM PDT 24
Peak memory 207092 kb
Host smart-6a6cb00e-ad9e-40e6-8155-8ca0de0ed8f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33595
46910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3359546910
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3344840581
Short name T2437
Test name
Test status
Simulation time 243469993 ps
CPU time 1.05 seconds
Started Jul 29 06:11:03 PM PDT 24
Finished Jul 29 06:11:04 PM PDT 24
Peak memory 207260 kb
Host smart-e7b15ff0-b9f3-471b-97e4-5bf38835a371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33448
40581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3344840581
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1832632933
Short name T1900
Test name
Test status
Simulation time 4510712033 ps
CPU time 43.35 seconds
Started Jul 29 06:11:03 PM PDT 24
Finished Jul 29 06:11:46 PM PDT 24
Peak memory 217236 kb
Host smart-9b37cf11-1a66-4d6e-bbc8-678ad29adffb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1832632933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1832632933
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3759650779
Short name T552
Test name
Test status
Simulation time 196455570 ps
CPU time 0.94 seconds
Started Jul 29 06:11:04 PM PDT 24
Finished Jul 29 06:11:05 PM PDT 24
Peak memory 206660 kb
Host smart-fcb8815f-afe3-465a-ac9f-ea8b0bac0db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37596
50779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3759650779
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3488275157
Short name T613
Test name
Test status
Simulation time 169149081 ps
CPU time 0.82 seconds
Started Jul 29 06:11:04 PM PDT 24
Finished Jul 29 06:11:05 PM PDT 24
Peak memory 207076 kb
Host smart-c3eadff1-6684-4e7f-902d-d26f5c111fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34882
75157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3488275157
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.1229475876
Short name T2295
Test name
Test status
Simulation time 1270038940 ps
CPU time 2.88 seconds
Started Jul 29 06:11:09 PM PDT 24
Finished Jul 29 06:11:12 PM PDT 24
Peak memory 207316 kb
Host smart-c49e20ac-933f-47df-a5ed-7370a5269f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12294
75876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.1229475876
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2863820979
Short name T2137
Test name
Test status
Simulation time 4651097900 ps
CPU time 34.18 seconds
Started Jul 29 06:11:09 PM PDT 24
Finished Jul 29 06:11:43 PM PDT 24
Peak memory 215604 kb
Host smart-07f6a318-98ad-4d49-bffb-8281a34a1853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28638
20979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2863820979
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.1934358737
Short name T117
Test name
Test status
Simulation time 13449298539 ps
CPU time 389.41 seconds
Started Jul 29 06:11:11 PM PDT 24
Finished Jul 29 06:17:41 PM PDT 24
Peak memory 215652 kb
Host smart-0fe82e2e-4323-4ae7-ab4a-e3c40f3f8236
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934358737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.1934358737
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.4207807818
Short name T1241
Test name
Test status
Simulation time 1117571415 ps
CPU time 26.03 seconds
Started Jul 29 06:10:46 PM PDT 24
Finished Jul 29 06:11:12 PM PDT 24
Peak memory 207220 kb
Host smart-28967536-4e9b-46aa-8526-ee7e98c17a7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207807818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host
_handshake.4207807818
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3594963531
Short name T2098
Test name
Test status
Simulation time 46952289 ps
CPU time 0.72 seconds
Started Jul 29 06:15:04 PM PDT 24
Finished Jul 29 06:15:05 PM PDT 24
Peak memory 207080 kb
Host smart-0f3c7dbc-ee26-489f-b9d7-57cbcb95ae08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3594963531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3594963531
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.850072559
Short name T12
Test name
Test status
Simulation time 3836408309 ps
CPU time 6.25 seconds
Started Jul 29 06:14:46 PM PDT 24
Finished Jul 29 06:14:52 PM PDT 24
Peak memory 207340 kb
Host smart-4134741e-cd3c-483d-b6e3-607801808cab
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850072559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_ao
n_wake_disconnect.850072559
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2802781004
Short name T2830
Test name
Test status
Simulation time 13337485130 ps
CPU time 14.23 seconds
Started Jul 29 06:14:49 PM PDT 24
Finished Jul 29 06:15:03 PM PDT 24
Peak memory 207404 kb
Host smart-a175679c-6dfb-41c2-9c1b-34d40ce229f7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802781004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2802781004
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.4232662791
Short name T1041
Test name
Test status
Simulation time 23418068400 ps
CPU time 29.14 seconds
Started Jul 29 06:14:47 PM PDT 24
Finished Jul 29 06:15:16 PM PDT 24
Peak memory 207372 kb
Host smart-8cf39cf7-ed5c-483f-968b-f258fbd6cb7e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232662791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.4232662791
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1513807708
Short name T2540
Test name
Test status
Simulation time 148759284 ps
CPU time 0.92 seconds
Started Jul 29 06:14:48 PM PDT 24
Finished Jul 29 06:14:49 PM PDT 24
Peak memory 207128 kb
Host smart-fce90ea2-da27-4094-bfa8-80aa3c33f099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15138
07708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1513807708
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.3536524165
Short name T606
Test name
Test status
Simulation time 156638360 ps
CPU time 0.85 seconds
Started Jul 29 06:14:51 PM PDT 24
Finished Jul 29 06:14:52 PM PDT 24
Peak memory 207096 kb
Host smart-1c2e74de-0f04-4d56-915a-f0e26532c4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35365
24165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3536524165
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2422008952
Short name T1135
Test name
Test status
Simulation time 474781344 ps
CPU time 1.56 seconds
Started Jul 29 06:14:50 PM PDT 24
Finished Jul 29 06:14:52 PM PDT 24
Peak memory 207272 kb
Host smart-0aa486f4-7b32-4282-b146-50a61cd1e576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24220
08952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2422008952
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.924564230
Short name T1915
Test name
Test status
Simulation time 1053542739 ps
CPU time 2.6 seconds
Started Jul 29 06:14:49 PM PDT 24
Finished Jul 29 06:14:52 PM PDT 24
Peak memory 207256 kb
Host smart-e1f56be5-ae78-4978-9242-14dae163cf4f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=924564230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.924564230
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.3306665361
Short name T1961
Test name
Test status
Simulation time 6218656816 ps
CPU time 12.99 seconds
Started Jul 29 06:14:50 PM PDT 24
Finished Jul 29 06:15:03 PM PDT 24
Peak memory 207384 kb
Host smart-9b9e4932-fb5e-4b28-a951-2e8a5aa32033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33066
65361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3306665361
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.1704065987
Short name T2845
Test name
Test status
Simulation time 569173193 ps
CPU time 11.67 seconds
Started Jul 29 06:14:52 PM PDT 24
Finished Jul 29 06:15:04 PM PDT 24
Peak memory 207176 kb
Host smart-8e2f35d3-7dae-44ed-8918-6b30983687df
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704065987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.1704065987
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3421285454
Short name T2498
Test name
Test status
Simulation time 374687513 ps
CPU time 1.31 seconds
Started Jul 29 06:14:51 PM PDT 24
Finished Jul 29 06:14:52 PM PDT 24
Peak memory 206984 kb
Host smart-d0eb9b75-e0bb-454c-8927-f8cfca2b5c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34212
85454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3421285454
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2075829810
Short name T2393
Test name
Test status
Simulation time 151070627 ps
CPU time 0.94 seconds
Started Jul 29 06:14:49 PM PDT 24
Finished Jul 29 06:14:50 PM PDT 24
Peak memory 207156 kb
Host smart-a12ba053-f590-44dc-9cad-36573eeea425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20758
29810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2075829810
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3911478123
Short name T756
Test name
Test status
Simulation time 35934377 ps
CPU time 0.71 seconds
Started Jul 29 06:14:50 PM PDT 24
Finished Jul 29 06:14:51 PM PDT 24
Peak memory 207040 kb
Host smart-845ceb9b-bb69-4525-953a-1168e46b2816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39114
78123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3911478123
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2825958353
Short name T2624
Test name
Test status
Simulation time 877692883 ps
CPU time 2.47 seconds
Started Jul 29 06:14:55 PM PDT 24
Finished Jul 29 06:14:58 PM PDT 24
Peak memory 207324 kb
Host smart-175b8812-77ed-4ddf-82f4-44d15d9ce31a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28259
58353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2825958353
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3745115754
Short name T2197
Test name
Test status
Simulation time 222770664 ps
CPU time 2.13 seconds
Started Jul 29 06:14:50 PM PDT 24
Finished Jul 29 06:14:53 PM PDT 24
Peak memory 207148 kb
Host smart-705140fc-5ae4-44bb-adae-7588cccec945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37451
15754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3745115754
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1423165170
Short name T1694
Test name
Test status
Simulation time 228866866 ps
CPU time 1.18 seconds
Started Jul 29 06:14:56 PM PDT 24
Finished Jul 29 06:14:57 PM PDT 24
Peak memory 216512 kb
Host smart-0d388c3a-640b-47b3-8323-7f9c65a20fd0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1423165170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1423165170
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.4049072293
Short name T2386
Test name
Test status
Simulation time 141519157 ps
CPU time 0.84 seconds
Started Jul 29 06:14:49 PM PDT 24
Finished Jul 29 06:14:50 PM PDT 24
Peak memory 207088 kb
Host smart-49840a8a-bf47-44d7-9214-d8fe7ad8b0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40490
72293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.4049072293
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2868789859
Short name T2220
Test name
Test status
Simulation time 212222124 ps
CPU time 1.01 seconds
Started Jul 29 06:14:52 PM PDT 24
Finished Jul 29 06:14:53 PM PDT 24
Peak memory 207092 kb
Host smart-16c7f0ba-1ce9-4ef5-8f65-717b04f696ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28687
89859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2868789859
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.542864760
Short name T156
Test name
Test status
Simulation time 4918544806 ps
CPU time 158.22 seconds
Started Jul 29 06:14:50 PM PDT 24
Finished Jul 29 06:17:28 PM PDT 24
Peak memory 215612 kb
Host smart-0147b474-e1a4-4b3c-808a-25cd91bd6b09
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=542864760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.542864760
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.2682853869
Short name T2414
Test name
Test status
Simulation time 8301691566 ps
CPU time 91.66 seconds
Started Jul 29 06:14:55 PM PDT 24
Finished Jul 29 06:16:27 PM PDT 24
Peak memory 207376 kb
Host smart-2e22e381-8e99-4d97-b64c-6656bdf18236
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2682853869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.2682853869
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.2755626504
Short name T1565
Test name
Test status
Simulation time 186245732 ps
CPU time 0.93 seconds
Started Jul 29 06:14:51 PM PDT 24
Finished Jul 29 06:14:52 PM PDT 24
Peak memory 207076 kb
Host smart-472531a5-0a05-41e4-a801-679169868fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27556
26504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.2755626504
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.3447264383
Short name T555
Test name
Test status
Simulation time 23311185795 ps
CPU time 26.6 seconds
Started Jul 29 06:14:55 PM PDT 24
Finished Jul 29 06:15:22 PM PDT 24
Peak memory 207364 kb
Host smart-9dbddeb8-1a0e-433f-9867-eddc3fd3c77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34472
64383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.3447264383
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.1627896959
Short name T357
Test name
Test status
Simulation time 3291877648 ps
CPU time 5.7 seconds
Started Jul 29 06:14:50 PM PDT 24
Finished Jul 29 06:14:56 PM PDT 24
Peak memory 207256 kb
Host smart-bc43d299-f116-45aa-8384-76e993b10103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16278
96959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1627896959
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.1837921762
Short name T212
Test name
Test status
Simulation time 10146559551 ps
CPU time 277.57 seconds
Started Jul 29 06:14:48 PM PDT 24
Finished Jul 29 06:19:26 PM PDT 24
Peak memory 215544 kb
Host smart-79030519-fbce-4573-b439-0205fa181e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18379
21762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.1837921762
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2354195223
Short name T934
Test name
Test status
Simulation time 6590941282 ps
CPU time 200.6 seconds
Started Jul 29 06:14:56 PM PDT 24
Finished Jul 29 06:18:16 PM PDT 24
Peak memory 215592 kb
Host smart-1b9b0227-c749-46ec-822c-14bec4851996
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2354195223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2354195223
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2377435226
Short name T2811
Test name
Test status
Simulation time 258370465 ps
CPU time 1.07 seconds
Started Jul 29 06:14:50 PM PDT 24
Finished Jul 29 06:14:51 PM PDT 24
Peak memory 207152 kb
Host smart-c9dee2b0-765e-4cfd-bfe3-10cbfbed8614
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2377435226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2377435226
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.357039721
Short name T2496
Test name
Test status
Simulation time 184171927 ps
CPU time 0.96 seconds
Started Jul 29 06:14:51 PM PDT 24
Finished Jul 29 06:14:52 PM PDT 24
Peak memory 207076 kb
Host smart-3e7afd13-3b3e-40d3-a9b8-5f1130f85a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35703
9721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.357039721
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3493786634
Short name T1868
Test name
Test status
Simulation time 5158187068 ps
CPU time 50.38 seconds
Started Jul 29 06:14:55 PM PDT 24
Finished Jul 29 06:15:46 PM PDT 24
Peak memory 217096 kb
Host smart-1d6b3b0d-1797-4e3b-87d0-a234715cf418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34937
86634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3493786634
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.664967880
Short name T698
Test name
Test status
Simulation time 5943395851 ps
CPU time 65.3 seconds
Started Jul 29 06:14:48 PM PDT 24
Finished Jul 29 06:15:53 PM PDT 24
Peak memory 207392 kb
Host smart-23408ead-0a55-4d0d-a5e2-0f4f4d77d572
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=664967880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.664967880
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1935886880
Short name T2769
Test name
Test status
Simulation time 150977769 ps
CPU time 0.82 seconds
Started Jul 29 06:14:50 PM PDT 24
Finished Jul 29 06:14:51 PM PDT 24
Peak memory 207108 kb
Host smart-bdf27b90-5948-42d4-b957-29d9db7b4dbb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1935886880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1935886880
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.165426280
Short name T1074
Test name
Test status
Simulation time 160284941 ps
CPU time 0.82 seconds
Started Jul 29 06:14:56 PM PDT 24
Finished Jul 29 06:14:57 PM PDT 24
Peak memory 207096 kb
Host smart-a07e957f-240a-40cc-847c-6f485bd3044c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16542
6280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.165426280
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2956682231
Short name T2395
Test name
Test status
Simulation time 166376736 ps
CPU time 0.91 seconds
Started Jul 29 06:14:56 PM PDT 24
Finished Jul 29 06:14:57 PM PDT 24
Peak memory 207120 kb
Host smart-e5956346-03f3-4b34-a9b6-33f30797ab1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29566
82231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2956682231
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.4121404818
Short name T1165
Test name
Test status
Simulation time 150563692 ps
CPU time 0.92 seconds
Started Jul 29 06:14:56 PM PDT 24
Finished Jul 29 06:14:57 PM PDT 24
Peak memory 207080 kb
Host smart-54845f26-d740-4582-a211-37ae6bc4496e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41214
04818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.4121404818
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.447057993
Short name T932
Test name
Test status
Simulation time 153585170 ps
CPU time 0.89 seconds
Started Jul 29 06:14:56 PM PDT 24
Finished Jul 29 06:14:57 PM PDT 24
Peak memory 207056 kb
Host smart-ef4b0f08-b371-4df3-b577-bb50c5e48778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44705
7993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.447057993
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.4083327455
Short name T921
Test name
Test status
Simulation time 180103722 ps
CPU time 0.93 seconds
Started Jul 29 06:14:55 PM PDT 24
Finished Jul 29 06:14:56 PM PDT 24
Peak memory 207068 kb
Host smart-36243ce0-506b-4126-9136-a5d664e27eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40833
27455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.4083327455
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2200846707
Short name T1458
Test name
Test status
Simulation time 151691672 ps
CPU time 0.87 seconds
Started Jul 29 06:14:58 PM PDT 24
Finished Jul 29 06:14:59 PM PDT 24
Peak memory 207132 kb
Host smart-e430455b-de53-4684-9ba8-b893cbe6b85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22008
46707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2200846707
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.730077686
Short name T2059
Test name
Test status
Simulation time 227200872 ps
CPU time 1.07 seconds
Started Jul 29 06:14:57 PM PDT 24
Finished Jul 29 06:14:58 PM PDT 24
Peak memory 207100 kb
Host smart-b0ffaa83-c928-4aeb-8a0e-62d495a1c3ed
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=730077686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.730077686
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.386070854
Short name T1189
Test name
Test status
Simulation time 144039431 ps
CPU time 0.81 seconds
Started Jul 29 06:14:56 PM PDT 24
Finished Jul 29 06:14:57 PM PDT 24
Peak memory 207064 kb
Host smart-3fcc4fab-eeba-41ad-9f32-9f9e42bcdacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38607
0854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.386070854
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3298713440
Short name T1610
Test name
Test status
Simulation time 57754762 ps
CPU time 0.7 seconds
Started Jul 29 06:14:57 PM PDT 24
Finished Jul 29 06:14:57 PM PDT 24
Peak memory 207044 kb
Host smart-a4c478eb-982c-4823-98c6-0424b84df3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32987
13440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3298713440
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.937531157
Short name T238
Test name
Test status
Simulation time 7629483033 ps
CPU time 19.56 seconds
Started Jul 29 06:14:57 PM PDT 24
Finished Jul 29 06:15:16 PM PDT 24
Peak memory 215644 kb
Host smart-ffc40e03-1b0d-4303-9535-6af9d2add97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93753
1157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.937531157
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2911416566
Short name T433
Test name
Test status
Simulation time 168247560 ps
CPU time 0.91 seconds
Started Jul 29 06:14:55 PM PDT 24
Finished Jul 29 06:14:56 PM PDT 24
Peak memory 207020 kb
Host smart-35ce98f9-32ea-47cb-a3bf-7bb52fbc45c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29114
16566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2911416566
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1160136716
Short name T2314
Test name
Test status
Simulation time 211886030 ps
CPU time 0.96 seconds
Started Jul 29 06:14:55 PM PDT 24
Finished Jul 29 06:14:56 PM PDT 24
Peak memory 207072 kb
Host smart-73b7d670-a6bd-46ca-9891-5e5be2c9c2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11601
36716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1160136716
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.4288551925
Short name T1766
Test name
Test status
Simulation time 184292875 ps
CPU time 0.91 seconds
Started Jul 29 06:14:57 PM PDT 24
Finished Jul 29 06:14:59 PM PDT 24
Peak memory 207100 kb
Host smart-452a0fa4-8bb0-4ffa-b603-281597381418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42885
51925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.4288551925
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.3323361106
Short name T1595
Test name
Test status
Simulation time 158418056 ps
CPU time 0.86 seconds
Started Jul 29 06:14:57 PM PDT 24
Finished Jul 29 06:14:58 PM PDT 24
Peak memory 207060 kb
Host smart-1519e2c6-3e45-4f6a-9593-e8ac3192de17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33233
61106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3323361106
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.248912004
Short name T1067
Test name
Test status
Simulation time 158061072 ps
CPU time 0.86 seconds
Started Jul 29 06:14:55 PM PDT 24
Finished Jul 29 06:14:56 PM PDT 24
Peak memory 207012 kb
Host smart-f4dfe8ef-a701-4da2-86e5-04c57f8b51ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24891
2004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.248912004
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.532088948
Short name T1440
Test name
Test status
Simulation time 160814292 ps
CPU time 0.84 seconds
Started Jul 29 06:14:55 PM PDT 24
Finished Jul 29 06:14:56 PM PDT 24
Peak memory 207092 kb
Host smart-4d816772-cf4a-410c-97b0-0ad42cd4d500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53208
8948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.532088948
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1588792095
Short name T2542
Test name
Test status
Simulation time 147439110 ps
CPU time 0.84 seconds
Started Jul 29 06:14:55 PM PDT 24
Finished Jul 29 06:14:56 PM PDT 24
Peak memory 207036 kb
Host smart-f06dfeef-fe54-4df8-a300-91c2d83a278c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15887
92095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1588792095
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2720177712
Short name T2581
Test name
Test status
Simulation time 235210425 ps
CPU time 1.03 seconds
Started Jul 29 06:14:58 PM PDT 24
Finished Jul 29 06:14:59 PM PDT 24
Peak memory 207052 kb
Host smart-dc5170f8-ae34-41af-9828-c13bf3423916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27201
77712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2720177712
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.4066065455
Short name T600
Test name
Test status
Simulation time 4566483109 ps
CPU time 36.65 seconds
Started Jul 29 06:14:58 PM PDT 24
Finished Jul 29 06:15:35 PM PDT 24
Peak memory 217212 kb
Host smart-6c94d20f-8aa6-491f-b42c-ef200438be29
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4066065455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.4066065455
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1982297826
Short name T1469
Test name
Test status
Simulation time 190142972 ps
CPU time 0.9 seconds
Started Jul 29 06:14:54 PM PDT 24
Finished Jul 29 06:14:55 PM PDT 24
Peak memory 207104 kb
Host smart-32dd9188-a5e2-41f1-bd81-b676b67a18b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
97826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1982297826
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2825181862
Short name T1178
Test name
Test status
Simulation time 167647708 ps
CPU time 0.85 seconds
Started Jul 29 06:15:00 PM PDT 24
Finished Jul 29 06:15:01 PM PDT 24
Peak memory 207068 kb
Host smart-93c21243-e65a-4809-9c1f-6541e392bd57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28251
81862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2825181862
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.1323168499
Short name T1280
Test name
Test status
Simulation time 310934657 ps
CPU time 1.16 seconds
Started Jul 29 06:15:00 PM PDT 24
Finished Jul 29 06:15:01 PM PDT 24
Peak memory 207112 kb
Host smart-57f0106d-985a-412b-831b-f259f2986719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13231
68499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.1323168499
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.4140054641
Short name T2416
Test name
Test status
Simulation time 5218110617 ps
CPU time 40.11 seconds
Started Jul 29 06:15:02 PM PDT 24
Finished Jul 29 06:15:42 PM PDT 24
Peak memory 217180 kb
Host smart-280ade80-5d50-40fd-8631-dbc2bf56e7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41400
54641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.4140054641
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.4208058517
Short name T1752
Test name
Test status
Simulation time 7053319572 ps
CPU time 50.71 seconds
Started Jul 29 06:14:47 PM PDT 24
Finished Jul 29 06:15:38 PM PDT 24
Peak memory 207476 kb
Host smart-aaf91568-5186-4ba0-a58e-09ad7d115bbc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208058517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.4208058517
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.1636774745
Short name T2292
Test name
Test status
Simulation time 56168007 ps
CPU time 0.68 seconds
Started Jul 29 06:15:08 PM PDT 24
Finished Jul 29 06:15:09 PM PDT 24
Peak memory 207124 kb
Host smart-66c81381-4a02-40de-8b3a-ae84a6d1581a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1636774745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.1636774745
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3521691625
Short name T2186
Test name
Test status
Simulation time 3945942235 ps
CPU time 5.89 seconds
Started Jul 29 06:15:04 PM PDT 24
Finished Jul 29 06:15:10 PM PDT 24
Peak memory 207344 kb
Host smart-3d859290-12c9-473e-95e9-f4193948a635
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521691625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.3521691625
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.1169581294
Short name T2340
Test name
Test status
Simulation time 23284663662 ps
CPU time 31.82 seconds
Started Jul 29 06:15:00 PM PDT 24
Finished Jul 29 06:15:32 PM PDT 24
Peak memory 207364 kb
Host smart-895ce5c3-3135-41fc-924d-152cb3acc123
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169581294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.1169581294
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.558625943
Short name T1272
Test name
Test status
Simulation time 196422989 ps
CPU time 0.98 seconds
Started Jul 29 06:15:03 PM PDT 24
Finished Jul 29 06:15:04 PM PDT 24
Peak memory 207064 kb
Host smart-6bb94d4f-a601-475d-98e5-a339b8c152e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55862
5943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.558625943
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3212387682
Short name T84
Test name
Test status
Simulation time 176363450 ps
CPU time 0.9 seconds
Started Jul 29 06:15:04 PM PDT 24
Finished Jul 29 06:15:05 PM PDT 24
Peak memory 207220 kb
Host smart-8cd13f33-2a13-4bab-857d-8bd8c4773fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32123
87682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3212387682
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.622551305
Short name T1098
Test name
Test status
Simulation time 519873026 ps
CPU time 1.73 seconds
Started Jul 29 06:15:04 PM PDT 24
Finished Jul 29 06:15:05 PM PDT 24
Peak memory 207092 kb
Host smart-c2697afc-0a4f-4523-a649-3fdd68e4356f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62255
1305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.622551305
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.454367279
Short name T1021
Test name
Test status
Simulation time 1477446076 ps
CPU time 3.5 seconds
Started Jul 29 06:15:04 PM PDT 24
Finished Jul 29 06:15:08 PM PDT 24
Peak memory 207524 kb
Host smart-dbfb02f7-d7c3-44b8-af13-81e555a2cc6c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=454367279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.454367279
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.151902270
Short name T2396
Test name
Test status
Simulation time 1162912178 ps
CPU time 26.51 seconds
Started Jul 29 06:15:04 PM PDT 24
Finished Jul 29 06:15:31 PM PDT 24
Peak memory 207252 kb
Host smart-cbb11d09-00ab-4dfa-98da-74ba217667b4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151902270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.151902270
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.554900814
Short name T2369
Test name
Test status
Simulation time 353931427 ps
CPU time 1.32 seconds
Started Jul 29 06:15:04 PM PDT 24
Finished Jul 29 06:15:05 PM PDT 24
Peak memory 206972 kb
Host smart-5e3e2c7a-c46e-491e-a42b-91218de5c13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55490
0814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.554900814
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1791627758
Short name T1784
Test name
Test status
Simulation time 138477279 ps
CPU time 0.86 seconds
Started Jul 29 06:15:01 PM PDT 24
Finished Jul 29 06:15:02 PM PDT 24
Peak memory 207104 kb
Host smart-752e5f9a-54d1-42f8-9748-87f37a1f6b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17916
27758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1791627758
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1572116360
Short name T2133
Test name
Test status
Simulation time 60599152 ps
CPU time 0.74 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:15:11 PM PDT 24
Peak memory 207180 kb
Host smart-61c89d70-b10c-4772-bfa8-feb8a2a78da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15721
16360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1572116360
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3103049711
Short name T1023
Test name
Test status
Simulation time 1034474861 ps
CPU time 2.52 seconds
Started Jul 29 06:15:03 PM PDT 24
Finished Jul 29 06:15:06 PM PDT 24
Peak memory 207292 kb
Host smart-4e173d97-075b-44ce-99c0-c49cba432cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31030
49711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3103049711
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2161550384
Short name T1110
Test name
Test status
Simulation time 226382998 ps
CPU time 1.88 seconds
Started Jul 29 06:15:04 PM PDT 24
Finished Jul 29 06:15:06 PM PDT 24
Peak memory 207308 kb
Host smart-d227d95c-2177-4dcc-b517-6030572b057e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21615
50384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2161550384
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1295283077
Short name T1832
Test name
Test status
Simulation time 213610976 ps
CPU time 1.13 seconds
Started Jul 29 06:15:07 PM PDT 24
Finished Jul 29 06:15:08 PM PDT 24
Peak memory 207188 kb
Host smart-0a4ef90a-e513-436e-a7ab-347350dc16b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1295283077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1295283077
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.475181851
Short name T104
Test name
Test status
Simulation time 133051124 ps
CPU time 0.83 seconds
Started Jul 29 06:15:07 PM PDT 24
Finished Jul 29 06:15:08 PM PDT 24
Peak memory 206952 kb
Host smart-827a1875-2483-4ccb-86b1-5b094773e004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47518
1851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.475181851
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2683510246
Short name T1064
Test name
Test status
Simulation time 176364511 ps
CPU time 0.92 seconds
Started Jul 29 06:15:08 PM PDT 24
Finished Jul 29 06:15:09 PM PDT 24
Peak memory 206984 kb
Host smart-d707c887-aa79-4c5c-9526-eaa60da20342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26835
10246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2683510246
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.2782760138
Short name T453
Test name
Test status
Simulation time 8278580096 ps
CPU time 93.81 seconds
Started Jul 29 06:15:03 PM PDT 24
Finished Jul 29 06:16:37 PM PDT 24
Peak memory 215644 kb
Host smart-34969c21-8ad7-4a77-801b-2cf23ca6432e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2782760138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.2782760138
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.138347594
Short name T2745
Test name
Test status
Simulation time 235970788 ps
CPU time 1.01 seconds
Started Jul 29 06:15:04 PM PDT 24
Finished Jul 29 06:15:06 PM PDT 24
Peak memory 207080 kb
Host smart-0611400a-79cb-42c3-b7b1-f4aa07670671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13834
7594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.138347594
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.2830616456
Short name T1233
Test name
Test status
Simulation time 23363960412 ps
CPU time 30.1 seconds
Started Jul 29 06:15:09 PM PDT 24
Finished Jul 29 06:15:39 PM PDT 24
Peak memory 207532 kb
Host smart-057fb4f4-7a72-41bf-9525-a35767cc73b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28306
16456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.2830616456
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3067859845
Short name T787
Test name
Test status
Simulation time 3350895421 ps
CPU time 5.38 seconds
Started Jul 29 06:15:05 PM PDT 24
Finished Jul 29 06:15:10 PM PDT 24
Peak memory 207324 kb
Host smart-706fc148-03c6-4e47-bd87-2732fc7bee7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30678
59845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3067859845
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1864955284
Short name T1551
Test name
Test status
Simulation time 6776360158 ps
CPU time 69.95 seconds
Started Jul 29 06:15:02 PM PDT 24
Finished Jul 29 06:16:12 PM PDT 24
Peak memory 217660 kb
Host smart-06517373-efe7-45b4-b657-0cb6545958b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18649
55284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1864955284
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.3427364755
Short name T381
Test name
Test status
Simulation time 3937965963 ps
CPU time 28.97 seconds
Started Jul 29 06:15:06 PM PDT 24
Finished Jul 29 06:15:35 PM PDT 24
Peak memory 215520 kb
Host smart-a7cd3ff5-c872-492e-a506-b4092899b28b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3427364755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.3427364755
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.1544722774
Short name T2718
Test name
Test status
Simulation time 236217462 ps
CPU time 1.11 seconds
Started Jul 29 06:15:06 PM PDT 24
Finished Jul 29 06:15:07 PM PDT 24
Peak memory 207076 kb
Host smart-0b1c53c5-e52b-419e-aabd-3cebd50c567d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1544722774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.1544722774
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3648098229
Short name T2402
Test name
Test status
Simulation time 198239136 ps
CPU time 0.98 seconds
Started Jul 29 06:15:08 PM PDT 24
Finished Jul 29 06:15:09 PM PDT 24
Peak memory 207080 kb
Host smart-523b43be-cc74-46f6-8c66-fa5adbe6eef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36480
98229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3648098229
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.2988857722
Short name T1362
Test name
Test status
Simulation time 4906947467 ps
CPU time 134.23 seconds
Started Jul 29 06:15:08 PM PDT 24
Finished Jul 29 06:17:22 PM PDT 24
Peak memory 215448 kb
Host smart-2a88e782-f6c0-4e6a-9cc6-5f701de934bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29888
57722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.2988857722
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1628401042
Short name T2171
Test name
Test status
Simulation time 3392451793 ps
CPU time 25.09 seconds
Started Jul 29 06:15:07 PM PDT 24
Finished Jul 29 06:15:32 PM PDT 24
Peak memory 216956 kb
Host smart-d762e9ce-c919-460a-98f4-cf477d17bc5e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1628401042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1628401042
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1648347338
Short name T370
Test name
Test status
Simulation time 201980338 ps
CPU time 0.91 seconds
Started Jul 29 06:15:06 PM PDT 24
Finished Jul 29 06:15:07 PM PDT 24
Peak memory 207108 kb
Host smart-fca1ba43-7ead-4b4f-83c3-68522cbd83a0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1648347338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1648347338
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.770339682
Short name T638
Test name
Test status
Simulation time 142226799 ps
CPU time 0.82 seconds
Started Jul 29 06:15:08 PM PDT 24
Finished Jul 29 06:15:10 PM PDT 24
Peak memory 206796 kb
Host smart-dc31c716-9826-474d-a16c-550cf9dd4202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77033
9682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.770339682
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3094773812
Short name T427
Test name
Test status
Simulation time 238590525 ps
CPU time 1 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:15:12 PM PDT 24
Peak memory 207104 kb
Host smart-5c70b8fa-5381-4e3e-b228-11750eb84ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30947
73812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3094773812
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2730728878
Short name T2748
Test name
Test status
Simulation time 233545491 ps
CPU time 0.96 seconds
Started Jul 29 06:15:11 PM PDT 24
Finished Jul 29 06:15:12 PM PDT 24
Peak memory 207108 kb
Host smart-01dc316c-2d6e-449e-bc0a-ee992f6456f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27307
28878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2730728878
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.671022735
Short name T452
Test name
Test status
Simulation time 180663065 ps
CPU time 0.87 seconds
Started Jul 29 06:15:09 PM PDT 24
Finished Jul 29 06:15:10 PM PDT 24
Peak memory 207084 kb
Host smart-e8457ec9-fd62-4a42-9961-9d61b46a011d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67102
2735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.671022735
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.747728689
Short name T768
Test name
Test status
Simulation time 155739829 ps
CPU time 0.87 seconds
Started Jul 29 06:15:07 PM PDT 24
Finished Jul 29 06:15:08 PM PDT 24
Peak memory 207036 kb
Host smart-a6f75509-ff23-416c-9058-efe06fe613f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74772
8689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.747728689
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.2036673270
Short name T829
Test name
Test status
Simulation time 248975290 ps
CPU time 1.06 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:15:11 PM PDT 24
Peak memory 206996 kb
Host smart-218ad4ee-f83f-4ab4-9ecc-1b19caf92d76
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2036673270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2036673270
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.4048032610
Short name T2103
Test name
Test status
Simulation time 159671652 ps
CPU time 0.87 seconds
Started Jul 29 06:15:08 PM PDT 24
Finished Jul 29 06:15:08 PM PDT 24
Peak memory 207020 kb
Host smart-cc883761-53c7-415f-8b96-a0d471920d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40480
32610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.4048032610
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1467066914
Short name T2519
Test name
Test status
Simulation time 51649770 ps
CPU time 0.7 seconds
Started Jul 29 06:15:08 PM PDT 24
Finished Jul 29 06:15:09 PM PDT 24
Peak memory 206984 kb
Host smart-c1d9a130-a30c-412c-8bcf-5f964f56223b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14670
66914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1467066914
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.207220312
Short name T2110
Test name
Test status
Simulation time 15083762189 ps
CPU time 35.53 seconds
Started Jul 29 06:15:08 PM PDT 24
Finished Jul 29 06:15:44 PM PDT 24
Peak memory 215604 kb
Host smart-6c05a35e-519e-4acd-a193-c7147aef21c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20722
0312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.207220312
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2397765519
Short name T2385
Test name
Test status
Simulation time 160748353 ps
CPU time 0.87 seconds
Started Jul 29 06:15:08 PM PDT 24
Finished Jul 29 06:15:10 PM PDT 24
Peak memory 206804 kb
Host smart-f5116d35-a316-4f7e-b56d-6276683806c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23977
65519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2397765519
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3672087580
Short name T1498
Test name
Test status
Simulation time 245699915 ps
CPU time 1.02 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:15:12 PM PDT 24
Peak memory 207080 kb
Host smart-dcc811d3-6c2a-4537-8875-b231c48e17d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36720
87580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3672087580
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.3844784187
Short name T608
Test name
Test status
Simulation time 170077885 ps
CPU time 0.96 seconds
Started Jul 29 06:15:08 PM PDT 24
Finished Jul 29 06:15:09 PM PDT 24
Peak memory 207064 kb
Host smart-4e0576ac-779c-4497-b60f-5764e4c6a4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38447
84187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.3844784187
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2216134309
Short name T2686
Test name
Test status
Simulation time 198051488 ps
CPU time 0.95 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:15:11 PM PDT 24
Peak memory 207076 kb
Host smart-2950bb1a-3e60-469d-88c2-99de26da71ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22161
34309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2216134309
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.478596249
Short name T2635
Test name
Test status
Simulation time 141305115 ps
CPU time 0.84 seconds
Started Jul 29 06:15:07 PM PDT 24
Finished Jul 29 06:15:08 PM PDT 24
Peak memory 207000 kb
Host smart-9c33db84-0188-4bb9-8679-42eb436ea615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47859
6249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.478596249
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.292286197
Short name T1001
Test name
Test status
Simulation time 154831852 ps
CPU time 0.85 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:15:11 PM PDT 24
Peak memory 207084 kb
Host smart-b434c2bd-7984-44bb-b840-52cce77d0d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29228
6197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.292286197
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2496212011
Short name T1673
Test name
Test status
Simulation time 194608942 ps
CPU time 0.95 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:15:11 PM PDT 24
Peak memory 206948 kb
Host smart-0b04a75c-451f-4d56-bc78-4107f984cde1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24962
12011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2496212011
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2525985664
Short name T2663
Test name
Test status
Simulation time 251235148 ps
CPU time 1.11 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:15:12 PM PDT 24
Peak memory 207116 kb
Host smart-ad1406ba-04f3-41e2-89a6-0458deae2b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25259
85664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2525985664
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.1451247160
Short name T1620
Test name
Test status
Simulation time 6624179153 ps
CPU time 195.55 seconds
Started Jul 29 06:15:09 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 215616 kb
Host smart-4cddf339-ad5d-44fb-95a4-e93837945261
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1451247160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.1451247160
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.612363906
Short name T1124
Test name
Test status
Simulation time 206636478 ps
CPU time 0.96 seconds
Started Jul 29 06:15:11 PM PDT 24
Finished Jul 29 06:15:12 PM PDT 24
Peak memory 207108 kb
Host smart-54c86389-e107-4938-bb2c-475928b1a9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61236
3906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.612363906
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3146493364
Short name T2609
Test name
Test status
Simulation time 185170980 ps
CPU time 0.94 seconds
Started Jul 29 06:15:09 PM PDT 24
Finished Jul 29 06:15:10 PM PDT 24
Peak memory 207084 kb
Host smart-e636fab3-3bde-4aee-9810-84d83083bb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31464
93364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3146493364
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.815361689
Short name T1858
Test name
Test status
Simulation time 1328941389 ps
CPU time 3.03 seconds
Started Jul 29 06:15:08 PM PDT 24
Finished Jul 29 06:15:12 PM PDT 24
Peak memory 207304 kb
Host smart-4b7fc02e-ccb8-4cc2-ac37-8a7f01d86f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81536
1689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.815361689
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.294963852
Short name T1393
Test name
Test status
Simulation time 6863300725 ps
CPU time 207.54 seconds
Started Jul 29 06:15:05 PM PDT 24
Finished Jul 29 06:18:32 PM PDT 24
Peak memory 215580 kb
Host smart-9f12c18f-18b0-430a-8cac-3a26e6b99365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29496
3852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.294963852
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.1606330957
Short name T97
Test name
Test status
Simulation time 3404144023 ps
CPU time 29.96 seconds
Started Jul 29 06:15:02 PM PDT 24
Finished Jul 29 06:15:33 PM PDT 24
Peak memory 207320 kb
Host smart-b8121030-e2a5-4aa9-ac5e-5d2515f052b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606330957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.1606330957
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.3848289529
Short name T2109
Test name
Test status
Simulation time 39309485 ps
CPU time 0.68 seconds
Started Jul 29 06:15:21 PM PDT 24
Finished Jul 29 06:15:22 PM PDT 24
Peak memory 207144 kb
Host smart-296a5634-7267-4db9-ad38-f39ebcc8d682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3848289529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.3848289529
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.4173142375
Short name T2681
Test name
Test status
Simulation time 4224777233 ps
CPU time 6.7 seconds
Started Jul 29 06:15:11 PM PDT 24
Finished Jul 29 06:15:17 PM PDT 24
Peak memory 207376 kb
Host smart-b1ee60ac-3bb4-4210-850c-238318d58261
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173142375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.4173142375
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.921834883
Short name T1586
Test name
Test status
Simulation time 13359607039 ps
CPU time 16 seconds
Started Jul 29 06:15:12 PM PDT 24
Finished Jul 29 06:15:28 PM PDT 24
Peak memory 207548 kb
Host smart-39994e17-1488-49a6-a8cf-659a1029b406
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=921834883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.921834883
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.712707078
Short name T10
Test name
Test status
Simulation time 23351088647 ps
CPU time 27.59 seconds
Started Jul 29 06:15:12 PM PDT 24
Finished Jul 29 06:15:40 PM PDT 24
Peak memory 207428 kb
Host smart-8765bfca-6335-4a3d-a72d-3cef6d12b7b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712707078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ao
n_wake_resume.712707078
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1972772033
Short name T1040
Test name
Test status
Simulation time 157534495 ps
CPU time 0.87 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:15:11 PM PDT 24
Peak memory 207100 kb
Host smart-c198ae15-fb45-44f6-87ac-eb7e7c452561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19727
72033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1972772033
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3168371721
Short name T1441
Test name
Test status
Simulation time 141756349 ps
CPU time 0.86 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:15:11 PM PDT 24
Peak memory 206968 kb
Host smart-ab304c65-1a41-4f58-b8f3-bac471771f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31683
71721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3168371721
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.4197368231
Short name T1384
Test name
Test status
Simulation time 471535125 ps
CPU time 1.6 seconds
Started Jul 29 06:15:08 PM PDT 24
Finished Jul 29 06:15:10 PM PDT 24
Peak memory 207064 kb
Host smart-a5f41827-d7bc-4586-9aa5-5b46480e9211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41973
68231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.4197368231
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3623424909
Short name T1368
Test name
Test status
Simulation time 1558194295 ps
CPU time 3.72 seconds
Started Jul 29 06:15:09 PM PDT 24
Finished Jul 29 06:15:13 PM PDT 24
Peak memory 207248 kb
Host smart-e7016c4c-98eb-48be-b8d2-f2fdec12ee13
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3623424909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3623424909
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.1240679105
Short name T164
Test name
Test status
Simulation time 17270442578 ps
CPU time 43.25 seconds
Started Jul 29 06:15:14 PM PDT 24
Finished Jul 29 06:15:58 PM PDT 24
Peak memory 207432 kb
Host smart-03275380-7692-426d-bd44-e0184375a33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12406
79105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1240679105
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.3914924240
Short name T2473
Test name
Test status
Simulation time 3378144035 ps
CPU time 29.85 seconds
Started Jul 29 06:15:11 PM PDT 24
Finished Jul 29 06:15:41 PM PDT 24
Peak memory 207392 kb
Host smart-1d4819cc-f9c9-40ba-99ae-6949b2e96d04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914924240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.3914924240
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.3857142678
Short name T806
Test name
Test status
Simulation time 350108207 ps
CPU time 1.42 seconds
Started Jul 29 06:15:13 PM PDT 24
Finished Jul 29 06:15:15 PM PDT 24
Peak memory 207048 kb
Host smart-b0b06ded-0f05-483e-92cb-c02adaab706d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38571
42678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.3857142678
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.905996052
Short name T320
Test name
Test status
Simulation time 144790116 ps
CPU time 0.82 seconds
Started Jul 29 06:15:13 PM PDT 24
Finished Jul 29 06:15:14 PM PDT 24
Peak memory 206996 kb
Host smart-7b7bbfb4-596d-485f-a0bc-030cc5e9d1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90599
6052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.905996052
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1920886171
Short name T851
Test name
Test status
Simulation time 54857360 ps
CPU time 0.77 seconds
Started Jul 29 06:15:11 PM PDT 24
Finished Jul 29 06:15:12 PM PDT 24
Peak memory 207032 kb
Host smart-c7bc60e5-e9de-4bca-bd26-e4583cda9276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19208
86171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1920886171
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.254134023
Short name T2666
Test name
Test status
Simulation time 949308235 ps
CPU time 2.35 seconds
Started Jul 29 06:15:12 PM PDT 24
Finished Jul 29 06:15:14 PM PDT 24
Peak memory 207344 kb
Host smart-71f37117-d9f1-462d-8dde-81b823569c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25413
4023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.254134023
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.4192339414
Short name T1887
Test name
Test status
Simulation time 174102909 ps
CPU time 1.66 seconds
Started Jul 29 06:15:13 PM PDT 24
Finished Jul 29 06:15:15 PM PDT 24
Peak memory 207252 kb
Host smart-8d696f03-66d4-47fb-9920-533d165fd348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41923
39414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.4192339414
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1683305318
Short name T358
Test name
Test status
Simulation time 232137535 ps
CPU time 1.15 seconds
Started Jul 29 06:15:12 PM PDT 24
Finished Jul 29 06:15:13 PM PDT 24
Peak memory 215460 kb
Host smart-05bd4167-fa90-45e1-a81e-530376855455
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1683305318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1683305318
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2524033196
Short name T1568
Test name
Test status
Simulation time 195260784 ps
CPU time 0.87 seconds
Started Jul 29 06:15:13 PM PDT 24
Finished Jul 29 06:15:15 PM PDT 24
Peak memory 207084 kb
Host smart-8141b714-07fb-4bc2-a46f-c64b22eac156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25240
33196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2524033196
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.22483526
Short name T1193
Test name
Test status
Simulation time 224837597 ps
CPU time 1.04 seconds
Started Jul 29 06:15:12 PM PDT 24
Finished Jul 29 06:15:14 PM PDT 24
Peak memory 207148 kb
Host smart-75ad1db0-5163-4a3a-aa00-cc1e8f9e1908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22483
526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.22483526
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.1018741893
Short name T1196
Test name
Test status
Simulation time 6646193015 ps
CPU time 198.98 seconds
Started Jul 29 06:15:11 PM PDT 24
Finished Jul 29 06:18:31 PM PDT 24
Peak memory 215568 kb
Host smart-cca5d20c-47d8-4a2a-bd15-c9ac7860b429
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1018741893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1018741893
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.2684025965
Short name T2392
Test name
Test status
Simulation time 7096868089 ps
CPU time 52.62 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:16:03 PM PDT 24
Peak memory 207404 kb
Host smart-170e8ab3-a53b-4452-ab38-2fc510f0eaf9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2684025965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.2684025965
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2701759797
Short name T1927
Test name
Test status
Simulation time 240438840 ps
CPU time 0.98 seconds
Started Jul 29 06:15:13 PM PDT 24
Finished Jul 29 06:15:14 PM PDT 24
Peak memory 207032 kb
Host smart-73ff8fcc-3b1c-4023-a4a0-e663c060d7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27017
59797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2701759797
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.1750206409
Short name T603
Test name
Test status
Simulation time 23315648821 ps
CPU time 27.19 seconds
Started Jul 29 06:15:12 PM PDT 24
Finished Jul 29 06:15:40 PM PDT 24
Peak memory 207412 kb
Host smart-05fc00c4-c599-4625-9255-3140af1e9988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17502
06409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1750206409
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1295524761
Short name T42
Test name
Test status
Simulation time 3321341635 ps
CPU time 4.97 seconds
Started Jul 29 06:15:14 PM PDT 24
Finished Jul 29 06:15:19 PM PDT 24
Peak memory 207312 kb
Host smart-20922fbb-265c-474e-99b1-086d536f92a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12955
24761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1295524761
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.730394011
Short name T1987
Test name
Test status
Simulation time 5935645157 ps
CPU time 171.45 seconds
Started Jul 29 06:15:12 PM PDT 24
Finished Jul 29 06:18:04 PM PDT 24
Peak memory 215576 kb
Host smart-4ce86620-b6df-443a-a6df-616d80936132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73039
4011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.730394011
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.3643557270
Short name T2449
Test name
Test status
Simulation time 6510859497 ps
CPU time 65.65 seconds
Started Jul 29 06:15:13 PM PDT 24
Finished Jul 29 06:16:19 PM PDT 24
Peak memory 207432 kb
Host smart-4e33708f-b3c5-4571-93db-a7c04cabbfa9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3643557270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.3643557270
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3720554009
Short name T1741
Test name
Test status
Simulation time 257267197 ps
CPU time 1.02 seconds
Started Jul 29 06:15:14 PM PDT 24
Finished Jul 29 06:15:15 PM PDT 24
Peak memory 207252 kb
Host smart-fec7a9b3-755c-403a-ab53-f8c16c2328c9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3720554009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3720554009
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.960671525
Short name T2563
Test name
Test status
Simulation time 209498324 ps
CPU time 0.98 seconds
Started Jul 29 06:15:14 PM PDT 24
Finished Jul 29 06:15:15 PM PDT 24
Peak memory 207084 kb
Host smart-c8b4bebd-2403-4d72-b3a5-a6c0612e2e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96067
1525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.960671525
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.1686721035
Short name T1483
Test name
Test status
Simulation time 4614303986 ps
CPU time 50.07 seconds
Started Jul 29 06:15:11 PM PDT 24
Finished Jul 29 06:16:01 PM PDT 24
Peak memory 217116 kb
Host smart-36bac9c2-c5de-4c01-9c8b-33e7e4fd77bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16867
21035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.1686721035
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.3030651187
Short name T2754
Test name
Test status
Simulation time 4565701978 ps
CPU time 48.02 seconds
Started Jul 29 06:15:13 PM PDT 24
Finished Jul 29 06:16:02 PM PDT 24
Peak memory 207408 kb
Host smart-a7298188-e414-4409-9f55-6ed93bf78f1e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3030651187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3030651187
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.4108424557
Short name T2258
Test name
Test status
Simulation time 207588740 ps
CPU time 0.9 seconds
Started Jul 29 06:15:10 PM PDT 24
Finished Jul 29 06:15:11 PM PDT 24
Peak memory 207100 kb
Host smart-40c1d8ee-2744-4048-b647-f6add2bdd81e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4108424557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.4108424557
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2425421561
Short name T2486
Test name
Test status
Simulation time 187890270 ps
CPU time 0.87 seconds
Started Jul 29 06:15:13 PM PDT 24
Finished Jul 29 06:15:14 PM PDT 24
Peak memory 207052 kb
Host smart-49b91235-d366-4c81-a625-1b2000fba8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24254
21561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2425421561
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.1528156856
Short name T2170
Test name
Test status
Simulation time 148859171 ps
CPU time 0.88 seconds
Started Jul 29 06:15:15 PM PDT 24
Finished Jul 29 06:15:16 PM PDT 24
Peak memory 207188 kb
Host smart-081c69c0-52bf-439e-9dea-3df844fde1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15281
56856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1528156856
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3959489510
Short name T2705
Test name
Test status
Simulation time 194888323 ps
CPU time 0.89 seconds
Started Jul 29 06:15:18 PM PDT 24
Finished Jul 29 06:15:19 PM PDT 24
Peak memory 207136 kb
Host smart-760954de-ce70-4aa2-b742-9f4e2b04d12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39594
89510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3959489510
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1923347516
Short name T271
Test name
Test status
Simulation time 239177995 ps
CPU time 0.95 seconds
Started Jul 29 06:15:18 PM PDT 24
Finished Jul 29 06:15:19 PM PDT 24
Peak memory 207104 kb
Host smart-735f9e10-8e3a-47d9-ad07-9e5c63b2893d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19233
47516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1923347516
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.683715635
Short name T2475
Test name
Test status
Simulation time 156834480 ps
CPU time 0.91 seconds
Started Jul 29 06:15:14 PM PDT 24
Finished Jul 29 06:15:15 PM PDT 24
Peak memory 207004 kb
Host smart-20b17d57-74df-4f41-a681-f1d5592f4433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68371
5635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.683715635
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.189428011
Short name T2598
Test name
Test status
Simulation time 251766235 ps
CPU time 1.16 seconds
Started Jul 29 06:15:15 PM PDT 24
Finished Jul 29 06:15:16 PM PDT 24
Peak memory 207128 kb
Host smart-d725d452-1629-4235-80f2-e3f5ad626d10
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=189428011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.189428011
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3590938537
Short name T2520
Test name
Test status
Simulation time 160915332 ps
CPU time 0.87 seconds
Started Jul 29 06:15:15 PM PDT 24
Finished Jul 29 06:15:17 PM PDT 24
Peak memory 207088 kb
Host smart-904ceca7-bec2-4dad-aa27-35aaf952859d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35909
38537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3590938537
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2061637618
Short name T2541
Test name
Test status
Simulation time 59450849 ps
CPU time 0.72 seconds
Started Jul 29 06:15:17 PM PDT 24
Finished Jul 29 06:15:18 PM PDT 24
Peak memory 207024 kb
Host smart-0111d878-3f6b-45d6-94c2-2edec0933542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20616
37618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2061637618
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.3707359299
Short name T1517
Test name
Test status
Simulation time 23839461031 ps
CPU time 60.42 seconds
Started Jul 29 06:15:17 PM PDT 24
Finished Jul 29 06:16:18 PM PDT 24
Peak memory 215576 kb
Host smart-014f7c50-a834-4dbc-8a87-490ec822bcc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37073
59299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3707359299
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3022721750
Short name T1989
Test name
Test status
Simulation time 195754564 ps
CPU time 0.98 seconds
Started Jul 29 06:15:17 PM PDT 24
Finished Jul 29 06:15:18 PM PDT 24
Peak memory 207052 kb
Host smart-faf29c82-11fa-4528-9b22-5ad64e1c211e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30227
21750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3022721750
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1269289688
Short name T404
Test name
Test status
Simulation time 188605796 ps
CPU time 0.93 seconds
Started Jul 29 06:15:16 PM PDT 24
Finished Jul 29 06:15:17 PM PDT 24
Peak memory 207064 kb
Host smart-7fe19bc8-2caa-40d3-b09e-5cc92577aac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12692
89688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1269289688
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.1584239735
Short name T2047
Test name
Test status
Simulation time 268629502 ps
CPU time 1.03 seconds
Started Jul 29 06:15:15 PM PDT 24
Finished Jul 29 06:15:16 PM PDT 24
Peak memory 207076 kb
Host smart-b39a513a-dae7-4eb5-a8e1-b81ff3bf4882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15842
39735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.1584239735
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.2895077046
Short name T364
Test name
Test status
Simulation time 187718596 ps
CPU time 0.91 seconds
Started Jul 29 06:15:16 PM PDT 24
Finished Jul 29 06:15:17 PM PDT 24
Peak memory 207104 kb
Host smart-5d9a0264-6015-4537-a93f-06ef8cbb5c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28950
77046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.2895077046
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.850523766
Short name T2226
Test name
Test status
Simulation time 145807809 ps
CPU time 0.88 seconds
Started Jul 29 06:15:16 PM PDT 24
Finished Jul 29 06:15:17 PM PDT 24
Peak memory 207044 kb
Host smart-73fcb115-2ff7-446d-9ace-2c54cccb132d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85052
3766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.850523766
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.1005541774
Short name T1091
Test name
Test status
Simulation time 163009473 ps
CPU time 0.85 seconds
Started Jul 29 06:15:14 PM PDT 24
Finished Jul 29 06:15:15 PM PDT 24
Peak memory 207104 kb
Host smart-07b22f7a-b392-43ab-ac90-92348f104d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10055
41774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.1005541774
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.40033014
Short name T805
Test name
Test status
Simulation time 157607349 ps
CPU time 0.92 seconds
Started Jul 29 06:15:17 PM PDT 24
Finished Jul 29 06:15:18 PM PDT 24
Peak memory 207092 kb
Host smart-9391c837-81bd-4740-95b8-e5485a792cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40033
014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.40033014
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3179334344
Short name T2837
Test name
Test status
Simulation time 214544672 ps
CPU time 0.95 seconds
Started Jul 29 06:15:20 PM PDT 24
Finished Jul 29 06:15:21 PM PDT 24
Peak memory 207072 kb
Host smart-e37284c4-4798-485f-b953-9bbdd6eade5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31793
34344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3179334344
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.877316704
Short name T793
Test name
Test status
Simulation time 4484990891 ps
CPU time 34.66 seconds
Started Jul 29 06:15:15 PM PDT 24
Finished Jul 29 06:15:50 PM PDT 24
Peak memory 217172 kb
Host smart-368bc7dc-1cc6-4930-a850-ec293af961d5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=877316704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.877316704
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1027877363
Short name T2617
Test name
Test status
Simulation time 234435683 ps
CPU time 0.92 seconds
Started Jul 29 06:15:17 PM PDT 24
Finished Jul 29 06:15:18 PM PDT 24
Peak memory 207104 kb
Host smart-2691d222-356f-455e-9b20-b3087010ecd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10278
77363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1027877363
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.3044811287
Short name T1275
Test name
Test status
Simulation time 173028236 ps
CPU time 0.88 seconds
Started Jul 29 06:15:15 PM PDT 24
Finished Jul 29 06:15:16 PM PDT 24
Peak memory 207104 kb
Host smart-42240500-9211-4e76-ba37-8a9b92641ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30448
11287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3044811287
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.1661772775
Short name T1760
Test name
Test status
Simulation time 374477740 ps
CPU time 1.35 seconds
Started Jul 29 06:15:16 PM PDT 24
Finished Jul 29 06:15:17 PM PDT 24
Peak memory 207096 kb
Host smart-95c1dcfc-c430-4416-9132-6d503c196761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16617
72775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.1661772775
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3000491765
Short name T1395
Test name
Test status
Simulation time 4534854819 ps
CPU time 46.26 seconds
Started Jul 29 06:15:16 PM PDT 24
Finished Jul 29 06:16:03 PM PDT 24
Peak memory 207380 kb
Host smart-cdc53b6a-bddb-457a-9075-9c8ea74dfedd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30004
91765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3000491765
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.518145014
Short name T470
Test name
Test status
Simulation time 4362514888 ps
CPU time 39.2 seconds
Started Jul 29 06:15:12 PM PDT 24
Finished Jul 29 06:15:51 PM PDT 24
Peak memory 207464 kb
Host smart-6c900f93-f6c0-4957-ad16-2e1721dd54b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518145014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_host
_handshake.518145014
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.4268680665
Short name T885
Test name
Test status
Simulation time 55122727 ps
CPU time 0.71 seconds
Started Jul 29 06:15:30 PM PDT 24
Finished Jul 29 06:15:31 PM PDT 24
Peak memory 207140 kb
Host smart-6a7888cd-271f-48bb-af87-8adf4aaacb61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4268680665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.4268680665
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.4239817463
Short name T1187
Test name
Test status
Simulation time 3660127927 ps
CPU time 5.5 seconds
Started Jul 29 06:15:24 PM PDT 24
Finished Jul 29 06:15:30 PM PDT 24
Peak memory 207396 kb
Host smart-c634a3c1-71f7-472b-8259-24fa0fc15e02
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239817463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.4239817463
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3096473995
Short name T1576
Test name
Test status
Simulation time 13360055334 ps
CPU time 16.69 seconds
Started Jul 29 06:15:20 PM PDT 24
Finished Jul 29 06:15:37 PM PDT 24
Peak memory 207380 kb
Host smart-c3576f27-f879-4d8c-82ba-88257ec2e1c4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096473995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3096473995
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.356602148
Short name T1529
Test name
Test status
Simulation time 23343782105 ps
CPU time 27.6 seconds
Started Jul 29 06:15:21 PM PDT 24
Finished Jul 29 06:15:49 PM PDT 24
Peak memory 207388 kb
Host smart-30bbe354-39c4-4b3b-bd09-da42ef63fdb1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356602148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_ao
n_wake_resume.356602148
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1046542942
Short name T2270
Test name
Test status
Simulation time 189144372 ps
CPU time 0.88 seconds
Started Jul 29 06:15:20 PM PDT 24
Finished Jul 29 06:15:20 PM PDT 24
Peak memory 207112 kb
Host smart-9a45d831-8dd7-488b-86a9-2b71a1d7a207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10465
42942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1046542942
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.1577488879
Short name T2764
Test name
Test status
Simulation time 184790568 ps
CPU time 0.88 seconds
Started Jul 29 06:15:20 PM PDT 24
Finished Jul 29 06:15:21 PM PDT 24
Peak memory 207232 kb
Host smart-c61ebb28-852b-4654-8cbd-9d5a35ad5592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15774
88879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.1577488879
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.3903532769
Short name T30
Test name
Test status
Simulation time 356799357 ps
CPU time 1.27 seconds
Started Jul 29 06:15:24 PM PDT 24
Finished Jul 29 06:15:26 PM PDT 24
Peak memory 207116 kb
Host smart-7fb441b3-dc49-4789-b75c-2840485ce9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39035
32769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.3903532769
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.3683336177
Short name T1477
Test name
Test status
Simulation time 717315625 ps
CPU time 2.06 seconds
Started Jul 29 06:15:21 PM PDT 24
Finished Jul 29 06:15:23 PM PDT 24
Peak memory 207092 kb
Host smart-e4fc8fd3-26ba-429d-8f42-1d31b6daba91
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3683336177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.3683336177
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.3844928887
Short name T2497
Test name
Test status
Simulation time 9421056085 ps
CPU time 21.49 seconds
Started Jul 29 06:15:21 PM PDT 24
Finished Jul 29 06:15:43 PM PDT 24
Peak memory 207376 kb
Host smart-763d8b2c-5f3c-4e2b-9aff-35fc33007e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38449
28887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.3844928887
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.2885493351
Short name T1781
Test name
Test status
Simulation time 207955576 ps
CPU time 0.97 seconds
Started Jul 29 06:15:21 PM PDT 24
Finished Jul 29 06:15:22 PM PDT 24
Peak memory 207088 kb
Host smart-8a774e3b-a370-4fe9-8629-db686aaa2720
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885493351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.2885493351
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.966096343
Short name T1328
Test name
Test status
Simulation time 350860583 ps
CPU time 1.31 seconds
Started Jul 29 06:15:23 PM PDT 24
Finished Jul 29 06:15:24 PM PDT 24
Peak memory 207092 kb
Host smart-f6164da8-cb22-4b95-a3b0-f9cba0c1550e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96609
6343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.966096343
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2240901477
Short name T1949
Test name
Test status
Simulation time 144864295 ps
CPU time 0.94 seconds
Started Jul 29 06:15:19 PM PDT 24
Finished Jul 29 06:15:20 PM PDT 24
Peak memory 207092 kb
Host smart-b6a477f0-0bad-4d4b-8a90-b8bfe12503c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22409
01477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2240901477
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.490602007
Short name T1031
Test name
Test status
Simulation time 26427147 ps
CPU time 0.7 seconds
Started Jul 29 06:15:21 PM PDT 24
Finished Jul 29 06:15:21 PM PDT 24
Peak memory 207044 kb
Host smart-8fdf4509-1336-40a7-a1e0-944cd0f40a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49060
2007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.490602007
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.1118101747
Short name T1979
Test name
Test status
Simulation time 914771202 ps
CPU time 2.21 seconds
Started Jul 29 06:15:19 PM PDT 24
Finished Jul 29 06:15:22 PM PDT 24
Peak memory 207328 kb
Host smart-009ffa54-7b8d-4c54-b607-05aee6ffac3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11181
01747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.1118101747
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.347200391
Short name T1070
Test name
Test status
Simulation time 224181894 ps
CPU time 1.65 seconds
Started Jul 29 06:15:24 PM PDT 24
Finished Jul 29 06:15:26 PM PDT 24
Peak memory 207252 kb
Host smart-926fb151-d47d-4472-9899-1c50fb050324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34720
0391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.347200391
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3162467176
Short name T2079
Test name
Test status
Simulation time 219266377 ps
CPU time 0.98 seconds
Started Jul 29 06:15:22 PM PDT 24
Finished Jul 29 06:15:23 PM PDT 24
Peak memory 207132 kb
Host smart-a3f72eb7-b647-4ad1-ae09-fb232a21459d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3162467176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3162467176
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3293454863
Short name T102
Test name
Test status
Simulation time 180118554 ps
CPU time 0.87 seconds
Started Jul 29 06:15:21 PM PDT 24
Finished Jul 29 06:15:22 PM PDT 24
Peak memory 206952 kb
Host smart-73032a19-385f-4533-af78-8dcb2280dc52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32934
54863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3293454863
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1349378154
Short name T2100
Test name
Test status
Simulation time 166969159 ps
CPU time 0.89 seconds
Started Jul 29 06:15:24 PM PDT 24
Finished Jul 29 06:15:25 PM PDT 24
Peak memory 207124 kb
Host smart-f01591a2-8e37-41e8-9c48-201592e66c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13493
78154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1349378154
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.152266556
Short name T2329
Test name
Test status
Simulation time 7439210447 ps
CPU time 77.63 seconds
Started Jul 29 06:15:22 PM PDT 24
Finished Jul 29 06:16:40 PM PDT 24
Peak memory 215632 kb
Host smart-a12963cb-c808-4242-9099-4f7d7dba9ab4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=152266556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.152266556
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.4178578288
Short name T1471
Test name
Test status
Simulation time 13218001473 ps
CPU time 149.22 seconds
Started Jul 29 06:15:22 PM PDT 24
Finished Jul 29 06:17:51 PM PDT 24
Peak memory 207336 kb
Host smart-3f3310af-3b05-49a3-ae19-16ea91ca9105
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4178578288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.4178578288
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.593802594
Short name T1486
Test name
Test status
Simulation time 233272994 ps
CPU time 1.03 seconds
Started Jul 29 06:15:24 PM PDT 24
Finished Jul 29 06:15:25 PM PDT 24
Peak memory 207100 kb
Host smart-fbf65483-f236-42ea-b314-f906904719c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59380
2594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.593802594
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.3271896836
Short name T642
Test name
Test status
Simulation time 23318180466 ps
CPU time 25.5 seconds
Started Jul 29 06:15:24 PM PDT 24
Finished Jul 29 06:15:49 PM PDT 24
Peak memory 207388 kb
Host smart-20840603-bbe2-446f-b5cc-62547ce7ec16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32718
96836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.3271896836
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.2188438863
Short name T324
Test name
Test status
Simulation time 3334171428 ps
CPU time 5.02 seconds
Started Jul 29 06:15:22 PM PDT 24
Finished Jul 29 06:15:27 PM PDT 24
Peak memory 207332 kb
Host smart-7263d1f8-feee-420b-a4f9-19b04f0a49fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21884
38863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2188438863
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.77902404
Short name T2238
Test name
Test status
Simulation time 7155129362 ps
CPU time 56.13 seconds
Started Jul 29 06:15:24 PM PDT 24
Finished Jul 29 06:16:21 PM PDT 24
Peak memory 217692 kb
Host smart-8d3c0c25-f30c-4c85-b2ef-25e36642b1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77902
404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.77902404
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.2437504365
Short name T1084
Test name
Test status
Simulation time 5464070977 ps
CPU time 164.15 seconds
Started Jul 29 06:15:21 PM PDT 24
Finished Jul 29 06:18:06 PM PDT 24
Peak memory 215596 kb
Host smart-65f5ea48-134b-4894-bf83-363138e1e419
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2437504365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.2437504365
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.553489776
Short name T720
Test name
Test status
Simulation time 245161660 ps
CPU time 0.97 seconds
Started Jul 29 06:15:22 PM PDT 24
Finished Jul 29 06:15:23 PM PDT 24
Peak memory 207116 kb
Host smart-3e2611e2-1840-44eb-bbaa-3657719ce667
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=553489776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.553489776
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2456672345
Short name T739
Test name
Test status
Simulation time 190787025 ps
CPU time 1 seconds
Started Jul 29 06:15:20 PM PDT 24
Finished Jul 29 06:15:21 PM PDT 24
Peak memory 207052 kb
Host smart-18b39e81-09cc-45bc-8dca-dae7b3840f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24566
72345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2456672345
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.764521062
Short name T2015
Test name
Test status
Simulation time 6076901394 ps
CPU time 191.01 seconds
Started Jul 29 06:15:27 PM PDT 24
Finished Jul 29 06:18:38 PM PDT 24
Peak memory 215592 kb
Host smart-b480ea1d-7710-4758-9d8e-b3f0b04304a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76452
1062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.764521062
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.1221931522
Short name T2506
Test name
Test status
Simulation time 4780903838 ps
CPU time 150.16 seconds
Started Jul 29 06:15:25 PM PDT 24
Finished Jul 29 06:17:55 PM PDT 24
Peak memory 215620 kb
Host smart-df6b445d-1912-43e9-b07e-5c8c20eea13b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1221931522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.1221931522
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.2062296008
Short name T495
Test name
Test status
Simulation time 150625089 ps
CPU time 0.81 seconds
Started Jul 29 06:15:25 PM PDT 24
Finished Jul 29 06:15:26 PM PDT 24
Peak memory 207180 kb
Host smart-028a9907-a76e-451e-9b4b-0b43003bc65e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2062296008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2062296008
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.457795230
Short name T1510
Test name
Test status
Simulation time 145587384 ps
CPU time 0.85 seconds
Started Jul 29 06:15:28 PM PDT 24
Finished Jul 29 06:15:29 PM PDT 24
Peak memory 207096 kb
Host smart-3004343b-2e28-4e56-a581-3eae5479185a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45779
5230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.457795230
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3737245818
Short name T141
Test name
Test status
Simulation time 205814816 ps
CPU time 0.96 seconds
Started Jul 29 06:15:29 PM PDT 24
Finished Jul 29 06:15:30 PM PDT 24
Peak memory 207104 kb
Host smart-1fd156f1-5889-4047-80b5-c1c78b4c9fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37372
45818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3737245818
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.2917540638
Short name T1617
Test name
Test status
Simulation time 176258121 ps
CPU time 0.9 seconds
Started Jul 29 06:15:26 PM PDT 24
Finished Jul 29 06:15:27 PM PDT 24
Peak memory 207108 kb
Host smart-359eb8a8-bace-4173-a31f-5d3923124775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29175
40638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.2917540638
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2151744126
Short name T1415
Test name
Test status
Simulation time 175031824 ps
CPU time 0.86 seconds
Started Jul 29 06:15:25 PM PDT 24
Finished Jul 29 06:15:26 PM PDT 24
Peak memory 207056 kb
Host smart-e0225cff-9ddb-4a4f-8e69-e7c2ee03486d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21517
44126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2151744126
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2764830553
Short name T527
Test name
Test status
Simulation time 164892936 ps
CPU time 0.97 seconds
Started Jul 29 06:15:24 PM PDT 24
Finished Jul 29 06:15:25 PM PDT 24
Peak memory 207104 kb
Host smart-82ea1f92-e860-495f-a8b0-9620c0c47b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27648
30553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2764830553
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1944894765
Short name T653
Test name
Test status
Simulation time 158960956 ps
CPU time 0.87 seconds
Started Jul 29 06:15:25 PM PDT 24
Finished Jul 29 06:15:26 PM PDT 24
Peak memory 207108 kb
Host smart-0b2ed997-0679-4223-a172-f630951ea64a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19448
94765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1944894765
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.2071656082
Short name T995
Test name
Test status
Simulation time 233311320 ps
CPU time 1.01 seconds
Started Jul 29 06:15:29 PM PDT 24
Finished Jul 29 06:15:30 PM PDT 24
Peak memory 207120 kb
Host smart-b550506d-e87e-48f8-adc8-7e87bede52ea
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2071656082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.2071656082
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3063593051
Short name T1748
Test name
Test status
Simulation time 155837228 ps
CPU time 0.86 seconds
Started Jul 29 06:15:27 PM PDT 24
Finished Jul 29 06:15:28 PM PDT 24
Peak memory 207064 kb
Host smart-e1828909-e5f2-4a73-8534-37ece6c187d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30635
93051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3063593051
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3385033629
Short name T1886
Test name
Test status
Simulation time 8046620388 ps
CPU time 22.7 seconds
Started Jul 29 06:15:26 PM PDT 24
Finished Jul 29 06:15:49 PM PDT 24
Peak memory 215616 kb
Host smart-dd126b9e-e361-4fad-a846-630a4f58f40a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33850
33629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3385033629
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.128725739
Short name T556
Test name
Test status
Simulation time 178241255 ps
CPU time 0.89 seconds
Started Jul 29 06:15:24 PM PDT 24
Finished Jul 29 06:15:25 PM PDT 24
Peak memory 207000 kb
Host smart-f280c2b7-f53e-459a-aefb-8d012e9a9d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12872
5739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.128725739
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1414287254
Short name T1407
Test name
Test status
Simulation time 227626292 ps
CPU time 0.96 seconds
Started Jul 29 06:15:27 PM PDT 24
Finished Jul 29 06:15:28 PM PDT 24
Peak memory 207072 kb
Host smart-9291dfb7-5c6d-4d96-9a43-f1b56f47d70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14142
87254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1414287254
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.712826353
Short name T1780
Test name
Test status
Simulation time 172220066 ps
CPU time 0.84 seconds
Started Jul 29 06:15:25 PM PDT 24
Finished Jul 29 06:15:26 PM PDT 24
Peak memory 207116 kb
Host smart-8b9c5b78-d1d7-4f4b-b439-9f506754b3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71282
6353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.712826353
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.389074208
Short name T2517
Test name
Test status
Simulation time 172096076 ps
CPU time 0.93 seconds
Started Jul 29 06:15:28 PM PDT 24
Finished Jul 29 06:15:29 PM PDT 24
Peak memory 207104 kb
Host smart-6422793d-4df5-4d40-93f5-a1dc2fef6ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38907
4208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.389074208
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2787965957
Short name T692
Test name
Test status
Simulation time 169306736 ps
CPU time 0.9 seconds
Started Jul 29 06:15:24 PM PDT 24
Finished Jul 29 06:15:25 PM PDT 24
Peak memory 207096 kb
Host smart-11d9a306-324f-47e4-8788-3a5f828df663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27879
65957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2787965957
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3392017593
Short name T2426
Test name
Test status
Simulation time 160682664 ps
CPU time 0.86 seconds
Started Jul 29 06:15:27 PM PDT 24
Finished Jul 29 06:15:28 PM PDT 24
Peak memory 207072 kb
Host smart-b9a126a5-2ca3-4055-bc73-b32a950c5559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33920
17593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3392017593
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1449078839
Short name T545
Test name
Test status
Simulation time 165485878 ps
CPU time 0.87 seconds
Started Jul 29 06:15:27 PM PDT 24
Finished Jul 29 06:15:28 PM PDT 24
Peak memory 207004 kb
Host smart-b4b91042-7986-469d-9927-9e2e609d6d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14490
78839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1449078839
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.615589254
Short name T1127
Test name
Test status
Simulation time 217014609 ps
CPU time 0.99 seconds
Started Jul 29 06:15:28 PM PDT 24
Finished Jul 29 06:15:29 PM PDT 24
Peak memory 207068 kb
Host smart-856f342f-3f75-410d-ba9d-47ac1b8eba50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61558
9254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.615589254
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1480754390
Short name T1549
Test name
Test status
Simulation time 5812841006 ps
CPU time 170.4 seconds
Started Jul 29 06:15:25 PM PDT 24
Finished Jul 29 06:18:16 PM PDT 24
Peak memory 215588 kb
Host smart-c1102639-65d4-4f00-8f5d-12a47acc8646
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1480754390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1480754390
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3943876886
Short name T2391
Test name
Test status
Simulation time 227849930 ps
CPU time 0.99 seconds
Started Jul 29 06:15:29 PM PDT 24
Finished Jul 29 06:15:30 PM PDT 24
Peak memory 207084 kb
Host smart-233e3f6a-5912-4c23-9700-db32fee41160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39438
76886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3943876886
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.4283275533
Short name T1880
Test name
Test status
Simulation time 183742199 ps
CPU time 0.89 seconds
Started Jul 29 06:15:27 PM PDT 24
Finished Jul 29 06:15:28 PM PDT 24
Peak memory 207228 kb
Host smart-741a7f0a-53e5-4f35-9780-e9bf15849761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42832
75533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.4283275533
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.813435813
Short name T1768
Test name
Test status
Simulation time 1271349047 ps
CPU time 3.56 seconds
Started Jul 29 06:15:27 PM PDT 24
Finished Jul 29 06:15:30 PM PDT 24
Peak memory 207280 kb
Host smart-a055ab6c-95cc-404b-8a13-56506267ed7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81343
5813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.813435813
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.1889988309
Short name T1911
Test name
Test status
Simulation time 5680064314 ps
CPU time 167.87 seconds
Started Jul 29 06:15:26 PM PDT 24
Finished Jul 29 06:18:14 PM PDT 24
Peak memory 215500 kb
Host smart-1df86b56-265c-4cd9-b14c-7c9c51a3dc4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18899
88309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.1889988309
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.4081002033
Short name T2349
Test name
Test status
Simulation time 796069013 ps
CPU time 15.48 seconds
Started Jul 29 06:15:20 PM PDT 24
Finished Jul 29 06:15:36 PM PDT 24
Peak memory 207336 kb
Host smart-82662e15-1365-43ea-bc7e-afc6ece66447
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081002033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.4081002033
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.3679928638
Short name T2778
Test name
Test status
Simulation time 37366594 ps
CPU time 0.68 seconds
Started Jul 29 06:15:42 PM PDT 24
Finished Jul 29 06:15:42 PM PDT 24
Peak memory 207120 kb
Host smart-17dac409-1062-4663-a13a-a564f910a8a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3679928638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.3679928638
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.505056178
Short name T1478
Test name
Test status
Simulation time 4077042186 ps
CPU time 5.62 seconds
Started Jul 29 06:15:25 PM PDT 24
Finished Jul 29 06:15:31 PM PDT 24
Peak memory 207324 kb
Host smart-eb1a1d6a-f747-463f-98c8-3014baf8e441
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505056178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ao
n_wake_disconnect.505056178
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.4013679016
Short name T1846
Test name
Test status
Simulation time 13484765175 ps
CPU time 15.58 seconds
Started Jul 29 06:15:27 PM PDT 24
Finished Jul 29 06:15:43 PM PDT 24
Peak memory 207428 kb
Host smart-4a6d1cd6-51e5-439b-bf35-3d65f5a80d6d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013679016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.4013679016
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.484704540
Short name T2653
Test name
Test status
Simulation time 23369642100 ps
CPU time 27.51 seconds
Started Jul 29 06:15:27 PM PDT 24
Finished Jul 29 06:15:55 PM PDT 24
Peak memory 207356 kb
Host smart-98dd53bf-adbe-43cc-bcc8-a2d456a5b8fd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484704540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ao
n_wake_resume.484704540
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3159513864
Short name T319
Test name
Test status
Simulation time 150124031 ps
CPU time 0.85 seconds
Started Jul 29 06:15:25 PM PDT 24
Finished Jul 29 06:15:26 PM PDT 24
Peak memory 207104 kb
Host smart-094bc852-eedc-4758-9a89-db01fbc00c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31595
13864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3159513864
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.655084598
Short name T918
Test name
Test status
Simulation time 170536316 ps
CPU time 0.85 seconds
Started Jul 29 06:15:27 PM PDT 24
Finished Jul 29 06:15:28 PM PDT 24
Peak memory 207044 kb
Host smart-2a0e916b-a899-40da-867c-f757fe5555cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65508
4598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.655084598
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.2657816901
Short name T792
Test name
Test status
Simulation time 428017546 ps
CPU time 1.53 seconds
Started Jul 29 06:15:30 PM PDT 24
Finished Jul 29 06:15:32 PM PDT 24
Peak memory 207272 kb
Host smart-c01a877f-b17d-4520-b907-ea0deb6e49f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26578
16901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.2657816901
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.327376373
Short name T1749
Test name
Test status
Simulation time 308381887 ps
CPU time 1.05 seconds
Started Jul 29 06:15:31 PM PDT 24
Finished Jul 29 06:15:33 PM PDT 24
Peak memory 207080 kb
Host smart-4985b5ba-2394-4807-b0bf-a67c46ef7443
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=327376373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.327376373
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.2940111434
Short name T2806
Test name
Test status
Simulation time 17634682644 ps
CPU time 42.21 seconds
Started Jul 29 06:15:39 PM PDT 24
Finished Jul 29 06:16:21 PM PDT 24
Peak memory 207408 kb
Host smart-645fb4ae-9dc2-4dae-a2e0-4197247e9275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29401
11434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2940111434
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.4017298916
Short name T2665
Test name
Test status
Simulation time 3908683480 ps
CPU time 34.53 seconds
Started Jul 29 06:15:32 PM PDT 24
Finished Jul 29 06:16:07 PM PDT 24
Peak memory 207384 kb
Host smart-bc0bb46a-aac8-4788-99f6-35b3e6df5b04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017298916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.4017298916
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.1606733596
Short name T1330
Test name
Test status
Simulation time 511409079 ps
CPU time 1.75 seconds
Started Jul 29 06:15:30 PM PDT 24
Finished Jul 29 06:15:32 PM PDT 24
Peak memory 206968 kb
Host smart-b0fb8977-1c55-460a-80be-12ae3cea2666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16067
33596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.1606733596
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3217408053
Short name T774
Test name
Test status
Simulation time 184438082 ps
CPU time 0.96 seconds
Started Jul 29 06:15:34 PM PDT 24
Finished Jul 29 06:15:35 PM PDT 24
Peak memory 207032 kb
Host smart-e43b5dfe-7993-48ba-8eb3-96e5419dafda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32174
08053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3217408053
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.891943980
Short name T1804
Test name
Test status
Simulation time 89217250 ps
CPU time 0.74 seconds
Started Jul 29 06:15:32 PM PDT 24
Finished Jul 29 06:15:33 PM PDT 24
Peak memory 207040 kb
Host smart-755e56a5-6579-4513-aca1-4677a7babe2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89194
3980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.891943980
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.3735611231
Short name T1885
Test name
Test status
Simulation time 1040807262 ps
CPU time 2.73 seconds
Started Jul 29 06:15:31 PM PDT 24
Finished Jul 29 06:15:34 PM PDT 24
Peak memory 207336 kb
Host smart-b1bbafbd-d163-4c0b-991c-3b950488ec19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37356
11231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.3735611231
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1304086324
Short name T2025
Test name
Test status
Simulation time 245096928 ps
CPU time 2.37 seconds
Started Jul 29 06:15:31 PM PDT 24
Finished Jul 29 06:15:34 PM PDT 24
Peak memory 207280 kb
Host smart-d0e7a4ae-fd6f-4576-a18d-9aa05f2465aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13040
86324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1304086324
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2971428770
Short name T997
Test name
Test status
Simulation time 163078705 ps
CPU time 0.94 seconds
Started Jul 29 06:15:39 PM PDT 24
Finished Jul 29 06:15:40 PM PDT 24
Peak memory 207144 kb
Host smart-cb9bf4e5-f044-4619-8a07-827b196bee79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2971428770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2971428770
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.722633352
Short name T2273
Test name
Test status
Simulation time 163448561 ps
CPU time 0.91 seconds
Started Jul 29 06:15:34 PM PDT 24
Finished Jul 29 06:15:35 PM PDT 24
Peak memory 207024 kb
Host smart-d165284a-b939-4f95-82af-8643f2820cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72263
3352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.722633352
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3544845924
Short name T838
Test name
Test status
Simulation time 194472793 ps
CPU time 0.94 seconds
Started Jul 29 06:15:31 PM PDT 24
Finished Jul 29 06:15:32 PM PDT 24
Peak memory 207100 kb
Host smart-3cdd08e0-fce9-4ea1-b789-80df4edc970d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35448
45924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3544845924
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.1258800474
Short name T797
Test name
Test status
Simulation time 9132398274 ps
CPU time 269.69 seconds
Started Jul 29 06:15:30 PM PDT 24
Finished Jul 29 06:20:00 PM PDT 24
Peak memory 215568 kb
Host smart-97910027-49e5-45cd-ab20-570d3445926c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1258800474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.1258800474
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.2494584212
Short name T2285
Test name
Test status
Simulation time 13387384100 ps
CPU time 170.47 seconds
Started Jul 29 06:15:39 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207380 kb
Host smart-ed6d6920-a6eb-46a8-992c-71ea4cb43570
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2494584212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.2494584212
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3191056515
Short name T882
Test name
Test status
Simulation time 210018920 ps
CPU time 0.96 seconds
Started Jul 29 06:15:39 PM PDT 24
Finished Jul 29 06:15:40 PM PDT 24
Peak memory 207040 kb
Host smart-824dee4c-c785-440f-bfef-b8478a79bf51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31910
56515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3191056515
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.2548588526
Short name T1543
Test name
Test status
Simulation time 23307558874 ps
CPU time 30.88 seconds
Started Jul 29 06:15:31 PM PDT 24
Finished Jul 29 06:16:01 PM PDT 24
Peak memory 207412 kb
Host smart-d2689091-2f86-41f3-9356-cc1e430876fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25485
88526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.2548588526
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2718862528
Short name T1973
Test name
Test status
Simulation time 3327739744 ps
CPU time 5.44 seconds
Started Jul 29 06:15:32 PM PDT 24
Finished Jul 29 06:15:38 PM PDT 24
Peak memory 207340 kb
Host smart-a4f530da-db6b-42f2-b3bf-45ff76dedb47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27188
62528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2718862528
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.2753744738
Short name T550
Test name
Test status
Simulation time 7557043795 ps
CPU time 74.06 seconds
Started Jul 29 06:15:31 PM PDT 24
Finished Jul 29 06:16:45 PM PDT 24
Peak memory 223844 kb
Host smart-926aa3f4-d1e9-4ecd-a1a1-129dc61d1cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27537
44738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.2753744738
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.335127518
Short name T1716
Test name
Test status
Simulation time 3275614974 ps
CPU time 34.17 seconds
Started Jul 29 06:15:38 PM PDT 24
Finished Jul 29 06:16:13 PM PDT 24
Peak memory 217004 kb
Host smart-bb287e7d-03a3-4b4b-8c97-08fd21676a1b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=335127518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.335127518
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.700422547
Short name T1190
Test name
Test status
Simulation time 243367621 ps
CPU time 1.03 seconds
Started Jul 29 06:15:29 PM PDT 24
Finished Jul 29 06:15:30 PM PDT 24
Peak memory 207100 kb
Host smart-9a563a85-978a-42d1-a76a-10bf9bcf7164
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=700422547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.700422547
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.68718941
Short name T1719
Test name
Test status
Simulation time 210408247 ps
CPU time 0.98 seconds
Started Jul 29 06:15:31 PM PDT 24
Finished Jul 29 06:15:32 PM PDT 24
Peak memory 207232 kb
Host smart-09abbeb5-c9ef-4f0d-89e4-9255c051e361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68718
941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.68718941
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.2682239581
Short name T1495
Test name
Test status
Simulation time 4934481664 ps
CPU time 41.68 seconds
Started Jul 29 06:15:34 PM PDT 24
Finished Jul 29 06:16:16 PM PDT 24
Peak memory 215496 kb
Host smart-208c6f54-8c24-4791-b350-55f7202a083e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26822
39581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.2682239581
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3723852782
Short name T1990
Test name
Test status
Simulation time 4529198692 ps
CPU time 33.99 seconds
Started Jul 29 06:15:31 PM PDT 24
Finished Jul 29 06:16:05 PM PDT 24
Peak memory 207392 kb
Host smart-02d9b890-5de3-46d4-94f3-9be1498ce0a6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3723852782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3723852782
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.4152254477
Short name T2480
Test name
Test status
Simulation time 160363061 ps
CPU time 0.84 seconds
Started Jul 29 06:15:30 PM PDT 24
Finished Jul 29 06:15:31 PM PDT 24
Peak memory 207084 kb
Host smart-6acc3ca5-584a-4498-809d-4799cf8f3dff
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4152254477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.4152254477
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1690895760
Short name T604
Test name
Test status
Simulation time 166465001 ps
CPU time 0.84 seconds
Started Jul 29 06:15:26 PM PDT 24
Finished Jul 29 06:15:27 PM PDT 24
Peak memory 207016 kb
Host smart-c7898f83-2145-4915-9895-db58a69fdb7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16908
95760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1690895760
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3092352647
Short name T2102
Test name
Test status
Simulation time 171114834 ps
CPU time 0.98 seconds
Started Jul 29 06:15:31 PM PDT 24
Finished Jul 29 06:15:33 PM PDT 24
Peak memory 207080 kb
Host smart-9ec59d2f-5196-4fd5-ac92-40f512c83a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30923
52647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3092352647
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.1285555763
Short name T2749
Test name
Test status
Simulation time 190773396 ps
CPU time 0.96 seconds
Started Jul 29 06:15:38 PM PDT 24
Finished Jul 29 06:15:39 PM PDT 24
Peak memory 207068 kb
Host smart-8d7155a7-c43e-4f3c-b5bd-45688070678c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12855
55763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.1285555763
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1214396972
Short name T760
Test name
Test status
Simulation time 183290584 ps
CPU time 0.93 seconds
Started Jul 29 06:15:35 PM PDT 24
Finished Jul 29 06:15:36 PM PDT 24
Peak memory 207000 kb
Host smart-5439da3e-4a69-40c2-8525-bf435be58efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12143
96972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1214396972
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3911884674
Short name T1528
Test name
Test status
Simulation time 203624408 ps
CPU time 0.92 seconds
Started Jul 29 06:15:36 PM PDT 24
Finished Jul 29 06:15:37 PM PDT 24
Peak memory 207084 kb
Host smart-cb1c86cc-e27e-4ecb-bf81-62c96dc6affe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39118
84674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3911884674
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1677684245
Short name T157
Test name
Test status
Simulation time 159192118 ps
CPU time 0.88 seconds
Started Jul 29 06:15:36 PM PDT 24
Finished Jul 29 06:15:37 PM PDT 24
Peak memory 207044 kb
Host smart-4166b9fa-1b90-47af-bb23-df2aa9aea579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16776
84245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1677684245
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.2952507908
Short name T815
Test name
Test status
Simulation time 196506241 ps
CPU time 0.96 seconds
Started Jul 29 06:15:34 PM PDT 24
Finished Jul 29 06:15:36 PM PDT 24
Peak memory 207100 kb
Host smart-585f1bc0-c397-4dc5-bb6a-4aad4ce71cf1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2952507908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.2952507908
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3073781717
Short name T963
Test name
Test status
Simulation time 157306152 ps
CPU time 0.87 seconds
Started Jul 29 06:15:34 PM PDT 24
Finished Jul 29 06:15:35 PM PDT 24
Peak memory 207056 kb
Host smart-c9c2af0d-7657-41f3-b801-cac40b134551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30737
81717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3073781717
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1499478780
Short name T671
Test name
Test status
Simulation time 30902824 ps
CPU time 0.68 seconds
Started Jul 29 06:15:51 PM PDT 24
Finished Jul 29 06:15:52 PM PDT 24
Peak memory 207024 kb
Host smart-0245d135-7c30-40b5-86f2-145e8a3f6d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14994
78780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1499478780
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.492559932
Short name T2649
Test name
Test status
Simulation time 21473497060 ps
CPU time 52.53 seconds
Started Jul 29 06:15:36 PM PDT 24
Finished Jul 29 06:16:29 PM PDT 24
Peak memory 215676 kb
Host smart-347904a7-13bd-4b2c-9df2-fe07704c6b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49255
9932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.492559932
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2181918973
Short name T2733
Test name
Test status
Simulation time 190330163 ps
CPU time 0.98 seconds
Started Jul 29 06:15:35 PM PDT 24
Finished Jul 29 06:15:36 PM PDT 24
Peak memory 207084 kb
Host smart-9ee553e6-ad5b-427c-9f80-cbeddb4c99b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21819
18973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2181918973
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2288271077
Short name T2695
Test name
Test status
Simulation time 159523517 ps
CPU time 0.88 seconds
Started Jul 29 06:15:33 PM PDT 24
Finished Jul 29 06:15:34 PM PDT 24
Peak memory 207096 kb
Host smart-3cac026b-51c7-4c04-b272-43d4746a7c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22882
71077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2288271077
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3949704049
Short name T560
Test name
Test status
Simulation time 199740851 ps
CPU time 0.86 seconds
Started Jul 29 06:15:33 PM PDT 24
Finished Jul 29 06:15:34 PM PDT 24
Peak memory 207068 kb
Host smart-3d40bc70-75f1-498b-9bc3-efe605a984b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39497
04049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3949704049
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.115638927
Short name T1278
Test name
Test status
Simulation time 184060809 ps
CPU time 0.98 seconds
Started Jul 29 06:15:36 PM PDT 24
Finished Jul 29 06:15:37 PM PDT 24
Peak memory 207136 kb
Host smart-644396f5-d786-4366-b251-1d70ddfdf6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11563
8927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.115638927
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3952377314
Short name T2783
Test name
Test status
Simulation time 144314621 ps
CPU time 0.9 seconds
Started Jul 29 06:15:35 PM PDT 24
Finished Jul 29 06:15:36 PM PDT 24
Peak memory 207000 kb
Host smart-4ea5dea8-f7c0-4bf5-b9c5-2b7f2d0ad8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39523
77314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3952377314
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1337079867
Short name T1149
Test name
Test status
Simulation time 230731178 ps
CPU time 0.93 seconds
Started Jul 29 06:15:33 PM PDT 24
Finished Jul 29 06:15:34 PM PDT 24
Peak memory 207068 kb
Host smart-cfa674af-ae53-4df4-b3cc-1cd5f70ea7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13370
79867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1337079867
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1543866444
Short name T759
Test name
Test status
Simulation time 194983726 ps
CPU time 0.9 seconds
Started Jul 29 06:15:35 PM PDT 24
Finished Jul 29 06:15:36 PM PDT 24
Peak memory 207096 kb
Host smart-b18e7057-f1de-4b29-b9ef-6a09f9f5521d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15438
66444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1543866444
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.571514651
Short name T1238
Test name
Test status
Simulation time 244804161 ps
CPU time 1.05 seconds
Started Jul 29 06:15:44 PM PDT 24
Finished Jul 29 06:15:46 PM PDT 24
Peak memory 207036 kb
Host smart-314f22a0-fdb4-433f-9c7c-3984731596e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57151
4651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.571514651
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1368137747
Short name T416
Test name
Test status
Simulation time 4731320279 ps
CPU time 37.08 seconds
Started Jul 29 06:15:41 PM PDT 24
Finished Jul 29 06:16:18 PM PDT 24
Peak memory 216980 kb
Host smart-e80a2311-eb9c-45f6-8a46-2c12c3354348
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1368137747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1368137747
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1280135580
Short name T2558
Test name
Test status
Simulation time 228704084 ps
CPU time 0.91 seconds
Started Jul 29 06:15:40 PM PDT 24
Finished Jul 29 06:15:41 PM PDT 24
Peak memory 207072 kb
Host smart-fa59e012-c3c4-4454-a1ce-088b0a709904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12801
35580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1280135580
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3335811396
Short name T73
Test name
Test status
Simulation time 189630292 ps
CPU time 0.86 seconds
Started Jul 29 06:15:39 PM PDT 24
Finished Jul 29 06:15:40 PM PDT 24
Peak memory 207104 kb
Host smart-2985549c-12ac-4a95-a14d-c89ff28718cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33358
11396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3335811396
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1374698648
Short name T2684
Test name
Test status
Simulation time 329764109 ps
CPU time 1.17 seconds
Started Jul 29 06:15:38 PM PDT 24
Finished Jul 29 06:15:39 PM PDT 24
Peak memory 207072 kb
Host smart-75d647b4-8502-479f-8b7d-fa60005da279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13746
98648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1374698648
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.1079050551
Short name T2479
Test name
Test status
Simulation time 4425524976 ps
CPU time 45.43 seconds
Started Jul 29 06:15:42 PM PDT 24
Finished Jul 29 06:16:28 PM PDT 24
Peak memory 207396 kb
Host smart-f5302a61-584a-4c5d-8279-2c2dae399544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10790
50551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1079050551
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.146616945
Short name T663
Test name
Test status
Simulation time 1540818210 ps
CPU time 13.75 seconds
Started Jul 29 06:15:31 PM PDT 24
Finished Jul 29 06:15:45 PM PDT 24
Peak memory 207336 kb
Host smart-719cce1d-bbba-4626-9400-40ad6926ae5f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146616945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_host
_handshake.146616945
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2997483791
Short name T496
Test name
Test status
Simulation time 43075468 ps
CPU time 0.7 seconds
Started Jul 29 06:15:48 PM PDT 24
Finished Jul 29 06:15:49 PM PDT 24
Peak memory 207088 kb
Host smart-755c493a-cc1f-4cca-a972-1737a04407a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2997483791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2997483791
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.802064702
Short name T661
Test name
Test status
Simulation time 4434917028 ps
CPU time 6.68 seconds
Started Jul 29 06:15:38 PM PDT 24
Finished Jul 29 06:15:45 PM PDT 24
Peak memory 207336 kb
Host smart-0411ba0e-a521-4466-a532-2f05db3cc095
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802064702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_ao
n_wake_disconnect.802064702
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1373421037
Short name T785
Test name
Test status
Simulation time 13393598587 ps
CPU time 18.48 seconds
Started Jul 29 06:15:39 PM PDT 24
Finished Jul 29 06:15:57 PM PDT 24
Peak memory 207412 kb
Host smart-01297650-0248-4b32-ae47-fe75937180a7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373421037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1373421037
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.32797649
Short name T1429
Test name
Test status
Simulation time 23324140978 ps
CPU time 30.59 seconds
Started Jul 29 06:15:41 PM PDT 24
Finished Jul 29 06:16:11 PM PDT 24
Peak memory 207356 kb
Host smart-80f0b204-6e1f-4195-8b8e-ee28256f64ab
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32797649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon
_wake_resume.32797649
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3593041982
Short name T2279
Test name
Test status
Simulation time 160104448 ps
CPU time 0.87 seconds
Started Jul 29 06:15:39 PM PDT 24
Finished Jul 29 06:15:40 PM PDT 24
Peak memory 207068 kb
Host smart-21136008-b4ea-4228-8a53-f53d631f1094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35930
41982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3593041982
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.3353976713
Short name T1501
Test name
Test status
Simulation time 146812069 ps
CPU time 0.88 seconds
Started Jul 29 06:15:41 PM PDT 24
Finished Jul 29 06:15:42 PM PDT 24
Peak memory 207220 kb
Host smart-1d9e49af-0f28-4658-8229-54c4580a926f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33539
76713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.3353976713
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.178758663
Short name T1251
Test name
Test status
Simulation time 263702689 ps
CPU time 1.14 seconds
Started Jul 29 06:15:44 PM PDT 24
Finished Jul 29 06:15:45 PM PDT 24
Peak memory 207068 kb
Host smart-e8c3c41d-7b2e-4cab-99f4-76c56e498a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17875
8663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.178758663
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1212113548
Short name T2655
Test name
Test status
Simulation time 1068233788 ps
CPU time 2.7 seconds
Started Jul 29 06:15:44 PM PDT 24
Finished Jul 29 06:15:47 PM PDT 24
Peak memory 207248 kb
Host smart-7396b79e-bb64-40e8-a998-a8d2610c2023
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1212113548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1212113548
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.310086867
Short name T2256
Test name
Test status
Simulation time 19155082885 ps
CPU time 41.07 seconds
Started Jul 29 06:15:38 PM PDT 24
Finished Jul 29 06:16:20 PM PDT 24
Peak memory 207420 kb
Host smart-99f8b65d-12d1-4dcc-93a7-989010aa7cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31008
6867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.310086867
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.3169060191
Short name T2275
Test name
Test status
Simulation time 845300692 ps
CPU time 18.46 seconds
Started Jul 29 06:15:49 PM PDT 24
Finished Jul 29 06:16:08 PM PDT 24
Peak memory 207220 kb
Host smart-090e7bd9-f074-4aa4-ad5c-b0f5f98c1eee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169060191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.3169060191
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.2575043645
Short name T2225
Test name
Test status
Simulation time 458316202 ps
CPU time 1.6 seconds
Started Jul 29 06:15:48 PM PDT 24
Finished Jul 29 06:15:50 PM PDT 24
Peak memory 207016 kb
Host smart-54884594-eb1d-4efb-9c5f-2c108f6f9bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25750
43645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.2575043645
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.933904974
Short name T2796
Test name
Test status
Simulation time 141934045 ps
CPU time 0.86 seconds
Started Jul 29 06:15:44 PM PDT 24
Finished Jul 29 06:15:45 PM PDT 24
Peak memory 207064 kb
Host smart-6495183a-0f19-4a60-b157-cf28e8827ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93390
4974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.933904974
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.444270429
Short name T1744
Test name
Test status
Simulation time 75274137 ps
CPU time 0.75 seconds
Started Jul 29 06:15:44 PM PDT 24
Finished Jul 29 06:15:45 PM PDT 24
Peak memory 206964 kb
Host smart-6783736f-59bd-4e4f-aa38-85e4f5c96724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44427
0429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.444270429
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1205393819
Short name T1303
Test name
Test status
Simulation time 963548122 ps
CPU time 2.84 seconds
Started Jul 29 06:15:45 PM PDT 24
Finished Jul 29 06:15:48 PM PDT 24
Peak memory 207284 kb
Host smart-eb9f01b5-3ac0-489b-8256-19dec55f2577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12053
93819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1205393819
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1646815325
Short name T2850
Test name
Test status
Simulation time 377141923 ps
CPU time 2.41 seconds
Started Jul 29 06:15:44 PM PDT 24
Finished Jul 29 06:15:46 PM PDT 24
Peak memory 207280 kb
Host smart-00f75d16-eedc-494b-a798-1a0846ab80ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16468
15325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1646815325
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2010474196
Short name T2027
Test name
Test status
Simulation time 226491438 ps
CPU time 1.22 seconds
Started Jul 29 06:15:47 PM PDT 24
Finished Jul 29 06:15:49 PM PDT 24
Peak memory 215524 kb
Host smart-66c3cca4-8df4-4237-b29c-0c4e25107a22
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2010474196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2010474196
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.4226798399
Short name T1705
Test name
Test status
Simulation time 142162417 ps
CPU time 0.81 seconds
Started Jul 29 06:15:43 PM PDT 24
Finished Jul 29 06:15:44 PM PDT 24
Peak memory 207072 kb
Host smart-b2d64812-9288-4400-b98a-49888018fef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42267
98399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.4226798399
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2246755729
Short name T699
Test name
Test status
Simulation time 224299290 ps
CPU time 0.98 seconds
Started Jul 29 06:15:46 PM PDT 24
Finished Jul 29 06:15:47 PM PDT 24
Peak memory 207100 kb
Host smart-a3349dfa-02c4-4def-a304-9b7aab6df98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22467
55729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2246755729
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.3958232684
Short name T1662
Test name
Test status
Simulation time 6095902988 ps
CPU time 183.53 seconds
Started Jul 29 06:15:48 PM PDT 24
Finished Jul 29 06:18:52 PM PDT 24
Peak memory 215612 kb
Host smart-8976b477-b601-484c-87ac-d50c1008ddad
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3958232684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.3958232684
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.3142377282
Short name T1414
Test name
Test status
Simulation time 13996537436 ps
CPU time 91.58 seconds
Started Jul 29 06:15:48 PM PDT 24
Finished Jul 29 06:17:20 PM PDT 24
Peak memory 207380 kb
Host smart-058fe783-b02d-4ea5-823e-00dd4c11b610
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3142377282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.3142377282
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3344893170
Short name T813
Test name
Test status
Simulation time 159292575 ps
CPU time 0.82 seconds
Started Jul 29 06:15:45 PM PDT 24
Finished Jul 29 06:15:46 PM PDT 24
Peak memory 207060 kb
Host smart-897cb2e4-e70d-4e71-9c1f-c6f8452f40cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33448
93170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3344893170
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.1756317361
Short name T2016
Test name
Test status
Simulation time 23331642892 ps
CPU time 30.08 seconds
Started Jul 29 06:15:44 PM PDT 24
Finished Jul 29 06:16:14 PM PDT 24
Peak memory 207376 kb
Host smart-a1ce2030-5875-4624-a2b0-75dc19759952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17563
17361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.1756317361
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.823289665
Short name T2781
Test name
Test status
Simulation time 3313137206 ps
CPU time 4.73 seconds
Started Jul 29 06:15:48 PM PDT 24
Finished Jul 29 06:15:53 PM PDT 24
Peak memory 207348 kb
Host smart-5108fb95-0bcc-4a8c-97d5-02e8f89305c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82328
9665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.823289665
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.231405912
Short name T153
Test name
Test status
Simulation time 7460714336 ps
CPU time 58.16 seconds
Started Jul 29 06:15:50 PM PDT 24
Finished Jul 29 06:16:48 PM PDT 24
Peak memory 223704 kb
Host smart-b79f4f27-b896-4b43-9909-6db0186fa8ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23140
5912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.231405912
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3959599499
Short name T509
Test name
Test status
Simulation time 5178751705 ps
CPU time 146.7 seconds
Started Jul 29 06:15:45 PM PDT 24
Finished Jul 29 06:18:12 PM PDT 24
Peak memory 215620 kb
Host smart-a885d1bf-f00e-4410-b632-68ecacd46753
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3959599499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3959599499
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1640566597
Short name T677
Test name
Test status
Simulation time 243812067 ps
CPU time 1.04 seconds
Started Jul 29 06:15:47 PM PDT 24
Finished Jul 29 06:15:48 PM PDT 24
Peak memory 207108 kb
Host smart-9fae00b0-6a84-4982-8c33-da119a3944a7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1640566597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1640566597
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1204125041
Short name T1264
Test name
Test status
Simulation time 194086358 ps
CPU time 0.93 seconds
Started Jul 29 06:15:48 PM PDT 24
Finished Jul 29 06:15:49 PM PDT 24
Peak memory 207076 kb
Host smart-b9c1036b-e994-440a-a6b8-43a732f65424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12041
25041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1204125041
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.480436978
Short name T2317
Test name
Test status
Simulation time 5474455054 ps
CPU time 170.44 seconds
Started Jul 29 06:15:48 PM PDT 24
Finished Jul 29 06:18:39 PM PDT 24
Peak memory 215568 kb
Host smart-81250fce-3c1f-461c-8c3d-8acc5750a4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48043
6978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.480436978
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.3910809042
Short name T2188
Test name
Test status
Simulation time 4426583088 ps
CPU time 43.75 seconds
Started Jul 29 06:15:46 PM PDT 24
Finished Jul 29 06:16:30 PM PDT 24
Peak memory 207416 kb
Host smart-bd7603b0-c017-4e9f-a776-d7c888f61b3b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3910809042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.3910809042
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.46640479
Short name T380
Test name
Test status
Simulation time 156377524 ps
CPU time 0.96 seconds
Started Jul 29 06:15:48 PM PDT 24
Finished Jul 29 06:15:49 PM PDT 24
Peak memory 207104 kb
Host smart-9cccd9af-b3e8-401b-b6e8-1084611cc602
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=46640479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.46640479
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3322387155
Short name T457
Test name
Test status
Simulation time 216983422 ps
CPU time 0.91 seconds
Started Jul 29 06:15:48 PM PDT 24
Finished Jul 29 06:15:49 PM PDT 24
Peak memory 207068 kb
Host smart-4073f566-8faf-4e8f-af22-279bf5973325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33223
87155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3322387155
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1461884850
Short name T119
Test name
Test status
Simulation time 225594313 ps
CPU time 1.17 seconds
Started Jul 29 06:15:46 PM PDT 24
Finished Jul 29 06:15:47 PM PDT 24
Peak memory 207064 kb
Host smart-0443cf60-99ff-41b0-a713-88c804c651ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14618
84850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1461884850
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3891021324
Short name T1369
Test name
Test status
Simulation time 181164064 ps
CPU time 0.94 seconds
Started Jul 29 06:15:45 PM PDT 24
Finished Jul 29 06:15:46 PM PDT 24
Peak memory 207120 kb
Host smart-19edbfa6-7d62-4fe2-b282-2def0b0d06bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38910
21324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3891021324
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1373435851
Short name T2213
Test name
Test status
Simulation time 199964966 ps
CPU time 0.93 seconds
Started Jul 29 06:15:49 PM PDT 24
Finished Jul 29 06:15:50 PM PDT 24
Peak memory 207032 kb
Host smart-866fe7cf-7e09-4b50-8df4-49a201f62c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13734
35851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1373435851
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2764422942
Short name T171
Test name
Test status
Simulation time 161017692 ps
CPU time 0.84 seconds
Started Jul 29 06:15:49 PM PDT 24
Finished Jul 29 06:15:50 PM PDT 24
Peak memory 206664 kb
Host smart-97ed74df-f7b8-4b02-bf9f-7b989f1bbe31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27644
22942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2764422942
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.672143808
Short name T2222
Test name
Test status
Simulation time 252087294 ps
CPU time 1.15 seconds
Started Jul 29 06:15:47 PM PDT 24
Finished Jul 29 06:15:48 PM PDT 24
Peak memory 207080 kb
Host smart-9d542a28-b09c-4c65-81b5-28f5e76faca6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=672143808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.672143808
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2634845962
Short name T535
Test name
Test status
Simulation time 157187356 ps
CPU time 0.88 seconds
Started Jul 29 06:15:46 PM PDT 24
Finished Jul 29 06:15:47 PM PDT 24
Peak memory 207032 kb
Host smart-01ef5772-40a9-48d9-a33c-7e90c6d77d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26348
45962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2634845962
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1934415852
Short name T937
Test name
Test status
Simulation time 66523742 ps
CPU time 0.71 seconds
Started Jul 29 06:15:44 PM PDT 24
Finished Jul 29 06:15:45 PM PDT 24
Peak memory 207216 kb
Host smart-941a9db0-ecdd-4258-b6e3-a7f3f9933cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19344
15852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1934415852
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.143975454
Short name T2249
Test name
Test status
Simulation time 14175541859 ps
CPU time 33.99 seconds
Started Jul 29 06:15:46 PM PDT 24
Finished Jul 29 06:16:20 PM PDT 24
Peak memory 215648 kb
Host smart-62808874-c128-4053-9866-7d69d556676b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14397
5454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.143975454
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1682124789
Short name T2736
Test name
Test status
Simulation time 220426508 ps
CPU time 0.9 seconds
Started Jul 29 06:15:48 PM PDT 24
Finished Jul 29 06:15:49 PM PDT 24
Peak memory 207048 kb
Host smart-c6348fc7-7de5-4008-99ee-fef648f087df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16821
24789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1682124789
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3425929052
Short name T1955
Test name
Test status
Simulation time 206718750 ps
CPU time 0.97 seconds
Started Jul 29 06:15:45 PM PDT 24
Finished Jul 29 06:15:46 PM PDT 24
Peak memory 207096 kb
Host smart-be7ef593-de57-4bea-b9da-90777e73e8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34259
29052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3425929052
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.54061596
Short name T2313
Test name
Test status
Simulation time 201512033 ps
CPU time 0.96 seconds
Started Jul 29 06:15:45 PM PDT 24
Finished Jul 29 06:15:46 PM PDT 24
Peak memory 207120 kb
Host smart-b789a35e-046d-4c6e-a832-bbc5b689fad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54061
596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.54061596
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.3418264578
Short name T1197
Test name
Test status
Simulation time 191361652 ps
CPU time 0.99 seconds
Started Jul 29 06:15:49 PM PDT 24
Finished Jul 29 06:15:51 PM PDT 24
Peak memory 206980 kb
Host smart-c409fbab-e253-4748-9376-5382287f4818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34182
64578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3418264578
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3440595630
Short name T777
Test name
Test status
Simulation time 142323561 ps
CPU time 0.83 seconds
Started Jul 29 06:15:49 PM PDT 24
Finished Jul 29 06:15:50 PM PDT 24
Peak memory 207052 kb
Host smart-7cb58bcb-8139-471e-b461-e8764598723d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34405
95630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3440595630
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1488483687
Short name T1004
Test name
Test status
Simulation time 147705797 ps
CPU time 0.83 seconds
Started Jul 29 06:15:45 PM PDT 24
Finished Jul 29 06:15:46 PM PDT 24
Peak memory 207052 kb
Host smart-4ec21971-4360-403e-a4c3-4bc11e069abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14884
83687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1488483687
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.250754404
Short name T977
Test name
Test status
Simulation time 150923647 ps
CPU time 0.91 seconds
Started Jul 29 06:15:46 PM PDT 24
Finished Jul 29 06:15:47 PM PDT 24
Peak memory 207064 kb
Host smart-1ce7d779-e07b-4b87-80f2-479e5a2db4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25075
4404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.250754404
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2073094635
Short name T935
Test name
Test status
Simulation time 209912028 ps
CPU time 1.13 seconds
Started Jul 29 06:15:49 PM PDT 24
Finished Jul 29 06:15:51 PM PDT 24
Peak memory 207032 kb
Host smart-1abe3d29-44fd-4989-96a8-b200061a2474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20730
94635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2073094635
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.4021125439
Short name T938
Test name
Test status
Simulation time 4204389993 ps
CPU time 36.26 seconds
Started Jul 29 06:15:44 PM PDT 24
Finished Jul 29 06:16:20 PM PDT 24
Peak memory 216992 kb
Host smart-daa02b93-4986-4777-9892-7b8957a66065
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4021125439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.4021125439
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2321596752
Short name T564
Test name
Test status
Simulation time 194859337 ps
CPU time 0.88 seconds
Started Jul 29 06:15:47 PM PDT 24
Finished Jul 29 06:15:48 PM PDT 24
Peak memory 207084 kb
Host smart-428cdf95-9e4b-48b2-9000-61e2ba3e89f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23215
96752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2321596752
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.660301367
Short name T1170
Test name
Test status
Simulation time 188634027 ps
CPU time 0.95 seconds
Started Jul 29 06:15:46 PM PDT 24
Finished Jul 29 06:15:47 PM PDT 24
Peak memory 207100 kb
Host smart-0617d520-c4c6-4876-bbf6-f15ebb3270ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66030
1367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.660301367
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.1993532832
Short name T1562
Test name
Test status
Simulation time 1080131326 ps
CPU time 2.71 seconds
Started Jul 29 06:15:49 PM PDT 24
Finished Jul 29 06:15:52 PM PDT 24
Peak memory 207236 kb
Host smart-f118ca84-73b2-4004-a612-1a4043b66318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19935
32832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.1993532832
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.657598733
Short name T1668
Test name
Test status
Simulation time 5023396127 ps
CPU time 152.56 seconds
Started Jul 29 06:15:48 PM PDT 24
Finished Jul 29 06:18:21 PM PDT 24
Peak memory 215548 kb
Host smart-437d06e5-3b09-4287-ad44-86b0f06578c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65759
8733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.657598733
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.1333294825
Short name T2636
Test name
Test status
Simulation time 839832747 ps
CPU time 19.36 seconds
Started Jul 29 06:15:46 PM PDT 24
Finished Jul 29 06:16:06 PM PDT 24
Peak memory 207312 kb
Host smart-e5ea8094-1eb0-4603-9d55-22596f243b70
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333294825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.1333294825
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.1829133888
Short name T1207
Test name
Test status
Simulation time 44886888 ps
CPU time 0.69 seconds
Started Jul 29 06:15:54 PM PDT 24
Finished Jul 29 06:15:55 PM PDT 24
Peak memory 207148 kb
Host smart-fe0b6947-1fcc-4415-a897-c2ac07ca3785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1829133888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.1829133888
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1356942290
Short name T2045
Test name
Test status
Simulation time 4334184481 ps
CPU time 6.14 seconds
Started Jul 29 06:15:49 PM PDT 24
Finished Jul 29 06:15:55 PM PDT 24
Peak memory 207392 kb
Host smart-6d46b63e-c796-42a3-967d-38a54c953802
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356942290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_disconnect.1356942290
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2491216996
Short name T2251
Test name
Test status
Simulation time 13326229518 ps
CPU time 15.89 seconds
Started Jul 29 06:15:50 PM PDT 24
Finished Jul 29 06:16:06 PM PDT 24
Peak memory 207440 kb
Host smart-49ae15cc-eb91-4ac3-89f6-45cc79a87ad2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491216996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2491216996
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1806081090
Short name T1208
Test name
Test status
Simulation time 23465785677 ps
CPU time 29.25 seconds
Started Jul 29 06:15:54 PM PDT 24
Finished Jul 29 06:16:23 PM PDT 24
Peak memory 207372 kb
Host smart-88a402c0-6d7f-48ef-afd2-9529cd6ffc10
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806081090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.1806081090
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2499853289
Short name T2555
Test name
Test status
Simulation time 210995109 ps
CPU time 1.02 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:15:56 PM PDT 24
Peak memory 207108 kb
Host smart-93a928ae-bb45-4be4-a904-47d04320534b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24998
53289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2499853289
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3671178384
Short name T1484
Test name
Test status
Simulation time 146680920 ps
CPU time 0.86 seconds
Started Jul 29 06:15:53 PM PDT 24
Finished Jul 29 06:15:54 PM PDT 24
Peak memory 207104 kb
Host smart-4ef26fca-f44c-47a4-ad99-1fb890d78682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36711
78384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3671178384
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.4012361609
Short name T2357
Test name
Test status
Simulation time 209226022 ps
CPU time 1 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:15:56 PM PDT 24
Peak memory 207092 kb
Host smart-c0ae2bda-830b-4077-935e-f9b3bd25d2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40123
61609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.4012361609
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.952103816
Short name T1375
Test name
Test status
Simulation time 955588400 ps
CPU time 2.65 seconds
Started Jul 29 06:15:52 PM PDT 24
Finished Jul 29 06:15:55 PM PDT 24
Peak memory 207292 kb
Host smart-e8ecb027-47bf-49bd-96a2-a5411a0c9387
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=952103816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.952103816
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.241589696
Short name T1717
Test name
Test status
Simulation time 9142561539 ps
CPU time 20.18 seconds
Started Jul 29 06:15:53 PM PDT 24
Finished Jul 29 06:16:13 PM PDT 24
Peak memory 207576 kb
Host smart-285ba770-fe0a-48b9-88c2-e46ed394e79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24158
9696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.241589696
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.1404711920
Short name T369
Test name
Test status
Simulation time 1304486574 ps
CPU time 30.55 seconds
Started Jul 29 06:15:53 PM PDT 24
Finished Jul 29 06:16:23 PM PDT 24
Peak memory 207272 kb
Host smart-5e85eaa6-55e9-430c-9737-4777410a6aae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404711920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.1404711920
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1515912279
Short name T1527
Test name
Test status
Simulation time 374286518 ps
CPU time 1.39 seconds
Started Jul 29 06:15:53 PM PDT 24
Finished Jul 29 06:15:54 PM PDT 24
Peak memory 207044 kb
Host smart-ffe8a079-5045-48fb-82f0-ed6bcd8d5864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15159
12279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1515912279
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.431053193
Short name T50
Test name
Test status
Simulation time 145070078 ps
CPU time 0.86 seconds
Started Jul 29 06:15:49 PM PDT 24
Finished Jul 29 06:15:51 PM PDT 24
Peak memory 207064 kb
Host smart-27c42d93-70ad-47e9-ac5d-a255573ea2a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43105
3193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.431053193
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1417793820
Short name T1425
Test name
Test status
Simulation time 49926065 ps
CPU time 0.72 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:15:56 PM PDT 24
Peak memory 207072 kb
Host smart-a070461b-bd43-4c13-83a3-62887cb982e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14177
93820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1417793820
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.1968317228
Short name T2114
Test name
Test status
Simulation time 848939017 ps
CPU time 2.24 seconds
Started Jul 29 06:15:50 PM PDT 24
Finished Jul 29 06:15:53 PM PDT 24
Peak memory 207328 kb
Host smart-c646a2aa-a436-4e70-8176-1fe427fbacb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19683
17228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.1968317228
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1918132442
Short name T1960
Test name
Test status
Simulation time 174872816 ps
CPU time 2.16 seconds
Started Jul 29 06:15:52 PM PDT 24
Finished Jul 29 06:15:54 PM PDT 24
Peak memory 207264 kb
Host smart-51cbc186-e461-4227-888f-13efbe29ae9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19181
32442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1918132442
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3973956546
Short name T1313
Test name
Test status
Simulation time 200268025 ps
CPU time 0.93 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:15:56 PM PDT 24
Peak memory 207112 kb
Host smart-10694614-acb5-4b7d-a68d-30d387e157f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3973956546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3973956546
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3383003083
Short name T2282
Test name
Test status
Simulation time 142434856 ps
CPU time 0.81 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:15:56 PM PDT 24
Peak memory 207076 kb
Host smart-d1ca1868-0a78-4454-89a9-1b300a216556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33830
03083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3383003083
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.4171630884
Short name T2381
Test name
Test status
Simulation time 229753886 ps
CPU time 1 seconds
Started Jul 29 06:15:52 PM PDT 24
Finished Jul 29 06:15:53 PM PDT 24
Peak memory 207116 kb
Host smart-ee0c9275-bcab-4df5-9a00-dd62f1e058b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41716
30884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.4171630884
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.964234668
Short name T2217
Test name
Test status
Simulation time 10061396827 ps
CPU time 300.57 seconds
Started Jul 29 06:15:51 PM PDT 24
Finished Jul 29 06:20:51 PM PDT 24
Peak memory 215516 kb
Host smart-b10fc13a-cb98-4414-bc42-0017da72b0bc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=964234668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.964234668
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.1943614354
Short name T334
Test name
Test status
Simulation time 5883997234 ps
CPU time 77.43 seconds
Started Jul 29 06:15:53 PM PDT 24
Finished Jul 29 06:17:10 PM PDT 24
Peak memory 207372 kb
Host smart-236d0d60-2f21-4b82-8991-30ddfe119f39
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1943614354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.1943614354
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1593357541
Short name T2131
Test name
Test status
Simulation time 281594618 ps
CPU time 1.06 seconds
Started Jul 29 06:15:49 PM PDT 24
Finished Jul 29 06:15:50 PM PDT 24
Peak memory 207132 kb
Host smart-d1d8f03e-a016-4a06-9993-f87f9af90fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15933
57541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1593357541
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3921834060
Short name T587
Test name
Test status
Simulation time 23322032820 ps
CPU time 31.47 seconds
Started Jul 29 06:15:53 PM PDT 24
Finished Jul 29 06:16:25 PM PDT 24
Peak memory 207424 kb
Host smart-897c0e20-95c8-4987-b126-d696f8b7f4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39218
34060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3921834060
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.3792514914
Short name T1216
Test name
Test status
Simulation time 3413438121 ps
CPU time 6.17 seconds
Started Jul 29 06:15:52 PM PDT 24
Finished Jul 29 06:15:58 PM PDT 24
Peak memory 207456 kb
Host smart-7e3b549d-06f4-4941-9d1b-e759b1f7a79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37925
14914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.3792514914
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.3960308182
Short name T1212
Test name
Test status
Simulation time 8199665438 ps
CPU time 68.98 seconds
Started Jul 29 06:15:49 PM PDT 24
Finished Jul 29 06:16:58 PM PDT 24
Peak memory 217476 kb
Host smart-fa6b8707-06b4-4781-b856-c98fa671e61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39603
08182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.3960308182
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1419767151
Short name T514
Test name
Test status
Simulation time 5793070965 ps
CPU time 61.11 seconds
Started Jul 29 06:15:52 PM PDT 24
Finished Jul 29 06:16:53 PM PDT 24
Peak memory 207464 kb
Host smart-7c7226a2-4d59-4c09-95ce-efcbe3ea2b9f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1419767151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1419767151
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.113099901
Short name T2068
Test name
Test status
Simulation time 235323220 ps
CPU time 0.96 seconds
Started Jul 29 06:15:49 PM PDT 24
Finished Jul 29 06:15:50 PM PDT 24
Peak memory 207128 kb
Host smart-e8369d98-1082-4987-b7ff-7f27b726345f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=113099901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.113099901
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.133144488
Short name T874
Test name
Test status
Simulation time 188308091 ps
CPU time 0.89 seconds
Started Jul 29 06:15:54 PM PDT 24
Finished Jul 29 06:15:54 PM PDT 24
Peak memory 207068 kb
Host smart-ebd035f0-c865-4db6-b91d-aabeb6049656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13314
4488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.133144488
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.4093142815
Short name T1162
Test name
Test status
Simulation time 5338489114 ps
CPU time 159.31 seconds
Started Jul 29 06:15:53 PM PDT 24
Finished Jul 29 06:18:32 PM PDT 24
Peak memory 215572 kb
Host smart-89927693-2876-43a7-b6e0-1818dfaa2eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40931
42815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.4093142815
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.3611226485
Short name T853
Test name
Test status
Simulation time 5048797697 ps
CPU time 151.34 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:18:26 PM PDT 24
Peak memory 215576 kb
Host smart-3bd0ce44-a50c-45f0-b475-f495dc076dc4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3611226485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.3611226485
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.231510564
Short name T2365
Test name
Test status
Simulation time 174057538 ps
CPU time 0.9 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:15:56 PM PDT 24
Peak memory 207104 kb
Host smart-fe2ad80d-8ec9-4101-bfe3-0ba82c908f7e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=231510564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.231510564
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3980073975
Short name T2554
Test name
Test status
Simulation time 137295705 ps
CPU time 0.84 seconds
Started Jul 29 06:15:57 PM PDT 24
Finished Jul 29 06:15:58 PM PDT 24
Peak memory 207096 kb
Host smart-cc0ca68c-7d8f-4042-836d-4a93fa6f82db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39800
73975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3980073975
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1620482710
Short name T118
Test name
Test status
Simulation time 184949940 ps
CPU time 0.9 seconds
Started Jul 29 06:16:01 PM PDT 24
Finished Jul 29 06:16:02 PM PDT 24
Peak memory 207124 kb
Host smart-372b1135-5f81-48a1-98aa-9fc2ebe09fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16204
82710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1620482710
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.888100104
Short name T2843
Test name
Test status
Simulation time 157266216 ps
CPU time 0.94 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:00 PM PDT 24
Peak memory 207132 kb
Host smart-9bebb58c-89c8-45ca-ad9f-3270cf3288fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88810
0104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.888100104
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2998095800
Short name T2409
Test name
Test status
Simulation time 178965185 ps
CPU time 0.88 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:15:56 PM PDT 24
Peak memory 207060 kb
Host smart-c0e43d63-5073-4d70-a1f6-abbf63cc148b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29980
95800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2998095800
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3043012444
Short name T878
Test name
Test status
Simulation time 166308137 ps
CPU time 0.85 seconds
Started Jul 29 06:15:53 PM PDT 24
Finished Jul 29 06:15:54 PM PDT 24
Peak memory 207188 kb
Host smart-3f64a333-3b95-465f-824a-8196d8b1d7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30430
12444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3043012444
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2872728319
Short name T2847
Test name
Test status
Simulation time 171014460 ps
CPU time 0.84 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:15:56 PM PDT 24
Peak memory 207104 kb
Host smart-3bb191ab-1ceb-4ecd-abfa-880a5c2bd53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28727
28319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2872728319
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.2535929597
Short name T513
Test name
Test status
Simulation time 231381932 ps
CPU time 1.15 seconds
Started Jul 29 06:15:56 PM PDT 24
Finished Jul 29 06:15:57 PM PDT 24
Peak memory 207100 kb
Host smart-389f6698-2403-4066-9e13-4bf1d5dd7e13
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2535929597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.2535929597
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2380660825
Short name T1672
Test name
Test status
Simulation time 162205241 ps
CPU time 0.88 seconds
Started Jul 29 06:15:54 PM PDT 24
Finished Jul 29 06:15:55 PM PDT 24
Peak memory 207064 kb
Host smart-d9ca6d48-5370-493c-b54b-630fd9638fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23806
60825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2380660825
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1587609431
Short name T923
Test name
Test status
Simulation time 52394657 ps
CPU time 0.72 seconds
Started Jul 29 06:15:57 PM PDT 24
Finished Jul 29 06:15:57 PM PDT 24
Peak memory 207176 kb
Host smart-7dff9f8a-6163-4869-868c-c9f2ce61be0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15876
09431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1587609431
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3256768404
Short name T1994
Test name
Test status
Simulation time 11877281850 ps
CPU time 31.73 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:16:26 PM PDT 24
Peak memory 215668 kb
Host smart-755280dd-7467-4bd1-8e0e-54d2271710a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32567
68404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3256768404
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3338837323
Short name T2309
Test name
Test status
Simulation time 186140126 ps
CPU time 0.96 seconds
Started Jul 29 06:15:58 PM PDT 24
Finished Jul 29 06:15:59 PM PDT 24
Peak memory 207072 kb
Host smart-626cf5e5-33da-480d-a254-5a1fd1d5bd74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33388
37323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3338837323
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.963399571
Short name T1815
Test name
Test status
Simulation time 172276722 ps
CPU time 0.95 seconds
Started Jul 29 06:15:57 PM PDT 24
Finished Jul 29 06:15:58 PM PDT 24
Peak memory 207104 kb
Host smart-38cef3c1-4a9e-4122-b928-f05642c1c883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96339
9571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.963399571
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1333743175
Short name T313
Test name
Test status
Simulation time 170948541 ps
CPU time 0.86 seconds
Started Jul 29 06:15:54 PM PDT 24
Finished Jul 29 06:15:55 PM PDT 24
Peak memory 207076 kb
Host smart-fcbd5a3b-7072-45ea-98be-475820586850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13337
43175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1333743175
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.2577312360
Short name T586
Test name
Test status
Simulation time 180077597 ps
CPU time 0.97 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:00 PM PDT 24
Peak memory 207108 kb
Host smart-7966167a-e8ed-480f-b829-cbfb8ec4b87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25773
12360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.2577312360
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.560150552
Short name T1578
Test name
Test status
Simulation time 224862296 ps
CPU time 0.95 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:00 PM PDT 24
Peak memory 207100 kb
Host smart-fab484dd-9a22-4fdc-8f8c-387fca707951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56015
0552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.560150552
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3873582273
Short name T865
Test name
Test status
Simulation time 162996121 ps
CPU time 0.87 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:00 PM PDT 24
Peak memory 207080 kb
Host smart-abd8ef5b-3db8-4edb-9825-5e5dde10eb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38735
82273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3873582273
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2697573240
Short name T1273
Test name
Test status
Simulation time 151018602 ps
CPU time 0.86 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:15:56 PM PDT 24
Peak memory 207004 kb
Host smart-288e55da-426e-4691-bd4d-abfeaea3e911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26975
73240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2697573240
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.274738649
Short name T2084
Test name
Test status
Simulation time 247512350 ps
CPU time 1.21 seconds
Started Jul 29 06:15:56 PM PDT 24
Finished Jul 29 06:15:57 PM PDT 24
Peak memory 207124 kb
Host smart-a5e90303-c158-4895-9c7f-6de6f9da2025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27473
8649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.274738649
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2555746633
Short name T1929
Test name
Test status
Simulation time 5879745029 ps
CPU time 177.85 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:18:53 PM PDT 24
Peak memory 215632 kb
Host smart-939f8808-40a8-4cc3-815f-1891d69b3278
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2555746633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2555746633
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1958229643
Short name T546
Test name
Test status
Simulation time 212602443 ps
CPU time 1.05 seconds
Started Jul 29 06:15:58 PM PDT 24
Finished Jul 29 06:16:00 PM PDT 24
Peak memory 207092 kb
Host smart-ac4e7476-2a3f-46b3-be85-432971a95f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19582
29643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1958229643
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.434860132
Short name T1118
Test name
Test status
Simulation time 161360339 ps
CPU time 0.9 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:00 PM PDT 24
Peak memory 207064 kb
Host smart-86ac7a0f-36b1-4502-b64b-7ff56153e886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43486
0132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.434860132
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.3356457310
Short name T1873
Test name
Test status
Simulation time 474470881 ps
CPU time 1.42 seconds
Started Jul 29 06:15:56 PM PDT 24
Finished Jul 29 06:15:58 PM PDT 24
Peak memory 207048 kb
Host smart-8068c19c-ee20-4b8f-9e19-aab513dc9773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33564
57310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.3356457310
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.958395628
Short name T355
Test name
Test status
Simulation time 4287057806 ps
CPU time 33.04 seconds
Started Jul 29 06:15:58 PM PDT 24
Finished Jul 29 06:16:31 PM PDT 24
Peak memory 207292 kb
Host smart-c1d20804-d131-48f3-8205-63761b3c61d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95839
5628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.958395628
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.3716254984
Short name T557
Test name
Test status
Simulation time 3385250552 ps
CPU time 28.61 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:28 PM PDT 24
Peak memory 207352 kb
Host smart-c59f5433-d986-47d3-82b4-6658521e1430
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716254984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.3716254984
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3291198620
Short name T796
Test name
Test status
Simulation time 55253562 ps
CPU time 0.7 seconds
Started Jul 29 06:16:02 PM PDT 24
Finished Jul 29 06:16:03 PM PDT 24
Peak memory 207084 kb
Host smart-fe82e7b1-a865-4f8a-9782-553d81243d56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3291198620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3291198620
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1582605971
Short name T2640
Test name
Test status
Simulation time 3414932612 ps
CPU time 5.68 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:05 PM PDT 24
Peak memory 207304 kb
Host smart-5e7a1e94-ed18-48a4-ab39-143fe2b28c5c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582605971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.1582605971
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.69222021
Short name T2407
Test name
Test status
Simulation time 13396222599 ps
CPU time 17.08 seconds
Started Jul 29 06:15:57 PM PDT 24
Finished Jul 29 06:16:14 PM PDT 24
Peak memory 207404 kb
Host smart-677ce529-6aba-4601-b542-0c07567d29da
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=69222021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.69222021
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.2129776774
Short name T2470
Test name
Test status
Simulation time 23408545586 ps
CPU time 28.67 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:16:24 PM PDT 24
Peak memory 207424 kb
Host smart-3e0110fe-b362-49c1-8e63-19329695c0a8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129776774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.2129776774
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3224279461
Short name T730
Test name
Test status
Simulation time 167690552 ps
CPU time 0.88 seconds
Started Jul 29 06:15:54 PM PDT 24
Finished Jul 29 06:15:55 PM PDT 24
Peak memory 207088 kb
Host smart-eea61e52-736f-4f61-baaa-316c199d67bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32242
79461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3224279461
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.3709025095
Short name T637
Test name
Test status
Simulation time 151648983 ps
CPU time 0.93 seconds
Started Jul 29 06:15:55 PM PDT 24
Finished Jul 29 06:15:56 PM PDT 24
Peak memory 207020 kb
Host smart-c72a951a-6bcc-4b0e-9e5f-a2c7cbdf3337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37090
25095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.3709025095
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.389948095
Short name T1420
Test name
Test status
Simulation time 186233669 ps
CPU time 0.93 seconds
Started Jul 29 06:16:05 PM PDT 24
Finished Jul 29 06:16:06 PM PDT 24
Peak memory 207072 kb
Host smart-5718263d-6df3-455e-b9ac-8b0b1798811b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38994
8095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.389948095
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3506671414
Short name T1821
Test name
Test status
Simulation time 710719227 ps
CPU time 1.82 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:01 PM PDT 24
Peak memory 207128 kb
Host smart-4bbeac7d-8f1a-4a48-bd2b-7a6a952da311
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3506671414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3506671414
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.74497049
Short name T2716
Test name
Test status
Simulation time 16628703355 ps
CPU time 35.86 seconds
Started Jul 29 06:16:01 PM PDT 24
Finished Jul 29 06:16:37 PM PDT 24
Peak memory 207348 kb
Host smart-30fb15f5-17da-40f8-bcca-e8e82865d21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74497
049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.74497049
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.3648525009
Short name T1457
Test name
Test status
Simulation time 1000430607 ps
CPU time 22.05 seconds
Started Jul 29 06:16:02 PM PDT 24
Finished Jul 29 06:16:24 PM PDT 24
Peak memory 207252 kb
Host smart-dc1c0d7b-7aed-4f0d-ae7f-91b61a45ac63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648525009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.3648525009
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3552488136
Short name T2085
Test name
Test status
Simulation time 540001057 ps
CPU time 1.59 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:01 PM PDT 24
Peak memory 207080 kb
Host smart-64023a44-e395-4f75-88d4-b9480df667d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35524
88136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3552488136
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.861788835
Short name T1729
Test name
Test status
Simulation time 139903184 ps
CPU time 0.82 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:00 PM PDT 24
Peak memory 207064 kb
Host smart-e039e3fb-c998-45d8-8fd0-0d1a7a462c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86178
8835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.861788835
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.4025353099
Short name T461
Test name
Test status
Simulation time 33512546 ps
CPU time 0.69 seconds
Started Jul 29 06:16:00 PM PDT 24
Finished Jul 29 06:16:01 PM PDT 24
Peak memory 207036 kb
Host smart-bf589817-36c8-4113-924a-06ed97a4a4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40253
53099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.4025353099
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.2434027662
Short name T868
Test name
Test status
Simulation time 908280303 ps
CPU time 2.41 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:02 PM PDT 24
Peak memory 207300 kb
Host smart-e699bd25-6406-44e0-897d-75c2c250a974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24340
27662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2434027662
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3515305433
Short name T351
Test name
Test status
Simulation time 238758863 ps
CPU time 2.19 seconds
Started Jul 29 06:16:04 PM PDT 24
Finished Jul 29 06:16:06 PM PDT 24
Peak memory 207252 kb
Host smart-b6858399-08b2-4263-b300-83ec633dcd2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35153
05433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3515305433
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.3294665786
Short name T2248
Test name
Test status
Simulation time 154039943 ps
CPU time 0.92 seconds
Started Jul 29 06:16:00 PM PDT 24
Finished Jul 29 06:16:01 PM PDT 24
Peak memory 207048 kb
Host smart-ceb662f1-bb2e-4192-9d80-8a6290cfeab5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3294665786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3294665786
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1841062782
Short name T2332
Test name
Test status
Simulation time 218992305 ps
CPU time 0.93 seconds
Started Jul 29 06:16:04 PM PDT 24
Finished Jul 29 06:16:05 PM PDT 24
Peak memory 206952 kb
Host smart-5f2795b3-4a5e-43f8-9c10-f2ee2f69601c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18410
62782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1841062782
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.4222672726
Short name T1431
Test name
Test status
Simulation time 224452923 ps
CPU time 1.01 seconds
Started Jul 29 06:16:06 PM PDT 24
Finished Jul 29 06:16:07 PM PDT 24
Peak memory 207092 kb
Host smart-71dfe931-9774-4d0b-aee6-ed750718bc2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42226
72726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.4222672726
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.1842320095
Short name T515
Test name
Test status
Simulation time 7024038792 ps
CPU time 204.95 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:19:25 PM PDT 24
Peak memory 215640 kb
Host smart-f5238e40-cc4c-42c4-afb5-c95fe3add871
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1842320095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.1842320095
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.249682859
Short name T1807
Test name
Test status
Simulation time 9101703795 ps
CPU time 66.51 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:17:05 PM PDT 24
Peak memory 207404 kb
Host smart-0872fd49-a291-4e84-a625-fb70c907ec7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=249682859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.249682859
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2394803974
Short name T1111
Test name
Test status
Simulation time 231737389 ps
CPU time 1.01 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:00 PM PDT 24
Peak memory 207076 kb
Host smart-7c971b49-a12b-4b87-ade1-09b3f6bc5aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23948
03974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2394803974
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.2539286139
Short name T2652
Test name
Test status
Simulation time 23349718997 ps
CPU time 33.16 seconds
Started Jul 29 06:16:02 PM PDT 24
Finished Jul 29 06:16:36 PM PDT 24
Peak memory 207400 kb
Host smart-ef6167ef-c8ad-417f-a99c-5b2ea29254a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25392
86139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.2539286139
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1655916277
Short name T1139
Test name
Test status
Simulation time 3337964880 ps
CPU time 4.83 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:04 PM PDT 24
Peak memory 207304 kb
Host smart-50da6514-f13c-4428-ae74-9316a865face
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16559
16277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1655916277
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3643198253
Short name T2671
Test name
Test status
Simulation time 7744456002 ps
CPU time 226.89 seconds
Started Jul 29 06:16:00 PM PDT 24
Finished Jul 29 06:19:47 PM PDT 24
Peak memory 215744 kb
Host smart-7054589f-c8d2-478c-8997-05c68b0d4684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36431
98253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3643198253
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.1357979604
Short name T1262
Test name
Test status
Simulation time 7569194502 ps
CPU time 58.05 seconds
Started Jul 29 06:16:03 PM PDT 24
Finished Jul 29 06:17:01 PM PDT 24
Peak memory 207356 kb
Host smart-4396bb8b-a1c4-40f4-aa63-89a4b75f793a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1357979604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.1357979604
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.3209929305
Short name T2254
Test name
Test status
Simulation time 289471544 ps
CPU time 1.07 seconds
Started Jul 29 06:16:05 PM PDT 24
Finished Jul 29 06:16:06 PM PDT 24
Peak memory 207116 kb
Host smart-37911e7d-d3a0-463d-8def-caceae153b99
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3209929305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.3209929305
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2668796224
Short name T2185
Test name
Test status
Simulation time 192924460 ps
CPU time 0.89 seconds
Started Jul 29 06:16:00 PM PDT 24
Finished Jul 29 06:16:01 PM PDT 24
Peak memory 207100 kb
Host smart-dc277fe7-f501-4151-9675-70715198b35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26687
96224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2668796224
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.2082440035
Short name T1154
Test name
Test status
Simulation time 6757591104 ps
CPU time 71.03 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:17:10 PM PDT 24
Peak memory 215572 kb
Host smart-486e3670-5da8-479f-a75d-0bbfedf7a5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20824
40035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.2082440035
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.157628765
Short name T1496
Test name
Test status
Simulation time 5856928221 ps
CPU time 45.25 seconds
Started Jul 29 06:16:04 PM PDT 24
Finished Jul 29 06:16:49 PM PDT 24
Peak memory 207368 kb
Host smart-0a1d2fa2-6773-4f83-a1bc-f2d8222d1240
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=157628765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.157628765
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.1337658806
Short name T1509
Test name
Test status
Simulation time 159485013 ps
CPU time 0.9 seconds
Started Jul 29 06:16:00 PM PDT 24
Finished Jul 29 06:16:01 PM PDT 24
Peak memory 207112 kb
Host smart-e7c04b76-a7fe-405b-a1c6-54c855fad96a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1337658806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.1337658806
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2263374754
Short name T2827
Test name
Test status
Simulation time 156272567 ps
CPU time 0.86 seconds
Started Jul 29 06:16:04 PM PDT 24
Finished Jul 29 06:16:05 PM PDT 24
Peak memory 207052 kb
Host smart-371a3c11-0830-43db-be7e-260c29592cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22633
74754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2263374754
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3291262703
Short name T2132
Test name
Test status
Simulation time 255607444 ps
CPU time 1.08 seconds
Started Jul 29 06:16:00 PM PDT 24
Finished Jul 29 06:16:01 PM PDT 24
Peak memory 207120 kb
Host smart-21daa7db-b9b5-4d71-aedb-8d8221509418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32912
62703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3291262703
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3387070725
Short name T360
Test name
Test status
Simulation time 188059459 ps
CPU time 0.94 seconds
Started Jul 29 06:16:00 PM PDT 24
Finished Jul 29 06:16:01 PM PDT 24
Peak memory 207128 kb
Host smart-bb113ced-6763-4fab-9ac9-4d8ce983b341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33870
70725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3387070725
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3820333074
Short name T2805
Test name
Test status
Simulation time 162555571 ps
CPU time 0.89 seconds
Started Jul 29 06:16:06 PM PDT 24
Finished Jul 29 06:16:07 PM PDT 24
Peak memory 207092 kb
Host smart-d3937bbf-6068-460c-ac4f-4f9a0127a876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38203
33074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3820333074
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.655549202
Short name T439
Test name
Test status
Simulation time 241917299 ps
CPU time 0.98 seconds
Started Jul 29 06:16:07 PM PDT 24
Finished Jul 29 06:16:08 PM PDT 24
Peak memory 207224 kb
Host smart-af0ca3d7-2ef6-4a36-b5f1-a1f1fef9d08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65554
9202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.655549202
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.1966992216
Short name T1228
Test name
Test status
Simulation time 171943553 ps
CPU time 0.91 seconds
Started Jul 29 06:16:04 PM PDT 24
Finished Jul 29 06:16:05 PM PDT 24
Peak memory 207076 kb
Host smart-2956be08-3fe5-44b5-87bb-98bfd5fdcab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19669
92216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.1966992216
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.1637423233
Short name T1410
Test name
Test status
Simulation time 208226933 ps
CPU time 0.99 seconds
Started Jul 29 06:16:08 PM PDT 24
Finished Jul 29 06:16:10 PM PDT 24
Peak memory 207100 kb
Host smart-f452b53b-ea30-4e52-96e4-df9cac740298
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1637423233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.1637423233
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.4266745850
Short name T1627
Test name
Test status
Simulation time 146781990 ps
CPU time 0.85 seconds
Started Jul 29 06:16:04 PM PDT 24
Finished Jul 29 06:16:05 PM PDT 24
Peak memory 207072 kb
Host smart-0c93b14f-f69e-4a53-a052-7f8ca4079dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42667
45850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.4266745850
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1624910606
Short name T2637
Test name
Test status
Simulation time 37471351 ps
CPU time 0.72 seconds
Started Jul 29 06:16:07 PM PDT 24
Finished Jul 29 06:16:08 PM PDT 24
Peak memory 206964 kb
Host smart-375e31c0-0ba4-4f58-a182-b30f30a2c168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16249
10606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1624910606
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2945951386
Short name T262
Test name
Test status
Simulation time 19242376027 ps
CPU time 51.02 seconds
Started Jul 29 06:16:06 PM PDT 24
Finished Jul 29 06:16:57 PM PDT 24
Peak memory 215728 kb
Host smart-2616cdcc-aee5-4c3a-9600-6832bc55fdda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29459
51386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2945951386
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2427514245
Short name T2063
Test name
Test status
Simulation time 246965922 ps
CPU time 0.97 seconds
Started Jul 29 06:16:06 PM PDT 24
Finished Jul 29 06:16:07 PM PDT 24
Peak memory 207080 kb
Host smart-47cd5e48-63f5-4c8e-9dd6-7ea9a33b7955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24275
14245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2427514245
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2042894197
Short name T459
Test name
Test status
Simulation time 269410425 ps
CPU time 1.03 seconds
Started Jul 29 06:16:07 PM PDT 24
Finished Jul 29 06:16:08 PM PDT 24
Peak memory 207088 kb
Host smart-04ee19b2-0a90-4033-bbd5-c6d112c8f9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20428
94197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2042894197
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.1068815151
Short name T686
Test name
Test status
Simulation time 199527263 ps
CPU time 0.94 seconds
Started Jul 29 06:16:09 PM PDT 24
Finished Jul 29 06:16:10 PM PDT 24
Peak memory 207076 kb
Host smart-691bb65e-305d-42b2-ab55-f9378c238ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10688
15151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.1068815151
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.2299834573
Short name T571
Test name
Test status
Simulation time 155084173 ps
CPU time 0.9 seconds
Started Jul 29 06:16:05 PM PDT 24
Finished Jul 29 06:16:06 PM PDT 24
Peak memory 207076 kb
Host smart-9689257b-9a47-4d04-8bae-b6ff3c12bfdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22998
34573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.2299834573
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.2038488557
Short name T2740
Test name
Test status
Simulation time 208819655 ps
CPU time 0.95 seconds
Started Jul 29 06:16:07 PM PDT 24
Finished Jul 29 06:16:08 PM PDT 24
Peak memory 207224 kb
Host smart-ee1a8b84-9420-4dcd-be1c-11151577b16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20384
88557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.2038488557
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1718484993
Short name T1493
Test name
Test status
Simulation time 155355963 ps
CPU time 0.84 seconds
Started Jul 29 06:16:05 PM PDT 24
Finished Jul 29 06:16:06 PM PDT 24
Peak memory 207080 kb
Host smart-fd6877d4-237e-4cbc-92ac-83af60c97381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17184
84993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1718484993
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3205190973
Short name T1276
Test name
Test status
Simulation time 157777414 ps
CPU time 0.82 seconds
Started Jul 29 06:16:05 PM PDT 24
Finished Jul 29 06:16:06 PM PDT 24
Peak memory 207116 kb
Host smart-34e3d38e-4440-4bee-8cb9-ee281c7f4fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32051
90973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3205190973
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2834007975
Short name T2126
Test name
Test status
Simulation time 210043277 ps
CPU time 0.95 seconds
Started Jul 29 06:16:03 PM PDT 24
Finished Jul 29 06:16:05 PM PDT 24
Peak memory 207104 kb
Host smart-716c23cb-05a4-4ef2-aa84-0a5523cbcb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28340
07975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2834007975
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.4077765691
Short name T842
Test name
Test status
Simulation time 6734594058 ps
CPU time 68.72 seconds
Started Jul 29 06:16:04 PM PDT 24
Finished Jul 29 06:17:12 PM PDT 24
Peak memory 216752 kb
Host smart-10be9727-fffc-4feb-9d85-4071395e286a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4077765691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.4077765691
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3302715331
Short name T2492
Test name
Test status
Simulation time 182305569 ps
CPU time 0.89 seconds
Started Jul 29 06:16:08 PM PDT 24
Finished Jul 29 06:16:09 PM PDT 24
Peak memory 207108 kb
Host smart-f5e46454-beae-4465-a690-5240e4240500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33027
15331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3302715331
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1907398520
Short name T667
Test name
Test status
Simulation time 180752062 ps
CPU time 0.96 seconds
Started Jul 29 06:16:07 PM PDT 24
Finished Jul 29 06:16:08 PM PDT 24
Peak memory 207104 kb
Host smart-b5f0f255-d1c5-42be-a0fa-5bad519ca5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19073
98520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1907398520
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.2609642255
Short name T2067
Test name
Test status
Simulation time 670957108 ps
CPU time 1.82 seconds
Started Jul 29 06:16:07 PM PDT 24
Finished Jul 29 06:16:09 PM PDT 24
Peak memory 207064 kb
Host smart-17562a08-12ea-4065-a4c2-b2b15f003674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26096
42255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.2609642255
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1679685765
Short name T2772
Test name
Test status
Simulation time 5601051023 ps
CPU time 163.64 seconds
Started Jul 29 06:16:05 PM PDT 24
Finished Jul 29 06:18:49 PM PDT 24
Peak memory 215660 kb
Host smart-2a011730-86f0-475a-a8f2-12e70a8bea03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16796
85765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1679685765
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.3518205556
Short name T562
Test name
Test status
Simulation time 5664807681 ps
CPU time 36.01 seconds
Started Jul 29 06:15:59 PM PDT 24
Finished Jul 29 06:16:36 PM PDT 24
Peak memory 207412 kb
Host smart-eac48010-e187-49fc-a480-fd68f9ef05cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518205556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.3518205556
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.1833262528
Short name T2573
Test name
Test status
Simulation time 46452687 ps
CPU time 0.66 seconds
Started Jul 29 06:16:16 PM PDT 24
Finished Jul 29 06:16:17 PM PDT 24
Peak memory 207148 kb
Host smart-9c719476-ffce-4a57-a48c-5e4dc1b9ee1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1833262528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.1833262528
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.419202524
Short name T1722
Test name
Test status
Simulation time 3842609704 ps
CPU time 5.91 seconds
Started Jul 29 06:16:09 PM PDT 24
Finished Jul 29 06:16:15 PM PDT 24
Peak memory 207336 kb
Host smart-3f480053-a10f-4a1b-8c81-2d38c5bb100e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419202524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_ao
n_wake_disconnect.419202524
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.2512830756
Short name T766
Test name
Test status
Simulation time 13367718571 ps
CPU time 15.79 seconds
Started Jul 29 06:16:05 PM PDT 24
Finished Jul 29 06:16:21 PM PDT 24
Peak memory 207396 kb
Host smart-86b3e16b-a0e1-4e57-a361-39bd3a436fab
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512830756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.2512830756
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.2069729299
Short name T2493
Test name
Test status
Simulation time 23401570916 ps
CPU time 31.48 seconds
Started Jul 29 06:16:08 PM PDT 24
Finished Jul 29 06:16:40 PM PDT 24
Peak memory 207400 kb
Host smart-bd20f4b7-6d44-4c6d-89ca-cb4dd427a490
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069729299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.2069729299
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.547374157
Short name T2618
Test name
Test status
Simulation time 165682971 ps
CPU time 0.98 seconds
Started Jul 29 06:16:08 PM PDT 24
Finished Jul 29 06:16:09 PM PDT 24
Peak memory 207104 kb
Host smart-8cf7889d-254d-4279-ab9a-d28fb774b3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54737
4157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.547374157
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.4260372523
Short name T2200
Test name
Test status
Simulation time 170377883 ps
CPU time 0.83 seconds
Started Jul 29 06:16:07 PM PDT 24
Finished Jul 29 06:16:08 PM PDT 24
Peak memory 207072 kb
Host smart-90ebe7ca-994e-414c-9117-ee9493bb1799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42603
72523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.4260372523
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2801885105
Short name T2731
Test name
Test status
Simulation time 177291770 ps
CPU time 0.89 seconds
Started Jul 29 06:16:04 PM PDT 24
Finished Jul 29 06:16:05 PM PDT 24
Peak memory 206996 kb
Host smart-464ff919-1b6b-441b-9db4-32004c82721d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28018
85105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2801885105
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.4275433310
Short name T2071
Test name
Test status
Simulation time 517265553 ps
CPU time 1.63 seconds
Started Jul 29 06:16:07 PM PDT 24
Finished Jul 29 06:16:09 PM PDT 24
Peak memory 207100 kb
Host smart-f628a8f9-8fd5-48d5-9e60-7cb09523c38b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4275433310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.4275433310
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.1602252150
Short name T1411
Test name
Test status
Simulation time 10028474289 ps
CPU time 23.15 seconds
Started Jul 29 06:16:05 PM PDT 24
Finished Jul 29 06:16:28 PM PDT 24
Peak memory 207464 kb
Host smart-0d640514-2683-4753-a1fe-c1b8c2cb40e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16022
52150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.1602252150
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.614904128
Short name T384
Test name
Test status
Simulation time 819337997 ps
CPU time 5.96 seconds
Started Jul 29 06:16:10 PM PDT 24
Finished Jul 29 06:16:17 PM PDT 24
Peak memory 207252 kb
Host smart-a85e7bd2-5b77-4329-836b-0b98a8eeb428
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614904128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.614904128
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.1177587611
Short name T1697
Test name
Test status
Simulation time 347562884 ps
CPU time 1.31 seconds
Started Jul 29 06:16:12 PM PDT 24
Finished Jul 29 06:16:13 PM PDT 24
Peak memory 206984 kb
Host smart-b8787f4f-c2b3-43ce-8900-fce3214f013f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11775
87611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.1177587611
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.403621312
Short name T2721
Test name
Test status
Simulation time 142870155 ps
CPU time 0.84 seconds
Started Jul 29 06:16:10 PM PDT 24
Finished Jul 29 06:16:11 PM PDT 24
Peak memory 207040 kb
Host smart-c44870e0-6265-4eb1-a1e6-d01de15163ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40362
1312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.403621312
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3546087395
Short name T1755
Test name
Test status
Simulation time 32427005 ps
CPU time 0.7 seconds
Started Jul 29 06:16:08 PM PDT 24
Finished Jul 29 06:16:09 PM PDT 24
Peak memory 207064 kb
Host smart-a5ef8b92-7fea-4a46-b8f2-47f350b8a3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35460
87395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3546087395
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2368688303
Short name T2361
Test name
Test status
Simulation time 918270452 ps
CPU time 2.26 seconds
Started Jul 29 06:16:11 PM PDT 24
Finished Jul 29 06:16:13 PM PDT 24
Peak memory 207312 kb
Host smart-16e4858e-a474-4fd3-ae1c-6dd56048790b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23686
88303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2368688303
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2588433101
Short name T2552
Test name
Test status
Simulation time 280099317 ps
CPU time 2.18 seconds
Started Jul 29 06:16:10 PM PDT 24
Finished Jul 29 06:16:12 PM PDT 24
Peak memory 207416 kb
Host smart-80175535-213c-44d7-beea-bebaa959ffe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25884
33101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2588433101
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.773027142
Short name T2278
Test name
Test status
Simulation time 168230824 ps
CPU time 0.94 seconds
Started Jul 29 06:16:10 PM PDT 24
Finished Jul 29 06:16:11 PM PDT 24
Peak memory 207144 kb
Host smart-149327a0-2dae-452a-ad63-e46c8cca0b1f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=773027142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.773027142
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.854888859
Short name T2856
Test name
Test status
Simulation time 167354834 ps
CPU time 0.86 seconds
Started Jul 29 06:16:08 PM PDT 24
Finished Jul 29 06:16:09 PM PDT 24
Peak memory 207016 kb
Host smart-920de5bb-8e2d-4125-9f1d-f0aaeae55af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85488
8859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.854888859
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.4247984606
Short name T2366
Test name
Test status
Simulation time 183162923 ps
CPU time 0.91 seconds
Started Jul 29 06:16:13 PM PDT 24
Finished Jul 29 06:16:14 PM PDT 24
Peak memory 207080 kb
Host smart-d0b07e5e-2c28-48fd-9e8b-ffa132e4bb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42479
84606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.4247984606
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.919751554
Short name T2439
Test name
Test status
Simulation time 10108586087 ps
CPU time 85.9 seconds
Started Jul 29 06:16:14 PM PDT 24
Finished Jul 29 06:17:40 PM PDT 24
Peak memory 215516 kb
Host smart-40b8545c-2d37-46e4-9b8b-eef4ffa3a86c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=919751554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.919751554
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.255149586
Short name T1131
Test name
Test status
Simulation time 12064471267 ps
CPU time 159.42 seconds
Started Jul 29 06:16:11 PM PDT 24
Finished Jul 29 06:18:51 PM PDT 24
Peak memory 207392 kb
Host smart-93e664bb-d4c8-417c-8c18-44d527816325
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=255149586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.255149586
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3353020927
Short name T1939
Test name
Test status
Simulation time 169106921 ps
CPU time 1 seconds
Started Jul 29 06:16:08 PM PDT 24
Finished Jul 29 06:16:09 PM PDT 24
Peak memory 207268 kb
Host smart-a2b09312-25a0-4b5b-bb4d-83ea56971488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33530
20927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3353020927
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.3967950275
Short name T2421
Test name
Test status
Simulation time 23285156815 ps
CPU time 28.27 seconds
Started Jul 29 06:16:13 PM PDT 24
Finished Jul 29 06:16:41 PM PDT 24
Peak memory 207384 kb
Host smart-7a458268-d9d9-4ade-a277-57b3cdc2b3c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39679
50275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.3967950275
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1814094638
Short name T338
Test name
Test status
Simulation time 3266477872 ps
CPU time 5.91 seconds
Started Jul 29 06:16:08 PM PDT 24
Finished Jul 29 06:16:14 PM PDT 24
Peak memory 207356 kb
Host smart-fe49c2b0-5c8d-4f4c-bc65-c619bdb4bf3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18140
94638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1814094638
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.3438468107
Short name T1082
Test name
Test status
Simulation time 6609300290 ps
CPU time 210.57 seconds
Started Jul 29 06:16:07 PM PDT 24
Finished Jul 29 06:19:38 PM PDT 24
Peak memory 215556 kb
Host smart-e373fc77-de6e-4d10-83f5-1ff7f60f1016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34384
68107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.3438468107
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2795484198
Short name T1037
Test name
Test status
Simulation time 3744652894 ps
CPU time 43.93 seconds
Started Jul 29 06:16:12 PM PDT 24
Finished Jul 29 06:16:56 PM PDT 24
Peak memory 215440 kb
Host smart-cb62efec-2fc4-4872-b22b-d7f2c1ee2dbe
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2795484198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2795484198
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.3475118472
Short name T1255
Test name
Test status
Simulation time 243789640 ps
CPU time 1.04 seconds
Started Jul 29 06:16:11 PM PDT 24
Finished Jul 29 06:16:12 PM PDT 24
Peak memory 207124 kb
Host smart-c0d90486-1d3c-4f54-a0b3-cbfe0a13b710
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3475118472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.3475118472
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1047798431
Short name T1518
Test name
Test status
Simulation time 231119945 ps
CPU time 0.98 seconds
Started Jul 29 06:16:09 PM PDT 24
Finished Jul 29 06:16:11 PM PDT 24
Peak memory 207132 kb
Host smart-b11f245b-3007-4eb0-95cd-ba4da965bdba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10477
98431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1047798431
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.953580686
Short name T2397
Test name
Test status
Simulation time 3823655675 ps
CPU time 108.3 seconds
Started Jul 29 06:16:13 PM PDT 24
Finished Jul 29 06:18:01 PM PDT 24
Peak memory 215484 kb
Host smart-bd7fe05d-6949-476f-874f-6651b005ec1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95358
0686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.953580686
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.2292535398
Short name T2713
Test name
Test status
Simulation time 6059286097 ps
CPU time 189.18 seconds
Started Jul 29 06:16:13 PM PDT 24
Finished Jul 29 06:19:22 PM PDT 24
Peak memory 215500 kb
Host smart-ec4ff9c8-5dec-486b-a200-b9ed9edb3a62
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2292535398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.2292535398
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.1489547929
Short name T1222
Test name
Test status
Simulation time 167386813 ps
CPU time 0.86 seconds
Started Jul 29 06:16:09 PM PDT 24
Finished Jul 29 06:16:10 PM PDT 24
Peak memory 207152 kb
Host smart-c9b890a0-6306-466a-9370-48b525a62d6e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1489547929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.1489547929
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2939696013
Short name T1218
Test name
Test status
Simulation time 148002185 ps
CPU time 0.84 seconds
Started Jul 29 06:16:11 PM PDT 24
Finished Jul 29 06:16:12 PM PDT 24
Peak memory 207120 kb
Host smart-e9cd7908-82a5-4b10-8f66-54a540f0ae51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29396
96013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2939696013
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1691838163
Short name T143
Test name
Test status
Simulation time 220618134 ps
CPU time 1.01 seconds
Started Jul 29 06:16:19 PM PDT 24
Finished Jul 29 06:16:20 PM PDT 24
Peak memory 207072 kb
Host smart-451e685c-7371-40a2-908b-760658fb0d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16918
38163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1691838163
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3575821389
Short name T116
Test name
Test status
Simulation time 174624869 ps
CPU time 0.88 seconds
Started Jul 29 06:16:17 PM PDT 24
Finished Jul 29 06:16:18 PM PDT 24
Peak memory 207064 kb
Host smart-346e32d1-4f68-4843-b647-5e50e0b43706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35758
21389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3575821389
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1377815082
Short name T1658
Test name
Test status
Simulation time 183795458 ps
CPU time 0.98 seconds
Started Jul 29 06:16:19 PM PDT 24
Finished Jul 29 06:16:20 PM PDT 24
Peak memory 207000 kb
Host smart-74dd4214-b537-420b-a035-2db3db9d2d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13778
15082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1377815082
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3281998198
Short name T2042
Test name
Test status
Simulation time 182465654 ps
CPU time 0.88 seconds
Started Jul 29 06:16:17 PM PDT 24
Finished Jul 29 06:16:18 PM PDT 24
Peak memory 207112 kb
Host smart-f17b5641-dbb9-449b-beaa-368718c240b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32819
98198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3281998198
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.4110619249
Short name T2418
Test name
Test status
Simulation time 161694612 ps
CPU time 0.87 seconds
Started Jul 29 06:16:17 PM PDT 24
Finished Jul 29 06:16:18 PM PDT 24
Peak memory 207044 kb
Host smart-c6cff7fd-89b5-41ed-934d-cfc1cc16df33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41106
19249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.4110619249
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.745335194
Short name T1683
Test name
Test status
Simulation time 210635003 ps
CPU time 1.03 seconds
Started Jul 29 06:16:16 PM PDT 24
Finished Jul 29 06:16:17 PM PDT 24
Peak memory 207096 kb
Host smart-b5b445c8-0d19-4742-8648-8dd7cc512a7e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=745335194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.745335194
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1123274355
Short name T1378
Test name
Test status
Simulation time 142218536 ps
CPU time 0.84 seconds
Started Jul 29 06:16:18 PM PDT 24
Finished Jul 29 06:16:18 PM PDT 24
Peak memory 207084 kb
Host smart-df248b51-6158-4936-a040-a88dd10ce755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11232
74355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1123274355
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1348184748
Short name T40
Test name
Test status
Simulation time 91108016 ps
CPU time 0.73 seconds
Started Jul 29 06:16:17 PM PDT 24
Finished Jul 29 06:16:18 PM PDT 24
Peak memory 207088 kb
Host smart-575bfe9a-1345-49fd-a9ba-987af04e9833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13481
84748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1348184748
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1273677007
Short name T237
Test name
Test status
Simulation time 20857986247 ps
CPU time 52.39 seconds
Started Jul 29 06:16:16 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 215628 kb
Host smart-11a65b27-09d8-44b4-9983-3bdcf86f7a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12736
77007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1273677007
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3601091413
Short name T285
Test name
Test status
Simulation time 164897552 ps
CPU time 0.89 seconds
Started Jul 29 06:16:17 PM PDT 24
Finished Jul 29 06:16:18 PM PDT 24
Peak memory 207116 kb
Host smart-69d2ea74-6bbe-4f49-8d04-d9b72b380c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36010
91413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3601091413
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3093388035
Short name T826
Test name
Test status
Simulation time 185815353 ps
CPU time 0.91 seconds
Started Jul 29 06:16:16 PM PDT 24
Finished Jul 29 06:16:17 PM PDT 24
Peak memory 207048 kb
Host smart-9ebcc082-fa81-4fbb-a544-ab691ab00952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30933
88035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3093388035
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2437675473
Short name T422
Test name
Test status
Simulation time 191953934 ps
CPU time 0.89 seconds
Started Jul 29 06:16:16 PM PDT 24
Finished Jul 29 06:16:17 PM PDT 24
Peak memory 207068 kb
Host smart-e9073e51-b2e8-4e17-bafa-2a46b1c10dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24376
75473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2437675473
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1444791397
Short name T1315
Test name
Test status
Simulation time 191493558 ps
CPU time 0.88 seconds
Started Jul 29 06:16:13 PM PDT 24
Finished Jul 29 06:16:14 PM PDT 24
Peak memory 207032 kb
Host smart-c324f1a5-342c-4a9c-8415-b19b9ec1a091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14447
91397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1444791397
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.168218955
Short name T2237
Test name
Test status
Simulation time 167089457 ps
CPU time 0.9 seconds
Started Jul 29 06:16:17 PM PDT 24
Finished Jul 29 06:16:18 PM PDT 24
Peak memory 207052 kb
Host smart-e755dd44-05fb-4d71-a396-8a456123543a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16821
8955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.168218955
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2668311493
Short name T1094
Test name
Test status
Simulation time 154050988 ps
CPU time 0.83 seconds
Started Jul 29 06:16:16 PM PDT 24
Finished Jul 29 06:16:17 PM PDT 24
Peak memory 207100 kb
Host smart-6b5c8fe5-d46b-4175-8fa1-0461ac3e5a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26683
11493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2668311493
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.266849450
Short name T1732
Test name
Test status
Simulation time 149285823 ps
CPU time 0.87 seconds
Started Jul 29 06:16:21 PM PDT 24
Finished Jul 29 06:16:22 PM PDT 24
Peak memory 207092 kb
Host smart-80934ac3-dddd-49a8-960c-5df257ed8762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26684
9450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.266849450
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1781220399
Short name T2020
Test name
Test status
Simulation time 234854228 ps
CPU time 1.02 seconds
Started Jul 29 06:16:17 PM PDT 24
Finished Jul 29 06:16:18 PM PDT 24
Peak memory 207136 kb
Host smart-7ff5631f-7c00-4118-a315-854ddda4107e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17812
20399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1781220399
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.2643630203
Short name T2803
Test name
Test status
Simulation time 4947473833 ps
CPU time 40.19 seconds
Started Jul 29 06:16:17 PM PDT 24
Finished Jul 29 06:16:57 PM PDT 24
Peak memory 217212 kb
Host smart-0978a488-021a-4079-a374-419e4ff17706
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2643630203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.2643630203
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3596695371
Short name T275
Test name
Test status
Simulation time 172761403 ps
CPU time 0.89 seconds
Started Jul 29 06:16:15 PM PDT 24
Finished Jul 29 06:16:16 PM PDT 24
Peak memory 207108 kb
Host smart-6f4fe3b1-4226-4d0e-853a-313cf3656a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35966
95371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3596695371
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1497772277
Short name T2024
Test name
Test status
Simulation time 150255345 ps
CPU time 0.89 seconds
Started Jul 29 06:16:15 PM PDT 24
Finished Jul 29 06:16:16 PM PDT 24
Peak memory 207104 kb
Host smart-83364dd0-8ce1-467d-b897-c854657508cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14977
72277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1497772277
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.4072416691
Short name T776
Test name
Test status
Simulation time 850136768 ps
CPU time 2.11 seconds
Started Jul 29 06:16:18 PM PDT 24
Finished Jul 29 06:16:21 PM PDT 24
Peak memory 207152 kb
Host smart-d2f6841b-97bd-49a8-8cc1-5a6d874986dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40724
16691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.4072416691
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3706963162
Short name T984
Test name
Test status
Simulation time 4984045621 ps
CPU time 50.43 seconds
Started Jul 29 06:16:17 PM PDT 24
Finished Jul 29 06:17:07 PM PDT 24
Peak memory 216744 kb
Host smart-e28a667d-ab08-4ca1-983a-fc642c4ac849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37069
63162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3706963162
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.3061856346
Short name T1391
Test name
Test status
Simulation time 1007319040 ps
CPU time 23.89 seconds
Started Jul 29 06:16:09 PM PDT 24
Finished Jul 29 06:16:33 PM PDT 24
Peak memory 207284 kb
Host smart-1bcde95a-6184-421f-832e-32de65b2a75a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061856346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.3061856346
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.1105116700
Short name T750
Test name
Test status
Simulation time 78854839 ps
CPU time 0.74 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:30 PM PDT 24
Peak memory 207128 kb
Host smart-4ed8a70a-9f93-4515-b3cd-cd8149f0a933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1105116700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.1105116700
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.4079825099
Short name T536
Test name
Test status
Simulation time 3737035795 ps
CPU time 5.71 seconds
Started Jul 29 06:16:16 PM PDT 24
Finished Jul 29 06:16:22 PM PDT 24
Peak memory 207324 kb
Host smart-86f8c2cc-b5ea-4929-ad3e-f7514ea35176
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079825099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_disconnect.4079825099
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.487998346
Short name T2676
Test name
Test status
Simulation time 13343474203 ps
CPU time 19.78 seconds
Started Jul 29 06:16:19 PM PDT 24
Finished Jul 29 06:16:39 PM PDT 24
Peak memory 207308 kb
Host smart-dd0c9903-b133-4671-a1cf-7ac66cfee097
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=487998346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.487998346
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.188985469
Short name T1512
Test name
Test status
Simulation time 23350457310 ps
CPU time 26.53 seconds
Started Jul 29 06:16:24 PM PDT 24
Finished Jul 29 06:16:50 PM PDT 24
Peak memory 207416 kb
Host smart-c4063052-11c5-4775-831d-349a48fafa8a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188985469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ao
n_wake_resume.188985469
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1716514294
Short name T705
Test name
Test status
Simulation time 154447677 ps
CPU time 0.91 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:30 PM PDT 24
Peak memory 207124 kb
Host smart-b2116583-748f-4bdd-8e5c-7723793e3274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17165
14294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1716514294
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3859514250
Short name T1566
Test name
Test status
Simulation time 177366642 ps
CPU time 0.87 seconds
Started Jul 29 06:16:20 PM PDT 24
Finished Jul 29 06:16:21 PM PDT 24
Peak memory 207068 kb
Host smart-b18ec49c-1ec3-4bf0-8c26-9173a068e0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38595
14250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3859514250
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.1389821356
Short name T989
Test name
Test status
Simulation time 304945050 ps
CPU time 1.25 seconds
Started Jul 29 06:16:21 PM PDT 24
Finished Jul 29 06:16:22 PM PDT 24
Peak memory 207120 kb
Host smart-9e0a281f-a42a-4ad1-8bd8-227d71959a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13898
21356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.1389821356
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1735593008
Short name T2061
Test name
Test status
Simulation time 1056679191 ps
CPU time 2.75 seconds
Started Jul 29 06:16:23 PM PDT 24
Finished Jul 29 06:16:26 PM PDT 24
Peak memory 207336 kb
Host smart-210996c6-b862-4bdf-b512-eefbebd7b492
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1735593008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1735593008
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.4282486418
Short name T798
Test name
Test status
Simulation time 16808006483 ps
CPU time 36.14 seconds
Started Jul 29 06:16:20 PM PDT 24
Finished Jul 29 06:16:56 PM PDT 24
Peak memory 207352 kb
Host smart-b5fe7cf0-c461-47ac-bfb2-04f57f00190d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42824
86418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.4282486418
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.4184212612
Short name T1723
Test name
Test status
Simulation time 286845533 ps
CPU time 4.57 seconds
Started Jul 29 06:16:23 PM PDT 24
Finished Jul 29 06:16:28 PM PDT 24
Peak memory 207276 kb
Host smart-9fb90fc3-9c1a-47de-a59a-4068ab6274a2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184212612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.4184212612
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.1176084832
Short name T1014
Test name
Test status
Simulation time 384845335 ps
CPU time 1.34 seconds
Started Jul 29 06:16:22 PM PDT 24
Finished Jul 29 06:16:24 PM PDT 24
Peak memory 207044 kb
Host smart-bbd28fb2-973d-4b68-b06a-84b9f1fee41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11760
84832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1176084832
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2525937809
Short name T1775
Test name
Test status
Simulation time 183049169 ps
CPU time 0.87 seconds
Started Jul 29 06:16:21 PM PDT 24
Finished Jul 29 06:16:22 PM PDT 24
Peak memory 206968 kb
Host smart-ea5bf9b7-dfd7-4028-bded-3f9c3c83f8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25259
37809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2525937809
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1141105422
Short name T2734
Test name
Test status
Simulation time 34275506 ps
CPU time 0.71 seconds
Started Jul 29 06:16:23 PM PDT 24
Finished Jul 29 06:16:23 PM PDT 24
Peak memory 206840 kb
Host smart-72b75b58-600a-4bf0-9185-c5982df7add2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11411
05422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1141105422
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.4010985964
Short name T1285
Test name
Test status
Simulation time 920340437 ps
CPU time 2.29 seconds
Started Jul 29 06:16:20 PM PDT 24
Finished Jul 29 06:16:22 PM PDT 24
Peak memory 207300 kb
Host smart-4c47e7ff-ddfd-428c-a149-3dc4e6bfdf5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40109
85964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.4010985964
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2441192875
Short name T2601
Test name
Test status
Simulation time 411034079 ps
CPU time 2.72 seconds
Started Jul 29 06:16:18 PM PDT 24
Finished Jul 29 06:16:21 PM PDT 24
Peak memory 207336 kb
Host smart-1fb2d2f4-fe73-40bd-8e76-05f0b068c121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24411
92875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2441192875
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1844502096
Short name T804
Test name
Test status
Simulation time 216267986 ps
CPU time 1.15 seconds
Started Jul 29 06:16:20 PM PDT 24
Finished Jul 29 06:16:22 PM PDT 24
Peak memory 215452 kb
Host smart-b9ae5e4d-7778-4d40-92b1-7f36edbcfc2e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1844502096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1844502096
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.518161024
Short name T2770
Test name
Test status
Simulation time 140982355 ps
CPU time 0.91 seconds
Started Jul 29 06:16:24 PM PDT 24
Finished Jul 29 06:16:25 PM PDT 24
Peak memory 207068 kb
Host smart-ed8d2611-ff17-4856-b318-6c924743df43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51816
1024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.518161024
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.184653619
Short name T907
Test name
Test status
Simulation time 209094050 ps
CPU time 0.99 seconds
Started Jul 29 06:16:21 PM PDT 24
Finished Jul 29 06:16:22 PM PDT 24
Peak memory 207264 kb
Host smart-64a751e1-67f0-44d6-8429-878e87a837e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18465
3619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.184653619
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.2624048727
Short name T1541
Test name
Test status
Simulation time 7196454856 ps
CPU time 76.24 seconds
Started Jul 29 06:16:22 PM PDT 24
Finished Jul 29 06:17:38 PM PDT 24
Peak memory 216752 kb
Host smart-1eb40fe7-f7de-463e-9017-0e4d6691a4ac
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2624048727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.2624048727
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.2902141509
Short name T1999
Test name
Test status
Simulation time 148402153 ps
CPU time 0.85 seconds
Started Jul 29 06:16:19 PM PDT 24
Finished Jul 29 06:16:20 PM PDT 24
Peak memory 207104 kb
Host smart-195d9cf6-bbff-4bc3-bdb9-c9e8472b13f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29021
41509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2902141509
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3514625840
Short name T1052
Test name
Test status
Simulation time 23313600257 ps
CPU time 26.44 seconds
Started Jul 29 06:16:22 PM PDT 24
Finished Jul 29 06:16:49 PM PDT 24
Peak memory 207380 kb
Host smart-0c1f8baf-b55f-40ba-bdea-89466146e898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35146
25840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3514625840
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.1719123593
Short name T1670
Test name
Test status
Simulation time 3268414674 ps
CPU time 5.64 seconds
Started Jul 29 06:16:23 PM PDT 24
Finished Jul 29 06:16:28 PM PDT 24
Peak memory 207320 kb
Host smart-708ea875-c870-4a2c-aac7-03297b110ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17191
23593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1719123593
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.2091359679
Short name T1801
Test name
Test status
Simulation time 7447322565 ps
CPU time 219.31 seconds
Started Jul 29 06:16:32 PM PDT 24
Finished Jul 29 06:20:12 PM PDT 24
Peak memory 215536 kb
Host smart-4d05f987-25b0-4e42-9ba8-8bb79eb398ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20913
59679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.2091359679
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.1087936315
Short name T2351
Test name
Test status
Simulation time 6595401487 ps
CPU time 69.05 seconds
Started Jul 29 06:16:20 PM PDT 24
Finished Jul 29 06:17:30 PM PDT 24
Peak memory 207412 kb
Host smart-ffaa9569-a7df-4298-adaa-5b730bb93f0c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1087936315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.1087936315
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.3257190677
Short name T323
Test name
Test status
Simulation time 247851019 ps
CPU time 0.98 seconds
Started Jul 29 06:16:20 PM PDT 24
Finished Jul 29 06:16:21 PM PDT 24
Peak memory 207128 kb
Host smart-7020c5e7-8742-4af0-8e38-7ff176800ac8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3257190677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.3257190677
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.369054492
Short name T2218
Test name
Test status
Simulation time 229201813 ps
CPU time 0.96 seconds
Started Jul 29 06:16:23 PM PDT 24
Finished Jul 29 06:16:25 PM PDT 24
Peak memory 207096 kb
Host smart-99f1ac45-69ff-4ead-ab68-2cf764b6aa89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36905
4492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.369054492
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3825384634
Short name T877
Test name
Test status
Simulation time 5557712835 ps
CPU time 47.46 seconds
Started Jul 29 06:16:21 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 217064 kb
Host smart-4ceae1c8-e1b7-4568-ba59-7466ab28f5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38253
84634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3825384634
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.2052862498
Short name T596
Test name
Test status
Simulation time 4266066739 ps
CPU time 130.16 seconds
Started Jul 29 06:16:23 PM PDT 24
Finished Jul 29 06:18:33 PM PDT 24
Peak memory 215312 kb
Host smart-736a0cc6-5a74-4a44-80fc-01fdfeb3a7c4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2052862498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.2052862498
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.475357999
Short name T1083
Test name
Test status
Simulation time 156329282 ps
CPU time 0.84 seconds
Started Jul 29 06:16:20 PM PDT 24
Finished Jul 29 06:16:21 PM PDT 24
Peak memory 207068 kb
Host smart-6761c850-d755-463e-8650-d5c56bb486ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=475357999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.475357999
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2448785668
Short name T2013
Test name
Test status
Simulation time 146051412 ps
CPU time 0.84 seconds
Started Jul 29 06:16:21 PM PDT 24
Finished Jul 29 06:16:22 PM PDT 24
Peak memory 207264 kb
Host smart-7fa0442b-43b6-4028-942c-fd547367583c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24487
85668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2448785668
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3133080700
Short name T2804
Test name
Test status
Simulation time 183790188 ps
CPU time 0.89 seconds
Started Jul 29 06:16:23 PM PDT 24
Finished Jul 29 06:16:24 PM PDT 24
Peak memory 207084 kb
Host smart-e2109d8f-c48e-42f6-88ae-139895602eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31330
80700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3133080700
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1407951277
Short name T336
Test name
Test status
Simulation time 161048183 ps
CPU time 0.86 seconds
Started Jul 29 06:16:22 PM PDT 24
Finished Jul 29 06:16:23 PM PDT 24
Peak memory 207072 kb
Host smart-f979e64a-c06d-44e3-b8d5-7f89c23926a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14079
51277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1407951277
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3154673317
Short name T1266
Test name
Test status
Simulation time 185784865 ps
CPU time 0.87 seconds
Started Jul 29 06:16:22 PM PDT 24
Finished Jul 29 06:16:23 PM PDT 24
Peak memory 207044 kb
Host smart-81b1549d-528a-4228-96cb-9d260b8f047c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31546
73317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3154673317
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.650726651
Short name T1789
Test name
Test status
Simulation time 185561900 ps
CPU time 0.88 seconds
Started Jul 29 06:16:20 PM PDT 24
Finished Jul 29 06:16:21 PM PDT 24
Peak memory 207068 kb
Host smart-30d5d497-da0f-46ff-add8-3757af7c1e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65072
6651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.650726651
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.178659017
Short name T2087
Test name
Test status
Simulation time 150777917 ps
CPU time 0.81 seconds
Started Jul 29 06:16:26 PM PDT 24
Finished Jul 29 06:16:27 PM PDT 24
Peak memory 207052 kb
Host smart-f5864a90-2aaf-4c47-8094-efe541fc1248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17865
9017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.178659017
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.3198330405
Short name T1615
Test name
Test status
Simulation time 274263413 ps
CPU time 1.1 seconds
Started Jul 29 06:16:27 PM PDT 24
Finished Jul 29 06:16:28 PM PDT 24
Peak memory 207108 kb
Host smart-c31d2d31-1375-41d8-8485-48b3742c4b86
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3198330405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.3198330405
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2563224007
Short name T1059
Test name
Test status
Simulation time 223084305 ps
CPU time 0.97 seconds
Started Jul 29 06:16:31 PM PDT 24
Finished Jul 29 06:16:32 PM PDT 24
Peak memory 207108 kb
Host smart-be652937-ea63-4ace-98ee-868e2471fe85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25632
24007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2563224007
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2552686591
Short name T1247
Test name
Test status
Simulation time 48040595 ps
CPU time 0.71 seconds
Started Jul 29 06:16:26 PM PDT 24
Finished Jul 29 06:16:27 PM PDT 24
Peak memory 207064 kb
Host smart-a3234250-e49c-4f50-9f9f-b82b15204a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25526
86591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2552686591
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1053465109
Short name T1661
Test name
Test status
Simulation time 19172459933 ps
CPU time 48.92 seconds
Started Jul 29 06:16:30 PM PDT 24
Finished Jul 29 06:17:19 PM PDT 24
Peak memory 220144 kb
Host smart-eec697e4-25df-40d9-88cd-393ad694c96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10534
65109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1053465109
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.667720522
Short name T610
Test name
Test status
Simulation time 205124365 ps
CPU time 0.95 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:30 PM PDT 24
Peak memory 207132 kb
Host smart-7853f4af-4b03-475b-b21b-941e949e6538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66772
0522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.667720522
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1211033799
Short name T2261
Test name
Test status
Simulation time 152931643 ps
CPU time 0.86 seconds
Started Jul 29 06:16:27 PM PDT 24
Finished Jul 29 06:16:28 PM PDT 24
Peak memory 207116 kb
Host smart-b2195a90-b0a3-471e-ab52-6d07466f2560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12110
33799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1211033799
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.305739033
Short name T2337
Test name
Test status
Simulation time 221594980 ps
CPU time 0.98 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:30 PM PDT 24
Peak memory 207088 kb
Host smart-44a6617f-ed4f-43bf-814a-c08e12e6e4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30573
9033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.305739033
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1516711981
Short name T2034
Test name
Test status
Simulation time 195735407 ps
CPU time 0.98 seconds
Started Jul 29 06:16:33 PM PDT 24
Finished Jul 29 06:16:34 PM PDT 24
Peak memory 207076 kb
Host smart-dd9884b2-5f71-4b98-8f99-294925a056b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15167
11981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1516711981
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.1622202062
Short name T1918
Test name
Test status
Simulation time 150418218 ps
CPU time 0.81 seconds
Started Jul 29 06:16:32 PM PDT 24
Finished Jul 29 06:16:33 PM PDT 24
Peak memory 207064 kb
Host smart-2df1f710-8724-4035-bda1-ddc5856be397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16222
02062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.1622202062
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.826230554
Short name T1454
Test name
Test status
Simulation time 153333581 ps
CPU time 0.86 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:30 PM PDT 24
Peak memory 207044 kb
Host smart-d7d334a4-3587-48f2-9ba0-152680cb0d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82623
0554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.826230554
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.142618009
Short name T2546
Test name
Test status
Simulation time 156294692 ps
CPU time 0.81 seconds
Started Jul 29 06:16:27 PM PDT 24
Finished Jul 29 06:16:28 PM PDT 24
Peak memory 207100 kb
Host smart-590e2b24-4b8a-4fe2-b3d4-b4292b863495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14261
8009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.142618009
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3174727912
Short name T1028
Test name
Test status
Simulation time 274688575 ps
CPU time 1.07 seconds
Started Jul 29 06:16:30 PM PDT 24
Finished Jul 29 06:16:31 PM PDT 24
Peak memory 207084 kb
Host smart-6bc6f390-2a6e-453b-ba39-faeabc17564f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31747
27912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3174727912
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.4038712792
Short name T812
Test name
Test status
Simulation time 4614959605 ps
CPU time 43.99 seconds
Started Jul 29 06:16:28 PM PDT 24
Finished Jul 29 06:17:12 PM PDT 24
Peak memory 215548 kb
Host smart-8bb04697-1b9a-4ba3-b0b4-c323b41e02d6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4038712792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.4038712792
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3271402561
Short name T1663
Test name
Test status
Simulation time 178421538 ps
CPU time 0.92 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:30 PM PDT 24
Peak memory 207108 kb
Host smart-fbf54279-d223-4e48-b7c5-c6612c943fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32714
02561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3271402561
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1305333631
Short name T1564
Test name
Test status
Simulation time 157990229 ps
CPU time 0.85 seconds
Started Jul 29 06:16:28 PM PDT 24
Finished Jul 29 06:16:29 PM PDT 24
Peak memory 207064 kb
Host smart-e9d7fb22-6e3d-4a8f-91c1-8b2fcf9d35a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13053
33631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1305333631
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.1993066996
Short name T2319
Test name
Test status
Simulation time 893422455 ps
CPU time 2.28 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:31 PM PDT 24
Peak memory 207308 kb
Host smart-bc746a44-ad5b-423d-a610-17071a297aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19930
66996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1993066996
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.2083839824
Short name T1877
Test name
Test status
Simulation time 5135915242 ps
CPU time 151.06 seconds
Started Jul 29 06:16:40 PM PDT 24
Finished Jul 29 06:19:11 PM PDT 24
Peak memory 215600 kb
Host smart-c329e94a-3ac6-4f3e-8605-b6c99a2bfb4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20838
39824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.2083839824
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.697667215
Short name T1631
Test name
Test status
Simulation time 1116044638 ps
CPU time 9.64 seconds
Started Jul 29 06:16:22 PM PDT 24
Finished Jul 29 06:16:31 PM PDT 24
Peak memory 207392 kb
Host smart-e86ad323-27ec-4928-8d33-1e9bbdb804f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697667215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_host
_handshake.697667215
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.325482517
Short name T1571
Test name
Test status
Simulation time 53666779 ps
CPU time 0.7 seconds
Started Jul 29 06:11:19 PM PDT 24
Finished Jul 29 06:11:20 PM PDT 24
Peak memory 207096 kb
Host smart-3436a800-4200-4c8f-8660-092001ac706e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=325482517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.325482517
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.4025855739
Short name T1283
Test name
Test status
Simulation time 3414773584 ps
CPU time 4.91 seconds
Started Jul 29 06:11:07 PM PDT 24
Finished Jul 29 06:11:12 PM PDT 24
Peak memory 207268 kb
Host smart-cf219ceb-cfe3-46ec-91fa-0e0c800b52b1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025855739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.4025855739
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.260630639
Short name T640
Test name
Test status
Simulation time 13362001022 ps
CPU time 16.36 seconds
Started Jul 29 06:11:07 PM PDT 24
Finished Jul 29 06:11:24 PM PDT 24
Peak memory 207440 kb
Host smart-89c79269-0004-454e-93a4-3e4dece3062c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=260630639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.260630639
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.90615868
Short name T197
Test name
Test status
Simulation time 23411786083 ps
CPU time 25.86 seconds
Started Jul 29 06:11:10 PM PDT 24
Finished Jul 29 06:11:36 PM PDT 24
Peak memory 207404 kb
Host smart-b2445077-5c54-441f-ab95-4435aa71aedd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90615868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_
wake_resume.90615868
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3868785651
Short name T1507
Test name
Test status
Simulation time 203559691 ps
CPU time 0.97 seconds
Started Jul 29 06:11:11 PM PDT 24
Finished Jul 29 06:11:12 PM PDT 24
Peak memory 207104 kb
Host smart-90b78afe-ee8d-45be-9cfc-57cd42242af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38687
85651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3868785651
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.3621732191
Short name T68
Test name
Test status
Simulation time 144861267 ps
CPU time 0.82 seconds
Started Jul 29 06:11:10 PM PDT 24
Finished Jul 29 06:11:11 PM PDT 24
Peak memory 207036 kb
Host smart-d4c15731-3df7-4da6-afaa-a69284ab37b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36217
32191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.3621732191
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.2493870601
Short name T1558
Test name
Test status
Simulation time 174767789 ps
CPU time 0.91 seconds
Started Jul 29 06:11:08 PM PDT 24
Finished Jul 29 06:11:09 PM PDT 24
Peak memory 206968 kb
Host smart-4d6b6892-337a-48af-9416-c473a54697cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24938
70601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.2493870601
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.1602218615
Short name T1654
Test name
Test status
Simulation time 199398884 ps
CPU time 1.07 seconds
Started Jul 29 06:11:09 PM PDT 24
Finished Jul 29 06:11:10 PM PDT 24
Peak memory 207092 kb
Host smart-e0e6ddf6-8761-4b8c-b4c5-1b9b0e21c0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16022
18615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.1602218615
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.4153941315
Short name T1632
Test name
Test status
Simulation time 1597730127 ps
CPU time 3.98 seconds
Started Jul 29 06:11:12 PM PDT 24
Finished Jul 29 06:11:16 PM PDT 24
Peak memory 207276 kb
Host smart-5ded090a-276e-460c-9305-24e795eb7b6a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4153941315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.4153941315
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.1627490817
Short name T94
Test name
Test status
Simulation time 14853886261 ps
CPU time 31.33 seconds
Started Jul 29 06:11:13 PM PDT 24
Finished Jul 29 06:11:44 PM PDT 24
Peak memory 207392 kb
Host smart-84adc0eb-f6da-4579-9e86-25a3e288ad68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16274
90817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1627490817
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.1005526759
Short name T2812
Test name
Test status
Simulation time 2910356357 ps
CPU time 19.95 seconds
Started Jul 29 06:11:12 PM PDT 24
Finished Jul 29 06:11:32 PM PDT 24
Peak memory 207296 kb
Host smart-f3bc08ce-84de-4b4c-94cd-84d029fe0a2f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005526759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.1005526759
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.4277465081
Short name T2179
Test name
Test status
Simulation time 444366431 ps
CPU time 1.58 seconds
Started Jul 29 06:11:10 PM PDT 24
Finished Jul 29 06:11:12 PM PDT 24
Peak memory 207108 kb
Host smart-4e0319a0-f935-449a-992a-c1c1b6fb1ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42774
65081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.4277465081
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.278750505
Short name T2214
Test name
Test status
Simulation time 167943754 ps
CPU time 0.9 seconds
Started Jul 29 06:11:15 PM PDT 24
Finished Jul 29 06:11:16 PM PDT 24
Peak memory 206948 kb
Host smart-7dc51c9f-0de9-4d33-8e6c-5ee9d8c4dbb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27875
0505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.278750505
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.3797974300
Short name T2433
Test name
Test status
Simulation time 41096268 ps
CPU time 0.71 seconds
Started Jul 29 06:11:08 PM PDT 24
Finished Jul 29 06:11:09 PM PDT 24
Peak memory 207068 kb
Host smart-42a23f19-beb8-4a62-ab81-24184f70108e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37979
74300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3797974300
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3705226730
Short name T2743
Test name
Test status
Simulation time 990716014 ps
CPU time 2.7 seconds
Started Jul 29 06:11:07 PM PDT 24
Finished Jul 29 06:11:10 PM PDT 24
Peak memory 207236 kb
Host smart-958e1d36-eb49-4d4d-a885-a4bc8d7ec9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37052
26730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3705226730
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.42457929
Short name T2246
Test name
Test status
Simulation time 164135043 ps
CPU time 1.37 seconds
Started Jul 29 06:11:08 PM PDT 24
Finished Jul 29 06:11:10 PM PDT 24
Peak memory 207208 kb
Host smart-8ca7a86e-7d61-459c-bcfd-f81ce52c69de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42457
929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.42457929
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3886126640
Short name T1746
Test name
Test status
Simulation time 103176900424 ps
CPU time 164.46 seconds
Started Jul 29 06:11:12 PM PDT 24
Finished Jul 29 06:13:57 PM PDT 24
Peak memory 207344 kb
Host smart-12f2f726-8bbf-486c-bd5f-11194951e19b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3886126640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3886126640
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.3182915231
Short name T306
Test name
Test status
Simulation time 104042676626 ps
CPU time 176.72 seconds
Started Jul 29 06:11:12 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 207264 kb
Host smart-04b83be4-9601-4744-b814-00ff6806fcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182915231 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.3182915231
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.285744642
Short name T301
Test name
Test status
Simulation time 82120409496 ps
CPU time 128.71 seconds
Started Jul 29 06:11:08 PM PDT 24
Finished Jul 29 06:13:17 PM PDT 24
Peak memory 207392 kb
Host smart-7a759b44-4d72-44dc-971e-48b884965621
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=285744642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.285744642
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.3753660648
Short name T1711
Test name
Test status
Simulation time 89972512855 ps
CPU time 163.91 seconds
Started Jul 29 06:11:09 PM PDT 24
Finished Jul 29 06:13:53 PM PDT 24
Peak memory 207336 kb
Host smart-5d3b0874-980f-480a-99f7-1ae7db485432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753660648 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.3753660648
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.2468786619
Short name T1603
Test name
Test status
Simulation time 84125233100 ps
CPU time 134.46 seconds
Started Jul 29 06:11:13 PM PDT 24
Finished Jul 29 06:13:27 PM PDT 24
Peak memory 207380 kb
Host smart-427a8cbe-3065-49e2-baeb-6f6941ad46bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24687
86619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.2468786619
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.4019593844
Short name T2344
Test name
Test status
Simulation time 198840441 ps
CPU time 1.25 seconds
Started Jul 29 06:11:12 PM PDT 24
Finished Jul 29 06:11:13 PM PDT 24
Peak memory 215452 kb
Host smart-9c5577c2-9fb6-4b81-ab97-103f1ef4d4c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4019593844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.4019593844
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1316101804
Short name T103
Test name
Test status
Simulation time 143236539 ps
CPU time 0.9 seconds
Started Jul 29 06:11:07 PM PDT 24
Finished Jul 29 06:11:08 PM PDT 24
Peak memory 207048 kb
Host smart-3e4aabe5-bf75-4613-90f6-2e4c8638fed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13161
01804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1316101804
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2233217727
Short name T2250
Test name
Test status
Simulation time 208442581 ps
CPU time 0.95 seconds
Started Jul 29 06:11:08 PM PDT 24
Finished Jul 29 06:11:09 PM PDT 24
Peak memory 207072 kb
Host smart-076cd792-a393-4ce0-9f3f-571553373f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22332
17727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2233217727
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.1854569382
Short name T2447
Test name
Test status
Simulation time 7224643119 ps
CPU time 221.8 seconds
Started Jul 29 06:11:08 PM PDT 24
Finished Jul 29 06:14:50 PM PDT 24
Peak memory 215564 kb
Host smart-aed21175-25ae-40cd-913b-d55d7f658ab2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1854569382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.1854569382
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.2440997350
Short name T1497
Test name
Test status
Simulation time 4300298080 ps
CPU time 32.59 seconds
Started Jul 29 06:11:09 PM PDT 24
Finished Jul 29 06:11:42 PM PDT 24
Peak memory 207280 kb
Host smart-f03acb3d-c8ba-409b-8a1c-2227aa1816d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2440997350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.2440997350
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.2975234440
Short name T2384
Test name
Test status
Simulation time 255539289 ps
CPU time 0.95 seconds
Started Jul 29 06:11:13 PM PDT 24
Finished Jul 29 06:11:14 PM PDT 24
Peak memory 207076 kb
Host smart-bd8ae491-558d-4c42-a72a-12c3503b72c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29752
34440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2975234440
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.542404627
Short name T662
Test name
Test status
Simulation time 23277411090 ps
CPU time 29.84 seconds
Started Jul 29 06:11:13 PM PDT 24
Finished Jul 29 06:11:43 PM PDT 24
Peak memory 207404 kb
Host smart-74338586-b9ec-494c-ac74-703d878991c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54240
4627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.542404627
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2420261028
Short name T2198
Test name
Test status
Simulation time 3306810377 ps
CPU time 5.45 seconds
Started Jul 29 06:11:13 PM PDT 24
Finished Jul 29 06:11:19 PM PDT 24
Peak memory 207300 kb
Host smart-b183ae60-da01-4d34-a30f-c827a6605a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24202
61028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2420261028
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.2531253370
Short name T1739
Test name
Test status
Simulation time 7560289794 ps
CPU time 236.88 seconds
Started Jul 29 06:11:13 PM PDT 24
Finished Jul 29 06:15:10 PM PDT 24
Peak memory 215592 kb
Host smart-88e1160d-637f-4696-a915-4252e5545199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25312
53370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2531253370
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.3054748405
Short name T159
Test name
Test status
Simulation time 3391536703 ps
CPU time 37.45 seconds
Started Jul 29 06:11:16 PM PDT 24
Finished Jul 29 06:11:54 PM PDT 24
Peak memory 215532 kb
Host smart-48669967-c610-4f1f-ac7a-cd079c05b3c7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3054748405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.3054748405
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3573445629
Short name T2266
Test name
Test status
Simulation time 250034168 ps
CPU time 1.05 seconds
Started Jul 29 06:11:13 PM PDT 24
Finished Jul 29 06:11:14 PM PDT 24
Peak memory 207104 kb
Host smart-860cb140-499b-4dd1-bcda-1340e10ad34c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3573445629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3573445629
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3721757044
Short name T2379
Test name
Test status
Simulation time 194117472 ps
CPU time 0.92 seconds
Started Jul 29 06:11:13 PM PDT 24
Finished Jul 29 06:11:14 PM PDT 24
Peak memory 207148 kb
Host smart-1bc5d872-5314-41c5-b4d0-c3f84e370c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37217
57044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3721757044
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.2588804214
Short name T1194
Test name
Test status
Simulation time 3269260425 ps
CPU time 33.67 seconds
Started Jul 29 06:11:16 PM PDT 24
Finished Jul 29 06:11:50 PM PDT 24
Peak memory 215504 kb
Host smart-f2e4857b-55b2-4a38-acb3-ecafd970ce6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25888
04214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2588804214
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.2738411242
Short name T924
Test name
Test status
Simulation time 5103713002 ps
CPU time 141.48 seconds
Started Jul 29 06:11:15 PM PDT 24
Finished Jul 29 06:13:37 PM PDT 24
Peak memory 215592 kb
Host smart-5c652862-7939-465c-9254-6c79e4fee901
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2738411242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.2738411242
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.1807415972
Short name T2035
Test name
Test status
Simulation time 153340451 ps
CPU time 0.86 seconds
Started Jul 29 06:11:14 PM PDT 24
Finished Jul 29 06:11:15 PM PDT 24
Peak memory 207108 kb
Host smart-70d15ca2-b837-4b7d-b9bd-ce25cd6d1925
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1807415972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.1807415972
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3038805890
Short name T2003
Test name
Test status
Simulation time 140192045 ps
CPU time 0.81 seconds
Started Jul 29 06:11:14 PM PDT 24
Finished Jul 29 06:11:15 PM PDT 24
Peak memory 207080 kb
Host smart-aec13d1a-4039-42a0-9234-d88cffe6fbf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30388
05890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3038805890
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1791566144
Short name T940
Test name
Test status
Simulation time 195793058 ps
CPU time 0.97 seconds
Started Jul 29 06:11:16 PM PDT 24
Finished Jul 29 06:11:17 PM PDT 24
Peak memory 207100 kb
Host smart-13fe4cba-69e8-4a92-8001-487b0ad56364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17915
66144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1791566144
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.164818480
Short name T1589
Test name
Test status
Simulation time 202214147 ps
CPU time 0.93 seconds
Started Jul 29 06:11:14 PM PDT 24
Finished Jul 29 06:11:16 PM PDT 24
Peak memory 207064 kb
Host smart-eb6bb3f1-b2bd-4595-b0b8-06d3b9a3b37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16481
8480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.164818480
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3216535522
Short name T72
Test name
Test status
Simulation time 196226209 ps
CPU time 0.9 seconds
Started Jul 29 06:11:15 PM PDT 24
Finished Jul 29 06:11:16 PM PDT 24
Peak memory 207068 kb
Host smart-54269437-81aa-481b-be60-d1f666ccc598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32165
35522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3216535522
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3602812628
Short name T2287
Test name
Test status
Simulation time 210814519 ps
CPU time 0.95 seconds
Started Jul 29 06:11:16 PM PDT 24
Finished Jul 29 06:11:17 PM PDT 24
Peak memory 207080 kb
Host smart-5fc34e59-e199-49e0-ba85-1c437a7b28d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36028
12628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3602812628
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3782596563
Short name T2037
Test name
Test status
Simulation time 155132600 ps
CPU time 0.85 seconds
Started Jul 29 06:11:14 PM PDT 24
Finished Jul 29 06:11:15 PM PDT 24
Peak memory 207068 kb
Host smart-1c52dd3d-c1a6-4b43-8142-968ca33ff004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37825
96563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3782596563
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.2098060581
Short name T517
Test name
Test status
Simulation time 212451532 ps
CPU time 0.97 seconds
Started Jul 29 06:11:19 PM PDT 24
Finished Jul 29 06:11:20 PM PDT 24
Peak memory 207124 kb
Host smart-7b125942-827b-4573-8d9f-adfe97b46321
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2098060581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.2098060581
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.1107625392
Short name T203
Test name
Test status
Simulation time 232210100 ps
CPU time 0.97 seconds
Started Jul 29 06:11:20 PM PDT 24
Finished Jul 29 06:11:21 PM PDT 24
Peak memory 207096 kb
Host smart-1145caac-9c7a-4a24-8156-96fba910945f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11076
25392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.1107625392
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2881743033
Short name T1388
Test name
Test status
Simulation time 141277363 ps
CPU time 0.85 seconds
Started Jul 29 06:11:18 PM PDT 24
Finished Jul 29 06:11:20 PM PDT 24
Peak memory 207088 kb
Host smart-9bc480ac-ee8a-4142-8a4c-baad635d1b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28817
43033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2881743033
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.4222795732
Short name T1699
Test name
Test status
Simulation time 37794528 ps
CPU time 0.7 seconds
Started Jul 29 06:11:20 PM PDT 24
Finished Jul 29 06:11:21 PM PDT 24
Peak memory 207044 kb
Host smart-6baf6021-6086-4e70-b405-93dd04d0bd0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42227
95732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.4222795732
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3734443704
Short name T2376
Test name
Test status
Simulation time 22449023241 ps
CPU time 53.73 seconds
Started Jul 29 06:11:21 PM PDT 24
Finished Jul 29 06:12:15 PM PDT 24
Peak memory 215640 kb
Host smart-632b672c-3fd6-4082-993f-1a6f9b285b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37344
43704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3734443704
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1633251771
Short name T665
Test name
Test status
Simulation time 168194786 ps
CPU time 0.97 seconds
Started Jul 29 06:11:21 PM PDT 24
Finished Jul 29 06:11:22 PM PDT 24
Peak memory 207136 kb
Host smart-ef5b275c-0cce-44d9-8f1e-dac08a3ffe0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16332
51771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1633251771
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1038840025
Short name T1516
Test name
Test status
Simulation time 171246339 ps
CPU time 0.87 seconds
Started Jul 29 06:11:20 PM PDT 24
Finished Jul 29 06:11:22 PM PDT 24
Peak memory 207076 kb
Host smart-3aba8206-c908-4db2-b59b-c0959cc01e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10388
40025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1038840025
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.4197036879
Short name T365
Test name
Test status
Simulation time 12373027989 ps
CPU time 101.64 seconds
Started Jul 29 06:11:19 PM PDT 24
Finished Jul 29 06:13:01 PM PDT 24
Peak memory 223752 kb
Host smart-40558d4f-c14d-4462-8135-a88c87d656a2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197036879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.4197036879
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.787332973
Short name T2656
Test name
Test status
Simulation time 7187227626 ps
CPU time 110.62 seconds
Started Jul 29 06:11:18 PM PDT 24
Finished Jul 29 06:13:09 PM PDT 24
Peak memory 215556 kb
Host smart-48319dc0-7f08-48c0-8182-f7303a4c5e54
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=787332973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.787332973
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.662843126
Short name T2345
Test name
Test status
Simulation time 13581552158 ps
CPU time 303.99 seconds
Started Jul 29 06:11:19 PM PDT 24
Finished Jul 29 06:16:24 PM PDT 24
Peak memory 215632 kb
Host smart-febd6899-8249-41d3-bf8f-1ce890ce6d2b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=662843126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.662843126
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.2305333380
Short name T1117
Test name
Test status
Simulation time 187578317 ps
CPU time 0.89 seconds
Started Jul 29 06:11:18 PM PDT 24
Finished Jul 29 06:11:19 PM PDT 24
Peak memory 207108 kb
Host smart-5a4d9dc8-7071-42f3-a48a-1a8a8cd248f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23053
33380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.2305333380
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.1809438086
Short name T1335
Test name
Test status
Simulation time 202297957 ps
CPU time 0.96 seconds
Started Jul 29 06:11:17 PM PDT 24
Finished Jul 29 06:11:18 PM PDT 24
Peak memory 207104 kb
Host smart-7e69fb89-a4a2-41c2-a558-d9bd01f9db13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18094
38086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.1809438086
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3762413242
Short name T1843
Test name
Test status
Simulation time 182731466 ps
CPU time 0.88 seconds
Started Jul 29 06:11:19 PM PDT 24
Finished Jul 29 06:11:20 PM PDT 24
Peak memory 207084 kb
Host smart-a3addad5-ec38-452a-9bf9-9883eb008b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37624
13242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3762413242
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.645859098
Short name T1331
Test name
Test status
Simulation time 160522292 ps
CPU time 0.88 seconds
Started Jul 29 06:11:21 PM PDT 24
Finished Jul 29 06:11:22 PM PDT 24
Peak memory 207088 kb
Host smart-fb52deda-7318-4785-9ad5-5e97f60e972d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64585
9098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.645859098
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.3116627047
Short name T2223
Test name
Test status
Simulation time 441744809 ps
CPU time 1.42 seconds
Started Jul 29 06:11:23 PM PDT 24
Finished Jul 29 06:11:24 PM PDT 24
Peak memory 207052 kb
Host smart-4e0072f0-d5bd-4984-a514-615bd0faf9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31166
27047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.3116627047
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2447993903
Short name T2709
Test name
Test status
Simulation time 169165833 ps
CPU time 0.92 seconds
Started Jul 29 06:11:23 PM PDT 24
Finished Jul 29 06:11:24 PM PDT 24
Peak memory 207092 kb
Host smart-6dbe60da-f2f5-4e90-8840-1a92e2cc6c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24479
93903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2447993903
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.4113516712
Short name T903
Test name
Test status
Simulation time 237024676 ps
CPU time 0.93 seconds
Started Jul 29 06:11:21 PM PDT 24
Finished Jul 29 06:11:22 PM PDT 24
Peak memory 207104 kb
Host smart-b5a3627a-e711-4ae6-9387-d2c58ecef746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41135
16712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.4113516712
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2160493799
Short name T1320
Test name
Test status
Simulation time 163418080 ps
CPU time 0.89 seconds
Started Jul 29 06:11:21 PM PDT 24
Finished Jul 29 06:11:22 PM PDT 24
Peak memory 207140 kb
Host smart-e2e9583e-da33-4b47-b052-f2ec87fc46e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21604
93799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2160493799
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2032152795
Short name T621
Test name
Test status
Simulation time 272706993 ps
CPU time 1.1 seconds
Started Jul 29 06:11:20 PM PDT 24
Finished Jul 29 06:11:21 PM PDT 24
Peak memory 207088 kb
Host smart-a02e7a9b-5c81-4b80-bdac-92d50cb2a9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20321
52795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2032152795
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.4252822308
Short name T1822
Test name
Test status
Simulation time 5774236807 ps
CPU time 63.59 seconds
Started Jul 29 06:11:23 PM PDT 24
Finished Jul 29 06:12:26 PM PDT 24
Peak memory 217196 kb
Host smart-8c42f1a5-dc59-4c54-bba6-40a91a7c5f45
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4252822308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.4252822308
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3030378115
Short name T991
Test name
Test status
Simulation time 213845407 ps
CPU time 0.95 seconds
Started Jul 29 06:11:21 PM PDT 24
Finished Jul 29 06:11:22 PM PDT 24
Peak memory 207084 kb
Host smart-469f9806-994e-460d-b175-faa332d62122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30303
78115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3030378115
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2045045547
Short name T446
Test name
Test status
Simulation time 178472619 ps
CPU time 0.91 seconds
Started Jul 29 06:11:18 PM PDT 24
Finished Jul 29 06:11:19 PM PDT 24
Peak memory 207264 kb
Host smart-bde6fff9-449b-49c7-ab61-b536a3c6aded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20450
45547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2045045547
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.1283014189
Short name T1889
Test name
Test status
Simulation time 614647605 ps
CPU time 1.66 seconds
Started Jul 29 06:11:18 PM PDT 24
Finished Jul 29 06:11:20 PM PDT 24
Peak memory 207012 kb
Host smart-857b72eb-7e1f-432a-b563-1e5652a0f96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12830
14189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.1283014189
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.1345081752
Short name T2494
Test name
Test status
Simulation time 7754975221 ps
CPU time 233.12 seconds
Started Jul 29 06:11:21 PM PDT 24
Finished Jul 29 06:15:14 PM PDT 24
Peak memory 215592 kb
Host smart-c91c1368-21f7-43f5-a06f-049504264856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13450
81752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.1345081752
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.4140848131
Short name T2204
Test name
Test status
Simulation time 2046204397 ps
CPU time 17.23 seconds
Started Jul 29 06:11:13 PM PDT 24
Finished Jul 29 06:11:30 PM PDT 24
Peak memory 207252 kb
Host smart-e08ec5ae-b071-4599-b3c0-430e4a843979
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140848131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.4140848131
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.3556811898
Short name T2491
Test name
Test status
Simulation time 37430300 ps
CPU time 0.69 seconds
Started Jul 29 06:16:36 PM PDT 24
Finished Jul 29 06:16:37 PM PDT 24
Peak memory 207108 kb
Host smart-0e13c6d5-5eb2-4461-8df9-1e88eebd11b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3556811898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3556811898
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.2904479686
Short name T1774
Test name
Test status
Simulation time 4204246353 ps
CPU time 6.71 seconds
Started Jul 29 06:16:30 PM PDT 24
Finished Jul 29 06:16:36 PM PDT 24
Peak memory 207328 kb
Host smart-0c565957-c433-49c3-a840-389a1eb66f13
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904479686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.2904479686
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.3732118401
Short name T2699
Test name
Test status
Simulation time 13335242120 ps
CPU time 18.07 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:47 PM PDT 24
Peak memory 207408 kb
Host smart-06ae2ee7-d57b-4be5-847b-0e10989bf58f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732118401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.3732118401
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.2571694090
Short name T1773
Test name
Test status
Simulation time 23352688731 ps
CPU time 28.39 seconds
Started Jul 29 06:16:28 PM PDT 24
Finished Jul 29 06:16:57 PM PDT 24
Peak memory 207340 kb
Host smart-c608141f-16a4-41c6-a892-0a010a35192a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571694090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_resume.2571694090
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1150801019
Short name T1706
Test name
Test status
Simulation time 236673998 ps
CPU time 0.94 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:30 PM PDT 24
Peak memory 207084 kb
Host smart-95327ed5-9e11-4942-b0fe-a9495c125148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11508
01019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1150801019
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.2480435489
Short name T588
Test name
Test status
Simulation time 155945790 ps
CPU time 0.84 seconds
Started Jul 29 06:16:31 PM PDT 24
Finished Jul 29 06:16:32 PM PDT 24
Peak memory 207104 kb
Host smart-ac513e82-058c-44ec-b264-650a8cd95514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24804
35489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.2480435489
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3605952373
Short name T729
Test name
Test status
Simulation time 398880329 ps
CPU time 1.4 seconds
Started Jul 29 06:16:28 PM PDT 24
Finished Jul 29 06:16:29 PM PDT 24
Peak memory 207060 kb
Host smart-d894c3d0-ab58-425d-aede-c7d145f9b317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36059
52373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3605952373
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.485557120
Short name T2569
Test name
Test status
Simulation time 991134845 ps
CPU time 2.58 seconds
Started Jul 29 06:16:28 PM PDT 24
Finished Jul 29 06:16:31 PM PDT 24
Peak memory 207288 kb
Host smart-931777b7-e7fe-411a-8c6e-665e74fa82be
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=485557120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.485557120
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.3065881490
Short name T2164
Test name
Test status
Simulation time 15748333047 ps
CPU time 39.25 seconds
Started Jul 29 06:16:30 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 207392 kb
Host smart-457ba65d-4d5d-43ed-90c9-da168d88903c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30658
81490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3065881490
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.1995752431
Short name T1340
Test name
Test status
Simulation time 850600515 ps
CPU time 19.7 seconds
Started Jul 29 06:16:25 PM PDT 24
Finished Jul 29 06:16:45 PM PDT 24
Peak memory 207236 kb
Host smart-34bc4aed-c6d2-402a-ac84-31e1c6998e72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995752431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.1995752431
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3772861568
Short name T1209
Test name
Test status
Simulation time 405305567 ps
CPU time 1.41 seconds
Started Jul 29 06:16:25 PM PDT 24
Finished Jul 29 06:16:26 PM PDT 24
Peak memory 207064 kb
Host smart-c99ec835-3495-4204-8247-5107f069c4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37728
61568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3772861568
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.4104664674
Short name T2861
Test name
Test status
Simulation time 143018346 ps
CPU time 0.85 seconds
Started Jul 29 06:16:31 PM PDT 24
Finished Jul 29 06:16:32 PM PDT 24
Peak memory 207000 kb
Host smart-bb36ae3a-67ab-41f9-a7c2-a442f63a4e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41046
64674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.4104664674
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2571541171
Short name T2547
Test name
Test status
Simulation time 43164397 ps
CPU time 0.72 seconds
Started Jul 29 06:16:30 PM PDT 24
Finished Jul 29 06:16:31 PM PDT 24
Peak memory 207076 kb
Host smart-8f8ab285-d3a9-43c5-b688-766cc4dbc337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25715
41171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2571541171
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.187238200
Short name T1147
Test name
Test status
Simulation time 993383185 ps
CPU time 2.64 seconds
Started Jul 29 06:16:31 PM PDT 24
Finished Jul 29 06:16:34 PM PDT 24
Peak memory 207232 kb
Host smart-bc3d6b33-8350-46f4-bf87-e9aa9cae056e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18723
8200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.187238200
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3065791133
Short name T2550
Test name
Test status
Simulation time 413838287 ps
CPU time 2.83 seconds
Started Jul 29 06:16:34 PM PDT 24
Finished Jul 29 06:16:37 PM PDT 24
Peak memory 207260 kb
Host smart-c7831c58-b282-4735-bddf-171c219f75d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30657
91133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3065791133
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1899097606
Short name T712
Test name
Test status
Simulation time 172323743 ps
CPU time 0.93 seconds
Started Jul 29 06:16:32 PM PDT 24
Finished Jul 29 06:16:33 PM PDT 24
Peak memory 207064 kb
Host smart-6965a888-cfa4-42de-b3e5-8c088ee0ba57
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1899097606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1899097606
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3796981856
Short name T682
Test name
Test status
Simulation time 140590552 ps
CPU time 0.78 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:30 PM PDT 24
Peak memory 207028 kb
Host smart-b03ae0eb-fb72-4060-b9f5-fd4a3ac6db8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37969
81856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3796981856
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1517202065
Short name T1930
Test name
Test status
Simulation time 244859934 ps
CPU time 0.98 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:30 PM PDT 24
Peak memory 207144 kb
Host smart-5a75ca99-90da-482c-a561-4de7048c14bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15172
02065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1517202065
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.4223550925
Short name T442
Test name
Test status
Simulation time 8413117143 ps
CPU time 69.86 seconds
Started Jul 29 06:16:32 PM PDT 24
Finished Jul 29 06:17:42 PM PDT 24
Peak memory 216844 kb
Host smart-28a61db1-a4f9-4257-9638-3ca4555ae605
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4223550925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.4223550925
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.3658054025
Short name T959
Test name
Test status
Simulation time 8819274259 ps
CPU time 56.07 seconds
Started Jul 29 06:16:35 PM PDT 24
Finished Jul 29 06:17:31 PM PDT 24
Peak memory 207404 kb
Host smart-8250b130-1ce4-4a48-ac7c-331f8ff8bd00
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3658054025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.3658054025
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.2933324873
Short name T1713
Test name
Test status
Simulation time 158162296 ps
CPU time 0.88 seconds
Started Jul 29 06:16:33 PM PDT 24
Finished Jul 29 06:16:35 PM PDT 24
Peak memory 206872 kb
Host smart-9061cb09-1b6f-4787-a16a-9a0685ffc02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29333
24873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2933324873
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.331513320
Short name T2239
Test name
Test status
Simulation time 23358100858 ps
CPU time 26.79 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:56 PM PDT 24
Peak memory 207404 kb
Host smart-593f8d72-9296-4f9b-ad50-033587b7c4f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33151
3320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.331513320
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.2215249501
Short name T1206
Test name
Test status
Simulation time 3374121474 ps
CPU time 5.52 seconds
Started Jul 29 06:16:31 PM PDT 24
Finished Jul 29 06:16:37 PM PDT 24
Peak memory 207352 kb
Host smart-cc531eed-e96e-45da-8b0e-12674c699caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22152
49501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.2215249501
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.2844934973
Short name T2828
Test name
Test status
Simulation time 8981207137 ps
CPU time 258.43 seconds
Started Jul 29 06:16:36 PM PDT 24
Finished Jul 29 06:20:55 PM PDT 24
Peak memory 215596 kb
Host smart-ca989878-2278-410c-a08e-126165feacc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28449
34973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.2844934973
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.2288759417
Short name T1582
Test name
Test status
Simulation time 6662480683 ps
CPU time 66.44 seconds
Started Jul 29 06:16:34 PM PDT 24
Finished Jul 29 06:17:41 PM PDT 24
Peak memory 207348 kb
Host smart-9ed4d552-0c21-4066-bfec-4de0b4704a12
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2288759417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.2288759417
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.456051669
Short name T1709
Test name
Test status
Simulation time 276731478 ps
CPU time 0.99 seconds
Started Jul 29 06:16:30 PM PDT 24
Finished Jul 29 06:16:32 PM PDT 24
Peak memory 207180 kb
Host smart-3d07cfd8-7c8f-4dbe-94d0-35199fa34a35
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=456051669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.456051669
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.652130945
Short name T539
Test name
Test status
Simulation time 187144006 ps
CPU time 1.02 seconds
Started Jul 29 06:16:35 PM PDT 24
Finished Jul 29 06:16:36 PM PDT 24
Peak memory 207156 kb
Host smart-a4cb5d82-af52-49d8-a86d-648f4269211f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65213
0945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.652130945
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.3487775849
Short name T316
Test name
Test status
Simulation time 5887543324 ps
CPU time 180.17 seconds
Started Jul 29 06:16:32 PM PDT 24
Finished Jul 29 06:19:32 PM PDT 24
Peak memory 215532 kb
Host smart-cf4cd094-c2a0-4061-8879-ac7125ca6688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34877
75849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.3487775849
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1696893259
Short name T936
Test name
Test status
Simulation time 5042278235 ps
CPU time 140.88 seconds
Started Jul 29 06:16:33 PM PDT 24
Finished Jul 29 06:18:55 PM PDT 24
Peak memory 215316 kb
Host smart-d2684ddd-7e99-450e-927c-983249481923
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1696893259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1696893259
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3518175750
Short name T870
Test name
Test status
Simulation time 150005105 ps
CPU time 0.81 seconds
Started Jul 29 06:16:32 PM PDT 24
Finished Jul 29 06:16:33 PM PDT 24
Peak memory 207076 kb
Host smart-1137a5b4-85a8-4925-8667-b52651225a72
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3518175750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3518175750
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2584427717
Short name T362
Test name
Test status
Simulation time 147103259 ps
CPU time 0.82 seconds
Started Jul 29 06:16:32 PM PDT 24
Finished Jul 29 06:16:33 PM PDT 24
Peak memory 207068 kb
Host smart-864975dd-57f3-4885-86b5-2c794f42416f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25844
27717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2584427717
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1745680531
Short name T137
Test name
Test status
Simulation time 221521009 ps
CPU time 0.98 seconds
Started Jul 29 06:16:35 PM PDT 24
Finished Jul 29 06:16:36 PM PDT 24
Peak memory 207120 kb
Host smart-663167f2-b481-4e3e-954a-d294005aafcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17456
80531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1745680531
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3480903347
Short name T2755
Test name
Test status
Simulation time 179233175 ps
CPU time 0.89 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:30 PM PDT 24
Peak memory 207036 kb
Host smart-46f82852-d0de-4c00-998d-0b81646587d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34809
03347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3480903347
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2951167663
Short name T1138
Test name
Test status
Simulation time 191804167 ps
CPU time 0.92 seconds
Started Jul 29 06:16:31 PM PDT 24
Finished Jul 29 06:16:32 PM PDT 24
Peak memory 207116 kb
Host smart-4be47966-db2c-4edd-b4ee-d2a0aefa4283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29511
67663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2951167663
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3176116480
Short name T417
Test name
Test status
Simulation time 188358539 ps
CPU time 0.93 seconds
Started Jul 29 06:16:29 PM PDT 24
Finished Jul 29 06:16:30 PM PDT 24
Peak memory 207124 kb
Host smart-604f9f17-f18a-4fbe-8f86-87a9e6649405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31761
16480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3176116480
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3782120630
Short name T180
Test name
Test status
Simulation time 168934592 ps
CPU time 0.89 seconds
Started Jul 29 06:16:32 PM PDT 24
Finished Jul 29 06:16:33 PM PDT 24
Peak memory 207116 kb
Host smart-a5ea91fa-4f47-439a-9715-64156cf7d54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37821
20630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3782120630
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.359110032
Short name T1225
Test name
Test status
Simulation time 205323068 ps
CPU time 0.98 seconds
Started Jul 29 06:16:34 PM PDT 24
Finished Jul 29 06:16:35 PM PDT 24
Peak memory 207004 kb
Host smart-fd377da8-76e7-4b35-ac6b-08c5beee7afd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=359110032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.359110032
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.385959362
Short name T502
Test name
Test status
Simulation time 145845766 ps
CPU time 0.86 seconds
Started Jul 29 06:16:32 PM PDT 24
Finished Jul 29 06:16:33 PM PDT 24
Peak memory 207104 kb
Host smart-f7576eee-a1d0-4959-967e-5e466e7f9c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38595
9362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.385959362
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1883516938
Short name T2173
Test name
Test status
Simulation time 33674053 ps
CPU time 0.67 seconds
Started Jul 29 06:16:34 PM PDT 24
Finished Jul 29 06:16:35 PM PDT 24
Peak memory 207072 kb
Host smart-099ce821-8e37-4144-acce-7138b0322658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18835
16938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1883516938
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.781710768
Short name T1969
Test name
Test status
Simulation time 21545859393 ps
CPU time 59.77 seconds
Started Jul 29 06:16:30 PM PDT 24
Finished Jul 29 06:17:30 PM PDT 24
Peak memory 215580 kb
Host smart-4426ce4a-138c-40a7-ad42-56ff5c79f1f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78171
0768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.781710768
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3217943750
Short name T2474
Test name
Test status
Simulation time 192296774 ps
CPU time 0.98 seconds
Started Jul 29 06:16:30 PM PDT 24
Finished Jul 29 06:16:31 PM PDT 24
Peak memory 207104 kb
Host smart-884309f3-e4ba-4d20-b86b-a4d40f9c515e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32179
43750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3217943750
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3201736785
Short name T2539
Test name
Test status
Simulation time 170886804 ps
CPU time 0.88 seconds
Started Jul 29 06:16:31 PM PDT 24
Finished Jul 29 06:16:32 PM PDT 24
Peak memory 207060 kb
Host smart-63657643-768e-4a7e-a84d-0462fce75399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32017
36785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3201736785
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3883918961
Short name T2533
Test name
Test status
Simulation time 236903018 ps
CPU time 1 seconds
Started Jul 29 06:16:31 PM PDT 24
Finished Jul 29 06:16:32 PM PDT 24
Peak memory 207052 kb
Host smart-fdbf4f13-2efa-4ab0-9386-a4c2748c77a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38839
18961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3883918961
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.2063575905
Short name T1514
Test name
Test status
Simulation time 184232457 ps
CPU time 0.98 seconds
Started Jul 29 06:16:32 PM PDT 24
Finished Jul 29 06:16:33 PM PDT 24
Peak memory 207076 kb
Host smart-15a07e28-f72d-470f-abb0-a473498b54c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20635
75905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.2063575905
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2617171191
Short name T1
Test name
Test status
Simulation time 157346531 ps
CPU time 0.89 seconds
Started Jul 29 06:16:31 PM PDT 24
Finished Jul 29 06:16:32 PM PDT 24
Peak memory 207116 kb
Host smart-e563c1f8-7f25-4cff-998f-4696696b3708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26171
71191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2617171191
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1758586963
Short name T2730
Test name
Test status
Simulation time 142730596 ps
CPU time 0.82 seconds
Started Jul 29 06:16:32 PM PDT 24
Finished Jul 29 06:16:33 PM PDT 24
Peak memory 207016 kb
Host smart-6687795a-9f4a-444b-af28-cd4c9fbc5a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17585
86963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1758586963
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2653632836
Short name T54
Test name
Test status
Simulation time 158630261 ps
CPU time 0.82 seconds
Started Jul 29 06:16:30 PM PDT 24
Finished Jul 29 06:16:31 PM PDT 24
Peak memory 207072 kb
Host smart-58d769cd-ec71-4299-a765-967713d25983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26536
32836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2653632836
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1070728020
Short name T1017
Test name
Test status
Simulation time 183734821 ps
CPU time 0.87 seconds
Started Jul 29 06:16:34 PM PDT 24
Finished Jul 29 06:16:35 PM PDT 24
Peak memory 206980 kb
Host smart-440ffe6d-b628-4408-9313-997497e13fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10707
28020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1070728020
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2489142218
Short name T2858
Test name
Test status
Simulation time 5259470889 ps
CPU time 56.3 seconds
Started Jul 29 06:16:40 PM PDT 24
Finished Jul 29 06:17:36 PM PDT 24
Peak memory 217132 kb
Host smart-6898a8f5-860f-4cbb-990a-2071dcc95f23
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2489142218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2489142218
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2130161328
Short name T2359
Test name
Test status
Simulation time 165401923 ps
CPU time 0.93 seconds
Started Jul 29 06:16:37 PM PDT 24
Finished Jul 29 06:16:38 PM PDT 24
Peak memory 207116 kb
Host smart-271946b4-f921-41c4-a028-20b6482747da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21301
61328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2130161328
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3194897899
Short name T1464
Test name
Test status
Simulation time 204115280 ps
CPU time 0.9 seconds
Started Jul 29 06:16:38 PM PDT 24
Finished Jul 29 06:16:39 PM PDT 24
Peak memory 207104 kb
Host smart-8ab64e98-83aa-4438-86d2-45171d87fba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31948
97899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3194897899
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.3214526392
Short name T2105
Test name
Test status
Simulation time 687253183 ps
CPU time 1.78 seconds
Started Jul 29 06:16:37 PM PDT 24
Finished Jul 29 06:16:39 PM PDT 24
Peak memory 207076 kb
Host smart-0c847212-99d8-44e1-b8e6-f723c6872138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32145
26392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3214526392
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.2917996447
Short name T1922
Test name
Test status
Simulation time 4536730092 ps
CPU time 33.78 seconds
Started Jul 29 06:16:36 PM PDT 24
Finished Jul 29 06:17:10 PM PDT 24
Peak memory 207352 kb
Host smart-034e3038-6316-4fac-ba2b-10c64951860f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29179
96447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2917996447
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.4122902689
Short name T674
Test name
Test status
Simulation time 929720160 ps
CPU time 19.38 seconds
Started Jul 29 06:16:30 PM PDT 24
Finished Jul 29 06:16:50 PM PDT 24
Peak memory 207308 kb
Host smart-c4fb0422-f3e4-4d5b-9b55-d52c152dcb02
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122902689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.4122902689
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.51414665
Short name T1974
Test name
Test status
Simulation time 42669148 ps
CPU time 0.71 seconds
Started Jul 29 06:16:43 PM PDT 24
Finished Jul 29 06:16:44 PM PDT 24
Peak memory 207152 kb
Host smart-0ef69167-b238-4c48-9986-4259ec87d658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=51414665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.51414665
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.1219566452
Short name T945
Test name
Test status
Simulation time 3760062320 ps
CPU time 5.64 seconds
Started Jul 29 06:16:39 PM PDT 24
Finished Jul 29 06:16:45 PM PDT 24
Peak memory 207360 kb
Host smart-da4ab5f1-594f-4ed0-96cb-b376a6ec5a1a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219566452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.1219566452
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2697271389
Short name T1205
Test name
Test status
Simulation time 13494109666 ps
CPU time 17.97 seconds
Started Jul 29 06:16:37 PM PDT 24
Finished Jul 29 06:16:55 PM PDT 24
Peak memory 207432 kb
Host smart-182c06a2-bcba-4d2f-9b76-74bf11dc0f95
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697271389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2697271389
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3517637196
Short name T2579
Test name
Test status
Simulation time 23364702536 ps
CPU time 31.95 seconds
Started Jul 29 06:16:36 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 207424 kb
Host smart-fbda0995-cfe9-4d3d-aec3-2fdcc30a65e8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517637196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.3517637196
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.4094462216
Short name T1474
Test name
Test status
Simulation time 196099019 ps
CPU time 0.88 seconds
Started Jul 29 06:16:38 PM PDT 24
Finished Jul 29 06:16:39 PM PDT 24
Peak memory 207084 kb
Host smart-5ba1a367-f476-4fe7-a4d1-87362661e1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40944
62216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.4094462216
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.3960567125
Short name T2151
Test name
Test status
Simulation time 147997238 ps
CPU time 0.87 seconds
Started Jul 29 06:16:39 PM PDT 24
Finished Jul 29 06:16:39 PM PDT 24
Peak memory 207064 kb
Host smart-c00663e1-b2fc-438f-8593-5c1808f5850d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39605
67125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3960567125
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.1357983033
Short name T915
Test name
Test status
Simulation time 151410183 ps
CPU time 0.9 seconds
Started Jul 29 06:16:42 PM PDT 24
Finished Jul 29 06:16:43 PM PDT 24
Peak memory 207072 kb
Host smart-1f401fed-fd57-4d97-9211-b02863a67175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13579
83033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.1357983033
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3003507142
Short name T914
Test name
Test status
Simulation time 1111510907 ps
CPU time 3.24 seconds
Started Jul 29 06:16:37 PM PDT 24
Finished Jul 29 06:16:40 PM PDT 24
Peak memory 207376 kb
Host smart-b0227c41-f9ed-4d28-9f52-53cb00ff1843
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3003507142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3003507142
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.4009999801
Short name T2677
Test name
Test status
Simulation time 10188067754 ps
CPU time 22.32 seconds
Started Jul 29 06:16:38 PM PDT 24
Finished Jul 29 06:17:00 PM PDT 24
Peak memory 207432 kb
Host smart-5e4ccaef-7df2-44e8-924e-0ff218687d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40099
99801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.4009999801
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.1916975893
Short name T2293
Test name
Test status
Simulation time 474173225 ps
CPU time 8.31 seconds
Started Jul 29 06:16:38 PM PDT 24
Finished Jul 29 06:16:47 PM PDT 24
Peak memory 207272 kb
Host smart-4bd3fd4f-1ec4-4898-9e72-3504ab27859c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916975893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.1916975893
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.2284355966
Short name T1646
Test name
Test status
Simulation time 588288004 ps
CPU time 1.71 seconds
Started Jul 29 06:16:40 PM PDT 24
Finished Jul 29 06:16:42 PM PDT 24
Peak memory 207192 kb
Host smart-c5b8b0e7-5c77-4ce6-adf6-15b0bd137d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22843
55966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.2284355966
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3293243608
Short name T1772
Test name
Test status
Simulation time 174967458 ps
CPU time 0.9 seconds
Started Jul 29 06:16:39 PM PDT 24
Finished Jul 29 06:16:40 PM PDT 24
Peak memory 207180 kb
Host smart-83b418ef-3f2b-4335-b393-e87983221b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32932
43608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3293243608
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1757522583
Short name T784
Test name
Test status
Simulation time 47917625 ps
CPU time 0.69 seconds
Started Jul 29 06:16:37 PM PDT 24
Finished Jul 29 06:16:38 PM PDT 24
Peak memory 206964 kb
Host smart-232e8138-5a76-4af5-801e-eafbca87512c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17575
22583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1757522583
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2730460796
Short name T1137
Test name
Test status
Simulation time 882577601 ps
CPU time 2.44 seconds
Started Jul 29 06:16:36 PM PDT 24
Finished Jul 29 06:16:39 PM PDT 24
Peak memory 207204 kb
Host smart-79951561-4812-41b7-9085-ce55658e830c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27304
60796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2730460796
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.701735190
Short name T182
Test name
Test status
Simulation time 245928289 ps
CPU time 2.02 seconds
Started Jul 29 06:16:38 PM PDT 24
Finished Jul 29 06:16:41 PM PDT 24
Peak memory 207312 kb
Host smart-382f6dcc-e24a-4202-acf1-70b641d9d0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70173
5190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.701735190
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1130418551
Short name T1148
Test name
Test status
Simulation time 221238319 ps
CPU time 1.18 seconds
Started Jul 29 06:16:38 PM PDT 24
Finished Jul 29 06:16:40 PM PDT 24
Peak memory 207316 kb
Host smart-ac12e42c-4892-43a4-a791-d8fc6af3be94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1130418551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1130418551
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1683793149
Short name T379
Test name
Test status
Simulation time 141419245 ps
CPU time 0.8 seconds
Started Jul 29 06:16:40 PM PDT 24
Finished Jul 29 06:16:41 PM PDT 24
Peak memory 207052 kb
Host smart-e09f395f-8270-4ba9-bded-6e59b6e06735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16837
93149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1683793149
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3090495490
Short name T786
Test name
Test status
Simulation time 198690642 ps
CPU time 0.94 seconds
Started Jul 29 06:16:39 PM PDT 24
Finished Jul 29 06:16:41 PM PDT 24
Peak memory 207116 kb
Host smart-4f3999e2-ed26-406e-b219-98dc83f8104a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30904
95490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3090495490
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.1821871820
Short name T2167
Test name
Test status
Simulation time 6199482796 ps
CPU time 47.49 seconds
Started Jul 29 06:16:37 PM PDT 24
Finished Jul 29 06:17:25 PM PDT 24
Peak memory 217108 kb
Host smart-05fb84ff-6bec-416f-8620-48229b0d625a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1821871820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.1821871820
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.432246087
Short name T1130
Test name
Test status
Simulation time 212870441 ps
CPU time 0.99 seconds
Started Jul 29 06:16:42 PM PDT 24
Finished Jul 29 06:16:43 PM PDT 24
Peak memory 207084 kb
Host smart-cabb4671-db6b-412e-874c-4b74c874240b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43224
6087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.432246087
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.390823239
Short name T1791
Test name
Test status
Simulation time 23305708491 ps
CPU time 27.63 seconds
Started Jul 29 06:16:43 PM PDT 24
Finished Jul 29 06:17:11 PM PDT 24
Peak memory 207436 kb
Host smart-ffe7daef-a47a-4b7a-af05-39605e33008c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39082
3239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.390823239
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2253176917
Short name T2628
Test name
Test status
Simulation time 3301798264 ps
CPU time 4.79 seconds
Started Jul 29 06:16:40 PM PDT 24
Finished Jul 29 06:16:45 PM PDT 24
Peak memory 207248 kb
Host smart-101d350b-486c-4b46-a29a-61c619aa3ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22531
76917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2253176917
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.3610214227
Short name T1171
Test name
Test status
Simulation time 8909957668 ps
CPU time 93.27 seconds
Started Jul 29 06:16:43 PM PDT 24
Finished Jul 29 06:18:16 PM PDT 24
Peak memory 223764 kb
Host smart-b2a14403-d181-488b-950e-70667c928f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36102
14227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.3610214227
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.251044725
Short name T622
Test name
Test status
Simulation time 6917932865 ps
CPU time 201.49 seconds
Started Jul 29 06:16:47 PM PDT 24
Finished Jul 29 06:20:09 PM PDT 24
Peak memory 215560 kb
Host smart-93612ecf-bf8c-49e4-a26e-49d99e3fe8c1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=251044725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.251044725
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.3651828578
Short name T2464
Test name
Test status
Simulation time 239428838 ps
CPU time 1.06 seconds
Started Jul 29 06:16:43 PM PDT 24
Finished Jul 29 06:16:44 PM PDT 24
Peak memory 207076 kb
Host smart-4600f4c3-d3d5-435e-9c7b-ef56629e25d5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3651828578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.3651828578
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1753631823
Short name T889
Test name
Test status
Simulation time 191693406 ps
CPU time 0.99 seconds
Started Jul 29 06:16:42 PM PDT 24
Finished Jul 29 06:16:44 PM PDT 24
Peak memory 207132 kb
Host smart-71576c73-63c7-40db-bcc3-b374fb5690cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17536
31823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1753631823
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.3972738147
Short name T744
Test name
Test status
Simulation time 3875527921 ps
CPU time 118.56 seconds
Started Jul 29 06:16:42 PM PDT 24
Finished Jul 29 06:18:40 PM PDT 24
Peak memory 215516 kb
Host smart-9824ce8d-7c59-42c8-8e45-06dcf910a560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39727
38147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.3972738147
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3095258559
Short name T1840
Test name
Test status
Simulation time 5079236978 ps
CPU time 150.81 seconds
Started Jul 29 06:16:44 PM PDT 24
Finished Jul 29 06:19:15 PM PDT 24
Peak memory 215584 kb
Host smart-0ded0a62-fc22-434b-bdb3-2f154a0c5068
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3095258559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3095258559
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.2962222224
Short name T2328
Test name
Test status
Simulation time 160558118 ps
CPU time 0.87 seconds
Started Jul 29 06:16:44 PM PDT 24
Finished Jul 29 06:16:45 PM PDT 24
Peak memory 207104 kb
Host smart-0e488f88-2a2f-41e0-aee0-a737004bbd2a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2962222224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.2962222224
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1913958027
Short name T1826
Test name
Test status
Simulation time 145012999 ps
CPU time 0.9 seconds
Started Jul 29 06:16:42 PM PDT 24
Finished Jul 29 06:16:43 PM PDT 24
Peak memory 207144 kb
Host smart-c69aa96e-2ca6-4639-8332-dba88b4d3f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19139
58027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1913958027
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1915502135
Short name T2227
Test name
Test status
Simulation time 252806378 ps
CPU time 1.01 seconds
Started Jul 29 06:16:45 PM PDT 24
Finished Jul 29 06:16:46 PM PDT 24
Peak memory 207108 kb
Host smart-9951c03a-8ad2-48fe-880c-84ac4b72954b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19155
02135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1915502135
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3945386877
Short name T451
Test name
Test status
Simulation time 170973141 ps
CPU time 0.95 seconds
Started Jul 29 06:16:42 PM PDT 24
Finished Jul 29 06:16:43 PM PDT 24
Peak memory 207072 kb
Host smart-36c91076-8860-4512-bcb8-0543097a1b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39453
86877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3945386877
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.823240916
Short name T1319
Test name
Test status
Simulation time 180106308 ps
CPU time 0.96 seconds
Started Jul 29 06:16:44 PM PDT 24
Finished Jul 29 06:16:46 PM PDT 24
Peak memory 207032 kb
Host smart-ec930f50-b8c7-41bc-9718-dbede8ab23e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82324
0916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.823240916
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3359990085
Short name T2775
Test name
Test status
Simulation time 156413698 ps
CPU time 0.81 seconds
Started Jul 29 06:16:44 PM PDT 24
Finished Jul 29 06:16:45 PM PDT 24
Peak memory 207032 kb
Host smart-cf7aa9bb-a66c-4450-b4d7-4d63e3f9d2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33599
90085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3359990085
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3022962795
Short name T2118
Test name
Test status
Simulation time 157881824 ps
CPU time 0.91 seconds
Started Jul 29 06:16:45 PM PDT 24
Finished Jul 29 06:16:46 PM PDT 24
Peak memory 207104 kb
Host smart-1c31ae77-5835-4627-abea-a205d9019b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30229
62795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3022962795
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.806980578
Short name T2707
Test name
Test status
Simulation time 249708705 ps
CPU time 1.04 seconds
Started Jul 29 06:16:50 PM PDT 24
Finished Jul 29 06:16:51 PM PDT 24
Peak memory 207096 kb
Host smart-7109ff3b-11f2-4542-be92-ae574132b07e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=806980578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.806980578
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1939432156
Short name T584
Test name
Test status
Simulation time 160537598 ps
CPU time 0.86 seconds
Started Jul 29 06:16:41 PM PDT 24
Finished Jul 29 06:16:42 PM PDT 24
Peak memory 207068 kb
Host smart-f77fd82c-9727-4024-9dbb-db6c875d017d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19394
32156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1939432156
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.803921004
Short name T2370
Test name
Test status
Simulation time 45959533 ps
CPU time 0.69 seconds
Started Jul 29 06:16:45 PM PDT 24
Finished Jul 29 06:16:46 PM PDT 24
Peak memory 207040 kb
Host smart-4505d5ff-54e3-4f12-af96-ef980d7c2f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80392
1004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.803921004
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.4140278106
Short name T1968
Test name
Test status
Simulation time 6196363296 ps
CPU time 15.95 seconds
Started Jul 29 06:16:45 PM PDT 24
Finished Jul 29 06:17:01 PM PDT 24
Peak memory 215704 kb
Host smart-a33a0bb2-f1ec-4479-a559-9c3bd2b28468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41402
78106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.4140278106
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.472203646
Short name T559
Test name
Test status
Simulation time 165278842 ps
CPU time 0.86 seconds
Started Jul 29 06:16:41 PM PDT 24
Finished Jul 29 06:16:42 PM PDT 24
Peak memory 207052 kb
Host smart-2f5c47e9-3d24-452b-a663-dae2670019c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47220
3646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.472203646
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.479495019
Short name T2140
Test name
Test status
Simulation time 252423383 ps
CPU time 1.01 seconds
Started Jul 29 06:16:42 PM PDT 24
Finished Jul 29 06:16:43 PM PDT 24
Peak memory 207112 kb
Host smart-b5092b6b-87a7-4817-ba13-c2abfcc18cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47949
5019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.479495019
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2549544654
Short name T1475
Test name
Test status
Simulation time 217028939 ps
CPU time 1.07 seconds
Started Jul 29 06:16:43 PM PDT 24
Finished Jul 29 06:16:45 PM PDT 24
Peak memory 207108 kb
Host smart-f3646954-9f50-47ff-ad9f-148a6bea6664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25495
44654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2549544654
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.2021392674
Short name T1419
Test name
Test status
Simulation time 250531538 ps
CPU time 1.08 seconds
Started Jul 29 06:16:43 PM PDT 24
Finished Jul 29 06:16:45 PM PDT 24
Peak memory 207104 kb
Host smart-9bd3c166-06f8-44a6-ae4d-fdae1ac0bb92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20213
92674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.2021392674
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.4015967144
Short name T1876
Test name
Test status
Simulation time 173585333 ps
CPU time 0.9 seconds
Started Jul 29 06:16:44 PM PDT 24
Finished Jul 29 06:16:45 PM PDT 24
Peak memory 207000 kb
Host smart-b4ed62ce-3ce4-40fe-99b3-04abffa2dffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40159
67144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.4015967144
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.4209512989
Short name T2688
Test name
Test status
Simulation time 214930396 ps
CPU time 0.93 seconds
Started Jul 29 06:16:48 PM PDT 24
Finished Jul 29 06:16:49 PM PDT 24
Peak memory 207032 kb
Host smart-39a634f0-5645-4689-ac0b-dd5c66516c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42095
12989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.4209512989
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3643364217
Short name T2089
Test name
Test status
Simulation time 154517643 ps
CPU time 0.93 seconds
Started Jul 29 06:16:44 PM PDT 24
Finished Jul 29 06:16:45 PM PDT 24
Peak memory 207104 kb
Host smart-b0c8e5de-0ca5-40f0-a432-69a5fa66c7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36433
64217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3643364217
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2920244304
Short name T460
Test name
Test status
Simulation time 234992321 ps
CPU time 1.12 seconds
Started Jul 29 06:16:43 PM PDT 24
Finished Jul 29 06:16:44 PM PDT 24
Peak memory 207064 kb
Host smart-7beca8e9-a6d7-440b-bed4-1f898ba46b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29202
44304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2920244304
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.348931065
Short name T971
Test name
Test status
Simulation time 6314162982 ps
CPU time 192.13 seconds
Started Jul 29 06:16:48 PM PDT 24
Finished Jul 29 06:20:00 PM PDT 24
Peak memory 215568 kb
Host smart-2e886b47-4790-4565-908a-56efa5606fc7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=348931065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.348931065
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2706127993
Short name T2271
Test name
Test status
Simulation time 161019611 ps
CPU time 0.84 seconds
Started Jul 29 06:16:48 PM PDT 24
Finished Jul 29 06:16:49 PM PDT 24
Peak memory 207072 kb
Host smart-659014db-e2f7-45e4-96ab-97def514d622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27061
27993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2706127993
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1333458461
Short name T441
Test name
Test status
Simulation time 157011598 ps
CPU time 0.86 seconds
Started Jul 29 06:16:49 PM PDT 24
Finished Jul 29 06:16:50 PM PDT 24
Peak memory 207092 kb
Host smart-3d47ee3f-6153-455b-a575-04f9954d6a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13334
58461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1333458461
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2304658550
Short name T1665
Test name
Test status
Simulation time 506617728 ps
CPU time 1.52 seconds
Started Jul 29 06:16:44 PM PDT 24
Finished Jul 29 06:16:46 PM PDT 24
Peak memory 206952 kb
Host smart-8ec850f3-65c9-473f-983d-394194cf90ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23046
58550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2304658550
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1692788987
Short name T2193
Test name
Test status
Simulation time 3863687148 ps
CPU time 31.38 seconds
Started Jul 29 06:16:47 PM PDT 24
Finished Jul 29 06:17:19 PM PDT 24
Peak memory 216964 kb
Host smart-5fc3294f-c924-4276-8b62-bc82f4e17176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16927
88987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1692788987
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.68730718
Short name T2029
Test name
Test status
Simulation time 1318683034 ps
CPU time 30.17 seconds
Started Jul 29 06:16:38 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 207324 kb
Host smart-33cf0086-a222-4bd4-910c-8176a5d2b47b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68730718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_host_
handshake.68730718
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.1969114115
Short name T2702
Test name
Test status
Simulation time 51232342 ps
CPU time 0.69 seconds
Started Jul 29 06:17:00 PM PDT 24
Finished Jul 29 06:17:01 PM PDT 24
Peak memory 207112 kb
Host smart-e31e223d-557f-4e2f-b289-e06031fc3017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1969114115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.1969114115
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2249798042
Short name T2589
Test name
Test status
Simulation time 3896763807 ps
CPU time 5.71 seconds
Started Jul 29 06:16:49 PM PDT 24
Finished Jul 29 06:16:55 PM PDT 24
Peak memory 207348 kb
Host smart-3efd24a8-814c-47e1-a281-f0edf3f2fef1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249798042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.2249798042
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.2874247919
Short name T1245
Test name
Test status
Simulation time 13336948689 ps
CPU time 15.39 seconds
Started Jul 29 06:16:52 PM PDT 24
Finished Jul 29 06:17:08 PM PDT 24
Peak memory 207072 kb
Host smart-a88e47d9-96dd-41a4-a863-34d33d745801
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874247919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2874247919
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3556349019
Short name T1720
Test name
Test status
Simulation time 23392575373 ps
CPU time 28.32 seconds
Started Jul 29 06:16:47 PM PDT 24
Finished Jul 29 06:17:16 PM PDT 24
Peak memory 207424 kb
Host smart-1e0668fa-93e7-4bf6-aeb4-f3ae1da4b19d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556349019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.3556349019
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2436028448
Short name T2632
Test name
Test status
Simulation time 153451000 ps
CPU time 0.89 seconds
Started Jul 29 06:16:45 PM PDT 24
Finished Jul 29 06:16:46 PM PDT 24
Peak memory 207064 kb
Host smart-4bc2f1fe-5c37-4a6a-bbd7-a7dcfd7f7d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24360
28448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2436028448
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.3712546943
Short name T335
Test name
Test status
Simulation time 197247783 ps
CPU time 0.94 seconds
Started Jul 29 06:16:47 PM PDT 24
Finished Jul 29 06:16:49 PM PDT 24
Peak memory 207068 kb
Host smart-fabee7a5-c982-47bf-ad82-dd6134d1286e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37125
46943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.3712546943
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1892628608
Short name T2687
Test name
Test status
Simulation time 229612471 ps
CPU time 1.12 seconds
Started Jul 29 06:16:52 PM PDT 24
Finished Jul 29 06:16:53 PM PDT 24
Peak memory 207232 kb
Host smart-7acd28a3-6963-494e-af81-011c9be359cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18926
28608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1892628608
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3107437643
Short name T476
Test name
Test status
Simulation time 1533433026 ps
CPU time 3.69 seconds
Started Jul 29 06:16:52 PM PDT 24
Finished Jul 29 06:16:56 PM PDT 24
Peak memory 207412 kb
Host smart-dcfd9885-ccc0-4536-b2d2-5c65fc39d3ff
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3107437643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3107437643
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.4182100072
Short name T2525
Test name
Test status
Simulation time 8371923129 ps
CPU time 18.25 seconds
Started Jul 29 06:16:46 PM PDT 24
Finished Jul 29 06:17:05 PM PDT 24
Peak memory 207420 kb
Host smart-01716cbb-554e-4200-9cae-079b8a18c6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41821
00072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.4182100072
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.3536185777
Short name T976
Test name
Test status
Simulation time 636050110 ps
CPU time 5.68 seconds
Started Jul 29 06:16:51 PM PDT 24
Finished Jul 29 06:16:56 PM PDT 24
Peak memory 206560 kb
Host smart-0137ff78-3d43-4c20-b848-3dc670b016e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536185777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.3536185777
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.212364710
Short name T1289
Test name
Test status
Simulation time 453166184 ps
CPU time 1.52 seconds
Started Jul 29 06:16:52 PM PDT 24
Finished Jul 29 06:16:54 PM PDT 24
Peak memory 207108 kb
Host smart-0f547e44-a2e7-4e0a-8461-9c6d0d2e47b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21236
4710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.212364710
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3476665466
Short name T1287
Test name
Test status
Simulation time 164615015 ps
CPU time 0.9 seconds
Started Jul 29 06:16:51 PM PDT 24
Finished Jul 29 06:16:52 PM PDT 24
Peak memory 206364 kb
Host smart-995cd051-b8c7-4f3d-9959-b357be68f239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34766
65466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3476665466
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2497269366
Short name T1279
Test name
Test status
Simulation time 64404897 ps
CPU time 0.72 seconds
Started Jul 29 06:16:45 PM PDT 24
Finished Jul 29 06:16:46 PM PDT 24
Peak memory 206964 kb
Host smart-8b2fbb0f-1527-40b4-bac4-206aa79b5a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24972
69366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2497269366
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3161720234
Short name T1055
Test name
Test status
Simulation time 764072929 ps
CPU time 2.09 seconds
Started Jul 29 06:16:52 PM PDT 24
Finished Jul 29 06:16:54 PM PDT 24
Peak memory 207000 kb
Host smart-1a9d341d-d1f5-43ae-b92d-d3a13f9da060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31617
20234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3161720234
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.755121907
Short name T2051
Test name
Test status
Simulation time 171269600 ps
CPU time 1.84 seconds
Started Jul 29 06:16:46 PM PDT 24
Finished Jul 29 06:16:49 PM PDT 24
Peak memory 207256 kb
Host smart-c04e4836-2cb7-4ad3-8725-d5c38d08860b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75512
1907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.755121907
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2669831494
Short name T1690
Test name
Test status
Simulation time 171472074 ps
CPU time 0.97 seconds
Started Jul 29 06:16:47 PM PDT 24
Finished Jul 29 06:16:48 PM PDT 24
Peak memory 207128 kb
Host smart-17ff9596-5b66-49a1-8d4c-b0029100ca2f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2669831494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2669831494
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.604263286
Short name T2691
Test name
Test status
Simulation time 148563913 ps
CPU time 0.84 seconds
Started Jul 29 06:16:50 PM PDT 24
Finished Jul 29 06:16:51 PM PDT 24
Peak memory 207044 kb
Host smart-2b972c22-554e-4bc1-8b25-d37c97feb7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60426
3286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.604263286
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2334525178
Short name T754
Test name
Test status
Simulation time 239637901 ps
CPU time 1.05 seconds
Started Jul 29 06:16:47 PM PDT 24
Finished Jul 29 06:16:48 PM PDT 24
Peak memory 207124 kb
Host smart-69fc0f9d-ef13-490f-b269-0f0c11083445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23345
25178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2334525178
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.1823020460
Short name T690
Test name
Test status
Simulation time 9077548639 ps
CPU time 71.6 seconds
Started Jul 29 06:16:52 PM PDT 24
Finished Jul 29 06:18:04 PM PDT 24
Peak memory 216892 kb
Host smart-16f5af9f-9c9e-4f7f-8817-019a99b32fce
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1823020460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1823020460
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.145166222
Short name T1945
Test name
Test status
Simulation time 11575248904 ps
CPU time 78.91 seconds
Started Jul 29 06:16:54 PM PDT 24
Finished Jul 29 06:18:13 PM PDT 24
Peak memory 207416 kb
Host smart-67f41625-2d0b-421a-85ee-4a6526439a35
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=145166222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.145166222
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1288135491
Short name T65
Test name
Test status
Simulation time 171870371 ps
CPU time 0.9 seconds
Started Jul 29 06:16:47 PM PDT 24
Finished Jul 29 06:16:48 PM PDT 24
Peak memory 207268 kb
Host smart-f027bcbd-57ea-439c-9e37-845a459557d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12881
35491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1288135491
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.1072831103
Short name T981
Test name
Test status
Simulation time 23325615793 ps
CPU time 27.87 seconds
Started Jul 29 06:16:50 PM PDT 24
Finished Jul 29 06:17:18 PM PDT 24
Peak memory 207428 kb
Host smart-e290c2e8-db25-4241-99a4-3db685998ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10728
31103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.1072831103
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.4251130402
Short name T1226
Test name
Test status
Simulation time 3279892130 ps
CPU time 5.05 seconds
Started Jul 29 06:16:50 PM PDT 24
Finished Jul 29 06:16:56 PM PDT 24
Peak memory 207312 kb
Host smart-a95977c0-88d2-4690-945a-068fb51209d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42511
30402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.4251130402
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.698402351
Short name T2852
Test name
Test status
Simulation time 8442236471 ps
CPU time 87.3 seconds
Started Jul 29 06:16:50 PM PDT 24
Finished Jul 29 06:18:17 PM PDT 24
Peak memory 218388 kb
Host smart-98c19dde-f410-46d9-8df1-eb98d6a9b4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69840
2351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.698402351
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.1478862293
Short name T1908
Test name
Test status
Simulation time 4488559387 ps
CPU time 130.37 seconds
Started Jul 29 06:16:53 PM PDT 24
Finished Jul 29 06:19:04 PM PDT 24
Peak memory 215568 kb
Host smart-cdce4571-d184-49d3-a3d2-d30aad9183e0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1478862293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.1478862293
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1784870029
Short name T1243
Test name
Test status
Simulation time 241629135 ps
CPU time 1 seconds
Started Jul 29 06:16:54 PM PDT 24
Finished Jul 29 06:16:55 PM PDT 24
Peak memory 207112 kb
Host smart-189545e7-8eef-40a2-9b9c-b76193a52b17
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1784870029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1784870029
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1357149968
Short name T1191
Test name
Test status
Simulation time 200656783 ps
CPU time 0.91 seconds
Started Jul 29 06:16:57 PM PDT 24
Finished Jul 29 06:16:58 PM PDT 24
Peak memory 207060 kb
Host smart-f950fe9b-7836-46a0-9830-689af022c67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13571
49968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1357149968
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.2772160200
Short name T595
Test name
Test status
Simulation time 5084324994 ps
CPU time 157.59 seconds
Started Jul 29 06:16:57 PM PDT 24
Finished Jul 29 06:19:35 PM PDT 24
Peak memory 215528 kb
Host smart-2eb7f90b-afb0-4691-8cc5-51d1fc9e8b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27721
60200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.2772160200
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.3738066870
Short name T808
Test name
Test status
Simulation time 6581257073 ps
CPU time 50.16 seconds
Started Jul 29 06:16:52 PM PDT 24
Finished Jul 29 06:17:43 PM PDT 24
Peak memory 207412 kb
Host smart-28bfb604-a951-4923-aa9d-19c5908ca8c6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3738066870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.3738066870
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3752892884
Short name T1995
Test name
Test status
Simulation time 174850082 ps
CPU time 0.86 seconds
Started Jul 29 06:16:54 PM PDT 24
Finished Jul 29 06:16:55 PM PDT 24
Peak memory 207076 kb
Host smart-1b86a423-9995-4a0f-8aaa-b50409a77786
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3752892884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3752892884
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1015228896
Short name T372
Test name
Test status
Simulation time 217026059 ps
CPU time 0.98 seconds
Started Jul 29 06:16:51 PM PDT 24
Finished Jul 29 06:16:53 PM PDT 24
Peak memory 207124 kb
Host smart-0894ca74-4890-472b-8ee1-b5b8c34b035b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10152
28896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1015228896
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2892811982
Short name T130
Test name
Test status
Simulation time 203875455 ps
CPU time 1.01 seconds
Started Jul 29 06:16:53 PM PDT 24
Finished Jul 29 06:16:54 PM PDT 24
Peak memory 207044 kb
Host smart-5fb75878-8a96-4201-82c8-f2abc60faf43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28928
11982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2892811982
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3278272024
Short name T2180
Test name
Test status
Simulation time 198392376 ps
CPU time 0.98 seconds
Started Jul 29 06:16:54 PM PDT 24
Finished Jul 29 06:16:55 PM PDT 24
Peak memory 207056 kb
Host smart-91d99fe5-e723-49ed-aefb-6603a0c4a2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32782
72024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3278272024
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3578526166
Short name T1400
Test name
Test status
Simulation time 186190340 ps
CPU time 0.91 seconds
Started Jul 29 06:16:53 PM PDT 24
Finished Jul 29 06:16:54 PM PDT 24
Peak memory 207104 kb
Host smart-57a41597-5c17-4481-a3cc-8cc54f64fde3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35785
26166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3578526166
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2968697806
Short name T1570
Test name
Test status
Simulation time 158810446 ps
CPU time 0.86 seconds
Started Jul 29 06:16:53 PM PDT 24
Finished Jul 29 06:16:54 PM PDT 24
Peak memory 207080 kb
Host smart-62ffa684-5e50-449f-8b8c-7ad6df216106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29686
97806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2968697806
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.4005728619
Short name T1002
Test name
Test status
Simulation time 178211506 ps
CPU time 0.9 seconds
Started Jul 29 06:16:52 PM PDT 24
Finished Jul 29 06:16:53 PM PDT 24
Peak memory 207100 kb
Host smart-a8231fc3-dad2-4d09-962d-76d1b73765d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40057
28619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.4005728619
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2011487585
Short name T905
Test name
Test status
Simulation time 237228538 ps
CPU time 1.04 seconds
Started Jul 29 06:16:51 PM PDT 24
Finished Jul 29 06:16:53 PM PDT 24
Peak memory 207116 kb
Host smart-b43cbeef-3539-43e9-9fd1-89ab06e84236
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2011487585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2011487585
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2763149619
Short name T962
Test name
Test status
Simulation time 139414899 ps
CPU time 0.87 seconds
Started Jul 29 06:16:53 PM PDT 24
Finished Jul 29 06:16:54 PM PDT 24
Peak memory 207068 kb
Host smart-47ca20c9-260b-4f75-a831-6dbc2ca7d3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27631
49619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2763149619
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.190219959
Short name T2011
Test name
Test status
Simulation time 37675828 ps
CPU time 0.69 seconds
Started Jul 29 06:16:55 PM PDT 24
Finished Jul 29 06:16:56 PM PDT 24
Peak memory 207084 kb
Host smart-a994355a-9d2f-4e10-a846-9d88d3e48553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19021
9959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.190219959
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.4162998773
Short name T2786
Test name
Test status
Simulation time 22808980476 ps
CPU time 61.18 seconds
Started Jul 29 06:16:53 PM PDT 24
Finished Jul 29 06:17:55 PM PDT 24
Peak memory 220360 kb
Host smart-e9c1d253-e3f9-4d82-8ac8-574c44ab4805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41629
98773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.4162998773
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3032311264
Short name T1640
Test name
Test status
Simulation time 164850430 ps
CPU time 0.9 seconds
Started Jul 29 06:16:54 PM PDT 24
Finished Jul 29 06:16:55 PM PDT 24
Peak memory 207120 kb
Host smart-e1a68da1-b9f8-4fa9-bbe6-ba0c1f498395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30323
11264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3032311264
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.4201047755
Short name T1405
Test name
Test status
Simulation time 254149764 ps
CPU time 1.03 seconds
Started Jul 29 06:16:57 PM PDT 24
Finished Jul 29 06:16:58 PM PDT 24
Peak memory 207056 kb
Host smart-b99bd503-4c9e-4bd3-97c3-32c69d1a5f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42010
47755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.4201047755
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.3118790152
Short name T2789
Test name
Test status
Simulation time 227200560 ps
CPU time 0.97 seconds
Started Jul 29 06:16:52 PM PDT 24
Finished Jul 29 06:16:53 PM PDT 24
Peak memory 207040 kb
Host smart-97a5c8cd-d9ea-4961-b382-fa28a2591d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31187
90152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.3118790152
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2701696058
Short name T1185
Test name
Test status
Simulation time 195803123 ps
CPU time 0.97 seconds
Started Jul 29 06:16:54 PM PDT 24
Finished Jul 29 06:16:55 PM PDT 24
Peak memory 207216 kb
Host smart-8a638f11-4490-42c7-bc14-3cc682f626c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27016
96058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2701696058
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.426273249
Short name T2752
Test name
Test status
Simulation time 135802551 ps
CPU time 0.8 seconds
Started Jul 29 06:16:54 PM PDT 24
Finished Jul 29 06:16:55 PM PDT 24
Peak memory 207008 kb
Host smart-7feb2d0e-56dd-4530-b95e-79c08d1a6978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42627
3249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.426273249
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3531009613
Short name T2435
Test name
Test status
Simulation time 165223497 ps
CPU time 0.81 seconds
Started Jul 29 06:16:53 PM PDT 24
Finished Jul 29 06:16:54 PM PDT 24
Peak memory 206892 kb
Host smart-bdb44ac6-5ad4-4889-bca4-0d84d945c7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35310
09613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3531009613
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2337254430
Short name T2259
Test name
Test status
Simulation time 158436103 ps
CPU time 0.91 seconds
Started Jul 29 06:16:54 PM PDT 24
Finished Jul 29 06:16:55 PM PDT 24
Peak memory 207128 kb
Host smart-2b3489de-3437-4ca0-81ae-8e36e7fdbd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23372
54430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2337254430
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1695716513
Short name T2424
Test name
Test status
Simulation time 228505810 ps
CPU time 0.95 seconds
Started Jul 29 06:16:56 PM PDT 24
Finished Jul 29 06:16:57 PM PDT 24
Peak memory 207108 kb
Host smart-37b7ff61-4838-441c-9631-8f3bfd9382a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16957
16513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1695716513
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3691489684
Short name T1731
Test name
Test status
Simulation time 5516485046 ps
CPU time 162.64 seconds
Started Jul 29 06:16:53 PM PDT 24
Finished Jul 29 06:19:35 PM PDT 24
Peak memory 215548 kb
Host smart-f7d42182-03e4-4267-9af2-c9b850f42900
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3691489684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3691489684
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.853158401
Short name T1155
Test name
Test status
Simulation time 161305646 ps
CPU time 0.88 seconds
Started Jul 29 06:16:54 PM PDT 24
Finished Jul 29 06:16:55 PM PDT 24
Peak memory 207140 kb
Host smart-0b74cbb6-1df5-4f22-8c29-811dc443f8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85315
8401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.853158401
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3824797854
Short name T523
Test name
Test status
Simulation time 181355463 ps
CPU time 0.98 seconds
Started Jul 29 06:16:54 PM PDT 24
Finished Jul 29 06:16:55 PM PDT 24
Peak memory 207032 kb
Host smart-8583fd1b-47f8-4069-9e66-15b2da3381c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38247
97854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3824797854
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.628480782
Short name T1491
Test name
Test status
Simulation time 374143849 ps
CPU time 1.19 seconds
Started Jul 29 06:16:53 PM PDT 24
Finished Jul 29 06:16:55 PM PDT 24
Peak memory 206936 kb
Host smart-57d5a8b6-6308-4fab-8d8e-cf8c38ead15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62848
0782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.628480782
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2163963991
Short name T503
Test name
Test status
Simulation time 4022937455 ps
CPU time 121.19 seconds
Started Jul 29 06:16:53 PM PDT 24
Finished Jul 29 06:18:54 PM PDT 24
Peak memory 215528 kb
Host smart-af68a1a7-9671-492c-a0d1-057c8848cc92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21639
63991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2163963991
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.383029248
Short name T933
Test name
Test status
Simulation time 1166475811 ps
CPU time 26.59 seconds
Started Jul 29 06:16:47 PM PDT 24
Finished Jul 29 06:17:14 PM PDT 24
Peak memory 207360 kb
Host smart-dba5df74-ab8f-4eea-a061-33d31e9136c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383029248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_host
_handshake.383029248
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.3434067380
Short name T855
Test name
Test status
Simulation time 45333031 ps
CPU time 0.68 seconds
Started Jul 29 06:17:06 PM PDT 24
Finished Jul 29 06:17:07 PM PDT 24
Peak memory 207112 kb
Host smart-4fe8299c-2e08-481f-8102-5dfe6909553d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3434067380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3434067380
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.34632297
Short name T1300
Test name
Test status
Simulation time 4372401420 ps
CPU time 6.02 seconds
Started Jul 29 06:17:06 PM PDT 24
Finished Jul 29 06:17:12 PM PDT 24
Peak memory 207376 kb
Host smart-2d7b0bad-91ff-4da7-8abc-7a7244637b23
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34632297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon
_wake_disconnect.34632297
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.2676039864
Short name T1302
Test name
Test status
Simulation time 13382008270 ps
CPU time 17.77 seconds
Started Jul 29 06:17:05 PM PDT 24
Finished Jul 29 06:17:23 PM PDT 24
Peak memory 207448 kb
Host smart-cf22e650-24e7-44f0-8394-6f7275ca1926
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676039864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.2676039864
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2093841723
Short name T1504
Test name
Test status
Simulation time 23361915934 ps
CPU time 28.48 seconds
Started Jul 29 06:17:00 PM PDT 24
Finished Jul 29 06:17:29 PM PDT 24
Peak memory 207340 kb
Host smart-fc7985aa-598e-4247-bd9d-7c2e4cc6c63c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093841723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.2093841723
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.4014196530
Short name T2647
Test name
Test status
Simulation time 176490050 ps
CPU time 0.9 seconds
Started Jul 29 06:17:07 PM PDT 24
Finished Jul 29 06:17:08 PM PDT 24
Peak memory 207104 kb
Host smart-58944b03-bf21-4804-aabb-4fce33337f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40141
96530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.4014196530
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.1321520895
Short name T2529
Test name
Test status
Simulation time 180981004 ps
CPU time 0.91 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:17:03 PM PDT 24
Peak memory 207020 kb
Host smart-6b493258-b41f-4d90-aaf7-6b37c32c238b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13215
20895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.1321520895
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.566350133
Short name T2199
Test name
Test status
Simulation time 409917003 ps
CPU time 1.59 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:17:04 PM PDT 24
Peak memory 207116 kb
Host smart-c94d238b-76cd-4671-acdf-dae8ca6b5d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56635
0133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.566350133
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1147563120
Short name T66
Test name
Test status
Simulation time 326590526 ps
CPU time 1.1 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:17:03 PM PDT 24
Peak memory 207124 kb
Host smart-a9799f2b-8ca6-4cdb-8d84-8d30c8b6ad6e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1147563120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1147563120
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.721333506
Short name T2144
Test name
Test status
Simulation time 6995075209 ps
CPU time 14.55 seconds
Started Jul 29 06:17:03 PM PDT 24
Finished Jul 29 06:17:18 PM PDT 24
Peak memory 207364 kb
Host smart-c6268f64-ffd8-4a4a-8723-9255f61f5e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72133
3506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.721333506
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.3122710832
Short name T1485
Test name
Test status
Simulation time 850038181 ps
CPU time 5.46 seconds
Started Jul 29 06:16:59 PM PDT 24
Finished Jul 29 06:17:05 PM PDT 24
Peak memory 207332 kb
Host smart-40b36e88-56f1-4d5a-83fc-ef7a6e92816a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122710832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.3122710832
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.1109168876
Short name T1653
Test name
Test status
Simulation time 456372263 ps
CPU time 1.61 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:17:04 PM PDT 24
Peak memory 207064 kb
Host smart-7c4a6272-0e34-4d57-9c80-e8ab67314a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11091
68876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.1109168876
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.1671808533
Short name T1513
Test name
Test status
Simulation time 142045235 ps
CPU time 0.87 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:17:03 PM PDT 24
Peak memory 207044 kb
Host smart-0475b001-6927-420b-a8b4-fc539e000187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16718
08533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.1671808533
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2181181644
Short name T1996
Test name
Test status
Simulation time 75066398 ps
CPU time 0.72 seconds
Started Jul 29 06:17:00 PM PDT 24
Finished Jul 29 06:17:01 PM PDT 24
Peak memory 207076 kb
Host smart-20257b4a-2c6f-424e-802a-15eec5c34612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21811
81644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2181181644
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.96925600
Short name T547
Test name
Test status
Simulation time 782978978 ps
CPU time 2.04 seconds
Started Jul 29 06:17:01 PM PDT 24
Finished Jul 29 06:17:03 PM PDT 24
Peak memory 207268 kb
Host smart-b28c24c8-3b9d-4ad1-93f3-b157cfa73915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96925
600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.96925600
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3112232961
Short name T2080
Test name
Test status
Simulation time 200404118 ps
CPU time 2.57 seconds
Started Jul 29 06:17:03 PM PDT 24
Finished Jul 29 06:17:06 PM PDT 24
Peak memory 207256 kb
Host smart-f3bff6df-2092-4cde-baa6-5536284d4559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31122
32961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3112232961
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.239023313
Short name T983
Test name
Test status
Simulation time 164769526 ps
CPU time 0.96 seconds
Started Jul 29 06:17:00 PM PDT 24
Finished Jul 29 06:17:01 PM PDT 24
Peak memory 207044 kb
Host smart-bcea616b-396b-40c9-a608-f73b0919bea5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=239023313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.239023313
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2672449355
Short name T2277
Test name
Test status
Simulation time 192904837 ps
CPU time 0.87 seconds
Started Jul 29 06:16:58 PM PDT 24
Finished Jul 29 06:16:59 PM PDT 24
Peak memory 207072 kb
Host smart-39ba4394-57c8-4f6f-a0dc-8e0baa37f163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26724
49355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2672449355
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.947055895
Short name T2378
Test name
Test status
Simulation time 218156731 ps
CPU time 1.17 seconds
Started Jul 29 06:17:00 PM PDT 24
Finished Jul 29 06:17:01 PM PDT 24
Peak memory 207072 kb
Host smart-86a4fd60-db32-4a28-9eb0-ec62a48be5c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94705
5895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.947055895
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.1296265841
Short name T2260
Test name
Test status
Simulation time 7971930080 ps
CPU time 237.87 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:21:00 PM PDT 24
Peak memory 215572 kb
Host smart-3d2c4f26-9f2f-4163-ac27-4eb9284effb2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1296265841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1296265841
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.3666422615
Short name T1976
Test name
Test status
Simulation time 8891070870 ps
CPU time 61.25 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:18:03 PM PDT 24
Peak memory 207360 kb
Host smart-8ea4e46b-c2c5-45b2-b5e3-35058c6b3339
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3666422615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.3666422615
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2465307174
Short name T1089
Test name
Test status
Simulation time 228778230 ps
CPU time 1.05 seconds
Started Jul 29 06:17:04 PM PDT 24
Finished Jul 29 06:17:05 PM PDT 24
Peak memory 207096 kb
Host smart-fe790350-e371-4bf0-b1ee-b41877a1ef3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24653
07174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2465307174
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1385490514
Short name T1993
Test name
Test status
Simulation time 23319857335 ps
CPU time 30.83 seconds
Started Jul 29 06:17:01 PM PDT 24
Finished Jul 29 06:17:32 PM PDT 24
Peak memory 207408 kb
Host smart-70e5b5f3-77e1-4ee0-8921-7a9b2bc00dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13854
90514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1385490514
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3362487053
Short name T992
Test name
Test status
Simulation time 3341024578 ps
CPU time 5.34 seconds
Started Jul 29 06:16:59 PM PDT 24
Finished Jul 29 06:17:05 PM PDT 24
Peak memory 207348 kb
Host smart-ee4989cd-97e4-4080-b2d6-9982d6a813b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33624
87053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3362487053
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.413424318
Short name T2283
Test name
Test status
Simulation time 5141257313 ps
CPU time 158.28 seconds
Started Jul 29 06:17:01 PM PDT 24
Finished Jul 29 06:19:40 PM PDT 24
Peak memory 215620 kb
Host smart-6b06cda3-d296-4651-b166-0e951cdc79c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41342
4318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.413424318
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1616613740
Short name T489
Test name
Test status
Simulation time 7060825596 ps
CPU time 71.06 seconds
Started Jul 29 06:16:59 PM PDT 24
Finished Jul 29 06:18:10 PM PDT 24
Peak memory 207356 kb
Host smart-9f928098-1404-4f9d-838f-307f21b2857c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1616613740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1616613740
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.2142300659
Short name T1676
Test name
Test status
Simulation time 242963670 ps
CPU time 1.04 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:17:03 PM PDT 24
Peak memory 207060 kb
Host smart-2f92ee09-de06-4ccb-b809-2e466c91e3f1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2142300659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.2142300659
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.610390856
Short name T1005
Test name
Test status
Simulation time 225265644 ps
CPU time 0.99 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:17:03 PM PDT 24
Peak memory 207048 kb
Host smart-092f7830-57b0-47f4-937c-c744fe36e4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61039
0856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.610390856
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.2250483665
Short name T965
Test name
Test status
Simulation time 4275019257 ps
CPU time 35.67 seconds
Started Jul 29 06:17:04 PM PDT 24
Finished Jul 29 06:17:39 PM PDT 24
Peak memory 217132 kb
Host smart-1a3e6f04-7fa0-4144-a13f-4f3efd5258fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22504
83665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.2250483665
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1294118504
Short name T2060
Test name
Test status
Simulation time 5175693369 ps
CPU time 157.29 seconds
Started Jul 29 06:17:04 PM PDT 24
Finished Jul 29 06:19:42 PM PDT 24
Peak memory 215580 kb
Host smart-d8819773-582b-472d-858b-bbbfa08277f2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1294118504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1294118504
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2876069228
Short name T693
Test name
Test status
Simulation time 156155165 ps
CPU time 0.86 seconds
Started Jul 29 06:17:04 PM PDT 24
Finished Jul 29 06:17:05 PM PDT 24
Peak memory 207076 kb
Host smart-faa63be6-4f29-4fc6-988c-5bd6aa72a150
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2876069228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2876069228
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1763071772
Short name T1045
Test name
Test status
Simulation time 165739852 ps
CPU time 0.84 seconds
Started Jul 29 06:17:06 PM PDT 24
Finished Jul 29 06:17:07 PM PDT 24
Peak memory 207116 kb
Host smart-f251b489-fe9c-4f07-9110-fa6ddf8b5cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17630
71772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1763071772
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2687101363
Short name T2111
Test name
Test status
Simulation time 221137574 ps
CPU time 1.07 seconds
Started Jul 29 06:17:03 PM PDT 24
Finished Jul 29 06:17:04 PM PDT 24
Peak memory 207140 kb
Host smart-b52b045e-9ffc-42a1-873d-e76c4848459e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26871
01363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2687101363
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2631298675
Short name T1611
Test name
Test status
Simulation time 156541827 ps
CPU time 0.89 seconds
Started Jul 29 06:17:03 PM PDT 24
Finished Jul 29 06:17:04 PM PDT 24
Peak memory 207132 kb
Host smart-f6426982-aa1e-4201-b031-03dbe11f4468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26312
98675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2631298675
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2737891034
Short name T359
Test name
Test status
Simulation time 179198233 ps
CPU time 0.88 seconds
Started Jul 29 06:17:00 PM PDT 24
Finished Jul 29 06:17:01 PM PDT 24
Peak memory 207100 kb
Host smart-7779030e-0b6a-4d14-936f-b5d8fa4b0a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27378
91034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2737891034
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1872997654
Short name T395
Test name
Test status
Simulation time 205685031 ps
CPU time 0.96 seconds
Started Jul 29 06:17:00 PM PDT 24
Finished Jul 29 06:17:01 PM PDT 24
Peak memory 207060 kb
Host smart-e254d0bd-9f5f-4a13-9304-a9116c7bba95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18729
97654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1872997654
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1365305037
Short name T162
Test name
Test status
Simulation time 148087379 ps
CPU time 0.84 seconds
Started Jul 29 06:17:06 PM PDT 24
Finished Jul 29 06:17:07 PM PDT 24
Peak memory 207092 kb
Host smart-45a9e544-d6f0-47dd-80ee-333434ef5f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13653
05037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1365305037
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3889838914
Short name T2056
Test name
Test status
Simulation time 259672949 ps
CPU time 1.12 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:17:04 PM PDT 24
Peak memory 207124 kb
Host smart-5739164f-4f35-40c5-9ca5-987ddd58e5df
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3889838914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3889838914
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1429461304
Short name T864
Test name
Test status
Simulation time 205017565 ps
CPU time 0.88 seconds
Started Jul 29 06:17:05 PM PDT 24
Finished Jul 29 06:17:06 PM PDT 24
Peak memory 207084 kb
Host smart-e5a3b484-fa17-428e-9f25-e31dcec432a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14294
61304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1429461304
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3830949282
Short name T1379
Test name
Test status
Simulation time 46775648 ps
CPU time 0.7 seconds
Started Jul 29 06:17:04 PM PDT 24
Finished Jul 29 06:17:05 PM PDT 24
Peak memory 207108 kb
Host smart-a527a375-ed7a-4f44-be1d-bc5eb9b1dc52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38309
49282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3830949282
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.2673735794
Short name T240
Test name
Test status
Simulation time 19293618303 ps
CPU time 47.82 seconds
Started Jul 29 06:17:05 PM PDT 24
Finished Jul 29 06:17:53 PM PDT 24
Peak memory 215624 kb
Host smart-b9665dd5-4838-4ea7-954f-6e3747800447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26737
35794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.2673735794
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2143698970
Short name T2094
Test name
Test status
Simulation time 172351437 ps
CPU time 0.86 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:17:03 PM PDT 24
Peak memory 207056 kb
Host smart-006ce6a2-6fdb-4f9b-b597-75aed0f02bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21436
98970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2143698970
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.677358662
Short name T1813
Test name
Test status
Simulation time 217705100 ps
CPU time 0.96 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:10 PM PDT 24
Peak memory 207120 kb
Host smart-192f63ed-8396-4c9c-a307-5e420cedbf59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67735
8662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.677358662
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.3713729214
Short name T909
Test name
Test status
Simulation time 172391399 ps
CPU time 0.86 seconds
Started Jul 29 06:17:05 PM PDT 24
Finished Jul 29 06:17:06 PM PDT 24
Peak memory 207068 kb
Host smart-43e04c11-5731-4c15-aa10-14be4f59fb40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37137
29214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.3713729214
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.2398680304
Short name T761
Test name
Test status
Simulation time 231792923 ps
CPU time 0.95 seconds
Started Jul 29 06:17:06 PM PDT 24
Finished Jul 29 06:17:07 PM PDT 24
Peak memory 207104 kb
Host smart-72d10681-c5e6-4967-be39-fd9c3daeb8c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23986
80304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.2398680304
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2977052426
Short name T1186
Test name
Test status
Simulation time 145235350 ps
CPU time 0.8 seconds
Started Jul 29 06:17:06 PM PDT 24
Finished Jul 29 06:17:07 PM PDT 24
Peak memory 207060 kb
Host smart-66a32f8a-1408-4583-a764-7ddcf26a5fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29770
52426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2977052426
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1057767298
Short name T2327
Test name
Test status
Simulation time 160977524 ps
CPU time 0.87 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:10 PM PDT 24
Peak memory 207084 kb
Host smart-295fb80d-7078-4a1e-9344-06750b499e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10577
67298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1057767298
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1396658499
Short name T276
Test name
Test status
Simulation time 168524793 ps
CPU time 0.86 seconds
Started Jul 29 06:17:04 PM PDT 24
Finished Jul 29 06:17:05 PM PDT 24
Peak memory 207140 kb
Host smart-e6df2c68-9275-418e-bf6f-9499ac6f4bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13966
58499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1396658499
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3949649546
Short name T1983
Test name
Test status
Simulation time 266590062 ps
CPU time 1.06 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:17:03 PM PDT 24
Peak memory 207100 kb
Host smart-8721db7b-903f-4bb4-93c7-90c3fc51888e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39496
49546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3949649546
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1171979449
Short name T1891
Test name
Test status
Simulation time 3528779283 ps
CPU time 101.61 seconds
Started Jul 29 06:17:07 PM PDT 24
Finished Jul 29 06:18:48 PM PDT 24
Peak memory 215500 kb
Host smart-10188b7b-f6dc-4666-b3e5-017d2cfe8bb1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1171979449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1171979449
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.766369623
Short name T2262
Test name
Test status
Simulation time 162138604 ps
CPU time 0.9 seconds
Started Jul 29 06:17:03 PM PDT 24
Finished Jul 29 06:17:04 PM PDT 24
Peak memory 207060 kb
Host smart-f34bc323-92ec-4db2-a2d2-7463fee83259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76636
9623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.766369623
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.565742948
Short name T1695
Test name
Test status
Simulation time 223688237 ps
CPU time 0.91 seconds
Started Jul 29 06:17:06 PM PDT 24
Finished Jul 29 06:17:07 PM PDT 24
Peak memory 207076 kb
Host smart-c0a737d4-e0ca-40fb-a091-02ca1ff94118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56574
2948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.565742948
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.3265353106
Short name T2362
Test name
Test status
Simulation time 472918312 ps
CPU time 1.41 seconds
Started Jul 29 06:17:05 PM PDT 24
Finished Jul 29 06:17:06 PM PDT 24
Peak memory 207044 kb
Host smart-831bdcff-d536-4b7f-9172-db7d5ce3c3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32653
53106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.3265353106
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3275352226
Short name T1937
Test name
Test status
Simulation time 4072310517 ps
CPU time 42.71 seconds
Started Jul 29 06:17:03 PM PDT 24
Finished Jul 29 06:17:46 PM PDT 24
Peak memory 207524 kb
Host smart-d47b55c9-8e67-4529-9f03-41e5e5cca930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32753
52226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3275352226
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.3873605938
Short name T2776
Test name
Test status
Simulation time 667486234 ps
CPU time 5.11 seconds
Started Jul 29 06:17:01 PM PDT 24
Finished Jul 29 06:17:06 PM PDT 24
Peak memory 207324 kb
Host smart-ed4c216a-3dbe-4c36-bf79-85ca1a36e54c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873605938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.3873605938
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3832330967
Short name T2794
Test name
Test status
Simulation time 80000212 ps
CPU time 0.7 seconds
Started Jul 29 06:17:17 PM PDT 24
Finished Jul 29 06:17:18 PM PDT 24
Peak memory 207008 kb
Host smart-d4fd5a9d-7b1f-4004-8d4b-23ef34ba2b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3832330967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3832330967
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2528809945
Short name T9
Test name
Test status
Simulation time 3469595434 ps
CPU time 5.71 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:15 PM PDT 24
Peak memory 207392 kb
Host smart-509a93b5-9b67-43bf-a475-82c58581a82c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528809945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.2528809945
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.4096225658
Short name T2790
Test name
Test status
Simulation time 13368865871 ps
CPU time 16.63 seconds
Started Jul 29 06:17:04 PM PDT 24
Finished Jul 29 06:17:21 PM PDT 24
Peak memory 207408 kb
Host smart-1dd2a199-020f-4ddd-a540-f35938955987
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096225658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.4096225658
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.64961535
Short name T1096
Test name
Test status
Simulation time 23381089687 ps
CPU time 26.29 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:36 PM PDT 24
Peak memory 207432 kb
Host smart-be654204-7c11-4b45-a2e0-c2c60d999209
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64961535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon
_wake_resume.64961535
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1643392617
Short name T2308
Test name
Test status
Simulation time 162791069 ps
CPU time 0.91 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:10 PM PDT 24
Peak memory 207084 kb
Host smart-e0af6e8d-514b-459e-9161-71d2fb196472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16433
92617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1643392617
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1631571240
Short name T2235
Test name
Test status
Simulation time 149575609 ps
CPU time 0.83 seconds
Started Jul 29 06:17:02 PM PDT 24
Finished Jul 29 06:17:03 PM PDT 24
Peak memory 207080 kb
Host smart-407d36c4-9cc7-4f3b-b2e6-f10e64a6b379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16315
71240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1631571240
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.2451355050
Short name T1682
Test name
Test status
Simulation time 373301424 ps
CPU time 1.42 seconds
Started Jul 29 06:17:04 PM PDT 24
Finished Jul 29 06:17:06 PM PDT 24
Peak memory 207084 kb
Host smart-97e8d9f1-ce5d-431e-a92f-a0e179875875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24513
55050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.2451355050
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2590656185
Short name T1079
Test name
Test status
Simulation time 416937672 ps
CPU time 1.33 seconds
Started Jul 29 06:17:06 PM PDT 24
Finished Jul 29 06:17:08 PM PDT 24
Peak memory 207080 kb
Host smart-9f9081f5-f778-4ac5-ae93-d1ade523eceb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2590656185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2590656185
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.1471902546
Short name T839
Test name
Test status
Simulation time 21242788182 ps
CPU time 48.2 seconds
Started Jul 29 06:17:05 PM PDT 24
Finished Jul 29 06:17:53 PM PDT 24
Peak memory 207360 kb
Host smart-fe778477-fea5-4898-a0de-cab64834aabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14719
02546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.1471902546
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.2130578165
Short name T1675
Test name
Test status
Simulation time 2497276057 ps
CPU time 22.51 seconds
Started Jul 29 06:17:06 PM PDT 24
Finished Jul 29 06:17:28 PM PDT 24
Peak memory 207344 kb
Host smart-6e76da60-82db-4aaf-b015-5e485ad8b86e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130578165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.2130578165
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.1117316072
Short name T817
Test name
Test status
Simulation time 457642460 ps
CPU time 1.39 seconds
Started Jul 29 06:17:11 PM PDT 24
Finished Jul 29 06:17:12 PM PDT 24
Peak memory 207040 kb
Host smart-184a3ab7-3453-4c9f-9bbb-7901acd99df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11173
16072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.1117316072
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2184942657
Short name T426
Test name
Test status
Simulation time 143928663 ps
CPU time 0.86 seconds
Started Jul 29 06:17:13 PM PDT 24
Finished Jul 29 06:17:14 PM PDT 24
Peak memory 207104 kb
Host smart-6d2ec015-cbea-475a-a4d0-2601d3f0b7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21849
42657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2184942657
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.2589557879
Short name T329
Test name
Test status
Simulation time 39173375 ps
CPU time 0.72 seconds
Started Jul 29 06:17:08 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 207004 kb
Host smart-dba5af67-d6c7-445d-a36c-645ef4af0d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25895
57879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2589557879
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.1143740544
Short name T1346
Test name
Test status
Simulation time 882365317 ps
CPU time 2.27 seconds
Started Jul 29 06:17:10 PM PDT 24
Finished Jul 29 06:17:13 PM PDT 24
Peak memory 207288 kb
Host smart-9919967a-d625-4e64-9482-5c9d526459a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11437
40544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1143740544
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1238885334
Short name T1733
Test name
Test status
Simulation time 282130172 ps
CPU time 1.92 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:11 PM PDT 24
Peak memory 207260 kb
Host smart-76b7d2c2-a8d4-4bc2-8c3d-cdcd09b4edc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12388
85334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1238885334
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2447788840
Short name T949
Test name
Test status
Simulation time 223323181 ps
CPU time 0.95 seconds
Started Jul 29 06:17:08 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 207088 kb
Host smart-1753b9df-691c-4861-b431-1dac36c244eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2447788840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2447788840
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1842079545
Short name T2521
Test name
Test status
Simulation time 140441350 ps
CPU time 0.78 seconds
Started Jul 29 06:17:08 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 207156 kb
Host smart-4f504cfa-8945-4b4b-bac0-cbe0feb01bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18420
79545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1842079545
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.511017402
Short name T2093
Test name
Test status
Simulation time 206202518 ps
CPU time 0.93 seconds
Started Jul 29 06:17:08 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 207224 kb
Host smart-368bf966-0c71-458f-92dc-b4a80448d0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51101
7402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.511017402
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.308361662
Short name T975
Test name
Test status
Simulation time 6881028150 ps
CPU time 70.85 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:18:20 PM PDT 24
Peak memory 215632 kb
Host smart-c909a5a8-46cc-4adf-9115-062a762a3740
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=308361662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.308361662
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2844870189
Short name T2428
Test name
Test status
Simulation time 207415457 ps
CPU time 0.94 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:10 PM PDT 24
Peak memory 207104 kb
Host smart-7cbf8905-9e58-4cda-97a2-564d115aafff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28448
70189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2844870189
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.843322766
Short name T561
Test name
Test status
Simulation time 23356530456 ps
CPU time 27.54 seconds
Started Jul 29 06:17:11 PM PDT 24
Finished Jul 29 06:17:38 PM PDT 24
Peak memory 207412 kb
Host smart-94eacc51-9300-4ebd-8aa6-93cb5f3f91aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84332
2766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.843322766
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2480834262
Short name T1740
Test name
Test status
Simulation time 3275979380 ps
CPU time 6 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:15 PM PDT 24
Peak memory 207348 kb
Host smart-1a1f1074-1ad8-4167-b8b6-6c0b358a6759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24808
34262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2480834262
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2757766724
Short name T332
Test name
Test status
Simulation time 5108361466 ps
CPU time 153.02 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:19:42 PM PDT 24
Peak memory 217620 kb
Host smart-e8f45a0f-0060-43e5-b8e1-e60a4681107f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27577
66724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2757766724
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3000962820
Short name T2842
Test name
Test status
Simulation time 3698680160 ps
CPU time 28.22 seconds
Started Jul 29 06:17:07 PM PDT 24
Finished Jul 29 06:17:35 PM PDT 24
Peak memory 216952 kb
Host smart-4d91aa60-16aa-4dcc-b5d6-6789e7bad934
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3000962820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3000962820
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.910780552
Short name T2586
Test name
Test status
Simulation time 294779466 ps
CPU time 1.09 seconds
Started Jul 29 06:17:13 PM PDT 24
Finished Jul 29 06:17:14 PM PDT 24
Peak memory 207124 kb
Host smart-af92a9cd-7db5-449d-88ae-04f4f2e770e2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=910780552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.910780552
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3419153792
Short name T507
Test name
Test status
Simulation time 195400336 ps
CPU time 0.97 seconds
Started Jul 29 06:17:11 PM PDT 24
Finished Jul 29 06:17:12 PM PDT 24
Peak memory 207052 kb
Host smart-ff9bf506-ed6a-4fd7-8e39-3d4d76ccc001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34191
53792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3419153792
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.2788594270
Short name T2615
Test name
Test status
Simulation time 3955965083 ps
CPU time 41.19 seconds
Started Jul 29 06:17:10 PM PDT 24
Finished Jul 29 06:17:51 PM PDT 24
Peak memory 216764 kb
Host smart-fcd7b158-aa9c-4f5e-9bd8-030ae8c7378b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27885
94270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.2788594270
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.2920198961
Short name T2456
Test name
Test status
Simulation time 3116983810 ps
CPU time 31.96 seconds
Started Jul 29 06:17:08 PM PDT 24
Finished Jul 29 06:17:40 PM PDT 24
Peak memory 216708 kb
Host smart-a502943a-7ed3-4943-af12-1e6c736f3d88
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2920198961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.2920198961
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.2023350183
Short name T1944
Test name
Test status
Simulation time 157100742 ps
CPU time 0.86 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:10 PM PDT 24
Peak memory 207148 kb
Host smart-060b67d6-2627-45e5-8740-bf43ecadb1fd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2023350183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2023350183
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.276688611
Short name T1763
Test name
Test status
Simulation time 169117942 ps
CPU time 0.86 seconds
Started Jul 29 06:17:10 PM PDT 24
Finished Jul 29 06:17:11 PM PDT 24
Peak memory 207124 kb
Host smart-bce5a028-be3d-4047-a6ce-c7b679128337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27668
8611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.276688611
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1709403382
Short name T2544
Test name
Test status
Simulation time 236259871 ps
CPU time 1.01 seconds
Started Jul 29 06:17:08 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 207120 kb
Host smart-8434d8e9-3885-45a8-b5b1-ddd0c592ed57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17094
03382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1709403382
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3825517488
Short name T532
Test name
Test status
Simulation time 153628185 ps
CPU time 0.82 seconds
Started Jul 29 06:17:08 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 207076 kb
Host smart-e997423a-87da-4a8b-b1fd-190e85517e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38255
17488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3825517488
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3709565700
Short name T2760
Test name
Test status
Simulation time 164827040 ps
CPU time 0.84 seconds
Started Jul 29 06:17:08 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 207124 kb
Host smart-8d74d5b7-ac84-47ff-9a07-d81b1bc10981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37095
65700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3709565700
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1928278629
Short name T1641
Test name
Test status
Simulation time 183174294 ps
CPU time 0.92 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:11 PM PDT 24
Peak memory 207136 kb
Host smart-316ac693-beb9-4a22-8b4e-06ee6bb0279b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19282
78629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1928278629
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.385667559
Short name T670
Test name
Test status
Simulation time 159444005 ps
CPU time 0.85 seconds
Started Jul 29 06:17:08 PM PDT 24
Finished Jul 29 06:17:09 PM PDT 24
Peak memory 207076 kb
Host smart-210154fc-9902-4bbe-b7ba-0c5c7c92e812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38566
7559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.385667559
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.4273153275
Short name T926
Test name
Test status
Simulation time 258208110 ps
CPU time 1.04 seconds
Started Jul 29 06:17:08 PM PDT 24
Finished Jul 29 06:17:10 PM PDT 24
Peak memory 207104 kb
Host smart-0dab3199-e949-4dfd-8ac3-75573845b66b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4273153275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.4273153275
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2413414546
Short name T1771
Test name
Test status
Simulation time 212906005 ps
CPU time 0.97 seconds
Started Jul 29 06:17:08 PM PDT 24
Finished Jul 29 06:17:10 PM PDT 24
Peak memory 207068 kb
Host smart-2a267c7a-01d8-4b30-ad83-873d38c1a732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24134
14546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2413414546
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1798412179
Short name T2107
Test name
Test status
Simulation time 52750439 ps
CPU time 0.71 seconds
Started Jul 29 06:17:10 PM PDT 24
Finished Jul 29 06:17:10 PM PDT 24
Peak memory 207012 kb
Host smart-6fc6d9c4-e52d-4863-b3cc-e9e3c8b0d53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17984
12179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1798412179
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3578809239
Short name T1879
Test name
Test status
Simulation time 13132077611 ps
CPU time 32.84 seconds
Started Jul 29 06:17:07 PM PDT 24
Finished Jul 29 06:17:40 PM PDT 24
Peak memory 220400 kb
Host smart-a9ea9d24-fb52-46d9-b937-95cc67ad7ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35788
09239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3578809239
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.505177100
Short name T1068
Test name
Test status
Simulation time 187813454 ps
CPU time 0.92 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:10 PM PDT 24
Peak memory 207124 kb
Host smart-3115931f-2a69-411f-b751-02dbdb6566b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50517
7100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.505177100
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.856782862
Short name T620
Test name
Test status
Simulation time 234044144 ps
CPU time 0.95 seconds
Started Jul 29 06:17:11 PM PDT 24
Finished Jul 29 06:17:12 PM PDT 24
Peak memory 207052 kb
Host smart-abf1e02f-0e08-44fe-b410-b3e811fea57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85678
2862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.856782862
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3766334025
Short name T1851
Test name
Test status
Simulation time 228387257 ps
CPU time 1.09 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:11 PM PDT 24
Peak memory 207072 kb
Host smart-12aefe00-61c4-43b3-aa7e-db95f139db1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37663
34025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3766334025
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.1153880719
Short name T325
Test name
Test status
Simulation time 189657686 ps
CPU time 0.99 seconds
Started Jul 29 06:17:09 PM PDT 24
Finished Jul 29 06:17:11 PM PDT 24
Peak memory 207060 kb
Host smart-9333b4d0-d448-47a6-819c-48a4ebb5d66c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11538
80719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.1153880719
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.43418504
Short name T2255
Test name
Test status
Simulation time 153133281 ps
CPU time 0.82 seconds
Started Jul 29 06:17:13 PM PDT 24
Finished Jul 29 06:17:14 PM PDT 24
Peak memory 207048 kb
Host smart-322f7cf0-39df-4788-8068-ee7cc761f660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43418
504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.43418504
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.70065932
Short name T1830
Test name
Test status
Simulation time 170517845 ps
CPU time 0.94 seconds
Started Jul 29 06:17:16 PM PDT 24
Finished Jul 29 06:17:17 PM PDT 24
Peak memory 207060 kb
Host smart-8491361c-5c99-49db-9f40-61c6745b5103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70065
932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.70065932
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3742013373
Short name T2318
Test name
Test status
Simulation time 150870700 ps
CPU time 0.85 seconds
Started Jul 29 06:17:19 PM PDT 24
Finished Jul 29 06:17:20 PM PDT 24
Peak memory 207116 kb
Host smart-7a7818f1-feb6-4811-beda-fdf6e214e2df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37420
13373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3742013373
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3328485939
Short name T2010
Test name
Test status
Simulation time 234652156 ps
CPU time 1.06 seconds
Started Jul 29 06:17:13 PM PDT 24
Finished Jul 29 06:17:14 PM PDT 24
Peak memory 207108 kb
Host smart-5d9f02bb-72f9-4a04-b6a5-8a3bd29a9e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33284
85939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3328485939
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2015355614
Short name T2836
Test name
Test status
Simulation time 3553623325 ps
CPU time 35.79 seconds
Started Jul 29 06:17:14 PM PDT 24
Finished Jul 29 06:17:50 PM PDT 24
Peak memory 217164 kb
Host smart-d02d28e1-2105-4a51-b9f1-c3d32a180d96
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2015355614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2015355614
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1262449402
Short name T2602
Test name
Test status
Simulation time 195064656 ps
CPU time 0.97 seconds
Started Jul 29 06:17:21 PM PDT 24
Finished Jul 29 06:17:22 PM PDT 24
Peak memory 207116 kb
Host smart-05bfc30b-a697-4502-a1e4-5476b8223330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12624
49402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1262449402
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.4089891444
Short name T2568
Test name
Test status
Simulation time 166779120 ps
CPU time 0.92 seconds
Started Jul 29 06:17:14 PM PDT 24
Finished Jul 29 06:17:15 PM PDT 24
Peak memory 207020 kb
Host smart-4ae4a646-41ff-40d4-9c14-5c219cbc8bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40898
91444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.4089891444
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.2019550501
Short name T1200
Test name
Test status
Simulation time 432094179 ps
CPU time 1.45 seconds
Started Jul 29 06:17:17 PM PDT 24
Finished Jul 29 06:17:19 PM PDT 24
Peak memory 207080 kb
Host smart-0b78caf9-144f-4ac2-b27b-5bb8cafd3552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20195
50501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.2019550501
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1795272257
Short name T1403
Test name
Test status
Simulation time 4767568117 ps
CPU time 50.9 seconds
Started Jul 29 06:17:13 PM PDT 24
Finished Jul 29 06:18:04 PM PDT 24
Peak memory 207372 kb
Host smart-4ee7db34-56db-4ce3-8cca-f99a3a4d4c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17952
72257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1795272257
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.2117747264
Short name T1964
Test name
Test status
Simulation time 562281621 ps
CPU time 11.97 seconds
Started Jul 29 06:17:07 PM PDT 24
Finished Jul 29 06:17:19 PM PDT 24
Peak memory 207260 kb
Host smart-08621c22-fd0e-417e-8445-de57dc6a6a68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117747264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos
t_handshake.2117747264
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.1620798548
Short name T2675
Test name
Test status
Simulation time 49334376 ps
CPU time 0.69 seconds
Started Jul 29 06:17:20 PM PDT 24
Finished Jul 29 06:17:21 PM PDT 24
Peak memory 207144 kb
Host smart-97bea779-a385-44b2-9c69-b46ad8fc0f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1620798548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.1620798548
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3996529979
Short name T2612
Test name
Test status
Simulation time 4353326968 ps
CPU time 7.52 seconds
Started Jul 29 06:17:12 PM PDT 24
Finished Jul 29 06:17:20 PM PDT 24
Peak memory 207404 kb
Host smart-1b1271b7-7610-4116-a46e-2ef08e282924
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996529979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.3996529979
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2121729209
Short name T1819
Test name
Test status
Simulation time 13411249904 ps
CPU time 15.2 seconds
Started Jul 29 06:17:13 PM PDT 24
Finished Jul 29 06:17:28 PM PDT 24
Peak memory 207408 kb
Host smart-a8a47c13-9243-4ab9-bf24-88c1e435a2e2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121729209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2121729209
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.428104145
Short name T1256
Test name
Test status
Simulation time 23352661398 ps
CPU time 31.65 seconds
Started Jul 29 06:17:12 PM PDT 24
Finished Jul 29 06:17:44 PM PDT 24
Peak memory 207424 kb
Host smart-245a14a9-c210-41a4-b038-bb78c10b1e72
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428104145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ao
n_wake_resume.428104145
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.4074454149
Short name T2596
Test name
Test status
Simulation time 196850637 ps
CPU time 0.93 seconds
Started Jul 29 06:17:13 PM PDT 24
Finished Jul 29 06:17:14 PM PDT 24
Peak memory 207076 kb
Host smart-832e8d74-5ab4-408c-b4c2-6067bb8dc885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40744
54149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.4074454149
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.551064169
Short name T917
Test name
Test status
Simulation time 154262814 ps
CPU time 0.82 seconds
Started Jul 29 06:17:16 PM PDT 24
Finished Jul 29 06:17:17 PM PDT 24
Peak memory 207040 kb
Host smart-4b148a63-1552-4b33-907e-9dfebf25043a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55106
4169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.551064169
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2623774960
Short name T895
Test name
Test status
Simulation time 174271579 ps
CPU time 0.87 seconds
Started Jul 29 06:17:13 PM PDT 24
Finished Jul 29 06:17:14 PM PDT 24
Peak memory 207072 kb
Host smart-a7ced23c-0e82-4e36-ae2c-9ecac42c11ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26237
74960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2623774960
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.2154191784
Short name T398
Test name
Test status
Simulation time 1126468200 ps
CPU time 2.89 seconds
Started Jul 29 06:17:12 PM PDT 24
Finished Jul 29 06:17:15 PM PDT 24
Peak memory 207292 kb
Host smart-12ca87ff-1a78-4777-8e34-df9959cd158b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2154191784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.2154191784
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3131061425
Short name T1991
Test name
Test status
Simulation time 16814628352 ps
CPU time 39.5 seconds
Started Jul 29 06:17:12 PM PDT 24
Finished Jul 29 06:17:52 PM PDT 24
Peak memory 207440 kb
Host smart-b69a60ff-6d2d-4457-88bd-b8cfb8434a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31310
61425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3131061425
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.1982361392
Short name T2000
Test name
Test status
Simulation time 847127338 ps
CPU time 18.88 seconds
Started Jul 29 06:17:16 PM PDT 24
Finished Jul 29 06:17:35 PM PDT 24
Peak memory 207140 kb
Host smart-246fdeaf-dea6-48f4-a047-c0d69aaf523a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982361392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.1982361392
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.4029741379
Short name T1953
Test name
Test status
Simulation time 298249891 ps
CPU time 1.19 seconds
Started Jul 29 06:17:13 PM PDT 24
Finished Jul 29 06:17:15 PM PDT 24
Peak memory 207072 kb
Host smart-1ae1100f-1e3d-4969-b0dc-4bdd3f36d03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40297
41379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.4029741379
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.2252400061
Short name T1107
Test name
Test status
Simulation time 229736608 ps
CPU time 0.95 seconds
Started Jul 29 06:17:12 PM PDT 24
Finished Jul 29 06:17:13 PM PDT 24
Peak memory 207036 kb
Host smart-b87918b5-c767-4c51-afda-81f69fc3a6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22524
00061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.2252400061
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.4202118566
Short name T1434
Test name
Test status
Simulation time 51123177 ps
CPU time 0.69 seconds
Started Jul 29 06:17:20 PM PDT 24
Finished Jul 29 06:17:20 PM PDT 24
Peak memory 207080 kb
Host smart-fa54a81e-a199-47b4-b107-67280945d674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42021
18566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.4202118566
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2834431379
Short name T1129
Test name
Test status
Simulation time 860812438 ps
CPU time 2.35 seconds
Started Jul 29 06:17:16 PM PDT 24
Finished Jul 29 06:17:18 PM PDT 24
Peak memory 207292 kb
Host smart-f0da6910-a568-47d2-9f68-409071e712d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28344
31379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2834431379
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3013715468
Short name T184
Test name
Test status
Simulation time 217729901 ps
CPU time 1.78 seconds
Started Jul 29 06:17:21 PM PDT 24
Finished Jul 29 06:17:23 PM PDT 24
Peak memory 207252 kb
Host smart-892705f2-fde5-4cfe-afce-95e2bf6a2979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30137
15468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3013715468
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1003687978
Short name T2039
Test name
Test status
Simulation time 168155681 ps
CPU time 0.97 seconds
Started Jul 29 06:17:17 PM PDT 24
Finished Jul 29 06:17:18 PM PDT 24
Peak memory 207080 kb
Host smart-cfcc078f-3773-480d-a00b-65bda1e73495
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1003687978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1003687978
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1969795530
Short name T1555
Test name
Test status
Simulation time 139630488 ps
CPU time 0.79 seconds
Started Jul 29 06:17:12 PM PDT 24
Finished Jul 29 06:17:13 PM PDT 24
Peak memory 207052 kb
Host smart-c9b3bad0-22f3-46f4-b228-df63631343e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19697
95530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1969795530
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2875707561
Short name T1809
Test name
Test status
Simulation time 249493679 ps
CPU time 1.01 seconds
Started Jul 29 06:17:12 PM PDT 24
Finished Jul 29 06:17:13 PM PDT 24
Peak memory 207056 kb
Host smart-7c4b8495-90d1-4e62-8506-f3f9e11c621c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28757
07561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2875707561
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.3730510731
Short name T2800
Test name
Test status
Simulation time 7639559646 ps
CPU time 234.16 seconds
Started Jul 29 06:17:18 PM PDT 24
Finished Jul 29 06:21:12 PM PDT 24
Peak memory 215648 kb
Host smart-f785f5fa-c794-4e24-8f2b-a79796c81508
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3730510731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.3730510731
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.264292740
Short name T655
Test name
Test status
Simulation time 10205335825 ps
CPU time 65.78 seconds
Started Jul 29 06:17:21 PM PDT 24
Finished Jul 29 06:18:27 PM PDT 24
Peak memory 207400 kb
Host smart-eb767fca-e286-467a-b907-1584f7c2f7ff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=264292740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.264292740
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2269264485
Short name T973
Test name
Test status
Simulation time 189856035 ps
CPU time 0.9 seconds
Started Jul 29 06:17:17 PM PDT 24
Finished Jul 29 06:17:18 PM PDT 24
Peak memory 207104 kb
Host smart-f2ff62b6-6232-4be2-b128-6882bfdeb0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22692
64485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2269264485
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.2668508947
Short name T2706
Test name
Test status
Simulation time 23335062195 ps
CPU time 27.65 seconds
Started Jul 29 06:17:16 PM PDT 24
Finished Jul 29 06:17:44 PM PDT 24
Peak memory 207528 kb
Host smart-7fa70db8-83a2-472e-9f0d-c945d933146a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26685
08947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.2668508947
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2610210597
Short name T415
Test name
Test status
Simulation time 3354234312 ps
CPU time 5.38 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:27 PM PDT 24
Peak memory 207316 kb
Host smart-e0528802-0a7a-4201-a105-608ee9fce02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102
10597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2610210597
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.2310248135
Short name T1338
Test name
Test status
Simulation time 9901814064 ps
CPU time 271.51 seconds
Started Jul 29 06:17:16 PM PDT 24
Finished Jul 29 06:21:48 PM PDT 24
Peak memory 215544 kb
Host smart-6bb7e970-0bd9-4aa6-a319-fd48be4b6e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23102
48135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.2310248135
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.1059607116
Short name T1925
Test name
Test status
Simulation time 3513925784 ps
CPU time 38.39 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:18:00 PM PDT 24
Peak memory 216804 kb
Host smart-82b41d84-113b-4998-b1b9-2623c1fe72b7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1059607116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.1059607116
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.557527453
Short name T2798
Test name
Test status
Simulation time 251828850 ps
CPU time 0.97 seconds
Started Jul 29 06:17:15 PM PDT 24
Finished Jul 29 06:17:16 PM PDT 24
Peak memory 207112 kb
Host smart-c1a0566f-6c02-4273-be4e-23cc1cd17fa6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=557527453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.557527453
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3149539230
Short name T1417
Test name
Test status
Simulation time 189006030 ps
CPU time 0.96 seconds
Started Jul 29 06:17:18 PM PDT 24
Finished Jul 29 06:17:19 PM PDT 24
Peak memory 207052 kb
Host smart-cab3b43c-638f-4c59-9e01-b82e6e8c2196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31495
39230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3149539230
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.2683340135
Short name T234
Test name
Test status
Simulation time 4965477357 ps
CPU time 142.61 seconds
Started Jul 29 06:17:19 PM PDT 24
Finished Jul 29 06:19:42 PM PDT 24
Peak memory 215624 kb
Host smart-d64b9400-0c15-43b7-add9-b87f539a9877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26833
40135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.2683340135
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.1502519425
Short name T400
Test name
Test status
Simulation time 4531387405 ps
CPU time 131 seconds
Started Jul 29 06:17:17 PM PDT 24
Finished Jul 29 06:19:28 PM PDT 24
Peak memory 215556 kb
Host smart-29e83f13-6b7f-4462-97bf-f3121ea6d238
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1502519425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.1502519425
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.254681979
Short name T506
Test name
Test status
Simulation time 162702865 ps
CPU time 0.86 seconds
Started Jul 29 06:17:17 PM PDT 24
Finished Jul 29 06:17:18 PM PDT 24
Peak memory 207116 kb
Host smart-180d2b8d-0c8f-4d94-ada1-9181a75c1329
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=254681979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.254681979
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3048420110
Short name T1634
Test name
Test status
Simulation time 160115588 ps
CPU time 0.81 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:23 PM PDT 24
Peak memory 207120 kb
Host smart-b53d006f-51c6-4f9d-932e-8d7a6ef2a7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30484
20110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3048420110
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.4024174766
Short name T131
Test name
Test status
Simulation time 248046363 ps
CPU time 1 seconds
Started Jul 29 06:17:21 PM PDT 24
Finished Jul 29 06:17:22 PM PDT 24
Peak memory 207116 kb
Host smart-26bd7941-e3a9-443e-980c-3bb2deb484b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40241
74766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.4024174766
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.3990078476
Short name T549
Test name
Test status
Simulation time 159420249 ps
CPU time 0.96 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:23 PM PDT 24
Peak memory 207112 kb
Host smart-c478b1f3-7b88-4702-8ccc-7ebbac784c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39900
78476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3990078476
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3002318599
Short name T1020
Test name
Test status
Simulation time 174409960 ps
CPU time 0.94 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:23 PM PDT 24
Peak memory 207136 kb
Host smart-f5bc44d2-a3f8-4058-acbc-42aab50af005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30023
18599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3002318599
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2621490309
Short name T1035
Test name
Test status
Simulation time 175430406 ps
CPU time 0.92 seconds
Started Jul 29 06:17:20 PM PDT 24
Finished Jul 29 06:17:21 PM PDT 24
Peak memory 207100 kb
Host smart-6ecea77c-934d-452b-822b-2d0d97f067bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26214
90309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2621490309
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1129348972
Short name T687
Test name
Test status
Simulation time 155667649 ps
CPU time 0.94 seconds
Started Jul 29 06:17:19 PM PDT 24
Finished Jul 29 06:17:20 PM PDT 24
Peak memory 207100 kb
Host smart-c3623bbb-1a57-4d77-b139-69b69d766cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11293
48972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1129348972
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.2814975586
Short name T2471
Test name
Test status
Simulation time 216737212 ps
CPU time 0.99 seconds
Started Jul 29 06:17:17 PM PDT 24
Finished Jul 29 06:17:19 PM PDT 24
Peak memory 207124 kb
Host smart-567415f2-ffca-4b73-912d-01ee2cb74dda
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2814975586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.2814975586
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.4098071602
Short name T485
Test name
Test status
Simulation time 158502932 ps
CPU time 0.89 seconds
Started Jul 29 06:17:21 PM PDT 24
Finished Jul 29 06:17:22 PM PDT 24
Peak memory 206836 kb
Host smart-25a216b5-1225-4452-840e-f09450df14c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40980
71602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.4098071602
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.881992470
Short name T1295
Test name
Test status
Simulation time 130321915 ps
CPU time 0.81 seconds
Started Jul 29 06:17:19 PM PDT 24
Finished Jul 29 06:17:20 PM PDT 24
Peak memory 207048 kb
Host smart-89bad41f-9ee4-4a0e-a00a-55e3db0a48ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88199
2470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.881992470
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1918212829
Short name T1317
Test name
Test status
Simulation time 18708618099 ps
CPU time 48.64 seconds
Started Jul 29 06:17:20 PM PDT 24
Finished Jul 29 06:18:09 PM PDT 24
Peak memory 219972 kb
Host smart-068ba07e-eae8-427d-9334-a5810f698c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19182
12829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1918212829
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2724396929
Short name T521
Test name
Test status
Simulation time 146094078 ps
CPU time 0.82 seconds
Started Jul 29 06:17:21 PM PDT 24
Finished Jul 29 06:17:22 PM PDT 24
Peak memory 206852 kb
Host smart-66c934e9-41d9-49ca-ba21-dcf7f4738a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27243
96929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2724396929
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.189850981
Short name T2788
Test name
Test status
Simulation time 210195442 ps
CPU time 0.96 seconds
Started Jul 29 06:17:20 PM PDT 24
Finished Jul 29 06:17:21 PM PDT 24
Peak memory 207068 kb
Host smart-f968f5b2-1233-4cff-abc8-6caea5037176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18985
0981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.189850981
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.2232696297
Short name T340
Test name
Test status
Simulation time 170814564 ps
CPU time 0.88 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:23 PM PDT 24
Peak memory 207116 kb
Host smart-d7892d84-0f17-4e90-97fe-9b3776d4641e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22326
96297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2232696297
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.1277945538
Short name T448
Test name
Test status
Simulation time 203703970 ps
CPU time 0.94 seconds
Started Jul 29 06:17:17 PM PDT 24
Finished Jul 29 06:17:18 PM PDT 24
Peak memory 207080 kb
Host smart-e4b72743-ecd3-4a2e-8424-673afe18e063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12779
45538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.1277945538
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2217183852
Short name T2787
Test name
Test status
Simulation time 165228676 ps
CPU time 0.85 seconds
Started Jul 29 06:17:19 PM PDT 24
Finished Jul 29 06:17:20 PM PDT 24
Peak memory 207084 kb
Host smart-0160959b-1806-46eb-a855-bf1f776e7936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22171
83852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2217183852
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.591165479
Short name T585
Test name
Test status
Simulation time 192174801 ps
CPU time 0.9 seconds
Started Jul 29 06:17:21 PM PDT 24
Finished Jul 29 06:17:22 PM PDT 24
Peak memory 207060 kb
Host smart-5dac9067-ee31-4ab2-bf87-faa44cde0828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59116
5479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.591165479
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.314603264
Short name T2419
Test name
Test status
Simulation time 220263209 ps
CPU time 1.02 seconds
Started Jul 29 06:17:21 PM PDT 24
Finished Jul 29 06:17:22 PM PDT 24
Peak memory 207100 kb
Host smart-989f7807-b563-4cab-8a6a-c107231885f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31460
3264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.314603264
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3005703874
Short name T1884
Test name
Test status
Simulation time 210746397 ps
CPU time 1 seconds
Started Jul 29 06:17:21 PM PDT 24
Finished Jul 29 06:17:22 PM PDT 24
Peak memory 206848 kb
Host smart-22c29e86-5dff-47d6-bb43-1d66f552d5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30057
03874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3005703874
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.2620862295
Short name T2116
Test name
Test status
Simulation time 5444290131 ps
CPU time 158 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:20:00 PM PDT 24
Peak memory 215584 kb
Host smart-79f7d42a-6b9a-4f65-bebd-29565ff01ffd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2620862295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.2620862295
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3394205151
Short name T1051
Test name
Test status
Simulation time 148456351 ps
CPU time 0.85 seconds
Started Jul 29 06:17:20 PM PDT 24
Finished Jul 29 06:17:21 PM PDT 24
Peak memory 207128 kb
Host smart-75f90697-835b-4c42-9cae-3bb4d6dbf05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33942
05151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3394205151
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.198365794
Short name T1926
Test name
Test status
Simulation time 165212518 ps
CPU time 0.87 seconds
Started Jul 29 06:17:17 PM PDT 24
Finished Jul 29 06:17:18 PM PDT 24
Peak memory 207148 kb
Host smart-489a583c-d190-4f6f-8589-a1efc73db0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19836
5794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.198365794
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.1662447186
Short name T1657
Test name
Test status
Simulation time 820641791 ps
CPU time 2.16 seconds
Started Jul 29 06:17:16 PM PDT 24
Finished Jul 29 06:17:18 PM PDT 24
Peak memory 207160 kb
Host smart-68857c57-fbcb-4211-9ae4-13b5db6c3146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16624
47186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.1662447186
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1685313876
Short name T1626
Test name
Test status
Simulation time 5964868427 ps
CPU time 168.82 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:20:11 PM PDT 24
Peak memory 215336 kb
Host smart-15e7a092-81e2-42a2-8e48-2585bf91cc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16853
13876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1685313876
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.3944636489
Short name T1100
Test name
Test status
Simulation time 747359399 ps
CPU time 15.34 seconds
Started Jul 29 06:17:14 PM PDT 24
Finished Jul 29 06:17:29 PM PDT 24
Peak memory 207356 kb
Host smart-aa980f9d-a68c-4d81-97b2-28da590118b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944636489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.3944636489
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.3673138714
Short name T996
Test name
Test status
Simulation time 41696525 ps
CPU time 0.66 seconds
Started Jul 29 06:17:38 PM PDT 24
Finished Jul 29 06:17:39 PM PDT 24
Peak memory 207100 kb
Host smart-fd830bfc-ee70-4fe8-96f9-b517c3b24eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3673138714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.3673138714
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.530435826
Short name T700
Test name
Test status
Simulation time 3572549179 ps
CPU time 5.29 seconds
Started Jul 29 06:17:24 PM PDT 24
Finished Jul 29 06:17:29 PM PDT 24
Peak memory 207296 kb
Host smart-b0f737d1-fc9e-4ed8-a4b2-2976fc308cad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530435826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_ao
n_wake_disconnect.530435826
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.2721128591
Short name T2502
Test name
Test status
Simulation time 13356883819 ps
CPU time 16.43 seconds
Started Jul 29 06:17:21 PM PDT 24
Finished Jul 29 06:17:37 PM PDT 24
Peak memory 207388 kb
Host smart-9e5914fd-c139-4b00-a812-a552c5d37732
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721128591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.2721128591
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.492938786
Short name T1101
Test name
Test status
Simulation time 23368274637 ps
CPU time 32.06 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:54 PM PDT 24
Peak memory 207552 kb
Host smart-2e69c27c-abb2-400b-9a40-bbefd5528666
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492938786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_ao
n_wake_resume.492938786
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3364834974
Short name T554
Test name
Test status
Simulation time 166391097 ps
CPU time 0.87 seconds
Started Jul 29 06:17:23 PM PDT 24
Finished Jul 29 06:17:24 PM PDT 24
Peak memory 207124 kb
Host smart-79600e49-e947-4126-b214-fa2f519b3bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33648
34974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3364834974
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3416615413
Short name T775
Test name
Test status
Simulation time 163038006 ps
CPU time 0.93 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:23 PM PDT 24
Peak memory 206968 kb
Host smart-4d469daa-f8fa-479d-862f-9c7a00359b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34166
15413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3416615413
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.2272060763
Short name T2241
Test name
Test status
Simulation time 189190941 ps
CPU time 0.96 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:23 PM PDT 24
Peak memory 207060 kb
Host smart-f10ac210-75bb-4e25-97ee-53444045f38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22720
60763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.2272060763
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.62938800
Short name T2404
Test name
Test status
Simulation time 468552463 ps
CPU time 1.47 seconds
Started Jul 29 06:17:24 PM PDT 24
Finished Jul 29 06:17:26 PM PDT 24
Peak memory 207128 kb
Host smart-2e093c34-49d5-4898-bc69-c8df0d907c15
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=62938800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.62938800
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.2211196383
Short name T2190
Test name
Test status
Simulation time 6593818320 ps
CPU time 14.01 seconds
Started Jul 29 06:17:24 PM PDT 24
Finished Jul 29 06:17:38 PM PDT 24
Peak memory 207444 kb
Host smart-0b1038d4-22ac-402d-a166-444c2fdeca04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22111
96383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.2211196383
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.2453015423
Short name T2528
Test name
Test status
Simulation time 605174296 ps
CPU time 5.53 seconds
Started Jul 29 06:17:24 PM PDT 24
Finished Jul 29 06:17:29 PM PDT 24
Peak memory 207324 kb
Host smart-4d41bedc-43b0-4a11-9ab8-1a99ddf4df37
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453015423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.2453015423
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.3387026301
Short name T1569
Test name
Test status
Simulation time 423365869 ps
CPU time 1.44 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:24 PM PDT 24
Peak memory 207032 kb
Host smart-a1723c09-34e6-41df-bf42-7ff474227af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33870
26301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.3387026301
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1739818982
Short name T2236
Test name
Test status
Simulation time 143558351 ps
CPU time 0.82 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:23 PM PDT 24
Peak memory 207072 kb
Host smart-f615a818-a7d6-439f-9c32-e90937163955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17398
18982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1739818982
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3824137380
Short name T1522
Test name
Test status
Simulation time 37134491 ps
CPU time 0.71 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:23 PM PDT 24
Peak memory 207040 kb
Host smart-581f4284-6e3d-4e28-9453-c65c21374438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38241
37380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3824137380
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3954166547
Short name T346
Test name
Test status
Simulation time 1003133970 ps
CPU time 2.58 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:25 PM PDT 24
Peak memory 207312 kb
Host smart-37ecd91b-5bac-4c49-ab76-0b8913a51e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39541
66547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3954166547
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.896575117
Short name T2457
Test name
Test status
Simulation time 280433859 ps
CPU time 2.08 seconds
Started Jul 29 06:17:23 PM PDT 24
Finished Jul 29 06:17:25 PM PDT 24
Peak memory 207256 kb
Host smart-0eb1a02e-84cf-44ce-8cad-c00cb91d842e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89657
5117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.896575117
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.4177882989
Short name T518
Test name
Test status
Simulation time 181908180 ps
CPU time 1.04 seconds
Started Jul 29 06:17:34 PM PDT 24
Finished Jul 29 06:17:35 PM PDT 24
Peak memory 207220 kb
Host smart-908e28ed-34d1-40f2-b667-119b0f6be2f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4177882989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.4177882989
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4219758009
Short name T1254
Test name
Test status
Simulation time 143455536 ps
CPU time 0.83 seconds
Started Jul 29 06:17:27 PM PDT 24
Finished Jul 29 06:17:28 PM PDT 24
Peak memory 207236 kb
Host smart-85007b03-af7b-4621-bf07-701630535530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42197
58009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4219758009
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.15449703
Short name T2446
Test name
Test status
Simulation time 226189830 ps
CPU time 0.99 seconds
Started Jul 29 06:17:29 PM PDT 24
Finished Jul 29 06:17:30 PM PDT 24
Peak memory 207112 kb
Host smart-246842bf-ece3-4efb-b528-7660d35a0a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15449
703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.15449703
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.2291440116
Short name T2296
Test name
Test status
Simulation time 5586345576 ps
CPU time 44.06 seconds
Started Jul 29 06:17:20 PM PDT 24
Finished Jul 29 06:18:05 PM PDT 24
Peak memory 217216 kb
Host smart-bd67e0aa-65b5-412b-af1e-93da1d49785b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2291440116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.2291440116
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.4251962393
Short name T2793
Test name
Test status
Simulation time 10432010460 ps
CPU time 71.42 seconds
Started Jul 29 06:17:27 PM PDT 24
Finished Jul 29 06:18:39 PM PDT 24
Peak memory 207348 kb
Host smart-7eff7411-1d2a-43ae-858a-4f4d8dcb50e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4251962393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.4251962393
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.256586792
Short name T688
Test name
Test status
Simulation time 156960359 ps
CPU time 0.94 seconds
Started Jul 29 06:17:29 PM PDT 24
Finished Jul 29 06:17:30 PM PDT 24
Peak memory 207100 kb
Host smart-7eac162e-ed42-4296-ba2a-fe2d6c0d0c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25658
6792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.256586792
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.652890603
Short name T498
Test name
Test status
Simulation time 23332310038 ps
CPU time 32.74 seconds
Started Jul 29 06:17:31 PM PDT 24
Finished Jul 29 06:18:03 PM PDT 24
Peak memory 207392 kb
Host smart-66d0607c-1a29-47a3-9d4a-f16f4410e434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65289
0603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.652890603
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.3621677362
Short name T979
Test name
Test status
Simulation time 3334716840 ps
CPU time 4.68 seconds
Started Jul 29 06:17:31 PM PDT 24
Finished Jul 29 06:17:36 PM PDT 24
Peak memory 207308 kb
Host smart-e1ff2d75-39c4-4d50-a1a2-be63e66cdebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36216
77362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3621677362
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2160789890
Short name T1816
Test name
Test status
Simulation time 5048978900 ps
CPU time 139.97 seconds
Started Jul 29 06:17:33 PM PDT 24
Finished Jul 29 06:19:54 PM PDT 24
Peak memory 215520 kb
Host smart-59734dc1-b994-40ef-abe0-606bb5d3c954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21607
89890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2160789890
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3876400196
Short name T2183
Test name
Test status
Simulation time 5331433439 ps
CPU time 157.62 seconds
Started Jul 29 06:17:27 PM PDT 24
Finished Jul 29 06:20:05 PM PDT 24
Peak memory 215584 kb
Host smart-2ef3c00e-9590-4f16-a97b-c38469d80ea5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3876400196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3876400196
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.430710480
Short name T569
Test name
Test status
Simulation time 236995813 ps
CPU time 1.11 seconds
Started Jul 29 06:17:33 PM PDT 24
Finished Jul 29 06:17:35 PM PDT 24
Peak memory 207056 kb
Host smart-c84ce8d9-a96e-4d42-850c-29f361043ccf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=430710480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.430710480
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.3560710092
Short name T109
Test name
Test status
Simulation time 192971062 ps
CPU time 1.02 seconds
Started Jul 29 06:17:28 PM PDT 24
Finished Jul 29 06:17:29 PM PDT 24
Peak memory 207096 kb
Host smart-7286a7ab-09d8-4afc-8e42-9b9aa02f44f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35607
10092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.3560710092
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.2428559429
Short name T2108
Test name
Test status
Simulation time 3726736078 ps
CPU time 117.82 seconds
Started Jul 29 06:17:33 PM PDT 24
Finished Jul 29 06:19:31 PM PDT 24
Peak memory 215556 kb
Host smart-0586be44-7f54-4ba8-966e-c245259f04cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24285
59429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.2428559429
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.3363693570
Short name T597
Test name
Test status
Simulation time 5592415801 ps
CPU time 55.83 seconds
Started Jul 29 06:17:27 PM PDT 24
Finished Jul 29 06:18:23 PM PDT 24
Peak memory 216896 kb
Host smart-012fb345-6b03-4daf-bb5b-60b07267737c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3363693570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.3363693570
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2787748734
Short name T748
Test name
Test status
Simulation time 163108425 ps
CPU time 0.84 seconds
Started Jul 29 06:17:30 PM PDT 24
Finished Jul 29 06:17:31 PM PDT 24
Peak memory 207108 kb
Host smart-0f5e02f3-7ab9-4618-a8f1-288abc94313a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2787748734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2787748734
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.340849260
Short name T2808
Test name
Test status
Simulation time 141929833 ps
CPU time 0.84 seconds
Started Jul 29 06:17:28 PM PDT 24
Finished Jul 29 06:17:29 PM PDT 24
Peak memory 207060 kb
Host smart-5136696c-47e6-4208-a7d5-98e56e67da2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34084
9260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.340849260
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.422786375
Short name T880
Test name
Test status
Simulation time 160844634 ps
CPU time 0.86 seconds
Started Jul 29 06:17:28 PM PDT 24
Finished Jul 29 06:17:29 PM PDT 24
Peak memory 207020 kb
Host smart-1f6947c6-473a-4bae-abbb-0e3de1b357d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42278
6375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.422786375
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2414117926
Short name T2825
Test name
Test status
Simulation time 193025489 ps
CPU time 0.89 seconds
Started Jul 29 06:17:27 PM PDT 24
Finished Jul 29 06:17:28 PM PDT 24
Peak memory 207140 kb
Host smart-1ff38494-dabd-42cd-9b54-e25c90d85501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24141
17926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2414117926
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2491540581
Short name T1888
Test name
Test status
Simulation time 173978466 ps
CPU time 0.89 seconds
Started Jul 29 06:17:32 PM PDT 24
Finished Jul 29 06:17:34 PM PDT 24
Peak memory 207092 kb
Host smart-13909dbb-2763-48d6-8939-d62a46edb3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24915
40581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2491540581
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.301964162
Short name T177
Test name
Test status
Simulation time 147606498 ps
CPU time 0.94 seconds
Started Jul 29 06:17:28 PM PDT 24
Finished Jul 29 06:17:29 PM PDT 24
Peak memory 207136 kb
Host smart-576d6dbc-74aa-4c07-a7f4-d6b8f24fe250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30196
4162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.301964162
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1531664473
Short name T2809
Test name
Test status
Simulation time 225419354 ps
CPU time 1.01 seconds
Started Jul 29 06:17:27 PM PDT 24
Finished Jul 29 06:17:28 PM PDT 24
Peak memory 207112 kb
Host smart-a6b194a4-4ba5-4fb5-a2ad-f26b2d701304
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1531664473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1531664473
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1879314073
Short name T2320
Test name
Test status
Simulation time 142651874 ps
CPU time 0.8 seconds
Started Jul 29 06:17:29 PM PDT 24
Finished Jul 29 06:17:30 PM PDT 24
Peak memory 207064 kb
Host smart-1e9dda2f-4456-4988-ab44-e3ab57e3d27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18793
14073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1879314073
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.4294318794
Short name T2152
Test name
Test status
Simulation time 35379872 ps
CPU time 0.67 seconds
Started Jul 29 06:17:27 PM PDT 24
Finished Jul 29 06:17:28 PM PDT 24
Peak memory 207028 kb
Host smart-a06bcb02-fc9c-4bd7-9d53-6343926aa3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42943
18794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.4294318794
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2592858163
Short name T108
Test name
Test status
Simulation time 10464446597 ps
CPU time 25.67 seconds
Started Jul 29 06:17:26 PM PDT 24
Finished Jul 29 06:17:52 PM PDT 24
Peak memory 219984 kb
Host smart-0f133751-57b0-44c8-a0e4-f39146a3a5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25928
58163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2592858163
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.641936007
Short name T1703
Test name
Test status
Simulation time 177236866 ps
CPU time 0.91 seconds
Started Jul 29 06:17:35 PM PDT 24
Finished Jul 29 06:17:36 PM PDT 24
Peak memory 207028 kb
Host smart-c82b3773-1685-4a06-9b3c-86a4a7f858a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64193
6007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.641936007
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2843729116
Short name T607
Test name
Test status
Simulation time 285373409 ps
CPU time 1.17 seconds
Started Jul 29 06:17:35 PM PDT 24
Finished Jul 29 06:17:37 PM PDT 24
Peak memory 207004 kb
Host smart-31be5d81-f620-45c2-977b-f1a4f4eda8b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28437
29116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2843729116
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.783556089
Short name T1326
Test name
Test status
Simulation time 171757094 ps
CPU time 0.88 seconds
Started Jul 29 06:17:32 PM PDT 24
Finished Jul 29 06:17:33 PM PDT 24
Peak memory 207104 kb
Host smart-cb5707b4-273d-4eed-acce-89bd70fe1e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78355
6089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.783556089
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.69362462
Short name T2592
Test name
Test status
Simulation time 164494737 ps
CPU time 0.93 seconds
Started Jul 29 06:17:29 PM PDT 24
Finished Jul 29 06:17:30 PM PDT 24
Peak memory 207124 kb
Host smart-f0c2169c-0477-40de-8573-80c1a5622b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69362
462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.69362462
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.81061663
Short name T2265
Test name
Test status
Simulation time 149594272 ps
CPU time 0.8 seconds
Started Jul 29 06:17:32 PM PDT 24
Finished Jul 29 06:17:32 PM PDT 24
Peak memory 207104 kb
Host smart-35958df9-31ce-4348-a7ff-9b287bcc5615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81061
663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.81061663
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.3725915152
Short name T1448
Test name
Test status
Simulation time 168047711 ps
CPU time 0.84 seconds
Started Jul 29 06:17:35 PM PDT 24
Finished Jul 29 06:17:36 PM PDT 24
Peak memory 207060 kb
Host smart-03df4e60-aef7-4acb-9acc-74a96a0c50eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37259
15152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3725915152
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.905443723
Short name T1982
Test name
Test status
Simulation time 157327563 ps
CPU time 0.94 seconds
Started Jul 29 06:17:33 PM PDT 24
Finished Jul 29 06:17:34 PM PDT 24
Peak memory 207072 kb
Host smart-85ba2d32-3054-488a-b17b-01b12bc11d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90544
3723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.905443723
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3960839613
Short name T53
Test name
Test status
Simulation time 229540777 ps
CPU time 1 seconds
Started Jul 29 06:17:32 PM PDT 24
Finished Jul 29 06:17:33 PM PDT 24
Peak memory 207044 kb
Host smart-4b9cfb87-c18b-4652-9223-ce440c78f2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39608
39613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3960839613
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.3752387261
Short name T1622
Test name
Test status
Simulation time 6561401349 ps
CPU time 52.29 seconds
Started Jul 29 06:17:32 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 215608 kb
Host smart-ed7bdbce-ad1d-49db-9e8e-c3f9cdc72bd2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3752387261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.3752387261
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.989800003
Short name T473
Test name
Test status
Simulation time 175269652 ps
CPU time 0.9 seconds
Started Jul 29 06:17:37 PM PDT 24
Finished Jul 29 06:17:38 PM PDT 24
Peak memory 207000 kb
Host smart-e35eab19-a808-4a56-9629-7ca0a29c737f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98980
0003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.989800003
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.4142167716
Short name T394
Test name
Test status
Simulation time 207233988 ps
CPU time 0.94 seconds
Started Jul 29 06:17:32 PM PDT 24
Finished Jul 29 06:17:34 PM PDT 24
Peak memory 207040 kb
Host smart-5e957b65-168e-4ece-ade1-51ecc514f75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41421
67716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.4142167716
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.1298341401
Short name T419
Test name
Test status
Simulation time 995639299 ps
CPU time 2.86 seconds
Started Jul 29 06:17:33 PM PDT 24
Finished Jul 29 06:17:36 PM PDT 24
Peak memory 207248 kb
Host smart-8144a69a-4c93-44cb-84a1-b2f0c68bc65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12983
41401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.1298341401
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.4208937474
Short name T633
Test name
Test status
Simulation time 3195283188 ps
CPU time 23.7 seconds
Started Jul 29 06:17:35 PM PDT 24
Finished Jul 29 06:17:59 PM PDT 24
Peak memory 217140 kb
Host smart-96653165-6c1a-451b-8e53-6261501492a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42089
37474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.4208937474
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.2543811402
Short name T1180
Test name
Test status
Simulation time 818473760 ps
CPU time 19.31 seconds
Started Jul 29 06:17:22 PM PDT 24
Finished Jul 29 06:17:42 PM PDT 24
Peak memory 207264 kb
Host smart-ee3eab98-2645-401a-81fc-6c8143485207
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543811402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.2543811402
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.3697812710
Short name T1356
Test name
Test status
Simulation time 36634448 ps
CPU time 0.68 seconds
Started Jul 29 06:17:44 PM PDT 24
Finished Jul 29 06:17:45 PM PDT 24
Peak memory 207112 kb
Host smart-953efd4b-eec9-4608-9a3d-ca0f74dfcac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3697812710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.3697812710
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.396669073
Short name T1397
Test name
Test status
Simulation time 4160227989 ps
CPU time 5.7 seconds
Started Jul 29 06:17:32 PM PDT 24
Finished Jul 29 06:17:38 PM PDT 24
Peak memory 207376 kb
Host smart-b6fb7ccb-cd4b-443b-81ee-e90dd6d9278d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396669073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ao
n_wake_disconnect.396669073
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.383517131
Short name T2834
Test name
Test status
Simulation time 13376608318 ps
CPU time 15.96 seconds
Started Jul 29 06:17:32 PM PDT 24
Finished Jul 29 06:17:49 PM PDT 24
Peak memory 207380 kb
Host smart-a1c7c7cc-46f0-4169-8248-c334eba4b852
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=383517131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.383517131
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3695542877
Short name T492
Test name
Test status
Simulation time 23424150400 ps
CPU time 31.72 seconds
Started Jul 29 06:17:37 PM PDT 24
Finished Jul 29 06:18:08 PM PDT 24
Peak memory 207440 kb
Host smart-71468d26-0937-46da-bdc3-422432266a18
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695542877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_resume.3695542877
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3790860388
Short name T2582
Test name
Test status
Simulation time 195290345 ps
CPU time 0.98 seconds
Started Jul 29 06:17:31 PM PDT 24
Finished Jul 29 06:17:32 PM PDT 24
Peak memory 207124 kb
Host smart-5b222b92-0ec3-4ba1-92df-f95479b6967a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37908
60388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3790860388
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1200845409
Short name T953
Test name
Test status
Simulation time 172462187 ps
CPU time 0.93 seconds
Started Jul 29 06:17:33 PM PDT 24
Finished Jul 29 06:17:34 PM PDT 24
Peak memory 207060 kb
Host smart-3b26af76-d04a-4560-863b-b9316f312a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12008
45409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1200845409
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.4214154272
Short name T328
Test name
Test status
Simulation time 342054256 ps
CPU time 1.35 seconds
Started Jul 29 06:17:33 PM PDT 24
Finished Jul 29 06:17:35 PM PDT 24
Peak memory 207116 kb
Host smart-9223f19f-6c6d-44bf-9b2e-fbf91d1e6940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42141
54272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.4214154272
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3105805777
Short name T2488
Test name
Test status
Simulation time 1048938811 ps
CPU time 2.51 seconds
Started Jul 29 06:17:34 PM PDT 24
Finished Jul 29 06:17:37 PM PDT 24
Peak memory 207248 kb
Host smart-a393c2ed-db0d-4305-9424-f7b5d2e230b4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3105805777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3105805777
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.3669040693
Short name T680
Test name
Test status
Simulation time 14318630440 ps
CPU time 30.78 seconds
Started Jul 29 06:17:36 PM PDT 24
Finished Jul 29 06:18:07 PM PDT 24
Peak memory 207400 kb
Host smart-76aeef68-dd0c-44b1-8eaa-cacf834712b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36690
40693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3669040693
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.4218217762
Short name T946
Test name
Test status
Simulation time 1129108151 ps
CPU time 9.07 seconds
Started Jul 29 06:17:32 PM PDT 24
Finished Jul 29 06:17:41 PM PDT 24
Peak memory 207328 kb
Host smart-7290bbcc-4b34-475f-9d96-1b02cf7fb104
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218217762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.4218217762
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2152262258
Short name T2429
Test name
Test status
Simulation time 446543309 ps
CPU time 1.45 seconds
Started Jul 29 06:17:35 PM PDT 24
Finished Jul 29 06:17:36 PM PDT 24
Peak memory 207084 kb
Host smart-55f70913-2186-42c5-9ea7-fcde1be682be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21522
62258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2152262258
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1287566467
Short name T2458
Test name
Test status
Simulation time 155510499 ps
CPU time 0.8 seconds
Started Jul 29 06:17:36 PM PDT 24
Finished Jul 29 06:17:37 PM PDT 24
Peak memory 207088 kb
Host smart-f6b4e4e0-9385-4f53-be02-cf7304a7469c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12875
66467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1287566467
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2816153312
Short name T1447
Test name
Test status
Simulation time 47157219 ps
CPU time 0.69 seconds
Started Jul 29 06:17:34 PM PDT 24
Finished Jul 29 06:17:35 PM PDT 24
Peak memory 207084 kb
Host smart-f7cd8552-265d-4cc4-b869-15750d032f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28161
53312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2816153312
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.895665979
Short name T1932
Test name
Test status
Simulation time 711510538 ps
CPU time 2.01 seconds
Started Jul 29 06:17:36 PM PDT 24
Finished Jul 29 06:17:38 PM PDT 24
Peak memory 207304 kb
Host smart-cf9fbd5d-9f13-4d73-aa82-2a74c2a09ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89566
5979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.895665979
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3669623146
Short name T723
Test name
Test status
Simulation time 351436803 ps
CPU time 2.53 seconds
Started Jul 29 06:17:33 PM PDT 24
Finished Jul 29 06:17:36 PM PDT 24
Peak memory 207172 kb
Host smart-6ec77475-1664-405e-8ea8-bdba72effd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36696
23146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3669623146
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2850675850
Short name T2530
Test name
Test status
Simulation time 240927195 ps
CPU time 1.02 seconds
Started Jul 29 06:17:36 PM PDT 24
Finished Jul 29 06:17:37 PM PDT 24
Peak memory 207004 kb
Host smart-ad2212ed-fec1-471c-a9c1-d89ff7454a5e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2850675850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2850675850
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1845843864
Short name T1459
Test name
Test status
Simulation time 147522174 ps
CPU time 0.85 seconds
Started Jul 29 06:17:41 PM PDT 24
Finished Jul 29 06:17:42 PM PDT 24
Peak memory 207044 kb
Host smart-ad8e3c98-e6be-4c99-b588-05a68c80b14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18458
43864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1845843864
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3143364322
Short name T2347
Test name
Test status
Simulation time 232976270 ps
CPU time 1.01 seconds
Started Jul 29 06:17:44 PM PDT 24
Finished Jul 29 06:17:46 PM PDT 24
Peak memory 207108 kb
Host smart-9c09fbfc-06a3-43fa-b4af-ba1c78caa89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31433
64322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3143364322
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.1653995378
Short name T5
Test name
Test status
Simulation time 6417374997 ps
CPU time 50.57 seconds
Started Jul 29 06:17:33 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 207428 kb
Host smart-29effb98-ca3b-4f0f-9b49-2369033f779a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1653995378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.1653995378
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.3583574232
Short name T2017
Test name
Test status
Simulation time 10818131314 ps
CPU time 130.03 seconds
Started Jul 29 06:17:40 PM PDT 24
Finished Jul 29 06:19:50 PM PDT 24
Peak memory 207352 kb
Host smart-fc8bc116-1a1f-46a3-92f8-2ea74bc78886
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3583574232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.3583574232
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.2431536889
Short name T2120
Test name
Test status
Simulation time 229139312 ps
CPU time 1.01 seconds
Started Jul 29 06:17:44 PM PDT 24
Finished Jul 29 06:17:45 PM PDT 24
Peak memory 207108 kb
Host smart-df107d23-94e5-4483-ac87-d7e5770493ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24315
36889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.2431536889
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.375887676
Short name T1601
Test name
Test status
Simulation time 23333556557 ps
CPU time 33.86 seconds
Started Jul 29 06:17:40 PM PDT 24
Finished Jul 29 06:18:14 PM PDT 24
Peak memory 207348 kb
Host smart-8d5dd4b1-532f-4085-956e-52c8197877a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37588
7676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.375887676
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2732880541
Short name T2835
Test name
Test status
Simulation time 3297362841 ps
CPU time 4.83 seconds
Started Jul 29 06:17:38 PM PDT 24
Finished Jul 29 06:17:43 PM PDT 24
Peak memory 207248 kb
Host smart-f865161a-b1f5-463c-88e6-d405bc99bfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27328
80541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2732880541
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.3547111130
Short name T1521
Test name
Test status
Simulation time 9205413524 ps
CPU time 277.76 seconds
Started Jul 29 06:17:36 PM PDT 24
Finished Jul 29 06:22:14 PM PDT 24
Peak memory 215576 kb
Host smart-575236df-ee37-459c-a1a0-daaaafbc40e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35471
11130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.3547111130
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3092136700
Short name T111
Test name
Test status
Simulation time 3958833840 ps
CPU time 113.18 seconds
Started Jul 29 06:17:42 PM PDT 24
Finished Jul 29 06:19:35 PM PDT 24
Peak memory 215512 kb
Host smart-b05c4972-d867-4cdf-bfdf-b67109826180
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3092136700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3092136700
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1696560701
Short name T1436
Test name
Test status
Simulation time 266423866 ps
CPU time 1.06 seconds
Started Jul 29 06:17:39 PM PDT 24
Finished Jul 29 06:17:40 PM PDT 24
Peak memory 207100 kb
Host smart-4627b93b-2593-47c7-a20f-d4689e73d553
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1696560701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1696560701
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1737439695
Short name T525
Test name
Test status
Simulation time 202549032 ps
CPU time 0.96 seconds
Started Jul 29 06:17:39 PM PDT 24
Finished Jul 29 06:17:41 PM PDT 24
Peak memory 207124 kb
Host smart-f1e477a8-8853-40a8-8da4-046b15601b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17374
39695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1737439695
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.4196195614
Short name T2066
Test name
Test status
Simulation time 5645910071 ps
CPU time 168.28 seconds
Started Jul 29 06:17:37 PM PDT 24
Finished Jul 29 06:20:25 PM PDT 24
Peak memory 215536 kb
Host smart-2338ac82-dac9-40d9-b3ea-db0e392a156a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41961
95614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.4196195614
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.4005976527
Short name T1923
Test name
Test status
Simulation time 3067604951 ps
CPU time 29.65 seconds
Started Jul 29 06:17:38 PM PDT 24
Finished Jul 29 06:18:07 PM PDT 24
Peak memory 216660 kb
Host smart-496aeadc-04dc-4a57-9a6b-3edc20c1f5c9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4005976527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.4005976527
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1329527377
Short name T1845
Test name
Test status
Simulation time 164052436 ps
CPU time 0.87 seconds
Started Jul 29 06:17:39 PM PDT 24
Finished Jul 29 06:17:40 PM PDT 24
Peak memory 207136 kb
Host smart-09201e02-553f-4898-896b-35bbb5f971a4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1329527377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1329527377
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2343024028
Short name T795
Test name
Test status
Simulation time 217535809 ps
CPU time 0.95 seconds
Started Jul 29 06:17:41 PM PDT 24
Finished Jul 29 06:17:42 PM PDT 24
Peak memory 207048 kb
Host smart-f601adc1-5f8a-47f4-bf7d-3519909b3e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23430
24028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2343024028
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.4157293914
Short name T2158
Test name
Test status
Simulation time 195998900 ps
CPU time 0.91 seconds
Started Jul 29 06:17:36 PM PDT 24
Finished Jul 29 06:17:38 PM PDT 24
Peak memory 207100 kb
Host smart-c725e54e-935d-4829-a136-46d8b9b18602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41572
93914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.4157293914
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1787571191
Short name T1581
Test name
Test status
Simulation time 152009857 ps
CPU time 0.93 seconds
Started Jul 29 06:17:41 PM PDT 24
Finished Jul 29 06:17:42 PM PDT 24
Peak memory 207100 kb
Host smart-51f796c4-f71f-4e8b-9fff-9e3b261e68ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17875
71191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1787571191
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1708473035
Short name T2101
Test name
Test status
Simulation time 166155656 ps
CPU time 0.85 seconds
Started Jul 29 06:17:41 PM PDT 24
Finished Jul 29 06:17:42 PM PDT 24
Peak memory 207116 kb
Host smart-e81a1a98-ad37-4fd9-aa23-b3e7b3479de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17084
73035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1708473035
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.626669795
Short name T1480
Test name
Test status
Simulation time 167163176 ps
CPU time 0.88 seconds
Started Jul 29 06:17:38 PM PDT 24
Finished Jul 29 06:17:39 PM PDT 24
Peak memory 207048 kb
Host smart-5fc75256-5a17-49a5-af0f-d56a23d9aaee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62666
9795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.626669795
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.113785753
Short name T1998
Test name
Test status
Simulation time 154555023 ps
CPU time 0.86 seconds
Started Jul 29 06:17:40 PM PDT 24
Finished Jul 29 06:17:41 PM PDT 24
Peak memory 207056 kb
Host smart-07a057b5-c8f0-464e-ba3c-cf14acb24254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11378
5753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.113785753
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.1969780516
Short name T2507
Test name
Test status
Simulation time 209084745 ps
CPU time 0.95 seconds
Started Jul 29 06:17:39 PM PDT 24
Finished Jul 29 06:17:40 PM PDT 24
Peak memory 207120 kb
Host smart-9c5c71c8-b125-4b83-9c78-efcf8961d448
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1969780516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.1969780516
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2396563179
Short name T734
Test name
Test status
Simulation time 154837698 ps
CPU time 0.85 seconds
Started Jul 29 06:17:41 PM PDT 24
Finished Jul 29 06:17:42 PM PDT 24
Peak memory 207124 kb
Host smart-612dc2fb-9eee-43f2-8408-e1de76c9f506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23965
63179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2396563179
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3658460170
Short name T1081
Test name
Test status
Simulation time 71290069 ps
CPU time 0.79 seconds
Started Jul 29 06:17:36 PM PDT 24
Finished Jul 29 06:17:37 PM PDT 24
Peak memory 207024 kb
Host smart-e3e902e5-853c-4d94-8c9f-68a7a8584545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36584
60170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3658460170
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1414249592
Short name T2394
Test name
Test status
Simulation time 21076302462 ps
CPU time 58.64 seconds
Started Jul 29 06:17:39 PM PDT 24
Finished Jul 29 06:18:38 PM PDT 24
Peak memory 215768 kb
Host smart-cb9014f8-2e95-4f50-81b0-a677c630c711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14142
49592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1414249592
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.1742235184
Short name T2339
Test name
Test status
Simulation time 162989790 ps
CPU time 0.84 seconds
Started Jul 29 06:17:41 PM PDT 24
Finished Jul 29 06:17:42 PM PDT 24
Peak memory 207072 kb
Host smart-1b85f98b-6d8d-44c7-9133-25aff9974466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17422
35184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1742235184
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.329405031
Short name T1011
Test name
Test status
Simulation time 213578134 ps
CPU time 0.94 seconds
Started Jul 29 06:17:40 PM PDT 24
Finished Jul 29 06:17:41 PM PDT 24
Peak memory 207048 kb
Host smart-f4fc08f9-c45c-4813-b981-1a0df4b0fa4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32940
5031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.329405031
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.877171145
Short name T2002
Test name
Test status
Simulation time 183464294 ps
CPU time 0.91 seconds
Started Jul 29 06:17:45 PM PDT 24
Finished Jul 29 06:17:46 PM PDT 24
Peak memory 207108 kb
Host smart-afd1a57f-a245-488e-ad8d-28f43da348ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87717
1145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.877171145
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3845770913
Short name T1584
Test name
Test status
Simulation time 208593604 ps
CPU time 0.91 seconds
Started Jul 29 06:17:38 PM PDT 24
Finished Jul 29 06:17:39 PM PDT 24
Peak memory 207088 kb
Host smart-58104c58-c0ff-4c29-bea0-702029847cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38457
70913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3845770913
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3520110734
Short name T1134
Test name
Test status
Simulation time 192027926 ps
CPU time 0.88 seconds
Started Jul 29 06:17:38 PM PDT 24
Finished Jul 29 06:17:39 PM PDT 24
Peak memory 207104 kb
Host smart-ae643012-52ff-4925-9d33-fae7a07f8512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35201
10734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3520110734
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.4023026973
Short name T1810
Test name
Test status
Simulation time 170209898 ps
CPU time 0.9 seconds
Started Jul 29 06:17:39 PM PDT 24
Finished Jul 29 06:17:40 PM PDT 24
Peak memory 207068 kb
Host smart-aa542678-ec75-47c0-934b-a549e6fa62d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40230
26973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.4023026973
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3075834596
Short name T2441
Test name
Test status
Simulation time 219455482 ps
CPU time 0.94 seconds
Started Jul 29 06:17:46 PM PDT 24
Finished Jul 29 06:17:47 PM PDT 24
Peak memory 207104 kb
Host smart-27bd5daa-7a06-4e28-913e-6326a61515ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30758
34596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3075834596
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.4094863122
Short name T2459
Test name
Test status
Simulation time 215297467 ps
CPU time 0.99 seconds
Started Jul 29 06:17:39 PM PDT 24
Finished Jul 29 06:17:40 PM PDT 24
Peak memory 207112 kb
Host smart-86ab8ec2-8cb1-4d26-971e-d45afc30add6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40948
63122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.4094863122
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.804261561
Short name T1503
Test name
Test status
Simulation time 3803273972 ps
CPU time 108.67 seconds
Started Jul 29 06:17:38 PM PDT 24
Finished Jul 29 06:19:27 PM PDT 24
Peak memory 215548 kb
Host smart-be62836a-f828-458c-bacf-7547fc4b19c0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=804261561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.804261561
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.4123169083
Short name T1652
Test name
Test status
Simulation time 160706651 ps
CPU time 0.83 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:17:49 PM PDT 24
Peak memory 207100 kb
Host smart-c523e650-2fd1-4049-80a3-a24df010625f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41231
69083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.4123169083
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1258487108
Short name T589
Test name
Test status
Simulation time 191697745 ps
CPU time 0.99 seconds
Started Jul 29 06:17:44 PM PDT 24
Finished Jul 29 06:17:45 PM PDT 24
Peak memory 207064 kb
Host smart-defafd69-03a8-4ab2-a03b-d829f5d4b26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12584
87108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1258487108
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.2964082813
Short name T724
Test name
Test status
Simulation time 448399484 ps
CPU time 1.47 seconds
Started Jul 29 06:17:43 PM PDT 24
Finished Jul 29 06:17:44 PM PDT 24
Peak memory 207096 kb
Host smart-9ac7f2a6-a6c4-45ee-bd14-313fab4dc428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29640
82813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.2964082813
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2426229819
Short name T678
Test name
Test status
Simulation time 5195713074 ps
CPU time 54.14 seconds
Started Jul 29 06:17:44 PM PDT 24
Finished Jul 29 06:18:38 PM PDT 24
Peak memory 217064 kb
Host smart-b70cb034-3268-493f-b368-6f841d68f61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24262
29819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2426229819
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.1341788986
Short name T847
Test name
Test status
Simulation time 874390890 ps
CPU time 5.7 seconds
Started Jul 29 06:17:34 PM PDT 24
Finished Jul 29 06:17:39 PM PDT 24
Peak memory 207276 kb
Host smart-946377a5-43e2-4253-ab2a-31f349a96dcd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341788986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_hos
t_handshake.1341788986
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.1449335636
Short name T2625
Test name
Test status
Simulation time 85071880 ps
CPU time 0.71 seconds
Started Jul 29 06:17:49 PM PDT 24
Finished Jul 29 06:17:50 PM PDT 24
Peak memory 207104 kb
Host smart-13eaf690-3b73-49c0-ba07-59f1bc2b39df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1449335636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.1449335636
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.3479134519
Short name T1316
Test name
Test status
Simulation time 3813469254 ps
CPU time 5.48 seconds
Started Jul 29 06:17:46 PM PDT 24
Finished Jul 29 06:17:52 PM PDT 24
Peak memory 207332 kb
Host smart-1d34c9bd-0cf0-4dd8-b3b0-5d415e9b598c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479134519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.3479134519
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.3294751577
Short name T16
Test name
Test status
Simulation time 13403863647 ps
CPU time 15.34 seconds
Started Jul 29 06:17:49 PM PDT 24
Finished Jul 29 06:18:04 PM PDT 24
Peak memory 207448 kb
Host smart-aa6b5a84-88e6-4277-b6a9-d76ebef25403
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294751577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.3294751577
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.286320813
Short name T1069
Test name
Test status
Simulation time 23384140089 ps
CPU time 26.93 seconds
Started Jul 29 06:17:44 PM PDT 24
Finished Jul 29 06:18:11 PM PDT 24
Peak memory 207400 kb
Host smart-daf1249b-46a5-4961-8d57-d7ac6eae76ab
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286320813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ao
n_wake_resume.286320813
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3630088355
Short name T1764
Test name
Test status
Simulation time 148122521 ps
CPU time 0.86 seconds
Started Jul 29 06:17:43 PM PDT 24
Finished Jul 29 06:17:45 PM PDT 24
Peak memory 207088 kb
Host smart-d4a62d4c-ee59-455c-8b84-acbc8f85a7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36300
88355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3630088355
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2089688082
Short name T1519
Test name
Test status
Simulation time 146678199 ps
CPU time 0.81 seconds
Started Jul 29 06:17:42 PM PDT 24
Finished Jul 29 06:17:43 PM PDT 24
Peak memory 207068 kb
Host smart-c1cabe65-c85e-4f1d-9aa8-e6321b1bda75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20896
88082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2089688082
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.3538220418
Short name T28
Test name
Test status
Simulation time 418968591 ps
CPU time 1.5 seconds
Started Jul 29 06:17:45 PM PDT 24
Finished Jul 29 06:17:47 PM PDT 24
Peak memory 207120 kb
Host smart-076c99d6-413f-44ad-bebd-d8af1a1caf2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35382
20418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.3538220418
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3288961526
Short name T2166
Test name
Test status
Simulation time 888125096 ps
CPU time 2.37 seconds
Started Jul 29 06:17:43 PM PDT 24
Finished Jul 29 06:17:46 PM PDT 24
Peak memory 207352 kb
Host smart-dc7dd9cf-9bc8-4f56-aba7-0b5c813e6014
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3288961526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3288961526
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.1132706871
Short name T2184
Test name
Test status
Simulation time 19538363867 ps
CPU time 41.25 seconds
Started Jul 29 06:17:43 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 207448 kb
Host smart-cc0efd7d-03af-4c65-a8ab-cc8b5dd850f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11327
06871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1132706871
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.3157290922
Short name T2564
Test name
Test status
Simulation time 1017130506 ps
CPU time 22.42 seconds
Started Jul 29 06:17:46 PM PDT 24
Finished Jul 29 06:18:09 PM PDT 24
Peak memory 207268 kb
Host smart-2ea8921b-0fa2-4f5a-b9ad-a3996861231b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157290922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.3157290922
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2818698556
Short name T1479
Test name
Test status
Simulation time 437814339 ps
CPU time 1.43 seconds
Started Jul 29 06:17:45 PM PDT 24
Finished Jul 29 06:17:47 PM PDT 24
Peak memory 207028 kb
Host smart-01a57ad8-8830-4a8e-bcb1-4a55229b8459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28186
98556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2818698556
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.4112118324
Short name T44
Test name
Test status
Simulation time 140413098 ps
CPU time 0.85 seconds
Started Jul 29 06:17:43 PM PDT 24
Finished Jul 29 06:17:45 PM PDT 24
Peak memory 207044 kb
Host smart-6f6c2c1f-fca4-4a7f-bd5b-4ac6985b3b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41121
18324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.4112118324
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3189324312
Short name T746
Test name
Test status
Simulation time 50979135 ps
CPU time 0.7 seconds
Started Jul 29 06:17:43 PM PDT 24
Finished Jul 29 06:17:44 PM PDT 24
Peak memory 207032 kb
Host smart-5e82de8d-2a75-4016-abf9-59ba5f4a719a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31893
24312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3189324312
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.38554176
Short name T857
Test name
Test status
Simulation time 892337522 ps
CPU time 2.66 seconds
Started Jul 29 06:17:47 PM PDT 24
Finished Jul 29 06:17:50 PM PDT 24
Peak memory 207412 kb
Host smart-46e61e36-7a8b-44ef-802b-5318922166cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38554
176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.38554176
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3090321431
Short name T2477
Test name
Test status
Simulation time 268246799 ps
CPU time 1.73 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:17:50 PM PDT 24
Peak memory 207256 kb
Host smart-d5d20073-686b-49e1-b44a-f0127c2f88db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30903
21431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3090321431
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3786757791
Short name T101
Test name
Test status
Simulation time 190551822 ps
CPU time 1.04 seconds
Started Jul 29 06:17:45 PM PDT 24
Finished Jul 29 06:17:47 PM PDT 24
Peak memory 207248 kb
Host smart-0c0fb285-8998-4d3d-ab23-7b4ef7793d56
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3786757791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3786757791
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2907218998
Short name T2398
Test name
Test status
Simulation time 150458899 ps
CPU time 0.82 seconds
Started Jul 29 06:17:47 PM PDT 24
Finished Jul 29 06:17:48 PM PDT 24
Peak memory 207112 kb
Host smart-3ad63d4e-209c-4e6d-8216-15e1e3b56557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29072
18998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2907218998
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3981287694
Short name T1585
Test name
Test status
Simulation time 148447642 ps
CPU time 0.84 seconds
Started Jul 29 06:17:43 PM PDT 24
Finished Jul 29 06:17:44 PM PDT 24
Peak memory 207104 kb
Host smart-d58d1ce1-0b5b-4dfe-af58-d600a3fd2f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39812
87694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3981287694
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.1188693012
Short name T2758
Test name
Test status
Simulation time 6615511913 ps
CPU time 67.89 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:18:56 PM PDT 24
Peak memory 217076 kb
Host smart-a942cb83-a56d-44af-a78a-36869697201c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1188693012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.1188693012
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.129400404
Short name T1355
Test name
Test status
Simulation time 9642445987 ps
CPU time 62.91 seconds
Started Jul 29 06:17:52 PM PDT 24
Finished Jul 29 06:18:55 PM PDT 24
Peak memory 207308 kb
Host smart-79d1cc88-ef98-4155-a136-9628e2619560
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=129400404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.129400404
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.1482384249
Short name T706
Test name
Test status
Simulation time 165093227 ps
CPU time 0.92 seconds
Started Jul 29 06:17:43 PM PDT 24
Finished Jul 29 06:17:44 PM PDT 24
Peak memory 207136 kb
Host smart-9098fc47-f77a-4590-9ca6-cb33ca5976ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14823
84249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1482384249
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.4271722061
Short name T2536
Test name
Test status
Simulation time 23346852663 ps
CPU time 27.87 seconds
Started Jul 29 06:17:45 PM PDT 24
Finished Jul 29 06:18:13 PM PDT 24
Peak memory 207392 kb
Host smart-dcd6167f-c20f-4f9c-9d26-cc015820f1c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42717
22061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.4271722061
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1589583796
Short name T1087
Test name
Test status
Simulation time 3282846722 ps
CPU time 4.75 seconds
Started Jul 29 06:17:43 PM PDT 24
Finished Jul 29 06:17:47 PM PDT 24
Peak memory 207304 kb
Host smart-6375b493-d74c-4eb2-9248-92e9286cb43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15895
83796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1589583796
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1293343383
Short name T1108
Test name
Test status
Simulation time 6923787471 ps
CPU time 200.04 seconds
Started Jul 29 06:17:47 PM PDT 24
Finished Jul 29 06:21:07 PM PDT 24
Peak memory 215592 kb
Host smart-eba1dcd1-0a0d-45ec-a1e0-bd760517abf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12933
43383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1293343383
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3904933954
Short name T342
Test name
Test status
Simulation time 5107688754 ps
CPU time 37.75 seconds
Started Jul 29 06:17:44 PM PDT 24
Finished Jul 29 06:18:22 PM PDT 24
Peak memory 207436 kb
Host smart-248c29c6-3433-4bd5-ac95-5ba08ea15ce8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3904933954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3904933954
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1658544376
Short name T1470
Test name
Test status
Simulation time 256241878 ps
CPU time 1.01 seconds
Started Jul 29 06:17:50 PM PDT 24
Finished Jul 29 06:17:51 PM PDT 24
Peak memory 207116 kb
Host smart-b318ad7a-52c8-421d-98a5-d4bbbbbde924
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1658544376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1658544376
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1096868182
Short name T1864
Test name
Test status
Simulation time 205335569 ps
CPU time 0.94 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:17:49 PM PDT 24
Peak memory 207096 kb
Host smart-42ac0d86-1dba-4288-81a7-185157c0e6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10968
68182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1096868182
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1336069647
Short name T800
Test name
Test status
Simulation time 6169025386 ps
CPU time 47.22 seconds
Started Jul 29 06:17:49 PM PDT 24
Finished Jul 29 06:18:42 PM PDT 24
Peak memory 215640 kb
Host smart-4ea2933c-83b6-43f1-9e84-3b6a24fc4b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13360
69647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1336069647
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1055390366
Short name T412
Test name
Test status
Simulation time 3601301439 ps
CPU time 26.39 seconds
Started Jul 29 06:17:52 PM PDT 24
Finished Jul 29 06:18:19 PM PDT 24
Peak memory 216872 kb
Host smart-b177b976-713a-4f8e-9009-ec24f7abd6c9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1055390366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1055390366
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.2196169910
Short name T1502
Test name
Test status
Simulation time 199829138 ps
CPU time 0.92 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:17:49 PM PDT 24
Peak memory 207252 kb
Host smart-d7c906ec-d95a-4a62-8940-658db8be25fd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2196169910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.2196169910
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2518545445
Short name T574
Test name
Test status
Simulation time 190437375 ps
CPU time 0.88 seconds
Started Jul 29 06:17:52 PM PDT 24
Finished Jul 29 06:17:53 PM PDT 24
Peak memory 207052 kb
Host smart-c0c7d278-fce2-454c-9220-816764fef055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25185
45445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2518545445
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.821136923
Short name T126
Test name
Test status
Simulation time 201702134 ps
CPU time 0.98 seconds
Started Jul 29 06:17:44 PM PDT 24
Finished Jul 29 06:17:45 PM PDT 24
Peak memory 207056 kb
Host smart-e2ca143c-bdbe-4daf-a36c-bf95a5fbcada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82113
6923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.821136923
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.3001286745
Short name T684
Test name
Test status
Simulation time 169386591 ps
CPU time 0.92 seconds
Started Jul 29 06:17:45 PM PDT 24
Finished Jul 29 06:17:46 PM PDT 24
Peak memory 207096 kb
Host smart-ee59b0b0-87da-4150-8f9f-e0d966109553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30012
86745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3001286745
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.609732125
Short name T1450
Test name
Test status
Simulation time 178058010 ps
CPU time 0.9 seconds
Started Jul 29 06:17:47 PM PDT 24
Finished Jul 29 06:17:48 PM PDT 24
Peak memory 207224 kb
Host smart-08f2669d-694e-4db9-a14b-997292854418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60973
2125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.609732125
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3125301449
Short name T2566
Test name
Test status
Simulation time 211510105 ps
CPU time 0.97 seconds
Started Jul 29 06:17:44 PM PDT 24
Finished Jul 29 06:17:45 PM PDT 24
Peak memory 207188 kb
Host smart-09b2c64b-1243-41d6-8cda-748407ff0205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31253
01449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3125301449
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2409194653
Short name T2159
Test name
Test status
Simulation time 149752748 ps
CPU time 0.88 seconds
Started Jul 29 06:17:54 PM PDT 24
Finished Jul 29 06:17:55 PM PDT 24
Peak memory 207032 kb
Host smart-c55b14f2-f114-4e9d-abe3-7347bb91bdb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24091
94653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2409194653
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2959475608
Short name T1183
Test name
Test status
Simulation time 225089880 ps
CPU time 0.99 seconds
Started Jul 29 06:17:50 PM PDT 24
Finished Jul 29 06:17:51 PM PDT 24
Peak memory 207132 kb
Host smart-8c269723-7fcf-46fd-9e0c-b88a5b908ddc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2959475608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2959475608
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3475468666
Short name T190
Test name
Test status
Simulation time 186808278 ps
CPU time 0.92 seconds
Started Jul 29 06:17:52 PM PDT 24
Finished Jul 29 06:17:53 PM PDT 24
Peak memory 207020 kb
Host smart-3866038d-9c9d-4d21-906f-91fef756a1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34754
68666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3475468666
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3742024191
Short name T1173
Test name
Test status
Simulation time 49907076 ps
CPU time 0.79 seconds
Started Jul 29 06:17:43 PM PDT 24
Finished Jul 29 06:17:44 PM PDT 24
Peak memory 207064 kb
Host smart-750b8528-df67-4ddd-af64-62f0f390bffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37420
24191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3742024191
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2623363866
Short name T2377
Test name
Test status
Simulation time 16554120479 ps
CPU time 43.06 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:18:31 PM PDT 24
Peak memory 215668 kb
Host smart-12453989-d169-4de0-8de8-e0f4542f4041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26233
63866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2623363866
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3702346752
Short name T2773
Test name
Test status
Simulation time 187766724 ps
CPU time 0.94 seconds
Started Jul 29 06:17:50 PM PDT 24
Finished Jul 29 06:17:51 PM PDT 24
Peak memory 207108 kb
Host smart-f5ca62d7-ce63-4cd8-99aa-798632bf749f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37023
46752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3702346752
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.708779333
Short name T2211
Test name
Test status
Simulation time 216695131 ps
CPU time 0.97 seconds
Started Jul 29 06:17:52 PM PDT 24
Finished Jul 29 06:17:53 PM PDT 24
Peak memory 207000 kb
Host smart-e1d361a2-dfc9-4bff-9021-8ee1bc626dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70877
9333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.708779333
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2589711895
Short name T374
Test name
Test status
Simulation time 225468446 ps
CPU time 0.97 seconds
Started Jul 29 06:17:46 PM PDT 24
Finished Jul 29 06:17:47 PM PDT 24
Peak memory 207052 kb
Host smart-2e1c1db7-f696-4f0e-82f4-0c4af8ecf6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25897
11895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2589711895
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3050169352
Short name T1728
Test name
Test status
Simulation time 171214534 ps
CPU time 0.85 seconds
Started Jul 29 06:17:45 PM PDT 24
Finished Jul 29 06:17:46 PM PDT 24
Peak memory 207092 kb
Host smart-1386ff75-b071-44b7-a62b-84434b810b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30501
69352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3050169352
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1093709206
Short name T1090
Test name
Test status
Simulation time 155057477 ps
CPU time 0.9 seconds
Started Jul 29 06:17:50 PM PDT 24
Finished Jul 29 06:17:51 PM PDT 24
Peak memory 207032 kb
Host smart-1fb2e9ff-1279-487a-8afd-088ea18521e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10937
09206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1093709206
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.236101378
Short name T98
Test name
Test status
Simulation time 159284495 ps
CPU time 0.82 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:17:49 PM PDT 24
Peak memory 207044 kb
Host smart-71af84ab-a028-4eac-9b50-fc481aef7c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23610
1378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.236101378
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2715747142
Short name T2620
Test name
Test status
Simulation time 153199864 ps
CPU time 0.89 seconds
Started Jul 29 06:17:52 PM PDT 24
Finished Jul 29 06:17:53 PM PDT 24
Peak memory 207096 kb
Host smart-533f8ce3-724c-402b-8c7f-47fca2e8735f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27157
47142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2715747142
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1311528697
Short name T1179
Test name
Test status
Simulation time 214945865 ps
CPU time 0.97 seconds
Started Jul 29 06:17:46 PM PDT 24
Finished Jul 29 06:17:47 PM PDT 24
Peak memory 207076 kb
Host smart-d50e434e-25e8-4c3c-89d6-6ad56c0614f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13115
28697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1311528697
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.2274648676
Short name T998
Test name
Test status
Simulation time 5850475786 ps
CPU time 58.35 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:18:47 PM PDT 24
Peak memory 207392 kb
Host smart-e4f4014e-f6cc-4d3a-aebb-c655b52055bc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2274648676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.2274648676
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1625490154
Short name T1560
Test name
Test status
Simulation time 210155389 ps
CPU time 0.93 seconds
Started Jul 29 06:17:49 PM PDT 24
Finished Jul 29 06:17:50 PM PDT 24
Peak memory 207108 kb
Host smart-89768bab-f63c-4016-a498-daaf8c6eaf0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16254
90154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1625490154
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1223904169
Short name T1811
Test name
Test status
Simulation time 162221431 ps
CPU time 0.84 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:17:49 PM PDT 24
Peak memory 207148 kb
Host smart-8746a927-470f-426b-8092-af7953435c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12239
04169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1223904169
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.3671327229
Short name T2005
Test name
Test status
Simulation time 1028232463 ps
CPU time 2.34 seconds
Started Jul 29 06:17:50 PM PDT 24
Finished Jul 29 06:17:52 PM PDT 24
Peak memory 207412 kb
Host smart-ff3aca48-5ca8-466b-ae46-04b36414a46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36713
27229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.3671327229
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.4054926415
Short name T1423
Test name
Test status
Simulation time 3891194192 ps
CPU time 39.75 seconds
Started Jul 29 06:17:50 PM PDT 24
Finished Jul 29 06:18:30 PM PDT 24
Peak memory 215548 kb
Host smart-00047714-e98e-4793-bec4-ae536306f8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40549
26415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.4054926415
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.2197768587
Short name T2693
Test name
Test status
Simulation time 2153202593 ps
CPU time 17.39 seconds
Started Jul 29 06:17:42 PM PDT 24
Finished Jul 29 06:18:00 PM PDT 24
Peak memory 207304 kb
Host smart-8bde1d8c-5020-4281-a362-a0a1622e884b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197768587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.2197768587
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1956716269
Short name T2599
Test name
Test status
Simulation time 70880816 ps
CPU time 0.72 seconds
Started Jul 29 06:17:59 PM PDT 24
Finished Jul 29 06:18:00 PM PDT 24
Peak memory 207132 kb
Host smart-89839297-69b6-4a3a-8a79-077109b684fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1956716269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1956716269
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.928107316
Short name T2202
Test name
Test status
Simulation time 13358862596 ps
CPU time 16.32 seconds
Started Jul 29 06:17:58 PM PDT 24
Finished Jul 29 06:18:15 PM PDT 24
Peak memory 207432 kb
Host smart-8b6851af-8b27-4b1f-b2c9-78bb43ca0d55
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=928107316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.928107316
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3540027386
Short name T1612
Test name
Test status
Simulation time 23383778727 ps
CPU time 26.51 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:18:15 PM PDT 24
Peak memory 207424 kb
Host smart-444178ed-df86-4682-b4c3-3bdd08b6eac9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540027386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.3540027386
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.4023826841
Short name T2371
Test name
Test status
Simulation time 150053877 ps
CPU time 0.94 seconds
Started Jul 29 06:17:49 PM PDT 24
Finished Jul 29 06:17:50 PM PDT 24
Peak memory 207084 kb
Host smart-a0ff174a-d8df-47a6-8b93-3712ea741c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40238
26841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.4023826841
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.1839749460
Short name T1198
Test name
Test status
Simulation time 193705759 ps
CPU time 0.88 seconds
Started Jul 29 06:17:47 PM PDT 24
Finished Jul 29 06:17:48 PM PDT 24
Peak memory 207012 kb
Host smart-069f8eae-e95b-4563-a209-9bba98f13fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18397
49460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.1839749460
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.3561309217
Short name T1981
Test name
Test status
Simulation time 205011184 ps
CPU time 0.94 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:17:49 PM PDT 24
Peak memory 207080 kb
Host smart-ad25d815-fb03-41da-8d8f-61e02d9ac79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35613
09217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.3561309217
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.2153111717
Short name T391
Test name
Test status
Simulation time 1304357442 ps
CPU time 3.05 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:17:51 PM PDT 24
Peak memory 207296 kb
Host smart-84097247-3c7e-43a3-9a80-01058f0f80af
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2153111717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2153111717
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.4130573053
Short name T2560
Test name
Test status
Simulation time 13074983922 ps
CPU time 29.89 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:18:18 PM PDT 24
Peak memory 207392 kb
Host smart-7860ae7b-265a-4f10-a6ba-febb47daad2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41305
73053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.4130573053
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.2260761326
Short name T2841
Test name
Test status
Simulation time 5633854833 ps
CPU time 40.31 seconds
Started Jul 29 06:17:47 PM PDT 24
Finished Jul 29 06:18:28 PM PDT 24
Peak memory 207396 kb
Host smart-314e900a-c0ef-4303-8ee0-0dd969e8a493
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260761326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.2260761326
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.2534218402
Short name T1734
Test name
Test status
Simulation time 447021355 ps
CPU time 1.54 seconds
Started Jul 29 06:17:50 PM PDT 24
Finished Jul 29 06:17:52 PM PDT 24
Peak memory 207016 kb
Host smart-1c3ba2e7-4ee5-477b-acc8-28856f5d3999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25342
18402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2534218402
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3187385330
Short name T1435
Test name
Test status
Simulation time 139565774 ps
CPU time 0.83 seconds
Started Jul 29 06:17:47 PM PDT 24
Finished Jul 29 06:17:48 PM PDT 24
Peak memory 207036 kb
Host smart-45f2f460-c0e4-49ba-977d-3cba2512c526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31873
85330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3187385330
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.120111996
Short name T2383
Test name
Test status
Simulation time 39112114 ps
CPU time 0.73 seconds
Started Jul 29 06:17:52 PM PDT 24
Finished Jul 29 06:17:52 PM PDT 24
Peak memory 207036 kb
Host smart-e46a2e34-4422-4cdc-979e-3c9f2b88ee39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12011
1996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.120111996
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.1080698790
Short name T2112
Test name
Test status
Simulation time 1001104314 ps
CPU time 2.46 seconds
Started Jul 29 06:17:48 PM PDT 24
Finished Jul 29 06:17:51 PM PDT 24
Peak memory 207308 kb
Host smart-d92753a5-dc68-462a-99fd-b191ec3f9a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10806
98790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1080698790
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.2810931745
Short name T2712
Test name
Test status
Simulation time 203763059 ps
CPU time 1.43 seconds
Started Jul 29 06:17:47 PM PDT 24
Finished Jul 29 06:17:48 PM PDT 24
Peak memory 207316 kb
Host smart-70105566-b91a-4c93-bf10-40796818de53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28109
31745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2810931745
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1941885000
Short name T1097
Test name
Test status
Simulation time 257527836 ps
CPU time 1.25 seconds
Started Jul 29 06:17:57 PM PDT 24
Finished Jul 29 06:17:58 PM PDT 24
Peak memory 215500 kb
Host smart-598d68c8-f7a8-4591-b881-4f24a193390c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1941885000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1941885000
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.4126610553
Short name T1367
Test name
Test status
Simulation time 163438341 ps
CPU time 0.84 seconds
Started Jul 29 06:17:54 PM PDT 24
Finished Jul 29 06:17:55 PM PDT 24
Peak memory 207096 kb
Host smart-0276f940-fbcc-43be-970a-fc782100e505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41266
10553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.4126610553
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2009725959
Short name T1859
Test name
Test status
Simulation time 231701978 ps
CPU time 1.03 seconds
Started Jul 29 06:17:56 PM PDT 24
Finished Jul 29 06:17:57 PM PDT 24
Peak memory 207104 kb
Host smart-ea2c7c79-17be-4867-aef6-4e0ce321cade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20097
25959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2009725959
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.476631510
Short name T801
Test name
Test status
Simulation time 8614268104 ps
CPU time 242.35 seconds
Started Jul 29 06:17:51 PM PDT 24
Finished Jul 29 06:21:53 PM PDT 24
Peak memory 215584 kb
Host smart-a9309634-5e8b-4ea1-8b12-a2d30fd9bfcc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=476631510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.476631510
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.492155498
Short name T1659
Test name
Test status
Simulation time 9168420961 ps
CPU time 57.66 seconds
Started Jul 29 06:17:54 PM PDT 24
Finished Jul 29 06:18:52 PM PDT 24
Peak memory 207404 kb
Host smart-e2d2c522-4d2e-4dbd-921d-2f244058b534
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=492155498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.492155498
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.3227260665
Short name T1602
Test name
Test status
Simulation time 162009043 ps
CPU time 0.88 seconds
Started Jul 29 06:17:56 PM PDT 24
Finished Jul 29 06:17:57 PM PDT 24
Peak memory 207104 kb
Host smart-407bf4e9-657f-43ff-82f7-ef818ca77ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32272
60665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.3227260665
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.4041650684
Short name T2252
Test name
Test status
Simulation time 23325223527 ps
CPU time 31.22 seconds
Started Jul 29 06:17:56 PM PDT 24
Finished Jul 29 06:18:28 PM PDT 24
Peak memory 207360 kb
Host smart-a1f34292-8b25-4af5-b8f8-a9c4e1df4584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40416
50684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.4041650684
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.402921111
Short name T2711
Test name
Test status
Simulation time 3317330319 ps
CPU time 4.98 seconds
Started Jul 29 06:17:54 PM PDT 24
Finished Jul 29 06:18:00 PM PDT 24
Peak memory 207352 kb
Host smart-c7d14a9f-b736-489a-b9e7-fcb08c241442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40292
1111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.402921111
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.1477807295
Short name T2570
Test name
Test status
Simulation time 6740307864 ps
CPU time 207.4 seconds
Started Jul 29 06:17:57 PM PDT 24
Finished Jul 29 06:21:25 PM PDT 24
Peak memory 215536 kb
Host smart-a6424131-1be5-4ec0-ab58-c26d61da166a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14778
07295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.1477807295
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.489596249
Short name T2136
Test name
Test status
Simulation time 7089329024 ps
CPU time 61.49 seconds
Started Jul 29 06:17:56 PM PDT 24
Finished Jul 29 06:18:58 PM PDT 24
Peak memory 207408 kb
Host smart-ea296462-7473-4f96-afdc-8f02a4c59f4c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=489596249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.489596249
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2137103391
Short name T2557
Test name
Test status
Simulation time 260473308 ps
CPU time 1.08 seconds
Started Jul 29 06:17:56 PM PDT 24
Finished Jul 29 06:17:57 PM PDT 24
Peak memory 207092 kb
Host smart-bccccb2f-1714-46d3-859e-d549f5d3f8d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2137103391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2137103391
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1031505147
Short name T579
Test name
Test status
Simulation time 233237485 ps
CPU time 0.98 seconds
Started Jul 29 06:17:54 PM PDT 24
Finished Jul 29 06:17:55 PM PDT 24
Peak memory 207100 kb
Host smart-a85a848a-dcf8-49da-bddf-7e84ebc46482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10315
05147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1031505147
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.647972212
Short name T2522
Test name
Test status
Simulation time 4452754975 ps
CPU time 45.38 seconds
Started Jul 29 06:17:54 PM PDT 24
Finished Jul 29 06:18:40 PM PDT 24
Peak memory 216680 kb
Host smart-d46cb0e4-354a-49bd-beae-e3058a6faed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64797
2212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.647972212
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1247862495
Short name T999
Test name
Test status
Simulation time 4204348090 ps
CPU time 34.96 seconds
Started Jul 29 06:17:55 PM PDT 24
Finished Jul 29 06:18:30 PM PDT 24
Peak memory 215568 kb
Host smart-dbcad1ba-0eff-40d6-bec9-9b583b7a36a0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1247862495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1247862495
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.426468380
Short name T505
Test name
Test status
Simulation time 160462459 ps
CPU time 0.92 seconds
Started Jul 29 06:17:53 PM PDT 24
Finished Jul 29 06:17:55 PM PDT 24
Peak memory 207112 kb
Host smart-5d272b2e-02f0-4f44-bf64-2c866c57e27c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=426468380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.426468380
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1954516825
Short name T413
Test name
Test status
Simulation time 150116679 ps
CPU time 0.85 seconds
Started Jul 29 06:17:57 PM PDT 24
Finished Jul 29 06:17:58 PM PDT 24
Peak memory 207020 kb
Host smart-6232d701-3a0e-401f-9a7c-a1da549ea54d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19545
16825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1954516825
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3639419151
Short name T147
Test name
Test status
Simulation time 232047348 ps
CPU time 0.97 seconds
Started Jul 29 06:17:53 PM PDT 24
Finished Jul 29 06:17:54 PM PDT 24
Peak memory 207076 kb
Host smart-0abf541b-968a-435e-bc7f-0d707f4be65d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36394
19151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3639419151
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2755775184
Short name T2300
Test name
Test status
Simulation time 200751980 ps
CPU time 0.94 seconds
Started Jul 29 06:17:58 PM PDT 24
Finished Jul 29 06:18:00 PM PDT 24
Peak memory 206996 kb
Host smart-8674c530-f37c-40b7-b953-fab6c2b3d7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27557
75184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2755775184
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2940373473
Short name T625
Test name
Test status
Simulation time 203879439 ps
CPU time 0.97 seconds
Started Jul 29 06:17:59 PM PDT 24
Finished Jul 29 06:18:00 PM PDT 24
Peak memory 207000 kb
Host smart-a9148032-ce08-468d-a6b4-b3de2356cf2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29403
73473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2940373473
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2655049069
Short name T418
Test name
Test status
Simulation time 157488450 ps
CPU time 0.88 seconds
Started Jul 29 06:17:57 PM PDT 24
Finished Jul 29 06:17:58 PM PDT 24
Peak memory 207140 kb
Host smart-d095f31e-40da-4f38-bfc9-c5d390fd2ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26550
49069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2655049069
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1517929064
Short name T1061
Test name
Test status
Simulation time 154127813 ps
CPU time 0.86 seconds
Started Jul 29 06:17:53 PM PDT 24
Finished Jul 29 06:17:54 PM PDT 24
Peak memory 207048 kb
Host smart-7fc0116e-9363-4b92-b442-a3c707f0af3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15179
29064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1517929064
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.2573264788
Short name T1230
Test name
Test status
Simulation time 236253159 ps
CPU time 1.03 seconds
Started Jul 29 06:17:56 PM PDT 24
Finished Jul 29 06:17:57 PM PDT 24
Peak memory 207044 kb
Host smart-255092fe-102b-4fbc-b1bf-69c47460cf48
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2573264788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.2573264788
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3819382075
Short name T2593
Test name
Test status
Simulation time 144142745 ps
CPU time 0.85 seconds
Started Jul 29 06:17:57 PM PDT 24
Finished Jul 29 06:17:59 PM PDT 24
Peak memory 206944 kb
Host smart-bf2bf2d7-650f-492e-b4b2-6c8579f760a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38193
82075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3819382075
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2995492338
Short name T1192
Test name
Test status
Simulation time 34869037 ps
CPU time 0.73 seconds
Started Jul 29 06:17:57 PM PDT 24
Finished Jul 29 06:17:58 PM PDT 24
Peak memory 207068 kb
Host smart-b880eab6-5e43-4897-a43c-e9ad715d3f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29954
92338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2995492338
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3912441165
Short name T2801
Test name
Test status
Simulation time 15450805780 ps
CPU time 40.16 seconds
Started Jul 29 06:17:55 PM PDT 24
Finished Jul 29 06:18:35 PM PDT 24
Peak memory 215624 kb
Host smart-6372b83a-242b-4f1f-bd3f-dd788de22b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39124
41165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3912441165
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.282935539
Short name T721
Test name
Test status
Simulation time 202430248 ps
CPU time 0.9 seconds
Started Jul 29 06:17:56 PM PDT 24
Finished Jul 29 06:17:57 PM PDT 24
Peak memory 207072 kb
Host smart-66ee7993-f2ef-4976-a8e6-0f1d47488127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28293
5539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.282935539
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2981644520
Short name T2324
Test name
Test status
Simulation time 164864725 ps
CPU time 0.94 seconds
Started Jul 29 06:17:58 PM PDT 24
Finished Jul 29 06:18:00 PM PDT 24
Peak memory 207000 kb
Host smart-c16f93ff-e2a8-4db9-8d33-552c5dce552b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29816
44520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2981644520
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.1380435304
Short name T2857
Test name
Test status
Simulation time 200347452 ps
CPU time 0.95 seconds
Started Jul 29 06:17:54 PM PDT 24
Finished Jul 29 06:17:56 PM PDT 24
Peak memory 207056 kb
Host smart-97544d4d-aadc-46b7-8070-c09b0fc92a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13804
35304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.1380435304
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.1165583894
Short name T1239
Test name
Test status
Simulation time 202702889 ps
CPU time 0.99 seconds
Started Jul 29 06:17:59 PM PDT 24
Finished Jul 29 06:18:00 PM PDT 24
Peak memory 207040 kb
Host smart-fe47aa74-5ea1-43ea-8ed6-19318efb2f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11655
83894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.1165583894
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2043174889
Short name T1685
Test name
Test status
Simulation time 140042614 ps
CPU time 0.85 seconds
Started Jul 29 06:17:56 PM PDT 24
Finished Jul 29 06:17:57 PM PDT 24
Peak memory 207072 kb
Host smart-7f48c5b7-8dbf-450b-a300-9371a84bb2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20431
74889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2043174889
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3653332659
Short name T1852
Test name
Test status
Simulation time 199206637 ps
CPU time 0.93 seconds
Started Jul 29 06:17:54 PM PDT 24
Finished Jul 29 06:17:55 PM PDT 24
Peak memory 207080 kb
Host smart-3b398ce0-a797-4a53-bf7c-a79f520ba289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36533
32659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3653332659
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1961818371
Short name T767
Test name
Test status
Simulation time 188767032 ps
CPU time 0.91 seconds
Started Jul 29 06:17:53 PM PDT 24
Finished Jul 29 06:17:54 PM PDT 24
Peak memory 207128 kb
Host smart-4eb0ffec-4288-4148-8ac4-db20226ba578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19618
18371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1961818371
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.321904677
Short name T916
Test name
Test status
Simulation time 238584314 ps
CPU time 1.02 seconds
Started Jul 29 06:17:57 PM PDT 24
Finished Jul 29 06:17:58 PM PDT 24
Peak memory 207068 kb
Host smart-2a096661-2d3b-42c9-b5a5-3fe3c7bcfdde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32190
4677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.321904677
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.2360329712
Short name T2605
Test name
Test status
Simulation time 4506436111 ps
CPU time 45.93 seconds
Started Jul 29 06:17:59 PM PDT 24
Finished Jul 29 06:18:45 PM PDT 24
Peak memory 217168 kb
Host smart-a5933119-0423-41fc-8515-96162e4130b3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2360329712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.2360329712
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2106833801
Short name T872
Test name
Test status
Simulation time 179512981 ps
CPU time 0.89 seconds
Started Jul 29 06:17:56 PM PDT 24
Finished Jul 29 06:17:57 PM PDT 24
Peak memory 207088 kb
Host smart-7b7ea8f9-59d4-4328-8d8d-59a19d1da275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21068
33801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2106833801
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.500687496
Short name T2468
Test name
Test status
Simulation time 224737554 ps
CPU time 0.99 seconds
Started Jul 29 06:18:03 PM PDT 24
Finished Jul 29 06:18:05 PM PDT 24
Peak memory 206980 kb
Host smart-12730294-1514-4880-9f34-4b5bc1d626c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50068
7496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.500687496
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3761733564
Short name T2610
Test name
Test status
Simulation time 784202803 ps
CPU time 2.1 seconds
Started Jul 29 06:18:00 PM PDT 24
Finished Jul 29 06:18:03 PM PDT 24
Peak memory 207168 kb
Host smart-08553d0d-8eb0-43a3-894d-2b50bab3b9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37617
33564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3761733564
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.2003747182
Short name T717
Test name
Test status
Simulation time 5914406014 ps
CPU time 62.5 seconds
Started Jul 29 06:18:00 PM PDT 24
Finished Jul 29 06:19:03 PM PDT 24
Peak memory 207332 kb
Host smart-07f22832-87a4-4ef0-b42a-2452d53e8677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20037
47182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.2003747182
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.1999035765
Short name T1210
Test name
Test status
Simulation time 169652384 ps
CPU time 0.87 seconds
Started Jul 29 06:17:50 PM PDT 24
Finished Jul 29 06:17:51 PM PDT 24
Peak memory 207068 kb
Host smart-73470f07-5d7e-4e8d-8d33-4f1031893d3b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999035765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos
t_handshake.1999035765
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.810496267
Short name T1806
Test name
Test status
Simulation time 69592311 ps
CPU time 0.72 seconds
Started Jul 29 06:11:44 PM PDT 24
Finished Jul 29 06:11:45 PM PDT 24
Peak memory 207124 kb
Host smart-60fe181b-4a3f-4676-b270-017e90c7c711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=810496267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.810496267
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.1005571362
Short name T88
Test name
Test status
Simulation time 3434146484 ps
CPU time 5.19 seconds
Started Jul 29 06:11:19 PM PDT 24
Finished Jul 29 06:11:25 PM PDT 24
Peak memory 207328 kb
Host smart-791e1a63-f2fb-4b83-b722-90d7f4e9fdff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005571362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.1005571362
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2481674413
Short name T13
Test name
Test status
Simulation time 13310274418 ps
CPU time 16.58 seconds
Started Jul 29 06:11:19 PM PDT 24
Finished Jul 29 06:11:36 PM PDT 24
Peak memory 207408 kb
Host smart-9044e4c7-06c2-4c9e-88ee-f5925ff5fe79
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481674413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2481674413
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.987616014
Short name T2119
Test name
Test status
Simulation time 23306377420 ps
CPU time 32.9 seconds
Started Jul 29 06:11:23 PM PDT 24
Finished Jul 29 06:11:56 PM PDT 24
Peak memory 207376 kb
Host smart-f048b393-365f-4684-8f36-79a4e376031c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987616014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon
_wake_resume.987616014
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.4130683522
Short name T1370
Test name
Test status
Simulation time 242965605 ps
CPU time 0.98 seconds
Started Jul 29 06:11:23 PM PDT 24
Finished Jul 29 06:11:24 PM PDT 24
Peak memory 207024 kb
Host smart-998e5cc8-6ad8-4878-8442-282baf68b8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41306
83522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.4130683522
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.2648857177
Short name T63
Test name
Test status
Simulation time 195873012 ps
CPU time 0.9 seconds
Started Jul 29 06:11:25 PM PDT 24
Finished Jul 29 06:11:27 PM PDT 24
Peak memory 207120 kb
Host smart-f68702ac-04d6-4143-9897-e8082befc678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26488
57177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.2648857177
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.1014445070
Short name T1778
Test name
Test status
Simulation time 150763968 ps
CPU time 0.81 seconds
Started Jul 29 06:11:24 PM PDT 24
Finished Jul 29 06:11:25 PM PDT 24
Peak memory 207080 kb
Host smart-e89a0d0e-b8a9-40a9-922d-2b9ea40ec9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10144
45070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.1014445070
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.1799721648
Short name T741
Test name
Test status
Simulation time 172267038 ps
CPU time 0.88 seconds
Started Jul 29 06:11:23 PM PDT 24
Finished Jul 29 06:11:24 PM PDT 24
Peak memory 207192 kb
Host smart-e1c89f8f-3a4e-4ea6-90d0-ab430d99a6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17997
21648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.1799721648
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.1380053910
Short name T1921
Test name
Test status
Simulation time 487102222 ps
CPU time 1.55 seconds
Started Jul 29 06:11:23 PM PDT 24
Finished Jul 29 06:11:25 PM PDT 24
Peak memory 207056 kb
Host smart-ec8facdd-8ad1-48ff-9261-1a0bdf3bdce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13800
53910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.1380053910
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1157716986
Short name T2604
Test name
Test status
Simulation time 806299997 ps
CPU time 2.38 seconds
Started Jul 29 06:11:22 PM PDT 24
Finished Jul 29 06:11:24 PM PDT 24
Peak memory 207332 kb
Host smart-fee43287-53c0-40e2-9240-5470f310defc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1157716986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1157716986
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.2550976762
Short name T1376
Test name
Test status
Simulation time 8285731538 ps
CPU time 18.63 seconds
Started Jul 29 06:11:26 PM PDT 24
Finished Jul 29 06:11:45 PM PDT 24
Peak memory 207480 kb
Host smart-7fcaae89-c82d-4871-8882-14eb16f480f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25509
76762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2550976762
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.4247834516
Short name T888
Test name
Test status
Simulation time 4892683516 ps
CPU time 43.91 seconds
Started Jul 29 06:11:26 PM PDT 24
Finished Jul 29 06:12:10 PM PDT 24
Peak memory 207336 kb
Host smart-47cd5d29-5f1c-4a9b-9bfb-91e3ae7c095f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247834516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.4247834516
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.140013538
Short name T1997
Test name
Test status
Simulation time 446809258 ps
CPU time 1.39 seconds
Started Jul 29 06:11:23 PM PDT 24
Finished Jul 29 06:11:25 PM PDT 24
Peak memory 207064 kb
Host smart-3d82bb34-cda5-405e-a74d-c30dd66b6b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14001
3538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.140013538
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.4158805504
Short name T2763
Test name
Test status
Simulation time 217415695 ps
CPU time 0.89 seconds
Started Jul 29 06:11:23 PM PDT 24
Finished Jul 29 06:11:24 PM PDT 24
Peak memory 207072 kb
Host smart-41f8b54e-5767-423a-a1d6-425f3f6c3961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41588
05504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.4158805504
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.2846849877
Short name T770
Test name
Test status
Simulation time 32505424 ps
CPU time 0.71 seconds
Started Jul 29 06:11:23 PM PDT 24
Finished Jul 29 06:11:24 PM PDT 24
Peak memory 207040 kb
Host smart-7061f3fa-95ec-48d9-bca0-897961ec4c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28468
49877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2846849877
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.441248279
Short name T2756
Test name
Test status
Simulation time 941278894 ps
CPU time 2.38 seconds
Started Jul 29 06:11:27 PM PDT 24
Finished Jul 29 06:11:29 PM PDT 24
Peak memory 207352 kb
Host smart-2dceab7b-c788-4452-a7b3-ff229b0bbcc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44124
8279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.441248279
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2508888500
Short name T803
Test name
Test status
Simulation time 208474133 ps
CPU time 1.59 seconds
Started Jul 29 06:11:25 PM PDT 24
Finished Jul 29 06:11:27 PM PDT 24
Peak memory 207288 kb
Host smart-c2ba5b50-d97b-496e-9176-389fa1a7c452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25088
88500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2508888500
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2088225272
Short name T2298
Test name
Test status
Simulation time 90196129235 ps
CPU time 150.92 seconds
Started Jul 29 06:11:24 PM PDT 24
Finished Jul 29 06:13:55 PM PDT 24
Peak memory 207444 kb
Host smart-14ac5443-a520-4ab3-a8fd-00841c226d78
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2088225272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2088225272
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.836817756
Short name T1044
Test name
Test status
Simulation time 98364441758 ps
CPU time 149.88 seconds
Started Jul 29 06:11:24 PM PDT 24
Finished Jul 29 06:13:54 PM PDT 24
Peak memory 207324 kb
Host smart-11ce6f2d-0d6a-44d0-b069-ab396fbc9c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836817756 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.836817756
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1040673166
Short name T304
Test name
Test status
Simulation time 110122852780 ps
CPU time 196.88 seconds
Started Jul 29 06:11:25 PM PDT 24
Finished Jul 29 06:14:42 PM PDT 24
Peak memory 207424 kb
Host smart-a7a7ff3c-3fc0-4e32-b291-1a0a9e25c377
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1040673166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1040673166
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.3281098028
Short name T1481
Test name
Test status
Simulation time 105245372906 ps
CPU time 171.9 seconds
Started Jul 29 06:11:27 PM PDT 24
Finished Jul 29 06:14:19 PM PDT 24
Peak memory 207400 kb
Host smart-ee526bb7-eec3-4811-820c-3079b8b4cafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281098028 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.3281098028
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.2909499618
Short name T307
Test name
Test status
Simulation time 114149170655 ps
CPU time 188.64 seconds
Started Jul 29 06:11:26 PM PDT 24
Finished Jul 29 06:14:35 PM PDT 24
Peak memory 207468 kb
Host smart-61681b60-1926-414c-aa6c-a05fa99a386e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29094
99618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.2909499618
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.2636429209
Short name T366
Test name
Test status
Simulation time 189291141 ps
CPU time 1.04 seconds
Started Jul 29 06:11:33 PM PDT 24
Finished Jul 29 06:11:34 PM PDT 24
Peak memory 207308 kb
Host smart-945d66ea-b020-4aa2-bd61-0ba855aa60bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2636429209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.2636429209
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2479551244
Short name T566
Test name
Test status
Simulation time 154545967 ps
CPU time 0.82 seconds
Started Jul 29 06:11:30 PM PDT 24
Finished Jul 29 06:11:31 PM PDT 24
Peak memory 207156 kb
Host smart-5f502f88-e3db-4aae-a895-d6b7add26536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24795
51244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2479551244
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1523217595
Short name T2417
Test name
Test status
Simulation time 183720492 ps
CPU time 0.96 seconds
Started Jul 29 06:11:32 PM PDT 24
Finished Jul 29 06:11:33 PM PDT 24
Peak memory 207104 kb
Host smart-d8ac2048-4d2b-4acb-b0e9-2f051b7d552b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15232
17595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1523217595
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.746343584
Short name T1975
Test name
Test status
Simulation time 7677872018 ps
CPU time 79.96 seconds
Started Jul 29 06:11:25 PM PDT 24
Finished Jul 29 06:12:45 PM PDT 24
Peak memory 215628 kb
Host smart-d8279d86-0c5d-4a00-943c-7acc98a060c0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=746343584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.746343584
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.2585804524
Short name T2690
Test name
Test status
Simulation time 6445065347 ps
CPU time 40.63 seconds
Started Jul 29 06:11:29 PM PDT 24
Finished Jul 29 06:12:10 PM PDT 24
Peak memory 207380 kb
Host smart-c89cea22-edb0-4292-870f-c20eae5b107a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2585804524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.2585804524
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.596204701
Short name T1870
Test name
Test status
Simulation time 220284469 ps
CPU time 0.99 seconds
Started Jul 29 06:11:30 PM PDT 24
Finished Jul 29 06:11:31 PM PDT 24
Peak memory 207112 kb
Host smart-b142eaf4-34b3-43b5-b716-4ef954c114d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59620
4701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.596204701
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.100875414
Short name T2685
Test name
Test status
Simulation time 23298112815 ps
CPU time 26.38 seconds
Started Jul 29 06:11:33 PM PDT 24
Finished Jul 29 06:12:00 PM PDT 24
Peak memory 207428 kb
Host smart-0fb45fe3-ddb0-48ef-84df-0ebfa379fa99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
5414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.100875414
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.1951071457
Short name T1725
Test name
Test status
Simulation time 3322005111 ps
CPU time 4.98 seconds
Started Jul 29 06:11:33 PM PDT 24
Finished Jul 29 06:11:38 PM PDT 24
Peak memory 207228 kb
Host smart-f72d3821-c548-4157-bfeb-a92cff86a82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19510
71457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1951071457
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.2226312119
Short name T1548
Test name
Test status
Simulation time 10018000078 ps
CPU time 299.2 seconds
Started Jul 29 06:11:29 PM PDT 24
Finished Jul 29 06:16:28 PM PDT 24
Peak memory 215556 kb
Host smart-075594ab-1d01-4fdd-a693-182c5598b643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22263
12119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.2226312119
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2810277119
Short name T2453
Test name
Test status
Simulation time 2867806325 ps
CPU time 30.29 seconds
Started Jul 29 06:11:31 PM PDT 24
Finished Jul 29 06:12:01 PM PDT 24
Peak memory 217028 kb
Host smart-c680f01f-f5c4-49b7-81ae-5a37ebdbd60b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2810277119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2810277119
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.3936701929
Short name T2846
Test name
Test status
Simulation time 261330400 ps
CPU time 1.06 seconds
Started Jul 29 06:11:30 PM PDT 24
Finished Jul 29 06:11:31 PM PDT 24
Peak memory 207108 kb
Host smart-52de1f87-1504-45f3-9a76-c4fbe684a831
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3936701929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3936701929
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2892399704
Short name T214
Test name
Test status
Simulation time 222939757 ps
CPU time 0.95 seconds
Started Jul 29 06:11:30 PM PDT 24
Finished Jul 29 06:11:31 PM PDT 24
Peak memory 207096 kb
Host smart-080ef843-b678-43df-9ab7-7080e240bb88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28923
99704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2892399704
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.4068742357
Short name T377
Test name
Test status
Simulation time 4125303503 ps
CPU time 42.92 seconds
Started Jul 29 06:11:31 PM PDT 24
Finished Jul 29 06:12:14 PM PDT 24
Peak memory 215652 kb
Host smart-5ed8b4d9-cf1f-482c-8112-08bfc48d43ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40687
42357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.4068742357
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2431325766
Short name T1609
Test name
Test status
Simulation time 4656876358 ps
CPU time 140.47 seconds
Started Jul 29 06:11:30 PM PDT 24
Finished Jul 29 06:13:51 PM PDT 24
Peak memory 215592 kb
Host smart-6d443fba-8cda-4bc0-8f0b-24123152b5b1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2431325766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2431325766
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1735744691
Short name T2551
Test name
Test status
Simulation time 163796038 ps
CPU time 0.89 seconds
Started Jul 29 06:11:34 PM PDT 24
Finished Jul 29 06:11:36 PM PDT 24
Peak memory 207064 kb
Host smart-aec4bf45-7b44-45cd-98e1-b181c07b6a78
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1735744691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1735744691
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3201288016
Short name T2575
Test name
Test status
Simulation time 149864190 ps
CPU time 0.84 seconds
Started Jul 29 06:11:37 PM PDT 24
Finished Jul 29 06:11:37 PM PDT 24
Peak memory 207096 kb
Host smart-2ccf60bd-8a24-48fe-a442-dbaa78b25979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32012
88016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3201288016
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.9010696
Short name T132
Test name
Test status
Simulation time 263380797 ps
CPU time 1.04 seconds
Started Jul 29 06:11:34 PM PDT 24
Finished Jul 29 06:11:35 PM PDT 24
Peak memory 207100 kb
Host smart-c0c1b230-dbca-4844-a8a5-c0a9c2cd9ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90106
96 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.9010696
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2954117292
Short name T2330
Test name
Test status
Simulation time 158589669 ps
CPU time 0.85 seconds
Started Jul 29 06:11:35 PM PDT 24
Finished Jul 29 06:11:36 PM PDT 24
Peak memory 207056 kb
Host smart-cf58c3a5-6128-4c2b-8657-464a62170290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29541
17292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2954117292
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.567753387
Short name T2023
Test name
Test status
Simulation time 195739998 ps
CPU time 0.86 seconds
Started Jul 29 06:11:35 PM PDT 24
Finished Jul 29 06:11:36 PM PDT 24
Peak memory 207004 kb
Host smart-791988b2-71a3-477f-9113-01e1c5d1e011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56775
3387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.567753387
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2413173305
Short name T450
Test name
Test status
Simulation time 178392315 ps
CPU time 0.9 seconds
Started Jul 29 06:11:34 PM PDT 24
Finished Jul 29 06:11:35 PM PDT 24
Peak memory 207056 kb
Host smart-09248f6c-ed4f-499c-8ea1-8f2f4e65d4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24131
73305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2413173305
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.328091742
Short name T1814
Test name
Test status
Simulation time 171538413 ps
CPU time 0.85 seconds
Started Jul 29 06:11:35 PM PDT 24
Finished Jul 29 06:11:36 PM PDT 24
Peak memory 207004 kb
Host smart-9fda2cbe-c3ae-45bc-adab-19d1851e8c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32809
1742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.328091742
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.1072941382
Short name T2187
Test name
Test status
Simulation time 236150352 ps
CPU time 1.01 seconds
Started Jul 29 06:11:33 PM PDT 24
Finished Jul 29 06:11:34 PM PDT 24
Peak memory 207128 kb
Host smart-f559293c-f876-4e7c-8254-0f8d27a57e83
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1072941382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.1072941382
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.709544105
Short name T204
Test name
Test status
Simulation time 247932244 ps
CPU time 1.13 seconds
Started Jul 29 06:11:35 PM PDT 24
Finished Jul 29 06:11:36 PM PDT 24
Peak memory 207088 kb
Host smart-e1eb53d3-7fcd-4401-a456-71bba4e376dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70954
4105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.709544105
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.290562279
Short name T2304
Test name
Test status
Simulation time 151219505 ps
CPU time 0.84 seconds
Started Jul 29 06:11:34 PM PDT 24
Finished Jul 29 06:11:35 PM PDT 24
Peak memory 207016 kb
Host smart-d9aab5b4-8140-46a3-af1b-34d591245244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29056
2279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.290562279
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1240138736
Short name T26
Test name
Test status
Simulation time 35543098 ps
CPU time 0.7 seconds
Started Jul 29 06:11:36 PM PDT 24
Finished Jul 29 06:11:37 PM PDT 24
Peak memory 207064 kb
Host smart-10f1ab33-facc-4499-8906-5934ff41a5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12401
38736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1240138736
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3152963056
Short name T1952
Test name
Test status
Simulation time 21121365066 ps
CPU time 55.27 seconds
Started Jul 29 06:11:33 PM PDT 24
Finished Jul 29 06:12:28 PM PDT 24
Peak memory 215588 kb
Host smart-5d5e2b1b-6067-4982-80b1-89dcf62124a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31529
63056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3152963056
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3189272042
Short name T1757
Test name
Test status
Simulation time 174393302 ps
CPU time 0.9 seconds
Started Jul 29 06:11:43 PM PDT 24
Finished Jul 29 06:11:44 PM PDT 24
Peak memory 207100 kb
Host smart-8685b78a-b795-4a6e-8a6e-6c2453587c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31892
72042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3189272042
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2983012512
Short name T1572
Test name
Test status
Simulation time 235698691 ps
CPU time 1.01 seconds
Started Jul 29 06:11:40 PM PDT 24
Finished Jul 29 06:11:41 PM PDT 24
Peak memory 207076 kb
Host smart-3d1b2b36-3d14-4d4d-879c-b2bca27d8dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29830
12512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2983012512
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.2887075789
Short name T2323
Test name
Test status
Simulation time 8793501948 ps
CPU time 63.09 seconds
Started Jul 29 06:11:39 PM PDT 24
Finished Jul 29 06:12:42 PM PDT 24
Peak memory 223592 kb
Host smart-1ee26b7e-b2e7-46c4-a0ae-5247ca397de7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887075789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.2887075789
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.1816747885
Short name T2484
Test name
Test status
Simulation time 9136224777 ps
CPU time 48.61 seconds
Started Jul 29 06:11:41 PM PDT 24
Finished Jul 29 06:12:30 PM PDT 24
Peak memory 218672 kb
Host smart-26256bdb-12c6-4a19-bbe6-736a9f670a9d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1816747885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.1816747885
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.263011454
Short name T1935
Test name
Test status
Simulation time 11476473795 ps
CPU time 62.27 seconds
Started Jul 29 06:11:42 PM PDT 24
Finished Jul 29 06:12:44 PM PDT 24
Peak memory 223708 kb
Host smart-4f31550e-1169-4368-9c73-5bfdd34ec415
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=263011454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.263011454
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1902469620
Short name T1352
Test name
Test status
Simulation time 200630586 ps
CPU time 0.95 seconds
Started Jul 29 06:11:41 PM PDT 24
Finished Jul 29 06:11:42 PM PDT 24
Peak memory 207092 kb
Host smart-fe49732b-742c-4085-8ddd-097f4a9b8bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19024
69620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1902469620
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.447342511
Short name T445
Test name
Test status
Simulation time 201421680 ps
CPU time 1.02 seconds
Started Jul 29 06:11:39 PM PDT 24
Finished Jul 29 06:11:41 PM PDT 24
Peak memory 207100 kb
Host smart-ca145306-0112-4f19-ac7c-05c78385681d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44734
2511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.447342511
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.3993673206
Short name T2368
Test name
Test status
Simulation time 169755925 ps
CPU time 0.88 seconds
Started Jul 29 06:11:40 PM PDT 24
Finished Jul 29 06:11:41 PM PDT 24
Peak memory 207116 kb
Host smart-f78e9192-4cd8-47f3-b3b6-e61d641ea45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39936
73206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3993673206
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.4102042315
Short name T2358
Test name
Test status
Simulation time 195083950 ps
CPU time 0.92 seconds
Started Jul 29 06:11:40 PM PDT 24
Finished Jul 29 06:11:41 PM PDT 24
Peak memory 207084 kb
Host smart-f54a7f39-a3b3-4c48-8035-3d19bda40d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41020
42315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.4102042315
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.830161909
Short name T192
Test name
Test status
Simulation time 496651793 ps
CPU time 1.2 seconds
Started Jul 29 06:11:43 PM PDT 24
Finished Jul 29 06:11:45 PM PDT 24
Peak memory 223128 kb
Host smart-1170cf70-9d9b-4604-b5ed-7b2c11308348
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=830161909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.830161909
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.4206286522
Short name T59
Test name
Test status
Simulation time 404622222 ps
CPU time 1.45 seconds
Started Jul 29 06:11:43 PM PDT 24
Finished Jul 29 06:11:45 PM PDT 24
Peak memory 207112 kb
Host smart-67754109-17ec-4aef-9886-56d41d151c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42062
86522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.4206286522
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.4155265663
Short name T2818
Test name
Test status
Simulation time 214308593 ps
CPU time 0.91 seconds
Started Jul 29 06:11:40 PM PDT 24
Finished Jul 29 06:11:41 PM PDT 24
Peak memory 207004 kb
Host smart-f9d3f856-1d6e-4bfd-9bcf-40eb348710e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41552
65663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.4155265663
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.4065321045
Short name T2074
Test name
Test status
Simulation time 149845802 ps
CPU time 0.82 seconds
Started Jul 29 06:11:43 PM PDT 24
Finished Jul 29 06:11:44 PM PDT 24
Peak memory 207072 kb
Host smart-6a65b847-bd9b-42df-8be4-ea4180575f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40653
21045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.4065321045
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.763995244
Short name T709
Test name
Test status
Simulation time 169138963 ps
CPU time 0.84 seconds
Started Jul 29 06:11:40 PM PDT 24
Finished Jul 29 06:11:41 PM PDT 24
Peak memory 207092 kb
Host smart-79b2e7f8-1641-4a0f-b7f2-b8051820437c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76399
5244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.763995244
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3235237223
Short name T1269
Test name
Test status
Simulation time 261988093 ps
CPU time 1.02 seconds
Started Jul 29 06:11:42 PM PDT 24
Finished Jul 29 06:11:43 PM PDT 24
Peak memory 206980 kb
Host smart-704e4d82-2c2e-4e2a-877b-6021c76b143f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32352
37223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3235237223
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.3634891395
Short name T1853
Test name
Test status
Simulation time 8045168610 ps
CPU time 83.32 seconds
Started Jul 29 06:11:43 PM PDT 24
Finished Jul 29 06:13:07 PM PDT 24
Peak memory 207420 kb
Host smart-134ba9f2-06ba-4593-b5fe-6f8f989f0f2c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3634891395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.3634891395
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.2179839405
Short name T1158
Test name
Test status
Simulation time 173662598 ps
CPU time 0.88 seconds
Started Jul 29 06:11:45 PM PDT 24
Finished Jul 29 06:11:46 PM PDT 24
Peak memory 207088 kb
Host smart-6ec4132a-1285-4227-803e-69231747e6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21798
39405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.2179839405
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1789307018
Short name T2096
Test name
Test status
Simulation time 161922854 ps
CPU time 0.87 seconds
Started Jul 29 06:11:40 PM PDT 24
Finished Jul 29 06:11:41 PM PDT 24
Peak memory 207100 kb
Host smart-3b08e586-cb8d-4888-bb87-e7aab7ee1144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17893
07018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1789307018
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.1901891269
Short name T1635
Test name
Test status
Simulation time 448615924 ps
CPU time 1.39 seconds
Started Jul 29 06:11:45 PM PDT 24
Finished Jul 29 06:11:46 PM PDT 24
Peak memory 207044 kb
Host smart-a8986e3b-0b50-4001-8beb-7404136a3824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19018
91269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.1901891269
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.143193915
Short name T1398
Test name
Test status
Simulation time 6455126365 ps
CPU time 46.63 seconds
Started Jul 29 06:11:42 PM PDT 24
Finished Jul 29 06:12:29 PM PDT 24
Peak memory 207392 kb
Host smart-5d206e06-6aa8-4a61-a1a9-93517ef1acfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14319
3915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.143193915
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.2166792903
Short name T732
Test name
Test status
Simulation time 720705986 ps
CPU time 15.04 seconds
Started Jul 29 06:11:25 PM PDT 24
Finished Jul 29 06:11:40 PM PDT 24
Peak memory 207304 kb
Host smart-09aec633-af92-46cb-9d52-4e8618d0dba4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166792903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.2166792903
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.1800914924
Short name T942
Test name
Test status
Simulation time 63548656 ps
CPU time 0.74 seconds
Started Jul 29 06:18:10 PM PDT 24
Finished Jul 29 06:18:11 PM PDT 24
Peak memory 207148 kb
Host smart-52ced534-6fa8-4c97-9fe5-b50fd0da7ec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1800914924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.1800914924
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.4005837337
Short name T2639
Test name
Test status
Simulation time 3697233365 ps
CPU time 5.39 seconds
Started Jul 29 06:18:09 PM PDT 24
Finished Jul 29 06:18:14 PM PDT 24
Peak memory 207384 kb
Host smart-f06b4b80-b893-4a81-87e5-25dc445b178c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005837337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.4005837337
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.3122202920
Short name T2048
Test name
Test status
Simulation time 13415987031 ps
CPU time 17.93 seconds
Started Jul 29 06:18:09 PM PDT 24
Finished Jul 29 06:18:27 PM PDT 24
Peak memory 207424 kb
Host smart-f2998b79-6407-4b52-86f1-34d9b1bcb6af
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122202920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.3122202920
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.728058715
Short name T406
Test name
Test status
Simulation time 23376651639 ps
CPU time 36.06 seconds
Started Jul 29 06:18:01 PM PDT 24
Finished Jul 29 06:18:37 PM PDT 24
Peak memory 207388 kb
Host smart-794db4b1-2849-49a5-ba17-04343c4b21df
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728058715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_ao
n_wake_resume.728058715
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3932466955
Short name T1660
Test name
Test status
Simulation time 186138784 ps
CPU time 0.88 seconds
Started Jul 29 06:18:06 PM PDT 24
Finished Jul 29 06:18:07 PM PDT 24
Peak memory 207120 kb
Host smart-fa49d07f-e671-4a2a-ae34-2c2395a53e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39324
66955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3932466955
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.1816197752
Short name T2062
Test name
Test status
Simulation time 144895701 ps
CPU time 0.83 seconds
Started Jul 29 06:18:09 PM PDT 24
Finished Jul 29 06:18:10 PM PDT 24
Peak memory 207076 kb
Host smart-7dc756ff-00db-453b-a0a9-a3cbacfbcf67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18161
97752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.1816197752
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.99891613
Short name T1984
Test name
Test status
Simulation time 490041025 ps
CPU time 1.64 seconds
Started Jul 29 06:18:01 PM PDT 24
Finished Jul 29 06:18:02 PM PDT 24
Peak memory 207116 kb
Host smart-afc10204-62ff-4120-bf1c-9c5c84342db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99891
613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.99891613
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.3811565738
Short name T2430
Test name
Test status
Simulation time 1738353566 ps
CPU time 3.96 seconds
Started Jul 29 06:18:01 PM PDT 24
Finished Jul 29 06:18:05 PM PDT 24
Peak memory 207348 kb
Host smart-0bdfbd9c-7c8c-4b2e-9604-ce31f1f0cf12
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3811565738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.3811565738
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.2881923265
Short name T2353
Test name
Test status
Simulation time 4762669924 ps
CPU time 42.93 seconds
Started Jul 29 06:17:59 PM PDT 24
Finished Jul 29 06:18:42 PM PDT 24
Peak memory 207436 kb
Host smart-25b4f09e-2b83-43f9-823c-e3bc256cf675
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881923265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.2881923265
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2288158755
Short name T1559
Test name
Test status
Simulation time 521556151 ps
CPU time 1.71 seconds
Started Jul 29 06:18:01 PM PDT 24
Finished Jul 29 06:18:03 PM PDT 24
Peak memory 207072 kb
Host smart-8a039a21-2ffa-43d3-80c0-eb79ee1112cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22881
58755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2288158755
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.3181052098
Short name T367
Test name
Test status
Simulation time 162805493 ps
CPU time 0.87 seconds
Started Jul 29 06:18:02 PM PDT 24
Finished Jul 29 06:18:03 PM PDT 24
Peak memory 207044 kb
Host smart-178dcfdc-0a7d-4f3c-9caf-0095b66f6ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31810
52098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3181052098
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.1983337648
Short name T1919
Test name
Test status
Simulation time 38727005 ps
CPU time 0.71 seconds
Started Jul 29 06:18:07 PM PDT 24
Finished Jul 29 06:18:08 PM PDT 24
Peak memory 207112 kb
Host smart-9bac22b8-ef0b-464c-bc00-e216608ae3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19833
37648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1983337648
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2717555903
Short name T2268
Test name
Test status
Simulation time 878051987 ps
CPU time 2.35 seconds
Started Jul 29 06:18:00 PM PDT 24
Finished Jul 29 06:18:03 PM PDT 24
Peak memory 207260 kb
Host smart-8342f600-5cba-49c5-b17e-f8cfa0fd7aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27175
55903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2717555903
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2584967146
Short name T1318
Test name
Test status
Simulation time 194320392 ps
CPU time 2.58 seconds
Started Jul 29 06:18:01 PM PDT 24
Finished Jul 29 06:18:04 PM PDT 24
Peak memory 207228 kb
Host smart-1be473aa-773f-45f6-926e-13ca6d21ba0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25849
67146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2584967146
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.520606103
Short name T497
Test name
Test status
Simulation time 199789724 ps
CPU time 1.07 seconds
Started Jul 29 06:18:03 PM PDT 24
Finished Jul 29 06:18:05 PM PDT 24
Peak memory 215516 kb
Host smart-624ee269-2744-4161-a484-533651a804b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=520606103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.520606103
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1610752942
Short name T2556
Test name
Test status
Simulation time 179839448 ps
CPU time 0.87 seconds
Started Jul 29 06:18:00 PM PDT 24
Finished Jul 29 06:18:01 PM PDT 24
Peak memory 207040 kb
Host smart-8e811512-4208-474d-a8a9-1277a78b58d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16107
52942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1610752942
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2722548033
Short name T828
Test name
Test status
Simulation time 218822298 ps
CPU time 1.06 seconds
Started Jul 29 06:18:01 PM PDT 24
Finished Jul 29 06:18:02 PM PDT 24
Peak memory 207076 kb
Host smart-649350b3-35e5-47aa-9fc8-2227b19f9f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27225
48033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2722548033
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.2212831419
Short name T160
Test name
Test status
Simulation time 5252767300 ps
CPU time 152.42 seconds
Started Jul 29 06:18:08 PM PDT 24
Finished Jul 29 06:20:40 PM PDT 24
Peak memory 215584 kb
Host smart-9b3500ac-b4c0-4a57-afea-ff6faf46a945
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2212831419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2212831419
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.1699760095
Short name T1977
Test name
Test status
Simulation time 5320659525 ps
CPU time 34.17 seconds
Started Jul 29 06:18:04 PM PDT 24
Finished Jul 29 06:18:38 PM PDT 24
Peak memory 207344 kb
Host smart-989700fb-15e8-4468-b13d-50f076ead004
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1699760095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.1699760095
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2585979458
Short name T2623
Test name
Test status
Simulation time 253359895 ps
CPU time 1 seconds
Started Jul 29 06:18:01 PM PDT 24
Finished Jul 29 06:18:02 PM PDT 24
Peak memory 207000 kb
Host smart-c432c388-7e0d-447d-81fc-c84cf43e3083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25859
79458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2585979458
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3927050965
Short name T1980
Test name
Test status
Simulation time 23330856570 ps
CPU time 25.95 seconds
Started Jul 29 06:18:09 PM PDT 24
Finished Jul 29 06:18:35 PM PDT 24
Peak memory 207408 kb
Host smart-134f0454-58c5-43fe-a0c1-18ba643917b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39270
50965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3927050965
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.2012713351
Short name T1349
Test name
Test status
Simulation time 3307063565 ps
CPU time 4.98 seconds
Started Jul 29 06:18:06 PM PDT 24
Finished Jul 29 06:18:11 PM PDT 24
Peak memory 207332 kb
Host smart-8e54e9b5-03bf-4c88-98ca-62d53fb32b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20127
13351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2012713351
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1048603635
Short name T172
Test name
Test status
Simulation time 7773908361 ps
CPU time 74.94 seconds
Started Jul 29 06:18:07 PM PDT 24
Finished Jul 29 06:19:22 PM PDT 24
Peak memory 217480 kb
Host smart-8a111f7e-b2ec-4589-9ade-d40ba4ed4a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10486
03635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1048603635
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1297518877
Short name T1860
Test name
Test status
Simulation time 5766909589 ps
CPU time 164.96 seconds
Started Jul 29 06:18:04 PM PDT 24
Finished Jul 29 06:20:49 PM PDT 24
Peak memory 215608 kb
Host smart-4f20aad5-e3bc-40bc-b6dc-9e78ece3e9d4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1297518877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.1297518877
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2316831761
Short name T409
Test name
Test status
Simulation time 245845859 ps
CPU time 0.98 seconds
Started Jul 29 06:18:12 PM PDT 24
Finished Jul 29 06:18:13 PM PDT 24
Peak memory 207128 kb
Host smart-9213bb8d-84d6-4cda-a6eb-7977fb6dd3b7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2316831761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2316831761
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1971187849
Short name T2242
Test name
Test status
Simulation time 199703157 ps
CPU time 0.94 seconds
Started Jul 29 06:18:06 PM PDT 24
Finished Jul 29 06:18:08 PM PDT 24
Peak memory 207144 kb
Host smart-4c49adb7-c7bc-43d6-ba0f-f49d7fba5610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19711
87849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1971187849
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1791476554
Short name T2325
Test name
Test status
Simulation time 4283683639 ps
CPU time 33.48 seconds
Started Jul 29 06:18:05 PM PDT 24
Finished Jul 29 06:18:39 PM PDT 24
Peak memory 216724 kb
Host smart-0d8d9492-3034-4c20-804f-362f9e21898e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17914
76554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1791476554
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.81964544
Short name T1863
Test name
Test status
Simulation time 5440805285 ps
CPU time 42.37 seconds
Started Jul 29 06:18:12 PM PDT 24
Finished Jul 29 06:18:54 PM PDT 24
Peak memory 216912 kb
Host smart-64e40fbb-a2ad-457b-97e8-c772e0587a23
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=81964544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.81964544
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.2942697137
Short name T834
Test name
Test status
Simulation time 198758923 ps
CPU time 0.92 seconds
Started Jul 29 06:18:07 PM PDT 24
Finished Jul 29 06:18:08 PM PDT 24
Peak memory 207108 kb
Host smart-515d6d71-316f-4f04-9740-525560e1a967
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2942697137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.2942697137
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.569578784
Short name T2352
Test name
Test status
Simulation time 158869726 ps
CPU time 0.84 seconds
Started Jul 29 06:18:05 PM PDT 24
Finished Jul 29 06:18:06 PM PDT 24
Peak memory 207264 kb
Host smart-cac36ef8-e7e0-421c-97ab-f4d2f45e0a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56957
8784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.569578784
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1881344761
Short name T148
Test name
Test status
Simulation time 226439066 ps
CPU time 0.96 seconds
Started Jul 29 06:18:09 PM PDT 24
Finished Jul 29 06:18:10 PM PDT 24
Peak memory 207000 kb
Host smart-a3c95861-2bfe-412e-a8e4-0aac99963bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18813
44761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1881344761
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.214867711
Short name T1594
Test name
Test status
Simulation time 169423793 ps
CPU time 0.91 seconds
Started Jul 29 06:18:10 PM PDT 24
Finished Jul 29 06:18:12 PM PDT 24
Peak memory 206996 kb
Host smart-92d2d083-f335-49b0-8470-7abd91737ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21486
7711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.214867711
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3482444104
Short name T2750
Test name
Test status
Simulation time 156315246 ps
CPU time 0.84 seconds
Started Jul 29 06:18:06 PM PDT 24
Finished Jul 29 06:18:07 PM PDT 24
Peak memory 207136 kb
Host smart-81f025bc-68cb-4c17-a2be-f03cb469498f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34824
44104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3482444104
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.567541604
Short name T830
Test name
Test status
Simulation time 184474922 ps
CPU time 0.95 seconds
Started Jul 29 06:18:11 PM PDT 24
Finished Jul 29 06:18:12 PM PDT 24
Peak memory 207104 kb
Host smart-3b2ce18c-5808-4bce-bb36-14c7becbade7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56754
1604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.567541604
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1095839541
Short name T1267
Test name
Test status
Simulation time 151575801 ps
CPU time 0.86 seconds
Started Jul 29 06:18:07 PM PDT 24
Finished Jul 29 06:18:08 PM PDT 24
Peak memory 207136 kb
Host smart-845edc4d-2885-4f0e-a55a-b73ffe495ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10958
39541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1095839541
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.3827378030
Short name T2759
Test name
Test status
Simulation time 245960861 ps
CPU time 1.01 seconds
Started Jul 29 06:18:03 PM PDT 24
Finished Jul 29 06:18:04 PM PDT 24
Peak memory 207108 kb
Host smart-7ed130a3-788b-4a89-9f81-6f6ddea5c07a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3827378030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.3827378030
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2583463822
Short name T2654
Test name
Test status
Simulation time 154661322 ps
CPU time 0.84 seconds
Started Jul 29 06:18:09 PM PDT 24
Finished Jul 29 06:18:10 PM PDT 24
Peak memory 207084 kb
Host smart-8676325b-7de3-4d66-97ac-102f48a2b3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25834
63822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2583463822
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2397074915
Short name T2483
Test name
Test status
Simulation time 72597831 ps
CPU time 0.75 seconds
Started Jul 29 06:18:10 PM PDT 24
Finished Jul 29 06:18:11 PM PDT 24
Peak memory 206964 kb
Host smart-6eed719e-50e2-4ef2-b0f9-74f649d78af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23970
74915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2397074915
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3631364601
Short name T1539
Test name
Test status
Simulation time 22772489817 ps
CPU time 58.8 seconds
Started Jul 29 06:18:08 PM PDT 24
Finished Jul 29 06:19:07 PM PDT 24
Peak memory 215636 kb
Host smart-303891d6-bf84-4d71-8ad7-d9426fb70711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36313
64601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3631364601
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.168219283
Short name T491
Test name
Test status
Simulation time 163172885 ps
CPU time 0.83 seconds
Started Jul 29 06:18:07 PM PDT 24
Finished Jul 29 06:18:08 PM PDT 24
Peak memory 207064 kb
Host smart-39e864aa-6364-497a-a97f-0c3ed0e4ae57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16821
9283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.168219283
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1761628529
Short name T695
Test name
Test status
Simulation time 174239259 ps
CPU time 0.87 seconds
Started Jul 29 06:18:09 PM PDT 24
Finished Jul 29 06:18:10 PM PDT 24
Peak memory 207096 kb
Host smart-f0a36f43-3cb6-4c8d-b5df-0ea8622a4457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17616
28529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1761628529
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1317111848
Short name T540
Test name
Test status
Simulation time 202078283 ps
CPU time 0.93 seconds
Started Jul 29 06:18:07 PM PDT 24
Finished Jul 29 06:18:08 PM PDT 24
Peak memory 207112 kb
Host smart-dfb1c11d-13f0-4c86-a44d-350c7b5ccf16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13171
11848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1317111848
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.3017797972
Short name T1988
Test name
Test status
Simulation time 181268994 ps
CPU time 1 seconds
Started Jul 29 06:18:06 PM PDT 24
Finished Jul 29 06:18:07 PM PDT 24
Peak memory 207048 kb
Host smart-c010462f-0671-405d-9bd4-5e117c33eada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30177
97972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.3017797972
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.3747757015
Short name T1600
Test name
Test status
Simulation time 160499964 ps
CPU time 0.9 seconds
Started Jul 29 06:18:06 PM PDT 24
Finished Jul 29 06:18:07 PM PDT 24
Peak memory 207064 kb
Host smart-bbb91b56-4370-4dd4-94b4-0c1ff36116c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37477
57015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.3747757015
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.930816429
Short name T2723
Test name
Test status
Simulation time 145539573 ps
CPU time 0.89 seconds
Started Jul 29 06:18:12 PM PDT 24
Finished Jul 29 06:18:13 PM PDT 24
Peak memory 207064 kb
Host smart-aff921af-dde9-470c-bf30-1ca8df81b6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93081
6429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.930816429
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1893640101
Short name T2482
Test name
Test status
Simulation time 155384018 ps
CPU time 0.88 seconds
Started Jul 29 06:18:12 PM PDT 24
Finished Jul 29 06:18:13 PM PDT 24
Peak memory 207092 kb
Host smart-369972d1-46c8-4cbc-9c5a-d171be859056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18936
40101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1893640101
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1691488728
Short name T477
Test name
Test status
Simulation time 234972029 ps
CPU time 1.09 seconds
Started Jul 29 06:18:06 PM PDT 24
Finished Jul 29 06:18:07 PM PDT 24
Peak memory 207064 kb
Host smart-167b286f-6387-4e4e-836e-ab99abf48694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16914
88728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1691488728
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.1519451242
Short name T910
Test name
Test status
Simulation time 4459209858 ps
CPU time 137.17 seconds
Started Jul 29 06:18:07 PM PDT 24
Finished Jul 29 06:20:24 PM PDT 24
Peak memory 215592 kb
Host smart-3dddeebd-218b-4a38-9e06-2c2e24cc6939
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1519451242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.1519451242
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2792829590
Short name T2509
Test name
Test status
Simulation time 158307718 ps
CPU time 0.85 seconds
Started Jul 29 06:18:06 PM PDT 24
Finished Jul 29 06:18:07 PM PDT 24
Peak memory 207116 kb
Host smart-5af6db7c-7559-48d9-a305-2e44be45f54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27928
29590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2792829590
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1225491087
Short name T2299
Test name
Test status
Simulation time 167242549 ps
CPU time 0.87 seconds
Started Jul 29 06:18:09 PM PDT 24
Finished Jul 29 06:18:10 PM PDT 24
Peak memory 207100 kb
Host smart-fce201ab-b71b-4b2f-b822-b10d8cdf620d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12254
91087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1225491087
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.538011874
Short name T961
Test name
Test status
Simulation time 1144116091 ps
CPU time 2.67 seconds
Started Jul 29 06:18:11 PM PDT 24
Finished Jul 29 06:18:13 PM PDT 24
Peak memory 207296 kb
Host smart-143d723e-bcb9-4fdf-b7fe-2c70ba0c5f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53801
1874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.538011874
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3901590218
Short name T1759
Test name
Test status
Simulation time 4379793622 ps
CPU time 127.55 seconds
Started Jul 29 06:18:07 PM PDT 24
Finished Jul 29 06:20:14 PM PDT 24
Peak memory 215544 kb
Host smart-82e144a0-b466-437d-9553-3f3ceae449c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39015
90218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3901590218
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.2191629981
Short name T2799
Test name
Test status
Simulation time 1421894400 ps
CPU time 34.65 seconds
Started Jul 29 06:18:04 PM PDT 24
Finished Jul 29 06:18:39 PM PDT 24
Peak memory 207308 kb
Host smart-2cf6994a-f9e7-42bb-9acb-b0dd84373f82
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191629981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.2191629981
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1067943126
Short name T47
Test name
Test status
Simulation time 89203363 ps
CPU time 0.72 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 207120 kb
Host smart-568f9ebb-c992-4093-af04-891b9ed06c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1067943126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1067943126
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.392112315
Short name T1383
Test name
Test status
Simulation time 3666081707 ps
CPU time 5.47 seconds
Started Jul 29 06:18:15 PM PDT 24
Finished Jul 29 06:18:21 PM PDT 24
Peak memory 207360 kb
Host smart-acdf3155-a5bf-4d85-898d-26f54b4d3c63
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392112315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_ao
n_wake_disconnect.392112315
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3251169369
Short name T2831
Test name
Test status
Simulation time 13392857629 ps
CPU time 16.95 seconds
Started Jul 29 06:18:14 PM PDT 24
Finished Jul 29 06:18:31 PM PDT 24
Peak memory 207420 kb
Host smart-be0f6e19-c383-4dab-af9b-c73714f023ab
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251169369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3251169369
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.1893977809
Short name T218
Test name
Test status
Simulation time 23477300847 ps
CPU time 33.79 seconds
Started Jul 29 06:18:13 PM PDT 24
Finished Jul 29 06:18:46 PM PDT 24
Peak memory 207432 kb
Host smart-14bb0152-e67d-40bc-ba4e-49e27091314c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893977809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.1893977809
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.865118011
Short name T763
Test name
Test status
Simulation time 148095458 ps
CPU time 0.8 seconds
Started Jul 29 06:18:13 PM PDT 24
Finished Jul 29 06:18:14 PM PDT 24
Peak memory 207100 kb
Host smart-9ffdf9f5-067c-4cb9-b3dd-9118561973b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86511
8011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.865118011
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2288746849
Short name T1120
Test name
Test status
Simulation time 179470239 ps
CPU time 0.86 seconds
Started Jul 29 06:18:13 PM PDT 24
Finished Jul 29 06:18:14 PM PDT 24
Peak memory 207032 kb
Host smart-3a028237-bfdc-45cb-9216-fb9f3dadbae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22887
46849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2288746849
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2293620238
Short name T1499
Test name
Test status
Simulation time 274938111 ps
CPU time 1.13 seconds
Started Jul 29 06:18:15 PM PDT 24
Finished Jul 29 06:18:16 PM PDT 24
Peak memory 207116 kb
Host smart-a9884fbf-4c91-424e-9060-90ac22459ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22936
20238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2293620238
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.686814197
Short name T90
Test name
Test status
Simulation time 348514853 ps
CPU time 1.36 seconds
Started Jul 29 06:18:11 PM PDT 24
Finished Jul 29 06:18:12 PM PDT 24
Peak memory 207068 kb
Host smart-36a0f6ba-9ed9-4c46-9e7f-0b0b6e30efcc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=686814197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.686814197
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.868732668
Short name T2143
Test name
Test status
Simulation time 23614362804 ps
CPU time 54.84 seconds
Started Jul 29 06:18:10 PM PDT 24
Finished Jul 29 06:19:05 PM PDT 24
Peak memory 207380 kb
Host smart-2e622f8f-5855-4297-a376-32d1f93e4c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86873
2668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.868732668
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.2922251225
Short name T2785
Test name
Test status
Simulation time 2552777310 ps
CPU time 21.73 seconds
Started Jul 29 06:18:14 PM PDT 24
Finished Jul 29 06:18:36 PM PDT 24
Peak memory 207352 kb
Host smart-5176146d-ac2f-4691-85a9-630c6bcb02f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922251225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.2922251225
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.1562561460
Short name T2046
Test name
Test status
Simulation time 414621844 ps
CPU time 1.32 seconds
Started Jul 29 06:18:13 PM PDT 24
Finished Jul 29 06:18:14 PM PDT 24
Peak memory 207104 kb
Host smart-aeecdb6b-6ccb-4d00-abd9-2ea9dd9f8ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15625
61460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.1562561460
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.2594086966
Short name T1520
Test name
Test status
Simulation time 158749708 ps
CPU time 0.85 seconds
Started Jul 29 06:18:11 PM PDT 24
Finished Jul 29 06:18:12 PM PDT 24
Peak memory 207220 kb
Host smart-95947746-8929-4550-9861-cf5a856e7f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25940
86966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.2594086966
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.65496185
Short name T2608
Test name
Test status
Simulation time 58188637 ps
CPU time 0.76 seconds
Started Jul 29 06:18:11 PM PDT 24
Finished Jul 29 06:18:12 PM PDT 24
Peak memory 207032 kb
Host smart-b4f17f5c-0455-44e0-acbd-1fa5655cb60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65496
185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.65496185
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.2815065460
Short name T1837
Test name
Test status
Simulation time 731499024 ps
CPU time 2.09 seconds
Started Jul 29 06:18:15 PM PDT 24
Finished Jul 29 06:18:17 PM PDT 24
Peak memory 207204 kb
Host smart-413394c7-c1d6-48d0-91f4-c36f4cf165a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28150
65460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2815065460
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2835506294
Short name T2274
Test name
Test status
Simulation time 298516469 ps
CPU time 2.47 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 207244 kb
Host smart-eeb678a3-8dc9-41ed-80cb-5d825a78d142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28355
06294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2835506294
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1411360122
Short name T1904
Test name
Test status
Simulation time 220850488 ps
CPU time 1.05 seconds
Started Jul 29 06:18:18 PM PDT 24
Finished Jul 29 06:18:20 PM PDT 24
Peak memory 207316 kb
Host smart-b0f62f4f-7d3b-4144-8906-3fbdb326e4ad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1411360122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1411360122
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2127796006
Short name T1430
Test name
Test status
Simulation time 140416875 ps
CPU time 0.87 seconds
Started Jul 29 06:18:14 PM PDT 24
Finished Jul 29 06:18:15 PM PDT 24
Peak memory 207008 kb
Host smart-fc0700c5-5d15-461f-a6d3-de2e9894940f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21277
96006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2127796006
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3893415642
Short name T1715
Test name
Test status
Simulation time 232978211 ps
CPU time 0.97 seconds
Started Jul 29 06:18:10 PM PDT 24
Finished Jul 29 06:18:11 PM PDT 24
Peak memory 207072 kb
Host smart-8c11f8d6-fa93-4814-ab5a-7e04188e86cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38934
15642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3893415642
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.1046650124
Short name T1767
Test name
Test status
Simulation time 5017337936 ps
CPU time 37.71 seconds
Started Jul 29 06:18:11 PM PDT 24
Finished Jul 29 06:18:49 PM PDT 24
Peak memory 217156 kb
Host smart-1a0ff16b-f0ff-49a7-a66e-ded46aecda8c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1046650124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.1046650124
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.819705587
Short name T1958
Test name
Test status
Simulation time 7751398003 ps
CPU time 51.96 seconds
Started Jul 29 06:18:11 PM PDT 24
Finished Jul 29 06:19:03 PM PDT 24
Peak memory 207404 kb
Host smart-bb81884b-7ee2-4bdd-90f4-904805445571
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=819705587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.819705587
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2382112859
Short name T105
Test name
Test status
Simulation time 263100751 ps
CPU time 1 seconds
Started Jul 29 06:18:11 PM PDT 24
Finished Jul 29 06:18:12 PM PDT 24
Peak memory 207104 kb
Host smart-437abd97-8579-4c87-a026-3cb07dbd333f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23821
12859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2382112859
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.2674494124
Short name T1389
Test name
Test status
Simulation time 23265630111 ps
CPU time 28.1 seconds
Started Jul 29 06:18:18 PM PDT 24
Finished Jul 29 06:18:46 PM PDT 24
Peak memory 207400 kb
Host smart-13d24f32-6002-4ac5-9636-05d0f218fcf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26744
94124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.2674494124
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2920839030
Short name T2388
Test name
Test status
Simulation time 3330310286 ps
CPU time 4.6 seconds
Started Jul 29 06:18:15 PM PDT 24
Finished Jul 29 06:18:20 PM PDT 24
Peak memory 207368 kb
Host smart-9b867b10-c34b-40e8-9474-b44059630c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29208
39030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2920839030
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.2583046071
Short name T2698
Test name
Test status
Simulation time 4616749951 ps
CPU time 43.45 seconds
Started Jul 29 06:18:18 PM PDT 24
Finished Jul 29 06:19:02 PM PDT 24
Peak memory 217260 kb
Host smart-1470e46e-31bb-499d-953f-c24dbd30d971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25830
46071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.2583046071
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.2747570947
Short name T165
Test name
Test status
Simulation time 4314725478 ps
CPU time 42.82 seconds
Started Jul 29 06:18:14 PM PDT 24
Finished Jul 29 06:18:57 PM PDT 24
Peak memory 207336 kb
Host smart-2edd8e43-7f51-40a6-8fef-983be1ad6bcb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2747570947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.2747570947
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.2502462014
Short name T1693
Test name
Test status
Simulation time 283813634 ps
CPU time 0.99 seconds
Started Jul 29 06:18:13 PM PDT 24
Finished Jul 29 06:18:14 PM PDT 24
Peak memory 207056 kb
Host smart-e0404c9f-21d1-4645-8e70-4fe3c23b5673
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2502462014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.2502462014
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3656856767
Short name T434
Test name
Test status
Simulation time 215610570 ps
CPU time 0.99 seconds
Started Jul 29 06:18:13 PM PDT 24
Finished Jul 29 06:18:15 PM PDT 24
Peak memory 207096 kb
Host smart-c110e63e-019a-4d3f-a574-9a2aa6c05077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36568
56767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3656856767
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.2458528045
Short name T2576
Test name
Test status
Simulation time 6465395676 ps
CPU time 65.02 seconds
Started Jul 29 06:18:12 PM PDT 24
Finished Jul 29 06:19:18 PM PDT 24
Peak memory 217032 kb
Host smart-ce8b2b25-87bd-4fc7-a157-9c449682e350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24585
28045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.2458528045
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2408911039
Short name T1898
Test name
Test status
Simulation time 4608355647 ps
CPU time 34.62 seconds
Started Jul 29 06:18:11 PM PDT 24
Finished Jul 29 06:18:46 PM PDT 24
Peak memory 207360 kb
Host smart-7dd4ae55-3a50-4773-90e6-75b1860c3cb9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2408911039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2408911039
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.1054582928
Short name T299
Test name
Test status
Simulation time 149224441 ps
CPU time 0.85 seconds
Started Jul 29 06:18:18 PM PDT 24
Finished Jul 29 06:18:19 PM PDT 24
Peak memory 207116 kb
Host smart-c48fe048-e1ff-432d-90a3-fca3f723ea39
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1054582928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.1054582928
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1323383606
Short name T31
Test name
Test status
Simulation time 205871662 ps
CPU time 0.92 seconds
Started Jul 29 06:18:20 PM PDT 24
Finished Jul 29 06:18:21 PM PDT 24
Peak memory 207128 kb
Host smart-e58fc82f-090e-4625-b7c7-81d147bfb91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13233
83606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1323383606
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.4224648086
Short name T139
Test name
Test status
Simulation time 206447435 ps
CPU time 0.95 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 207040 kb
Host smart-a50e4e19-4f5a-4dd7-8714-5d8e745b4331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42246
48086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.4224648086
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2749471755
Short name T454
Test name
Test status
Simulation time 217847141 ps
CPU time 0.92 seconds
Started Jul 29 06:18:18 PM PDT 24
Finished Jul 29 06:18:19 PM PDT 24
Peak memory 207044 kb
Host smart-71a73991-a6a3-42d4-87f7-b6c51df1812e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27494
71755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2749471755
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.270534162
Short name T444
Test name
Test status
Simulation time 177125669 ps
CPU time 0.93 seconds
Started Jul 29 06:18:21 PM PDT 24
Finished Jul 29 06:18:22 PM PDT 24
Peak memory 207100 kb
Host smart-6734c26d-658c-431b-b6ec-6b2a789c4c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27053
4162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.270534162
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2490247101
Short name T272
Test name
Test status
Simulation time 184226334 ps
CPU time 0.92 seconds
Started Jul 29 06:18:19 PM PDT 24
Finished Jul 29 06:18:20 PM PDT 24
Peak memory 207072 kb
Host smart-b69d132e-9420-4004-bf8d-e891853a722a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24902
47101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2490247101
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2454503168
Short name T2683
Test name
Test status
Simulation time 152202667 ps
CPU time 0.87 seconds
Started Jul 29 06:18:22 PM PDT 24
Finished Jul 29 06:18:23 PM PDT 24
Peak memory 207112 kb
Host smart-af69b209-d2c1-4db2-b902-e7d0f30b20b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24545
03168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2454503168
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.3503988232
Short name T1217
Test name
Test status
Simulation time 234334721 ps
CPU time 1.06 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 207084 kb
Host smart-b3eeeca8-be8c-4b01-a94b-9cd675046922
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3503988232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.3503988232
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3399126709
Short name T862
Test name
Test status
Simulation time 148511648 ps
CPU time 0.82 seconds
Started Jul 29 06:18:18 PM PDT 24
Finished Jul 29 06:18:19 PM PDT 24
Peak memory 207068 kb
Host smart-1fbb74a1-d805-4bbc-a2e0-45a81ff51e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33991
26709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3399126709
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.1327918036
Short name T624
Test name
Test status
Simulation time 36600502 ps
CPU time 0.67 seconds
Started Jul 29 06:18:18 PM PDT 24
Finished Jul 29 06:18:19 PM PDT 24
Peak memory 207108 kb
Host smart-fb3c938b-57cc-4b08-8563-298478c7923c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13279
18036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.1327918036
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1454861673
Short name T1907
Test name
Test status
Simulation time 19677246832 ps
CPU time 47.72 seconds
Started Jul 29 06:18:20 PM PDT 24
Finished Jul 29 06:19:08 PM PDT 24
Peak memory 215672 kb
Host smart-5bd45096-635c-484b-b66d-bcd9998322b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14548
61673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1454861673
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1801316559
Short name T1500
Test name
Test status
Simulation time 157512645 ps
CPU time 0.83 seconds
Started Jul 29 06:18:18 PM PDT 24
Finished Jul 29 06:18:19 PM PDT 24
Peak memory 207056 kb
Host smart-3aa98395-072d-4e40-8aa8-ed06c634f075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18013
16559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1801316559
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3354514246
Short name T1553
Test name
Test status
Simulation time 202792403 ps
CPU time 0.9 seconds
Started Jul 29 06:18:19 PM PDT 24
Finished Jul 29 06:18:20 PM PDT 24
Peak memory 207072 kb
Host smart-d3c77143-2b51-400e-ad06-7ffbcfe40e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33545
14246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3354514246
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.2776076040
Short name T2206
Test name
Test status
Simulation time 178960194 ps
CPU time 0.98 seconds
Started Jul 29 06:18:16 PM PDT 24
Finished Jul 29 06:18:18 PM PDT 24
Peak memory 207140 kb
Host smart-e63021ae-85e3-45cf-abca-8cd7a83fff25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27760
76040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.2776076040
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.1403395936
Short name T2545
Test name
Test status
Simulation time 159098504 ps
CPU time 0.91 seconds
Started Jul 29 06:18:24 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 207092 kb
Host smart-61104757-4db9-46fc-85e8-7b2ced4229b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14033
95936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.1403395936
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.603135576
Short name T408
Test name
Test status
Simulation time 133193586 ps
CPU time 0.81 seconds
Started Jul 29 06:18:20 PM PDT 24
Finished Jul 29 06:18:20 PM PDT 24
Peak memory 207068 kb
Host smart-ed6d74ca-3722-4fb9-89b5-ee965af56363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60313
5576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.603135576
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2196184496
Short name T368
Test name
Test status
Simulation time 156818641 ps
CPU time 0.83 seconds
Started Jul 29 06:18:19 PM PDT 24
Finished Jul 29 06:18:20 PM PDT 24
Peak memory 207080 kb
Host smart-edc7b1e1-d7c9-4f11-8a10-ad1e4dabd1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21961
84496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2196184496
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.711812602
Short name T2129
Test name
Test status
Simulation time 153920438 ps
CPU time 0.84 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207084 kb
Host smart-b84fe739-f1dd-4a51-81f6-60fc8c180e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71181
2602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.711812602
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2614114832
Short name T1893
Test name
Test status
Simulation time 238832302 ps
CPU time 1.02 seconds
Started Jul 29 06:18:20 PM PDT 24
Finished Jul 29 06:18:21 PM PDT 24
Peak memory 207076 kb
Host smart-1c9012ea-b7a9-4512-94d9-ac569ed8c297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26141
14832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2614114832
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2920640486
Short name T154
Test name
Test status
Simulation time 3852660228 ps
CPU time 39.07 seconds
Started Jul 29 06:18:20 PM PDT 24
Finished Jul 29 06:18:59 PM PDT 24
Peak memory 215524 kb
Host smart-05bcd795-1d2f-4bcf-a2be-ed42713c0d32
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2920640486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2920640486
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.4018996865
Short name T2128
Test name
Test status
Simulation time 180574312 ps
CPU time 0.89 seconds
Started Jul 29 06:18:17 PM PDT 24
Finished Jul 29 06:18:18 PM PDT 24
Peak memory 207104 kb
Host smart-3326f015-fa81-44f1-81bc-0ca35956d368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40189
96865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.4018996865
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3885462954
Short name T1143
Test name
Test status
Simulation time 206344710 ps
CPU time 0.96 seconds
Started Jul 29 06:18:26 PM PDT 24
Finished Jul 29 06:18:27 PM PDT 24
Peak memory 207084 kb
Host smart-00401944-387b-494e-a446-1c7a372a2cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38854
62954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3885462954
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.1739608883
Short name T1544
Test name
Test status
Simulation time 1118508750 ps
CPU time 2.72 seconds
Started Jul 29 06:18:24 PM PDT 24
Finished Jul 29 06:18:27 PM PDT 24
Peak memory 207256 kb
Host smart-faba7599-6890-41c8-bc77-2b63fdb2c2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17396
08883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.1739608883
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.3892787833
Short name T2176
Test name
Test status
Simulation time 5623438537 ps
CPU time 166.9 seconds
Started Jul 29 06:18:18 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 215512 kb
Host smart-96d54c04-915e-4411-9980-d4464e492249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38927
87833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.3892787833
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.3168802674
Short name T2514
Test name
Test status
Simulation time 1132313755 ps
CPU time 27.02 seconds
Started Jul 29 06:18:11 PM PDT 24
Finished Jul 29 06:18:38 PM PDT 24
Peak memory 207268 kb
Host smart-82841401-ae53-4bd6-bcff-26b9d1ed64a5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168802674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.3168802674
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.3267764212
Short name T2768
Test name
Test status
Simulation time 35415360 ps
CPU time 0.68 seconds
Started Jul 29 06:18:29 PM PDT 24
Finished Jul 29 06:18:30 PM PDT 24
Peak memory 207104 kb
Host smart-c576e5bc-1a0f-4c0d-8750-030f95796801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3267764212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.3267764212
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.1272085643
Short name T437
Test name
Test status
Simulation time 3570132934 ps
CPU time 5.62 seconds
Started Jul 29 06:18:19 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 207256 kb
Host smart-f1525e78-ee8e-4e18-8427-f238d36155c6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272085643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.1272085643
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3732570757
Short name T1802
Test name
Test status
Simulation time 13295944341 ps
CPU time 16.51 seconds
Started Jul 29 06:18:19 PM PDT 24
Finished Jul 29 06:18:35 PM PDT 24
Peak memory 207372 kb
Host smart-d6f15bff-3239-4634-b9f2-be6438c657c9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732570757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3732570757
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.3221296723
Short name T779
Test name
Test status
Simulation time 23323365675 ps
CPU time 29.72 seconds
Started Jul 29 06:18:20 PM PDT 24
Finished Jul 29 06:18:50 PM PDT 24
Peak memory 207372 kb
Host smart-ed148e94-ad76-46e8-a2a6-8c1985086d96
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221296723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.3221296723
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1162411478
Short name T892
Test name
Test status
Simulation time 147409703 ps
CPU time 0.82 seconds
Started Jul 29 06:18:22 PM PDT 24
Finished Jul 29 06:18:23 PM PDT 24
Peak memory 207140 kb
Host smart-53dd75e5-dd1c-4cdc-8f67-7d9fe90bd940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11624
11478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1162411478
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.387587713
Short name T703
Test name
Test status
Simulation time 161893343 ps
CPU time 0.87 seconds
Started Jul 29 06:18:22 PM PDT 24
Finished Jul 29 06:18:23 PM PDT 24
Peak memory 206996 kb
Host smart-3e6ae3f3-387f-40d6-9b24-bebd78de2f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38758
7713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.387587713
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.90692896
Short name T378
Test name
Test status
Simulation time 268685729 ps
CPU time 1.18 seconds
Started Jul 29 06:18:21 PM PDT 24
Finished Jul 29 06:18:23 PM PDT 24
Peak memory 207100 kb
Host smart-79bd24c6-c02d-4033-8482-d8f4d3b1b9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90692
896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.90692896
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.946426931
Short name T2840
Test name
Test status
Simulation time 1475971304 ps
CPU time 3.22 seconds
Started Jul 29 06:18:21 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 207280 kb
Host smart-ed68a518-ab13-49e3-8a7f-58aca5e4bf1a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=946426931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.946426931
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.2302389820
Short name T1125
Test name
Test status
Simulation time 2486765260 ps
CPU time 20.96 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:44 PM PDT 24
Peak memory 207392 kb
Host smart-bc98b941-7d27-42c1-8dcc-a2fb43d9212d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302389820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.2302389820
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.1654880751
Short name T647
Test name
Test status
Simulation time 448117158 ps
CPU time 1.49 seconds
Started Jul 29 06:18:22 PM PDT 24
Finished Jul 29 06:18:23 PM PDT 24
Peak memory 207084 kb
Host smart-190d1cc8-25c6-41e6-aa16-91cb83badb12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16548
80751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.1654880751
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.10153160
Short name T330
Test name
Test status
Simulation time 146834461 ps
CPU time 0.85 seconds
Started Jul 29 06:18:22 PM PDT 24
Finished Jul 29 06:18:23 PM PDT 24
Peak memory 207088 kb
Host smart-e9c58119-18ad-4f66-b862-31d245f2305b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10153
160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.10153160
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1170153296
Short name T731
Test name
Test status
Simulation time 43585606 ps
CPU time 0.7 seconds
Started Jul 29 06:18:19 PM PDT 24
Finished Jul 29 06:18:20 PM PDT 24
Peak memory 207076 kb
Host smart-188cc9a5-b9e0-473a-8cf7-e80e3b2f6a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11701
53296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1170153296
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2091010183
Short name T1531
Test name
Test status
Simulation time 798101249 ps
CPU time 2.12 seconds
Started Jul 29 06:18:20 PM PDT 24
Finished Jul 29 06:18:22 PM PDT 24
Peak memory 207336 kb
Host smart-f16b9ef4-e020-4b37-9ac7-85f3b2e5baee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20910
10183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2091010183
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2998975965
Short name T820
Test name
Test status
Simulation time 336481544 ps
CPU time 3.08 seconds
Started Jul 29 06:18:17 PM PDT 24
Finished Jul 29 06:18:20 PM PDT 24
Peak memory 207260 kb
Host smart-bb75c9b1-03c3-471c-aed0-6fd86722c4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29989
75965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2998975965
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3942300374
Short name T2524
Test name
Test status
Simulation time 182225837 ps
CPU time 0.95 seconds
Started Jul 29 06:18:22 PM PDT 24
Finished Jul 29 06:18:23 PM PDT 24
Peak memory 207104 kb
Host smart-6ee9a2e9-1d58-4b53-8981-d144f0571492
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3942300374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3942300374
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2961414347
Short name T2367
Test name
Test status
Simulation time 146233907 ps
CPU time 0.87 seconds
Started Jul 29 06:18:21 PM PDT 24
Finished Jul 29 06:18:22 PM PDT 24
Peak memory 207044 kb
Host smart-fa2190ea-eac8-4493-a6d9-3eb194b00a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29614
14347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2961414347
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.31605091
Short name T849
Test name
Test status
Simulation time 226336643 ps
CPU time 1.05 seconds
Started Jul 29 06:18:26 PM PDT 24
Finished Jul 29 06:18:27 PM PDT 24
Peak memory 207116 kb
Host smart-59f6cad0-dcfb-414d-b13f-83a78d3acc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31605
091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.31605091
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1492921918
Short name T2826
Test name
Test status
Simulation time 9027476050 ps
CPU time 260.69 seconds
Started Jul 29 06:18:19 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 215552 kb
Host smart-e1c3e7fe-7f29-4dc1-94af-9c1728f74cf8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1492921918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1492921918
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.3760603131
Short name T2744
Test name
Test status
Simulation time 3979999391 ps
CPU time 49.98 seconds
Started Jul 29 06:18:22 PM PDT 24
Finished Jul 29 06:19:12 PM PDT 24
Peak memory 207312 kb
Host smart-799a14af-2c91-42ff-95e2-1a9dc34401c1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3760603131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.3760603131
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.2992497340
Short name T504
Test name
Test status
Simulation time 195953488 ps
CPU time 0.92 seconds
Started Jul 29 06:18:29 PM PDT 24
Finished Jul 29 06:18:30 PM PDT 24
Peak memory 207084 kb
Host smart-0c8220c2-55da-4bd4-972c-f1ea861660b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29924
97340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2992497340
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1768024934
Short name T1291
Test name
Test status
Simulation time 23297619532 ps
CPU time 35.34 seconds
Started Jul 29 06:18:25 PM PDT 24
Finished Jul 29 06:19:00 PM PDT 24
Peak memory 207412 kb
Host smart-4c1783e2-99b1-4d42-a6e5-ec8c90f60663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17680
24934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1768024934
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1310767714
Short name T657
Test name
Test status
Simulation time 3291617531 ps
CPU time 4.48 seconds
Started Jul 29 06:18:22 PM PDT 24
Finished Jul 29 06:18:26 PM PDT 24
Peak memory 207348 kb
Host smart-101495f4-993d-441e-954c-3b366f51634c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13107
67714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1310767714
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.3610651655
Short name T4
Test name
Test status
Simulation time 6498673740 ps
CPU time 179.76 seconds
Started Jul 29 06:18:29 PM PDT 24
Finished Jul 29 06:21:29 PM PDT 24
Peak memory 215692 kb
Host smart-534b8f3b-034d-44eb-8b78-1495df51e9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36106
51655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.3610651655
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.1485116243
Short name T6
Test name
Test status
Simulation time 5023595460 ps
CPU time 152.8 seconds
Started Jul 29 06:18:22 PM PDT 24
Finished Jul 29 06:20:55 PM PDT 24
Peak memory 215740 kb
Host smart-4fdfd25a-b490-428c-8885-05eecd4dfe01
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1485116243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.1485116243
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.1409613828
Short name T2534
Test name
Test status
Simulation time 264992469 ps
CPU time 1.07 seconds
Started Jul 29 06:18:24 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 207160 kb
Host smart-989bd91c-10eb-42a1-bba2-4ef5a09c6bfa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1409613828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.1409613828
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.599383230
Short name T1446
Test name
Test status
Simulation time 208278795 ps
CPU time 1.01 seconds
Started Jul 29 06:18:26 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207100 kb
Host smart-c25af744-d345-4ac0-9bb5-a5a89716c347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59938
3230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.599383230
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.1999430231
Short name T344
Test name
Test status
Simulation time 4225299585 ps
CPU time 33.68 seconds
Started Jul 29 06:18:24 PM PDT 24
Finished Jul 29 06:18:58 PM PDT 24
Peak memory 217244 kb
Host smart-33d6aab1-729a-4b69-8bea-ac5b84828fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19994
30231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.1999430231
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3895119455
Short name T1348
Test name
Test status
Simulation time 6953171422 ps
CPU time 54.05 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:19:18 PM PDT 24
Peak memory 207396 kb
Host smart-7c4d7b4d-a333-48e0-9271-29fc94328bd0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3895119455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3895119455
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.4056847015
Short name T2838
Test name
Test status
Simulation time 157765166 ps
CPU time 0.9 seconds
Started Jul 29 06:18:25 PM PDT 24
Finished Jul 29 06:18:26 PM PDT 24
Peak memory 207112 kb
Host smart-0b337c3f-bc2a-40a3-bc1e-c3ec09b00910
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4056847015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.4056847015
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2133953553
Short name T310
Test name
Test status
Simulation time 142619718 ps
CPU time 0.85 seconds
Started Jul 29 06:18:25 PM PDT 24
Finished Jul 29 06:18:26 PM PDT 24
Peak memory 207100 kb
Host smart-b75dc67a-b1f6-45ab-8a42-bfe2cbbf4108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21339
53553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2133953553
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3408704487
Short name T149
Test name
Test status
Simulation time 192631400 ps
CPU time 0.93 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 207120 kb
Host smart-8437953b-7f22-4bf9-97c2-71bce5c23feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34087
04487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3408704487
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.272796945
Short name T425
Test name
Test status
Simulation time 174832072 ps
CPU time 0.85 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207076 kb
Host smart-147c47a1-82bd-450f-87c0-764a7bb17f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27279
6945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.272796945
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3282170911
Short name T1025
Test name
Test status
Simulation time 159706075 ps
CPU time 0.85 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 207092 kb
Host smart-b9512e66-ea06-4e15-961e-6b23aecde80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32821
70911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3282170911
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.960739696
Short name T1443
Test name
Test status
Simulation time 164605233 ps
CPU time 0.86 seconds
Started Jul 29 06:18:22 PM PDT 24
Finished Jul 29 06:18:23 PM PDT 24
Peak memory 207104 kb
Host smart-91095b75-223c-4502-aea4-b71729bb57a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96073
9696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.960739696
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2719878925
Short name T1758
Test name
Test status
Simulation time 176702228 ps
CPU time 0.88 seconds
Started Jul 29 06:18:22 PM PDT 24
Finished Jul 29 06:18:23 PM PDT 24
Peak memory 207048 kb
Host smart-022cfa06-c848-4ff0-9c90-aec00e173d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27198
78925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2719878925
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.1428826580
Short name T1305
Test name
Test status
Simulation time 215083988 ps
CPU time 0.96 seconds
Started Jul 29 06:18:26 PM PDT 24
Finished Jul 29 06:18:27 PM PDT 24
Peak memory 207080 kb
Host smart-3e927ff0-b03a-4022-ad7b-2b2315022b9c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1428826580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.1428826580
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2362748275
Short name T1785
Test name
Test status
Simulation time 157779888 ps
CPU time 0.83 seconds
Started Jul 29 06:18:26 PM PDT 24
Finished Jul 29 06:18:27 PM PDT 24
Peak memory 207068 kb
Host smart-cfaff926-404e-456d-bee9-fa494c4fb9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23627
48275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2362748275
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2952051277
Short name T1392
Test name
Test status
Simulation time 36314284 ps
CPU time 0.69 seconds
Started Jul 29 06:18:24 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 206948 kb
Host smart-50a67fd8-9c9c-4a34-84e7-eaa109350d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29520
51277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2952051277
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.775939676
Short name T2224
Test name
Test status
Simulation time 11435184521 ps
CPU time 26.76 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:55 PM PDT 24
Peak memory 223848 kb
Host smart-114ff23e-51df-4908-aafa-fe5e1dd26f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77593
9676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.775939676
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.633251920
Short name T1656
Test name
Test status
Simulation time 185880274 ps
CPU time 0.92 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 207188 kb
Host smart-65f1562d-8cf8-4843-9b37-7fb4f77d65c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63325
1920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.633251920
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2655851343
Short name T211
Test name
Test status
Simulation time 230807238 ps
CPU time 1 seconds
Started Jul 29 06:18:24 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 207040 kb
Host smart-f1c51389-9eb6-4f1c-bd26-be6e5db21c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26558
51343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2655851343
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.908296602
Short name T867
Test name
Test status
Simulation time 260501680 ps
CPU time 0.98 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 207076 kb
Host smart-74aa08f0-5581-459a-9551-13f4e2e89dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90829
6602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.908296602
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3954085963
Short name T1013
Test name
Test status
Simulation time 157748971 ps
CPU time 0.89 seconds
Started Jul 29 06:18:24 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 207068 kb
Host smart-d5e4a8e7-25a7-4477-9fb0-2d3ebdd42505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39540
85963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3954085963
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1989723018
Short name T520
Test name
Test status
Simulation time 159771903 ps
CPU time 0.86 seconds
Started Jul 29 06:18:25 PM PDT 24
Finished Jul 29 06:18:26 PM PDT 24
Peak memory 207048 kb
Host smart-8cc55fec-17e8-4384-aed3-77a1f3962e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19897
23018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1989723018
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.401711945
Short name T458
Test name
Test status
Simulation time 177855808 ps
CPU time 0.88 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 207024 kb
Host smart-dd92f2ff-a9f6-43b8-a09d-6139194d9ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40171
1945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.401711945
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3161997243
Short name T890
Test name
Test status
Simulation time 143523581 ps
CPU time 0.85 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 206996 kb
Host smart-194c95a7-5400-4a88-87c8-da7d47ee98b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31619
97243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3161997243
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3521457827
Short name T2719
Test name
Test status
Simulation time 217763607 ps
CPU time 1.03 seconds
Started Jul 29 06:18:24 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 207100 kb
Host smart-e7fe9dfb-6272-400d-8c29-c0c0835fe523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35214
57827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3521457827
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.188006088
Short name T615
Test name
Test status
Simulation time 6423291254 ps
CPU time 65.04 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:19:28 PM PDT 24
Peak memory 215588 kb
Host smart-7248e7e2-206a-4b70-9d8d-9cf2e1ef53b8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=188006088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.188006088
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1559351060
Short name T1924
Test name
Test status
Simulation time 186691818 ps
CPU time 0.88 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 207080 kb
Host smart-1a187999-8755-4311-aa64-e252d9165648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15593
51060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1559351060
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.1159936690
Short name T455
Test name
Test status
Simulation time 150843199 ps
CPU time 0.87 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 207100 kb
Host smart-cf1a1924-1f6b-42dd-8798-56c2e49af8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11599
36690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.1159936690
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.2431932058
Short name T2312
Test name
Test status
Simulation time 686504856 ps
CPU time 1.92 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:25 PM PDT 24
Peak memory 207044 kb
Host smart-8ffe0325-3365-48d7-886f-d8dfe46a07a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24319
32058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.2431932058
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.3557060945
Short name T1310
Test name
Test status
Simulation time 4951505987 ps
CPU time 55.61 seconds
Started Jul 29 06:18:22 PM PDT 24
Finished Jul 29 06:19:18 PM PDT 24
Peak memory 207352 kb
Host smart-08a60a68-2f76-4866-91e7-443a358e961c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35570
60945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.3557060945
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.3104642351
Short name T2082
Test name
Test status
Simulation time 2498910944 ps
CPU time 20.66 seconds
Started Jul 29 06:18:18 PM PDT 24
Finished Jul 29 06:18:39 PM PDT 24
Peak memory 207304 kb
Host smart-3a2d43b6-5f64-4360-a065-0d69e7f8d8c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104642351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.3104642351
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.587887131
Short name T2782
Test name
Test status
Simulation time 37399898 ps
CPU time 0.68 seconds
Started Jul 29 06:18:35 PM PDT 24
Finished Jul 29 06:18:36 PM PDT 24
Peak memory 207164 kb
Host smart-b31e48a0-6780-4ef6-9eb3-1f71603b495c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=587887131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.587887131
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3336083354
Short name T836
Test name
Test status
Simulation time 4048269040 ps
CPU time 5.59 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207300 kb
Host smart-7387c516-5610-4a07-a3c7-12155c662717
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336083354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.3336083354
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.2611117419
Short name T1204
Test name
Test status
Simulation time 13306784648 ps
CPU time 15.74 seconds
Started Jul 29 06:18:27 PM PDT 24
Finished Jul 29 06:18:43 PM PDT 24
Peak memory 207424 kb
Host smart-535665d2-c7e5-47a2-8889-2d68d609ddf7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611117419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.2611117419
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3403763639
Short name T1418
Test name
Test status
Simulation time 23378193936 ps
CPU time 28.82 seconds
Started Jul 29 06:18:23 PM PDT 24
Finished Jul 29 06:18:52 PM PDT 24
Peak memory 207424 kb
Host smart-a15842cc-aaa3-4a72-8163-15566eb07d7a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403763639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.3403763639
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3622074276
Short name T1597
Test name
Test status
Simulation time 151062345 ps
CPU time 0.9 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207064 kb
Host smart-7e2c0ee0-74bd-4896-ba21-a52799ddef9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36220
74276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3622074276
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.1276229134
Short name T1227
Test name
Test status
Simulation time 149673100 ps
CPU time 0.87 seconds
Started Jul 29 06:18:29 PM PDT 24
Finished Jul 29 06:18:30 PM PDT 24
Peak memory 207096 kb
Host smart-07753f9f-af38-46d8-b6bb-4bfe1469f77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12762
29134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.1276229134
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.302774395
Short name T2696
Test name
Test status
Simulation time 337286713 ps
CPU time 1.27 seconds
Started Jul 29 06:18:32 PM PDT 24
Finished Jul 29 06:18:33 PM PDT 24
Peak memory 207212 kb
Host smart-6f6281f9-33dd-4a08-9c46-9a60b96a24d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30277
4395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.302774395
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1640235574
Short name T1808
Test name
Test status
Simulation time 1076083397 ps
CPU time 2.61 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:31 PM PDT 24
Peak memory 207264 kb
Host smart-7bcfa4c1-dbec-4f88-aea2-22ef52d5774f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1640235574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1640235574
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.3762987659
Short name T672
Test name
Test status
Simulation time 1643329754 ps
CPU time 40.24 seconds
Started Jul 29 06:18:29 PM PDT 24
Finished Jul 29 06:19:10 PM PDT 24
Peak memory 207288 kb
Host smart-e4fc8416-d5d8-4f08-a43f-f526d3e54833
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762987659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.3762987659
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3141849072
Short name T1057
Test name
Test status
Simulation time 403574644 ps
CPU time 1.52 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207016 kb
Host smart-c1305b32-35fd-429b-945e-89d57b222066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31418
49072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3141849072
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3472002412
Short name T1707
Test name
Test status
Simulation time 165783359 ps
CPU time 0.84 seconds
Started Jul 29 06:18:31 PM PDT 24
Finished Jul 29 06:18:32 PM PDT 24
Peak memory 207052 kb
Host smart-5cf74c1f-631a-4051-9615-ad4e80e1f557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34720
02412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3472002412
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.4131094336
Short name T2004
Test name
Test status
Simulation time 65261271 ps
CPU time 0.73 seconds
Started Jul 29 06:18:29 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207040 kb
Host smart-3d6d6441-6cce-43b3-b0b0-36785a1ee6ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41310
94336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.4131094336
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.466313066
Short name T623
Test name
Test status
Simulation time 924918137 ps
CPU time 2.5 seconds
Started Jul 29 06:18:33 PM PDT 24
Finished Jul 29 06:18:36 PM PDT 24
Peak memory 207288 kb
Host smart-b67faf17-5df5-4722-b349-cd38ff60a87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46631
3066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.466313066
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3623065423
Short name T1093
Test name
Test status
Simulation time 300381819 ps
CPU time 2.03 seconds
Started Jul 29 06:18:30 PM PDT 24
Finished Jul 29 06:18:32 PM PDT 24
Peak memory 207372 kb
Host smart-f24451b6-9a38-4cea-9148-882554a386b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36230
65423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3623065423
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3057880599
Short name T1053
Test name
Test status
Simulation time 227845395 ps
CPU time 1.22 seconds
Started Jul 29 06:18:32 PM PDT 24
Finished Jul 29 06:18:33 PM PDT 24
Peak memory 207436 kb
Host smart-c5bad1f4-7c35-46db-8637-cf6945660075
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3057880599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3057880599
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1381484526
Short name T1406
Test name
Test status
Simulation time 143572405 ps
CPU time 0.89 seconds
Started Jul 29 06:18:33 PM PDT 24
Finished Jul 29 06:18:34 PM PDT 24
Peak memory 207044 kb
Host smart-1f0b2a71-a4f1-423b-9619-86dfaf1a6362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13814
84526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1381484526
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3216457514
Short name T2621
Test name
Test status
Simulation time 167812817 ps
CPU time 0.88 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207076 kb
Host smart-1ac01282-a1e8-4774-bf79-c5f4d00a105d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32164
57514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3216457514
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.747892377
Short name T704
Test name
Test status
Simulation time 6127352749 ps
CPU time 49.85 seconds
Started Jul 29 06:18:29 PM PDT 24
Finished Jul 29 06:19:19 PM PDT 24
Peak memory 216760 kb
Host smart-49c3650d-7388-410d-9c69-69478b4580f5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=747892377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.747892377
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.1719560430
Short name T654
Test name
Test status
Simulation time 12920680197 ps
CPU time 99.52 seconds
Started Jul 29 06:18:30 PM PDT 24
Finished Jul 29 06:20:09 PM PDT 24
Peak memory 207368 kb
Host smart-92058583-4671-48fe-8609-0cb50a08056e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1719560430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.1719560430
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.206150612
Short name T577
Test name
Test status
Simulation time 226443666 ps
CPU time 0.94 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207112 kb
Host smart-2806a88e-0136-45cf-9c10-d91c2b8affd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20615
0612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.206150612
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1788656063
Short name T2232
Test name
Test status
Simulation time 23345293136 ps
CPU time 32.52 seconds
Started Jul 29 06:18:30 PM PDT 24
Finished Jul 29 06:19:03 PM PDT 24
Peak memory 207388 kb
Host smart-adf31ec1-31f6-44d1-8987-86105431f37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17886
56063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1788656063
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.595593754
Short name T894
Test name
Test status
Simulation time 3285107768 ps
CPU time 5.06 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:33 PM PDT 24
Peak memory 207352 kb
Host smart-6c1b88e3-8aa8-4a6b-8e87-c31209ee8c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59559
3754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.595593754
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.2343545189
Short name T1244
Test name
Test status
Simulation time 6462024654 ps
CPU time 195.47 seconds
Started Jul 29 06:18:31 PM PDT 24
Finished Jul 29 06:21:47 PM PDT 24
Peak memory 215520 kb
Host smart-46e04917-e654-4d05-aab6-0d04b9d5f42b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23435
45189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2343545189
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.2772833311
Short name T728
Test name
Test status
Simulation time 4401144012 ps
CPU time 127.58 seconds
Started Jul 29 06:18:29 PM PDT 24
Finished Jul 29 06:20:37 PM PDT 24
Peak memory 215536 kb
Host smart-11010112-e642-45c0-a71e-5a10b27c6ff5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2772833311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.2772833311
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2861022969
Short name T401
Test name
Test status
Simulation time 242431552 ps
CPU time 1.02 seconds
Started Jul 29 06:18:29 PM PDT 24
Finished Jul 29 06:18:30 PM PDT 24
Peak memory 207108 kb
Host smart-55036799-9cf2-45f7-a7a0-f22fae9c9290
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2861022969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2861022969
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.931803796
Short name T651
Test name
Test status
Simulation time 194507646 ps
CPU time 1.02 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207064 kb
Host smart-dd100982-0026-4035-8eb0-d59925921cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93180
3796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.931803796
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.3843469234
Short name T432
Test name
Test status
Simulation time 6486911315 ps
CPU time 194.08 seconds
Started Jul 29 06:18:30 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 215616 kb
Host smart-45cd58d6-f66d-4a7b-8117-45f7a7a72436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38434
69234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.3843469234
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3668393528
Short name T2476
Test name
Test status
Simulation time 3438592323 ps
CPU time 105.06 seconds
Started Jul 29 06:18:29 PM PDT 24
Finished Jul 29 06:20:14 PM PDT 24
Peak memory 215536 kb
Host smart-81cefc6a-3681-4322-a1c3-1c49d29173ec
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3668393528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3668393528
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.4246230452
Short name T558
Test name
Test status
Simulation time 154273495 ps
CPU time 0.84 seconds
Started Jul 29 06:18:30 PM PDT 24
Finished Jul 29 06:18:31 PM PDT 24
Peak memory 207140 kb
Host smart-cffc08a9-0575-4ff5-9f01-b6d7f0e2d743
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4246230452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.4246230452
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1719111222
Short name T1750
Test name
Test status
Simulation time 141103565 ps
CPU time 0.85 seconds
Started Jul 29 06:18:36 PM PDT 24
Finished Jul 29 06:18:37 PM PDT 24
Peak memory 207100 kb
Host smart-3864a333-8d63-4f10-a7ed-7a11900bac4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17191
11222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1719111222
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.625195494
Short name T151
Test name
Test status
Simulation time 264165784 ps
CPU time 1.01 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207048 kb
Host smart-e2ef45dd-5bad-4825-862c-8c077886695b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62519
5494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.625195494
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.3942356937
Short name T2761
Test name
Test status
Simulation time 233845264 ps
CPU time 0.99 seconds
Started Jul 29 06:18:26 PM PDT 24
Finished Jul 29 06:18:28 PM PDT 24
Peak memory 207120 kb
Host smart-900b3464-019c-4ac7-9b41-0782085fa44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39423
56937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.3942356937
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3906264824
Short name T2169
Test name
Test status
Simulation time 181782156 ps
CPU time 0.9 seconds
Started Jul 29 06:18:30 PM PDT 24
Finished Jul 29 06:18:31 PM PDT 24
Peak memory 207072 kb
Host smart-b060fe63-0610-4adf-a1f0-51eaec44983c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39062
64824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3906264824
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.960593321
Short name T2485
Test name
Test status
Simulation time 171811584 ps
CPU time 0.84 seconds
Started Jul 29 06:18:29 PM PDT 24
Finished Jul 29 06:18:30 PM PDT 24
Peak memory 207144 kb
Host smart-b258794e-f16b-4387-ae25-f8f56298c600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96059
3321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.960593321
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2764684758
Short name T818
Test name
Test status
Simulation time 148942172 ps
CPU time 0.86 seconds
Started Jul 29 06:18:27 PM PDT 24
Finished Jul 29 06:18:28 PM PDT 24
Peak memory 207092 kb
Host smart-7acec0a5-fa4d-4d36-8e58-2e98eb950f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27646
84758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2764684758
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.551644706
Short name T689
Test name
Test status
Simulation time 227890412 ps
CPU time 1.1 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207044 kb
Host smart-c2b3672f-95e8-4f5e-9812-0da3ec7428f4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=551644706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.551644706
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.536101114
Short name T1956
Test name
Test status
Simulation time 153137224 ps
CPU time 0.83 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207092 kb
Host smart-1e9a7917-6c28-4772-b0bb-70a9b4bafec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53610
1114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.536101114
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.333265739
Short name T1897
Test name
Test status
Simulation time 42229750 ps
CPU time 0.69 seconds
Started Jul 29 06:18:28 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 207032 kb
Host smart-d3331fea-1b9b-42fe-b7b9-df1368884062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33326
5739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.333265739
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.50238735
Short name T614
Test name
Test status
Simulation time 19522250567 ps
CPU time 54.92 seconds
Started Jul 29 06:18:42 PM PDT 24
Finished Jul 29 06:19:37 PM PDT 24
Peak memory 215628 kb
Host smart-3582ff5c-3021-4c5b-bb9a-0e90657e50a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50238
735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.50238735
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2932783291
Short name T2203
Test name
Test status
Simulation time 191318346 ps
CPU time 0.91 seconds
Started Jul 29 06:18:35 PM PDT 24
Finished Jul 29 06:18:36 PM PDT 24
Peak memory 207076 kb
Host smart-50f5f279-ff81-4d32-8a49-9be64fbd3d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29327
83291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2932783291
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.1996169184
Short name T1151
Test name
Test status
Simulation time 223103569 ps
CPU time 1.02 seconds
Started Jul 29 06:18:40 PM PDT 24
Finished Jul 29 06:18:41 PM PDT 24
Peak memory 207080 kb
Host smart-4267ecb9-261a-4a79-b90a-6fb4ae451759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19961
69184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.1996169184
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.81659341
Short name T1322
Test name
Test status
Simulation time 170544863 ps
CPU time 0.9 seconds
Started Jul 29 06:18:35 PM PDT 24
Finished Jul 29 06:18:36 PM PDT 24
Peak memory 207076 kb
Host smart-fdcca1ff-411e-43fe-92c8-28a7055758cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81659
341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.81659341
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.91223332
Short name T1947
Test name
Test status
Simulation time 160060991 ps
CPU time 0.85 seconds
Started Jul 29 06:18:37 PM PDT 24
Finished Jul 29 06:18:37 PM PDT 24
Peak memory 207072 kb
Host smart-483c67d6-1a9d-4e5b-bef0-4ec4c04fe223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91223
332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.91223332
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3522439626
Short name T660
Test name
Test status
Simulation time 211504591 ps
CPU time 0.93 seconds
Started Jul 29 06:18:36 PM PDT 24
Finished Jul 29 06:18:37 PM PDT 24
Peak memory 207088 kb
Host smart-71607cc0-af39-4f06-b0b1-1a72328c2fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35224
39626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3522439626
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2960208789
Short name T1235
Test name
Test status
Simulation time 154482421 ps
CPU time 0.96 seconds
Started Jul 29 06:18:35 PM PDT 24
Finished Jul 29 06:18:36 PM PDT 24
Peak memory 207072 kb
Host smart-60ac406f-519c-4019-8978-b99b81099591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29602
08789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2960208789
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.310170275
Short name T814
Test name
Test status
Simulation time 147124057 ps
CPU time 0.89 seconds
Started Jul 29 06:18:36 PM PDT 24
Finished Jul 29 06:18:37 PM PDT 24
Peak memory 207108 kb
Host smart-21a0cb37-af69-4b87-8989-8529a70b060c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31017
0275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.310170275
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.683285102
Short name T1482
Test name
Test status
Simulation time 186591872 ps
CPU time 0.96 seconds
Started Jul 29 06:18:38 PM PDT 24
Finished Jul 29 06:18:39 PM PDT 24
Peak memory 207108 kb
Host smart-c7a0dcd1-ece5-419c-b3c2-ea60e82ec7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68328
5102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.683285102
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.3311351514
Short name T2331
Test name
Test status
Simulation time 3969032407 ps
CPU time 32.83 seconds
Started Jul 29 06:18:47 PM PDT 24
Finished Jul 29 06:19:20 PM PDT 24
Peak memory 215492 kb
Host smart-d96bd737-730e-4682-9c2f-cbd70cba06aa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3311351514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.3311351514
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.911146211
Short name T2247
Test name
Test status
Simulation time 172541010 ps
CPU time 0.89 seconds
Started Jul 29 06:18:38 PM PDT 24
Finished Jul 29 06:18:39 PM PDT 24
Peak memory 207000 kb
Host smart-39a28d43-68c8-472b-901e-c3f2efe034b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91114
6211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.911146211
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.4177528723
Short name T1651
Test name
Test status
Simulation time 184700927 ps
CPU time 0.98 seconds
Started Jul 29 06:18:46 PM PDT 24
Finished Jul 29 06:18:47 PM PDT 24
Peak memory 207112 kb
Host smart-b7d7a34d-d884-4cef-9b95-030ee27bcdcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41775
28723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.4177528723
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.3390640069
Short name T431
Test name
Test status
Simulation time 1154440962 ps
CPU time 2.77 seconds
Started Jul 29 06:18:37 PM PDT 24
Finished Jul 29 06:18:40 PM PDT 24
Peak memory 207312 kb
Host smart-d3330449-e48c-4024-b05b-ff9bef70dd2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33906
40069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.3390640069
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3124130103
Short name T516
Test name
Test status
Simulation time 5159492407 ps
CPU time 159.01 seconds
Started Jul 29 06:18:37 PM PDT 24
Finished Jul 29 06:21:16 PM PDT 24
Peak memory 215636 kb
Host smart-a95178a0-986b-4975-a22c-291a3c3a3c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31241
30103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3124130103
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.2804272953
Short name T2306
Test name
Test status
Simulation time 2025454716 ps
CPU time 18.59 seconds
Started Jul 29 06:18:27 PM PDT 24
Finished Jul 29 06:18:46 PM PDT 24
Peak memory 207280 kb
Host smart-47d5c6f9-832e-4d43-91d7-9c120087e9ec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804272953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.2804272953
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.250837872
Short name T1078
Test name
Test status
Simulation time 89856246 ps
CPU time 0.71 seconds
Started Jul 29 06:18:47 PM PDT 24
Finished Jul 29 06:18:48 PM PDT 24
Peak memory 207048 kb
Host smart-d1c04d26-5a49-4133-b700-a169ba992c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=250837872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.250837872
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2962151987
Short name T1325
Test name
Test status
Simulation time 3621058213 ps
CPU time 5.99 seconds
Started Jul 29 06:18:39 PM PDT 24
Finished Jul 29 06:18:45 PM PDT 24
Peak memory 207376 kb
Host smart-d9098f89-6cf6-4092-814a-9fe6d955796e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962151987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.2962151987
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.4077070605
Short name T2590
Test name
Test status
Simulation time 13493632375 ps
CPU time 16.64 seconds
Started Jul 29 06:18:35 PM PDT 24
Finished Jul 29 06:18:52 PM PDT 24
Peak memory 207400 kb
Host smart-8a782d72-08c4-49da-9ee7-1069851992f4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077070605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.4077070605
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.229041720
Short name T2802
Test name
Test status
Simulation time 23442085223 ps
CPU time 27.74 seconds
Started Jul 29 06:18:38 PM PDT 24
Finished Jul 29 06:19:06 PM PDT 24
Peak memory 207340 kb
Host smart-70628eab-4ab0-4e1e-b805-690ffe7d7d44
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229041720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_ao
n_wake_resume.229041720
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.441359225
Short name T747
Test name
Test status
Simulation time 156763215 ps
CPU time 0.89 seconds
Started Jul 29 06:18:36 PM PDT 24
Finished Jul 29 06:18:37 PM PDT 24
Peak memory 207044 kb
Host smart-258cb20d-b8cf-4396-a5c8-08c2fe1e36fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44135
9225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.441359225
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1281805545
Short name T781
Test name
Test status
Simulation time 150765396 ps
CPU time 0.9 seconds
Started Jul 29 06:18:38 PM PDT 24
Finished Jul 29 06:18:39 PM PDT 24
Peak memory 207016 kb
Host smart-ffb5ba98-a974-4cf4-ba1d-6f67ccb6f659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12818
05545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1281805545
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.1939601896
Short name T2057
Test name
Test status
Simulation time 459737706 ps
CPU time 1.64 seconds
Started Jul 29 06:18:43 PM PDT 24
Finished Jul 29 06:18:45 PM PDT 24
Peak memory 207120 kb
Host smart-b728d006-bac1-464c-b7f3-d6b7d43402f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19396
01896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.1939601896
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2448934157
Short name T1024
Test name
Test status
Simulation time 1004229934 ps
CPU time 2.38 seconds
Started Jul 29 06:18:45 PM PDT 24
Finished Jul 29 06:18:48 PM PDT 24
Peak memory 207348 kb
Host smart-e5c78db7-0233-485b-bcdf-67663db7627b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2448934157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2448934157
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1809602391
Short name T1344
Test name
Test status
Simulation time 12055727750 ps
CPU time 29.03 seconds
Started Jul 29 06:18:39 PM PDT 24
Finished Jul 29 06:19:08 PM PDT 24
Peak memory 207380 kb
Host smart-77dbf025-0da7-4cf3-93ea-73cc9219b97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18096
02391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1809602391
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.1216503290
Short name T2523
Test name
Test status
Simulation time 429228052 ps
CPU time 8.33 seconds
Started Jul 29 06:18:50 PM PDT 24
Finished Jul 29 06:18:59 PM PDT 24
Peak memory 207368 kb
Host smart-488238e5-7b3b-4992-a39f-df49baeb194f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216503290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.1216503290
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2366513823
Short name T1546
Test name
Test status
Simulation time 520916715 ps
CPU time 1.53 seconds
Started Jul 29 06:18:39 PM PDT 24
Finished Jul 29 06:18:40 PM PDT 24
Peak memory 207064 kb
Host smart-e28f6b4c-89d1-4142-8a20-ef8bd3be9e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23665
13823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2366513823
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.72509819
Short name T1542
Test name
Test status
Simulation time 144786114 ps
CPU time 0.82 seconds
Started Jul 29 06:18:47 PM PDT 24
Finished Jul 29 06:18:48 PM PDT 24
Peak memory 207076 kb
Host smart-b549f469-f007-42ed-a83e-6d662007a9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72509
819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.72509819
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.187319762
Short name T499
Test name
Test status
Simulation time 90802263 ps
CPU time 0.78 seconds
Started Jul 29 06:18:41 PM PDT 24
Finished Jul 29 06:18:42 PM PDT 24
Peak memory 207016 kb
Host smart-3fb2a24d-12bf-4f74-8b8a-76bd9ef6bc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18731
9762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.187319762
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2551093629
Short name T2018
Test name
Test status
Simulation time 725468484 ps
CPU time 2.09 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:18:50 PM PDT 24
Peak memory 207412 kb
Host smart-8332a88b-b2a1-4bf8-b5b1-4e629ec2b30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25510
93629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2551093629
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2311217616
Short name T528
Test name
Test status
Simulation time 208544418 ps
CPU time 1.82 seconds
Started Jul 29 06:18:45 PM PDT 24
Finished Jul 29 06:18:47 PM PDT 24
Peak memory 207192 kb
Host smart-66ae67a1-32e8-4734-b170-ca3d88ccf717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23112
17616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2311217616
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.662155700
Short name T2849
Test name
Test status
Simulation time 179915397 ps
CPU time 1.02 seconds
Started Jul 29 06:18:39 PM PDT 24
Finished Jul 29 06:18:40 PM PDT 24
Peak memory 207276 kb
Host smart-544968c8-be75-4c4f-8904-858649c92c4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=662155700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.662155700
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3302599205
Short name T788
Test name
Test status
Simulation time 173117550 ps
CPU time 0.83 seconds
Started Jul 29 06:18:49 PM PDT 24
Finished Jul 29 06:18:50 PM PDT 24
Peak memory 207052 kb
Host smart-1e1de127-5f31-479e-bd35-7ddb3607fd5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33025
99205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3302599205
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.912937278
Short name T2077
Test name
Test status
Simulation time 159404289 ps
CPU time 0.88 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:18:49 PM PDT 24
Peak memory 207040 kb
Host smart-c02d9903-d40d-404c-adc0-744b7c97b68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91293
7278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.912937278
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.3414762919
Short name T1545
Test name
Test status
Simulation time 4764015598 ps
CPU time 29.15 seconds
Started Jul 29 06:18:47 PM PDT 24
Finished Jul 29 06:19:16 PM PDT 24
Peak memory 207412 kb
Host smart-6b0b093b-384b-42b4-9f59-1cdfa80122fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3414762919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.3414762919
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2663163631
Short name T1831
Test name
Test status
Simulation time 242365486 ps
CPU time 1.02 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:18:49 PM PDT 24
Peak memory 207108 kb
Host smart-ff6c8c94-890a-4c7f-924e-5c150dd09e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26631
63631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2663163631
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.1211628961
Short name T1797
Test name
Test status
Simulation time 23311106796 ps
CPU time 26.18 seconds
Started Jul 29 06:18:49 PM PDT 24
Finished Jul 29 06:19:15 PM PDT 24
Peak memory 207400 kb
Host smart-c1884e0e-44fc-47d3-8e44-1baf30cc1f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12116
28961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.1211628961
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2836682153
Short name T326
Test name
Test status
Simulation time 3303121679 ps
CPU time 4.88 seconds
Started Jul 29 06:18:44 PM PDT 24
Finished Jul 29 06:18:49 PM PDT 24
Peak memory 207332 kb
Host smart-56824420-bbba-4d30-966e-a051e3b4af06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28366
82153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2836682153
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.1444272107
Short name T292
Test name
Test status
Simulation time 7366211335 ps
CPU time 221.32 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:22:30 PM PDT 24
Peak memory 215464 kb
Host smart-296de61a-5c19-418b-a998-10c3a63bece8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14442
72107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.1444272107
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1145509529
Short name T1071
Test name
Test status
Simulation time 4928628367 ps
CPU time 53.12 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:19:41 PM PDT 24
Peak memory 207436 kb
Host smart-07d81bfc-0de5-4aec-8fa1-ad794cb69115
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1145509529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1145509529
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.1342838638
Short name T2674
Test name
Test status
Simulation time 247212033 ps
CPU time 1 seconds
Started Jul 29 06:18:42 PM PDT 24
Finished Jul 29 06:18:43 PM PDT 24
Peak memory 206988 kb
Host smart-65c27c57-ba08-4168-97b4-1fd45e2276b7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1342838638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.1342838638
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1677794116
Short name T1360
Test name
Test status
Simulation time 193103502 ps
CPU time 1.03 seconds
Started Jul 29 06:18:47 PM PDT 24
Finished Jul 29 06:18:48 PM PDT 24
Peak memory 207136 kb
Host smart-27b24c8e-e348-49e3-90f3-52bc6bcf1e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16777
94116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1677794116
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1379483886
Short name T2527
Test name
Test status
Simulation time 6284234926 ps
CPU time 49.07 seconds
Started Jul 29 06:18:40 PM PDT 24
Finished Jul 29 06:19:29 PM PDT 24
Peak memory 215544 kb
Host smart-71d6d52e-4c51-4238-82c5-f0b9ab5600c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13794
83886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1379483886
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.543099284
Short name T575
Test name
Test status
Simulation time 4338723745 ps
CPU time 32.72 seconds
Started Jul 29 06:18:51 PM PDT 24
Finished Jul 29 06:19:24 PM PDT 24
Peak memory 207416 kb
Host smart-28006cd4-fedb-47d3-994b-8161716ce147
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=543099284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.543099284
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2622164581
Short name T3
Test name
Test status
Simulation time 157038040 ps
CPU time 0.84 seconds
Started Jul 29 06:18:45 PM PDT 24
Finished Jul 29 06:18:46 PM PDT 24
Peak memory 207108 kb
Host smart-d0549481-f18d-433d-8f82-820a8abafec3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2622164581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2622164581
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.4032141628
Short name T650
Test name
Test status
Simulation time 147819692 ps
CPU time 0.84 seconds
Started Jul 29 06:18:49 PM PDT 24
Finished Jul 29 06:18:50 PM PDT 24
Peak memory 207052 kb
Host smart-6004bfad-fd1a-4761-b808-13de4a957590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40321
41628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.4032141628
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2546748478
Short name T2244
Test name
Test status
Simulation time 238092486 ps
CPU time 0.96 seconds
Started Jul 29 06:18:50 PM PDT 24
Finished Jul 29 06:18:51 PM PDT 24
Peak memory 207136 kb
Host smart-ea055abb-50da-4930-a147-81909561643c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25467
48478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2546748478
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.673907688
Short name T353
Test name
Test status
Simulation time 151842912 ps
CPU time 0.9 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:18:49 PM PDT 24
Peak memory 207076 kb
Host smart-878634dc-b14d-4a01-a27a-d36633a011ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67390
7688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.673907688
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.4224713331
Short name T321
Test name
Test status
Simulation time 178087186 ps
CPU time 0.9 seconds
Started Jul 29 06:18:41 PM PDT 24
Finished Jul 29 06:18:42 PM PDT 24
Peak memory 207020 kb
Host smart-54073b0e-dfa3-4323-a616-c31952906c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42247
13331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.4224713331
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.668620123
Short name T1174
Test name
Test status
Simulation time 194275771 ps
CPU time 0.91 seconds
Started Jul 29 06:18:51 PM PDT 24
Finished Jul 29 06:18:52 PM PDT 24
Peak memory 207108 kb
Host smart-592303c8-52ea-411f-bc21-ae310e982947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66862
0123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.668620123
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.797255620
Short name T737
Test name
Test status
Simulation time 158526189 ps
CPU time 0.87 seconds
Started Jul 29 06:18:39 PM PDT 24
Finished Jul 29 06:18:40 PM PDT 24
Peak memory 207116 kb
Host smart-068943bf-2c52-4aff-94f5-2483598de7b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79725
5620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.797255620
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1217792616
Short name T969
Test name
Test status
Simulation time 248867301 ps
CPU time 1.07 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:18:50 PM PDT 24
Peak memory 207132 kb
Host smart-dae088db-43d1-463e-81d0-af04b97b74e4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1217792616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1217792616
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3388709977
Short name T928
Test name
Test status
Simulation time 146850146 ps
CPU time 0.85 seconds
Started Jul 29 06:18:53 PM PDT 24
Finished Jul 29 06:18:54 PM PDT 24
Peak memory 207084 kb
Host smart-acd4cb4d-291d-49cf-bd70-da287fa2886c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33887
09977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3388709977
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.357519396
Short name T1691
Test name
Test status
Simulation time 129797795 ps
CPU time 0.77 seconds
Started Jul 29 06:18:46 PM PDT 24
Finished Jul 29 06:18:47 PM PDT 24
Peak memory 207108 kb
Host smart-75a0f90e-ce9b-4fae-86e3-ebf68f65a1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35751
9396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.357519396
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2504685199
Short name T261
Test name
Test status
Simulation time 9774510653 ps
CPU time 26.57 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:19:24 PM PDT 24
Peak memory 215600 kb
Host smart-2af231e5-45d5-4c07-a9b0-cdab977f475c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25046
85199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2504685199
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2671878228
Short name T284
Test name
Test status
Simulation time 205736640 ps
CPU time 0.9 seconds
Started Jul 29 06:18:53 PM PDT 24
Finished Jul 29 06:18:55 PM PDT 24
Peak memory 207100 kb
Host smart-1a18d979-89b0-4d70-bc85-b1fecc53491d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26718
78228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2671878228
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3700225010
Short name T2139
Test name
Test status
Simulation time 171757053 ps
CPU time 0.91 seconds
Started Jul 29 06:18:47 PM PDT 24
Finished Jul 29 06:18:48 PM PDT 24
Peak memory 207076 kb
Host smart-4688aaac-3d8a-4613-9b91-9337c6e9a241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37002
25010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3700225010
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2194239679
Short name T2499
Test name
Test status
Simulation time 250275674 ps
CPU time 0.98 seconds
Started Jul 29 06:18:50 PM PDT 24
Finished Jul 29 06:18:52 PM PDT 24
Peak memory 207108 kb
Host smart-e81ee490-3d2b-42b7-b5c9-5802c53cbe9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21942
39679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2194239679
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.2064952004
Short name T576
Test name
Test status
Simulation time 151966106 ps
CPU time 0.84 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:18:49 PM PDT 24
Peak memory 207112 kb
Host smart-e088be98-f106-476e-bf65-179317446bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20649
52004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.2064952004
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.1858087963
Short name T2844
Test name
Test status
Simulation time 144549381 ps
CPU time 0.84 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:18:59 PM PDT 24
Peak memory 206736 kb
Host smart-b7f52d3b-a9b2-4335-8f25-280e4f437a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18580
87963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.1858087963
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.820020217
Short name T1834
Test name
Test status
Simulation time 164405942 ps
CPU time 0.86 seconds
Started Jul 29 06:18:53 PM PDT 24
Finished Jul 29 06:18:54 PM PDT 24
Peak memory 207044 kb
Host smart-4b4d2f7f-f169-4e38-abb0-045c8114d56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82002
0217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.820020217
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3539364273
Short name T472
Test name
Test status
Simulation time 167653925 ps
CPU time 0.85 seconds
Started Jul 29 06:18:55 PM PDT 24
Finished Jul 29 06:18:56 PM PDT 24
Peak memory 206960 kb
Host smart-6d6d6515-5fb4-4b6e-b757-3e7774b6f0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35393
64273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3539364273
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2087344652
Short name T1102
Test name
Test status
Simulation time 249452376 ps
CPU time 1.14 seconds
Started Jul 29 06:18:53 PM PDT 24
Finished Jul 29 06:18:54 PM PDT 24
Peak memory 207108 kb
Host smart-18d67109-b441-48e9-b3e1-f6b37bb99f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20873
44652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2087344652
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.1649421543
Short name T1735
Test name
Test status
Simulation time 3333294421 ps
CPU time 94.67 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:20:32 PM PDT 24
Peak memory 215496 kb
Host smart-83652575-f7d7-43d3-b1be-0e2c334e95fc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1649421543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.1649421543
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1436147775
Short name T1408
Test name
Test status
Simulation time 229851233 ps
CPU time 0.95 seconds
Started Jul 29 06:18:51 PM PDT 24
Finished Jul 29 06:18:52 PM PDT 24
Peak memory 207108 kb
Host smart-1dc79954-a026-444f-9349-deedd8f497e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14361
47775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1436147775
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1339601390
Short name T966
Test name
Test status
Simulation time 167181387 ps
CPU time 0.94 seconds
Started Jul 29 06:18:50 PM PDT 24
Finished Jul 29 06:18:51 PM PDT 24
Peak memory 207068 kb
Host smart-0af09bc3-b695-4cec-8b28-34b8f9daa754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13396
01390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1339601390
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.4286586046
Short name T2839
Test name
Test status
Simulation time 751357024 ps
CPU time 1.96 seconds
Started Jul 29 06:18:54 PM PDT 24
Finished Jul 29 06:18:57 PM PDT 24
Peak memory 207052 kb
Host smart-f2656dcf-514f-40a8-83e2-da16bca3e6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42865
86046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.4286586046
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.1842762234
Short name T2322
Test name
Test status
Simulation time 5623800738 ps
CPU time 57.6 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:19:46 PM PDT 24
Peak memory 217124 kb
Host smart-c93fc2c6-4ce6-4d1c-a91a-7a6826105f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18427
62234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1842762234
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.2758161260
Short name T2356
Test name
Test status
Simulation time 2532511980 ps
CPU time 20.5 seconds
Started Jul 29 06:18:47 PM PDT 24
Finished Jul 29 06:19:08 PM PDT 24
Peak memory 207340 kb
Host smart-96d79955-1822-44a3-a474-9582fd273b5f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758161260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_hos
t_handshake.2758161260
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.591584494
Short name T967
Test name
Test status
Simulation time 56340459 ps
CPU time 0.66 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:05 PM PDT 24
Peak memory 207136 kb
Host smart-f7c77b73-4b9f-423d-905d-af17224e23b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=591584494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.591584494
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1894513055
Short name T931
Test name
Test status
Simulation time 3900572220 ps
CPU time 5.56 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:19:03 PM PDT 24
Peak memory 207352 kb
Host smart-e15bc8f5-7333-439a-b7c1-c6d88d8f7a15
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894513055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.1894513055
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.368619390
Short name T2821
Test name
Test status
Simulation time 13350843148 ps
CPU time 15.32 seconds
Started Jul 29 06:18:45 PM PDT 24
Finished Jul 29 06:19:01 PM PDT 24
Peak memory 207448 kb
Host smart-52a01d4c-7747-4be3-b954-f3d14c5d7505
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=368619390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.368619390
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1965989427
Short name T1382
Test name
Test status
Simulation time 23385186814 ps
CPU time 25.88 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:19:14 PM PDT 24
Peak memory 207420 kb
Host smart-1d50ed73-fed0-4964-a1dd-d36550179fa5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965989427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.1965989427
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.420280674
Short name T745
Test name
Test status
Simulation time 194485668 ps
CPU time 1.04 seconds
Started Jul 29 06:18:47 PM PDT 24
Finished Jul 29 06:18:48 PM PDT 24
Peak memory 207264 kb
Host smart-86a3f345-bbcd-478c-af8b-c4292e4f23d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42028
0674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.420280674
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.236193400
Short name T1684
Test name
Test status
Simulation time 198626460 ps
CPU time 0.95 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:18:50 PM PDT 24
Peak memory 206948 kb
Host smart-e1b80ae9-a066-4703-863d-d96589373b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23619
3400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.236193400
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2925548200
Short name T1437
Test name
Test status
Simulation time 373823432 ps
CPU time 1.33 seconds
Started Jul 29 06:18:47 PM PDT 24
Finished Jul 29 06:18:49 PM PDT 24
Peak memory 207060 kb
Host smart-aead8f67-9e3b-4cf4-8374-c82f9b20fcdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29255
48200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2925548200
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1086975565
Short name T635
Test name
Test status
Simulation time 520419181 ps
CPU time 1.72 seconds
Started Jul 29 06:18:53 PM PDT 24
Finished Jul 29 06:18:55 PM PDT 24
Peak memory 207136 kb
Host smart-6e5fe1ea-bcc1-4592-bdf4-4ad1f358c25a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1086975565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1086975565
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.12245085
Short name T1817
Test name
Test status
Simulation time 11259642485 ps
CPU time 23.61 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:19:12 PM PDT 24
Peak memory 207436 kb
Host smart-52a89a29-a08a-4273-ad5e-7c2bc091e2c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12245
085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.12245085
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.3235637612
Short name T1754
Test name
Test status
Simulation time 6349693702 ps
CPU time 40.76 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:19:38 PM PDT 24
Peak memory 207072 kb
Host smart-e371afbb-0b5e-402d-89e2-93113b1abf88
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235637612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.3235637612
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.263237133
Short name T1540
Test name
Test status
Simulation time 295350348 ps
CPU time 1.14 seconds
Started Jul 29 06:18:53 PM PDT 24
Finished Jul 29 06:18:54 PM PDT 24
Peak memory 207084 kb
Host smart-8376f2b2-c44d-4705-8a8c-31678bf79ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26323
7133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.263237133
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.853018212
Short name T1839
Test name
Test status
Simulation time 156364000 ps
CPU time 0.84 seconds
Started Jul 29 06:18:47 PM PDT 24
Finished Jul 29 06:18:48 PM PDT 24
Peak memory 207088 kb
Host smart-81a608cf-bab4-47a3-b2e1-894b21e0ee35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85301
8212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.853018212
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2381327652
Short name T1231
Test name
Test status
Simulation time 38964248 ps
CPU time 0.72 seconds
Started Jul 29 06:18:52 PM PDT 24
Finished Jul 29 06:18:53 PM PDT 24
Peak memory 207056 kb
Host smart-e2323a01-0609-4ef0-999f-79848d470e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23813
27652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2381327652
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1880936535
Short name T1080
Test name
Test status
Simulation time 871506209 ps
CPU time 2.2 seconds
Started Jul 29 06:18:48 PM PDT 24
Finished Jul 29 06:18:50 PM PDT 24
Peak memory 207268 kb
Host smart-167a77f3-2b19-4627-a81e-82c8536922f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18809
36535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1880936535
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.549186813
Short name T2594
Test name
Test status
Simulation time 263206171 ps
CPU time 2 seconds
Started Jul 29 06:18:47 PM PDT 24
Finished Jul 29 06:18:49 PM PDT 24
Peak memory 207428 kb
Host smart-dc1e772b-0e96-41dc-8423-16d413c4faca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54918
6813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.549186813
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.866463592
Short name T2700
Test name
Test status
Simulation time 148871870 ps
CPU time 0.85 seconds
Started Jul 29 06:18:46 PM PDT 24
Finished Jul 29 06:18:47 PM PDT 24
Peak memory 207124 kb
Host smart-4be792fc-ec9a-4f3b-8193-c04b774175cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=866463592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.866463592
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3898030697
Short name T1321
Test name
Test status
Simulation time 147534296 ps
CPU time 0.84 seconds
Started Jul 29 06:18:54 PM PDT 24
Finished Jul 29 06:18:55 PM PDT 24
Peak memory 207068 kb
Host smart-45fa6476-a7d9-40ca-9431-d7d88f3befb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38980
30697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3898030697
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3772548309
Short name T568
Test name
Test status
Simulation time 197083898 ps
CPU time 0.98 seconds
Started Jul 29 06:18:52 PM PDT 24
Finished Jul 29 06:18:53 PM PDT 24
Peak memory 207112 kb
Host smart-f0fd2cfc-90ac-4ce4-9be7-89bdcc3b12b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37725
48309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3772548309
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.2911474328
Short name T1599
Test name
Test status
Simulation time 4559655318 ps
CPU time 138.12 seconds
Started Jul 29 06:18:47 PM PDT 24
Finished Jul 29 06:21:06 PM PDT 24
Peak memory 215584 kb
Host smart-a83c14f0-7709-4733-90b7-0993fc7bed3f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2911474328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2911474328
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.825470357
Short name T2216
Test name
Test status
Simulation time 6544654596 ps
CPU time 41.76 seconds
Started Jul 29 06:18:56 PM PDT 24
Finished Jul 29 06:19:38 PM PDT 24
Peak memory 207364 kb
Host smart-2fd42478-b197-48b0-a68d-e9da8dccf8ff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=825470357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.825470357
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1485311366
Short name T1043
Test name
Test status
Simulation time 236083881 ps
CPU time 1 seconds
Started Jul 29 06:18:55 PM PDT 24
Finished Jul 29 06:18:56 PM PDT 24
Peak memory 207100 kb
Host smart-870e29da-c93e-4be3-93f2-f788eb8e6b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14853
11366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1485311366
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2516152363
Short name T726
Test name
Test status
Simulation time 23368095156 ps
CPU time 25.71 seconds
Started Jul 29 06:18:59 PM PDT 24
Finished Jul 29 06:19:25 PM PDT 24
Peak memory 207420 kb
Host smart-d7ac8ecc-54d9-48e8-a8cb-9e08a8ff5245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25161
52363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2516152363
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.4050321483
Short name T2436
Test name
Test status
Simulation time 3398158766 ps
CPU time 5.05 seconds
Started Jul 29 06:18:55 PM PDT 24
Finished Jul 29 06:19:00 PM PDT 24
Peak memory 207368 kb
Host smart-54647101-e14f-4eea-bdf5-46a41be77192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40503
21483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.4050321483
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.3829089820
Short name T1896
Test name
Test status
Simulation time 6403323719 ps
CPU time 192.47 seconds
Started Jul 29 06:18:55 PM PDT 24
Finished Jul 29 06:22:08 PM PDT 24
Peak memory 215744 kb
Host smart-1dc3efcb-b201-46ec-98b3-a861a9d8e408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38290
89820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.3829089820
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3768082468
Short name T1726
Test name
Test status
Simulation time 8006209258 ps
CPU time 243.46 seconds
Started Jul 29 06:18:58 PM PDT 24
Finished Jul 29 06:23:01 PM PDT 24
Peak memory 215524 kb
Host smart-4134ff34-c181-4c02-84f3-1983d8a8ef04
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3768082468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3768082468
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.1663434418
Short name T1036
Test name
Test status
Simulation time 265983544 ps
CPU time 0.98 seconds
Started Jul 29 06:18:50 PM PDT 24
Finished Jul 29 06:18:51 PM PDT 24
Peak memory 207128 kb
Host smart-b3c71e76-4821-49d4-9c0c-8ad600546fd6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1663434418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.1663434418
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.4092391138
Short name T1136
Test name
Test status
Simulation time 205379075 ps
CPU time 0.96 seconds
Started Jul 29 06:18:49 PM PDT 24
Finished Jul 29 06:18:50 PM PDT 24
Peak memory 207096 kb
Host smart-a6837459-acdb-4059-847a-31f2ddaeb27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40923
91138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.4092391138
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.1106521846
Short name T1972
Test name
Test status
Simulation time 3758938569 ps
CPU time 28.15 seconds
Started Jul 29 06:18:59 PM PDT 24
Finished Jul 29 06:19:28 PM PDT 24
Peak memory 215608 kb
Host smart-4c4f83f3-f359-4334-86ea-c4fbda81ffb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11065
21846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.1106521846
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.2493851993
Short name T1281
Test name
Test status
Simulation time 6901453549 ps
CPU time 196.6 seconds
Started Jul 29 06:18:58 PM PDT 24
Finished Jul 29 06:22:14 PM PDT 24
Peak memory 215556 kb
Host smart-9555e839-22b5-4e66-bbdc-d61e87b91452
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2493851993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.2493851993
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.356105682
Short name T341
Test name
Test status
Simulation time 153653115 ps
CPU time 0.83 seconds
Started Jul 29 06:18:52 PM PDT 24
Finished Jul 29 06:18:53 PM PDT 24
Peak memory 207076 kb
Host smart-62d088e9-e0cf-47d9-b24c-5c5203d99f34
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=356105682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.356105682
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3087272828
Short name T974
Test name
Test status
Simulation time 152142727 ps
CPU time 0.86 seconds
Started Jul 29 06:18:53 PM PDT 24
Finished Jul 29 06:18:54 PM PDT 24
Peak memory 207148 kb
Host smart-91f15669-d02e-4d31-ba0e-532c496bb2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30872
72828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3087272828
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3683349489
Short name T679
Test name
Test status
Simulation time 176690238 ps
CPU time 0.92 seconds
Started Jul 29 06:18:55 PM PDT 24
Finished Jul 29 06:18:56 PM PDT 24
Peak memory 207064 kb
Host smart-864e6182-769c-461f-86b7-141052d2e592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36833
49489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3683349489
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2839263087
Short name T1065
Test name
Test status
Simulation time 183764503 ps
CPU time 0.96 seconds
Started Jul 29 06:18:54 PM PDT 24
Finished Jul 29 06:18:55 PM PDT 24
Peak memory 207084 kb
Host smart-59620092-7400-40d5-9c5d-73ca9776e0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28392
63087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2839263087
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1382058530
Short name T1678
Test name
Test status
Simulation time 171110189 ps
CPU time 0.86 seconds
Started Jul 29 06:18:53 PM PDT 24
Finished Jul 29 06:18:54 PM PDT 24
Peak memory 207108 kb
Host smart-4ad32263-6337-416f-8816-e11c496fe552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13820
58530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1382058530
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.496766479
Short name T1866
Test name
Test status
Simulation time 161663344 ps
CPU time 0.85 seconds
Started Jul 29 06:18:55 PM PDT 24
Finished Jul 29 06:18:56 PM PDT 24
Peak memory 207048 kb
Host smart-0b0de6fe-6cfa-466e-8851-9ecadf1dd4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49676
6479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.496766479
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.1018766881
Short name T1592
Test name
Test status
Simulation time 169686831 ps
CPU time 0.96 seconds
Started Jul 29 06:18:55 PM PDT 24
Finished Jul 29 06:18:56 PM PDT 24
Peak memory 207100 kb
Host smart-9d46b6dc-bed9-480e-a23d-702bb50af426
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1018766881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.1018766881
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1864318582
Short name T2321
Test name
Test status
Simulation time 161587217 ps
CPU time 0.84 seconds
Started Jul 29 06:18:53 PM PDT 24
Finished Jul 29 06:18:54 PM PDT 24
Peak memory 207060 kb
Host smart-7cd02176-994c-4df8-85c7-6060873a4889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18643
18582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1864318582
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3143342159
Short name T2006
Test name
Test status
Simulation time 48202418 ps
CPU time 0.68 seconds
Started Jul 29 06:18:56 PM PDT 24
Finished Jul 29 06:18:57 PM PDT 24
Peak memory 207068 kb
Host smart-6c9fd38c-3738-4f45-a1cf-50f014112ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31433
42159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3143342159
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3470966400
Short name T2672
Test name
Test status
Simulation time 18360465962 ps
CPU time 49.23 seconds
Started Jul 29 06:18:55 PM PDT 24
Finished Jul 29 06:19:45 PM PDT 24
Peak memory 215580 kb
Host smart-b6e8a2da-0203-492c-8f1c-1afc65b13076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34709
66400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3470966400
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2666528887
Short name T467
Test name
Test status
Simulation time 239718598 ps
CPU time 0.96 seconds
Started Jul 29 06:18:59 PM PDT 24
Finished Jul 29 06:19:00 PM PDT 24
Peak memory 207100 kb
Host smart-c927b6d9-7d73-4cfd-8fe4-19e760275334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26665
28887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2666528887
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3555231024
Short name T1577
Test name
Test status
Simulation time 160886706 ps
CPU time 0.92 seconds
Started Jul 29 06:18:53 PM PDT 24
Finished Jul 29 06:18:55 PM PDT 24
Peak memory 207084 kb
Host smart-64656a41-53f8-4d47-94dd-05468767cd4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35552
31024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3555231024
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3183290720
Short name T590
Test name
Test status
Simulation time 301509479 ps
CPU time 1.05 seconds
Started Jul 29 06:18:53 PM PDT 24
Finished Jul 29 06:18:54 PM PDT 24
Peak memory 207020 kb
Host smart-2f38347b-468f-4687-8039-eabb487bd495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31832
90720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3183290720
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.3173861763
Short name T2272
Test name
Test status
Simulation time 187636105 ps
CPU time 0.95 seconds
Started Jul 29 06:18:55 PM PDT 24
Finished Jul 29 06:18:56 PM PDT 24
Peak memory 206932 kb
Host smart-c7f73464-301b-4c83-bdbb-7ee9322da89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31738
61763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.3173861763
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.1113987379
Short name T397
Test name
Test status
Simulation time 197080972 ps
CPU time 0.91 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:18:59 PM PDT 24
Peak memory 207008 kb
Host smart-d7feac83-a6d3-4b82-834e-58050ae76e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11139
87379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.1113987379
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2890000026
Short name T2233
Test name
Test status
Simulation time 156964379 ps
CPU time 0.84 seconds
Started Jul 29 06:18:52 PM PDT 24
Finished Jul 29 06:18:53 PM PDT 24
Peak memory 207068 kb
Host smart-957f0246-7106-4969-94d9-39757162d95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28900
00026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2890000026
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1026575095
Short name T2572
Test name
Test status
Simulation time 156430458 ps
CPU time 0.87 seconds
Started Jul 29 06:18:59 PM PDT 24
Finished Jul 29 06:19:00 PM PDT 24
Peak memory 207044 kb
Host smart-63ef7a04-d683-4781-a838-286b93e0b911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10265
75095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1026575095
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.4157408366
Short name T405
Test name
Test status
Simulation time 227325653 ps
CPU time 1.02 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:05 PM PDT 24
Peak memory 207136 kb
Host smart-8d686a53-3430-4f72-be28-bd4b2c9fbab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41574
08366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.4157408366
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.1609493865
Short name T1157
Test name
Test status
Simulation time 3914543867 ps
CPU time 30.84 seconds
Started Jul 29 06:18:55 PM PDT 24
Finished Jul 29 06:19:26 PM PDT 24
Peak memory 217060 kb
Host smart-a05b013a-c082-4cae-a5d8-7498ad2f203a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1609493865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.1609493865
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2647115003
Short name T2076
Test name
Test status
Simulation time 214498853 ps
CPU time 0.95 seconds
Started Jul 29 06:18:56 PM PDT 24
Finished Jul 29 06:18:57 PM PDT 24
Peak memory 207104 kb
Host smart-6389182d-e1f6-44a3-8cd2-1aa1c1ddf6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26471
15003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2647115003
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1042648600
Short name T386
Test name
Test status
Simulation time 215093258 ps
CPU time 0.99 seconds
Started Jul 29 06:18:56 PM PDT 24
Finished Jul 29 06:18:57 PM PDT 24
Peak memory 207104 kb
Host smart-7caa2e46-2d4c-422b-9682-3218667f036c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10426
48600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1042648600
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.322958739
Short name T2697
Test name
Test status
Simulation time 1146771965 ps
CPU time 2.85 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:19:00 PM PDT 24
Peak memory 207256 kb
Host smart-b5c3e003-c2f8-4284-8dc5-30eb1ab6eb46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32295
8739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.322958739
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.556932520
Short name T20
Test name
Test status
Simulation time 2981310488 ps
CPU time 84.41 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:20:22 PM PDT 24
Peak memory 215516 kb
Host smart-6cb30aa8-de96-4a68-8d00-143462651875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55693
2520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.556932520
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.874473809
Short name T2642
Test name
Test status
Simulation time 1555246815 ps
CPU time 13.48 seconds
Started Jul 29 06:18:49 PM PDT 24
Finished Jul 29 06:19:02 PM PDT 24
Peak memory 207288 kb
Host smart-dd70cbb6-73bd-4850-85c1-8905a6f774a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874473809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_host
_handshake.874473809
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.286217251
Short name T1882
Test name
Test status
Simulation time 110095963 ps
CPU time 0.75 seconds
Started Jul 29 06:19:14 PM PDT 24
Finished Jul 29 06:19:15 PM PDT 24
Peak memory 207016 kb
Host smart-ebe5e34b-73b2-4ff0-bba5-d6430c7dbe86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=286217251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.286217251
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.748758759
Short name T1296
Test name
Test status
Simulation time 4276383824 ps
CPU time 6.04 seconds
Started Jul 29 06:18:55 PM PDT 24
Finished Jul 29 06:19:02 PM PDT 24
Peak memory 207344 kb
Host smart-af7229b5-7b82-4881-a12e-296b06a2103a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748758759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_ao
n_wake_disconnect.748758759
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1605785069
Short name T217
Test name
Test status
Simulation time 13475956738 ps
CPU time 15.89 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:19:14 PM PDT 24
Peak memory 207364 kb
Host smart-998ac5bd-02d3-4640-8318-98f3c9dd70a0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605785069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1605785069
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.975541638
Short name T1490
Test name
Test status
Simulation time 23352349731 ps
CPU time 29.25 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:19:27 PM PDT 24
Peak memory 207408 kb
Host smart-f6993a96-d88b-437d-8eae-7e8c20f07bff
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975541638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_ao
n_wake_resume.975541638
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.857197059
Short name T1433
Test name
Test status
Simulation time 155812932 ps
CPU time 0.87 seconds
Started Jul 29 06:18:56 PM PDT 24
Finished Jul 29 06:18:57 PM PDT 24
Peak memory 207124 kb
Host smart-70e0a41a-011f-4318-8e6e-2c0eea8325f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85719
7059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.857197059
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2878874142
Short name T2401
Test name
Test status
Simulation time 191872160 ps
CPU time 0.87 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:05 PM PDT 24
Peak memory 207084 kb
Host smart-9b30916b-d3ed-4bc1-b611-8b39d8b31078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28788
74142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2878874142
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.2121051612
Short name T634
Test name
Test status
Simulation time 511572071 ps
CPU time 1.66 seconds
Started Jul 29 06:18:56 PM PDT 24
Finished Jul 29 06:18:58 PM PDT 24
Peak memory 207128 kb
Host smart-21520974-6386-4864-8178-11e6768de141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21210
51612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.2121051612
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.2833626093
Short name T2634
Test name
Test status
Simulation time 1395744029 ps
CPU time 3.48 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:19:01 PM PDT 24
Peak memory 207256 kb
Host smart-a18df170-6ec5-4b98-b999-50bc7aa7d355
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2833626093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2833626093
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2241712903
Short name T2511
Test name
Test status
Simulation time 12803035571 ps
CPU time 28.25 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:31 PM PDT 24
Peak memory 207368 kb
Host smart-de226937-3386-4d0e-8ff1-da11057bc002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22417
12903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2241712903
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.1820521762
Short name T1172
Test name
Test status
Simulation time 307707231 ps
CPU time 4.38 seconds
Started Jul 29 06:18:56 PM PDT 24
Finished Jul 29 06:19:01 PM PDT 24
Peak memory 207212 kb
Host smart-4eedf47b-cadb-4b45-9a62-bf714d947f97
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820521762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.1820521762
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3925414151
Short name T1327
Test name
Test status
Simulation time 374603450 ps
CPU time 1.3 seconds
Started Jul 29 06:18:58 PM PDT 24
Finished Jul 29 06:19:00 PM PDT 24
Peak memory 207080 kb
Host smart-6dce23a2-f10b-4f1c-9647-1c81bd5b8722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39254
14151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3925414151
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.643762213
Short name T1199
Test name
Test status
Simulation time 154869467 ps
CPU time 0.84 seconds
Started Jul 29 06:19:01 PM PDT 24
Finished Jul 29 06:19:02 PM PDT 24
Peak memory 207044 kb
Host smart-1dc87236-9f73-4b48-af1b-232abd6a7c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64376
2213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.643762213
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3401710747
Short name T375
Test name
Test status
Simulation time 64444172 ps
CPU time 0.75 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:18:58 PM PDT 24
Peak memory 207096 kb
Host smart-ab6980b6-3b59-4403-98fe-ea809b2d762f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34017
10747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3401710747
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.566956593
Short name T1047
Test name
Test status
Simulation time 904451895 ps
CPU time 2.37 seconds
Started Jul 29 06:19:00 PM PDT 24
Finished Jul 29 06:19:02 PM PDT 24
Peak memory 207352 kb
Host smart-8d1312fa-825f-43e7-8d2a-211c03742d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56695
6593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.566956593
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.861328998
Short name T2390
Test name
Test status
Simulation time 221708789 ps
CPU time 1.63 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:18:59 PM PDT 24
Peak memory 207252 kb
Host smart-b5cc49b1-3500-424f-9481-323c89b39a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86132
8998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.861328998
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1529923532
Short name T373
Test name
Test status
Simulation time 235347263 ps
CPU time 1.24 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:03 PM PDT 24
Peak memory 215432 kb
Host smart-ff3faef0-b7c9-44b3-8edb-60990cf79185
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1529923532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1529923532
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.789073020
Short name T469
Test name
Test status
Simulation time 158956690 ps
CPU time 0.87 seconds
Started Jul 29 06:19:00 PM PDT 24
Finished Jul 29 06:19:01 PM PDT 24
Peak memory 207044 kb
Host smart-0bb379c3-0032-4b54-b704-8c80b25e3040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78907
3020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.789073020
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2837065064
Short name T519
Test name
Test status
Simulation time 184892136 ps
CPU time 0.92 seconds
Started Jul 29 06:18:55 PM PDT 24
Finished Jul 29 06:18:56 PM PDT 24
Peak memory 207144 kb
Host smart-c0485660-9f06-4dd8-906b-112483af41b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28370
65064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2837065064
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.4215551748
Short name T2735
Test name
Test status
Simulation time 7035325766 ps
CPU time 52.17 seconds
Started Jul 29 06:19:01 PM PDT 24
Finished Jul 29 06:19:54 PM PDT 24
Peak memory 207444 kb
Host smart-4171a61e-a9b4-433d-8d17-bb282a40320d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4215551748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.4215551748
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.3165566663
Short name T1579
Test name
Test status
Simulation time 5093216405 ps
CPU time 61.17 seconds
Started Jul 29 06:19:01 PM PDT 24
Finished Jul 29 06:20:02 PM PDT 24
Peak memory 207340 kb
Host smart-1fd49a37-2826-4ec8-93f0-d4dec4dd70bc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3165566663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.3165566663
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.958941666
Short name T821
Test name
Test status
Simulation time 199928320 ps
CPU time 0.91 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:06 PM PDT 24
Peak memory 207116 kb
Host smart-40ac5ffd-0584-4008-8fc0-486cd49212be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95894
1666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.958941666
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.3975657177
Short name T832
Test name
Test status
Simulation time 23299272440 ps
CPU time 27.32 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:31 PM PDT 24
Peak memory 207380 kb
Host smart-90cc54db-16e1-412f-96c0-52e1ec759b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39756
57177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.3975657177
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.1935540631
Short name T863
Test name
Test status
Simulation time 3322051550 ps
CPU time 5.44 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:08 PM PDT 24
Peak memory 207324 kb
Host smart-d78221ca-faf7-4996-be59-f33f2388be93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19355
40631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1935540631
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.3619580255
Short name T1867
Test name
Test status
Simulation time 8533313358 ps
CPU time 83.27 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:20:28 PM PDT 24
Peak memory 217608 kb
Host smart-b8db54e5-343c-469b-b98a-ce83c6615900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36195
80255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.3619580255
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.2184449851
Short name T19
Test name
Test status
Simulation time 6976142730 ps
CPU time 67.4 seconds
Started Jul 29 06:19:01 PM PDT 24
Finished Jul 29 06:20:08 PM PDT 24
Peak memory 207396 kb
Host smart-d4842751-3b37-41e1-aaf0-9db79a4eab3a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2184449851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.2184449851
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.823204708
Short name T2163
Test name
Test status
Simulation time 239432483 ps
CPU time 1.01 seconds
Started Jul 29 06:19:03 PM PDT 24
Finished Jul 29 06:19:04 PM PDT 24
Peak memory 207072 kb
Host smart-4e7076cf-6a80-4994-ad4a-f72ac4503a45
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=823204708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.823204708
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2138912669
Short name T1616
Test name
Test status
Simulation time 197508064 ps
CPU time 0.91 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:05 PM PDT 24
Peak memory 207112 kb
Host smart-0237cd31-4773-463f-b098-a949b556f90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21389
12669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2138912669
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.2107390872
Short name T2036
Test name
Test status
Simulation time 3817926245 ps
CPU time 28.44 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:33 PM PDT 24
Peak memory 217060 kb
Host smart-d78af9c8-34cb-438a-b313-79b182f5bcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21073
90872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.2107390872
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.1671120688
Short name T1946
Test name
Test status
Simulation time 5139420490 ps
CPU time 152.32 seconds
Started Jul 29 06:18:59 PM PDT 24
Finished Jul 29 06:21:31 PM PDT 24
Peak memory 215536 kb
Host smart-98cea154-0eba-4389-941e-502e5c9da091
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1671120688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1671120688
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.1846561681
Short name T361
Test name
Test status
Simulation time 215452192 ps
CPU time 0.93 seconds
Started Jul 29 06:18:57 PM PDT 24
Finished Jul 29 06:18:58 PM PDT 24
Peak memory 207132 kb
Host smart-72ed9349-d19a-43c4-acaa-b2afd4fe3f24
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1846561681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.1846561681
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3841615212
Short name T1986
Test name
Test status
Simulation time 157865518 ps
CPU time 0.85 seconds
Started Jul 29 06:19:00 PM PDT 24
Finished Jul 29 06:19:01 PM PDT 24
Peak memory 207084 kb
Host smart-9a26942c-07d8-400e-8422-6a3fdd354271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38416
15212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3841615212
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2533306725
Short name T134
Test name
Test status
Simulation time 212019499 ps
CPU time 0.95 seconds
Started Jul 29 06:18:54 PM PDT 24
Finished Jul 29 06:18:55 PM PDT 24
Peak memory 207100 kb
Host smart-6d187cad-ca35-4a24-bbed-9acd2b243ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25333
06725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2533306725
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3411121462
Short name T1827
Test name
Test status
Simulation time 207837157 ps
CPU time 0.94 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:05 PM PDT 24
Peak memory 207116 kb
Host smart-c57d990b-0624-437c-80f7-47808f73f2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34111
21462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3411121462
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.409369430
Short name T2662
Test name
Test status
Simulation time 158111802 ps
CPU time 0.87 seconds
Started Jul 29 06:19:06 PM PDT 24
Finished Jul 29 06:19:07 PM PDT 24
Peak memory 207136 kb
Host smart-e0deb11b-5262-4a3c-9ee7-184b9db948d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40936
9430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.409369430
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3162297381
Short name T1580
Test name
Test status
Simulation time 159366160 ps
CPU time 0.89 seconds
Started Jul 29 06:18:59 PM PDT 24
Finished Jul 29 06:19:00 PM PDT 24
Peak memory 207188 kb
Host smart-6d31b7dd-faaa-4c1d-8edc-2bf1cd2db50a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31622
97381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3162297381
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3300133988
Short name T1862
Test name
Test status
Simulation time 166863927 ps
CPU time 0.92 seconds
Started Jul 29 06:19:06 PM PDT 24
Finished Jul 29 06:19:07 PM PDT 24
Peak memory 207136 kb
Host smart-c80b7e02-7b1c-40f9-89ba-fb8bfa3906cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33001
33988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3300133988
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3964889853
Short name T1538
Test name
Test status
Simulation time 238978893 ps
CPU time 1.06 seconds
Started Jul 29 06:19:01 PM PDT 24
Finished Jul 29 06:19:02 PM PDT 24
Peak memory 207100 kb
Host smart-2a023feb-8631-40b8-be07-f3edee11c5bc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3964889853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3964889853
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.1785607434
Short name T1533
Test name
Test status
Simulation time 155877939 ps
CPU time 0.89 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:03 PM PDT 24
Peak memory 207016 kb
Host smart-81c8a333-125f-4f1b-a25a-097eaec28839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17856
07434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.1785607434
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1241992658
Short name T632
Test name
Test status
Simulation time 75026175 ps
CPU time 0.73 seconds
Started Jul 29 06:19:05 PM PDT 24
Finished Jul 29 06:19:06 PM PDT 24
Peak memory 207064 kb
Host smart-024f8428-e68e-428a-bdb4-4ea42c7f8103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12419
92658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1241992658
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3415713739
Short name T466
Test name
Test status
Simulation time 22846047231 ps
CPU time 52.48 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:55 PM PDT 24
Peak memory 219916 kb
Host smart-9720bf88-04ef-4529-b9e1-d856c8c4ce18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34157
13739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3415713739
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3839704670
Short name T2574
Test name
Test status
Simulation time 254741008 ps
CPU time 1.12 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:03 PM PDT 24
Peak memory 207076 kb
Host smart-20291c14-218b-4554-8b64-8e6d2345300e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38397
04670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3839704670
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.157699718
Short name T2603
Test name
Test status
Simulation time 208588222 ps
CPU time 1.04 seconds
Started Jul 29 06:19:03 PM PDT 24
Finished Jul 29 06:19:05 PM PDT 24
Peak memory 207068 kb
Host smart-30450d3b-41bf-4d5f-92ec-5871134f1ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15769
9718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.157699718
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.892189807
Short name T641
Test name
Test status
Simulation time 243034733 ps
CPU time 1.07 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:04 PM PDT 24
Peak memory 207044 kb
Host smart-428039aa-b827-4ce6-afa2-ffcb8f164e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89218
9807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.892189807
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1634129309
Short name T1883
Test name
Test status
Simulation time 147757633 ps
CPU time 0.87 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:03 PM PDT 24
Peak memory 207024 kb
Host smart-9b2aa474-4d07-4582-8169-93bbab54cfb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16341
29309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1634129309
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.1075316654
Short name T2442
Test name
Test status
Simulation time 151999897 ps
CPU time 0.89 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:03 PM PDT 24
Peak memory 207084 kb
Host smart-da7440f8-779a-4b17-b7e7-0d8ecdf6e07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10753
16654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1075316654
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2119438416
Short name T2095
Test name
Test status
Simulation time 179356751 ps
CPU time 0.91 seconds
Started Jul 29 06:19:09 PM PDT 24
Finished Jul 29 06:19:10 PM PDT 24
Peak memory 206968 kb
Host smart-821b7d1a-3cf4-452e-b6b1-b3c77ced6526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21194
38416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2119438416
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2424457103
Short name T968
Test name
Test status
Simulation time 162400274 ps
CPU time 0.88 seconds
Started Jul 29 06:19:05 PM PDT 24
Finished Jul 29 06:19:06 PM PDT 24
Peak memory 207104 kb
Host smart-ec8729f9-a24c-4216-8411-ea248da822e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24244
57103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2424457103
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1172239269
Short name T854
Test name
Test status
Simulation time 172626233 ps
CPU time 0.9 seconds
Started Jul 29 06:19:00 PM PDT 24
Finished Jul 29 06:19:01 PM PDT 24
Peak memory 207060 kb
Host smart-61284dd7-dbcd-40bd-90a5-adee512fccb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11722
39269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1172239269
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.938212801
Short name T33
Test name
Test status
Simulation time 3942785676 ps
CPU time 118.58 seconds
Started Jul 29 06:19:00 PM PDT 24
Finished Jul 29 06:20:58 PM PDT 24
Peak memory 215540 kb
Host smart-2287383b-4a9f-4471-bb20-1c087de59be5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=938212801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.938212801
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.1848947782
Short name T1796
Test name
Test status
Simulation time 179974930 ps
CPU time 0.91 seconds
Started Jul 29 06:19:08 PM PDT 24
Finished Jul 29 06:19:09 PM PDT 24
Peak memory 207004 kb
Host smart-12087154-7731-49e0-b62f-d0c9d19087c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18489
47782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.1848947782
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2775076307
Short name T740
Test name
Test status
Simulation time 186483745 ps
CPU time 0.89 seconds
Started Jul 29 06:19:01 PM PDT 24
Finished Jul 29 06:19:02 PM PDT 24
Peak memory 207032 kb
Host smart-8a05044e-2d4b-4e79-be7d-284a26c85e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27750
76307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2775076307
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.1409504556
Short name T393
Test name
Test status
Simulation time 1074970275 ps
CPU time 2.65 seconds
Started Jul 29 06:19:01 PM PDT 24
Finished Jul 29 06:19:04 PM PDT 24
Peak memory 207300 kb
Host smart-047e5874-75f8-4212-afa3-fc507b805597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14095
04556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.1409504556
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.2127425005
Short name T873
Test name
Test status
Simulation time 6988765845 ps
CPU time 55.12 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:59 PM PDT 24
Peak memory 207380 kb
Host smart-f9a3ca12-a5d4-4e72-b371-9850ed5acb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21274
25005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.2127425005
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.1541390085
Short name T875
Test name
Test status
Simulation time 1998698523 ps
CPU time 17.68 seconds
Started Jul 29 06:19:00 PM PDT 24
Finished Jul 29 06:19:18 PM PDT 24
Peak memory 207328 kb
Host smart-fc33a5a0-f048-422d-b2f8-e84879f15af2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541390085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos
t_handshake.1541390085
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.381901819
Short name T762
Test name
Test status
Simulation time 72959089 ps
CPU time 0.71 seconds
Started Jul 29 06:19:06 PM PDT 24
Finished Jul 29 06:19:07 PM PDT 24
Peak memory 207096 kb
Host smart-9ddbee6f-84d3-4fad-b7c1-44b8a1e6f1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=381901819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.381901819
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.1846436650
Short name T1779
Test name
Test status
Simulation time 3949022818 ps
CPU time 6.79 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:11 PM PDT 24
Peak memory 207320 kb
Host smart-6f3f28dc-a552-4131-a083-438c56bc0224
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846436650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_disconnect.1846436650
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3089088827
Short name T2230
Test name
Test status
Simulation time 13360315118 ps
CPU time 17.37 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:19 PM PDT 24
Peak memory 207408 kb
Host smart-cbdb2d43-466f-4ddd-8c1d-71bd88a1bfc4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089088827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3089088827
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.3161532499
Short name T1550
Test name
Test status
Simulation time 23377741626 ps
CPU time 33.78 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:38 PM PDT 24
Peak memory 207416 kb
Host smart-e733d48f-f6fc-4d35-b972-196cebf92e56
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161532499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.3161532499
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2644405456
Short name T2614
Test name
Test status
Simulation time 155146585 ps
CPU time 0.86 seconds
Started Jul 29 06:19:05 PM PDT 24
Finished Jul 29 06:19:06 PM PDT 24
Peak memory 207116 kb
Host smart-64c5ed14-4b8d-4141-9e07-f85b5c2dba22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26444
05456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2644405456
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.3136250875
Short name T77
Test name
Test status
Simulation time 144044275 ps
CPU time 0.82 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:05 PM PDT 24
Peak memory 207068 kb
Host smart-203afd52-b1ca-40ce-b4a3-133e170263ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31362
50875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.3136250875
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.2400461095
Short name T2807
Test name
Test status
Simulation time 206245098 ps
CPU time 1.02 seconds
Started Jul 29 06:19:06 PM PDT 24
Finished Jul 29 06:19:07 PM PDT 24
Peak memory 207144 kb
Host smart-29300e73-e39b-4248-b56d-4b91e3d71e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24004
61095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.2400461095
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.464996275
Short name T551
Test name
Test status
Simulation time 506856235 ps
CPU time 1.56 seconds
Started Jul 29 06:19:08 PM PDT 24
Finished Jul 29 06:19:10 PM PDT 24
Peak memory 206992 kb
Host smart-abb69ac1-4d8d-4848-a736-72e76227ad3b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=464996275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.464996275
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.4068994730
Short name T1184
Test name
Test status
Simulation time 16120178233 ps
CPU time 33.58 seconds
Started Jul 29 06:19:06 PM PDT 24
Finished Jul 29 06:19:40 PM PDT 24
Peak memory 207404 kb
Host smart-d3849957-32f3-4a0d-b528-239bd04cc1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40689
94730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.4068994730
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.2386906845
Short name T2668
Test name
Test status
Simulation time 2441126110 ps
CPU time 21.81 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:26 PM PDT 24
Peak memory 207264 kb
Host smart-b64cb87a-a89f-43fb-bfe9-df2d2483ba48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386906845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.2386906845
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.165340001
Short name T1006
Test name
Test status
Simulation time 463222197 ps
CPU time 1.5 seconds
Started Jul 29 06:19:09 PM PDT 24
Finished Jul 29 06:19:10 PM PDT 24
Peak memory 206972 kb
Host smart-e3016d36-1204-478e-9cf9-590b3e73d3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16534
0001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.165340001
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3941250254
Short name T2829
Test name
Test status
Simulation time 142870971 ps
CPU time 0.83 seconds
Started Jul 29 06:19:03 PM PDT 24
Finished Jul 29 06:19:04 PM PDT 24
Peak memory 207000 kb
Host smart-297fe031-f5c3-4221-8128-4585c357eb3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39412
50254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3941250254
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.555518805
Short name T1003
Test name
Test status
Simulation time 52081046 ps
CPU time 0.75 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:05 PM PDT 24
Peak memory 207044 kb
Host smart-4f208915-52ef-4546-887b-d35fbc887dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55551
8805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.555518805
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2143889059
Short name T2766
Test name
Test status
Simulation time 853906877 ps
CPU time 2.28 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:05 PM PDT 24
Peak memory 207332 kb
Host smart-c96b6f65-56df-45cc-90bc-b8902532e320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21438
89059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2143889059
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3855012458
Short name T183
Test name
Test status
Simulation time 304940153 ps
CPU time 2.36 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:04 PM PDT 24
Peak memory 207272 kb
Host smart-864a110d-bf91-408c-9587-ecfe6344d911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38550
12458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3855012458
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.4154746707
Short name T2633
Test name
Test status
Simulation time 278065015 ps
CPU time 1.15 seconds
Started Jul 29 06:19:02 PM PDT 24
Finished Jul 29 06:19:03 PM PDT 24
Peak memory 207328 kb
Host smart-8144d732-58b0-4057-810e-ef0bf8e819a2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4154746707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.4154746707
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.95692133
Short name T440
Test name
Test status
Simulation time 168328374 ps
CPU time 0.81 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:05 PM PDT 24
Peak memory 207000 kb
Host smart-12f08bdd-1520-4174-8d93-515b615979cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95692
133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.95692133
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1818378817
Short name T2315
Test name
Test status
Simulation time 172577554 ps
CPU time 0.92 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:06 PM PDT 24
Peak memory 207092 kb
Host smart-fa24d324-d710-443d-b389-ea65c06d9d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18183
78817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1818378817
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.1700860840
Short name T1088
Test name
Test status
Simulation time 5853799593 ps
CPU time 59 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:20:04 PM PDT 24
Peak memory 207460 kb
Host smart-a6489666-613a-4a1f-972f-e6eb7e1a2bd3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1700860840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.1700860840
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.3614140529
Short name T2161
Test name
Test status
Simulation time 3817194827 ps
CPU time 41.23 seconds
Started Jul 29 06:19:08 PM PDT 24
Finished Jul 29 06:19:49 PM PDT 24
Peak memory 207216 kb
Host smart-a9d584a1-ec4a-44fc-bcb0-95e091cef57d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3614140529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.3614140529
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.2351159305
Short name T1914
Test name
Test status
Simulation time 223411775 ps
CPU time 0.95 seconds
Started Jul 29 06:19:01 PM PDT 24
Finished Jul 29 06:19:02 PM PDT 24
Peak memory 207056 kb
Host smart-d03d21d5-64ae-4904-bd3b-a334c24c452d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23511
59305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.2351159305
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.500978832
Short name T2816
Test name
Test status
Simulation time 23346454060 ps
CPU time 33.29 seconds
Started Jul 29 06:19:03 PM PDT 24
Finished Jul 29 06:19:36 PM PDT 24
Peak memory 207396 kb
Host smart-a9c2bbff-7926-4669-b9dd-1c454678164c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50097
8832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.500978832
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.4215609634
Short name T735
Test name
Test status
Simulation time 3288850489 ps
CPU time 4.8 seconds
Started Jul 29 06:19:04 PM PDT 24
Finished Jul 29 06:19:09 PM PDT 24
Peak memory 207328 kb
Host smart-1a622a96-2fae-4a06-998b-c882ff4f7dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42156
09634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.4215609634
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.4198732749
Short name T1892
Test name
Test status
Simulation time 6770181208 ps
CPU time 55.09 seconds
Started Jul 29 06:19:07 PM PDT 24
Finished Jul 29 06:20:02 PM PDT 24
Peak memory 215596 kb
Host smart-e2c86b75-c5b5-4fe8-a6d1-a5992c70ddbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41987
32749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.4198732749
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.4182099283
Short name T1593
Test name
Test status
Simulation time 3878336045 ps
CPU time 115.19 seconds
Started Jul 29 06:19:08 PM PDT 24
Finished Jul 29 06:21:03 PM PDT 24
Peak memory 215520 kb
Host smart-aec85ce1-95d9-4bf1-a03a-e97fb6d87a0f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4182099283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.4182099283
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3593242746
Short name T1309
Test name
Test status
Simulation time 250447645 ps
CPU time 1.13 seconds
Started Jul 29 06:19:09 PM PDT 24
Finished Jul 29 06:19:10 PM PDT 24
Peak memory 207128 kb
Host smart-7f86026b-fc98-40cc-a51a-806347287f52
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3593242746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3593242746
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1933941037
Short name T563
Test name
Test status
Simulation time 188019342 ps
CPU time 0.91 seconds
Started Jul 29 06:19:07 PM PDT 24
Finished Jul 29 06:19:08 PM PDT 24
Peak memory 207080 kb
Host smart-1da46b13-705b-479d-83d3-bbcee897bbea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19339
41037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1933941037
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.3726069945
Short name T628
Test name
Test status
Simulation time 3263159308 ps
CPU time 32.6 seconds
Started Jul 29 06:19:08 PM PDT 24
Finished Jul 29 06:19:40 PM PDT 24
Peak memory 215564 kb
Host smart-415d6f92-ca1e-4bd8-b3ca-469a9c460494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37260
69945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.3726069945
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.1756348677
Short name T2215
Test name
Test status
Simulation time 5963693290 ps
CPU time 169.49 seconds
Started Jul 29 06:19:08 PM PDT 24
Finished Jul 29 06:21:57 PM PDT 24
Peak memory 223500 kb
Host smart-b6312b2e-cdb4-4b82-9fc1-d90b25aeaa07
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1756348677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.1756348677
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.3256107786
Short name T424
Test name
Test status
Simulation time 160257732 ps
CPU time 0.89 seconds
Started Jul 29 06:19:12 PM PDT 24
Finished Jul 29 06:19:13 PM PDT 24
Peak memory 207060 kb
Host smart-a056c03f-1270-48f3-ae14-2fae3605e6b3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3256107786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.3256107786
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3345715650
Short name T986
Test name
Test status
Simulation time 164219218 ps
CPU time 0.87 seconds
Started Jul 29 06:19:10 PM PDT 24
Finished Jul 29 06:19:11 PM PDT 24
Peak memory 207068 kb
Host smart-7bd05b6b-49d5-4d84-8959-490c8108f82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33457
15650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3345715650
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.774888060
Short name T123
Test name
Test status
Simulation time 231023811 ps
CPU time 1 seconds
Started Jul 29 06:19:07 PM PDT 24
Finished Jul 29 06:19:08 PM PDT 24
Peak memory 207068 kb
Host smart-25c3d665-a2a2-4f27-b689-d4c871a6f33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77488
8060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.774888060
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.4102111184
Short name T2629
Test name
Test status
Simulation time 150115135 ps
CPU time 0.87 seconds
Started Jul 29 06:19:07 PM PDT 24
Finished Jul 29 06:19:08 PM PDT 24
Peak memory 207100 kb
Host smart-87f432dc-7468-418c-8255-c1077ad30647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41021
11184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.4102111184
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3871597289
Short name T2777
Test name
Test status
Simulation time 162879170 ps
CPU time 0.86 seconds
Started Jul 29 06:19:08 PM PDT 24
Finished Jul 29 06:19:09 PM PDT 24
Peak memory 207140 kb
Host smart-c8f8a802-8569-4c1c-a5c7-fe35cb029620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38715
97289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3871597289
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.416833143
Short name T648
Test name
Test status
Simulation time 156267343 ps
CPU time 0.89 seconds
Started Jul 29 06:19:09 PM PDT 24
Finished Jul 29 06:19:10 PM PDT 24
Peak memory 207104 kb
Host smart-0dca4818-1caa-4aa5-9157-0bdd1b61cbfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41683
3143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.416833143
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3055531343
Short name T170
Test name
Test status
Simulation time 167992992 ps
CPU time 0.86 seconds
Started Jul 29 06:19:10 PM PDT 24
Finished Jul 29 06:19:10 PM PDT 24
Peak memory 207044 kb
Host smart-b06c8460-452c-417f-b3a6-fe252c5ed314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30555
31343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3055531343
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.17465930
Short name T2130
Test name
Test status
Simulation time 217659990 ps
CPU time 0.99 seconds
Started Jul 29 06:19:06 PM PDT 24
Finished Jul 29 06:19:07 PM PDT 24
Peak memory 207124 kb
Host smart-63c3a1ab-fca2-4477-9215-3ceedb5bdfb3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=17465930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.17465930
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.995823510
Short name T2375
Test name
Test status
Simulation time 139400757 ps
CPU time 0.84 seconds
Started Jul 29 06:19:11 PM PDT 24
Finished Jul 29 06:19:12 PM PDT 24
Peak memory 207040 kb
Host smart-0598f149-0518-4c67-b06b-97f3a078e2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99582
3510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.995823510
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2872067441
Short name T1054
Test name
Test status
Simulation time 42122794 ps
CPU time 0.7 seconds
Started Jul 29 06:19:08 PM PDT 24
Finished Jul 29 06:19:09 PM PDT 24
Peak memory 207072 kb
Host smart-0fda1e88-96ce-4ab7-a119-9e00ca455f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28720
67441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2872067441
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3881094422
Short name T239
Test name
Test status
Simulation time 7572711129 ps
CPU time 18.83 seconds
Started Jul 29 06:19:09 PM PDT 24
Finished Jul 29 06:19:28 PM PDT 24
Peak memory 219896 kb
Host smart-96af23eb-85dd-4281-bc89-bed5d227c925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38810
94422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3881094422
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.189936722
Short name T2737
Test name
Test status
Simulation time 170606432 ps
CPU time 0.85 seconds
Started Jul 29 06:19:09 PM PDT 24
Finished Jul 29 06:19:09 PM PDT 24
Peak memory 207128 kb
Host smart-d3f41011-f103-4e19-aa6c-ecc755284c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18993
6722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.189936722
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3059191649
Short name T56
Test name
Test status
Simulation time 247583650 ps
CPU time 0.96 seconds
Started Jul 29 06:19:06 PM PDT 24
Finished Jul 29 06:19:07 PM PDT 24
Peak memory 207104 kb
Host smart-78588cfb-ffb6-46c7-802a-afb2029e8234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30591
91649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3059191649
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.359766166
Short name T1297
Test name
Test status
Simulation time 196952415 ps
CPU time 0.96 seconds
Started Jul 29 06:19:09 PM PDT 24
Finished Jul 29 06:19:10 PM PDT 24
Peak memory 207120 kb
Host smart-35f5b44e-d3fa-4afb-a917-5e48d38d5aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35976
6166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.359766166
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.2101282750
Short name T2343
Test name
Test status
Simulation time 168385897 ps
CPU time 0.96 seconds
Started Jul 29 06:19:10 PM PDT 24
Finished Jul 29 06:19:11 PM PDT 24
Peak memory 207136 kb
Host smart-444e4609-0b85-4eca-be0e-bc525033954d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21012
82750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.2101282750
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.724768895
Short name T898
Test name
Test status
Simulation time 185765284 ps
CPU time 0.9 seconds
Started Jul 29 06:19:10 PM PDT 24
Finished Jul 29 06:19:11 PM PDT 24
Peak memory 207080 kb
Host smart-67a8de02-5aeb-499b-8377-eb56e0b005e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72476
8895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.724768895
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.762305877
Short name T2667
Test name
Test status
Simulation time 159429096 ps
CPU time 0.92 seconds
Started Jul 29 06:19:07 PM PDT 24
Finished Jul 29 06:19:08 PM PDT 24
Peak memory 207052 kb
Host smart-ad753d3b-b98c-43e1-b8a4-20728ed8579e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76230
5877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.762305877
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.110527401
Short name T841
Test name
Test status
Simulation time 162498293 ps
CPU time 0.89 seconds
Started Jul 29 06:19:07 PM PDT 24
Finished Jul 29 06:19:08 PM PDT 24
Peak memory 207084 kb
Host smart-35cd1f60-f4dc-4c8f-8912-061e269fbcbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11052
7401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.110527401
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.892534236
Short name T296
Test name
Test status
Simulation time 208658701 ps
CPU time 0.95 seconds
Started Jul 29 06:19:06 PM PDT 24
Finished Jul 29 06:19:07 PM PDT 24
Peak memory 207044 kb
Host smart-4c542363-8850-4f56-b592-14a939e1481d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89253
4236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.892534236
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.3478444620
Short name T2372
Test name
Test status
Simulation time 5083892480 ps
CPU time 144.55 seconds
Started Jul 29 06:19:09 PM PDT 24
Finished Jul 29 06:21:34 PM PDT 24
Peak memory 215596 kb
Host smart-93351c97-c772-43ec-a28b-fa1fda98f8b0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3478444620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.3478444620
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.918780854
Short name T1223
Test name
Test status
Simulation time 181206706 ps
CPU time 0.92 seconds
Started Jul 29 06:19:07 PM PDT 24
Finished Jul 29 06:19:08 PM PDT 24
Peak memory 207056 kb
Host smart-44d31379-722d-441b-a8b9-0866f341cdcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91878
0854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.918780854
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2976131012
Short name T2461
Test name
Test status
Simulation time 151547995 ps
CPU time 0.92 seconds
Started Jul 29 06:19:09 PM PDT 24
Finished Jul 29 06:19:10 PM PDT 24
Peak memory 206980 kb
Host smart-bce96e5f-f16e-413c-86d7-1b4b00a6f4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29761
31012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2976131012
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.1880170200
Short name T1046
Test name
Test status
Simulation time 209684831 ps
CPU time 0.99 seconds
Started Jul 29 06:19:09 PM PDT 24
Finished Jul 29 06:19:10 PM PDT 24
Peak memory 206952 kb
Host smart-503d22d8-4542-4c1d-89c3-2b5a8c46d044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18801
70200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1880170200
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.2530170926
Short name T465
Test name
Test status
Simulation time 6082335620 ps
CPU time 50.12 seconds
Started Jul 29 06:19:10 PM PDT 24
Finished Jul 29 06:20:00 PM PDT 24
Peak memory 207412 kb
Host smart-67d78945-c288-41e3-92a1-dc6b3960f881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25301
70926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2530170926
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.4039851721
Short name T2500
Test name
Test status
Simulation time 4782711232 ps
CPU time 43.95 seconds
Started Jul 29 06:19:03 PM PDT 24
Finished Jul 29 06:19:48 PM PDT 24
Peak memory 207420 kb
Host smart-6ffa3927-4a1c-47f9-a5d7-097b50b9be9d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039851721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos
t_handshake.4039851721
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.2315473668
Short name T376
Test name
Test status
Simulation time 57088291 ps
CPU time 0.74 seconds
Started Jul 29 06:19:24 PM PDT 24
Finished Jul 29 06:19:25 PM PDT 24
Peak memory 207160 kb
Host smart-240c8a1d-6a9e-4fc3-a7eb-f2de3c083118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2315473668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.2315473668
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1704530325
Short name T599
Test name
Test status
Simulation time 4045969024 ps
CPU time 6.13 seconds
Started Jul 29 06:19:08 PM PDT 24
Finished Jul 29 06:19:14 PM PDT 24
Peak memory 207344 kb
Host smart-80bbe704-4e53-4a19-9f5a-807ce5d74192
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704530325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.1704530325
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.57687829
Short name T2420
Test name
Test status
Simulation time 13349444365 ps
CPU time 20.07 seconds
Started Jul 29 06:19:13 PM PDT 24
Finished Jul 29 06:19:33 PM PDT 24
Peak memory 207380 kb
Host smart-31a3c7cb-b605-4009-ba83-d733ee9e9792
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=57687829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.57687829
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3904295740
Short name T2440
Test name
Test status
Simulation time 23356674853 ps
CPU time 27.85 seconds
Started Jul 29 06:19:09 PM PDT 24
Finished Jul 29 06:19:37 PM PDT 24
Peak memory 207372 kb
Host smart-4fd7e10e-3b0d-458b-9a1b-ac01c2b3b94e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904295740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_resume.3904295740
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3870871869
Short name T958
Test name
Test status
Simulation time 188633093 ps
CPU time 0.95 seconds
Started Jul 29 06:19:11 PM PDT 24
Finished Jul 29 06:19:12 PM PDT 24
Peak memory 207124 kb
Host smart-54a41925-ca3a-4ffe-8622-c53046948656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38708
71869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3870871869
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.4063140277
Short name T2090
Test name
Test status
Simulation time 145899045 ps
CPU time 0.85 seconds
Started Jul 29 06:19:13 PM PDT 24
Finished Jul 29 06:19:14 PM PDT 24
Peak memory 207068 kb
Host smart-1066fc2e-b4ba-4713-9747-e1e676285b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40631
40277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.4063140277
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.101521047
Short name T1341
Test name
Test status
Simulation time 333413602 ps
CPU time 1.3 seconds
Started Jul 29 06:19:12 PM PDT 24
Finished Jul 29 06:19:14 PM PDT 24
Peak memory 207184 kb
Host smart-5e80c05f-bf5a-42f5-8966-7afbedad89ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10152
1047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.101521047
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.3399422704
Short name T802
Test name
Test status
Simulation time 1491248846 ps
CPU time 3.76 seconds
Started Jul 29 06:19:16 PM PDT 24
Finished Jul 29 06:19:20 PM PDT 24
Peak memory 207308 kb
Host smart-360fdaf0-d8a2-48e0-a432-e230d70542cb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3399422704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.3399422704
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.2132450157
Short name T2792
Test name
Test status
Simulation time 17790829892 ps
CPU time 38 seconds
Started Jul 29 06:19:13 PM PDT 24
Finished Jul 29 06:19:52 PM PDT 24
Peak memory 207428 kb
Host smart-e7b08813-e67f-4810-8418-4d119142bdc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21324
50157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.2132450157
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.850755826
Short name T824
Test name
Test status
Simulation time 1399761631 ps
CPU time 35.06 seconds
Started Jul 29 06:19:11 PM PDT 24
Finished Jul 29 06:19:46 PM PDT 24
Peak memory 207260 kb
Host smart-b9a3bd87-73d3-43af-89f8-443519e11110
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850755826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.850755826
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1944361351
Short name T2221
Test name
Test status
Simulation time 149494775 ps
CPU time 0.84 seconds
Started Jul 29 06:19:11 PM PDT 24
Finished Jul 29 06:19:13 PM PDT 24
Peak memory 207072 kb
Host smart-1ced6990-0bef-4b53-bcde-9ddf634946b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19443
61351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1944361351
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.4031134198
Short name T2008
Test name
Test status
Simulation time 59520468 ps
CPU time 0.78 seconds
Started Jul 29 06:19:14 PM PDT 24
Finished Jul 29 06:19:15 PM PDT 24
Peak memory 207044 kb
Host smart-3748a5c4-7ed6-4d8d-9aa8-bd3a240a70e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40311
34198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.4031134198
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.256057940
Short name T1029
Test name
Test status
Simulation time 864365668 ps
CPU time 2.2 seconds
Started Jul 29 06:19:10 PM PDT 24
Finished Jul 29 06:19:12 PM PDT 24
Peak memory 207332 kb
Host smart-b1a2feed-dc72-4a1f-a646-611887f87016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25605
7940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.256057940
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3558391691
Short name T757
Test name
Test status
Simulation time 295504654 ps
CPU time 2.02 seconds
Started Jul 29 06:19:13 PM PDT 24
Finished Jul 29 06:19:15 PM PDT 24
Peak memory 207296 kb
Host smart-ec08418e-619e-48ff-a283-4badd66153eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35583
91691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3558391691
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.625577305
Short name T1786
Test name
Test status
Simulation time 234643709 ps
CPU time 1.07 seconds
Started Jul 29 06:19:13 PM PDT 24
Finished Jul 29 06:19:14 PM PDT 24
Peak memory 207260 kb
Host smart-c9375ecc-7794-438b-b046-4a92150277a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=625577305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.625577305
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1506851813
Short name T1211
Test name
Test status
Simulation time 139455930 ps
CPU time 0.82 seconds
Started Jul 29 06:19:14 PM PDT 24
Finished Jul 29 06:19:15 PM PDT 24
Peak memory 207068 kb
Host smart-584cb383-3995-4a65-9ff3-594f4e28ee91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15068
51813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1506851813
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1050408924
Short name T1246
Test name
Test status
Simulation time 246680501 ps
CPU time 1.02 seconds
Started Jul 29 06:19:15 PM PDT 24
Finished Jul 29 06:19:17 PM PDT 24
Peak memory 207076 kb
Host smart-977e6b5e-e923-453d-baf1-a88233d8bf42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10504
08924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1050408924
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.508617107
Short name T2855
Test name
Test status
Simulation time 8187879720 ps
CPU time 244.82 seconds
Started Jul 29 06:19:11 PM PDT 24
Finished Jul 29 06:23:16 PM PDT 24
Peak memory 215608 kb
Host smart-e84c731e-1b53-410b-8376-ccaff5332e67
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=508617107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.508617107
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.2790291371
Short name T93
Test name
Test status
Simulation time 13150084173 ps
CPU time 87.56 seconds
Started Jul 29 06:19:12 PM PDT 24
Finished Jul 29 06:20:39 PM PDT 24
Peak memory 207380 kb
Host smart-0191e5e5-62f8-45b6-84ec-5388ec2d124c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2790291371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.2790291371
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2639245846
Short name T957
Test name
Test status
Simulation time 206248585 ps
CPU time 0.98 seconds
Started Jul 29 06:19:14 PM PDT 24
Finished Jul 29 06:19:15 PM PDT 24
Peak memory 207064 kb
Host smart-7f7bb0ed-0771-493d-9281-abfd6c28018d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26392
45846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2639245846
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2788064507
Short name T2156
Test name
Test status
Simulation time 23308864514 ps
CPU time 27.92 seconds
Started Jul 29 06:19:13 PM PDT 24
Finished Jul 29 06:19:42 PM PDT 24
Peak memory 207416 kb
Host smart-de3a704f-e5d8-4e97-9e84-68622b37a86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27880
64507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2788064507
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.4225721968
Short name T2832
Test name
Test status
Simulation time 3327289607 ps
CPU time 4.91 seconds
Started Jul 29 06:19:11 PM PDT 24
Finished Jul 29 06:19:16 PM PDT 24
Peak memory 207352 kb
Host smart-81975a8e-bc76-483b-a62b-50548196dd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42257
21968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.4225721968
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.3211047466
Short name T1476
Test name
Test status
Simulation time 9253075917 ps
CPU time 274.69 seconds
Started Jul 29 06:19:14 PM PDT 24
Finished Jul 29 06:23:49 PM PDT 24
Peak memory 215620 kb
Host smart-a1377a21-26b8-4dfd-8c2f-2b5000a3b32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32110
47466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.3211047466
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.3033842799
Short name T1432
Test name
Test status
Simulation time 3158163327 ps
CPU time 88.13 seconds
Started Jul 29 06:19:12 PM PDT 24
Finished Jul 29 06:20:40 PM PDT 24
Peak memory 215516 kb
Host smart-ece9b98c-5d82-4660-9f5d-db83d37ae47a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3033842799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.3033842799
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3628678880
Short name T449
Test name
Test status
Simulation time 260414144 ps
CPU time 1.08 seconds
Started Jul 29 06:19:16 PM PDT 24
Finished Jul 29 06:19:17 PM PDT 24
Peak memory 207104 kb
Host smart-f3b23688-77bd-4415-92c3-2fef8bd5aa15
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3628678880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3628678880
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.487408875
Short name T1062
Test name
Test status
Simulation time 194487234 ps
CPU time 0.92 seconds
Started Jul 29 06:19:13 PM PDT 24
Finished Jul 29 06:19:15 PM PDT 24
Peak memory 207132 kb
Host smart-d4e9bc5e-f275-448d-9a49-14d4017c08df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48740
8875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.487408875
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.2841109357
Short name T1455
Test name
Test status
Simulation time 5106889541 ps
CPU time 42.36 seconds
Started Jul 29 06:19:12 PM PDT 24
Finished Jul 29 06:19:55 PM PDT 24
Peak memory 217088 kb
Host smart-93eed4af-b5d4-420c-af73-b02f2dd9d3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28411
09357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.2841109357
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.801142281
Short name T322
Test name
Test status
Simulation time 3539580854 ps
CPU time 27.78 seconds
Started Jul 29 06:19:12 PM PDT 24
Finished Jul 29 06:19:40 PM PDT 24
Peak memory 215560 kb
Host smart-55dd6c9c-32af-4025-b26c-eb488d6fce98
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=801142281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.801142281
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.1862461203
Short name T683
Test name
Test status
Simulation time 171086535 ps
CPU time 0.87 seconds
Started Jul 29 06:19:12 PM PDT 24
Finished Jul 29 06:19:13 PM PDT 24
Peak memory 207108 kb
Host smart-3270debc-165f-419f-ad10-53adb840f79e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1862461203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.1862461203
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3236792890
Short name T312
Test name
Test status
Simulation time 157809620 ps
CPU time 0.88 seconds
Started Jul 29 06:19:16 PM PDT 24
Finished Jul 29 06:19:17 PM PDT 24
Peak memory 207096 kb
Host smart-8385817d-7344-4aaf-a391-8737a58d0f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32367
92890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3236792890
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.734264407
Short name T142
Test name
Test status
Simulation time 202831715 ps
CPU time 1.02 seconds
Started Jul 29 06:19:14 PM PDT 24
Finished Jul 29 06:19:15 PM PDT 24
Peak memory 207100 kb
Host smart-464b1827-e373-4bc7-a891-816b7c6568c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73426
4407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.734264407
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.381373088
Short name T2715
Test name
Test status
Simulation time 201869674 ps
CPU time 0.99 seconds
Started Jul 29 06:19:13 PM PDT 24
Finished Jul 29 06:19:14 PM PDT 24
Peak memory 207080 kb
Host smart-e32ee0c0-b4e4-482a-b810-cb79022a823e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38137
3088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.381373088
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.543147754
Short name T1421
Test name
Test status
Simulation time 169745348 ps
CPU time 0.99 seconds
Started Jul 29 06:19:16 PM PDT 24
Finished Jul 29 06:19:17 PM PDT 24
Peak memory 207076 kb
Host smart-8fac3eb0-0469-4302-a27f-2b3811f14011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54314
7754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.543147754
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.57635043
Short name T2742
Test name
Test status
Simulation time 205649045 ps
CPU time 0.91 seconds
Started Jul 29 06:19:11 PM PDT 24
Finished Jul 29 06:19:13 PM PDT 24
Peak memory 207064 kb
Host smart-a74ab678-d4d8-485d-b45f-02f1e981c83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57635
043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.57635043
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.3254599581
Short name T169
Test name
Test status
Simulation time 148377123 ps
CPU time 0.84 seconds
Started Jul 29 06:19:14 PM PDT 24
Finished Jul 29 06:19:15 PM PDT 24
Peak memory 207116 kb
Host smart-6dae9790-7703-46cb-8c20-2e70c4c33bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32545
99581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.3254599581
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.2508849677
Short name T1825
Test name
Test status
Simulation time 229254174 ps
CPU time 1.04 seconds
Started Jul 29 06:19:13 PM PDT 24
Finished Jul 29 06:19:15 PM PDT 24
Peak memory 207112 kb
Host smart-f113be67-4aea-41a2-bd17-c9da23d0cef8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2508849677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.2508849677
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2516338105
Short name T876
Test name
Test status
Simulation time 194615343 ps
CPU time 0.88 seconds
Started Jul 29 06:19:16 PM PDT 24
Finished Jul 29 06:19:17 PM PDT 24
Peak memory 207036 kb
Host smart-ad014108-f824-4dee-af0a-de8be7018279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25163
38105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2516338105
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2396388044
Short name T407
Test name
Test status
Simulation time 40071062 ps
CPU time 0.7 seconds
Started Jul 29 06:19:17 PM PDT 24
Finished Jul 29 06:19:18 PM PDT 24
Peak memory 207076 kb
Host smart-efff7efc-cbc8-4b64-866d-2ebbc910aa46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23963
88044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2396388044
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1157220581
Short name T2779
Test name
Test status
Simulation time 14605191552 ps
CPU time 35.81 seconds
Started Jul 29 06:19:16 PM PDT 24
Finished Jul 29 06:19:52 PM PDT 24
Peak memory 215684 kb
Host smart-83ed9045-69ff-41ca-aff9-a5507c4ba65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11572
20581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1157220581
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.293101091
Short name T1681
Test name
Test status
Simulation time 158154627 ps
CPU time 0.87 seconds
Started Jul 29 06:19:17 PM PDT 24
Finished Jul 29 06:19:18 PM PDT 24
Peak memory 207080 kb
Host smart-d36b32fa-b5cf-48ca-9fd3-ea0103d8c53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29310
1091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.293101091
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2082770678
Short name T2316
Test name
Test status
Simulation time 224556163 ps
CPU time 0.95 seconds
Started Jul 29 06:19:16 PM PDT 24
Finished Jul 29 06:19:17 PM PDT 24
Peak memory 207044 kb
Host smart-6f3a72be-8c7a-4b9c-82d4-8f200d128e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20827
70678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2082770678
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2274321060
Short name T2791
Test name
Test status
Simulation time 230973981 ps
CPU time 0.98 seconds
Started Jul 29 06:19:24 PM PDT 24
Finished Jul 29 06:19:25 PM PDT 24
Peak memory 207104 kb
Host smart-2f6fc998-6b1f-4bf1-9bea-d0472429227e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22743
21060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2274321060
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.3003880960
Short name T2400
Test name
Test status
Simulation time 160236649 ps
CPU time 0.9 seconds
Started Jul 29 06:19:16 PM PDT 24
Finished Jul 29 06:19:17 PM PDT 24
Peak memory 207108 kb
Host smart-3bd0d013-4ee8-4791-8b5e-8472e01aa52e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30038
80960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.3003880960
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2092321921
Short name T626
Test name
Test status
Simulation time 146472049 ps
CPU time 0.79 seconds
Started Jul 29 06:19:16 PM PDT 24
Finished Jul 29 06:19:17 PM PDT 24
Peak memory 207032 kb
Host smart-b7dd655c-a0b9-49f0-9e7b-7559f602b224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20923
21921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2092321921
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.770480823
Short name T1271
Test name
Test status
Simulation time 168990658 ps
CPU time 0.85 seconds
Started Jul 29 06:19:17 PM PDT 24
Finished Jul 29 06:19:18 PM PDT 24
Peak memory 207072 kb
Host smart-1c530829-545b-42df-9fe4-96893c10688c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77048
0823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.770480823
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3349384901
Short name T1114
Test name
Test status
Simulation time 173477385 ps
CPU time 0.86 seconds
Started Jul 29 06:19:16 PM PDT 24
Finished Jul 29 06:19:17 PM PDT 24
Peak memory 207064 kb
Host smart-a3279cdf-5fd6-431b-8176-6cb4f4f2bd29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33493
84901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3349384901
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1444327101
Short name T52
Test name
Test status
Simulation time 251641240 ps
CPU time 1.14 seconds
Started Jul 29 06:19:17 PM PDT 24
Finished Jul 29 06:19:18 PM PDT 24
Peak memory 207068 kb
Host smart-79a09890-aef2-4e9a-bc9d-fdea24ab2164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14443
27101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1444327101
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2130023380
Short name T1221
Test name
Test status
Simulation time 5101665194 ps
CPU time 38.19 seconds
Started Jul 29 06:19:16 PM PDT 24
Finished Jul 29 06:19:55 PM PDT 24
Peak memory 217144 kb
Host smart-2436f49a-0721-49ad-9a69-6987e471d638
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2130023380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2130023380
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3212537466
Short name T2382
Test name
Test status
Simulation time 191180523 ps
CPU time 0.89 seconds
Started Jul 29 06:19:24 PM PDT 24
Finished Jul 29 06:19:25 PM PDT 24
Peak memory 207080 kb
Host smart-b7f99cce-0022-4d27-b455-3101017233e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32125
37466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3212537466
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1607458137
Short name T1168
Test name
Test status
Simulation time 157440708 ps
CPU time 0.88 seconds
Started Jul 29 06:19:19 PM PDT 24
Finished Jul 29 06:19:20 PM PDT 24
Peak memory 206980 kb
Host smart-98b5420b-20e7-4f42-b6b7-99858fc2bbd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16074
58137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1607458137
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.3121480634
Short name T414
Test name
Test status
Simulation time 1016088156 ps
CPU time 2.42 seconds
Started Jul 29 06:19:25 PM PDT 24
Finished Jul 29 06:19:28 PM PDT 24
Peak memory 207244 kb
Host smart-ded579f8-a4fa-4ee1-9321-0873666cb656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31214
80634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.3121480634
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3029850115
Short name T1689
Test name
Test status
Simulation time 4843960692 ps
CPU time 50.61 seconds
Started Jul 29 06:19:24 PM PDT 24
Finished Jul 29 06:20:15 PM PDT 24
Peak memory 216964 kb
Host smart-5261e7b1-ab89-4daa-9faf-76a9e8bfaf25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30298
50115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3029850115
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.3969495755
Short name T1644
Test name
Test status
Simulation time 1671118860 ps
CPU time 41.57 seconds
Started Jul 29 06:19:11 PM PDT 24
Finished Jul 29 06:19:52 PM PDT 24
Peak memory 207244 kb
Host smart-839daae5-7c73-45f0-a6b0-e1407755f4c1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969495755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.3969495755
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.3433362524
Short name T1769
Test name
Test status
Simulation time 71005260 ps
CPU time 0.74 seconds
Started Jul 29 06:19:38 PM PDT 24
Finished Jul 29 06:19:39 PM PDT 24
Peak memory 207008 kb
Host smart-79f56c7f-9f32-4ba8-b165-912dd35cd674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3433362524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.3433362524
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.1048139492
Short name T2286
Test name
Test status
Simulation time 13364441293 ps
CPU time 16.31 seconds
Started Jul 29 06:19:23 PM PDT 24
Finished Jul 29 06:19:40 PM PDT 24
Peak memory 207432 kb
Host smart-7f55aecb-e068-42d6-ab8a-9a50c10a39e2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048139492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.1048139492
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.52901077
Short name T2813
Test name
Test status
Simulation time 23334242350 ps
CPU time 27.52 seconds
Started Jul 29 06:19:30 PM PDT 24
Finished Jul 29 06:19:58 PM PDT 24
Peak memory 207432 kb
Host smart-87e67473-4d0e-4b3d-a03b-de5c4bde9602
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52901077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon
_wake_resume.52901077
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.4215546801
Short name T2741
Test name
Test status
Simulation time 157640473 ps
CPU time 0.87 seconds
Started Jul 29 06:19:35 PM PDT 24
Finished Jul 29 06:19:36 PM PDT 24
Peak memory 207040 kb
Host smart-3495b677-4cf9-429b-a64f-3508f050c721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42155
46801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.4215546801
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2479360838
Short name T2518
Test name
Test status
Simulation time 150188760 ps
CPU time 0.88 seconds
Started Jul 29 06:19:24 PM PDT 24
Finished Jul 29 06:19:25 PM PDT 24
Peak memory 207080 kb
Host smart-d44d686e-b95a-4c9b-a278-120a41a0abe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24793
60838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2479360838
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.2825495135
Short name T993
Test name
Test status
Simulation time 302907092 ps
CPU time 1.19 seconds
Started Jul 29 06:19:25 PM PDT 24
Finished Jul 29 06:19:27 PM PDT 24
Peak memory 207096 kb
Host smart-2a6cb8bc-f819-4fdc-8511-ffd129bacc98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28254
95135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.2825495135
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.1429473370
Short name T1386
Test name
Test status
Simulation time 1315817011 ps
CPU time 3.13 seconds
Started Jul 29 06:19:22 PM PDT 24
Finished Jul 29 06:19:26 PM PDT 24
Peak memory 207304 kb
Host smart-f07dc61b-7f02-4a58-9390-910a6200f79f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1429473370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.1429473370
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.3790020182
Short name T2138
Test name
Test status
Simulation time 19897556237 ps
CPU time 39.84 seconds
Started Jul 29 06:19:26 PM PDT 24
Finished Jul 29 06:20:06 PM PDT 24
Peak memory 207340 kb
Host smart-7533f6da-8ba2-4f32-b5ce-90ba19712991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37900
20182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.3790020182
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.2705531866
Short name T2021
Test name
Test status
Simulation time 2170425299 ps
CPU time 13.83 seconds
Started Jul 29 06:19:24 PM PDT 24
Finished Jul 29 06:19:38 PM PDT 24
Peak memory 207328 kb
Host smart-e2c560a8-1fac-4f82-8cf2-de09866cd642
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705531866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.2705531866
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.4181573419
Short name T1820
Test name
Test status
Simulation time 491103401 ps
CPU time 1.59 seconds
Started Jul 29 06:19:30 PM PDT 24
Finished Jul 29 06:19:32 PM PDT 24
Peak memory 207040 kb
Host smart-87c677cf-7a4d-44ab-863b-cebedf878e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41815
73419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.4181573419
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.2982702032
Short name T837
Test name
Test status
Simulation time 192755869 ps
CPU time 0.9 seconds
Started Jul 29 06:19:25 PM PDT 24
Finished Jul 29 06:19:26 PM PDT 24
Peak memory 207220 kb
Host smart-7d18c545-4daf-40ef-9756-f11966e54033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29827
02032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2982702032
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2134500276
Short name T722
Test name
Test status
Simulation time 52623043 ps
CPU time 0.74 seconds
Started Jul 29 06:19:25 PM PDT 24
Finished Jul 29 06:19:25 PM PDT 24
Peak memory 207084 kb
Host smart-057304a2-7a6e-479d-bbe7-bfb2caba11a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21345
00276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2134500276
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3426004073
Short name T691
Test name
Test status
Simulation time 841791891 ps
CPU time 2.23 seconds
Started Jul 29 06:19:26 PM PDT 24
Finished Jul 29 06:19:28 PM PDT 24
Peak memory 207296 kb
Host smart-3b5ae88d-360a-4010-bfed-0a30cbe75122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34260
04073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3426004073
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1851100406
Short name T2747
Test name
Test status
Simulation time 198819042 ps
CPU time 1.41 seconds
Started Jul 29 06:19:29 PM PDT 24
Finished Jul 29 06:19:31 PM PDT 24
Peak memory 207212 kb
Host smart-e0b3f941-ab86-43c2-b202-0eacbdba8741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18511
00406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1851100406
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.112890413
Short name T100
Test name
Test status
Simulation time 229669554 ps
CPU time 1.22 seconds
Started Jul 29 06:19:25 PM PDT 24
Finished Jul 29 06:19:27 PM PDT 24
Peak memory 215428 kb
Host smart-9cc4d626-2a64-444d-a510-3a98751f6a06
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=112890413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.112890413
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.378231933
Short name T668
Test name
Test status
Simulation time 156954082 ps
CPU time 0.83 seconds
Started Jul 29 06:19:24 PM PDT 24
Finished Jul 29 06:19:25 PM PDT 24
Peak memory 207040 kb
Host smart-d586c1e2-c1e1-4cdb-9669-75ca2756522d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37823
1933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.378231933
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.499681263
Short name T782
Test name
Test status
Simulation time 186806354 ps
CPU time 0.92 seconds
Started Jul 29 06:19:25 PM PDT 24
Finished Jul 29 06:19:27 PM PDT 24
Peak memory 207036 kb
Host smart-ddaecf09-4e13-45b1-989d-afbf6e45bfab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49968
1263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.499681263
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.641329101
Short name T2478
Test name
Test status
Simulation time 7193744463 ps
CPU time 208.23 seconds
Started Jul 29 06:19:30 PM PDT 24
Finished Jul 29 06:22:59 PM PDT 24
Peak memory 215528 kb
Host smart-e35ad10f-9a35-4029-a6b5-7d93ae4bb03c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=641329101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.641329101
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.1607854324
Short name T2333
Test name
Test status
Simulation time 12398501362 ps
CPU time 149.02 seconds
Started Jul 29 06:19:25 PM PDT 24
Finished Jul 29 06:21:55 PM PDT 24
Peak memory 207352 kb
Host smart-53f4dc16-423f-4d8e-80bd-161078d5776b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1607854324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.1607854324
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3555839195
Short name T2584
Test name
Test status
Simulation time 190006215 ps
CPU time 0.92 seconds
Started Jul 29 06:19:26 PM PDT 24
Finished Jul 29 06:19:27 PM PDT 24
Peak memory 207048 kb
Host smart-e20e430b-98af-4867-9287-9953ef11a623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35558
39195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3555839195
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.4138486552
Short name T1761
Test name
Test status
Simulation time 23298630301 ps
CPU time 28.28 seconds
Started Jul 29 06:19:24 PM PDT 24
Finished Jul 29 06:19:52 PM PDT 24
Peak memory 207412 kb
Host smart-df759ea5-9b4f-4944-b176-3ee31e13e33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41384
86552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.4138486552
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3610276182
Short name T1596
Test name
Test status
Simulation time 3355326453 ps
CPU time 5.25 seconds
Started Jul 29 06:19:24 PM PDT 24
Finished Jul 29 06:19:30 PM PDT 24
Peak memory 207384 kb
Host smart-6c9725f3-2d59-4f88-b5b8-7f6c28ffdc8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36102
76182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3610276182
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.3583788204
Short name T1049
Test name
Test status
Simulation time 6523010903 ps
CPU time 48.63 seconds
Started Jul 29 06:19:22 PM PDT 24
Finished Jul 29 06:20:11 PM PDT 24
Peak memory 223832 kb
Host smart-35fda4bf-f12f-43d9-8dfc-3db6dce17f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35837
88204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.3583788204
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.20329884
Short name T879
Test name
Test status
Simulation time 5125652099 ps
CPU time 39.61 seconds
Started Jul 29 06:19:30 PM PDT 24
Finished Jul 29 06:20:09 PM PDT 24
Peak memory 215620 kb
Host smart-658b4bb8-988d-4db5-bff4-3d90e89673d2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=20329884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.20329884
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.1471003705
Short name T2150
Test name
Test status
Simulation time 250999469 ps
CPU time 1.02 seconds
Started Jul 29 06:19:35 PM PDT 24
Finished Jul 29 06:19:36 PM PDT 24
Peak memory 207076 kb
Host smart-192c4c8b-30a3-425b-8247-275ce4e634d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1471003705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.1471003705
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.934066807
Short name T327
Test name
Test status
Simulation time 196846841 ps
CPU time 0.96 seconds
Started Jul 29 06:19:32 PM PDT 24
Finished Jul 29 06:19:34 PM PDT 24
Peak memory 207104 kb
Host smart-6e62bc8f-164d-4bd8-95c5-56f2b0244aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93406
6807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.934066807
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.4015685397
Short name T696
Test name
Test status
Simulation time 4826917781 ps
CPU time 49.45 seconds
Started Jul 29 06:19:26 PM PDT 24
Finished Jul 29 06:20:16 PM PDT 24
Peak memory 217192 kb
Host smart-8919bd1d-43c3-4ffb-905f-b6bca81f0c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40156
85397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.4015685397
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.1376979262
Short name T1742
Test name
Test status
Simulation time 5749113369 ps
CPU time 50.5 seconds
Started Jul 29 06:19:28 PM PDT 24
Finished Jul 29 06:20:19 PM PDT 24
Peak memory 207476 kb
Host smart-531cb044-ff99-4715-8040-481722c3bc22
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1376979262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.1376979262
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.3069415336
Short name T2276
Test name
Test status
Simulation time 205773782 ps
CPU time 0.97 seconds
Started Jul 29 06:19:27 PM PDT 24
Finished Jul 29 06:19:28 PM PDT 24
Peak memory 207104 kb
Host smart-d88ffb96-22c9-4ed9-8a4e-0de81099e108
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3069415336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.3069415336
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.589014211
Short name T317
Test name
Test status
Simulation time 214756955 ps
CPU time 0.92 seconds
Started Jul 29 06:19:27 PM PDT 24
Finished Jul 29 06:19:28 PM PDT 24
Peak memory 207104 kb
Host smart-dd8935fb-58e3-4a10-ba2e-9863bed20f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58901
4211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.589014211
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2663971961
Short name T128
Test name
Test status
Simulation time 191532541 ps
CPU time 0.89 seconds
Started Jul 29 06:19:29 PM PDT 24
Finished Jul 29 06:19:30 PM PDT 24
Peak memory 207092 kb
Host smart-3e4d9043-6dea-4ea1-b8e6-925c1c1de8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26639
71961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2663971961
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.3258222004
Short name T1242
Test name
Test status
Simulation time 148689746 ps
CPU time 0.89 seconds
Started Jul 29 06:19:37 PM PDT 24
Finished Jul 29 06:19:38 PM PDT 24
Peak memory 207120 kb
Host smart-2f2e2bfe-0201-43f3-bfdf-bd0b01dfc7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32582
22004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.3258222004
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.886538213
Short name T2172
Test name
Test status
Simulation time 165137162 ps
CPU time 0.86 seconds
Started Jul 29 06:19:27 PM PDT 24
Finished Jul 29 06:19:28 PM PDT 24
Peak memory 207084 kb
Host smart-f7fc3c2c-fe46-41b4-8282-12d3fc18f867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88653
8213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.886538213
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3347661224
Short name T2515
Test name
Test status
Simulation time 194008294 ps
CPU time 0.94 seconds
Started Jul 29 06:19:32 PM PDT 24
Finished Jul 29 06:19:33 PM PDT 24
Peak memory 207112 kb
Host smart-7c9ca327-1b0d-491c-a7b8-ac00fae4cfa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33476
61224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3347661224
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3862784536
Short name T572
Test name
Test status
Simulation time 146294139 ps
CPU time 0.82 seconds
Started Jul 29 06:19:29 PM PDT 24
Finished Jul 29 06:19:30 PM PDT 24
Peak memory 207096 kb
Host smart-47410f21-3f31-4df2-b350-63914b601181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38627
84536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3862784536
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3095102159
Short name T479
Test name
Test status
Simulation time 247427206 ps
CPU time 1 seconds
Started Jul 29 06:19:27 PM PDT 24
Finished Jul 29 06:19:28 PM PDT 24
Peak memory 207032 kb
Host smart-2a5529d9-efd7-4742-95d2-dff0acabc682
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3095102159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3095102159
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3210028522
Short name T392
Test name
Test status
Simulation time 184644015 ps
CPU time 0.86 seconds
Started Jul 29 06:19:34 PM PDT 24
Finished Jul 29 06:19:35 PM PDT 24
Peak memory 207072 kb
Host smart-e368c5bc-3a18-4453-b513-55ba6f46592d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32100
28522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3210028522
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2967032376
Short name T27
Test name
Test status
Simulation time 77064838 ps
CPU time 0.74 seconds
Started Jul 29 06:19:34 PM PDT 24
Finished Jul 29 06:19:36 PM PDT 24
Peak memory 207048 kb
Host smart-74d5e9c1-4f23-4314-8eeb-8ef73e23bbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29670
32376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2967032376
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3501333391
Short name T1765
Test name
Test status
Simulation time 13059720173 ps
CPU time 33.67 seconds
Started Jul 29 06:19:28 PM PDT 24
Finished Jul 29 06:20:02 PM PDT 24
Peak memory 223800 kb
Host smart-22a5aeb6-f2e0-4487-8120-6dcf3dcda04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35013
33391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3501333391
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3232900583
Short name T2053
Test name
Test status
Simulation time 161712865 ps
CPU time 0.88 seconds
Started Jul 29 06:19:41 PM PDT 24
Finished Jul 29 06:19:42 PM PDT 24
Peak memory 207092 kb
Host smart-48a3cf48-44bd-4043-9f24-c52ddde1471a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32329
00583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3232900583
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1251470983
Short name T2535
Test name
Test status
Simulation time 178392416 ps
CPU time 0.89 seconds
Started Jul 29 06:19:33 PM PDT 24
Finished Jul 29 06:19:34 PM PDT 24
Peak memory 207112 kb
Host smart-c5f17510-0437-440c-aa9f-01b6e89fc31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12514
70983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1251470983
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.4186221469
Short name T420
Test name
Test status
Simulation time 201623256 ps
CPU time 0.98 seconds
Started Jul 29 06:19:31 PM PDT 24
Finished Jul 29 06:19:32 PM PDT 24
Peak memory 207188 kb
Host smart-cc6024ba-b594-494c-8e60-dfb40cdff89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41862
21469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.4186221469
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.1611844655
Short name T1373
Test name
Test status
Simulation time 163203477 ps
CPU time 0.86 seconds
Started Jul 29 06:19:36 PM PDT 24
Finished Jul 29 06:19:37 PM PDT 24
Peak memory 207076 kb
Host smart-08a892a3-d670-4b8a-83d5-3406590d401c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16118
44655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.1611844655
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.1834414414
Short name T1027
Test name
Test status
Simulation time 140978300 ps
CPU time 0.81 seconds
Started Jul 29 06:19:36 PM PDT 24
Finished Jul 29 06:19:37 PM PDT 24
Peak memory 207032 kb
Host smart-dd1a931d-3ec0-48ee-86bb-84f19ae74b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18344
14414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.1834414414
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.3968445920
Short name T99
Test name
Test status
Simulation time 199745664 ps
CPU time 0.9 seconds
Started Jul 29 06:19:32 PM PDT 24
Finished Jul 29 06:19:33 PM PDT 24
Peak memory 207156 kb
Host smart-5226344e-412f-4d80-afdb-a1adbdc6acc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39684
45920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3968445920
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3638594503
Short name T2415
Test name
Test status
Simulation time 145512258 ps
CPU time 0.83 seconds
Started Jul 29 06:19:34 PM PDT 24
Finished Jul 29 06:19:35 PM PDT 24
Peak memory 207132 kb
Host smart-b212041e-e6a1-4583-ada5-de0cbcbad89a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36385
94503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3638594503
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2753890329
Short name T1793
Test name
Test status
Simulation time 215945017 ps
CPU time 0.95 seconds
Started Jul 29 06:19:33 PM PDT 24
Finished Jul 29 06:19:34 PM PDT 24
Peak memory 206980 kb
Host smart-8819916e-6109-400d-b926-656fafffcef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27538
90329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2753890329
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.3078889113
Short name T1587
Test name
Test status
Simulation time 6054090975 ps
CPU time 63.41 seconds
Started Jul 29 06:19:37 PM PDT 24
Finished Jul 29 06:20:41 PM PDT 24
Peak memory 217284 kb
Host smart-886a0c84-5660-4204-921a-7bfe0f8e7e93
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3078889113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.3078889113
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.710248540
Short name T428
Test name
Test status
Simulation time 186373038 ps
CPU time 0.91 seconds
Started Jul 29 06:19:30 PM PDT 24
Finished Jul 29 06:19:31 PM PDT 24
Peak memory 207104 kb
Host smart-17105d7c-dcc3-4d26-ad56-2c5c822c82ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71024
8540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.710248540
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1618342092
Short name T765
Test name
Test status
Simulation time 152057429 ps
CPU time 0.85 seconds
Started Jul 29 06:19:30 PM PDT 24
Finished Jul 29 06:19:31 PM PDT 24
Peak memory 207108 kb
Host smart-063dae55-98f8-4164-936d-edec7ea440d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16183
42092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1618342092
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.3508129321
Short name T1301
Test name
Test status
Simulation time 377164303 ps
CPU time 1.21 seconds
Started Jul 29 06:19:36 PM PDT 24
Finished Jul 29 06:19:37 PM PDT 24
Peak memory 207156 kb
Host smart-44cf61ad-6284-4c90-a1c8-ace606f1f864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35081
29321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.3508129321
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.3041093061
Short name T2253
Test name
Test status
Simulation time 3958980462 ps
CPU time 116.91 seconds
Started Jul 29 06:19:36 PM PDT 24
Finished Jul 29 06:21:33 PM PDT 24
Peak memory 215452 kb
Host smart-b284b42e-71ad-45ae-bdc4-56092280b1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30410
93061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.3041093061
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.1315109285
Short name T2334
Test name
Test status
Simulation time 2995006364 ps
CPU time 19.64 seconds
Started Jul 29 06:19:24 PM PDT 24
Finished Jul 29 06:19:44 PM PDT 24
Peak memory 207372 kb
Host smart-fb198059-8ea5-4a89-ab6b-44a6d5b4844a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315109285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.1315109285
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.3455857073
Short name T939
Test name
Test status
Simulation time 38369333 ps
CPU time 0.66 seconds
Started Jul 29 06:12:06 PM PDT 24
Finished Jul 29 06:12:07 PM PDT 24
Peak memory 207140 kb
Host smart-08f49e87-a6b0-4ba5-add3-da6fc4c31a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3455857073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3455857073
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.705191487
Short name T15
Test name
Test status
Simulation time 4247548552 ps
CPU time 6.15 seconds
Started Jul 29 06:11:52 PM PDT 24
Finished Jul 29 06:11:59 PM PDT 24
Peak memory 207332 kb
Host smart-3dfbee51-f436-4489-83ff-34d6e19e12bc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705191487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon
_wake_disconnect.705191487
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2044081552
Short name T198
Test name
Test status
Simulation time 13399907811 ps
CPU time 15.18 seconds
Started Jul 29 06:11:49 PM PDT 24
Finished Jul 29 06:12:04 PM PDT 24
Peak memory 207424 kb
Host smart-fa3970d4-0a74-4e99-ada5-4eaca6185410
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044081552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2044081552
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2015234874
Short name T2708
Test name
Test status
Simulation time 23367613812 ps
CPU time 27.84 seconds
Started Jul 29 06:11:46 PM PDT 24
Finished Jul 29 06:12:14 PM PDT 24
Peak memory 207432 kb
Host smart-6fa38ed8-2535-4078-a419-a23d6db771cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015234874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.2015234874
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2838717862
Short name T1236
Test name
Test status
Simulation time 228518163 ps
CPU time 0.97 seconds
Started Jul 29 06:11:45 PM PDT 24
Finished Jul 29 06:11:46 PM PDT 24
Peak memory 207060 kb
Host smart-ded9617c-ff28-41de-b779-e06641cebfd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28387
17862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2838717862
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3323407899
Short name T1056
Test name
Test status
Simulation time 173544248 ps
CPU time 0.91 seconds
Started Jul 29 06:11:50 PM PDT 24
Finished Jul 29 06:11:51 PM PDT 24
Peak memory 207060 kb
Host smart-d1d6cfb9-6ec1-4292-bf6a-fe3a69c2bb4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33234
07899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3323407899
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.3584475530
Short name T919
Test name
Test status
Simulation time 236050150 ps
CPU time 1.14 seconds
Started Jul 29 06:11:46 PM PDT 24
Finished Jul 29 06:11:47 PM PDT 24
Peak memory 207136 kb
Host smart-d2487c0e-ec53-49dd-85df-85d16d887378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35844
75530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.3584475530
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.4017601697
Short name T1494
Test name
Test status
Simulation time 1337907284 ps
CPU time 3.28 seconds
Started Jul 29 06:11:46 PM PDT 24
Finished Jul 29 06:11:49 PM PDT 24
Peak memory 207260 kb
Host smart-537cefec-bab4-45bd-a473-edc64321253c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4017601697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.4017601697
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.1655067300
Short name T1901
Test name
Test status
Simulation time 8791746775 ps
CPU time 16.96 seconds
Started Jul 29 06:11:49 PM PDT 24
Finished Jul 29 06:12:06 PM PDT 24
Peak memory 207380 kb
Host smart-e2317ae3-ed5f-45ee-85a2-40dece886cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16550
67300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1655067300
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.1323588086
Short name T1268
Test name
Test status
Simulation time 4999725852 ps
CPU time 31.93 seconds
Started Jul 29 06:11:46 PM PDT 24
Finished Jul 29 06:12:18 PM PDT 24
Peak memory 207348 kb
Host smart-dc6a565d-758b-4557-962c-a2650ec629ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323588086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.1323588086
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.1468280163
Short name T738
Test name
Test status
Simulation time 311977041 ps
CPU time 1.21 seconds
Started Jul 29 06:11:45 PM PDT 24
Finished Jul 29 06:11:46 PM PDT 24
Peak memory 207048 kb
Host smart-edcd61cb-e2d0-4324-821f-26d3e505f8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14682
80163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.1468280163
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.678655655
Short name T1941
Test name
Test status
Simulation time 146792804 ps
CPU time 0.79 seconds
Started Jul 29 06:11:45 PM PDT 24
Finished Jul 29 06:11:46 PM PDT 24
Peak memory 207076 kb
Host smart-0915e875-32cb-4108-b6ed-4d990cfdb79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67865
5655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.678655655
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.3060620226
Short name T2141
Test name
Test status
Simulation time 33889955 ps
CPU time 0.69 seconds
Started Jul 29 06:11:49 PM PDT 24
Finished Jul 29 06:11:49 PM PDT 24
Peak memory 207064 kb
Host smart-16842007-3b66-4179-a6a9-eeaec43687c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30606
20226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.3060620226
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1703471054
Short name T2795
Test name
Test status
Simulation time 761642761 ps
CPU time 1.97 seconds
Started Jul 29 06:11:44 PM PDT 24
Finished Jul 29 06:11:46 PM PDT 24
Peak memory 207236 kb
Host smart-34282ede-e710-4351-9a99-b6fc09e65543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17034
71054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1703471054
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1910806106
Short name T2472
Test name
Test status
Simulation time 174817679 ps
CPU time 1.45 seconds
Started Jul 29 06:11:47 PM PDT 24
Finished Jul 29 06:11:48 PM PDT 24
Peak memory 207252 kb
Host smart-55e2b556-f7a6-41bd-b3ac-dc8b855c4b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19108
06106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1910806106
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3850408487
Short name T1030
Test name
Test status
Simulation time 161461045 ps
CPU time 0.87 seconds
Started Jul 29 06:11:46 PM PDT 24
Finished Jul 29 06:11:47 PM PDT 24
Peak memory 207100 kb
Host smart-106c5dfd-a652-4eb9-b24d-2ddbe5b4f0bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3850408487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3850408487
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2608631393
Short name T893
Test name
Test status
Simulation time 143179387 ps
CPU time 0.82 seconds
Started Jul 29 06:11:52 PM PDT 24
Finished Jul 29 06:11:53 PM PDT 24
Peak memory 207044 kb
Host smart-35411fd8-f258-4f10-84a5-f8e1e1ae0c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26086
31393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2608631393
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2537624564
Short name T541
Test name
Test status
Simulation time 235783286 ps
CPU time 1.05 seconds
Started Jul 29 06:11:45 PM PDT 24
Finished Jul 29 06:11:46 PM PDT 24
Peak memory 207056 kb
Host smart-f6da776f-a400-4b70-a2d3-1efd6967faa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25376
24564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2537624564
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.1750845721
Short name T2729
Test name
Test status
Simulation time 5694290590 ps
CPU time 155.35 seconds
Started Jul 29 06:11:46 PM PDT 24
Finished Jul 29 06:14:22 PM PDT 24
Peak memory 215624 kb
Host smart-bda71c36-834c-44fb-9b04-8d669cf92eb1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1750845721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.1750845721
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.308701401
Short name T402
Test name
Test status
Simulation time 4568525490 ps
CPU time 30.8 seconds
Started Jul 29 06:11:45 PM PDT 24
Finished Jul 29 06:12:16 PM PDT 24
Peak memory 207392 kb
Host smart-d7ad0926-2c4a-43a2-beea-5899f6189d34
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=308701401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.308701401
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1314500557
Short name T1588
Test name
Test status
Simulation time 220529798 ps
CPU time 0.97 seconds
Started Jul 29 06:11:46 PM PDT 24
Finished Jul 29 06:11:47 PM PDT 24
Peak memory 207104 kb
Host smart-334fce73-22a2-4336-adea-800e379aa70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13145
00557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1314500557
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.2942908565
Short name T2145
Test name
Test status
Simulation time 23273666297 ps
CPU time 28.21 seconds
Started Jul 29 06:11:44 PM PDT 24
Finished Jul 29 06:12:12 PM PDT 24
Peak memory 207412 kb
Host smart-078e539f-36c9-49a1-b3ee-654bf3ba65b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29429
08565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.2942908565
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2703226677
Short name T908
Test name
Test status
Simulation time 3332825602 ps
CPU time 5.85 seconds
Started Jul 29 06:11:48 PM PDT 24
Finished Jul 29 06:11:54 PM PDT 24
Peak memory 207224 kb
Host smart-d3c6a37e-b8cd-47d0-9ba6-78dc89eacf17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27032
26677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2703226677
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3077728566
Short name T2134
Test name
Test status
Simulation time 7470620959 ps
CPU time 221.55 seconds
Started Jul 29 06:11:46 PM PDT 24
Finished Jul 29 06:15:28 PM PDT 24
Peak memory 215564 kb
Host smart-da9d068c-57cc-47f5-953c-31c4a50f061b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30777
28566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3077728566
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3081481900
Short name T1575
Test name
Test status
Simulation time 2714232444 ps
CPU time 27 seconds
Started Jul 29 06:11:51 PM PDT 24
Finished Jul 29 06:12:18 PM PDT 24
Peak memory 216932 kb
Host smart-eaa8906b-d7a8-4c8e-a89f-85a10945cff5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3081481900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3081481900
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2002099169
Short name T1890
Test name
Test status
Simulation time 245723475 ps
CPU time 1 seconds
Started Jul 29 06:11:52 PM PDT 24
Finished Jul 29 06:11:53 PM PDT 24
Peak memory 206988 kb
Host smart-6cecd415-554a-48d8-ac6e-fb64aba9525b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2002099169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2002099169
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3541632178
Short name T2411
Test name
Test status
Simulation time 236034824 ps
CPU time 1 seconds
Started Jul 29 06:11:52 PM PDT 24
Finished Jul 29 06:11:53 PM PDT 24
Peak memory 207068 kb
Host smart-074ebb48-43b4-462a-a7f9-57aa474613c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35416
32178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3541632178
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1840378367
Short name T1861
Test name
Test status
Simulation time 4014102408 ps
CPU time 121.4 seconds
Started Jul 29 06:11:51 PM PDT 24
Finished Jul 29 06:13:53 PM PDT 24
Peak memory 215488 kb
Host smart-b0e7664f-a623-4282-b4d2-277ea6212e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18403
78367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1840378367
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.585848073
Short name T2106
Test name
Test status
Simulation time 3873913932 ps
CPU time 38.87 seconds
Started Jul 29 06:11:56 PM PDT 24
Finished Jul 29 06:12:35 PM PDT 24
Peak memory 207336 kb
Host smart-1ae8e494-7827-4dde-8c54-c01e7e41cf03
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=585848073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.585848073
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.3248148845
Short name T1396
Test name
Test status
Simulation time 186872153 ps
CPU time 0.87 seconds
Started Jul 29 06:11:51 PM PDT 24
Finished Jul 29 06:11:52 PM PDT 24
Peak memory 207148 kb
Host smart-65e9eab6-3272-4fea-aced-555b4c2d3ab2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3248148845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.3248148845
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2789587567
Short name T1426
Test name
Test status
Simulation time 167348723 ps
CPU time 0.93 seconds
Started Jul 29 06:11:53 PM PDT 24
Finished Jul 29 06:11:54 PM PDT 24
Peak memory 207100 kb
Host smart-67b85572-2f17-4275-af23-c0811c5148d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27895
87567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2789587567
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3203685631
Short name T2191
Test name
Test status
Simulation time 204876917 ps
CPU time 0.89 seconds
Started Jul 29 06:11:52 PM PDT 24
Finished Jul 29 06:11:53 PM PDT 24
Peak memory 207024 kb
Host smart-bec2c9aa-5ba8-4db7-8af3-9f312f794bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32036
85631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3203685631
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.1281429788
Short name T347
Test name
Test status
Simulation time 234760941 ps
CPU time 0.98 seconds
Started Jul 29 06:11:52 PM PDT 24
Finished Jul 29 06:11:53 PM PDT 24
Peak memory 207100 kb
Host smart-908d1ef6-a36c-428e-ad91-f83fcc6b938b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12814
29788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.1281429788
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3696292765
Short name T2196
Test name
Test status
Simulation time 200880978 ps
CPU time 0.94 seconds
Started Jul 29 06:11:52 PM PDT 24
Finished Jul 29 06:11:53 PM PDT 24
Peak memory 207136 kb
Host smart-fe1ab707-bc2d-4f3a-ae9f-67cd50051464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36962
92765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3696292765
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3053066505
Short name T526
Test name
Test status
Simulation time 157887672 ps
CPU time 0.8 seconds
Started Jul 29 06:11:56 PM PDT 24
Finished Jul 29 06:11:57 PM PDT 24
Peak memory 207064 kb
Host smart-6d8b8ed1-b456-4730-9f0d-b2e363012365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30530
66505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3053066505
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.142607087
Short name T1358
Test name
Test status
Simulation time 159794099 ps
CPU time 0.87 seconds
Started Jul 29 06:11:52 PM PDT 24
Finished Jul 29 06:11:53 PM PDT 24
Peak memory 207092 kb
Host smart-bd76b54e-ad7b-4d08-8590-8c25b8f93fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14260
7087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.142607087
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.478278605
Short name T964
Test name
Test status
Simulation time 224485950 ps
CPU time 1.06 seconds
Started Jul 29 06:11:53 PM PDT 24
Finished Jul 29 06:11:54 PM PDT 24
Peak memory 207120 kb
Host smart-633c3b48-f996-439e-8b13-8a0e48614cf1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=478278605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.478278605
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.729097830
Short name T1721
Test name
Test status
Simulation time 169123047 ps
CPU time 0.9 seconds
Started Jul 29 06:11:53 PM PDT 24
Finished Jul 29 06:11:54 PM PDT 24
Peak memory 207092 kb
Host smart-87cb9362-fb63-4d49-a8fe-97e764598bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72909
7830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.729097830
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.555317250
Short name T2462
Test name
Test status
Simulation time 27129935 ps
CPU time 0.71 seconds
Started Jul 29 06:11:54 PM PDT 24
Finished Jul 29 06:11:55 PM PDT 24
Peak memory 207068 kb
Host smart-74af939e-5f3a-4673-91a8-d207e8da8334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55531
7250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.555317250
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.197565852
Short name T619
Test name
Test status
Simulation time 11079822736 ps
CPU time 27.07 seconds
Started Jul 29 06:11:56 PM PDT 24
Finished Jul 29 06:12:23 PM PDT 24
Peak memory 215584 kb
Host smart-19be6069-07f2-426a-b8f0-a9dbba1dbdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19756
5852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.197565852
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2397013673
Short name T644
Test name
Test status
Simulation time 170389933 ps
CPU time 0.91 seconds
Started Jul 29 06:11:54 PM PDT 24
Finished Jul 29 06:11:55 PM PDT 24
Peak memory 207100 kb
Host smart-01bed890-4533-48c9-8651-3d3a060148d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23970
13673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2397013673
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2295894119
Short name T1442
Test name
Test status
Simulation time 274927540 ps
CPU time 1.07 seconds
Started Jul 29 06:11:55 PM PDT 24
Finished Jul 29 06:11:57 PM PDT 24
Peak memory 207080 kb
Host smart-b51005b1-9280-49fc-ac56-61ddf6abf66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22958
94119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2295894119
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1120381809
Short name T1920
Test name
Test status
Simulation time 12040944662 ps
CPU time 113 seconds
Started Jul 29 06:11:51 PM PDT 24
Finished Jul 29 06:13:44 PM PDT 24
Peak memory 217540 kb
Host smart-b8599fcb-5676-46f8-9c99-46ad1f84fa3f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120381809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1120381809
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.1893708284
Short name T187
Test name
Test status
Simulation time 16650959546 ps
CPU time 109.57 seconds
Started Jul 29 06:11:57 PM PDT 24
Finished Jul 29 06:13:47 PM PDT 24
Peak memory 217708 kb
Host smart-c86dd9a1-3353-4311-a70a-b55504445cf7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893708284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.1893708284
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.1069548286
Short name T881
Test name
Test status
Simulation time 234209001 ps
CPU time 1.05 seconds
Started Jul 29 06:11:52 PM PDT 24
Finished Jul 29 06:11:53 PM PDT 24
Peak memory 207060 kb
Host smart-ca359b60-6745-4751-bef3-94f3f10ecf90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10695
48286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.1069548286
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.972844496
Short name T2443
Test name
Test status
Simulation time 186017080 ps
CPU time 0.95 seconds
Started Jul 29 06:11:51 PM PDT 24
Finished Jul 29 06:11:52 PM PDT 24
Peak memory 207068 kb
Host smart-ff28213b-b3ca-4c49-aff7-01c1153ba6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97284
4496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.972844496
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2500383698
Short name T1824
Test name
Test status
Simulation time 144894395 ps
CPU time 0.82 seconds
Started Jul 29 06:12:01 PM PDT 24
Finished Jul 29 06:12:02 PM PDT 24
Peak memory 207104 kb
Host smart-1384d37a-752d-41f7-b2ea-ddb2cb3d7840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25003
83698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2500383698
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1528569083
Short name T1380
Test name
Test status
Simulation time 177185191 ps
CPU time 0.9 seconds
Started Jul 29 06:11:58 PM PDT 24
Finished Jul 29 06:11:59 PM PDT 24
Peak memory 207048 kb
Host smart-2a2ec3af-5fdf-498d-908a-64909a49463c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15285
69083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1528569083
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.2432436155
Short name T2660
Test name
Test status
Simulation time 150511275 ps
CPU time 0.89 seconds
Started Jul 29 06:12:03 PM PDT 24
Finished Jul 29 06:12:04 PM PDT 24
Peak memory 207080 kb
Host smart-0d35a69e-ec04-4d81-8f36-d8166d31e030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24324
36155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.2432436155
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.56217961
Short name T1648
Test name
Test status
Simulation time 227833739 ps
CPU time 0.99 seconds
Started Jul 29 06:11:59 PM PDT 24
Finished Jul 29 06:12:00 PM PDT 24
Peak memory 207020 kb
Host smart-827a14ea-558e-420d-a9a0-7736e927bddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56217
961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.56217961
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.485398766
Short name T490
Test name
Test status
Simulation time 4038556159 ps
CPU time 112.16 seconds
Started Jul 29 06:12:00 PM PDT 24
Finished Jul 29 06:13:52 PM PDT 24
Peak memory 215568 kb
Host smart-1576dc47-745b-4a8e-8dd4-d0c52c59ebf8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=485398766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.485398766
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.4276569082
Short name T627
Test name
Test status
Simulation time 171695346 ps
CPU time 0.91 seconds
Started Jul 29 06:12:01 PM PDT 24
Finished Jul 29 06:12:02 PM PDT 24
Peak memory 207120 kb
Host smart-f0c97a30-82eb-474e-9efc-b25d13d426b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42765
69082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.4276569082
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1872288975
Short name T922
Test name
Test status
Simulation time 173059960 ps
CPU time 0.9 seconds
Started Jul 29 06:11:58 PM PDT 24
Finished Jul 29 06:11:59 PM PDT 24
Peak memory 207068 kb
Host smart-70cca177-1bfc-4fbc-b16a-c5563236a180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18722
88975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1872288975
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.3225203685
Short name T464
Test name
Test status
Simulation time 261598876 ps
CPU time 1.1 seconds
Started Jul 29 06:12:06 PM PDT 24
Finished Jul 29 06:12:07 PM PDT 24
Peak memory 207088 kb
Host smart-cd5de367-f892-4e8b-902d-adaccbba96f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32252
03685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.3225203685
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1615342829
Short name T18
Test name
Test status
Simulation time 5984132846 ps
CPU time 166.67 seconds
Started Jul 29 06:12:06 PM PDT 24
Finished Jul 29 06:14:53 PM PDT 24
Peak memory 215612 kb
Host smart-2a9377de-36d7-4a52-b975-c351585a2808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16153
42829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1615342829
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.3569719012
Short name T835
Test name
Test status
Simulation time 1194158845 ps
CPU time 26.22 seconds
Started Jul 29 06:11:52 PM PDT 24
Finished Jul 29 06:12:19 PM PDT 24
Peak memory 207328 kb
Host smart-e9ac846a-36fe-4906-a186-f404d1ecbc83
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569719012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.3569719012
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.677483656
Short name T1361
Test name
Test status
Simulation time 45859506 ps
CPU time 0.68 seconds
Started Jul 29 06:12:11 PM PDT 24
Finished Jul 29 06:12:12 PM PDT 24
Peak memory 207200 kb
Host smart-df853feb-0d68-4e5f-bcc1-c226929da7df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=677483656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.677483656
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.4061460404
Short name T2194
Test name
Test status
Simulation time 4256896874 ps
CPU time 6.03 seconds
Started Jul 29 06:11:58 PM PDT 24
Finished Jul 29 06:12:05 PM PDT 24
Peak memory 207348 kb
Host smart-e0796fde-43a3-42a3-99a9-a79510b6027b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061460404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.4061460404
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.1258773835
Short name T2288
Test name
Test status
Simulation time 13435319881 ps
CPU time 19.56 seconds
Started Jul 29 06:12:06 PM PDT 24
Finished Jul 29 06:12:26 PM PDT 24
Peak memory 207420 kb
Host smart-7f5ef593-fed9-422a-bc0c-9d69ee71ba33
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258773835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.1258773835
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.1671832023
Short name T1805
Test name
Test status
Simulation time 23320973538 ps
CPU time 28.08 seconds
Started Jul 29 06:11:57 PM PDT 24
Finished Jul 29 06:12:25 PM PDT 24
Peak memory 207576 kb
Host smart-0a4528aa-88b6-4945-b401-0f1fc5909883
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671832023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.1671832023
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3918497958
Short name T956
Test name
Test status
Simulation time 172344856 ps
CPU time 0.97 seconds
Started Jul 29 06:12:01 PM PDT 24
Finished Jul 29 06:12:02 PM PDT 24
Peak memory 207136 kb
Host smart-dc68333b-1fdb-4ffd-afa2-eea30b8a551d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39184
97958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3918497958
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.3308670153
Short name T2065
Test name
Test status
Simulation time 191756695 ps
CPU time 0.9 seconds
Started Jul 29 06:12:01 PM PDT 24
Finished Jul 29 06:12:02 PM PDT 24
Peak memory 207044 kb
Host smart-dc8f7824-e431-4fd2-ab11-cb0931015436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33086
70153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.3308670153
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.2085926643
Short name T2720
Test name
Test status
Simulation time 396301884 ps
CPU time 1.44 seconds
Started Jul 29 06:11:58 PM PDT 24
Finished Jul 29 06:11:59 PM PDT 24
Peak memory 207112 kb
Host smart-3822a0c1-e406-41eb-8f71-1a96ecbd2dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20859
26643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.2085926643
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.505944028
Short name T2526
Test name
Test status
Simulation time 1145863507 ps
CPU time 2.76 seconds
Started Jul 29 06:12:00 PM PDT 24
Finished Jul 29 06:12:03 PM PDT 24
Peak memory 207340 kb
Host smart-eabd450e-79ff-49b5-851a-212b2f6ee909
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=505944028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.505944028
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.319906781
Short name T2817
Test name
Test status
Simulation time 15840441811 ps
CPU time 37.95 seconds
Started Jul 29 06:12:02 PM PDT 24
Finished Jul 29 06:12:40 PM PDT 24
Peak memory 207380 kb
Host smart-4eb9ff71-38d8-40bb-a648-22167f219fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31990
6781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.319906781
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.89957613
Short name T2302
Test name
Test status
Simulation time 3692823008 ps
CPU time 23.76 seconds
Started Jul 29 06:11:59 PM PDT 24
Finished Jul 29 06:12:23 PM PDT 24
Peak memory 207384 kb
Host smart-84c018ea-7fa0-422e-8198-1d88b38320c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89957613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.89957613
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.2406279191
Short name T1608
Test name
Test status
Simulation time 467088547 ps
CPU time 1.55 seconds
Started Jul 29 06:12:02 PM PDT 24
Finished Jul 29 06:12:03 PM PDT 24
Peak memory 207104 kb
Host smart-97cf6013-4a38-4d2e-beab-22756b34aaf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24062
79191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.2406279191
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2251289075
Short name T831
Test name
Test status
Simulation time 171143890 ps
CPU time 0.84 seconds
Started Jul 29 06:11:59 PM PDT 24
Finished Jul 29 06:12:00 PM PDT 24
Peak memory 207020 kb
Host smart-664270ac-1d5f-434a-938a-bd99bf51d11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22512
89075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2251289075
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2626912831
Short name T483
Test name
Test status
Simulation time 46858218 ps
CPU time 0.71 seconds
Started Jul 29 06:11:57 PM PDT 24
Finished Jul 29 06:11:58 PM PDT 24
Peak memory 207004 kb
Host smart-eb8c0648-25fb-4245-9382-b3b7027a8557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26269
12831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2626912831
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1300531237
Short name T1460
Test name
Test status
Simulation time 785468493 ps
CPU time 2.21 seconds
Started Jul 29 06:11:58 PM PDT 24
Finished Jul 29 06:12:01 PM PDT 24
Peak memory 207328 kb
Host smart-b5848a32-9c57-404f-bb8a-2b31bb15fa17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13005
31237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1300531237
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3243916133
Short name T927
Test name
Test status
Simulation time 186911022 ps
CPU time 2.42 seconds
Started Jul 29 06:11:58 PM PDT 24
Finished Jul 29 06:12:01 PM PDT 24
Peak memory 207252 kb
Host smart-87dcd18d-bfa7-4d99-80c8-9b23d092c381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32439
16133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3243916133
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3188236024
Short name T1072
Test name
Test status
Simulation time 150070503 ps
CPU time 0.94 seconds
Started Jul 29 06:11:59 PM PDT 24
Finished Jul 29 06:12:00 PM PDT 24
Peak memory 207060 kb
Host smart-f6af1482-8ccc-4796-8fe3-cf28f1e8e218
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3188236024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3188236024
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1737415762
Short name T2739
Test name
Test status
Simulation time 160461642 ps
CPU time 0.82 seconds
Started Jul 29 06:11:58 PM PDT 24
Finished Jul 29 06:11:59 PM PDT 24
Peak memory 207080 kb
Host smart-22b5bcd2-cd8a-4410-9eec-ffeac63ea070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17374
15762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1737415762
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2246453965
Short name T1850
Test name
Test status
Simulation time 214136108 ps
CPU time 1.01 seconds
Started Jul 29 06:12:01 PM PDT 24
Finished Jul 29 06:12:02 PM PDT 24
Peak memory 207112 kb
Host smart-aa23266c-be6a-4b00-9719-08ed8852f6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22464
53965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2246453965
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.3339033905
Short name T542
Test name
Test status
Simulation time 7052625594 ps
CPU time 76.46 seconds
Started Jul 29 06:11:58 PM PDT 24
Finished Jul 29 06:13:15 PM PDT 24
Peak memory 215552 kb
Host smart-53ad82ae-91d9-46b3-a864-ab02557bc46e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3339033905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.3339033905
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.1516771759
Short name T1899
Test name
Test status
Simulation time 11836457031 ps
CPU time 70.62 seconds
Started Jul 29 06:11:58 PM PDT 24
Finished Jul 29 06:13:08 PM PDT 24
Peak memory 207320 kb
Host smart-be847b68-aed6-4551-98dc-8c1b193f55b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1516771759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.1516771759
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.1444199085
Short name T1308
Test name
Test status
Simulation time 185497144 ps
CPU time 0.87 seconds
Started Jul 29 06:11:59 PM PDT 24
Finished Jul 29 06:12:00 PM PDT 24
Peak memory 207020 kb
Host smart-f93346e4-154a-4df4-8273-712207615cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14441
99085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.1444199085
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.3427718874
Short name T833
Test name
Test status
Simulation time 23310042071 ps
CPU time 30.76 seconds
Started Jul 29 06:11:56 PM PDT 24
Finished Jul 29 06:12:27 PM PDT 24
Peak memory 207348 kb
Host smart-9cccc735-db0f-43e0-ad68-2a1acbbae4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34277
18874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.3427718874
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3395789987
Short name T447
Test name
Test status
Simulation time 3294957548 ps
CPU time 4.46 seconds
Started Jul 29 06:11:59 PM PDT 24
Finished Jul 29 06:12:04 PM PDT 24
Peak memory 207356 kb
Host smart-0d2a56b6-ba94-400c-9fe2-fc71afc76148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33957
89987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3395789987
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2808285827
Short name T2710
Test name
Test status
Simulation time 7233349875 ps
CPU time 221.85 seconds
Started Jul 29 06:12:07 PM PDT 24
Finished Jul 29 06:15:49 PM PDT 24
Peak memory 223484 kb
Host smart-aafde325-6e43-4df6-80a8-937856aadb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28082
85827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2808285827
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.2937460473
Short name T1126
Test name
Test status
Simulation time 4105105289 ps
CPU time 123.51 seconds
Started Jul 29 06:12:02 PM PDT 24
Finished Jul 29 06:14:05 PM PDT 24
Peak memory 215704 kb
Host smart-d713bf8a-cd49-4a88-b73d-48078d1dcaa4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2937460473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.2937460473
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.408196841
Short name T2052
Test name
Test status
Simulation time 237374901 ps
CPU time 1.07 seconds
Started Jul 29 06:12:05 PM PDT 24
Finished Jul 29 06:12:07 PM PDT 24
Peak memory 207124 kb
Host smart-8b93abba-8072-471f-a796-5897dfdbe294
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=408196841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.408196841
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2652588937
Short name T1000
Test name
Test status
Simulation time 192209449 ps
CPU time 0.93 seconds
Started Jul 29 06:12:04 PM PDT 24
Finished Jul 29 06:12:05 PM PDT 24
Peak memory 207132 kb
Host smart-ef764b42-1735-498e-9999-a9b3e951b231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26525
88937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2652588937
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2691451693
Short name T2757
Test name
Test status
Simulation time 4942333960 ps
CPU time 145.45 seconds
Started Jul 29 06:12:03 PM PDT 24
Finished Jul 29 06:14:29 PM PDT 24
Peak memory 215592 kb
Host smart-0f22a052-b53f-4b3f-980e-9b0d60b993ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26914
51693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2691451693
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.692603387
Short name T2508
Test name
Test status
Simulation time 3542205725 ps
CPU time 32.05 seconds
Started Jul 29 06:12:05 PM PDT 24
Finished Jul 29 06:12:37 PM PDT 24
Peak memory 215552 kb
Host smart-68f0479a-f392-4ff7-9e09-147c4b493a50
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=692603387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.692603387
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2954812454
Short name T2097
Test name
Test status
Simulation time 165726417 ps
CPU time 0.87 seconds
Started Jul 29 06:12:04 PM PDT 24
Finished Jul 29 06:12:05 PM PDT 24
Peak memory 207124 kb
Host smart-349184c5-781d-4108-bbc4-569d88ba4844
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2954812454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2954812454
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3507244700
Short name T2022
Test name
Test status
Simulation time 149616938 ps
CPU time 0.84 seconds
Started Jul 29 06:12:04 PM PDT 24
Finished Jul 29 06:12:05 PM PDT 24
Peak memory 207144 kb
Host smart-15ae4b8f-20f0-4c6e-9716-72214dd625b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35072
44700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3507244700
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3746182276
Short name T1871
Test name
Test status
Simulation time 166359347 ps
CPU time 0.93 seconds
Started Jul 29 06:12:04 PM PDT 24
Finished Jul 29 06:12:05 PM PDT 24
Peak memory 207116 kb
Host smart-b9113272-cb9a-40ee-8449-5f70b499debe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37461
82276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3746182276
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1306891468
Short name T2181
Test name
Test status
Simulation time 191412910 ps
CPU time 0.98 seconds
Started Jul 29 06:12:07 PM PDT 24
Finished Jul 29 06:12:08 PM PDT 24
Peak memory 207044 kb
Host smart-dacd6850-bd6c-4de9-8d57-38d335c756d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13068
91468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1306891468
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3264119332
Short name T1156
Test name
Test status
Simulation time 164673961 ps
CPU time 0.85 seconds
Started Jul 29 06:12:04 PM PDT 24
Finished Jul 29 06:12:05 PM PDT 24
Peak memory 207112 kb
Host smart-c52dd67f-7584-475d-a478-97eb24012258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32641
19332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3264119332
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1038611536
Short name T2175
Test name
Test status
Simulation time 167219497 ps
CPU time 0.91 seconds
Started Jul 29 06:12:07 PM PDT 24
Finished Jul 29 06:12:08 PM PDT 24
Peak memory 207124 kb
Host smart-011ceaba-c2dd-4c36-8f63-45b1a348d160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10386
11536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1038611536
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.795961871
Short name T871
Test name
Test status
Simulation time 145658774 ps
CPU time 0.85 seconds
Started Jul 29 06:12:05 PM PDT 24
Finished Jul 29 06:12:06 PM PDT 24
Peak memory 207080 kb
Host smart-4273f288-4444-4af3-8147-3fa41cacfe0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79596
1871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.795961871
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.1813123762
Short name T2012
Test name
Test status
Simulation time 256449905 ps
CPU time 1.15 seconds
Started Jul 29 06:12:06 PM PDT 24
Finished Jul 29 06:12:07 PM PDT 24
Peak memory 207088 kb
Host smart-63ea6c4f-c85b-40dc-a998-9ed55099cb33
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1813123762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.1813123762
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.853347726
Short name T2182
Test name
Test status
Simulation time 142085252 ps
CPU time 0.82 seconds
Started Jul 29 06:12:05 PM PDT 24
Finished Jul 29 06:12:05 PM PDT 24
Peak memory 207068 kb
Host smart-d72d3177-0849-48b0-90c5-56550dbe648e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85334
7726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.853347726
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1848146481
Short name T1220
Test name
Test status
Simulation time 34573196 ps
CPU time 0.7 seconds
Started Jul 29 06:12:03 PM PDT 24
Finished Jul 29 06:12:04 PM PDT 24
Peak memory 207068 kb
Host smart-a6630aee-c003-48fb-a287-49457743a4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18481
46481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1848146481
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3264952016
Short name T236
Test name
Test status
Simulation time 22571242276 ps
CPU time 59.12 seconds
Started Jul 29 06:12:11 PM PDT 24
Finished Jul 29 06:13:11 PM PDT 24
Peak memory 215764 kb
Host smart-877295cc-b997-4375-91f5-d43cb326ca9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32649
52016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3264952016
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.443841445
Short name T544
Test name
Test status
Simulation time 219247230 ps
CPU time 0.97 seconds
Started Jul 29 06:12:11 PM PDT 24
Finished Jul 29 06:12:12 PM PDT 24
Peak memory 207136 kb
Host smart-5b93a694-d691-49c5-85df-0b456f4f825d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44384
1445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.443841445
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2459773131
Short name T1177
Test name
Test status
Simulation time 266226690 ps
CPU time 1.01 seconds
Started Jul 29 06:12:13 PM PDT 24
Finished Jul 29 06:12:14 PM PDT 24
Peak memory 207092 kb
Host smart-d616247f-dd9f-4f97-a6b2-cf92475306d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24597
73131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2459773131
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3913410745
Short name T166
Test name
Test status
Simulation time 12064863909 ps
CPU time 70 seconds
Started Jul 29 06:12:11 PM PDT 24
Finished Jul 29 06:13:21 PM PDT 24
Peak memory 217764 kb
Host smart-e35e9bda-1f71-4bbf-b511-438d493ad202
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913410745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3913410745
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.789107907
Short name T158
Test name
Test status
Simulation time 4566713185 ps
CPU time 37.43 seconds
Started Jul 29 06:12:07 PM PDT 24
Finished Jul 29 06:12:44 PM PDT 24
Peak memory 223788 kb
Host smart-94ad4450-4ebf-4f01-aef5-a123878870c8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=789107907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.789107907
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.1841674593
Short name T1232
Test name
Test status
Simulation time 11802140561 ps
CPU time 64.58 seconds
Started Jul 29 06:12:08 PM PDT 24
Finished Jul 29 06:13:13 PM PDT 24
Peak memory 217700 kb
Host smart-03aedafe-70b8-46ae-872e-85ed50ae6e39
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841674593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1841674593
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2508454755
Short name T2585
Test name
Test status
Simulation time 212329781 ps
CPU time 1.04 seconds
Started Jul 29 06:12:12 PM PDT 24
Finished Jul 29 06:12:13 PM PDT 24
Peak memory 207092 kb
Host smart-64e4b8e1-1404-4ce8-a7e1-6bbd32858f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084
54755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2508454755
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.98873056
Short name T2234
Test name
Test status
Simulation time 219718512 ps
CPU time 0.95 seconds
Started Jul 29 06:12:10 PM PDT 24
Finished Jul 29 06:12:11 PM PDT 24
Peak memory 207132 kb
Host smart-7bb1acf5-a7f6-4416-bfd2-62af49009aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98873
056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.98873056
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.263759260
Short name T1931
Test name
Test status
Simulation time 158642746 ps
CPU time 0.87 seconds
Started Jul 29 06:12:16 PM PDT 24
Finished Jul 29 06:12:17 PM PDT 24
Peak memory 207064 kb
Host smart-c0ea8c0d-9342-42d1-9ca3-9f58887a2b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26375
9260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.263759260
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.4192417346
Short name T1249
Test name
Test status
Simulation time 152037435 ps
CPU time 0.83 seconds
Started Jul 29 06:12:09 PM PDT 24
Finished Jul 29 06:12:10 PM PDT 24
Peak memory 207012 kb
Host smart-b71d720d-6ffc-495a-b004-28796b0e09fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41924
17346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.4192417346
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.4070150562
Short name T1790
Test name
Test status
Simulation time 145396995 ps
CPU time 0.83 seconds
Started Jul 29 06:12:16 PM PDT 24
Finished Jul 29 06:12:17 PM PDT 24
Peak memory 207080 kb
Host smart-a3c58c32-fc09-4662-bcd8-2cbb6911034b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40701
50562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.4070150562
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2689028805
Short name T1449
Test name
Test status
Simulation time 252257347 ps
CPU time 1.08 seconds
Started Jul 29 06:12:16 PM PDT 24
Finished Jul 29 06:12:17 PM PDT 24
Peak memory 207076 kb
Host smart-bdc0a94f-0889-49c2-b610-2cab3437e368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26890
28805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2689028805
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1345443243
Short name T1556
Test name
Test status
Simulation time 6184916869 ps
CPU time 50.62 seconds
Started Jul 29 06:12:11 PM PDT 24
Finished Jul 29 06:13:01 PM PDT 24
Peak memory 207484 kb
Host smart-ff1080a2-0672-4fbe-9bc1-649c373f869b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1345443243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1345443243
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.352227923
Short name T2664
Test name
Test status
Simulation time 211703105 ps
CPU time 0.9 seconds
Started Jul 29 06:12:11 PM PDT 24
Finished Jul 29 06:12:12 PM PDT 24
Peak memory 207116 kb
Host smart-780ea66a-2943-4ce7-a27b-8aaa0a888e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35222
7923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.352227923
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.4205538921
Short name T396
Test name
Test status
Simulation time 232377973 ps
CPU time 0.96 seconds
Started Jul 29 06:12:11 PM PDT 24
Finished Jul 29 06:12:12 PM PDT 24
Peak memory 207100 kb
Host smart-ab5d1c67-e9f0-4ccf-a816-3f843b689bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42055
38921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.4205538921
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.3710634245
Short name T2746
Test name
Test status
Simulation time 630033878 ps
CPU time 1.92 seconds
Started Jul 29 06:12:11 PM PDT 24
Finished Jul 29 06:12:13 PM PDT 24
Peak memory 207036 kb
Host smart-1dc61254-e1d5-4b01-aef0-6e1f49ac15b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37106
34245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.3710634245
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.503580052
Short name T1747
Test name
Test status
Simulation time 7619587488 ps
CPU time 69.69 seconds
Started Jul 29 06:12:10 PM PDT 24
Finished Jul 29 06:13:20 PM PDT 24
Peak memory 207536 kb
Host smart-8e14f0bc-4c21-4f70-ad98-0abc6bb662c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50358
0052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.503580052
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.677344091
Short name T96
Test name
Test status
Simulation time 760583569 ps
CPU time 15.97 seconds
Started Jul 29 06:11:58 PM PDT 24
Finished Jul 29 06:12:14 PM PDT 24
Peak memory 207272 kb
Host smart-0eebeadd-4536-407c-a232-b2b17777bc79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677344091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host_
handshake.677344091
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2250025184
Short name T755
Test name
Test status
Simulation time 44253148 ps
CPU time 0.68 seconds
Started Jul 29 06:12:33 PM PDT 24
Finished Jul 29 06:12:34 PM PDT 24
Peak memory 207128 kb
Host smart-4648bb68-e71f-4166-8e3a-3a21d912739d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2250025184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2250025184
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3143696960
Short name T186
Test name
Test status
Simulation time 3954752266 ps
CPU time 5.69 seconds
Started Jul 29 06:12:11 PM PDT 24
Finished Jul 29 06:12:17 PM PDT 24
Peak memory 207296 kb
Host smart-ef05c96b-b387-458b-a3d7-4620bf0afacb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143696960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.3143696960
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.271116549
Short name T1445
Test name
Test status
Simulation time 13338608499 ps
CPU time 15.39 seconds
Started Jul 29 06:12:09 PM PDT 24
Finished Jul 29 06:12:25 PM PDT 24
Peak memory 207428 kb
Host smart-a13b270c-838c-47d9-aa52-1c1fbfd91822
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=271116549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.271116549
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.859671991
Short name T1345
Test name
Test status
Simulation time 23338289800 ps
CPU time 28 seconds
Started Jul 29 06:12:12 PM PDT 24
Finished Jul 29 06:12:40 PM PDT 24
Peak memory 207404 kb
Host smart-1c017935-0cef-449d-a00e-ce2ebf9d066f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859671991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon
_wake_resume.859671991
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.1245802667
Short name T403
Test name
Test status
Simulation time 211049575 ps
CPU time 0.95 seconds
Started Jul 29 06:12:10 PM PDT 24
Finished Jul 29 06:12:11 PM PDT 24
Peak memory 207056 kb
Host smart-2c55235a-6920-4d7b-87f1-381838e660a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12458
02667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.1245802667
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1293436355
Short name T2148
Test name
Test status
Simulation time 145355748 ps
CPU time 0.88 seconds
Started Jul 29 06:12:10 PM PDT 24
Finished Jul 29 06:12:11 PM PDT 24
Peak memory 207068 kb
Host smart-a2d7178c-e1b4-4239-8f26-dc893d0f9894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12934
36355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1293436355
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.1741006267
Short name T960
Test name
Test status
Simulation time 359107641 ps
CPU time 1.29 seconds
Started Jul 29 06:12:13 PM PDT 24
Finished Jul 29 06:12:14 PM PDT 24
Peak memory 207116 kb
Host smart-17910ac7-9dae-48e2-abf4-f97c937542ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17410
06267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.1741006267
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3286609844
Short name T1284
Test name
Test status
Simulation time 635956519 ps
CPU time 1.79 seconds
Started Jul 29 06:12:16 PM PDT 24
Finished Jul 29 06:12:18 PM PDT 24
Peak memory 207080 kb
Host smart-52ee056e-3e7d-4f2d-accf-f7292538f5fc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3286609844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3286609844
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.3585817119
Short name T858
Test name
Test status
Simulation time 17648110175 ps
CPU time 37.31 seconds
Started Jul 29 06:12:13 PM PDT 24
Finished Jul 29 06:12:50 PM PDT 24
Peak memory 207408 kb
Host smart-196f8428-22be-40bd-8e0f-972e49730221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35858
17119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.3585817119
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.2737669829
Short name T480
Test name
Test status
Simulation time 865324213 ps
CPU time 18.76 seconds
Started Jul 29 06:12:12 PM PDT 24
Finished Jul 29 06:12:31 PM PDT 24
Peak memory 207372 kb
Host smart-532c5b02-7710-4a29-b9ac-0e13c5110c7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737669829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.2737669829
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.3872024857
Short name T2423
Test name
Test status
Simulation time 424862230 ps
CPU time 1.51 seconds
Started Jul 29 06:12:15 PM PDT 24
Finished Jul 29 06:12:17 PM PDT 24
Peak memory 207084 kb
Host smart-e56ef49c-5efa-4267-a5b0-6db336ebd203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38720
24857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.3872024857
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.1319853951
Short name T2626
Test name
Test status
Simulation time 199577032 ps
CPU time 0.87 seconds
Started Jul 29 06:12:14 PM PDT 24
Finished Jul 29 06:12:15 PM PDT 24
Peak memory 207012 kb
Host smart-996c340e-7eeb-4b95-9f3f-4acb936bf815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13198
53951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1319853951
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.1197554756
Short name T2588
Test name
Test status
Simulation time 42352914 ps
CPU time 0.71 seconds
Started Jul 29 06:12:19 PM PDT 24
Finished Jul 29 06:12:20 PM PDT 24
Peak memory 207088 kb
Host smart-0528f6ee-2383-41f7-aaa8-084736fe4f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11975
54756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1197554756
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.3022575134
Short name T1547
Test name
Test status
Simulation time 816549943 ps
CPU time 2.33 seconds
Started Jul 29 06:12:18 PM PDT 24
Finished Jul 29 06:12:20 PM PDT 24
Peak memory 207332 kb
Host smart-66453a11-54b6-4146-ad2f-8be53aaa5a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30225
75134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.3022575134
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2684842942
Short name T845
Test name
Test status
Simulation time 273159932 ps
CPU time 2.17 seconds
Started Jul 29 06:12:17 PM PDT 24
Finished Jul 29 06:12:19 PM PDT 24
Peak memory 207224 kb
Host smart-2d471ff7-a6a0-4b9c-bd0d-355b622c6085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26848
42942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2684842942
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.977712704
Short name T601
Test name
Test status
Simulation time 216272639 ps
CPU time 0.95 seconds
Started Jul 29 06:12:16 PM PDT 24
Finished Jul 29 06:12:17 PM PDT 24
Peak memory 207124 kb
Host smart-15c9f860-89ba-48fa-8301-fd397c2125d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=977712704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.977712704
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.34158280
Short name T2495
Test name
Test status
Simulation time 142031012 ps
CPU time 0.83 seconds
Started Jul 29 06:12:16 PM PDT 24
Finished Jul 29 06:12:17 PM PDT 24
Peak memory 207032 kb
Host smart-b7e84392-8763-45d4-b8e2-d531d320efbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34158
280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.34158280
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.1681594901
Short name T1916
Test name
Test status
Simulation time 163144013 ps
CPU time 0.9 seconds
Started Jul 29 06:12:17 PM PDT 24
Finished Jul 29 06:12:18 PM PDT 24
Peak memory 207056 kb
Host smart-851b6762-fb09-4756-bfd9-37bba106b6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16815
94901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.1681594901
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.3731288133
Short name T2058
Test name
Test status
Simulation time 7763409249 ps
CPU time 60.55 seconds
Started Jul 29 06:12:19 PM PDT 24
Finished Jul 29 06:13:19 PM PDT 24
Peak memory 217084 kb
Host smart-ed8b2650-35a7-48e6-b00a-5f9b09d8738e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3731288133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.3731288133
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.482200764
Short name T2670
Test name
Test status
Simulation time 6475031986 ps
CPU time 73.84 seconds
Started Jul 29 06:12:15 PM PDT 24
Finished Jul 29 06:13:29 PM PDT 24
Peak memory 207284 kb
Host smart-02367cb8-eeeb-440d-ae6d-72c55b122fb5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=482200764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.482200764
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.3668253378
Short name T1906
Test name
Test status
Simulation time 278818394 ps
CPU time 1.05 seconds
Started Jul 29 06:12:18 PM PDT 24
Finished Jul 29 06:12:19 PM PDT 24
Peak memory 207104 kb
Host smart-2a51d493-3929-45fa-8946-6ecea393f11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36682
53378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3668253378
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.1927502990
Short name T764
Test name
Test status
Simulation time 23349549021 ps
CPU time 28.75 seconds
Started Jul 29 06:12:15 PM PDT 24
Finished Jul 29 06:12:44 PM PDT 24
Peak memory 207416 kb
Host smart-51e78134-1d54-4934-8b4e-5b35f8f8604d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19275
02990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.1927502990
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.515623446
Short name T352
Test name
Test status
Simulation time 3256286061 ps
CPU time 4.74 seconds
Started Jul 29 06:12:17 PM PDT 24
Finished Jul 29 06:12:22 PM PDT 24
Peak memory 207348 kb
Host smart-751cf593-0cff-4fee-9469-d190fa527a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51562
3446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.515623446
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.1854470343
Short name T295
Test name
Test status
Simulation time 10203494265 ps
CPU time 73.81 seconds
Started Jul 29 06:12:15 PM PDT 24
Finished Jul 29 06:13:28 PM PDT 24
Peak memory 223828 kb
Host smart-07048cea-45d0-47b5-a678-bfab2ca1e78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18544
70343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1854470343
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.2785884574
Short name T2355
Test name
Test status
Simulation time 4975312775 ps
CPU time 153.53 seconds
Started Jul 29 06:12:17 PM PDT 24
Finished Jul 29 06:14:51 PM PDT 24
Peak memory 215568 kb
Host smart-21e705e8-aa79-45cb-9803-0d58d86af8b5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2785884574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.2785884574
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.718378865
Short name T2405
Test name
Test status
Simulation time 232745211 ps
CPU time 1.01 seconds
Started Jul 29 06:12:17 PM PDT 24
Finished Jul 29 06:12:18 PM PDT 24
Peak memory 207076 kb
Host smart-7f67bc6b-5857-401b-a677-7bfc3ed3a717
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=718378865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.718378865
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3180697875
Short name T573
Test name
Test status
Simulation time 189237209 ps
CPU time 0.96 seconds
Started Jul 29 06:12:16 PM PDT 24
Finished Jul 29 06:12:17 PM PDT 24
Peak memory 207104 kb
Host smart-96f6aa87-1804-4516-aeaa-b044b64479b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31806
97875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3180697875
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.3979028379
Short name T339
Test name
Test status
Simulation time 3336942494 ps
CPU time 33.34 seconds
Started Jul 29 06:12:16 PM PDT 24
Finished Jul 29 06:12:50 PM PDT 24
Peak memory 216800 kb
Host smart-bebe935d-7adb-484e-88d6-0d762027fc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39790
28379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.3979028379
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.780725627
Short name T2212
Test name
Test status
Simulation time 4270281470 ps
CPU time 131.82 seconds
Started Jul 29 06:12:23 PM PDT 24
Finished Jul 29 06:14:35 PM PDT 24
Peak memory 215536 kb
Host smart-af6b4b4a-c19e-4ad6-bd95-ec8577753a00
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=780725627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.780725627
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.1796784733
Short name T884
Test name
Test status
Simulation time 171729176 ps
CPU time 0.92 seconds
Started Jul 29 06:12:25 PM PDT 24
Finished Jul 29 06:12:26 PM PDT 24
Peak memory 207080 kb
Host smart-fa6b0f8a-c821-4540-916a-98e7412c54ee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1796784733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.1796784733
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1629379724
Short name T348
Test name
Test status
Simulation time 151761048 ps
CPU time 0.84 seconds
Started Jul 29 06:12:21 PM PDT 24
Finished Jul 29 06:12:22 PM PDT 24
Peak memory 207052 kb
Host smart-951e8b2c-0d2e-4335-9d81-1a5535a2633b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16293
79724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1629379724
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.2080815677
Short name T2192
Test name
Test status
Simulation time 167937089 ps
CPU time 0.87 seconds
Started Jul 29 06:12:26 PM PDT 24
Finished Jul 29 06:12:27 PM PDT 24
Peak memory 207128 kb
Host smart-d566b978-cdf0-48a6-85ab-129dc27a940e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20808
15677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2080815677
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2529729347
Short name T2444
Test name
Test status
Simulation time 181895159 ps
CPU time 0.88 seconds
Started Jul 29 06:12:25 PM PDT 24
Finished Jul 29 06:12:26 PM PDT 24
Peak memory 206980 kb
Host smart-14a7c8ea-96ce-4e68-8e41-08b69110e91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25297
29347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2529729347
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1968495821
Short name T1169
Test name
Test status
Simulation time 196885908 ps
CPU time 0.91 seconds
Started Jul 29 06:12:24 PM PDT 24
Finished Jul 29 06:12:25 PM PDT 24
Peak memory 207100 kb
Host smart-438798f2-9615-4c88-aaaa-547757b60727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19684
95821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1968495821
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2390910915
Short name T883
Test name
Test status
Simulation time 173019955 ps
CPU time 0.88 seconds
Started Jul 29 06:12:24 PM PDT 24
Finished Jul 29 06:12:25 PM PDT 24
Peak memory 207096 kb
Host smart-62e74072-3104-4b95-bed0-99a598e6bca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23909
10915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2390910915
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3473444089
Short name T436
Test name
Test status
Simulation time 169210508 ps
CPU time 0.91 seconds
Started Jul 29 06:12:22 PM PDT 24
Finished Jul 29 06:12:23 PM PDT 24
Peak memory 207068 kb
Host smart-87869836-52ab-478a-9c02-628fcf30cd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34734
44089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3473444089
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.688787491
Short name T1829
Test name
Test status
Simulation time 212462063 ps
CPU time 0.95 seconds
Started Jul 29 06:12:22 PM PDT 24
Finished Jul 29 06:12:23 PM PDT 24
Peak memory 207104 kb
Host smart-e948e4a9-472b-46ab-91cd-44155c06f58f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=688787491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.688787491
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.4152565330
Short name T538
Test name
Test status
Simulation time 147822894 ps
CPU time 0.81 seconds
Started Jul 29 06:12:26 PM PDT 24
Finished Jul 29 06:12:27 PM PDT 24
Peak memory 207068 kb
Host smart-93f7bc0c-e149-4da4-8702-0a79cc9383df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41525
65330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.4152565330
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2039961787
Short name T36
Test name
Test status
Simulation time 33491465 ps
CPU time 0.69 seconds
Started Jul 29 06:12:24 PM PDT 24
Finished Jul 29 06:12:25 PM PDT 24
Peak memory 207064 kb
Host smart-2a281444-afb2-4088-9d16-5513bd0bed99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20399
61787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2039961787
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.732034963
Short name T107
Test name
Test status
Simulation time 11419138280 ps
CPU time 30.19 seconds
Started Jul 29 06:12:24 PM PDT 24
Finished Jul 29 06:12:54 PM PDT 24
Peak memory 215620 kb
Host smart-b2f2f053-5d5d-48ee-bb66-f7cb7d35c73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73203
4963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.732034963
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3152568175
Short name T2147
Test name
Test status
Simulation time 170873844 ps
CPU time 0.92 seconds
Started Jul 29 06:12:26 PM PDT 24
Finished Jul 29 06:12:27 PM PDT 24
Peak memory 207080 kb
Host smart-b92cbedb-fe93-4773-b119-5f1b9f71b455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31525
68175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3152568175
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3589389320
Short name T567
Test name
Test status
Simulation time 284996509 ps
CPU time 1.22 seconds
Started Jul 29 06:12:25 PM PDT 24
Finished Jul 29 06:12:26 PM PDT 24
Peak memory 207096 kb
Host smart-8c78dd13-312b-412a-af33-8a395e35a325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35893
89320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3589389320
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.755796083
Short name T161
Test name
Test status
Simulation time 18214737225 ps
CPU time 415.8 seconds
Started Jul 29 06:12:26 PM PDT 24
Finished Jul 29 06:19:22 PM PDT 24
Peak memory 215668 kb
Host smart-518584a0-224d-4294-a7aa-3ccf56dacbe0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=755796083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.755796083
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.770281699
Short name T175
Test name
Test status
Simulation time 9444419261 ps
CPU time 54.19 seconds
Started Jul 29 06:12:23 PM PDT 24
Finished Jul 29 06:13:17 PM PDT 24
Peak memory 218512 kb
Host smart-4588f7b3-cbfc-47a4-ac76-4b98c91cd0f4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=770281699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.770281699
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.331941077
Short name T749
Test name
Test status
Simulation time 7356720501 ps
CPU time 112.86 seconds
Started Jul 29 06:12:24 PM PDT 24
Finished Jul 29 06:14:17 PM PDT 24
Peak memory 215644 kb
Host smart-a028a742-0d14-4d52-aa4a-fc8b0c84c0ab
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=331941077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.331941077
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3997995711
Short name T2135
Test name
Test status
Simulation time 217720913 ps
CPU time 0.98 seconds
Started Jul 29 06:12:24 PM PDT 24
Finished Jul 29 06:12:25 PM PDT 24
Peak memory 207124 kb
Host smart-3ec6fefc-4870-4fdc-9567-84078fb84145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39979
95711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3997995711
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.615169761
Short name T1112
Test name
Test status
Simulation time 146022745 ps
CPU time 0.85 seconds
Started Jul 29 06:12:22 PM PDT 24
Finished Jul 29 06:12:23 PM PDT 24
Peak memory 207080 kb
Host smart-8b29ae20-dc92-4839-949f-4e485e6d9ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61516
9761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.615169761
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2848441534
Short name T1624
Test name
Test status
Simulation time 182260317 ps
CPU time 0.86 seconds
Started Jul 29 06:12:23 PM PDT 24
Finished Jul 29 06:12:24 PM PDT 24
Peak memory 207104 kb
Host smart-c33d5050-d079-4905-a3b5-3aa16e17af84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28484
41534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2848441534
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.23521835
Short name T1050
Test name
Test status
Simulation time 192017861 ps
CPU time 0.96 seconds
Started Jul 29 06:12:26 PM PDT 24
Finished Jul 29 06:12:27 PM PDT 24
Peak memory 207060 kb
Host smart-375e6900-a064-4fa0-80df-c2deee7ded06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23521
835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.23521835
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2179349265
Short name T2041
Test name
Test status
Simulation time 158555230 ps
CPU time 0.84 seconds
Started Jul 29 06:12:23 PM PDT 24
Finished Jul 29 06:12:24 PM PDT 24
Peak memory 207056 kb
Host smart-4b07290b-18af-4006-9735-5b8957e71389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21793
49265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2179349265
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1863860088
Short name T1350
Test name
Test status
Simulation time 270120106 ps
CPU time 1.05 seconds
Started Jul 29 06:12:24 PM PDT 24
Finished Jul 29 06:12:25 PM PDT 24
Peak memory 207100 kb
Host smart-208a2eb1-7cd1-48db-8984-4ec025433166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18638
60088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1863860088
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.585136827
Short name T1938
Test name
Test status
Simulation time 4028832137 ps
CPU time 39.91 seconds
Started Jul 29 06:12:22 PM PDT 24
Finished Jul 29 06:13:02 PM PDT 24
Peak memory 215516 kb
Host smart-3b76a2be-824d-4e5e-9c23-85586d3dfd1f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=585136827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.585136827
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3782358087
Short name T1473
Test name
Test status
Simulation time 153538666 ps
CPU time 0.83 seconds
Started Jul 29 06:12:27 PM PDT 24
Finished Jul 29 06:12:28 PM PDT 24
Peak memory 207116 kb
Host smart-2ad168cb-d4c1-4c8a-bf38-dc0f9b761ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37823
58087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3782358087
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.1431722138
Short name T1451
Test name
Test status
Simulation time 184127280 ps
CPU time 0.9 seconds
Started Jul 29 06:12:30 PM PDT 24
Finished Jul 29 06:12:31 PM PDT 24
Peak memory 207064 kb
Host smart-8446bb89-6fbe-4852-bb99-20710cdd0180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14317
22138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.1431722138
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.3568697402
Short name T333
Test name
Test status
Simulation time 674700333 ps
CPU time 1.96 seconds
Started Jul 29 06:12:27 PM PDT 24
Finished Jul 29 06:12:29 PM PDT 24
Peak memory 207040 kb
Host smart-1447c103-38ed-49d4-8334-6a468ae13e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35686
97402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.3568697402
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3208797521
Short name T631
Test name
Test status
Simulation time 7758004224 ps
CPU time 244.7 seconds
Started Jul 29 06:12:31 PM PDT 24
Finished Jul 29 06:16:36 PM PDT 24
Peak memory 215576 kb
Host smart-c8fa645c-502c-4f90-bb07-d8e76dc19205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32087
97521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3208797521
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.2838479133
Short name T1105
Test name
Test status
Simulation time 826896293 ps
CPU time 19.6 seconds
Started Jul 29 06:12:15 PM PDT 24
Finished Jul 29 06:12:35 PM PDT 24
Peak memory 207360 kb
Host smart-684f09e7-19fb-4469-ad93-1200aa95eaf4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838479133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.2838479133
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.1750602647
Short name T1438
Test name
Test status
Simulation time 63603218 ps
CPU time 0.73 seconds
Started Jul 29 06:12:41 PM PDT 24
Finished Jul 29 06:12:42 PM PDT 24
Peak memory 207144 kb
Host smart-b08a6ce6-f755-4447-a617-1b2bd8c1f6c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1750602647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1750602647
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3522821842
Short name T11
Test name
Test status
Simulation time 3544185704 ps
CPU time 5.1 seconds
Started Jul 29 06:12:31 PM PDT 24
Finished Jul 29 06:12:36 PM PDT 24
Peak memory 207304 kb
Host smart-09eb635f-fa5a-4b42-9002-31ab7b83fc2f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522821842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.3522821842
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.828466428
Short name T2162
Test name
Test status
Simulation time 13363652788 ps
CPU time 15.15 seconds
Started Jul 29 06:12:29 PM PDT 24
Finished Jul 29 06:12:45 PM PDT 24
Peak memory 207396 kb
Host smart-ef94807c-19cd-484d-b317-d990b6834d5a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=828466428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.828466428
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.3304010662
Short name T1633
Test name
Test status
Simulation time 23405536343 ps
CPU time 33.96 seconds
Started Jul 29 06:12:31 PM PDT 24
Finished Jul 29 06:13:05 PM PDT 24
Peak memory 207376 kb
Host smart-488676ab-dc9a-44ee-872e-dbb838922969
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304010662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.3304010662
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3408494977
Short name T840
Test name
Test status
Simulation time 162266140 ps
CPU time 0.86 seconds
Started Jul 29 06:12:28 PM PDT 24
Finished Jul 29 06:12:29 PM PDT 24
Peak memory 207136 kb
Host smart-dce87f42-b5fe-4ee1-84e9-1ff4ebc4b893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34084
94977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3408494977
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.4232562886
Short name T617
Test name
Test status
Simulation time 172527438 ps
CPU time 0.87 seconds
Started Jul 29 06:12:30 PM PDT 24
Finished Jul 29 06:12:31 PM PDT 24
Peak memory 207092 kb
Host smart-8b3424d6-e88d-472a-b05b-8cdcfdc842e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42325
62886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.4232562886
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.2595254230
Short name T106
Test name
Test status
Simulation time 185075744 ps
CPU time 0.9 seconds
Started Jul 29 06:12:30 PM PDT 24
Finished Jul 29 06:12:31 PM PDT 24
Peak memory 207108 kb
Host smart-de128d95-b564-4e40-911d-d3ba4f8bcd3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25952
54230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.2595254230
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.1432383387
Short name T1133
Test name
Test status
Simulation time 1053857319 ps
CPU time 2.63 seconds
Started Jul 29 06:12:30 PM PDT 24
Finished Jul 29 06:12:33 PM PDT 24
Peak memory 207348 kb
Host smart-45beb357-0c6f-4b49-9e54-2963ae0f27a2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1432383387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1432383387
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.3830515705
Short name T270
Test name
Test status
Simulation time 9220580895 ps
CPU time 21 seconds
Started Jul 29 06:12:29 PM PDT 24
Finished Jul 29 06:12:51 PM PDT 24
Peak memory 207376 kb
Host smart-0cd3ded6-6bed-47ef-9b26-be33e4c2f34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38305
15705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.3830515705
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.3191300726
Short name T1639
Test name
Test status
Simulation time 690302338 ps
CPU time 14.92 seconds
Started Jul 29 06:12:29 PM PDT 24
Finished Jul 29 06:12:45 PM PDT 24
Peak memory 207292 kb
Host smart-fe0149eb-91a1-4983-983b-e78554cad185
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191300726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.3191300726
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.406645916
Short name T2050
Test name
Test status
Simulation time 463385421 ps
CPU time 1.63 seconds
Started Jul 29 06:12:32 PM PDT 24
Finished Jul 29 06:12:34 PM PDT 24
Peak memory 207076 kb
Host smart-f33c521f-739f-40e6-8610-ce7e6ab32b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664
5916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.406645916
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.1134724491
Short name T553
Test name
Test status
Simulation time 178232324 ps
CPU time 0.87 seconds
Started Jul 29 06:12:33 PM PDT 24
Finished Jul 29 06:12:34 PM PDT 24
Peak memory 206948 kb
Host smart-a13439dc-a00a-4dd9-90b6-fc49c95a2219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11347
24491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1134724491
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2827977464
Short name T1292
Test name
Test status
Simulation time 84148906 ps
CPU time 0.77 seconds
Started Jul 29 06:12:33 PM PDT 24
Finished Jul 29 06:12:34 PM PDT 24
Peak memory 207056 kb
Host smart-814fa0b1-fec5-4744-a147-df2a4bea0776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28279
77464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2827977464
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.944154956
Short name T2455
Test name
Test status
Simulation time 805433759 ps
CPU time 2.16 seconds
Started Jul 29 06:12:30 PM PDT 24
Finished Jul 29 06:12:32 PM PDT 24
Peak memory 207332 kb
Host smart-d8b72921-7c01-426d-af5d-2fde53d2c7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94415
4956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.944154956
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.3055733286
Short name T1252
Test name
Test status
Simulation time 377285466 ps
CPU time 2.53 seconds
Started Jul 29 06:12:31 PM PDT 24
Finished Jul 29 06:12:33 PM PDT 24
Peak memory 207248 kb
Host smart-5683d9ee-7a4b-4c12-9c7d-ccf050d9a4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30557
33286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3055733286
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.4073208132
Short name T2267
Test name
Test status
Simulation time 147100338 ps
CPU time 0.83 seconds
Started Jul 29 06:12:32 PM PDT 24
Finished Jul 29 06:12:33 PM PDT 24
Peak memory 207128 kb
Host smart-abc3af7f-159f-47bc-bc28-adea3ed51c8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4073208132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.4073208132
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1845759951
Short name T2219
Test name
Test status
Simulation time 148004017 ps
CPU time 0.85 seconds
Started Jul 29 06:12:35 PM PDT 24
Finished Jul 29 06:12:36 PM PDT 24
Peak memory 207068 kb
Host smart-3cfd6ad5-7bfc-4ee7-abb8-644fd99ef480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18457
59951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1845759951
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3701632055
Short name T2243
Test name
Test status
Simulation time 241593747 ps
CPU time 1.05 seconds
Started Jul 29 06:12:40 PM PDT 24
Finished Jul 29 06:12:41 PM PDT 24
Peak memory 207112 kb
Host smart-628705b4-7db2-472a-8bfc-b86ba434fc42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37016
32055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3701632055
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.3966766160
Short name T1905
Test name
Test status
Simulation time 6290754950 ps
CPU time 67.52 seconds
Started Jul 29 06:12:30 PM PDT 24
Finished Jul 29 06:13:37 PM PDT 24
Peak memory 216736 kb
Host smart-436f1e4e-364a-4f58-863e-24d75ab13865
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3966766160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.3966766160
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.937460955
Short name T809
Test name
Test status
Simulation time 4801957660 ps
CPU time 48.31 seconds
Started Jul 29 06:12:37 PM PDT 24
Finished Jul 29 06:13:25 PM PDT 24
Peak memory 207344 kb
Host smart-a08dd976-a458-4ca7-be71-ae9df5402a52
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=937460955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.937460955
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.445294896
Short name T1933
Test name
Test status
Simulation time 186328997 ps
CPU time 0.92 seconds
Started Jul 29 06:12:35 PM PDT 24
Finished Jul 29 06:12:36 PM PDT 24
Peak memory 207064 kb
Host smart-a4f8e52e-f845-4cfc-ad67-2db6e4c04e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44529
4896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.445294896
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2176197052
Short name T314
Test name
Test status
Simulation time 23358851882 ps
CPU time 30.2 seconds
Started Jul 29 06:12:41 PM PDT 24
Finished Jul 29 06:13:11 PM PDT 24
Peak memory 207400 kb
Host smart-b4be1d73-e9b6-4ede-a0ad-715258a6ffe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21761
97052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2176197052
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.3781429064
Short name T598
Test name
Test status
Simulation time 3309374384 ps
CPU time 5.45 seconds
Started Jul 29 06:12:38 PM PDT 24
Finished Jul 29 06:12:44 PM PDT 24
Peak memory 207248 kb
Host smart-bb5458b0-1ec0-4a6a-8fcf-9325a8c90a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37814
29064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3781429064
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.2593909775
Short name T1153
Test name
Test status
Simulation time 9958248584 ps
CPU time 106.4 seconds
Started Jul 29 06:12:38 PM PDT 24
Finished Jul 29 06:14:24 PM PDT 24
Peak memory 215672 kb
Host smart-7875095f-0213-4b32-ab74-cca2b90d8dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25939
09775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.2593909775
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.132421161
Short name T2780
Test name
Test status
Simulation time 4151172030 ps
CPU time 48.13 seconds
Started Jul 29 06:12:37 PM PDT 24
Finished Jul 29 06:13:25 PM PDT 24
Peak memory 216800 kb
Host smart-320b9c12-98e0-4097-af30-701dbd1ecde5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=132421161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.132421161
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1048136654
Short name T1010
Test name
Test status
Simulation time 243978105 ps
CPU time 1.01 seconds
Started Jul 29 06:12:38 PM PDT 24
Finished Jul 29 06:12:39 PM PDT 24
Peak memory 207124 kb
Host smart-8eb1536a-28b7-4252-9ca9-20c4ddedbea4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1048136654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1048136654
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2297402939
Short name T1525
Test name
Test status
Simulation time 214609481 ps
CPU time 0.94 seconds
Started Jul 29 06:12:36 PM PDT 24
Finished Jul 29 06:12:37 PM PDT 24
Peak memory 207104 kb
Host smart-4c97dc68-5c04-421c-bc65-9be6d42a5696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22974
02939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2297402939
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2937082482
Short name T1237
Test name
Test status
Simulation time 6956538980 ps
CPU time 195.57 seconds
Started Jul 29 06:12:35 PM PDT 24
Finished Jul 29 06:15:51 PM PDT 24
Peak memory 215576 kb
Host smart-68c2b16e-3f3e-4132-b4fa-26aed735bf2c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2937082482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2937082482
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.1546073298
Short name T1175
Test name
Test status
Simulation time 156093732 ps
CPU time 0.84 seconds
Started Jul 29 06:12:37 PM PDT 24
Finished Jul 29 06:12:38 PM PDT 24
Peak memory 207136 kb
Host smart-c3055ad3-e13e-4dba-bb34-03ab737697e5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1546073298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.1546073298
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1572335619
Short name T1667
Test name
Test status
Simulation time 177157805 ps
CPU time 0.9 seconds
Started Jul 29 06:12:36 PM PDT 24
Finished Jul 29 06:12:37 PM PDT 24
Peak memory 207064 kb
Host smart-b06a56b6-b982-4960-ad43-beacaf10d1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15723
35619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1572335619
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2203653329
Short name T124
Test name
Test status
Simulation time 202297219 ps
CPU time 0.9 seconds
Started Jul 29 06:12:35 PM PDT 24
Finished Jul 29 06:12:36 PM PDT 24
Peak memory 207104 kb
Host smart-aed62e24-9ef6-4a76-bb69-60893800b348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22036
53329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2203653329
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.2486919699
Short name T2606
Test name
Test status
Simulation time 174839203 ps
CPU time 0.93 seconds
Started Jul 29 06:12:38 PM PDT 24
Finished Jul 29 06:12:39 PM PDT 24
Peak memory 207056 kb
Host smart-7c3ef421-a2d6-42fe-8c00-5ac1eaf7a8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24869
19699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.2486919699
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2012123465
Short name T2209
Test name
Test status
Simulation time 157463534 ps
CPU time 0.84 seconds
Started Jul 29 06:12:39 PM PDT 24
Finished Jul 29 06:12:40 PM PDT 24
Peak memory 207080 kb
Host smart-74999d7b-2248-4842-aefe-1972b1e6df68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20121
23465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2012123465
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1821153604
Short name T2627
Test name
Test status
Simulation time 219325757 ps
CPU time 0.88 seconds
Started Jul 29 06:12:38 PM PDT 24
Finished Jul 29 06:12:40 PM PDT 24
Peak memory 207128 kb
Host smart-d5970688-1bb9-4485-9e08-0d49638ec7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18211
53604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1821153604
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.97731243
Short name T1106
Test name
Test status
Simulation time 153165795 ps
CPU time 0.88 seconds
Started Jul 29 06:12:41 PM PDT 24
Finished Jul 29 06:12:42 PM PDT 24
Peak memory 207120 kb
Host smart-6773ba9d-d616-44ce-b47e-392d09a576b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97731
243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.97731243
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2062818239
Short name T773
Test name
Test status
Simulation time 239631805 ps
CPU time 1.03 seconds
Started Jul 29 06:12:36 PM PDT 24
Finished Jul 29 06:12:38 PM PDT 24
Peak memory 207036 kb
Host smart-25277834-48d5-404c-8ba2-7b9493134312
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2062818239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2062818239
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1999577941
Short name T1833
Test name
Test status
Simulation time 153643708 ps
CPU time 0.84 seconds
Started Jul 29 06:12:39 PM PDT 24
Finished Jul 29 06:12:40 PM PDT 24
Peak memory 206988 kb
Host smart-f27447e9-5606-4c84-bb55-1f08c4992031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19995
77941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1999577941
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3809167849
Short name T1263
Test name
Test status
Simulation time 32095764 ps
CPU time 0.73 seconds
Started Jul 29 06:12:39 PM PDT 24
Finished Jul 29 06:12:40 PM PDT 24
Peak memory 206964 kb
Host smart-89108b6d-d0dd-4969-9b61-b1882003144b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38091
67849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3809167849
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2921743824
Short name T2657
Test name
Test status
Simulation time 17248713185 ps
CPU time 41.02 seconds
Started Jul 29 06:12:38 PM PDT 24
Finished Jul 29 06:13:19 PM PDT 24
Peak memory 215640 kb
Host smart-a6ae0261-9552-4b37-8e16-7af6a240006a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29217
43824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2921743824
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3552628701
Short name T468
Test name
Test status
Simulation time 196449062 ps
CPU time 0.93 seconds
Started Jul 29 06:12:40 PM PDT 24
Finished Jul 29 06:12:41 PM PDT 24
Peak memory 207060 kb
Host smart-37524b6e-8989-428b-8c35-8c46b1c810c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35526
28701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3552628701
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.938558628
Short name T733
Test name
Test status
Simulation time 177704914 ps
CPU time 0.93 seconds
Started Jul 29 06:12:38 PM PDT 24
Finished Jul 29 06:12:39 PM PDT 24
Peak memory 207068 kb
Host smart-8e76c9ca-0066-4ced-983d-e4d4c7d5acd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93855
8628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.938558628
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.2524293879
Short name T1849
Test name
Test status
Simulation time 17958769193 ps
CPU time 442.8 seconds
Started Jul 29 06:12:35 PM PDT 24
Finished Jul 29 06:19:58 PM PDT 24
Peak memory 215624 kb
Host smart-2c0f786a-5e43-4f53-8492-0f9392a18e06
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524293879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.2524293879
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.339799634
Short name T167
Test name
Test status
Simulation time 7970542284 ps
CPU time 224.32 seconds
Started Jul 29 06:12:36 PM PDT 24
Finished Jul 29 06:16:20 PM PDT 24
Peak memory 215608 kb
Host smart-5cfd5a06-1257-4b5c-bfa2-78c261a8cfdc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=339799634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.339799634
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.908581392
Short name T758
Test name
Test status
Simulation time 15536020935 ps
CPU time 118.02 seconds
Started Jul 29 06:12:43 PM PDT 24
Finished Jul 29 06:14:41 PM PDT 24
Peak memory 223764 kb
Host smart-4c536111-49ee-4fa8-8fae-1d5f26126650
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=908581392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.908581392
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2902947930
Short name T1258
Test name
Test status
Simulation time 229022306 ps
CPU time 1.01 seconds
Started Jul 29 06:12:38 PM PDT 24
Finished Jul 29 06:12:39 PM PDT 24
Peak memory 207128 kb
Host smart-652c0320-d083-46af-9ee7-dc5350c6a26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29029
47930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2902947930
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.1845324717
Short name T235
Test name
Test status
Simulation time 183864963 ps
CPU time 0.93 seconds
Started Jul 29 06:12:37 PM PDT 24
Finished Jul 29 06:12:38 PM PDT 24
Peak memory 207100 kb
Host smart-ed3b94e6-aeee-4902-9e98-31fa4996a1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18453
24717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.1845324717
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2498717094
Short name T565
Test name
Test status
Simulation time 183145559 ps
CPU time 0.93 seconds
Started Jul 29 06:12:46 PM PDT 24
Finished Jul 29 06:12:47 PM PDT 24
Peak memory 207076 kb
Host smart-15ba9134-525d-47eb-b8f9-09000e549391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24987
17094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2498717094
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2936197224
Short name T2680
Test name
Test status
Simulation time 150693314 ps
CPU time 0.82 seconds
Started Jul 29 06:12:41 PM PDT 24
Finished Jul 29 06:12:42 PM PDT 24
Peak memory 207044 kb
Host smart-50adf393-c148-4293-83df-39febe19d91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29361
97224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2936197224
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.4275047474
Short name T1625
Test name
Test status
Simulation time 149657360 ps
CPU time 0.81 seconds
Started Jul 29 06:12:42 PM PDT 24
Finished Jul 29 06:12:43 PM PDT 24
Peak memory 207080 kb
Host smart-49dc2045-57f1-48a6-a66c-1b6ee38e1278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42750
47474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.4275047474
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3077551333
Short name T1844
Test name
Test status
Simulation time 207265498 ps
CPU time 0.94 seconds
Started Jul 29 06:12:44 PM PDT 24
Finished Jul 29 06:12:45 PM PDT 24
Peak memory 207108 kb
Host smart-460e7f9e-454d-488b-b3cd-8691118fbb38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30775
51333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3077551333
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1222757153
Short name T630
Test name
Test status
Simulation time 5820793643 ps
CPU time 172.17 seconds
Started Jul 29 06:12:42 PM PDT 24
Finished Jul 29 06:15:35 PM PDT 24
Peak memory 215636 kb
Host smart-dd77adb5-7a83-4fcf-b6cb-feb207f2300e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1222757153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1222757153
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.966943396
Short name T488
Test name
Test status
Simulation time 159002473 ps
CPU time 0.88 seconds
Started Jul 29 06:12:41 PM PDT 24
Finished Jul 29 06:12:42 PM PDT 24
Peak memory 207116 kb
Host smart-df88f798-7d4e-4c82-a210-38ef7d372e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96694
3396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.966943396
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3941048533
Short name T605
Test name
Test status
Simulation time 191101437 ps
CPU time 0.89 seconds
Started Jul 29 06:12:44 PM PDT 24
Finished Jul 29 06:12:45 PM PDT 24
Peak memory 207020 kb
Host smart-6991c100-ea55-4078-88bd-4b6295226c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39410
48533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3941048533
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.3052290633
Short name T1645
Test name
Test status
Simulation time 964835835 ps
CPU time 2.48 seconds
Started Jul 29 06:12:41 PM PDT 24
Finished Jul 29 06:12:43 PM PDT 24
Peak memory 207328 kb
Host smart-e8a57d6d-4fe3-407f-897a-eae2db72774d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30522
90633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.3052290633
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.147203207
Short name T1561
Test name
Test status
Simulation time 4179346389 ps
CPU time 31.56 seconds
Started Jul 29 06:12:44 PM PDT 24
Finished Jul 29 06:13:16 PM PDT 24
Peak memory 216892 kb
Host smart-f0ff1d4b-60f3-4eab-9b37-ed976d460f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14720
3207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.147203207
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.2645923567
Short name T2659
Test name
Test status
Simulation time 890499075 ps
CPU time 5.43 seconds
Started Jul 29 06:12:33 PM PDT 24
Finished Jul 29 06:12:38 PM PDT 24
Peak memory 207324 kb
Host smart-a8648457-da4b-403e-a1dc-49a443a57a13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645923567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.2645923567
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.2717381672
Short name T185
Test name
Test status
Simulation time 50282949 ps
CPU time 0.72 seconds
Started Jul 29 06:12:57 PM PDT 24
Finished Jul 29 06:12:58 PM PDT 24
Peak memory 207036 kb
Host smart-cc2f7392-8420-4630-9928-e7bb912e671b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2717381672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.2717381672
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2022485209
Short name T2425
Test name
Test status
Simulation time 3845469136 ps
CPU time 5.91 seconds
Started Jul 29 06:12:46 PM PDT 24
Finished Jul 29 06:12:53 PM PDT 24
Peak memory 207312 kb
Host smart-78b1770d-260f-458c-82c4-4c2881029853
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022485209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.2022485209
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.2179292133
Short name T1505
Test name
Test status
Simulation time 13392678101 ps
CPU time 16.66 seconds
Started Jul 29 06:12:41 PM PDT 24
Finished Jul 29 06:12:58 PM PDT 24
Peak memory 207444 kb
Host smart-a112883c-72fa-49c4-838f-44e4f268066b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179292133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.2179292133
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.1710333321
Short name T1387
Test name
Test status
Simulation time 23378155123 ps
CPU time 27.57 seconds
Started Jul 29 06:12:42 PM PDT 24
Finished Jul 29 06:13:10 PM PDT 24
Peak memory 207432 kb
Host smart-732e26a7-9733-4a63-ab65-63b9d0391567
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710333321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.1710333321
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1987867170
Short name T1643
Test name
Test status
Simulation time 168010286 ps
CPU time 1 seconds
Started Jul 29 06:12:43 PM PDT 24
Finished Jul 29 06:12:44 PM PDT 24
Peak memory 207112 kb
Host smart-96f99c11-76f7-4b3e-a354-2267bc03f365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19878
67170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1987867170
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.3201169149
Short name T2751
Test name
Test status
Simulation time 149564170 ps
CPU time 0.83 seconds
Started Jul 29 06:12:45 PM PDT 24
Finished Jul 29 06:12:46 PM PDT 24
Peak memory 207060 kb
Host smart-086c4126-14fa-4685-8966-b99c73a592d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32011
69149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.3201169149
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.1935432265
Short name T548
Test name
Test status
Simulation time 388137882 ps
CPU time 1.41 seconds
Started Jul 29 06:12:45 PM PDT 24
Finished Jul 29 06:12:47 PM PDT 24
Peak memory 207104 kb
Host smart-b7c3d9e0-da8f-4934-90f9-b875684961d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19354
32265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.1935432265
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3632152087
Short name T1762
Test name
Test status
Simulation time 1077133910 ps
CPU time 2.93 seconds
Started Jul 29 06:12:46 PM PDT 24
Finished Jul 29 06:12:50 PM PDT 24
Peak memory 207356 kb
Host smart-abbafb66-b07d-47d4-9703-211d46e9d0a2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3632152087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3632152087
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.3070211598
Short name T1351
Test name
Test status
Simulation time 11980517903 ps
CPU time 31.55 seconds
Started Jul 29 06:12:44 PM PDT 24
Finished Jul 29 06:13:15 PM PDT 24
Peak memory 207384 kb
Host smart-14065d0f-2b8e-4850-9c42-cb6c0a943762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30702
11598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.3070211598
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.1291202780
Short name T1963
Test name
Test status
Simulation time 155779850 ps
CPU time 0.89 seconds
Started Jul 29 06:12:44 PM PDT 24
Finished Jul 29 06:12:45 PM PDT 24
Peak memory 206992 kb
Host smart-6d168a27-b90a-4e6d-8543-e81f97136d83
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291202780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.1291202780
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.2142530434
Short name T1334
Test name
Test status
Simulation time 355426817 ps
CPU time 1.2 seconds
Started Jul 29 06:12:44 PM PDT 24
Finished Jul 29 06:12:45 PM PDT 24
Peak memory 207064 kb
Host smart-4caf9dec-6a36-41b8-9689-a0f163a3ebfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21425
30434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.2142530434
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1764574240
Short name T673
Test name
Test status
Simulation time 149585238 ps
CPU time 0.85 seconds
Started Jul 29 06:12:42 PM PDT 24
Finished Jul 29 06:12:43 PM PDT 24
Peak memory 207044 kb
Host smart-7f93dcea-1728-45be-b594-b2280d38e072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17645
74240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1764574240
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.3401226115
Short name T2043
Test name
Test status
Simulation time 63036398 ps
CPU time 0.73 seconds
Started Jul 29 06:12:42 PM PDT 24
Finished Jul 29 06:12:43 PM PDT 24
Peak memory 207072 kb
Host smart-8931088e-6d9d-4ab9-a4e4-6b911d7e33e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34012
26115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3401226115
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2301209775
Short name T652
Test name
Test status
Simulation time 1083538592 ps
CPU time 2.81 seconds
Started Jul 29 06:12:44 PM PDT 24
Finished Jul 29 06:12:46 PM PDT 24
Peak memory 207312 kb
Host smart-d394fcbe-d2b1-4185-aa03-45a684c20f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23012
09775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2301209775
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.795312159
Short name T2487
Test name
Test status
Simulation time 314446618 ps
CPU time 1.84 seconds
Started Jul 29 06:12:43 PM PDT 24
Finished Jul 29 06:12:45 PM PDT 24
Peak memory 207200 kb
Host smart-83a9df26-9f65-4b9b-8e8f-022300a846b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79531
2159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.795312159
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2831158453
Short name T501
Test name
Test status
Simulation time 186264006 ps
CPU time 1.03 seconds
Started Jul 29 06:12:42 PM PDT 24
Finished Jul 29 06:12:43 PM PDT 24
Peak memory 207232 kb
Host smart-7cf4ead5-61b2-4c9f-a545-18f7d06a9cd5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2831158453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2831158453
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2472027373
Short name T2448
Test name
Test status
Simulation time 166110191 ps
CPU time 0.86 seconds
Started Jul 29 06:12:50 PM PDT 24
Finished Jul 29 06:12:51 PM PDT 24
Peak memory 207048 kb
Host smart-bfbdeeca-9aa3-4af3-9b8a-ccd7102bf714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24720
27373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2472027373
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2705850305
Short name T646
Test name
Test status
Simulation time 237610983 ps
CPU time 0.99 seconds
Started Jul 29 06:12:50 PM PDT 24
Finished Jul 29 06:12:51 PM PDT 24
Peak memory 207108 kb
Host smart-40342786-6ca7-40bf-a74c-65e4fb3acdb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27058
50305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2705850305
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.1679374827
Short name T2577
Test name
Test status
Simulation time 5786722202 ps
CPU time 46.45 seconds
Started Jul 29 06:12:46 PM PDT 24
Finished Jul 29 06:13:33 PM PDT 24
Peak memory 216892 kb
Host smart-3d406906-7fca-40e4-beb2-fff047ded891
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1679374827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.1679374827
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.584116204
Short name T2679
Test name
Test status
Simulation time 14245870457 ps
CPU time 104.08 seconds
Started Jul 29 06:12:49 PM PDT 24
Finished Jul 29 06:14:34 PM PDT 24
Peak memory 207388 kb
Host smart-2f972f91-a391-466a-bc8c-bf67c2062ab4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=584116204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.584116204
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3094302003
Short name T887
Test name
Test status
Simulation time 212267059 ps
CPU time 0.97 seconds
Started Jul 29 06:12:47 PM PDT 24
Finished Jul 29 06:12:48 PM PDT 24
Peak memory 207084 kb
Host smart-488c3521-8999-4436-afda-bc4200a230af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30943
02003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3094302003
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.2537219496
Short name T531
Test name
Test status
Simulation time 23279435793 ps
CPU time 28.43 seconds
Started Jul 29 06:12:48 PM PDT 24
Finished Jul 29 06:13:16 PM PDT 24
Peak memory 207408 kb
Host smart-088233be-7fbf-4875-8a1d-bac99026e0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25372
19496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.2537219496
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.1638975695
Short name T1881
Test name
Test status
Simulation time 3317709290 ps
CPU time 4.84 seconds
Started Jul 29 06:12:48 PM PDT 24
Finished Jul 29 06:12:53 PM PDT 24
Peak memory 207288 kb
Host smart-36d52b6d-16ce-4865-a575-6adc0edb2366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16389
75695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1638975695
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.3123487789
Short name T1219
Test name
Test status
Simulation time 6611330731 ps
CPU time 202.72 seconds
Started Jul 29 06:12:50 PM PDT 24
Finished Jul 29 06:16:13 PM PDT 24
Peak memory 215564 kb
Host smart-3ece5b1d-faf9-4f12-a710-f436b8d3e140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31234
87789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.3123487789
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.832361663
Short name T2364
Test name
Test status
Simulation time 3069689120 ps
CPU time 22.58 seconds
Started Jul 29 06:12:46 PM PDT 24
Finished Jul 29 06:13:09 PM PDT 24
Peak memory 217084 kb
Host smart-2d496834-5760-45c7-8aa5-7db33bba036a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=832361663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.832361663
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.1673270235
Short name T951
Test name
Test status
Simulation time 241776461 ps
CPU time 1 seconds
Started Jul 29 06:12:55 PM PDT 24
Finished Jul 29 06:12:56 PM PDT 24
Peak memory 207108 kb
Host smart-ded56de6-0ede-41c3-a7e4-15d1b3a2e0ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1673270235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.1673270235
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.4110214816
Short name T2427
Test name
Test status
Simulation time 219460587 ps
CPU time 1.04 seconds
Started Jul 29 06:12:50 PM PDT 24
Finished Jul 29 06:12:52 PM PDT 24
Peak memory 207120 kb
Host smart-007a8b36-c5e0-4cf9-a1e0-c45b1ca8d70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41102
14816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.4110214816
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.273676870
Short name T1371
Test name
Test status
Simulation time 4627296126 ps
CPU time 35.45 seconds
Started Jul 29 06:12:56 PM PDT 24
Finished Jul 29 06:13:31 PM PDT 24
Peak memory 217092 kb
Host smart-ff20ef2b-d481-4e9f-b665-4d44d6ca3a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27367
6870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.273676870
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.1926450398
Short name T1294
Test name
Test status
Simulation time 5499858218 ps
CPU time 41.28 seconds
Started Jul 29 06:12:50 PM PDT 24
Finished Jul 29 06:13:31 PM PDT 24
Peak memory 215592 kb
Host smart-2fcc9c1a-b26a-4ffd-9f92-cca4c5e1fb2d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1926450398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.1926450398
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3843347332
Short name T713
Test name
Test status
Simulation time 154922879 ps
CPU time 0.86 seconds
Started Jul 29 06:12:48 PM PDT 24
Finished Jul 29 06:12:49 PM PDT 24
Peak memory 207040 kb
Host smart-e9cfae8f-daa9-4a5e-a233-e73fbd705165
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3843347332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3843347332
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3503685971
Short name T1928
Test name
Test status
Simulation time 169356836 ps
CPU time 0.83 seconds
Started Jul 29 06:12:56 PM PDT 24
Finished Jul 29 06:12:57 PM PDT 24
Peak memory 207104 kb
Host smart-39242599-b949-4478-a70d-74b576c91793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35036
85971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3503685971
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1313782523
Short name T121
Test name
Test status
Simulation time 225373935 ps
CPU time 0.98 seconds
Started Jul 29 06:12:50 PM PDT 24
Finished Jul 29 06:12:51 PM PDT 24
Peak memory 207096 kb
Host smart-e71ce7b7-397c-4da6-9900-1cc422fa64cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13137
82523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1313782523
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2916811088
Short name T2363
Test name
Test status
Simulation time 228013599 ps
CPU time 0.99 seconds
Started Jul 29 06:12:48 PM PDT 24
Finished Jul 29 06:12:50 PM PDT 24
Peak memory 207116 kb
Host smart-91d7440d-97eb-4ae2-aba1-379a9723fb5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29168
11088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2916811088
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.140983816
Short name T1970
Test name
Test status
Simulation time 148658357 ps
CPU time 0.87 seconds
Started Jul 29 06:12:53 PM PDT 24
Finished Jul 29 06:12:54 PM PDT 24
Peak memory 207140 kb
Host smart-1e0cc3eb-0035-4e68-9264-82b87ecfa564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14098
3816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.140983816
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.62392611
Short name T2032
Test name
Test status
Simulation time 190358884 ps
CPU time 0.92 seconds
Started Jul 29 06:12:49 PM PDT 24
Finished Jul 29 06:12:50 PM PDT 24
Peak memory 207076 kb
Host smart-25eafb98-9952-41ef-bcbd-b10d682dd2c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62392
611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.62392611
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3067030870
Short name T825
Test name
Test status
Simulation time 157412489 ps
CPU time 0.84 seconds
Started Jul 29 06:12:47 PM PDT 24
Finished Jul 29 06:12:48 PM PDT 24
Peak memory 207096 kb
Host smart-056273b4-af3c-43d2-ac85-9c73d524b7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30670
30870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3067030870
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.791149689
Short name T676
Test name
Test status
Simulation time 288095596 ps
CPU time 1.18 seconds
Started Jul 29 06:12:53 PM PDT 24
Finished Jul 29 06:12:54 PM PDT 24
Peak memory 207132 kb
Host smart-841729dc-0a9a-47f4-9962-cbbb6dc4c913
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=791149689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.791149689
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3777987279
Short name T508
Test name
Test status
Simulation time 178669841 ps
CPU time 0.91 seconds
Started Jul 29 06:12:50 PM PDT 24
Finished Jul 29 06:12:51 PM PDT 24
Peak memory 207044 kb
Host smart-27667e3d-2e01-4e7f-8abf-7d9761bb4e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37779
87279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3777987279
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3941870433
Short name T2481
Test name
Test status
Simulation time 39324698 ps
CPU time 0.68 seconds
Started Jul 29 06:12:47 PM PDT 24
Finished Jul 29 06:12:48 PM PDT 24
Peak memory 207020 kb
Host smart-1b044afa-1a12-4318-a3d4-aac0d437aa47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39418
70433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3941870433
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2785364499
Short name T2591
Test name
Test status
Simulation time 12409331370 ps
CPU time 34.05 seconds
Started Jul 29 06:12:49 PM PDT 24
Finished Jul 29 06:13:23 PM PDT 24
Peak memory 215624 kb
Host smart-a24ba454-720e-404b-8cf4-9bb733d5063c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27853
64499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2785364499
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1431149440
Short name T1424
Test name
Test status
Simulation time 198283154 ps
CPU time 0.95 seconds
Started Jul 29 06:12:49 PM PDT 24
Finished Jul 29 06:12:50 PM PDT 24
Peak memory 207064 kb
Host smart-a8894170-6e5c-46a2-97be-a1985482b80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14311
49440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1431149440
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3479247498
Short name T1638
Test name
Test status
Simulation time 184481004 ps
CPU time 0.94 seconds
Started Jul 29 06:12:57 PM PDT 24
Finished Jul 29 06:12:58 PM PDT 24
Peak memory 207080 kb
Host smart-d11b2420-bd8a-469e-b6be-99640543f5a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34792
47498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3479247498
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2158165888
Short name T173
Test name
Test status
Simulation time 7521573662 ps
CPU time 205.87 seconds
Started Jul 29 06:12:59 PM PDT 24
Finished Jul 29 06:16:25 PM PDT 24
Peak memory 215616 kb
Host smart-196c8cd5-9488-4b27-8c5b-f57b9678cf6d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158165888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2158165888
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3125704345
Short name T2269
Test name
Test status
Simulation time 5774165304 ps
CPU time 157.53 seconds
Started Jul 29 06:12:56 PM PDT 24
Finished Jul 29 06:15:33 PM PDT 24
Peak memory 215608 kb
Host smart-84ee5baf-3e7c-4d11-ae30-14d4f43b06db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3125704345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3125704345
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.1122321400
Short name T1461
Test name
Test status
Simulation time 15042557430 ps
CPU time 111.32 seconds
Started Jul 29 06:12:53 PM PDT 24
Finished Jul 29 06:14:45 PM PDT 24
Peak memory 217516 kb
Host smart-86f3ead4-1dd7-4999-9939-6e8007d22da1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122321400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1122321400
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.2154262408
Short name T1390
Test name
Test status
Simulation time 213769231 ps
CPU time 0.93 seconds
Started Jul 29 06:12:53 PM PDT 24
Finished Jul 29 06:12:54 PM PDT 24
Peak memory 207068 kb
Host smart-903cd639-b572-412c-bc04-9a93bd48bad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21542
62408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.2154262408
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.1714252965
Short name T702
Test name
Test status
Simulation time 176621714 ps
CPU time 0.9 seconds
Started Jul 29 06:12:57 PM PDT 24
Finished Jul 29 06:12:58 PM PDT 24
Peak memory 207104 kb
Host smart-fdaa7b79-90ae-405d-ab41-c3743d06d14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17142
52965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1714252965
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1839545036
Short name T1590
Test name
Test status
Simulation time 146013012 ps
CPU time 0.8 seconds
Started Jul 29 06:12:57 PM PDT 24
Finished Jul 29 06:12:58 PM PDT 24
Peak memory 207052 kb
Host smart-5b3737a6-b273-49e8-8a2b-f58827d59d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18395
45036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1839545036
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.3708710124
Short name T1872
Test name
Test status
Simulation time 204193119 ps
CPU time 0.95 seconds
Started Jul 29 06:12:58 PM PDT 24
Finished Jul 29 06:12:59 PM PDT 24
Peak memory 207028 kb
Host smart-94ae375d-fc79-454c-9e23-12df50b1e57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37087
10124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.3708710124
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3850732918
Short name T1903
Test name
Test status
Simulation time 165201629 ps
CPU time 0.87 seconds
Started Jul 29 06:12:55 PM PDT 24
Finished Jul 29 06:12:56 PM PDT 24
Peak memory 207184 kb
Host smart-4cb74c9a-bf60-4946-822e-f99978bea614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38507
32918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3850732918
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1664740566
Short name T1213
Test name
Test status
Simulation time 241588025 ps
CPU time 1.04 seconds
Started Jul 29 06:12:55 PM PDT 24
Finished Jul 29 06:12:56 PM PDT 24
Peak memory 207028 kb
Host smart-98a16f86-e22c-4b6f-98d0-f496a9ed8052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16647
40566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1664740566
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.129672770
Short name T1874
Test name
Test status
Simulation time 5558454637 ps
CPU time 164.25 seconds
Started Jul 29 06:12:57 PM PDT 24
Finished Jul 29 06:15:42 PM PDT 24
Peak memory 215576 kb
Host smart-6c1ee38a-fa5e-4f60-aad1-bae655a58e87
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=129672770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.129672770
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2840575228
Short name T1869
Test name
Test status
Simulation time 243435597 ps
CPU time 0.99 seconds
Started Jul 29 06:12:53 PM PDT 24
Finished Jul 29 06:12:54 PM PDT 24
Peak memory 207084 kb
Host smart-671924fe-96a6-4e2b-8a00-1f2e1bc55e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28405
75228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2840575228
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2177894228
Short name T645
Test name
Test status
Simulation time 191255562 ps
CPU time 0.89 seconds
Started Jul 29 06:12:52 PM PDT 24
Finished Jul 29 06:12:53 PM PDT 24
Peak memory 207064 kb
Host smart-cc9594e7-b4be-49ab-b476-eddea0bd445d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21778
94228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2177894228
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.3693503850
Short name T2030
Test name
Test status
Simulation time 815575964 ps
CPU time 2.17 seconds
Started Jul 29 06:12:58 PM PDT 24
Finished Jul 29 06:13:00 PM PDT 24
Peak memory 207056 kb
Host smart-2fe37e7f-19a8-4457-a54b-45705cee8d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36935
03850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3693503850
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.3338898583
Short name T1304
Test name
Test status
Simulation time 4772215001 ps
CPU time 47.69 seconds
Started Jul 29 06:12:52 PM PDT 24
Finished Jul 29 06:13:40 PM PDT 24
Peak memory 215564 kb
Host smart-b16f23c8-cb43-422c-a879-ff9b374bec51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33388
98583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.3338898583
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.4177755383
Short name T2341
Test name
Test status
Simulation time 5018028425 ps
CPU time 33.17 seconds
Started Jul 29 06:12:46 PM PDT 24
Finished Jul 29 06:13:20 PM PDT 24
Peak memory 207356 kb
Host smart-44c4701c-1804-42e3-9813-79e5ba735bbb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177755383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host
_handshake.4177755383
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest
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