Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	170598	1		T1	3		T2	3		T3	2
all_values[1]	170598	1		T1	3		T2	3		T3	2
all_values[2]	170598	1		T1	3		T2	3		T3	2
all_values[3]	170598	1		T1	3		T2	3		T3	2
all_values[4]	170598	1		T1	3		T2	3		T3	2
all_values[5]	170598	1		T1	3		T2	3		T3	2
all_values[6]	170598	1		T1	3		T2	3		T3	2
all_values[7]	170598	1		T1	3		T2	3		T3	2
all_values[8]	170598	1		T1	3		T2	3		T3	2
all_values[9]	170598	1		T1	3		T2	3		T3	2
all_values[10]	170598	1		T1	3		T2	3		T3	2
all_values[11]	170598	1		T1	3		T2	3		T3	2
all_values[12]	170598	1		T1	3		T2	3		T3	2
all_values[13]	170598	1		T1	3		T2	3		T3	2
all_values[14]	170598	1		T1	3		T2	3		T3	2
all_values[15]	170598	1		T1	3		T2	3		T3	2
all_values[16]	170598	1		T1	3		T2	3		T3	2
all_values[17]	170598	1		T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5452282	1		T1	93		T2	94		T3	64
auto[1]	6854	1		T1	3		T2	2		T7	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4672064	1		T1	83		T2	85		T3	54
auto[1]	787072	1		T1	13		T2	11		T3	10

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	143635	1		T2	3		T3	2		T4	2
all_values[0]	auto[0]	auto[1]	26131	1		T29	3		T30	1000		T99	1
all_values[0]	auto[1]	auto[0]	722	1		T1	3		T19	3		T23	3
all_values[0]	auto[1]	auto[1]	110	1		T23	1		T286	1		T287	1
all_values[1]	auto[0]	auto[0]	167330	1		T1	2		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	1599	1		T1	1		T29	3		T4	2
all_values[1]	auto[1]	auto[0]	666	1		T7	1		T8	1		T31	1
all_values[1]	auto[1]	auto[1]	1003	1		T7	1		T8	1		T31	1
all_values[2]	auto[0]	auto[0]	2957	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	167383	1		T1	2		T2	2		T3	1
all_values[2]	auto[1]	auto[0]	134	1		T38	1		T39	1		T40	1
all_values[2]	auto[1]	auto[1]	124	1		T38	1		T39	1		T40	1
all_values[3]	auto[0]	auto[0]	168492	1		T1	3		T2	3		T3	1
all_values[3]	auto[0]	auto[1]	538	1		T3	1		T5	1		T6	1
all_values[3]	auto[1]	auto[0]	1493	1		T54	1394		T197	4		T198	2
all_values[3]	auto[1]	auto[1]	75	1		T54	1		T197	1		T198	4
all_values[4]	auto[0]	auto[0]	2931	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	167519	1		T1	2		T2	2		T3	1
all_values[4]	auto[1]	auto[0]	89	1		T55	1		T197	1		T198	2
all_values[4]	auto[1]	auto[1]	59	1		T55	1		T197	3		T198	3
all_values[5]	auto[0]	auto[0]	170082	1		T1	3		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	353	1		T7	1		T8	1		T31	1
all_values[5]	auto[1]	auto[0]	93	1		T197	1		T198	2		T200	1
all_values[5]	auto[1]	auto[1]	70	1		T197	1		T198	3		T200	3
all_values[6]	auto[0]	auto[0]	170159	1		T1	3		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	267	1		T31	2		T35	2		T9	1
all_values[6]	auto[1]	auto[0]	100	1		T197	3		T198	5		T201	1
all_values[6]	auto[1]	auto[1]	72	1		T197	2		T201	2		T202	1
all_values[7]	auto[0]	auto[0]	114154	1		T2	3		T4	2		T30	2
all_values[7]	auto[0]	auto[1]	56297	1		T1	3		T3	2		T29	3
all_values[7]	auto[1]	auto[0]	103	1		T197	3		T198	1		T200	4
all_values[7]	auto[1]	auto[1]	44	1		T197	3		T201	1		T199	1
all_values[8]	auto[0]	auto[0]	170385	1		T1	3		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	50	1		T197	2		T200	2		T199	1
all_values[8]	auto[1]	auto[0]	110	1		T45	10		T197	1		T198	2
all_values[8]	auto[1]	auto[1]	53	1		T198	1		T201	2		T202	2
all_values[9]	auto[0]	auto[0]	170333	1		T1	3		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	61	1		T197	1		T198	2		T200	2
all_values[9]	auto[1]	auto[0]	123	1		T51	3		T52	3		T53	3
all_values[9]	auto[1]	auto[1]	81	1		T51	2		T52	2		T53	2
all_values[10]	auto[0]	auto[0]	170126	1		T1	3		T2	3		T3	1
all_values[10]	auto[0]	auto[1]	305	1		T3	1		T17	1		T50	2
all_values[10]	auto[1]	auto[0]	90	1		T197	2		T198	1		T200	3
all_values[10]	auto[1]	auto[1]	77	1		T197	2		T198	2		T200	1
all_values[11]	auto[0]	auto[0]	170192	1		T1	3		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	128	1		T2	1		T63	1		T64	1
all_values[11]	auto[1]	auto[0]	152	1		T22	1		T61	1		T62	1
all_values[11]	auto[1]	auto[1]	126	1		T22	1		T61	1		T62	1
all_values[12]	auto[0]	auto[0]	170363	1		T1	3		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	59	1		T65	1		T66	1		T67	1
all_values[12]	auto[1]	auto[0]	114	1		T68	2		T69	2		T70	2
all_values[12]	auto[1]	auto[1]	62	1		T68	1		T69	1		T70	1
all_values[13]	auto[0]	auto[0]	170266	1		T1	3		T2	1		T3	2
all_values[13]	auto[0]	auto[1]	108	1		T65	1		T66	1		T67	1
all_values[13]	auto[1]	auto[0]	125	1		T2	1		T63	1		T64	1
all_values[13]	auto[1]	auto[1]	99	1		T2	1		T63	1		T64	1
all_values[14]	auto[0]	auto[0]	31912	1		T1	3		T2	3		T3	1
all_values[14]	auto[0]	auto[1]	138529	1		T3	1		T4	1		T30	2001
all_values[14]	auto[1]	auto[0]	98	1		T197	1		T199	2		T277	4
all_values[14]	auto[1]	auto[1]	59	1		T198	1		T201	1		T199	3
all_values[15]	auto[0]	auto[0]	2984	1		T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	167456	1		T1	2		T2	2		T3	1
all_values[15]	auto[1]	auto[0]	91	1		T197	1		T198	3		T200	1
all_values[15]	auto[1]	auto[1]	67	1		T197	6		T199	3		T202	3
all_values[16]	auto[0]	auto[0]	169901	1		T1	3		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	493	1		T24	1		T56	1		T57	1
all_values[16]	auto[1]	auto[0]	101	1		T58	4		T59	4		T60	4
all_values[16]	auto[1]	auto[1]	103	1		T58	4		T59	4		T60	4
all_values[17]	auto[0]	auto[0]	112976	1		T4	2		T7	2		T8	2
all_values[17]	auto[0]	auto[1]	57456	1		T1	3		T2	3		T3	2
all_values[17]	auto[1]	auto[0]	110	1		T47	1		T48	1		T49	1
all_values[17]	auto[1]	auto[1]	56	1		T47	1		T48	1		T49	1