Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	132072	1		T1	2		T2	1		T29	1
auto[1]	62969	1		T1	1		T3	17		T29	1

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	31345	1		T30	1000		T5	6		T6	4
max_len_m1	1301	1		T4	2		T36	2		T97	2
max_len_m2	1233	1		T6	6		T37	4		T97	2
max_len_m3	1244	1		T5	2		T6	6		T36	2
five	1611	1		T4	2		T5	8		T6	2
four	1650	1		T5	4		T6	6		T36	2
three	1699	1		T4	2		T5	2		T6	2
one	1781	1		T4	4		T5	2		T6	2
zero	12449	1		T2	1		T3	17		T29	2

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	25652	1		T30	1000		T5	3		T6	2
max_len	auto[1]	5693	1		T5	3		T6	2		T36	1
max_len_m1	auto[0]	820	1		T4	1		T36	1		T97	1
max_len_m1	auto[1]	481	1		T4	1		T36	1		T97	1
max_len_m2	auto[0]	788	1		T6	3		T37	2		T97	1
max_len_m2	auto[1]	445	1		T6	3		T37	2		T97	1
max_len_m3	auto[0]	796	1		T5	1		T6	3		T36	1
max_len_m3	auto[1]	448	1		T5	1		T6	3		T36	1
five	auto[0]	874	1		T4	1		T5	4		T6	1
five	auto[1]	737	1		T4	1		T5	4		T6	1
four	auto[0]	864	1		T5	2		T6	3		T36	1
four	auto[1]	786	1		T5	2		T6	3		T36	1
three	auto[0]	871	1		T4	1		T5	1		T6	1
three	auto[1]	828	1		T4	1		T5	1		T6	1
one	auto[0]	872	1		T4	2		T5	1		T6	1
one	auto[1]	909	1		T4	2		T5	1		T6	1
zero	auto[0]	1023	1		T2	1		T29	1		T4	1
zero	auto[1]	11426	1		T3	17		T29	1		T4	1