Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
56.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	96	48	48	50.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	2	2	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	48	48	50.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	89174	1		T1	2		T29	1		T4	82
auto[1]	57476	1		T1	1		T3	17		T29	1

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	13075	1		T8	2		T17	12		T19	1
endpoints[0x1]	11259	1		T31	2		T5	26		T6	34
endpoints[0x2]	14310	1		T5	26		T6	34		T37	40
endpoints[0x3]	11905	1		T56	1		T99	1		T5	26
endpoints[0x4]	12390	1		T30	1000		T7	2		T24	1
endpoints[0x5]	13702	1		T1	3		T3	17		T23	1
endpoints[0x6]	11320	1		T4	164		T6	34		T92	1
endpoints[0x7]	11335	1		T29	2		T5	26		T6	34
endpoints[0x8]	12091	1		T6	34		T36	256		T110	1
endpoints[0x9]	10749	1		T37	40		T97	16		T147	2
endpoints[0xa]	12932	1		T57	1		T111	1		T79	46
endpoints[0xb]	11582	1		T37	40		T156	1		T149	3

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
nak	0	1	1
ack	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	69202	1		T1	2		T3	11		T4	81
data0	77406	1		T1	1		T3	6		T29	2

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	48	48	50.00	48

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER
[nak , ack]	*	*	--	--	48

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	auto[0]	endpoints[0x0]	3654	1		T5	6		T97	4		T96	1
data1	auto[0]	endpoints[0x1]	2706	1		T5	4		T6	8		T97	4
data1	auto[0]	endpoints[0x2]	4137	1		T5	6		T6	8		T37	9
data1	auto[0]	endpoints[0x3]	2915	1		T5	6		T97	4		T235	14
data1	auto[0]	endpoints[0x4]	3464	1		T30	500		T5	6		T6	8
data1	auto[0]	endpoints[0x5]	4096	1		T1	1		T5	5		T6	6
data1	auto[0]	endpoints[0x6]	2503	1		T4	30		T6	8		T46	1
data1	auto[0]	endpoints[0x7]	3036	1		T5	6		T6	8		T97	4
data1	auto[0]	endpoints[0x8]	3093	1		T6	6		T36	43		T37	10
data1	auto[0]	endpoints[0x9]	2221	1		T37	5		T97	2		T235	19
data1	auto[0]	endpoints[0xa]	3544	1		T79	13		T97	2		T235	14
data1	auto[0]	endpoints[0xb]	3081	1		T37	7		T149	1		T235	17
data1	auto[1]	endpoints[0x0]	2602	1		T17	4		T5	6		T97	4
data1	auto[1]	endpoints[0x1]	2567	1		T5	9		T6	8		T79	9
data1	auto[1]	endpoints[0x2]	2701	1		T5	6		T6	8		T37	10
data1	auto[1]	endpoints[0x3]	2685	1		T5	6		T97	4		T235	14
data1	auto[1]	endpoints[0x4]	2287	1		T5	6		T6	8		T37	10
data1	auto[1]	endpoints[0x5]	2405	1		T1	1		T3	11		T5	8
data1	auto[1]	endpoints[0x6]	2858	1		T4	51		T6	8		T46	1
data1	auto[1]	endpoints[0x7]	2339	1		T5	6		T6	8		T79	8
data1	auto[1]	endpoints[0x8]	2549	1		T6	11		T36	84		T37	10
data1	auto[1]	endpoints[0x9]	2841	1		T37	14		T97	6		T235	14
data1	auto[1]	endpoints[0xa]	2554	1		T79	8		T97	5		T235	15
data1	auto[1]	endpoints[0xb]	2364	1		T37	13		T149	1		T235	13
data0	auto[0]	endpoints[0x0]	4607	1		T8	1		T19	1		T5	7
data0	auto[0]	endpoints[0x1]	3770	1		T31	1		T5	9		T6	9
data0	auto[0]	endpoints[0x2]	5112	1		T5	7		T6	9		T37	11
data0	auto[0]	endpoints[0x3]	3841	1		T56	1		T99	1		T5	7
data0	auto[0]	endpoints[0x4]	4648	1		T30	500		T7	1		T24	1
data0	auto[0]	endpoints[0x5]	5015	1		T1	1		T23	1		T5	8
data0	auto[0]	endpoints[0x6]	3480	1		T4	52		T6	9		T92	1
data0	auto[0]	endpoints[0x7]	3838	1		T29	1		T5	7		T6	9
data0	auto[0]	endpoints[0x8]	4308	1		T6	11		T36	85		T110	1
data0	auto[0]	endpoints[0x9]	3396	1		T37	15		T97	6		T147	1
data0	auto[0]	endpoints[0xa]	4619	1		T57	1		T111	1		T79	18
data0	auto[0]	endpoints[0xb]	4048	1		T37	13		T156	1		T149	1
data0	auto[1]	endpoints[0x0]	2208	1		T8	1		T17	8		T5	7
data0	auto[1]	endpoints[0x1]	2209	1		T31	1		T5	4		T6	9
data0	auto[1]	endpoints[0x2]	2354	1		T5	7		T6	9		T37	10
data0	auto[1]	endpoints[0x3]	2458	1		T5	7		T97	4		T147	1
data0	auto[1]	endpoints[0x4]	1986	1		T7	1		T5	7		T6	9
data0	auto[1]	endpoints[0x5]	2181	1		T3	6		T5	5		T6	6
data0	auto[1]	endpoints[0x6]	2478	1		T4	31		T6	9		T73	1
data0	auto[1]	endpoints[0x7]	2122	1		T29	1		T5	7		T6	9
data0	auto[1]	endpoints[0x8]	2140	1		T6	6		T36	44		T37	10
data0	auto[1]	endpoints[0x9]	2290	1		T37	6		T97	2		T147	1
data0	auto[1]	endpoints[0xa]	2213	1		T79	7		T97	3		T147	1
data0	auto[1]	endpoints[0xb]	2085	1		T37	7		T147	1		T235	14