Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
24.15	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	1	14	93.33
Crosses	192	156	36	18.75

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_out_enable	2	0	2	100.00	100	1	1	2
cp_out_iso	2	0	2	100.00	100	1	1	2
cp_out_stall	2	0	2	100.00	100	1	1	2
cp_pid	3	1	2	66.67	100	1	1	0
cp_rxenable_out	2	0	2	100.00	100	1	1	2
cp_rxenable_setup	2	0	2	100.00	100	1	1	2
cp_set_nak_out	2	0	2	100.00	100	1	1	2

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	192	156	36	18.75	100	1	1	0

Summary for Variable cp_out_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_enable

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	18474	1		T2	1		T21	16		T79	714
auto[1]	98202	1		T1	2		T29	1		T4	82

---

Summary for Variable cp_out_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_iso

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	116626	1		T1	2		T2	1		T29	1
auto[1]	50	1		T93	1		T92	1		T109	1

---

Summary for Variable cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_stall

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	103351	1		T1	1		T2	1		T29	1
auto[1]	13325	1		T1	1		T21	4		T24	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
ignore_pre[PidTypePre]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	20973	1		T1	1		T4	38		T19	1
pkt_types[PidTypeOutToken]	95617	1		T1	1		T2	1		T29	1

---

Summary for Variable cp_rxenable_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_out

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	17610	1		T2	1		T19	1		T21	8
auto[1]	99066	1		T1	2		T29	1		T4	82

---

Summary for Variable cp_rxenable_setup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_setup

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	80830	1		T2	1		T29	1		T30	1000
auto[1]	35846	1		T1	2		T4	82		T21	3

---

Summary for Variable cp_set_nak_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_set_nak_out

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	116526	1		T1	2		T2	1		T29	1
auto[1]	150	1		T24	1		T56	1		T146	1

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_out_enable cp_rxenable_setup cp_rxenable_out cp_set_nak_out cp_out_iso cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	192	156	36	18.75	156

Automatically Generated Cross Bins for cr_pid_x_epconfig

Element holes

cp_pid	cp_out_enable	cp_rxenable_setup	cp_rxenable_out	cp_set_nak_out	cp_out_iso	cp_out_stall	COUNT	AT LEAST	NUMBER
[ignore_pre[PidTypePre]]	*	*	*	*	*	*	--	--	64
[pkt_types[PidTypeSetupToken]]	*	*	*	[auto[0]]	[auto[1]]	*	--	--	16
[pkt_types[PidTypeSetupToken]]	*	*	*	[auto[1]]	*	*	--	--	32
[pkt_types[PidTypeOutToken]]	[auto[0]]	*	*	[auto[0]]	[auto[1]]	*	--	--	8
[pkt_types[PidTypeOutToken]]	[auto[0]]	*	*	[auto[1]]	*	*	--	--	16
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	--	--	2
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[1]]	*	[auto[0]]	[auto[1]]	*	--	--	4
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[1]]	*	[auto[1]]	*	*	--	--	8

Uncovered bins

cp_pid	cp_out_enable	cp_rxenable_setup	cp_rxenable_out	cp_set_nak_out	cp_out_iso	cp_out_stall	COUNT	AT LEAST	NUMBER
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_pid

cp_out_enable

cp_rxenable_setup

cp_rxenable_out

cp_set_nak_out

cp_out_iso

cp_out_stall

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

891

1

T21

3

T154

4

T65

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

724

1

T79

61

T95

4

T80

13

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

812

1

T21

2

T79

33

T95

5

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

841

1

T21

1

T79

47

T81

30

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

718

1

T107

1

T154

4

T65

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

690

1

T80

12

T81

31

T82

45

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

633

1

T107

7

T80

12

T81

34

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

734

1

T21

1

T79

88

T95

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

659

1

T19

1

T108

1

T278

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

601

1

T80

7

T82

23

T170

26

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

908

1

T79

34

T154

1

T65

3

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

633

1

T81

26

T82

37

T170

26

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1599

1

T79

29

T84

1

T156

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

34

1

T79

1

T82

1

T47

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

10348

1

T4

38

T5

13

T6

16

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

148

1

T1

1

T46

1

T79

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1936

1

T2

1

T21

5

T64

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

1532

1

T79

134

T95

1

T80

15

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1662

1

T21

2

T79

61

T95

3

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1675

1

T79

111

T107

1

T81

61

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1334

1

T107

3

T154

4

T65

11

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1406

1

T80

28

T81

58

T82

98

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1247

1

T107

7

T80

24

T81

64

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1606

1

T21

2

T79

179

T80

34

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1266

1

T57

1

T110

1

T279

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

1154

1

T80

23

T82

32

T170

51

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T112

1

T127

1

T135

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

63934

1

T29

1

T30

1000

T7

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1350

1

T111

1

T81

57

T280

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

50

1

T93

1

T92

1

T109

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T112

1

T127

1

T135

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

50

1

T24

1

T56

1

T146

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

2928

1

T79

52

T81

130

T82

79

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

55

1

T79

5

T170

3

T281

3

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

12240

1

T1

1

T4

44

T5

13

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

92

1

T79

4

T89

1

T80

4