Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	170598	1		T1	3		T2	3		T3	2
all_pins[1]	170598	1		T1	3		T2	3		T3	2
all_pins[2]	170598	1		T1	3		T2	3		T3	2
all_pins[3]	170598	1		T1	3		T2	3		T3	2
all_pins[4]	170598	1		T1	3		T2	3		T3	2
all_pins[5]	170598	1		T1	3		T2	3		T3	2
all_pins[6]	170598	1		T1	3		T2	3		T3	2
all_pins[7]	170598	1		T1	3		T2	3		T3	2
all_pins[8]	170598	1		T1	3		T2	3		T3	2
all_pins[9]	170598	1		T1	3		T2	3		T3	2
all_pins[10]	170598	1		T1	3		T2	3		T3	2
all_pins[11]	170598	1		T1	3		T2	3		T3	2
all_pins[12]	170598	1		T1	3		T2	3		T3	2
all_pins[13]	170598	1		T1	3		T2	3		T3	2
all_pins[14]	170598	1		T1	3		T2	3		T3	2
all_pins[15]	170598	1		T1	3		T2	3		T3	2
all_pins[16]	170598	1		T1	3		T2	3		T3	2
all_pins[17]	170598	1		T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5456796	1		T1	96		T2	95		T3	64
values[0x1]	2340	1		T2	1		T7	1		T8	1
transitions[0x0=>0x1]	2075	1		T2	1		T7	1		T8	1
transitions[0x1=>0x0]	2075	1		T2	1		T7	1		T8	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	170488	1		T1	3		T2	3		T3	2
all_pins[0]	values[0x1]	110	1		T23	1		T286	1		T287	1
all_pins[0]	transitions[0x0=>0x1]	99	1		T23	1		T286	1		T287	1
all_pins[0]	transitions[0x1=>0x0]	992	1		T7	1		T8	1		T31	1
all_pins[1]	values[0x0]	169595	1		T1	3		T2	3		T3	2
all_pins[1]	values[0x1]	1003	1		T7	1		T8	1		T31	1
all_pins[1]	transitions[0x0=>0x1]	984	1		T7	1		T8	1		T31	1
all_pins[1]	transitions[0x1=>0x0]	105	1		T38	1		T39	1		T40	1
all_pins[2]	values[0x0]	170474	1		T1	3		T2	3		T3	2
all_pins[2]	values[0x1]	124	1		T38	1		T39	1		T40	1
all_pins[2]	transitions[0x0=>0x1]	97	1		T38	1		T39	1		T40	1
all_pins[2]	transitions[0x1=>0x0]	48	1		T54	1		T197	1		T198	4
all_pins[3]	values[0x0]	170523	1		T1	3		T2	3		T3	2
all_pins[3]	values[0x1]	75	1		T54	1		T197	1		T198	4
all_pins[3]	transitions[0x0=>0x1]	59	1		T54	1		T197	1		T198	3
all_pins[3]	transitions[0x1=>0x0]	43	1		T55	1		T197	3		T198	2
all_pins[4]	values[0x0]	170539	1		T1	3		T2	3		T3	2
all_pins[4]	values[0x1]	59	1		T55	1		T197	3		T198	3
all_pins[4]	transitions[0x0=>0x1]	45	1		T55	1		T197	3		T198	2
all_pins[4]	transitions[0x1=>0x0]	56	1		T197	1		T198	2		T200	3
all_pins[5]	values[0x0]	170528	1		T1	3		T2	3		T3	2
all_pins[5]	values[0x1]	70	1		T197	1		T198	3		T200	3
all_pins[5]	transitions[0x0=>0x1]	53	1		T197	1		T198	3		T200	3
all_pins[5]	transitions[0x1=>0x0]	55	1		T197	2		T201	2		T202	1
all_pins[6]	values[0x0]	170526	1		T1	3		T2	3		T3	2
all_pins[6]	values[0x1]	72	1		T197	2		T201	2		T202	1
all_pins[6]	transitions[0x0=>0x1]	62	1		T197	1		T201	2		T202	1
all_pins[6]	transitions[0x1=>0x0]	34	1		T197	2		T201	1		T199	1
all_pins[7]	values[0x0]	170554	1		T1	3		T2	3		T3	2
all_pins[7]	values[0x1]	44	1		T197	3		T201	1		T199	1
all_pins[7]	transitions[0x0=>0x1]	32	1		T197	3		T201	1		T199	1
all_pins[7]	transitions[0x1=>0x0]	41	1		T198	1		T201	2		T202	2
all_pins[8]	values[0x0]	170545	1		T1	3		T2	3		T3	2
all_pins[8]	values[0x1]	53	1		T198	1		T201	2		T202	2
all_pins[8]	transitions[0x0=>0x1]	41	1		T198	1		T201	2		T202	2
all_pins[8]	transitions[0x1=>0x0]	69	1		T51	2		T52	2		T53	2
all_pins[9]	values[0x0]	170517	1		T1	3		T2	3		T3	2
all_pins[9]	values[0x1]	81	1		T51	2		T52	2		T53	2
all_pins[9]	transitions[0x0=>0x1]	61	1		T51	2		T52	2		T53	2
all_pins[9]	transitions[0x1=>0x0]	57	1		T197	2		T198	1		T200	1
all_pins[10]	values[0x0]	170521	1		T1	3		T2	3		T3	2
all_pins[10]	values[0x1]	77	1		T197	2		T198	2		T200	1
all_pins[10]	transitions[0x0=>0x1]	57	1		T197	2		T198	2		T200	1
all_pins[10]	transitions[0x1=>0x0]	106	1		T22	1		T61	1		T62	1
all_pins[11]	values[0x0]	170472	1		T1	3		T2	3		T3	2
all_pins[11]	values[0x1]	126	1		T22	1		T61	1		T62	1
all_pins[11]	transitions[0x0=>0x1]	105	1		T22	1		T61	1		T62	1
all_pins[11]	transitions[0x1=>0x0]	41	1		T68	1		T69	1		T70	1
all_pins[12]	values[0x0]	170536	1		T1	3		T2	3		T3	2
all_pins[12]	values[0x1]	62	1		T68	1		T69	1		T70	1
all_pins[12]	transitions[0x0=>0x1]	53	1		T68	1		T69	1		T70	1
all_pins[12]	transitions[0x1=>0x0]	90	1		T2	1		T63	1		T64	1
all_pins[13]	values[0x0]	170499	1		T1	3		T2	2		T3	2
all_pins[13]	values[0x1]	99	1		T2	1		T63	1		T64	1
all_pins[13]	transitions[0x0=>0x1]	90	1		T2	1		T63	1		T64	1
all_pins[13]	transitions[0x1=>0x0]	50	1		T198	1		T201	1		T199	3
all_pins[14]	values[0x0]	170539	1		T1	3		T2	3		T3	2
all_pins[14]	values[0x1]	59	1		T198	1		T201	1		T199	3
all_pins[14]	transitions[0x0=>0x1]	43	1		T198	1		T201	1		T199	1
all_pins[14]	transitions[0x1=>0x0]	51	1		T197	6		T199	1		T202	2
all_pins[15]	values[0x0]	170531	1		T1	3		T2	3		T3	2
all_pins[15]	values[0x1]	67	1		T197	6		T199	3		T202	3
all_pins[15]	transitions[0x0=>0x1]	49	1		T197	6		T199	1		T202	3
all_pins[15]	transitions[0x1=>0x0]	85	1		T58	4		T59	4		T60	4
all_pins[16]	values[0x0]	170495	1		T1	3		T2	3		T3	2
all_pins[16]	values[0x1]	103	1		T58	4		T59	4		T60	4
all_pins[16]	transitions[0x0=>0x1]	89	1		T58	4		T59	4		T60	4
all_pins[16]	transitions[0x1=>0x0]	42	1		T47	1		T48	1		T49	1
all_pins[17]	values[0x0]	170542	1		T1	3		T2	3		T3	2
all_pins[17]	values[0x1]	56	1		T47	1		T48	1		T49	1
all_pins[17]	transitions[0x0=>0x1]	56	1		T47	1		T48	1		T49	1