Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4817	1		T79	114		T65	2		T80	38
invalid_ep[0xd]	4778	1		T79	122		T65	2		T80	38
invalid_ep[0xe]	4798	1		T79	100		T65	3		T80	47
invalid_ep[0xf]	4672	1		T79	127		T65	3		T80	48
endpoints[0x0]	16848	1		T2	1		T8	2		T17	12
endpoints[0x1]	15413	1		T31	2		T5	27		T6	35
endpoints[0x2]	18054	1		T5	27		T6	35		T37	41
endpoints[0x3]	15917	1		T56	1		T99	1		T5	27
endpoints[0x4]	16367	1		T30	1000		T7	2		T21	8
endpoints[0x5]	17290	1		T1	3		T3	17		T23	1
endpoints[0x6]	14782	1		T4	165		T6	35		T92	1
endpoints[0x7]	15221	1		T29	2		T21	3		T5	27
endpoints[0x8]	15651	1		T6	35		T36	257		T110	1
endpoints[0x9]	14486	1		T37	41		T79	103		T97	17
endpoints[0xa]	16152	1		T21	3		T57	1		T111	1
endpoints[0xb]	15313	1		T22	1		T37	41		T79	133

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	24682	1		T1	1		T4	38		T19	1
pkt_types[PidTypeOutToken]	107324	1		T1	1		T2	1		T29	1
pkt_types[PidTypeInToken]	78467	1		T1	1		T3	17		T29	1

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	959	1		T79	30		T80	11		T81	31
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	929	1		T79	29		T80	8		T81	35
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	924	1		T79	26		T80	9		T81	29
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	897	1		T79	25		T80	16		T81	27
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1830	1		T19	1		T21	2		T79	33
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1784	1		T5	8		T79	19		T95	3
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1823	1		T37	5		T79	32		T151	7
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1633	1		T79	27		T95	4		T150	6
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1686	1		T21	3		T79	30		T97	2
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1572	1		T1	1		T5	5		T6	9
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1875	1		T4	38		T46	1		T79	28
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1554	1		T21	1		T79	29		T97	3
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1748	1		T6	7		T36	63		T79	34
pkt_types[PidTypeSetupToken]	endpoints[0x9]	2051	1		T37	11		T79	28		T97	4
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1688	1		T21	1		T79	20		T97	4
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1729	1		T37	8		T79	33		T156	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	2961	1		T79	61		T65	2		T80	21
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	2949	1		T79	53		T65	2		T80	19
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	2943	1		T79	48		T65	3		T80	24
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	2854	1		T79	73		T65	3		T80	20
pkt_types[PidTypeOutToken]	endpoints[0x0]	8830	1		T2	1		T8	1		T21	2
pkt_types[PidTypeOutToken]	endpoints[0x1]	7041	1		T31	1		T5	5		T6	17
pkt_types[PidTypeOutToken]	endpoints[0x2]	9703	1		T5	13		T6	17		T37	15
pkt_types[PidTypeOutToken]	endpoints[0x3]	7747	1		T56	1		T99	1		T5	13
pkt_types[PidTypeOutToken]	endpoints[0x4]	8664	1		T30	1000		T7	1		T21	5
pkt_types[PidTypeOutToken]	endpoints[0x5]	9675	1		T1	1		T23	1		T5	8
pkt_types[PidTypeOutToken]	endpoints[0x6]	6394	1		T4	44		T6	17		T92	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	7537	1		T29	1		T21	2		T5	13
pkt_types[PidTypeOutToken]	endpoints[0x8]	7852	1		T6	10		T36	65		T110	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	5754	1		T37	9		T79	56		T97	4
pkt_types[PidTypeOutToken]	endpoints[0xa]	8596	1		T57	1		T111	1		T79	56
pkt_types[PidTypeOutToken]	endpoints[0xb]	7824	1		T22	1		T37	12		T79	70
pkt_types[PidTypeInToken]	invalid_ep[0xc]	897	1		T79	23		T80	6		T81	36
pkt_types[PidTypeInToken]	invalid_ep[0xd]	900	1		T79	40		T80	11		T81	26
pkt_types[PidTypeInToken]	invalid_ep[0xe]	931	1		T79	26		T80	14		T81	42
pkt_types[PidTypeInToken]	invalid_ep[0xf]	921	1		T79	29		T80	12		T81	24
pkt_types[PidTypeInToken]	endpoints[0x0]	6185	1		T8	1		T17	12		T5	14
pkt_types[PidTypeInToken]	endpoints[0x1]	6581	1		T31	1		T5	14		T6	18
pkt_types[PidTypeInToken]	endpoints[0x2]	6519	1		T5	14		T6	18		T37	21
pkt_types[PidTypeInToken]	endpoints[0x3]	6533	1		T5	14		T79	30		T97	9
pkt_types[PidTypeInToken]	endpoints[0x4]	6012	1		T7	1		T5	14		T6	18
pkt_types[PidTypeInToken]	endpoints[0x5]	6033	1		T1	1		T3	17		T5	14
pkt_types[PidTypeInToken]	endpoints[0x6]	6501	1		T4	83		T6	18		T73	1
pkt_types[PidTypeInToken]	endpoints[0x7]	6120	1		T29	1		T5	14		T6	18
pkt_types[PidTypeInToken]	endpoints[0x8]	6040	1		T6	18		T36	129		T37	21
pkt_types[PidTypeInToken]	endpoints[0x9]	6675	1		T37	21		T79	19		T97	9
pkt_types[PidTypeInToken]	endpoints[0xa]	5860	1		T21	2		T79	30		T97	9
pkt_types[PidTypeInToken]	endpoints[0xb]	5759	1		T37	21		T79	30		T149	1