Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T197	7		T198	7		T200	4
all_values[1]	272	1		T197	7		T198	7		T200	4
all_values[2]	272	1		T197	7		T198	7		T200	4
all_values[3]	272	1		T197	7		T198	7		T200	4
all_values[4]	272	1		T197	7		T198	7		T200	4
all_values[5]	272	1		T197	7		T198	7		T200	4
all_values[6]	272	1		T197	7		T198	7		T200	4
all_values[7]	272	1		T197	7		T198	7		T200	4
all_values[8]	272	1		T197	7		T198	7		T200	4
all_values[9]	272	1		T197	7		T198	7		T200	4
all_values[10]	272	1		T197	7		T198	7		T200	4
all_values[11]	272	1		T197	7		T198	7		T200	4
all_values[12]	272	1		T197	7		T198	7		T200	4
all_values[13]	272	1		T197	7		T198	7		T200	4
all_values[14]	272	1		T197	7		T198	7		T200	4
all_values[15]	272	1		T197	7		T198	7		T200	4
all_values[16]	272	1		T197	7		T198	7		T200	4
all_values[17]	272	1		T197	7		T198	7		T200	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6482	1		T197	161		T198	166		T200	102
auto[1]	2222	1		T197	63		T198	58		T200	26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5980	1		T197	146		T198	158		T200	89
auto[1]	2724	1		T197	78		T198	66		T200	39

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5200	1		T197	128		T198	132		T200	82
auto[1]	3504	1		T197	96		T198	92		T200	46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	86	1		T197	2		T198	1		T200	4
all_values[0]	auto[0]	auto[1]	auto[0]	73	1		T197	1		T198	1		T199	1
all_values[0]	auto[1]	auto[0]	auto[1]	61	1		T197	2		T198	2		T201	2
all_values[0]	auto[1]	auto[1]	auto[1]	52	1		T197	2		T198	3		T199	1
all_values[1]	auto[0]	auto[0]	auto[0]	81	1		T197	1		T198	1		T201	1
all_values[1]	auto[0]	auto[1]	auto[0]	81	1		T197	2		T198	2		T200	4
all_values[1]	auto[1]	auto[0]	auto[1]	65	1		T198	3		T202	2		T282	4
all_values[1]	auto[1]	auto[1]	auto[1]	45	1		T197	4		T198	1		T202	1
all_values[2]	auto[0]	auto[0]	auto[0]	49	1		T197	1		T198	1		T282	1
all_values[2]	auto[0]	auto[0]	auto[1]	53	1		T198	1		T200	3		T201	2
all_values[2]	auto[0]	auto[1]	auto[0]	41	1		T198	4		T282	1		T283	1
all_values[2]	auto[0]	auto[1]	auto[1]	34	1		T197	1		T202	1		T282	1
all_values[2]	auto[1]	auto[0]	auto[1]	48	1		T197	2		T198	1		T200	1
all_values[2]	auto[1]	auto[1]	auto[1]	47	1		T197	3		T201	1		T202	2
all_values[3]	auto[0]	auto[0]	auto[0]	52	1		T198	1		T200	2		T282	2
all_values[3]	auto[0]	auto[0]	auto[1]	27	1		T197	4		T202	1		T282	1
all_values[3]	auto[0]	auto[1]	auto[0]	49	1		T197	1		T200	2		T201	2
all_values[3]	auto[0]	auto[1]	auto[1]	37	1		T198	1		T199	1		T277	1
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T198	1		T201	1		T199	2
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T197	2		T198	4		T201	1
all_values[4]	auto[0]	auto[0]	auto[0]	52	1		T200	2		T199	1		T202	1
all_values[4]	auto[0]	auto[0]	auto[1]	34	1		T197	3		T198	1		T199	1
all_values[4]	auto[0]	auto[1]	auto[0]	46	1		T198	1		T202	1		T282	1
all_values[4]	auto[0]	auto[1]	auto[1]	27	1		T197	2		T198	1		T201	2
all_values[4]	auto[1]	auto[0]	auto[1]	71	1		T197	2		T198	1		T200	2
all_values[4]	auto[1]	auto[1]	auto[1]	42	1		T198	3		T201	1		T202	1
all_values[5]	auto[0]	auto[0]	auto[0]	56	1		T197	1		T198	1		T199	3
all_values[5]	auto[0]	auto[0]	auto[1]	26	1		T197	2		T201	1		T284	1
all_values[5]	auto[0]	auto[1]	auto[0]	51	1		T197	1		T198	1		T199	1
all_values[5]	auto[0]	auto[1]	auto[1]	29	1		T198	1		T200	3		T202	1
all_values[5]	auto[1]	auto[0]	auto[1]	56	1		T197	2		T198	2		T201	2
all_values[5]	auto[1]	auto[1]	auto[1]	54	1		T197	1		T198	2		T200	1
all_values[6]	auto[0]	auto[0]	auto[0]	57	1		T197	2		T198	4		T200	1
all_values[6]	auto[0]	auto[0]	auto[1]	26	1		T200	1		T277	1		T284	2
all_values[6]	auto[0]	auto[1]	auto[0]	50	1		T197	2		T198	2		T199	3
all_values[6]	auto[0]	auto[1]	auto[1]	30	1		T197	1		T201	1		T282	1
all_values[6]	auto[1]	auto[0]	auto[1]	60	1		T197	2		T198	1		T200	2
all_values[6]	auto[1]	auto[1]	auto[1]	49	1		T201	1		T202	1		T282	2
all_values[7]	auto[0]	auto[0]	auto[0]	91	1		T197	1		T198	5		T200	1
all_values[7]	auto[0]	auto[1]	auto[0]	71	1		T197	2		T200	2		T199	1
all_values[7]	auto[1]	auto[0]	auto[1]	61	1		T197	1		T198	1		T200	1
all_values[7]	auto[1]	auto[1]	auto[1]	49	1		T197	3		T198	1		T201	1
all_values[8]	auto[0]	auto[0]	auto[0]	99	1		T197	4		T198	3		T201	1
all_values[8]	auto[0]	auto[1]	auto[0]	70	1		T197	1		T198	3		T200	2
all_values[8]	auto[1]	auto[0]	auto[1]	52	1		T197	2		T200	2		T201	1
all_values[8]	auto[1]	auto[1]	auto[1]	51	1		T198	1		T201	1		T202	2
all_values[9]	auto[0]	auto[0]	auto[0]	57	1		T197	1		T201	1		T199	1
all_values[9]	auto[0]	auto[0]	auto[1]	24	1		T200	1		T202	1		T282	2
all_values[9]	auto[0]	auto[1]	auto[0]	58	1		T197	1		T198	1		T201	2
all_values[9]	auto[0]	auto[1]	auto[1]	25	1		T197	1		T198	1		T199	1
all_values[9]	auto[1]	auto[0]	auto[1]	51	1		T197	2		T198	3		T200	1
all_values[9]	auto[1]	auto[1]	auto[1]	57	1		T197	2		T198	2		T200	2
all_values[10]	auto[0]	auto[0]	auto[0]	52	1		T197	1		T198	3		T199	2
all_values[10]	auto[0]	auto[0]	auto[1]	25	1		T201	1		T282	1		T283	1
all_values[10]	auto[0]	auto[1]	auto[0]	51	1		T198	1		T200	2		T199	1
all_values[10]	auto[0]	auto[1]	auto[1]	31	1		T197	1		T198	1		T201	1
all_values[10]	auto[1]	auto[0]	auto[1]	66	1		T197	1		T200	2		T201	1
all_values[10]	auto[1]	auto[1]	auto[1]	47	1		T197	4		T198	2		T201	1
all_values[11]	auto[0]	auto[0]	auto[0]	53	1		T197	1		T198	2		T202	4
all_values[11]	auto[0]	auto[0]	auto[1]	23	1		T197	1		T282	2		T283	2
all_values[11]	auto[0]	auto[1]	auto[0]	55	1		T197	3		T198	4		T201	2
all_values[11]	auto[0]	auto[1]	auto[1]	27	1		T200	2		T199	2		T282	1
all_values[11]	auto[1]	auto[0]	auto[1]	57	1		T198	1		T201	1		T199	1
all_values[11]	auto[1]	auto[1]	auto[1]	57	1		T197	2		T200	2		T201	1
all_values[12]	auto[0]	auto[0]	auto[0]	84	1		T197	2		T198	3		T200	2
all_values[12]	auto[0]	auto[0]	auto[1]	16	1		T202	1		T282	1		T277	1
all_values[12]	auto[0]	auto[1]	auto[0]	49	1		T197	2		T198	1		T282	1
all_values[12]	auto[0]	auto[1]	auto[1]	26	1		T197	1		T200	1		T199	1
all_values[12]	auto[1]	auto[0]	auto[1]	59	1		T197	1		T198	2		T199	2
all_values[12]	auto[1]	auto[1]	auto[1]	38	1		T197	1		T198	1		T200	1
all_values[13]	auto[0]	auto[0]	auto[0]	54	1		T197	1		T200	2		T201	1
all_values[13]	auto[0]	auto[0]	auto[1]	44	1		T197	2		T198	1		T200	1
all_values[13]	auto[0]	auto[1]	auto[0]	41	1		T198	1		T201	1		T199	1
all_values[13]	auto[0]	auto[1]	auto[1]	18	1		T197	1		T277	1		T285	1
all_values[13]	auto[1]	auto[0]	auto[1]	74	1		T197	2		T198	2		T200	1
all_values[13]	auto[1]	auto[1]	auto[1]	41	1		T197	1		T198	3		T202	3
all_values[14]	auto[0]	auto[0]	auto[0]	70	1		T197	2		T198	1		T200	1
all_values[14]	auto[0]	auto[0]	auto[1]	25	1		T197	2		T198	1		T200	1
all_values[14]	auto[0]	auto[1]	auto[0]	44	1		T197	1		T277	2		T283	3
all_values[14]	auto[0]	auto[1]	auto[1]	26	1		T198	1		T199	2		T202	1
all_values[14]	auto[1]	auto[0]	auto[1]	67	1		T197	2		T198	4		T200	2
all_values[14]	auto[1]	auto[1]	auto[1]	40	1		T199	1		T202	1		T282	2
all_values[15]	auto[0]	auto[0]	auto[0]	56	1		T198	1		T201	2		T202	1
all_values[15]	auto[0]	auto[0]	auto[1]	25	1		T197	1		T200	1		T201	1
all_values[15]	auto[0]	auto[1]	auto[0]	57	1		T198	3		T200	2		T202	2
all_values[15]	auto[0]	auto[1]	auto[1]	27	1		T197	3		T199	1		T202	1
all_values[15]	auto[1]	auto[0]	auto[1]	61	1		T198	2		T200	1		T201	1
all_values[15]	auto[1]	auto[1]	auto[1]	46	1		T197	3		T198	1		T199	1
all_values[16]	auto[0]	auto[0]	auto[0]	37	1		T197	2		T198	3		T200	2
all_values[16]	auto[0]	auto[0]	auto[1]	38	1		T200	1		T202	1		T284	2
all_values[16]	auto[0]	auto[1]	auto[0]	32	1		T197	4		T198	1		T202	1
all_values[16]	auto[0]	auto[1]	auto[1]	39	1		T201	1		T199	2		T202	1
all_values[16]	auto[1]	auto[0]	auto[1]	67	1		T198	3		T200	1		T201	1
all_values[16]	auto[1]	auto[1]	auto[1]	59	1		T197	1		T201	2		T283	2
all_values[17]	auto[0]	auto[0]	auto[0]	102	1		T197	4		T198	3		T200	2
all_values[17]	auto[0]	auto[1]	auto[0]	65	1		T197	1		T198	1		T201	1
all_values[17]	auto[1]	auto[0]	auto[1]	64	1		T197	1		T198	2		T200	2
all_values[17]	auto[1]	auto[1]	auto[1]	41	1		T197	1		T198	1		T199	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal