Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.03 97.79 93.65 97.44 71.88 96.17 98.17 75.11


Total test records in report: 2978
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T2812 /workspace/coverage/default/0.usbdev_out_stall.2070237492 Jul 30 06:27:50 PM PDT 24 Jul 30 06:27:51 PM PDT 24 191368805 ps
T2813 /workspace/coverage/default/46.usbdev_in_iso.1781169103 Jul 30 06:34:34 PM PDT 24 Jul 30 06:34:35 PM PDT 24 182259414 ps
T2814 /workspace/coverage/default/7.usbdev_link_suspend.1930984450 Jul 30 06:29:13 PM PDT 24 Jul 30 06:29:18 PM PDT 24 3381682682 ps
T2815 /workspace/coverage/default/35.usbdev_data_toggle_restore.3404086511 Jul 30 06:32:59 PM PDT 24 Jul 30 06:33:00 PM PDT 24 349394261 ps
T2816 /workspace/coverage/default/9.usbdev_bitstuff_err.4187844059 Jul 30 06:29:05 PM PDT 24 Jul 30 06:29:06 PM PDT 24 150932255 ps
T2817 /workspace/coverage/default/17.usbdev_iso_retraction.741948814 Jul 30 06:30:27 PM PDT 24 Jul 30 06:31:00 PM PDT 24 5122400428 ps
T2818 /workspace/coverage/default/14.usbdev_random_length_out_transaction.2999254918 Jul 30 06:30:14 PM PDT 24 Jul 30 06:30:15 PM PDT 24 188478173 ps
T2819 /workspace/coverage/default/6.usbdev_in_trans.2370239851 Jul 30 06:28:52 PM PDT 24 Jul 30 06:28:53 PM PDT 24 227298485 ps
T2820 /workspace/coverage/default/0.usbdev_disconnected.4093254745 Jul 30 06:27:32 PM PDT 24 Jul 30 06:27:33 PM PDT 24 146703064 ps
T2821 /workspace/coverage/default/31.usbdev_pending_in_trans.2387510432 Jul 30 06:32:33 PM PDT 24 Jul 30 06:32:34 PM PDT 24 189231991 ps
T2822 /workspace/coverage/default/44.usbdev_stream_len_max.3552442728 Jul 30 06:34:28 PM PDT 24 Jul 30 06:34:31 PM PDT 24 931425555 ps
T2823 /workspace/coverage/default/4.usbdev_stall_trans.1961419531 Jul 30 06:28:43 PM PDT 24 Jul 30 06:28:44 PM PDT 24 239871572 ps
T2824 /workspace/coverage/default/41.usbdev_in_trans.1063166231 Jul 30 06:33:46 PM PDT 24 Jul 30 06:33:47 PM PDT 24 203807557 ps
T2825 /workspace/coverage/default/42.usbdev_aon_wake_resume.1272054111 Jul 30 06:34:18 PM PDT 24 Jul 30 06:34:47 PM PDT 24 23390561891 ps
T2826 /workspace/coverage/default/30.usbdev_link_in_err.78217836 Jul 30 06:32:40 PM PDT 24 Jul 30 06:32:41 PM PDT 24 179154924 ps
T2827 /workspace/coverage/default/2.usbdev_min_length_in_transaction.1402216516 Jul 30 06:28:09 PM PDT 24 Jul 30 06:28:10 PM PDT 24 175603693 ps
T2828 /workspace/coverage/default/30.usbdev_spurious_pids_ignored.1927843138 Jul 30 06:32:36 PM PDT 24 Jul 30 06:33:01 PM PDT 24 3157022830 ps
T2829 /workspace/coverage/default/48.usbdev_invalid_sync.249502548 Jul 30 06:34:46 PM PDT 24 Jul 30 06:35:28 PM PDT 24 5667799037 ps
T2830 /workspace/coverage/default/40.usbdev_max_length_out_transaction.1341180852 Jul 30 06:33:37 PM PDT 24 Jul 30 06:33:38 PM PDT 24 193081990 ps
T2831 /workspace/coverage/default/41.usbdev_rx_crc_err.704668423 Jul 30 06:33:55 PM PDT 24 Jul 30 06:33:56 PM PDT 24 174750717 ps
T2832 /workspace/coverage/default/20.usbdev_iso_retraction.2011565882 Jul 30 06:30:52 PM PDT 24 Jul 30 06:31:37 PM PDT 24 3429728877 ps
T2833 /workspace/coverage/default/19.usbdev_out_stall.2378180665 Jul 30 06:30:49 PM PDT 24 Jul 30 06:30:50 PM PDT 24 146781094 ps
T2834 /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.912051902 Jul 30 06:29:28 PM PDT 24 Jul 30 06:31:47 PM PDT 24 4701492887 ps
T2835 /workspace/coverage/default/30.usbdev_random_length_in_transaction.2119175578 Jul 30 06:32:39 PM PDT 24 Jul 30 06:32:40 PM PDT 24 162544945 ps
T2836 /workspace/coverage/default/10.usbdev_in_stall.3822915191 Jul 30 06:29:29 PM PDT 24 Jul 30 06:29:30 PM PDT 24 159794713 ps
T2837 /workspace/coverage/default/41.usbdev_alert_test.2914705444 Jul 30 06:34:11 PM PDT 24 Jul 30 06:34:12 PM PDT 24 57299674 ps
T2838 /workspace/coverage/default/21.usbdev_setup_stage.2309135002 Jul 30 06:31:06 PM PDT 24 Jul 30 06:31:07 PM PDT 24 180774408 ps
T2839 /workspace/coverage/default/38.usbdev_streaming_out.1534841869 Jul 30 06:33:32 PM PDT 24 Jul 30 06:35:56 PM PDT 24 4933956464 ps
T2840 /workspace/coverage/default/5.usbdev_rand_bus_disconnects.776149692 Jul 30 06:28:46 PM PDT 24 Jul 30 06:35:23 PM PDT 24 13634848710 ps
T2841 /workspace/coverage/default/6.usbdev_invalid_sync.4045663011 Jul 30 06:28:50 PM PDT 24 Jul 30 06:29:58 PM PDT 24 6471751421 ps
T2842 /workspace/coverage/default/38.usbdev_aon_wake_reset.2339594693 Jul 30 06:33:37 PM PDT 24 Jul 30 06:33:53 PM PDT 24 13547358427 ps
T2843 /workspace/coverage/default/1.usbdev_setup_stage.2226905240 Jul 30 06:28:00 PM PDT 24 Jul 30 06:28:01 PM PDT 24 148372475 ps
T2844 /workspace/coverage/default/19.usbdev_fifo_rst.1468077883 Jul 30 06:30:48 PM PDT 24 Jul 30 06:30:50 PM PDT 24 189450115 ps
T2845 /workspace/coverage/default/1.usbdev_min_length_in_transaction.2201858024 Jul 30 06:27:59 PM PDT 24 Jul 30 06:28:00 PM PDT 24 151075333 ps
T2846 /workspace/coverage/default/26.usbdev_max_length_in_transaction.103255537 Jul 30 06:31:50 PM PDT 24 Jul 30 06:31:51 PM PDT 24 243902884 ps
T2847 /workspace/coverage/default/13.usbdev_alert_test.3659617810 Jul 30 06:29:56 PM PDT 24 Jul 30 06:29:56 PM PDT 24 42140949 ps
T2848 /workspace/coverage/default/37.usbdev_stall_priority_over_nak.135949113 Jul 30 06:33:35 PM PDT 24 Jul 30 06:33:37 PM PDT 24 181765575 ps
T2849 /workspace/coverage/default/43.usbdev_phy_pins_sense.328145884 Jul 30 06:34:27 PM PDT 24 Jul 30 06:34:28 PM PDT 24 71080224 ps
T2850 /workspace/coverage/default/43.usbdev_random_length_out_transaction.2129353957 Jul 30 06:34:22 PM PDT 24 Jul 30 06:34:23 PM PDT 24 166384022 ps
T2851 /workspace/coverage/default/24.usbdev_setup_trans_ignored.2862954280 Jul 30 06:31:43 PM PDT 24 Jul 30 06:31:44 PM PDT 24 150739959 ps
T2852 /workspace/coverage/default/8.usbdev_in_stall.2522023075 Jul 30 06:29:09 PM PDT 24 Jul 30 06:29:10 PM PDT 24 133930177 ps
T2853 /workspace/coverage/default/25.usbdev_min_length_in_transaction.4101987727 Jul 30 06:31:47 PM PDT 24 Jul 30 06:31:48 PM PDT 24 152874675 ps
T2854 /workspace/coverage/default/4.usbdev_disable_endpoint.3028818360 Jul 30 06:28:17 PM PDT 24 Jul 30 06:28:19 PM PDT 24 435156242 ps
T2855 /workspace/coverage/default/11.usbdev_device_address.2122261792 Jul 30 06:29:29 PM PDT 24 Jul 30 06:30:03 PM PDT 24 14178074899 ps
T2856 /workspace/coverage/default/5.usbdev_rx_crc_err.632976920 Jul 30 06:28:51 PM PDT 24 Jul 30 06:28:52 PM PDT 24 154145125 ps
T2857 /workspace/coverage/default/19.usbdev_in_trans.355883158 Jul 30 06:30:47 PM PDT 24 Jul 30 06:30:49 PM PDT 24 232269909 ps
T2858 /workspace/coverage/default/9.usbdev_rand_bus_resets.3219538294 Jul 30 06:29:18 PM PDT 24 Jul 30 06:34:09 PM PDT 24 12928227860 ps
T2859 /workspace/coverage/default/9.usbdev_pending_in_trans.3586867799 Jul 30 06:29:17 PM PDT 24 Jul 30 06:29:19 PM PDT 24 143307817 ps
T2860 /workspace/coverage/default/5.usbdev_stall_trans.2843885240 Jul 30 06:28:47 PM PDT 24 Jul 30 06:28:48 PM PDT 24 175561977 ps
T2861 /workspace/coverage/default/29.usbdev_aon_wake_reset.2017713092 Jul 30 06:32:06 PM PDT 24 Jul 30 06:32:22 PM PDT 24 13307251852 ps
T2862 /workspace/coverage/default/11.usbdev_pending_in_trans.3756528714 Jul 30 06:29:40 PM PDT 24 Jul 30 06:29:41 PM PDT 24 154186562 ps
T2863 /workspace/coverage/default/14.usbdev_nak_trans.3026829232 Jul 30 06:30:14 PM PDT 24 Jul 30 06:30:15 PM PDT 24 178288913 ps
T2864 /workspace/coverage/default/1.usbdev_max_length_in_transaction.3100674271 Jul 30 06:27:52 PM PDT 24 Jul 30 06:27:53 PM PDT 24 237998116 ps
T190 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.997442758 Jul 30 05:10:23 PM PDT 24 Jul 30 05:10:24 PM PDT 24 92726260 ps
T216 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.167297607 Jul 30 05:09:57 PM PDT 24 Jul 30 05:09:58 PM PDT 24 41050296 ps
T197 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2062633179 Jul 30 05:10:49 PM PDT 24 Jul 30 05:10:50 PM PDT 24 36562746 ps
T198 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.130751626 Jul 30 05:10:53 PM PDT 24 Jul 30 05:10:54 PM PDT 24 57468608 ps
T200 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1990153089 Jul 30 05:10:51 PM PDT 24 Jul 30 05:10:52 PM PDT 24 39595934 ps
T201 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2998153137 Jul 30 05:10:56 PM PDT 24 Jul 30 05:10:57 PM PDT 24 40350770 ps
T233 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1824178402 Jul 30 05:10:26 PM PDT 24 Jul 30 05:10:27 PM PDT 24 56386467 ps
T199 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2030887486 Jul 30 05:10:53 PM PDT 24 Jul 30 05:10:54 PM PDT 24 40392223 ps
T191 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1018970029 Jul 30 05:10:26 PM PDT 24 Jul 30 05:10:28 PM PDT 24 164559660 ps
T202 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3776204979 Jul 30 05:10:32 PM PDT 24 Jul 30 05:10:33 PM PDT 24 46643892 ps
T258 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1598547676 Jul 30 05:10:21 PM PDT 24 Jul 30 05:10:21 PM PDT 24 54534688 ps
T192 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1918497261 Jul 30 05:10:24 PM PDT 24 Jul 30 05:10:26 PM PDT 24 79261153 ps
T2865 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3168324493 Jul 30 05:10:01 PM PDT 24 Jul 30 05:10:05 PM PDT 24 495673256 ps
T187 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2390077816 Jul 30 05:10:16 PM PDT 24 Jul 30 05:10:19 PM PDT 24 296834291 ps
T188 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.144823418 Jul 30 05:10:43 PM PDT 24 Jul 30 05:10:47 PM PDT 24 545742633 ps
T189 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2400062406 Jul 30 05:10:40 PM PDT 24 Jul 30 05:10:42 PM PDT 24 108428920 ps
T282 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2925307734 Jul 30 05:10:56 PM PDT 24 Jul 30 05:10:57 PM PDT 24 51193726 ps
T269 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3356951409 Jul 30 05:10:39 PM PDT 24 Jul 30 05:10:41 PM PDT 24 96058970 ps
T277 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3677510336 Jul 30 05:10:30 PM PDT 24 Jul 30 05:10:31 PM PDT 24 40137318 ps
T283 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.920422718 Jul 30 05:10:43 PM PDT 24 Jul 30 05:10:45 PM PDT 24 45357731 ps
T284 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3671483668 Jul 30 05:10:55 PM PDT 24 Jul 30 05:10:56 PM PDT 24 71319245 ps
T2866 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.953307627 Jul 30 05:10:25 PM PDT 24 Jul 30 05:10:26 PM PDT 24 49859514 ps
T214 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.936020454 Jul 30 05:10:24 PM PDT 24 Jul 30 05:10:26 PM PDT 24 185677218 ps
T270 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1176196239 Jul 30 05:10:28 PM PDT 24 Jul 30 05:10:30 PM PDT 24 227920340 ps
T2867 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3404160534 Jul 30 05:10:13 PM PDT 24 Jul 30 05:10:14 PM PDT 24 77736481 ps
T285 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2984948438 Jul 30 05:10:55 PM PDT 24 Jul 30 05:10:56 PM PDT 24 65953360 ps
T237 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1931905512 Jul 30 05:10:16 PM PDT 24 Jul 30 05:10:18 PM PDT 24 172096969 ps
T215 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2724456902 Jul 30 05:10:49 PM PDT 24 Jul 30 05:10:52 PM PDT 24 376466185 ps
T271 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1445954033 Jul 30 05:10:36 PM PDT 24 Jul 30 05:10:37 PM PDT 24 133718776 ps
T2868 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.380610953 Jul 30 05:11:01 PM PDT 24 Jul 30 05:11:02 PM PDT 24 55662846 ps
T2869 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.994505672 Jul 30 05:10:20 PM PDT 24 Jul 30 05:10:21 PM PDT 24 73674176 ps
T272 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3079804558 Jul 30 05:10:42 PM PDT 24 Jul 30 05:10:43 PM PDT 24 110044114 ps
T238 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.930101539 Jul 30 05:10:34 PM PDT 24 Jul 30 05:10:36 PM PDT 24 85662609 ps
T223 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2876738226 Jul 30 05:10:49 PM PDT 24 Jul 30 05:10:52 PM PDT 24 209275026 ps
T259 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3982031461 Jul 30 05:10:18 PM PDT 24 Jul 30 05:10:19 PM PDT 24 111932057 ps
T2870 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2937413048 Jul 30 05:10:31 PM PDT 24 Jul 30 05:10:32 PM PDT 24 62342042 ps
T2871 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3646478201 Jul 30 05:09:57 PM PDT 24 Jul 30 05:09:59 PM PDT 24 147293346 ps
T2872 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3505987743 Jul 30 05:10:53 PM PDT 24 Jul 30 05:10:54 PM PDT 24 56237366 ps
T2873 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1225764070 Jul 30 05:10:17 PM PDT 24 Jul 30 05:10:21 PM PDT 24 489985972 ps
T276 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2968956482 Jul 30 05:10:34 PM PDT 24 Jul 30 05:10:35 PM PDT 24 190845233 ps
T222 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1786351141 Jul 30 05:10:29 PM PDT 24 Jul 30 05:10:34 PM PDT 24 911415309 ps
T260 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3482684110 Jul 30 05:09:58 PM PDT 24 Jul 30 05:10:01 PM PDT 24 291358555 ps
T261 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3213949683 Jul 30 05:10:10 PM PDT 24 Jul 30 05:10:11 PM PDT 24 159570177 ps
T2874 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3908915423 Jul 30 05:10:53 PM PDT 24 Jul 30 05:10:54 PM PDT 24 32515326 ps
T2875 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.164409541 Jul 30 05:10:35 PM PDT 24 Jul 30 05:10:36 PM PDT 24 36872937 ps
T2876 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3298295222 Jul 30 05:10:47 PM PDT 24 Jul 30 05:10:48 PM PDT 24 72962907 ps
T2877 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3599754933 Jul 30 05:10:55 PM PDT 24 Jul 30 05:10:55 PM PDT 24 40883831 ps
T239 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3184479192 Jul 30 05:10:26 PM PDT 24 Jul 30 05:10:28 PM PDT 24 166275347 ps
T2878 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3902585951 Jul 30 05:10:38 PM PDT 24 Jul 30 05:10:39 PM PDT 24 62661630 ps
T262 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1088168381 Jul 30 05:10:44 PM PDT 24 Jul 30 05:10:45 PM PDT 24 78702149 ps
T240 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3103059207 Jul 30 05:10:28 PM PDT 24 Jul 30 05:10:35 PM PDT 24 2154062401 ps
T2879 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3909618060 Jul 30 05:10:35 PM PDT 24 Jul 30 05:10:35 PM PDT 24 38611069 ps
T263 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1538294451 Jul 30 05:10:28 PM PDT 24 Jul 30 05:10:29 PM PDT 24 46237203 ps
T2880 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2981200475 Jul 30 05:10:50 PM PDT 24 Jul 30 05:10:51 PM PDT 24 36109033 ps
T2881 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.887764520 Jul 30 05:10:11 PM PDT 24 Jul 30 05:10:15 PM PDT 24 479532395 ps
T2882 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2848823280 Jul 30 05:10:30 PM PDT 24 Jul 30 05:10:32 PM PDT 24 220495057 ps
T264 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2820074686 Jul 30 05:10:46 PM PDT 24 Jul 30 05:10:47 PM PDT 24 90621511 ps
T2883 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3111498261 Jul 30 05:10:24 PM PDT 24 Jul 30 05:10:25 PM PDT 24 241446685 ps
T268 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1156302415 Jul 30 05:10:19 PM PDT 24 Jul 30 05:10:20 PM PDT 24 60388350 ps
T265 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.475039039 Jul 30 05:10:06 PM PDT 24 Jul 30 05:10:14 PM PDT 24 538689032 ps
T291 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3593064113 Jul 30 05:10:20 PM PDT 24 Jul 30 05:10:22 PM PDT 24 400486827 ps
T2884 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3363412244 Jul 30 05:10:55 PM PDT 24 Jul 30 05:10:56 PM PDT 24 37520385 ps
T288 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.836370503 Jul 30 05:10:06 PM PDT 24 Jul 30 05:10:08 PM PDT 24 426414870 ps
T266 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.658422015 Jul 30 05:09:57 PM PDT 24 Jul 30 05:09:59 PM PDT 24 130382281 ps
T2885 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2177652985 Jul 30 05:10:50 PM PDT 24 Jul 30 05:10:51 PM PDT 24 41150765 ps
T2886 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2245992515 Jul 30 05:10:52 PM PDT 24 Jul 30 05:10:53 PM PDT 24 53055418 ps
T224 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1001437130 Jul 30 05:09:57 PM PDT 24 Jul 30 05:09:59 PM PDT 24 68360794 ps
T231 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1827261832 Jul 30 05:10:07 PM PDT 24 Jul 30 05:10:09 PM PDT 24 178959563 ps
T2887 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1653053221 Jul 30 05:10:15 PM PDT 24 Jul 30 05:10:17 PM PDT 24 92262155 ps
T227 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1002893976 Jul 30 05:10:43 PM PDT 24 Jul 30 05:10:47 PM PDT 24 256290319 ps
T267 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.326286046 Jul 30 05:10:37 PM PDT 24 Jul 30 05:10:38 PM PDT 24 97123944 ps
T2888 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2545071903 Jul 30 05:10:55 PM PDT 24 Jul 30 05:10:55 PM PDT 24 58429158 ps
T290 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2205192643 Jul 30 05:10:37 PM PDT 24 Jul 30 05:10:42 PM PDT 24 673504389 ps
T2889 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1111893750 Jul 30 05:10:33 PM PDT 24 Jul 30 05:10:34 PM PDT 24 82910940 ps
T2890 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2258206473 Jul 30 05:10:29 PM PDT 24 Jul 30 05:10:30 PM PDT 24 41330756 ps
T2891 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.93557544 Jul 30 05:10:43 PM PDT 24 Jul 30 05:10:46 PM PDT 24 278759062 ps
T2892 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2103572784 Jul 30 05:10:13 PM PDT 24 Jul 30 05:10:13 PM PDT 24 50419632 ps
T2893 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.580832020 Jul 30 05:10:47 PM PDT 24 Jul 30 05:10:49 PM PDT 24 94157828 ps
T2894 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3500740835 Jul 30 05:10:53 PM PDT 24 Jul 30 05:10:54 PM PDT 24 31850264 ps
T226 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2712063993 Jul 30 05:10:01 PM PDT 24 Jul 30 05:10:05 PM PDT 24 308467745 ps
T2895 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.950231944 Jul 30 05:10:55 PM PDT 24 Jul 30 05:10:56 PM PDT 24 70792326 ps
T229 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.996615502 Jul 30 05:10:42 PM PDT 24 Jul 30 05:10:45 PM PDT 24 245069744 ps
T2896 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1769623761 Jul 30 05:10:39 PM PDT 24 Jul 30 05:10:40 PM PDT 24 49995748 ps
T2897 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1334265221 Jul 30 05:10:47 PM PDT 24 Jul 30 05:10:47 PM PDT 24 48747524 ps
T2898 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2982555587 Jul 30 05:10:42 PM PDT 24 Jul 30 05:10:43 PM PDT 24 78088471 ps
T2899 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.938168471 Jul 30 05:10:45 PM PDT 24 Jul 30 05:10:47 PM PDT 24 226448012 ps
T2900 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2239372745 Jul 30 05:09:58 PM PDT 24 Jul 30 05:10:06 PM PDT 24 569347147 ps
T2901 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1034327129 Jul 30 05:10:16 PM PDT 24 Jul 30 05:10:17 PM PDT 24 90389157 ps
T230 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.649766950 Jul 30 05:10:34 PM PDT 24 Jul 30 05:10:36 PM PDT 24 75256284 ps
T297 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1078702916 Jul 30 05:10:01 PM PDT 24 Jul 30 05:10:03 PM PDT 24 307961885 ps
T2902 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3816808963 Jul 30 05:10:55 PM PDT 24 Jul 30 05:10:56 PM PDT 24 33595139 ps
T2903 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3177402824 Jul 30 05:10:20 PM PDT 24 Jul 30 05:10:21 PM PDT 24 103691631 ps
T2904 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.137100580 Jul 30 05:10:13 PM PDT 24 Jul 30 05:10:14 PM PDT 24 129445090 ps
T2905 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3057388742 Jul 30 05:10:19 PM PDT 24 Jul 30 05:10:20 PM PDT 24 137955603 ps
T228 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.880526299 Jul 30 05:10:17 PM PDT 24 Jul 30 05:10:20 PM PDT 24 104408387 ps
T2906 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2731908113 Jul 30 05:10:44 PM PDT 24 Jul 30 05:10:45 PM PDT 24 151455084 ps
T2907 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1096237684 Jul 30 05:10:54 PM PDT 24 Jul 30 05:10:55 PM PDT 24 40162966 ps
T2908 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3928890482 Jul 30 05:10:35 PM PDT 24 Jul 30 05:10:36 PM PDT 24 84295975 ps
T2909 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2271007766 Jul 30 05:10:13 PM PDT 24 Jul 30 05:10:14 PM PDT 24 121904332 ps
T2910 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3622649254 Jul 30 05:10:01 PM PDT 24 Jul 30 05:10:02 PM PDT 24 96015928 ps
T234 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2547182294 Jul 30 05:10:49 PM PDT 24 Jul 30 05:10:52 PM PDT 24 122642466 ps
T2911 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3524603665 Jul 30 05:10:09 PM PDT 24 Jul 30 05:10:11 PM PDT 24 238353067 ps
T2912 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.789698061 Jul 30 05:10:07 PM PDT 24 Jul 30 05:10:09 PM PDT 24 81352991 ps
T2913 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2764798216 Jul 30 05:10:42 PM PDT 24 Jul 30 05:10:44 PM PDT 24 70162962 ps
T2914 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1631226416 Jul 30 05:10:06 PM PDT 24 Jul 30 05:10:08 PM PDT 24 66839972 ps
T2915 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2210560661 Jul 30 05:10:18 PM PDT 24 Jul 30 05:10:19 PM PDT 24 44931807 ps
T293 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.142161207 Jul 30 05:10:45 PM PDT 24 Jul 30 05:10:48 PM PDT 24 446521215 ps
T2916 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3044615352 Jul 30 05:10:16 PM PDT 24 Jul 30 05:10:19 PM PDT 24 126277094 ps
T2917 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1326802370 Jul 30 05:10:16 PM PDT 24 Jul 30 05:10:20 PM PDT 24 300528096 ps
T2918 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.401352743 Jul 30 05:10:21 PM PDT 24 Jul 30 05:10:22 PM PDT 24 53918345 ps
T2919 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2664357109 Jul 30 05:10:56 PM PDT 24 Jul 30 05:10:57 PM PDT 24 44839825 ps
T2920 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2721106648 Jul 30 05:10:46 PM PDT 24 Jul 30 05:10:48 PM PDT 24 92942970 ps
T295 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1609939257 Jul 30 05:10:35 PM PDT 24 Jul 30 05:10:41 PM PDT 24 1300010649 ps
T2921 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.846043698 Jul 30 05:10:50 PM PDT 24 Jul 30 05:10:51 PM PDT 24 73745968 ps
T2922 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1044733013 Jul 30 05:10:47 PM PDT 24 Jul 30 05:10:50 PM PDT 24 290293480 ps
T2923 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.940792627 Jul 30 05:10:49 PM PDT 24 Jul 30 05:10:52 PM PDT 24 108058420 ps
T2924 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4164331045 Jul 30 05:10:35 PM PDT 24 Jul 30 05:10:39 PM PDT 24 327480862 ps
T2925 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1879892297 Jul 30 05:09:57 PM PDT 24 Jul 30 05:09:59 PM PDT 24 280458600 ps
T2926 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.25426773 Jul 30 05:09:56 PM PDT 24 Jul 30 05:09:58 PM PDT 24 257615197 ps
T2927 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2732898330 Jul 30 05:10:26 PM PDT 24 Jul 30 05:10:27 PM PDT 24 95920200 ps
T2928 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1539546086 Jul 30 05:10:39 PM PDT 24 Jul 30 05:10:41 PM PDT 24 137206217 ps
T2929 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.331071331 Jul 30 05:10:46 PM PDT 24 Jul 30 05:10:47 PM PDT 24 81134927 ps
T2930 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4231433644 Jul 30 05:10:05 PM PDT 24 Jul 30 05:10:08 PM PDT 24 214395542 ps
T2931 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2216404479 Jul 30 05:10:52 PM PDT 24 Jul 30 05:10:53 PM PDT 24 60955969 ps
T2932 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3683559640 Jul 30 05:10:55 PM PDT 24 Jul 30 05:10:56 PM PDT 24 48963289 ps
T2933 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4247308690 Jul 30 05:10:24 PM PDT 24 Jul 30 05:10:27 PM PDT 24 215143756 ps
T2934 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3701318642 Jul 30 05:10:10 PM PDT 24 Jul 30 05:10:18 PM PDT 24 1545006055 ps
T294 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2368978227 Jul 30 05:10:28 PM PDT 24 Jul 30 05:10:32 PM PDT 24 871285780 ps
T2935 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.516400241 Jul 30 05:10:37 PM PDT 24 Jul 30 05:10:41 PM PDT 24 308646178 ps
T2936 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1082573442 Jul 30 05:10:02 PM PDT 24 Jul 30 05:10:04 PM PDT 24 72353469 ps
T2937 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.481434551 Jul 30 05:10:53 PM PDT 24 Jul 30 05:10:54 PM PDT 24 60261100 ps
T2938 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4125711140 Jul 30 05:10:09 PM PDT 24 Jul 30 05:10:13 PM PDT 24 240596738 ps
T2939 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3116650688 Jul 30 05:09:56 PM PDT 24 Jul 30 05:09:57 PM PDT 24 84295392 ps
T2940 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1757168688 Jul 30 05:10:44 PM PDT 24 Jul 30 05:10:46 PM PDT 24 150450121 ps
T296 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3352376519 Jul 30 05:10:35 PM PDT 24 Jul 30 05:10:38 PM PDT 24 358966661 ps
T2941 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3033494664 Jul 30 05:09:54 PM PDT 24 Jul 30 05:09:55 PM PDT 24 75528005 ps
T289 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3766796963 Jul 30 05:10:13 PM PDT 24 Jul 30 05:10:17 PM PDT 24 472631951 ps
T2942 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1402747571 Jul 30 05:10:34 PM PDT 24 Jul 30 05:10:37 PM PDT 24 126355169 ps
T2943 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.326747100 Jul 30 05:10:35 PM PDT 24 Jul 30 05:10:37 PM PDT 24 107254283 ps
T2944 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3502228063 Jul 30 05:10:20 PM PDT 24 Jul 30 05:10:27 PM PDT 24 2378483592 ps
T292 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1423285971 Jul 30 05:10:47 PM PDT 24 Jul 30 05:10:50 PM PDT 24 427417034 ps
T2945 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3033754858 Jul 30 05:10:43 PM PDT 24 Jul 30 05:10:44 PM PDT 24 101717199 ps
T2946 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.494400833 Jul 30 05:10:48 PM PDT 24 Jul 30 05:10:49 PM PDT 24 59469034 ps
T2947 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4095840620 Jul 30 05:10:05 PM PDT 24 Jul 30 05:10:06 PM PDT 24 55430850 ps
T2948 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1174628137 Jul 30 05:10:54 PM PDT 24 Jul 30 05:10:55 PM PDT 24 59270967 ps
T2949 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3828693583 Jul 30 05:10:44 PM PDT 24 Jul 30 05:10:45 PM PDT 24 45235259 ps
T2950 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4262920764 Jul 30 05:10:27 PM PDT 24 Jul 30 05:10:30 PM PDT 24 244842079 ps
T2951 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2262629040 Jul 30 05:10:12 PM PDT 24 Jul 30 05:10:16 PM PDT 24 168291198 ps
T2952 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.33105904 Jul 30 05:10:35 PM PDT 24 Jul 30 05:10:36 PM PDT 24 97859773 ps
T2953 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3277496421 Jul 30 05:10:41 PM PDT 24 Jul 30 05:10:44 PM PDT 24 486697021 ps
T2954 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3223982141 Jul 30 05:10:58 PM PDT 24 Jul 30 05:10:59 PM PDT 24 48502449 ps
T2955 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2898139765 Jul 30 05:10:36 PM PDT 24 Jul 30 05:10:42 PM PDT 24 1392685565 ps
T2956 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3600970613 Jul 30 05:10:15 PM PDT 24 Jul 30 05:10:17 PM PDT 24 112211288 ps
T2957 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3077963697 Jul 30 05:10:06 PM PDT 24 Jul 30 05:10:07 PM PDT 24 87875558 ps
T2958 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3451803982 Jul 30 05:10:43 PM PDT 24 Jul 30 05:10:45 PM PDT 24 40032911 ps
T2959 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.358927572 Jul 30 05:10:47 PM PDT 24 Jul 30 05:10:49 PM PDT 24 101325491 ps
T2960 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4223932177 Jul 30 05:09:55 PM PDT 24 Jul 30 05:10:00 PM PDT 24 776675142 ps
T2961 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3484165084 Jul 30 05:10:46 PM PDT 24 Jul 30 05:10:47 PM PDT 24 60349824 ps
T2962 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.861865810 Jul 30 05:10:51 PM PDT 24 Jul 30 05:10:52 PM PDT 24 43997882 ps
T2963 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1183435119 Jul 30 05:10:13 PM PDT 24 Jul 30 05:10:21 PM PDT 24 541681937 ps
T2964 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3079804352 Jul 30 05:10:42 PM PDT 24 Jul 30 05:10:45 PM PDT 24 117157282 ps
T2965 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3687367994 Jul 30 05:10:43 PM PDT 24 Jul 30 05:10:46 PM PDT 24 388958217 ps
T2966 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.50280138 Jul 30 05:10:35 PM PDT 24 Jul 30 05:10:37 PM PDT 24 197995204 ps
T2967 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4010783512 Jul 30 05:10:17 PM PDT 24 Jul 30 05:10:22 PM PDT 24 341488590 ps
T2968 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3622336762 Jul 30 05:10:04 PM PDT 24 Jul 30 05:10:06 PM PDT 24 306470230 ps
T2969 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3711626925 Jul 30 05:10:28 PM PDT 24 Jul 30 05:10:29 PM PDT 24 78672495 ps
T2970 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4149317935 Jul 30 05:10:57 PM PDT 24 Jul 30 05:10:58 PM PDT 24 32821525 ps
T2971 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3052723013 Jul 30 05:10:04 PM PDT 24 Jul 30 05:10:06 PM PDT 24 104790133 ps
T2972 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1073897144 Jul 30 05:10:30 PM PDT 24 Jul 30 05:10:32 PM PDT 24 94626748 ps
T2973 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3723251451 Jul 30 05:10:14 PM PDT 24 Jul 30 05:10:18 PM PDT 24 506153217 ps
T2974 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1130436850 Jul 30 05:10:21 PM PDT 24 Jul 30 05:10:24 PM PDT 24 192376120 ps
T2975 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3644647176 Jul 30 05:10:11 PM PDT 24 Jul 30 05:10:13 PM PDT 24 154047969 ps
T2976 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.932356493 Jul 30 05:10:47 PM PDT 24 Jul 30 05:10:48 PM PDT 24 170393593 ps
T2977 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3466579954 Jul 30 05:10:51 PM PDT 24 Jul 30 05:10:52 PM PDT 24 63205932 ps
T2978 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1515103028 Jul 30 05:10:00 PM PDT 24 Jul 30 05:10:01 PM PDT 24 76995245 ps

Test location /workspace/coverage/default/30.usbdev_streaming_out.3209043731
Short name T4
Test name
Test status
Simulation time 3674047327 ps
CPU time 110.31 seconds
Started Jul 30 06:32:34 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 215336 kb
Host smart-25e70cac-9cc4-4526-9881-13cd0e0d1015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32090
43731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.3209043731
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2307659045
Short name T6
Test name
Test status
Simulation time 6647922276 ps
CPU time 188.99 seconds
Started Jul 30 06:30:32 PM PDT 24
Finished Jul 30 06:33:41 PM PDT 24
Peak memory 215324 kb
Host smart-3346e7fb-fa02-4891-9ae4-270cb6733ef0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2307659045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2307659045
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_device_address.1483052544
Short name T79
Test name
Test status
Simulation time 20825309083 ps
CPU time 44.52 seconds
Started Jul 30 06:31:59 PM PDT 24
Finished Jul 30 06:32:44 PM PDT 24
Peak memory 207092 kb
Host smart-d2f75596-4395-45bf-b09a-89eddbb174b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14830
52544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.1483052544
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.641657525
Short name T8
Test name
Test status
Simulation time 13378661867 ps
CPU time 16.44 seconds
Started Jul 30 06:31:41 PM PDT 24
Finished Jul 30 06:31:58 PM PDT 24
Peak memory 207140 kb
Host smart-055f713c-57e8-440a-9640-66df9eeafafc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=641657525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.641657525
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2062633179
Short name T197
Test name
Test status
Simulation time 36562746 ps
CPU time 0.74 seconds
Started Jul 30 05:10:49 PM PDT 24
Finished Jul 30 05:10:50 PM PDT 24
Peak memory 206388 kb
Host smart-dccd56c3-d7c3-4088-bebe-933d5d7b027b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2062633179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2062633179
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1786351141
Short name T222
Test name
Test status
Simulation time 911415309 ps
CPU time 4.52 seconds
Started Jul 30 05:10:29 PM PDT 24
Finished Jul 30 05:10:34 PM PDT 24
Peak memory 206732 kb
Host smart-6b287503-8151-425c-937e-331d015c0905
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1786351141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1786351141
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1404190280
Short name T92
Test name
Test status
Simulation time 214200890 ps
CPU time 0.94 seconds
Started Jul 30 06:32:33 PM PDT 24
Finished Jul 30 06:32:34 PM PDT 24
Peak memory 207076 kb
Host smart-f025ed3f-66e6-440c-8fa6-dcf888950898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14041
90280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1404190280
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.572626068
Short name T65
Test name
Test status
Simulation time 19146983036 ps
CPU time 466.16 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:35:58 PM PDT 24
Peak memory 215292 kb
Host smart-281e91fe-e60f-4e79-bd20-f8538bab5d26
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572626068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.572626068
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.3286912774
Short name T102
Test name
Test status
Simulation time 13468543980 ps
CPU time 84.26 seconds
Started Jul 30 06:28:31 PM PDT 24
Finished Jul 30 06:29:56 PM PDT 24
Peak memory 207112 kb
Host smart-de044b25-653f-4be3-a896-308814255607
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3286912774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.3286912774
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3919529326
Short name T39
Test name
Test status
Simulation time 220137609 ps
CPU time 0.92 seconds
Started Jul 30 06:27:54 PM PDT 24
Finished Jul 30 06:27:55 PM PDT 24
Peak memory 206932 kb
Host smart-ce44fd69-4ef1-417c-96b1-c6f4a597f62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39195
29326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3919529326
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3777328513
Short name T24
Test name
Test status
Simulation time 220099436 ps
CPU time 0.92 seconds
Started Jul 30 06:33:19 PM PDT 24
Finished Jul 30 06:33:20 PM PDT 24
Peak memory 206928 kb
Host smart-90dac015-9ffb-4356-8285-5bb8f2eded77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37773
28513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3777328513
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.447995622
Short name T74
Test name
Test status
Simulation time 1042116487 ps
CPU time 2.76 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:33:48 PM PDT 24
Peak memory 207060 kb
Host smart-56cf2d9c-3915-4663-9a37-11e7277fedd8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=447995622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.447995622
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2925307734
Short name T282
Test name
Test status
Simulation time 51193726 ps
CPU time 0.75 seconds
Started Jul 30 05:10:56 PM PDT 24
Finished Jul 30 05:10:57 PM PDT 24
Peak memory 206440 kb
Host smart-16e10b60-271c-48d9-a8e3-d447a2d3ee1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2925307734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2925307734
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.272468431
Short name T25
Test name
Test status
Simulation time 37182302 ps
CPU time 0.69 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:28:14 PM PDT 24
Peak memory 206948 kb
Host smart-29b4af38-1ef5-43ea-9ce9-8e5389d653dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27246
8431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.272468431
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2400062406
Short name T189
Test name
Test status
Simulation time 108428920 ps
CPU time 2.73 seconds
Started Jul 30 05:10:40 PM PDT 24
Finished Jul 30 05:10:42 PM PDT 24
Peak memory 214924 kb
Host smart-ab18bcb0-7d91-4d38-a822-0d5eae49c611
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400062406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2400062406
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.720479163
Short name T71
Test name
Test status
Simulation time 301605451 ps
CPU time 1.04 seconds
Started Jul 30 06:27:45 PM PDT 24
Finished Jul 30 06:27:46 PM PDT 24
Peak memory 206936 kb
Host smart-b42ea6a2-8f3f-4ab1-a9d7-153053879057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72047
9163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.720479163
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1868479581
Short name T9
Test name
Test status
Simulation time 3454214616 ps
CPU time 5.31 seconds
Started Jul 30 06:31:41 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 207080 kb
Host smart-0409600d-694b-4ca1-9810-c8c198f6f9a7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868479581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.1868479581
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2380186554
Short name T203
Test name
Test status
Simulation time 285584996 ps
CPU time 1.11 seconds
Started Jul 30 06:27:56 PM PDT 24
Finished Jul 30 06:27:57 PM PDT 24
Peak memory 222940 kb
Host smart-720f1ed6-00d6-433f-882a-c925c79c92af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2380186554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2380186554
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.3283539199
Short name T523
Test name
Test status
Simulation time 37549593 ps
CPU time 0.63 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:29:30 PM PDT 24
Peak memory 207028 kb
Host smart-56ff7999-46d9-49a7-b012-88949b438de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3283539199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.3283539199
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.2487983596
Short name T41
Test name
Test status
Simulation time 20172213849 ps
CPU time 26.04 seconds
Started Jul 30 06:27:42 PM PDT 24
Finished Jul 30 06:28:08 PM PDT 24
Peak memory 207016 kb
Host smart-0343a375-9c9a-49fa-8f91-4fd5053cf756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24879
83596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.2487983596
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1598547676
Short name T258
Test name
Test status
Simulation time 54534688 ps
CPU time 0.83 seconds
Started Jul 30 05:10:21 PM PDT 24
Finished Jul 30 05:10:21 PM PDT 24
Peak memory 206432 kb
Host smart-8be01ae4-6c7b-47c1-a621-3a0bc9461b73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1598547676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1598547676
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/default/36.usbdev_device_address.3516140623
Short name T80
Test name
Test status
Simulation time 8300314125 ps
CPU time 18.89 seconds
Started Jul 30 06:33:08 PM PDT 24
Finished Jul 30 06:33:27 PM PDT 24
Peak memory 207204 kb
Host smart-d3b9d1ca-6fd5-4443-a44c-5a47a54e4d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35161
40623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.3516140623
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.135084859
Short name T101
Test name
Test status
Simulation time 18558130213 ps
CPU time 48 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:33:25 PM PDT 24
Peak memory 215348 kb
Host smart-36d7ddcc-50f5-4e90-8ebe-e32b781b8232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13508
4859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.135084859
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2547182294
Short name T234
Test name
Test status
Simulation time 122642466 ps
CPU time 3.25 seconds
Started Jul 30 05:10:49 PM PDT 24
Finished Jul 30 05:10:52 PM PDT 24
Peak memory 219736 kb
Host smart-f04bac00-7803-4730-9fdc-7c94da24894b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2547182294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2547182294
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.137014341
Short name T307
Test name
Test status
Simulation time 133992541 ps
CPU time 0.81 seconds
Started Jul 30 06:34:13 PM PDT 24
Finished Jul 30 06:34:14 PM PDT 24
Peak memory 206912 kb
Host smart-8b3bc1a8-8071-4dd9-aa56-d6d8ba97a54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13701
4341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.137014341
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.3874525282
Short name T347
Test name
Test status
Simulation time 202383443 ps
CPU time 0.89 seconds
Started Jul 30 06:29:30 PM PDT 24
Finished Jul 30 06:29:31 PM PDT 24
Peak memory 206876 kb
Host smart-01158654-7258-40a8-885e-a27096bd31e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38745
25282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.3874525282
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.3037364804
Short name T42
Test name
Test status
Simulation time 345532948 ps
CPU time 1.43 seconds
Started Jul 30 06:27:45 PM PDT 24
Finished Jul 30 06:27:46 PM PDT 24
Peak memory 206956 kb
Host smart-b776bb0f-c92a-444f-a3d5-92e8ff9d6504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30373
64804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.3037364804
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3193418027
Short name T23
Test name
Test status
Simulation time 265154064 ps
CPU time 0.98 seconds
Started Jul 30 06:28:15 PM PDT 24
Finished Jul 30 06:28:16 PM PDT 24
Peak memory 206912 kb
Host smart-7accf72c-db6c-4ada-868d-c4c2fe29c33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31934
18027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3193418027
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_device_address.2341645460
Short name T81
Test name
Test status
Simulation time 23168172557 ps
CPU time 50.55 seconds
Started Jul 30 06:32:53 PM PDT 24
Finished Jul 30 06:33:44 PM PDT 24
Peak memory 207140 kb
Host smart-71f5e763-5bb2-4a57-8f23-516c2f6419b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23416
45460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2341645460
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3766796963
Short name T289
Test name
Test status
Simulation time 472631951 ps
CPU time 4.27 seconds
Started Jul 30 05:10:13 PM PDT 24
Finished Jul 30 05:10:17 PM PDT 24
Peak memory 206764 kb
Host smart-5ba94e25-7387-4937-be62-6f801c3655f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3766796963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3766796963
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3909618060
Short name T2879
Test name
Test status
Simulation time 38611069 ps
CPU time 0.69 seconds
Started Jul 30 05:10:35 PM PDT 24
Finished Jul 30 05:10:35 PM PDT 24
Peak memory 206344 kb
Host smart-f6404af9-c9c0-491f-b472-694b50cc8c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3909618060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3909618060
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.625878913
Short name T66
Test name
Test status
Simulation time 22471305866 ps
CPU time 570.13 seconds
Started Jul 30 06:28:03 PM PDT 24
Finished Jul 30 06:37:34 PM PDT 24
Peak memory 215420 kb
Host smart-7dd6bf19-60e1-4cbc-81b6-62ded7a6b351
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625878913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.625878913
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.2109300004
Short name T322
Test name
Test status
Simulation time 113945005529 ps
CPU time 180.51 seconds
Started Jul 30 06:28:01 PM PDT 24
Finished Jul 30 06:31:02 PM PDT 24
Peak memory 207060 kb
Host smart-d6ad0dab-e396-4f66-8c43-158964dd8986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109300004 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.2109300004
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2715046479
Short name T113
Test name
Test status
Simulation time 202965083 ps
CPU time 0.93 seconds
Started Jul 30 06:30:19 PM PDT 24
Finished Jul 30 06:30:20 PM PDT 24
Peak memory 206928 kb
Host smart-075b1167-6cab-4d21-9d2f-d7927c912e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27150
46479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2715046479
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.3364793324
Short name T58
Test name
Test status
Simulation time 490716683 ps
CPU time 1.55 seconds
Started Jul 30 06:27:37 PM PDT 24
Finished Jul 30 06:27:38 PM PDT 24
Peak memory 206924 kb
Host smart-a56a5b76-5374-4b4a-ad84-4a99a1c67a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33647
93324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.3364793324
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/39.usbdev_device_address.1513941869
Short name T724
Test name
Test status
Simulation time 14188391573 ps
CPU time 30.31 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:34:06 PM PDT 24
Peak memory 207144 kb
Host smart-d4e7b85d-c6c5-4367-8779-aae41ca65e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15139
41869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.1513941869
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.20965640
Short name T241
Test name
Test status
Simulation time 12874533885 ps
CPU time 32.26 seconds
Started Jul 30 06:27:50 PM PDT 24
Finished Jul 30 06:28:22 PM PDT 24
Peak memory 223492 kb
Host smart-75fd394e-210e-4d8c-a91b-d0169813bb9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20965
640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.20965640
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.3660823335
Short name T51
Test name
Test status
Simulation time 163195631 ps
CPU time 0.87 seconds
Started Jul 30 06:27:32 PM PDT 24
Finished Jul 30 06:27:33 PM PDT 24
Peak memory 206884 kb
Host smart-0467b481-4715-4519-a2d3-b4a09a69c2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36608
23335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3660823335
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2826071962
Short name T312
Test name
Test status
Simulation time 7238331705 ps
CPU time 17.7 seconds
Started Jul 30 06:30:23 PM PDT 24
Finished Jul 30 06:30:41 PM PDT 24
Peak memory 207120 kb
Host smart-e138cd8b-4873-4d9a-b8f8-d072889b77cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28260
71962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2826071962
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3460772089
Short name T100
Test name
Test status
Simulation time 159784508 ps
CPU time 0.85 seconds
Started Jul 30 06:30:32 PM PDT 24
Finished Jul 30 06:30:33 PM PDT 24
Peak memory 206912 kb
Host smart-239b7470-2719-4142-a84e-d07d74b39560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34607
72089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3460772089
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.3307162021
Short name T154
Test name
Test status
Simulation time 8707747448 ps
CPU time 84.47 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:34:01 PM PDT 24
Peak memory 215424 kb
Host smart-d5236ab6-f941-4322-9406-bf28e7dfe8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33071
62021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.3307162021
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2390077816
Short name T187
Test name
Test status
Simulation time 296834291 ps
CPU time 3.2 seconds
Started Jul 30 05:10:16 PM PDT 24
Finished Jul 30 05:10:19 PM PDT 24
Peak memory 214760 kb
Host smart-16f97c34-fc4e-495e-b49e-ad365c7c659b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2390077816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2390077816
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.735759763
Short name T97
Test name
Test status
Simulation time 4008764675 ps
CPU time 112.73 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:34:38 PM PDT 24
Peak memory 215340 kb
Host smart-a2d32211-c3c4-4c3a-a25b-03b3fc4f607b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=735759763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.735759763
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.725221309
Short name T45
Test name
Test status
Simulation time 414528501 ps
CPU time 1.47 seconds
Started Jul 30 06:27:48 PM PDT 24
Finished Jul 30 06:27:50 PM PDT 24
Peak memory 206944 kb
Host smart-70bd4d15-8595-4f1c-b54f-b1bbe14b1400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72522
1309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.725221309
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.316722385
Short name T166
Test name
Test status
Simulation time 18038610177 ps
CPU time 106.58 seconds
Started Jul 30 06:27:44 PM PDT 24
Finished Jul 30 06:29:30 PM PDT 24
Peak memory 223544 kb
Host smart-9f698552-1d3c-453f-83e4-7788c91f457e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316722385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.316722385
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1609939257
Short name T295
Test name
Test status
Simulation time 1300010649 ps
CPU time 5.93 seconds
Started Jul 30 05:10:35 PM PDT 24
Finished Jul 30 05:10:41 PM PDT 24
Peak memory 206636 kb
Host smart-4d480daf-3258-4eba-9ac8-84242bf69a16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1609939257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1609939257
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2915181351
Short name T321
Test name
Test status
Simulation time 5107076482 ps
CPU time 141.84 seconds
Started Jul 30 06:27:32 PM PDT 24
Finished Jul 30 06:29:54 PM PDT 24
Peak memory 215380 kb
Host smart-2df00b03-c788-422c-b660-b29bd4311597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29151
81351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2915181351
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.485175710
Short name T590
Test name
Test status
Simulation time 241740803 ps
CPU time 0.94 seconds
Started Jul 30 06:29:44 PM PDT 24
Finished Jul 30 06:29:45 PM PDT 24
Peak memory 206916 kb
Host smart-1e9bb540-0154-4332-82f6-424d0a42629a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48517
5710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.485175710
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3175583603
Short name T315
Test name
Test status
Simulation time 10299854364 ps
CPU time 29.07 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:28:41 PM PDT 24
Peak memory 215432 kb
Host smart-0b7b64da-c113-4b58-9b58-b7a27b1d8120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31755
83603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3175583603
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.1842924564
Short name T318
Test name
Test status
Simulation time 112127517978 ps
CPU time 187.06 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:31:18 PM PDT 24
Peak memory 207124 kb
Host smart-f481d989-420d-4b90-ab27-ccc30c6c165e
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1842924564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.1842924564
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3077303308
Short name T313
Test name
Test status
Simulation time 16471119260 ps
CPU time 41.49 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:28:55 PM PDT 24
Peak memory 215332 kb
Host smart-14cf1331-af4a-48e4-b673-eaa0fbe9816e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30773
03308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3077303308
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.189196007
Short name T1083
Test name
Test status
Simulation time 4248580452 ps
CPU time 6.38 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 207056 kb
Host smart-24ab3f2a-212f-457e-a5f3-845d28d791a6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189196007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon
_wake_disconnect.189196007
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.2323278843
Short name T53
Test name
Test status
Simulation time 129644734 ps
CPU time 0.83 seconds
Started Jul 30 06:27:59 PM PDT 24
Finished Jul 30 06:28:00 PM PDT 24
Peak memory 206924 kb
Host smart-b0933567-b2c7-4b87-bbdf-a52b1cda71a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23232
78843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.2323278843
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.276243249
Short name T28
Test name
Test status
Simulation time 56811895 ps
CPU time 0.74 seconds
Started Jul 30 06:30:47 PM PDT 24
Finished Jul 30 06:30:48 PM PDT 24
Peak memory 206912 kb
Host smart-4507839d-fd77-49a1-a147-86a54d6ae81e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27624
3249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.276243249
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3646478201
Short name T2871
Test name
Test status
Simulation time 147293346 ps
CPU time 1.74 seconds
Started Jul 30 05:09:57 PM PDT 24
Finished Jul 30 05:09:59 PM PDT 24
Peak memory 206624 kb
Host smart-ea90cc84-c60b-4305-b3e6-6c15be5bc159
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3646478201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3646478201
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.2070102276
Short name T1579
Test name
Test status
Simulation time 157420017 ps
CPU time 0.89 seconds
Started Jul 30 06:27:27 PM PDT 24
Finished Jul 30 06:27:28 PM PDT 24
Peak memory 206920 kb
Host smart-c8fb5017-d8de-4495-82c1-820568d668be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20701
02276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.2070102276
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1304889121
Short name T54
Test name
Test status
Simulation time 4224511346 ps
CPU time 11.55 seconds
Started Jul 30 06:27:43 PM PDT 24
Finished Jul 30 06:27:55 PM PDT 24
Peak memory 207232 kb
Host smart-0cc75de3-e668-47c5-b8f5-8668ef2b8613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13048
89121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1304889121
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1684784841
Short name T55
Test name
Test status
Simulation time 175631202 ps
CPU time 0.87 seconds
Started Jul 30 06:27:35 PM PDT 24
Finished Jul 30 06:27:36 PM PDT 24
Peak memory 206872 kb
Host smart-50a471b0-0f08-4e82-8da3-13eb468f9a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16847
84841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1684784841
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.3283211130
Short name T2076
Test name
Test status
Simulation time 8644024757 ps
CPU time 154.51 seconds
Started Jul 30 06:27:54 PM PDT 24
Finished Jul 30 06:30:29 PM PDT 24
Peak memory 214864 kb
Host smart-5369cf0f-2810-4a53-bfee-66dd93c169e5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283211130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.3283211130
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.1246301458
Short name T2122
Test name
Test status
Simulation time 160049004 ps
CPU time 0.87 seconds
Started Jul 30 06:27:53 PM PDT 24
Finished Jul 30 06:27:54 PM PDT 24
Peak memory 206912 kb
Host smart-eaf59145-e76c-4a23-88c8-5a286bad1705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12463
01458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.1246301458
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.523498183
Short name T176
Test name
Test status
Simulation time 424263749 ps
CPU time 3 seconds
Started Jul 30 06:27:31 PM PDT 24
Finished Jul 30 06:27:34 PM PDT 24
Peak memory 207036 kb
Host smart-65f94cc7-13e1-4d05-9e2d-a4c6348460dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52349
8183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.523498183
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2345933058
Short name T129
Test name
Test status
Simulation time 190010898 ps
CPU time 0.93 seconds
Started Jul 30 06:27:39 PM PDT 24
Finished Jul 30 06:27:40 PM PDT 24
Peak memory 206944 kb
Host smart-8d8a05d0-2977-468d-87b8-a5bcb4ef91ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23459
33058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2345933058
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2935236288
Short name T2187
Test name
Test status
Simulation time 181719024 ps
CPU time 0.9 seconds
Started Jul 30 06:28:05 PM PDT 24
Finished Jul 30 06:28:06 PM PDT 24
Peak memory 206928 kb
Host smart-fc1ba614-6f2d-495f-955f-a7b64c8fbdae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29352
36288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2935236288
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.771175092
Short name T120
Test name
Test status
Simulation time 220734624 ps
CPU time 0.98 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:29:30 PM PDT 24
Peak memory 206952 kb
Host smart-75085825-605d-481d-a582-e7d8c460448e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77117
5092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.771175092
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.537009928
Short name T118
Test name
Test status
Simulation time 264185647 ps
CPU time 0.99 seconds
Started Jul 30 06:29:39 PM PDT 24
Finished Jul 30 06:29:40 PM PDT 24
Peak memory 206908 kb
Host smart-cc652083-5c93-4511-a478-4f50960096a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53700
9928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.537009928
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3995530632
Short name T116
Test name
Test status
Simulation time 224733429 ps
CPU time 1.06 seconds
Started Jul 30 06:30:09 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 206976 kb
Host smart-3acf6889-d3d6-48ba-91be-99d87a8d74f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39955
30632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3995530632
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2354750022
Short name T137
Test name
Test status
Simulation time 320477136 ps
CPU time 1.06 seconds
Started Jul 30 06:30:48 PM PDT 24
Finished Jul 30 06:30:50 PM PDT 24
Peak memory 206900 kb
Host smart-8be622c7-4b94-4cfa-8e13-85c7b0188da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23547
50022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2354750022
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1002686597
Short name T2777
Test name
Test status
Simulation time 224322851 ps
CPU time 0.99 seconds
Started Jul 30 06:30:56 PM PDT 24
Finished Jul 30 06:30:58 PM PDT 24
Peak memory 206928 kb
Host smart-3f545da7-1c28-4c2c-b684-251749b7773d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10026
86597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1002686597
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2813003908
Short name T127
Test name
Test status
Simulation time 187162710 ps
CPU time 0.94 seconds
Started Jul 30 06:31:58 PM PDT 24
Finished Jul 30 06:31:59 PM PDT 24
Peak memory 206980 kb
Host smart-1cace366-6df0-4009-9aa2-15e62135388a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28130
03908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2813003908
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1782777323
Short name T124
Test name
Test status
Simulation time 228430507 ps
CPU time 1.03 seconds
Started Jul 30 06:31:57 PM PDT 24
Finished Jul 30 06:31:59 PM PDT 24
Peak memory 206932 kb
Host smart-4563c53c-e220-433c-8a93-aca851ef0f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17827
77323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1782777323
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1046182984
Short name T140
Test name
Test status
Simulation time 173882779 ps
CPU time 0.9 seconds
Started Jul 30 06:32:13 PM PDT 24
Finished Jul 30 06:32:14 PM PDT 24
Peak memory 206948 kb
Host smart-dd21ac35-f05b-4a34-9745-2edde16175e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10461
82984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1046182984
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.2387380488
Short name T144
Test name
Test status
Simulation time 205403844 ps
CPU time 0.97 seconds
Started Jul 30 06:29:13 PM PDT 24
Finished Jul 30 06:29:14 PM PDT 24
Peak memory 206944 kb
Host smart-2a858156-0b21-4527-8ecd-a3cd98aebbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23873
80488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2387380488
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3482684110
Short name T260
Test name
Test status
Simulation time 291358555 ps
CPU time 3.42 seconds
Started Jul 30 05:09:58 PM PDT 24
Finished Jul 30 05:10:01 PM PDT 24
Peak memory 206596 kb
Host smart-c1d03808-3904-4f47-ad0e-abd9e2cc8f6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3482684110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3482684110
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2239372745
Short name T2900
Test name
Test status
Simulation time 569347147 ps
CPU time 7.99 seconds
Started Jul 30 05:09:58 PM PDT 24
Finished Jul 30 05:10:06 PM PDT 24
Peak memory 206560 kb
Host smart-218b11e0-4201-477e-9e9b-d0c6dfe7b8b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2239372745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2239372745
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1879892297
Short name T2925
Test name
Test status
Simulation time 280458600 ps
CPU time 1.11 seconds
Started Jul 30 05:09:57 PM PDT 24
Finished Jul 30 05:09:59 PM PDT 24
Peak memory 206576 kb
Host smart-a250b5ee-acaa-45f2-9946-b7aca9f66e9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1879892297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1879892297
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1001437130
Short name T224
Test name
Test status
Simulation time 68360794 ps
CPU time 1.73 seconds
Started Jul 30 05:09:57 PM PDT 24
Finished Jul 30 05:09:59 PM PDT 24
Peak memory 214884 kb
Host smart-ceb58750-c3ac-458b-a4b7-060fd76ba3e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001437130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1001437130
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.167297607
Short name T216
Test name
Test status
Simulation time 41050296 ps
CPU time 0.84 seconds
Started Jul 30 05:09:57 PM PDT 24
Finished Jul 30 05:09:58 PM PDT 24
Peak memory 206456 kb
Host smart-da318ad0-74f6-486a-8cbc-1dad0107974f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=167297607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.167297607
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3116650688
Short name T2939
Test name
Test status
Simulation time 84295392 ps
CPU time 0.79 seconds
Started Jul 30 05:09:56 PM PDT 24
Finished Jul 30 05:09:57 PM PDT 24
Peak memory 206424 kb
Host smart-a82ddca0-e03d-4b2b-bc44-24c2794f8792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3116650688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3116650688
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.658422015
Short name T266
Test name
Test status
Simulation time 130382281 ps
CPU time 1.5 seconds
Started Jul 30 05:09:57 PM PDT 24
Finished Jul 30 05:09:59 PM PDT 24
Peak memory 214808 kb
Host smart-d7d906ad-f452-4bf7-ae24-8128a8ad6121
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=658422015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.658422015
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4223932177
Short name T2960
Test name
Test status
Simulation time 776675142 ps
CPU time 4.89 seconds
Started Jul 30 05:09:55 PM PDT 24
Finished Jul 30 05:10:00 PM PDT 24
Peak memory 206512 kb
Host smart-bdd65051-57e7-43a2-a2fd-40bad2d664fc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4223932177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.4223932177
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3033494664
Short name T2941
Test name
Test status
Simulation time 75528005 ps
CPU time 1.55 seconds
Started Jul 30 05:09:54 PM PDT 24
Finished Jul 30 05:09:55 PM PDT 24
Peak memory 206644 kb
Host smart-aceb96e8-5686-4e7f-821f-864f4dad2e34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3033494664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3033494664
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.25426773
Short name T2926
Test name
Test status
Simulation time 257615197 ps
CPU time 2.34 seconds
Started Jul 30 05:09:56 PM PDT 24
Finished Jul 30 05:09:58 PM PDT 24
Peak memory 206580 kb
Host smart-d5e036bd-7116-4794-9df8-89c09065abc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=25426773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.25426773
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4231433644
Short name T2930
Test name
Test status
Simulation time 214395542 ps
CPU time 2.19 seconds
Started Jul 30 05:10:05 PM PDT 24
Finished Jul 30 05:10:08 PM PDT 24
Peak memory 206556 kb
Host smart-cd0ea967-d6b5-48b2-837b-6a6a1c02d562
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4231433644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.4231433644
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.475039039
Short name T265
Test name
Test status
Simulation time 538689032 ps
CPU time 7.71 seconds
Started Jul 30 05:10:06 PM PDT 24
Finished Jul 30 05:10:14 PM PDT 24
Peak memory 206512 kb
Host smart-a4e28bc9-06c5-49f4-a332-04ef818e650c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=475039039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.475039039
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1515103028
Short name T2978
Test name
Test status
Simulation time 76995245 ps
CPU time 0.84 seconds
Started Jul 30 05:10:00 PM PDT 24
Finished Jul 30 05:10:01 PM PDT 24
Peak memory 206560 kb
Host smart-19def9b8-6a7d-4012-bde6-702815e1c782
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1515103028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1515103028
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.789698061
Short name T2912
Test name
Test status
Simulation time 81352991 ps
CPU time 1.55 seconds
Started Jul 30 05:10:07 PM PDT 24
Finished Jul 30 05:10:09 PM PDT 24
Peak memory 214884 kb
Host smart-19925c6d-5db1-457f-973b-b75051002811
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789698061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.789698061
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4095840620
Short name T2947
Test name
Test status
Simulation time 55430850 ps
CPU time 0.8 seconds
Started Jul 30 05:10:05 PM PDT 24
Finished Jul 30 05:10:06 PM PDT 24
Peak memory 206512 kb
Host smart-5af9890f-afd3-41a6-885f-a00777b5a2f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4095840620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.4095840620
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3622649254
Short name T2910
Test name
Test status
Simulation time 96015928 ps
CPU time 0.83 seconds
Started Jul 30 05:10:01 PM PDT 24
Finished Jul 30 05:10:02 PM PDT 24
Peak memory 206348 kb
Host smart-d7408019-e1c7-4d17-90af-c6250ef08980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3622649254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3622649254
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1082573442
Short name T2936
Test name
Test status
Simulation time 72353469 ps
CPU time 2.27 seconds
Started Jul 30 05:10:02 PM PDT 24
Finished Jul 30 05:10:04 PM PDT 24
Peak memory 214828 kb
Host smart-cd2ba4dd-f297-4a13-af1c-5d14b5d249a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1082573442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1082573442
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3168324493
Short name T2865
Test name
Test status
Simulation time 495673256 ps
CPU time 4.7 seconds
Started Jul 30 05:10:01 PM PDT 24
Finished Jul 30 05:10:05 PM PDT 24
Peak memory 206532 kb
Host smart-c2537cbb-0ba6-4634-a80c-20a416955409
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3168324493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3168324493
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3622336762
Short name T2968
Test name
Test status
Simulation time 306470230 ps
CPU time 1.83 seconds
Started Jul 30 05:10:04 PM PDT 24
Finished Jul 30 05:10:06 PM PDT 24
Peak memory 206684 kb
Host smart-5c78f2a8-c0f9-47b8-8454-3a32ef6c23ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3622336762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3622336762
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2712063993
Short name T226
Test name
Test status
Simulation time 308467745 ps
CPU time 3.5 seconds
Started Jul 30 05:10:01 PM PDT 24
Finished Jul 30 05:10:05 PM PDT 24
Peak memory 220280 kb
Host smart-73f7245e-4c53-401c-9d27-54b00d062c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2712063993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2712063993
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1078702916
Short name T297
Test name
Test status
Simulation time 307961885 ps
CPU time 2.55 seconds
Started Jul 30 05:10:01 PM PDT 24
Finished Jul 30 05:10:03 PM PDT 24
Peak memory 206688 kb
Host smart-0b703780-5123-4f57-892a-f0ceeb263824
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1078702916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1078702916
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.930101539
Short name T238
Test name
Test status
Simulation time 85662609 ps
CPU time 2.33 seconds
Started Jul 30 05:10:34 PM PDT 24
Finished Jul 30 05:10:36 PM PDT 24
Peak memory 214876 kb
Host smart-5f86d845-df51-4278-a543-6ca991b38df2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930101539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.930101539
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1111893750
Short name T2889
Test name
Test status
Simulation time 82910940 ps
CPU time 1.04 seconds
Started Jul 30 05:10:33 PM PDT 24
Finished Jul 30 05:10:34 PM PDT 24
Peak memory 206496 kb
Host smart-2e01e9cf-834b-4706-bd14-42b3a88d9e03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1111893750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1111893750
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.164409541
Short name T2875
Test name
Test status
Simulation time 36872937 ps
CPU time 0.75 seconds
Started Jul 30 05:10:35 PM PDT 24
Finished Jul 30 05:10:36 PM PDT 24
Peak memory 206360 kb
Host smart-d96953ff-453d-468e-86f3-2c715e40da61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=164409541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.164409541
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2968956482
Short name T276
Test name
Test status
Simulation time 190845233 ps
CPU time 1.38 seconds
Started Jul 30 05:10:34 PM PDT 24
Finished Jul 30 05:10:35 PM PDT 24
Peak memory 206708 kb
Host smart-8aa40852-b986-45ed-a346-d6dcac91bc23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2968956482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2968956482
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4164331045
Short name T2924
Test name
Test status
Simulation time 327480862 ps
CPU time 3.55 seconds
Started Jul 30 05:10:35 PM PDT 24
Finished Jul 30 05:10:39 PM PDT 24
Peak memory 222416 kb
Host smart-d6300489-bed1-4d60-9940-0f8bdd126019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4164331045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.4164331045
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.33105904
Short name T2952
Test name
Test status
Simulation time 97859773 ps
CPU time 1.14 seconds
Started Jul 30 05:10:35 PM PDT 24
Finished Jul 30 05:10:36 PM PDT 24
Peak memory 214684 kb
Host smart-75c92392-7bb9-46af-826e-3d174eb6e10e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33105904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev
_csr_mem_rw_with_rand_reset.33105904
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3928890482
Short name T2908
Test name
Test status
Simulation time 84295975 ps
CPU time 0.94 seconds
Started Jul 30 05:10:35 PM PDT 24
Finished Jul 30 05:10:36 PM PDT 24
Peak memory 206448 kb
Host smart-ad862453-7d85-4009-aed8-ae5ff180f247
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3928890482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3928890482
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3776204979
Short name T202
Test name
Test status
Simulation time 46643892 ps
CPU time 0.75 seconds
Started Jul 30 05:10:32 PM PDT 24
Finished Jul 30 05:10:33 PM PDT 24
Peak memory 206392 kb
Host smart-8aa1a71d-6da6-4002-84ac-e28ef38ff91d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3776204979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3776204979
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.50280138
Short name T2966
Test name
Test status
Simulation time 197995204 ps
CPU time 1.31 seconds
Started Jul 30 05:10:35 PM PDT 24
Finished Jul 30 05:10:37 PM PDT 24
Peak memory 206680 kb
Host smart-29810f3a-5a83-4144-8cd1-1876710c71d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=50280138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.50280138
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1402747571
Short name T2942
Test name
Test status
Simulation time 126355169 ps
CPU time 2.93 seconds
Started Jul 30 05:10:34 PM PDT 24
Finished Jul 30 05:10:37 PM PDT 24
Peak memory 222932 kb
Host smart-2cd444f7-adf4-4185-91f8-153d7cc77f81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1402747571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1402747571
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2898139765
Short name T2955
Test name
Test status
Simulation time 1392685565 ps
CPU time 5.89 seconds
Started Jul 30 05:10:36 PM PDT 24
Finished Jul 30 05:10:42 PM PDT 24
Peak memory 206660 kb
Host smart-f1731ce3-3f1e-47bf-a024-a25be03cc663
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2898139765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2898139765
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1539546086
Short name T2928
Test name
Test status
Simulation time 137206217 ps
CPU time 1.83 seconds
Started Jul 30 05:10:39 PM PDT 24
Finished Jul 30 05:10:41 PM PDT 24
Peak memory 223084 kb
Host smart-a16fcadf-824e-43a7-beef-d889279fdb87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539546086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1539546086
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1769623761
Short name T2896
Test name
Test status
Simulation time 49995748 ps
CPU time 0.82 seconds
Started Jul 30 05:10:39 PM PDT 24
Finished Jul 30 05:10:40 PM PDT 24
Peak memory 206516 kb
Host smart-b6557df9-7365-4182-9585-34c2c4fc5a40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1769623761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1769623761
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3356951409
Short name T269
Test name
Test status
Simulation time 96058970 ps
CPU time 1.1 seconds
Started Jul 30 05:10:39 PM PDT 24
Finished Jul 30 05:10:41 PM PDT 24
Peak memory 206572 kb
Host smart-8f144ff1-497b-4f1f-8481-247ae605b629
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3356951409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3356951409
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.649766950
Short name T230
Test name
Test status
Simulation time 75256284 ps
CPU time 1.77 seconds
Started Jul 30 05:10:34 PM PDT 24
Finished Jul 30 05:10:36 PM PDT 24
Peak memory 222996 kb
Host smart-e4cedd57-62c3-4935-be26-8b7c9dcb015f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=649766950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.649766950
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3352376519
Short name T296
Test name
Test status
Simulation time 358966661 ps
CPU time 2.39 seconds
Started Jul 30 05:10:35 PM PDT 24
Finished Jul 30 05:10:38 PM PDT 24
Peak memory 206624 kb
Host smart-c65bc235-ecbb-4fcc-9128-cfbf6a0a44dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3352376519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3352376519
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.326286046
Short name T267
Test name
Test status
Simulation time 97123944 ps
CPU time 1 seconds
Started Jul 30 05:10:37 PM PDT 24
Finished Jul 30 05:10:38 PM PDT 24
Peak memory 206528 kb
Host smart-5c36daf5-1605-41d5-9b2d-9c96bdff5767
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=326286046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.326286046
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3902585951
Short name T2878
Test name
Test status
Simulation time 62661630 ps
CPU time 0.73 seconds
Started Jul 30 05:10:38 PM PDT 24
Finished Jul 30 05:10:39 PM PDT 24
Peak memory 206396 kb
Host smart-26ee91ca-d635-4b81-bf39-9b104dc89c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3902585951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3902585951
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1445954033
Short name T271
Test name
Test status
Simulation time 133718776 ps
CPU time 1.2 seconds
Started Jul 30 05:10:36 PM PDT 24
Finished Jul 30 05:10:37 PM PDT 24
Peak memory 206576 kb
Host smart-c1a4a678-6530-4a32-9b52-36c75e5f9417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1445954033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1445954033
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.516400241
Short name T2935
Test name
Test status
Simulation time 308646178 ps
CPU time 3.6 seconds
Started Jul 30 05:10:37 PM PDT 24
Finished Jul 30 05:10:41 PM PDT 24
Peak memory 214856 kb
Host smart-a090d32c-64c2-49f0-a751-bbed50e00645
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=516400241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.516400241
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2205192643
Short name T290
Test name
Test status
Simulation time 673504389 ps
CPU time 4.25 seconds
Started Jul 30 05:10:37 PM PDT 24
Finished Jul 30 05:10:42 PM PDT 24
Peak memory 206644 kb
Host smart-40f11598-accb-42b2-816f-33c3a32713d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2205192643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2205192643
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3079804352
Short name T2964
Test name
Test status
Simulation time 117157282 ps
CPU time 2.54 seconds
Started Jul 30 05:10:42 PM PDT 24
Finished Jul 30 05:10:45 PM PDT 24
Peak memory 214896 kb
Host smart-6de7fa48-8730-4de2-8543-39100bb5404a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079804352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3079804352
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2982555587
Short name T2898
Test name
Test status
Simulation time 78088471 ps
CPU time 0.91 seconds
Started Jul 30 05:10:42 PM PDT 24
Finished Jul 30 05:10:43 PM PDT 24
Peak memory 206460 kb
Host smart-ee6dabac-1201-4c43-aef3-9aad3ec9c00a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2982555587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2982555587
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3451803982
Short name T2958
Test name
Test status
Simulation time 40032911 ps
CPU time 0.69 seconds
Started Jul 30 05:10:43 PM PDT 24
Finished Jul 30 05:10:45 PM PDT 24
Peak memory 206012 kb
Host smart-318dd3b3-9565-47f9-a724-4078ebf98a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3451803982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3451803982
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2731908113
Short name T2906
Test name
Test status
Simulation time 151455084 ps
CPU time 1.19 seconds
Started Jul 30 05:10:44 PM PDT 24
Finished Jul 30 05:10:45 PM PDT 24
Peak memory 206636 kb
Host smart-5e0a637a-12e0-4129-b65f-6a333252aa57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2731908113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2731908113
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.996615502
Short name T229
Test name
Test status
Simulation time 245069744 ps
CPU time 2.73 seconds
Started Jul 30 05:10:42 PM PDT 24
Finished Jul 30 05:10:45 PM PDT 24
Peak memory 206580 kb
Host smart-ba15bdbb-5043-4fc3-9799-9a419c10270c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=996615502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.996615502
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.144823418
Short name T188
Test name
Test status
Simulation time 545742633 ps
CPU time 2.73 seconds
Started Jul 30 05:10:43 PM PDT 24
Finished Jul 30 05:10:47 PM PDT 24
Peak memory 206628 kb
Host smart-fb2e3df7-5a31-4fa7-ab9a-2fa5990b775a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=144823418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.144823418
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.580832020
Short name T2893
Test name
Test status
Simulation time 94157828 ps
CPU time 2.28 seconds
Started Jul 30 05:10:47 PM PDT 24
Finished Jul 30 05:10:49 PM PDT 24
Peak memory 214872 kb
Host smart-0ad5d875-0586-45b1-8c2a-eba7449ca2de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580832020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.580832020
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3033754858
Short name T2945
Test name
Test status
Simulation time 101717199 ps
CPU time 1.11 seconds
Started Jul 30 05:10:43 PM PDT 24
Finished Jul 30 05:10:44 PM PDT 24
Peak memory 206580 kb
Host smart-e89822b8-2f43-431b-b1ad-2144adc6f13f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3033754858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3033754858
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.920422718
Short name T283
Test name
Test status
Simulation time 45357731 ps
CPU time 0.73 seconds
Started Jul 30 05:10:43 PM PDT 24
Finished Jul 30 05:10:45 PM PDT 24
Peak memory 206388 kb
Host smart-eb75ca7d-d4be-4f81-a5b0-888ed9bda061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=920422718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.920422718
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.93557544
Short name T2891
Test name
Test status
Simulation time 278759062 ps
CPU time 1.67 seconds
Started Jul 30 05:10:43 PM PDT 24
Finished Jul 30 05:10:46 PM PDT 24
Peak memory 206680 kb
Host smart-caf700bc-3083-48b9-acb6-00881c59f363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=93557544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.93557544
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1002893976
Short name T227
Test name
Test status
Simulation time 256290319 ps
CPU time 3.11 seconds
Started Jul 30 05:10:43 PM PDT 24
Finished Jul 30 05:10:47 PM PDT 24
Peak memory 222704 kb
Host smart-360938b0-dc3a-4545-8216-10bd3af4bb27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1002893976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1002893976
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3687367994
Short name T2965
Test name
Test status
Simulation time 388958217 ps
CPU time 2.77 seconds
Started Jul 30 05:10:43 PM PDT 24
Finished Jul 30 05:10:46 PM PDT 24
Peak memory 206608 kb
Host smart-204fc7c7-21cb-4d2d-bde8-cd794268a04c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3687367994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3687367994
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1757168688
Short name T2940
Test name
Test status
Simulation time 150450121 ps
CPU time 1.73 seconds
Started Jul 30 05:10:44 PM PDT 24
Finished Jul 30 05:10:46 PM PDT 24
Peak memory 214524 kb
Host smart-a9d774b2-33fb-4b27-a28e-735d62a92495
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757168688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1757168688
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1088168381
Short name T262
Test name
Test status
Simulation time 78702149 ps
CPU time 1.11 seconds
Started Jul 30 05:10:44 PM PDT 24
Finished Jul 30 05:10:45 PM PDT 24
Peak memory 206632 kb
Host smart-a170907d-783a-4c79-bbfb-d41aa1041af4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1088168381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1088168381
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3828693583
Short name T2949
Test name
Test status
Simulation time 45235259 ps
CPU time 0.68 seconds
Started Jul 30 05:10:44 PM PDT 24
Finished Jul 30 05:10:45 PM PDT 24
Peak memory 206012 kb
Host smart-0e98c7ac-15c8-4587-98ac-1d1f34959477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3828693583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3828693583
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3079804558
Short name T272
Test name
Test status
Simulation time 110044114 ps
CPU time 1.17 seconds
Started Jul 30 05:10:42 PM PDT 24
Finished Jul 30 05:10:43 PM PDT 24
Peak memory 206616 kb
Host smart-76ba3cd0-e2ce-478f-b898-00dd1929cdb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3079804558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3079804558
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1044733013
Short name T2922
Test name
Test status
Simulation time 290293480 ps
CPU time 3.36 seconds
Started Jul 30 05:10:47 PM PDT 24
Finished Jul 30 05:10:50 PM PDT 24
Peak memory 206672 kb
Host smart-7a306a26-e8e6-4b82-919c-206482819a86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1044733013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1044733013
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3277496421
Short name T2953
Test name
Test status
Simulation time 486697021 ps
CPU time 2.67 seconds
Started Jul 30 05:10:41 PM PDT 24
Finished Jul 30 05:10:44 PM PDT 24
Peak memory 206688 kb
Host smart-f3a28e55-43fe-450b-980d-e16548b1d3db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3277496421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3277496421
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.940792627
Short name T2923
Test name
Test status
Simulation time 108058420 ps
CPU time 2.96 seconds
Started Jul 30 05:10:49 PM PDT 24
Finished Jul 30 05:10:52 PM PDT 24
Peak memory 214908 kb
Host smart-b7eeaf0c-14b9-4400-9087-37ece2030d4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940792627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.940792627
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.494400833
Short name T2946
Test name
Test status
Simulation time 59469034 ps
CPU time 0.83 seconds
Started Jul 30 05:10:48 PM PDT 24
Finished Jul 30 05:10:49 PM PDT 24
Peak memory 206540 kb
Host smart-591351fd-bc6f-41f4-aca4-5ab2e2d7f943
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=494400833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.494400833
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1334265221
Short name T2897
Test name
Test status
Simulation time 48747524 ps
CPU time 0.71 seconds
Started Jul 30 05:10:47 PM PDT 24
Finished Jul 30 05:10:47 PM PDT 24
Peak memory 206388 kb
Host smart-2d1616e9-5b5c-4f7b-b13c-e67c34b8a1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1334265221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1334265221
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.932356493
Short name T2976
Test name
Test status
Simulation time 170393593 ps
CPU time 1.52 seconds
Started Jul 30 05:10:47 PM PDT 24
Finished Jul 30 05:10:48 PM PDT 24
Peak memory 206620 kb
Host smart-c30b852f-5773-4ef8-a17b-edb310ef0392
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=932356493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.932356493
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2764798216
Short name T2913
Test name
Test status
Simulation time 70162962 ps
CPU time 1.63 seconds
Started Jul 30 05:10:42 PM PDT 24
Finished Jul 30 05:10:44 PM PDT 24
Peak memory 219988 kb
Host smart-36fe7def-0ef9-4548-a051-0e2589e035f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2764798216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2764798216
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.142161207
Short name T293
Test name
Test status
Simulation time 446521215 ps
CPU time 2.79 seconds
Started Jul 30 05:10:45 PM PDT 24
Finished Jul 30 05:10:48 PM PDT 24
Peak memory 206724 kb
Host smart-fe723a55-215c-4880-a1f8-b19c1ca9c6b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=142161207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.142161207
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2721106648
Short name T2920
Test name
Test status
Simulation time 92942970 ps
CPU time 1.16 seconds
Started Jul 30 05:10:46 PM PDT 24
Finished Jul 30 05:10:48 PM PDT 24
Peak memory 214784 kb
Host smart-79a19f87-7e6c-4169-806a-7294a6d915bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721106648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2721106648
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.846043698
Short name T2921
Test name
Test status
Simulation time 73745968 ps
CPU time 0.95 seconds
Started Jul 30 05:10:50 PM PDT 24
Finished Jul 30 05:10:51 PM PDT 24
Peak memory 206572 kb
Host smart-72af586a-b111-44a9-ad90-569bf5261a33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=846043698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.846043698
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3298295222
Short name T2876
Test name
Test status
Simulation time 72962907 ps
CPU time 0.76 seconds
Started Jul 30 05:10:47 PM PDT 24
Finished Jul 30 05:10:48 PM PDT 24
Peak memory 206404 kb
Host smart-0d783312-e9cd-400c-9a05-d4904ec1afa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3298295222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3298295222
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.938168471
Short name T2899
Test name
Test status
Simulation time 226448012 ps
CPU time 1.73 seconds
Started Jul 30 05:10:45 PM PDT 24
Finished Jul 30 05:10:47 PM PDT 24
Peak memory 206596 kb
Host smart-044fe39a-d6f8-4534-b418-7b4884be0b97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=938168471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.938168471
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1423285971
Short name T292
Test name
Test status
Simulation time 427417034 ps
CPU time 2.9 seconds
Started Jul 30 05:10:47 PM PDT 24
Finished Jul 30 05:10:50 PM PDT 24
Peak memory 206668 kb
Host smart-8dee41a1-8885-42e7-ac0f-d99cf93ae86e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1423285971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1423285971
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.358927572
Short name T2959
Test name
Test status
Simulation time 101325491 ps
CPU time 2.65 seconds
Started Jul 30 05:10:47 PM PDT 24
Finished Jul 30 05:10:49 PM PDT 24
Peak memory 214804 kb
Host smart-dcfa5219-1b21-4786-a0ec-d8c6e35b98be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358927572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.358927572
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2820074686
Short name T264
Test name
Test status
Simulation time 90621511 ps
CPU time 0.83 seconds
Started Jul 30 05:10:46 PM PDT 24
Finished Jul 30 05:10:47 PM PDT 24
Peak memory 206532 kb
Host smart-9ad570df-2ebe-432c-8209-90ab4adacd84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2820074686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2820074686
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3484165084
Short name T2961
Test name
Test status
Simulation time 60349824 ps
CPU time 0.72 seconds
Started Jul 30 05:10:46 PM PDT 24
Finished Jul 30 05:10:47 PM PDT 24
Peak memory 206280 kb
Host smart-a43ec9bd-f238-47f7-af86-dd6b4dd84c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3484165084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3484165084
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.331071331
Short name T2929
Test name
Test status
Simulation time 81134927 ps
CPU time 1.33 seconds
Started Jul 30 05:10:46 PM PDT 24
Finished Jul 30 05:10:47 PM PDT 24
Peak memory 206636 kb
Host smart-b1373f4f-79ca-450c-9471-5b5b34e99d3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=331071331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.331071331
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2876738226
Short name T223
Test name
Test status
Simulation time 209275026 ps
CPU time 2.42 seconds
Started Jul 30 05:10:49 PM PDT 24
Finished Jul 30 05:10:52 PM PDT 24
Peak memory 206652 kb
Host smart-be22e5e4-42f9-4d94-8d85-274269f20b95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2876738226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2876738226
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2724456902
Short name T215
Test name
Test status
Simulation time 376466185 ps
CPU time 2.61 seconds
Started Jul 30 05:10:49 PM PDT 24
Finished Jul 30 05:10:52 PM PDT 24
Peak memory 206676 kb
Host smart-2b33a329-f064-4b43-af84-b3a0d849708f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2724456902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2724456902
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3524603665
Short name T2911
Test name
Test status
Simulation time 238353067 ps
CPU time 2.08 seconds
Started Jul 30 05:10:09 PM PDT 24
Finished Jul 30 05:10:11 PM PDT 24
Peak memory 206648 kb
Host smart-17db4024-e2f8-4873-865a-011b7a41762f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3524603665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3524603665
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3701318642
Short name T2934
Test name
Test status
Simulation time 1545006055 ps
CPU time 8.35 seconds
Started Jul 30 05:10:10 PM PDT 24
Finished Jul 30 05:10:18 PM PDT 24
Peak memory 206572 kb
Host smart-ea9027df-0f28-4261-81ae-8cc9d6ad5f43
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3701318642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3701318642
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3213949683
Short name T261
Test name
Test status
Simulation time 159570177 ps
CPU time 0.91 seconds
Started Jul 30 05:10:10 PM PDT 24
Finished Jul 30 05:10:11 PM PDT 24
Peak memory 206436 kb
Host smart-a2bd8762-d943-49be-b218-b88008d50166
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3213949683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3213949683
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1827261832
Short name T231
Test name
Test status
Simulation time 178959563 ps
CPU time 1.75 seconds
Started Jul 30 05:10:07 PM PDT 24
Finished Jul 30 05:10:09 PM PDT 24
Peak memory 214704 kb
Host smart-39362dbf-4d28-4e21-8805-ac7ccc260615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827261832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1827261832
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2103572784
Short name T2892
Test name
Test status
Simulation time 50419632 ps
CPU time 0.77 seconds
Started Jul 30 05:10:13 PM PDT 24
Finished Jul 30 05:10:13 PM PDT 24
Peak memory 206376 kb
Host smart-7bc18b35-2a4d-4080-953f-739c6a7b09a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2103572784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2103572784
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3077963697
Short name T2957
Test name
Test status
Simulation time 87875558 ps
CPU time 0.79 seconds
Started Jul 30 05:10:06 PM PDT 24
Finished Jul 30 05:10:07 PM PDT 24
Peak memory 206388 kb
Host smart-e3475be5-04a1-40ed-98df-497843283d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3077963697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3077963697
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3052723013
Short name T2971
Test name
Test status
Simulation time 104790133 ps
CPU time 1.42 seconds
Started Jul 30 05:10:04 PM PDT 24
Finished Jul 30 05:10:06 PM PDT 24
Peak memory 206624 kb
Host smart-6b53b222-8831-42ff-a0c0-ed54af9f0cd4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3052723013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3052723013
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.887764520
Short name T2881
Test name
Test status
Simulation time 479532395 ps
CPU time 4.47 seconds
Started Jul 30 05:10:11 PM PDT 24
Finished Jul 30 05:10:15 PM PDT 24
Peak memory 206500 kb
Host smart-ddbccebb-c738-4aa2-87a3-28caa4b3a474
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=887764520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.887764520
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1653053221
Short name T2887
Test name
Test status
Simulation time 92262155 ps
CPU time 1.49 seconds
Started Jul 30 05:10:15 PM PDT 24
Finished Jul 30 05:10:17 PM PDT 24
Peak memory 206588 kb
Host smart-2f66df13-fb1f-4e36-a953-e876661e0b1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1653053221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1653053221
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1631226416
Short name T2914
Test name
Test status
Simulation time 66839972 ps
CPU time 1.82 seconds
Started Jul 30 05:10:06 PM PDT 24
Finished Jul 30 05:10:08 PM PDT 24
Peak memory 222876 kb
Host smart-3748afc6-5180-4282-b207-1c8e3c567537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1631226416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1631226416
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.836370503
Short name T288
Test name
Test status
Simulation time 426414870 ps
CPU time 2.75 seconds
Started Jul 30 05:10:06 PM PDT 24
Finished Jul 30 05:10:08 PM PDT 24
Peak memory 206644 kb
Host smart-cbb266db-a138-41f1-af89-5566f49213ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=836370503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.836370503
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2216404479
Short name T2931
Test name
Test status
Simulation time 60955969 ps
CPU time 0.78 seconds
Started Jul 30 05:10:52 PM PDT 24
Finished Jul 30 05:10:53 PM PDT 24
Peak memory 206452 kb
Host smart-5dc75c7f-53c6-4f0a-934f-ccbb23305f76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2216404479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2216404479
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3505987743
Short name T2872
Test name
Test status
Simulation time 56237366 ps
CPU time 0.79 seconds
Started Jul 30 05:10:53 PM PDT 24
Finished Jul 30 05:10:54 PM PDT 24
Peak memory 206348 kb
Host smart-b8b353eb-84dc-4223-aa7a-5362597ada76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3505987743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3505987743
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1990153089
Short name T200
Test name
Test status
Simulation time 39595934 ps
CPU time 0.73 seconds
Started Jul 30 05:10:51 PM PDT 24
Finished Jul 30 05:10:52 PM PDT 24
Peak memory 206336 kb
Host smart-4676ede7-dd07-48c0-8e68-b75777279bab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1990153089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1990153089
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2981200475
Short name T2880
Test name
Test status
Simulation time 36109033 ps
CPU time 0.69 seconds
Started Jul 30 05:10:50 PM PDT 24
Finished Jul 30 05:10:51 PM PDT 24
Peak memory 206372 kb
Host smart-02c7e112-8f12-421a-9ffb-7bd76ddd204d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2981200475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2981200475
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2245992515
Short name T2886
Test name
Test status
Simulation time 53055418 ps
CPU time 0.75 seconds
Started Jul 30 05:10:52 PM PDT 24
Finished Jul 30 05:10:53 PM PDT 24
Peak memory 206312 kb
Host smart-a1b01181-b6d2-4c12-9669-214266222872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2245992515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2245992515
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2177652985
Short name T2885
Test name
Test status
Simulation time 41150765 ps
CPU time 0.7 seconds
Started Jul 30 05:10:50 PM PDT 24
Finished Jul 30 05:10:51 PM PDT 24
Peak memory 206396 kb
Host smart-ab8bb50f-3152-4879-81f9-5f958588e276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2177652985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2177652985
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3466579954
Short name T2977
Test name
Test status
Simulation time 63205932 ps
CPU time 0.74 seconds
Started Jul 30 05:10:51 PM PDT 24
Finished Jul 30 05:10:52 PM PDT 24
Peak memory 206404 kb
Host smart-14faf7a1-a5ae-40d7-8f96-73051c46f833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3466579954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3466579954
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2545071903
Short name T2888
Test name
Test status
Simulation time 58429158 ps
CPU time 0.8 seconds
Started Jul 30 05:10:55 PM PDT 24
Finished Jul 30 05:10:55 PM PDT 24
Peak memory 206336 kb
Host smart-27e4a7fc-8d16-4015-8374-65ff728ed2dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2545071903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2545071903
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.481434551
Short name T2937
Test name
Test status
Simulation time 60261100 ps
CPU time 0.77 seconds
Started Jul 30 05:10:53 PM PDT 24
Finished Jul 30 05:10:54 PM PDT 24
Peak memory 206396 kb
Host smart-587c1a72-251b-4176-8542-5640e2ce9780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=481434551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.481434551
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1326802370
Short name T2917
Test name
Test status
Simulation time 300528096 ps
CPU time 3.47 seconds
Started Jul 30 05:10:16 PM PDT 24
Finished Jul 30 05:10:20 PM PDT 24
Peak memory 206636 kb
Host smart-01a5ba62-0051-4d7d-90a6-9fe7317a4831
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1326802370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1326802370
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1183435119
Short name T2963
Test name
Test status
Simulation time 541681937 ps
CPU time 7.71 seconds
Started Jul 30 05:10:13 PM PDT 24
Finished Jul 30 05:10:21 PM PDT 24
Peak memory 206644 kb
Host smart-30294699-20bf-4908-bbda-c0d34e000d58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1183435119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1183435119
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2271007766
Short name T2909
Test name
Test status
Simulation time 121904332 ps
CPU time 0.89 seconds
Started Jul 30 05:10:13 PM PDT 24
Finished Jul 30 05:10:14 PM PDT 24
Peak memory 206460 kb
Host smart-2f2b09ca-eaf2-4fae-a1d6-b90ad97a0b9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2271007766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2271007766
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3057388742
Short name T2905
Test name
Test status
Simulation time 137955603 ps
CPU time 1.43 seconds
Started Jul 30 05:10:19 PM PDT 24
Finished Jul 30 05:10:20 PM PDT 24
Peak memory 214968 kb
Host smart-070ad7c8-5e8a-4e50-ad21-04a86d1e9665
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057388742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3057388742
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.137100580
Short name T2904
Test name
Test status
Simulation time 129445090 ps
CPU time 1.12 seconds
Started Jul 30 05:10:13 PM PDT 24
Finished Jul 30 05:10:14 PM PDT 24
Peak memory 206588 kb
Host smart-0a20ce9f-0bce-4c64-8309-4bfa1900ae9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=137100580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.137100580
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3404160534
Short name T2867
Test name
Test status
Simulation time 77736481 ps
CPU time 0.78 seconds
Started Jul 30 05:10:13 PM PDT 24
Finished Jul 30 05:10:14 PM PDT 24
Peak memory 206360 kb
Host smart-dcbd12af-f49a-456d-8979-aa69716dd4c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3404160534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3404160534
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3600970613
Short name T2956
Test name
Test status
Simulation time 112211288 ps
CPU time 1.41 seconds
Started Jul 30 05:10:15 PM PDT 24
Finished Jul 30 05:10:17 PM PDT 24
Peak memory 206604 kb
Host smart-348d4592-254e-4da9-9694-c69c9727f335
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3600970613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3600970613
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2262629040
Short name T2951
Test name
Test status
Simulation time 168291198 ps
CPU time 3.89 seconds
Started Jul 30 05:10:12 PM PDT 24
Finished Jul 30 05:10:16 PM PDT 24
Peak memory 206576 kb
Host smart-f362b577-72d9-414d-8253-2cfee1c6be17
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2262629040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2262629040
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3644647176
Short name T2975
Test name
Test status
Simulation time 154047969 ps
CPU time 1.61 seconds
Started Jul 30 05:10:11 PM PDT 24
Finished Jul 30 05:10:13 PM PDT 24
Peak memory 206628 kb
Host smart-a4f70a2f-22a0-474b-ba66-5ff831a5f953
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3644647176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3644647176
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4125711140
Short name T2938
Test name
Test status
Simulation time 240596738 ps
CPU time 3.41 seconds
Started Jul 30 05:10:09 PM PDT 24
Finished Jul 30 05:10:13 PM PDT 24
Peak memory 206604 kb
Host smart-e6d114ba-68cf-4201-9cbd-124221d21c94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4125711140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.4125711140
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3599754933
Short name T2877
Test name
Test status
Simulation time 40883831 ps
CPU time 0.75 seconds
Started Jul 30 05:10:55 PM PDT 24
Finished Jul 30 05:10:55 PM PDT 24
Peak memory 206332 kb
Host smart-f87ddfc0-59af-42fa-a776-af6a58e22a0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3599754933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3599754933
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.130751626
Short name T198
Test name
Test status
Simulation time 57468608 ps
CPU time 0.77 seconds
Started Jul 30 05:10:53 PM PDT 24
Finished Jul 30 05:10:54 PM PDT 24
Peak memory 206388 kb
Host smart-6c976012-de43-4871-9654-940cd83837ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=130751626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.130751626
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.861865810
Short name T2962
Test name
Test status
Simulation time 43997882 ps
CPU time 0.75 seconds
Started Jul 30 05:10:51 PM PDT 24
Finished Jul 30 05:10:52 PM PDT 24
Peak memory 206384 kb
Host smart-a5b150c1-faea-4141-aa91-126a7f63a36f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=861865810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.861865810
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3671483668
Short name T284
Test name
Test status
Simulation time 71319245 ps
CPU time 0.76 seconds
Started Jul 30 05:10:55 PM PDT 24
Finished Jul 30 05:10:56 PM PDT 24
Peak memory 206364 kb
Host smart-bd2caee8-9e71-4658-b757-a4db4a5512d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3671483668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3671483668
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1096237684
Short name T2907
Test name
Test status
Simulation time 40162966 ps
CPU time 0.73 seconds
Started Jul 30 05:10:54 PM PDT 24
Finished Jul 30 05:10:55 PM PDT 24
Peak memory 206356 kb
Host smart-92b73131-1169-4f53-aaa2-bab6a28a8179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1096237684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1096237684
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3683559640
Short name T2932
Test name
Test status
Simulation time 48963289 ps
CPU time 0.73 seconds
Started Jul 30 05:10:55 PM PDT 24
Finished Jul 30 05:10:56 PM PDT 24
Peak memory 206388 kb
Host smart-0970cfb7-d006-4c81-bfd5-0ae71daa685c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3683559640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3683559640
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2998153137
Short name T201
Test name
Test status
Simulation time 40350770 ps
CPU time 0.69 seconds
Started Jul 30 05:10:56 PM PDT 24
Finished Jul 30 05:10:57 PM PDT 24
Peak memory 206312 kb
Host smart-094fe2f8-1f9d-4c3b-b2cf-6092a97b0524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2998153137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2998153137
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2664357109
Short name T2919
Test name
Test status
Simulation time 44839825 ps
CPU time 0.76 seconds
Started Jul 30 05:10:56 PM PDT 24
Finished Jul 30 05:10:57 PM PDT 24
Peak memory 206416 kb
Host smart-f4f697ff-cd51-4021-a673-1f648481d7e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2664357109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2664357109
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3908915423
Short name T2874
Test name
Test status
Simulation time 32515326 ps
CPU time 0.73 seconds
Started Jul 30 05:10:53 PM PDT 24
Finished Jul 30 05:10:54 PM PDT 24
Peak memory 206372 kb
Host smart-fd9f46b9-80bb-4d1b-8221-796081ac733a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3908915423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3908915423
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3500740835
Short name T2894
Test name
Test status
Simulation time 31850264 ps
CPU time 0.69 seconds
Started Jul 30 05:10:53 PM PDT 24
Finished Jul 30 05:10:54 PM PDT 24
Peak memory 206396 kb
Host smart-0e959b7d-7493-4fb0-8b4f-43fede86dd3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3500740835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3500740835
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3044615352
Short name T2916
Test name
Test status
Simulation time 126277094 ps
CPU time 3.49 seconds
Started Jul 30 05:10:16 PM PDT 24
Finished Jul 30 05:10:19 PM PDT 24
Peak memory 206604 kb
Host smart-3e55753e-3381-4e0a-a9be-47b527c883eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3044615352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3044615352
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4010783512
Short name T2967
Test name
Test status
Simulation time 341488590 ps
CPU time 4.41 seconds
Started Jul 30 05:10:17 PM PDT 24
Finished Jul 30 05:10:22 PM PDT 24
Peak memory 206632 kb
Host smart-54f88a90-249e-4ee5-bece-2aa12b59cbbb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4010783512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.4010783512
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1034327129
Short name T2901
Test name
Test status
Simulation time 90389157 ps
CPU time 0.94 seconds
Started Jul 30 05:10:16 PM PDT 24
Finished Jul 30 05:10:17 PM PDT 24
Peak memory 206432 kb
Host smart-f6a271e7-f752-4592-b9b3-348f98d7ac39
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1034327129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1034327129
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1931905512
Short name T237
Test name
Test status
Simulation time 172096969 ps
CPU time 1.95 seconds
Started Jul 30 05:10:16 PM PDT 24
Finished Jul 30 05:10:18 PM PDT 24
Peak memory 214920 kb
Host smart-e3386182-a180-4747-97d8-0aca46b1e42d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931905512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1931905512
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1156302415
Short name T268
Test name
Test status
Simulation time 60388350 ps
CPU time 0.98 seconds
Started Jul 30 05:10:19 PM PDT 24
Finished Jul 30 05:10:20 PM PDT 24
Peak memory 206520 kb
Host smart-1661db37-0f1e-47c4-b2fb-f27c6cc6fa8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1156302415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1156302415
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2210560661
Short name T2915
Test name
Test status
Simulation time 44931807 ps
CPU time 0.76 seconds
Started Jul 30 05:10:18 PM PDT 24
Finished Jul 30 05:10:19 PM PDT 24
Peak memory 206416 kb
Host smart-6576cbbb-b3a3-4e68-95cf-111cc21c5bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2210560661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2210560661
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3982031461
Short name T259
Test name
Test status
Simulation time 111932057 ps
CPU time 1.41 seconds
Started Jul 30 05:10:18 PM PDT 24
Finished Jul 30 05:10:19 PM PDT 24
Peak memory 206612 kb
Host smart-92c89b86-2ee2-4252-bb88-884dfbeca284
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3982031461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3982031461
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1225764070
Short name T2873
Test name
Test status
Simulation time 489985972 ps
CPU time 4.45 seconds
Started Jul 30 05:10:17 PM PDT 24
Finished Jul 30 05:10:21 PM PDT 24
Peak memory 206596 kb
Host smart-fff53184-63b3-4d69-859e-ef774e141081
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1225764070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1225764070
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3177402824
Short name T2903
Test name
Test status
Simulation time 103691631 ps
CPU time 1.51 seconds
Started Jul 30 05:10:20 PM PDT 24
Finished Jul 30 05:10:21 PM PDT 24
Peak memory 206644 kb
Host smart-42578848-0cf8-4ef5-a455-0ee64cf8dd21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3177402824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3177402824
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3723251451
Short name T2973
Test name
Test status
Simulation time 506153217 ps
CPU time 3.93 seconds
Started Jul 30 05:10:14 PM PDT 24
Finished Jul 30 05:10:18 PM PDT 24
Peak memory 206532 kb
Host smart-ae96d230-b3b2-4440-bf03-0d8621c33d69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3723251451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3723251451
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3363412244
Short name T2884
Test name
Test status
Simulation time 37520385 ps
CPU time 0.71 seconds
Started Jul 30 05:10:55 PM PDT 24
Finished Jul 30 05:10:56 PM PDT 24
Peak memory 206408 kb
Host smart-07c2bc2a-2007-4b01-8937-cca42b764696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3363412244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3363412244
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3816808963
Short name T2902
Test name
Test status
Simulation time 33595139 ps
CPU time 0.68 seconds
Started Jul 30 05:10:55 PM PDT 24
Finished Jul 30 05:10:56 PM PDT 24
Peak memory 206372 kb
Host smart-56b475f6-9a12-4771-8fac-af1b7fa5e5df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3816808963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3816808963
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2984948438
Short name T285
Test name
Test status
Simulation time 65953360 ps
CPU time 0.75 seconds
Started Jul 30 05:10:55 PM PDT 24
Finished Jul 30 05:10:56 PM PDT 24
Peak memory 206452 kb
Host smart-74f13a35-1b38-4ce8-8d66-13abe809ee3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2984948438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2984948438
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1174628137
Short name T2948
Test name
Test status
Simulation time 59270967 ps
CPU time 0.72 seconds
Started Jul 30 05:10:54 PM PDT 24
Finished Jul 30 05:10:55 PM PDT 24
Peak memory 206348 kb
Host smart-c71c8abe-ab38-4072-91a7-1cda60a2d64e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1174628137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1174628137
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.380610953
Short name T2868
Test name
Test status
Simulation time 55662846 ps
CPU time 0.79 seconds
Started Jul 30 05:11:01 PM PDT 24
Finished Jul 30 05:11:02 PM PDT 24
Peak memory 206320 kb
Host smart-59fbb503-9556-45ff-9ae9-490c6a898666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=380610953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.380610953
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4149317935
Short name T2970
Test name
Test status
Simulation time 32821525 ps
CPU time 0.7 seconds
Started Jul 30 05:10:57 PM PDT 24
Finished Jul 30 05:10:58 PM PDT 24
Peak memory 206352 kb
Host smart-0c740c94-11d0-436d-b7a9-8139c24c1d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4149317935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.4149317935
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3223982141
Short name T2954
Test name
Test status
Simulation time 48502449 ps
CPU time 0.71 seconds
Started Jul 30 05:10:58 PM PDT 24
Finished Jul 30 05:10:59 PM PDT 24
Peak memory 206372 kb
Host smart-64490e5f-9569-480e-967f-de628bf56f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3223982141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3223982141
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.950231944
Short name T2895
Test name
Test status
Simulation time 70792326 ps
CPU time 0.76 seconds
Started Jul 30 05:10:55 PM PDT 24
Finished Jul 30 05:10:56 PM PDT 24
Peak memory 206408 kb
Host smart-b0e2b15c-4419-406c-be96-554729031929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=950231944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.950231944
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2030887486
Short name T199
Test name
Test status
Simulation time 40392223 ps
CPU time 0.75 seconds
Started Jul 30 05:10:53 PM PDT 24
Finished Jul 30 05:10:54 PM PDT 24
Peak memory 206400 kb
Host smart-c95476e5-a48e-46ea-987d-865d99abd4f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2030887486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2030887486
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.936020454
Short name T214
Test name
Test status
Simulation time 185677218 ps
CPU time 1.92 seconds
Started Jul 30 05:10:24 PM PDT 24
Finished Jul 30 05:10:26 PM PDT 24
Peak memory 214864 kb
Host smart-86705426-cd98-470b-8ced-994afcaff7c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936020454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.936020454
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.994505672
Short name T2869
Test name
Test status
Simulation time 73674176 ps
CPU time 0.76 seconds
Started Jul 30 05:10:20 PM PDT 24
Finished Jul 30 05:10:21 PM PDT 24
Peak memory 206320 kb
Host smart-057d67ae-80d6-4a83-ae4b-631527bd74c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=994505672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.994505672
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.997442758
Short name T190
Test name
Test status
Simulation time 92726260 ps
CPU time 1.4 seconds
Started Jul 30 05:10:23 PM PDT 24
Finished Jul 30 05:10:24 PM PDT 24
Peak memory 206628 kb
Host smart-4947e4f7-91d9-4f3a-8d76-f67d157ccdda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=997442758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.997442758
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.880526299
Short name T228
Test name
Test status
Simulation time 104408387 ps
CPU time 3.08 seconds
Started Jul 30 05:10:17 PM PDT 24
Finished Jul 30 05:10:20 PM PDT 24
Peak memory 214924 kb
Host smart-60acf6f0-297f-4c22-9c45-bee7210f7ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=880526299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.880526299
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3593064113
Short name T291
Test name
Test status
Simulation time 400486827 ps
CPU time 2.69 seconds
Started Jul 30 05:10:20 PM PDT 24
Finished Jul 30 05:10:22 PM PDT 24
Peak memory 206692 kb
Host smart-429b0875-4674-47ad-9ef6-b26dd541210d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3593064113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3593064113
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2732898330
Short name T2927
Test name
Test status
Simulation time 95920200 ps
CPU time 1.26 seconds
Started Jul 30 05:10:26 PM PDT 24
Finished Jul 30 05:10:27 PM PDT 24
Peak memory 214860 kb
Host smart-09bd1157-c50e-4c63-aeea-fbac2714be75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732898330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2732898330
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1824178402
Short name T233
Test name
Test status
Simulation time 56386467 ps
CPU time 0.82 seconds
Started Jul 30 05:10:26 PM PDT 24
Finished Jul 30 05:10:27 PM PDT 24
Peak memory 206548 kb
Host smart-8b581791-306d-4939-a90c-7e061de89c4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1824178402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1824178402
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.401352743
Short name T2918
Test name
Test status
Simulation time 53918345 ps
CPU time 0.75 seconds
Started Jul 30 05:10:21 PM PDT 24
Finished Jul 30 05:10:22 PM PDT 24
Peak memory 206400 kb
Host smart-8ecf39a2-92bd-44ff-b054-c34107a5ca59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=401352743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.401352743
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3111498261
Short name T2883
Test name
Test status
Simulation time 241446685 ps
CPU time 1.53 seconds
Started Jul 30 05:10:24 PM PDT 24
Finished Jul 30 05:10:25 PM PDT 24
Peak memory 206656 kb
Host smart-62bd8621-35ef-4a90-a03e-f10906ec1071
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3111498261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3111498261
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1130436850
Short name T2974
Test name
Test status
Simulation time 192376120 ps
CPU time 2.55 seconds
Started Jul 30 05:10:21 PM PDT 24
Finished Jul 30 05:10:24 PM PDT 24
Peak memory 206644 kb
Host smart-ede0888a-603b-4933-9396-9e8dea7f430d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1130436850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1130436850
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3502228063
Short name T2944
Test name
Test status
Simulation time 2378483592 ps
CPU time 6.55 seconds
Started Jul 30 05:10:20 PM PDT 24
Finished Jul 30 05:10:27 PM PDT 24
Peak memory 206628 kb
Host smart-8f911456-40b6-42b8-b108-3f87d1ddc76e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3502228063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3502228063
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3184479192
Short name T239
Test name
Test status
Simulation time 166275347 ps
CPU time 1.74 seconds
Started Jul 30 05:10:26 PM PDT 24
Finished Jul 30 05:10:28 PM PDT 24
Peak memory 214832 kb
Host smart-e172db13-7697-4a36-b9ab-9a5e4bf7c18a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184479192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3184479192
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1918497261
Short name T192
Test name
Test status
Simulation time 79261153 ps
CPU time 1.03 seconds
Started Jul 30 05:10:24 PM PDT 24
Finished Jul 30 05:10:26 PM PDT 24
Peak memory 206508 kb
Host smart-641a3dac-8ce7-41d3-9f91-9609f931b44f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1918497261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1918497261
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.953307627
Short name T2866
Test name
Test status
Simulation time 49859514 ps
CPU time 0.71 seconds
Started Jul 30 05:10:25 PM PDT 24
Finished Jul 30 05:10:26 PM PDT 24
Peak memory 206376 kb
Host smart-19be4aa2-f3e7-40e8-a930-789f60d41af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=953307627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.953307627
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1018970029
Short name T191
Test name
Test status
Simulation time 164559660 ps
CPU time 1.8 seconds
Started Jul 30 05:10:26 PM PDT 24
Finished Jul 30 05:10:28 PM PDT 24
Peak memory 206660 kb
Host smart-c39665fc-0735-4081-9e01-3d8c5752b80a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1018970029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1018970029
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4247308690
Short name T2933
Test name
Test status
Simulation time 215143756 ps
CPU time 2.48 seconds
Started Jul 30 05:10:24 PM PDT 24
Finished Jul 30 05:10:27 PM PDT 24
Peak memory 206744 kb
Host smart-a56e52a8-318f-4bf5-8807-57463c1e8562
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4247308690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.4247308690
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3103059207
Short name T240
Test name
Test status
Simulation time 2154062401 ps
CPU time 7.11 seconds
Started Jul 30 05:10:28 PM PDT 24
Finished Jul 30 05:10:35 PM PDT 24
Peak memory 206692 kb
Host smart-8b1df45d-8307-4efa-b7f2-6c1e73ac4a43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3103059207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3103059207
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3711626925
Short name T2969
Test name
Test status
Simulation time 78672495 ps
CPU time 1.16 seconds
Started Jul 30 05:10:28 PM PDT 24
Finished Jul 30 05:10:29 PM PDT 24
Peak memory 214748 kb
Host smart-866548db-9ae5-495f-b77c-e9991fd672df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711626925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3711626925
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2937413048
Short name T2870
Test name
Test status
Simulation time 62342042 ps
CPU time 1.01 seconds
Started Jul 30 05:10:31 PM PDT 24
Finished Jul 30 05:10:32 PM PDT 24
Peak memory 206532 kb
Host smart-603fbce5-f2cb-4d09-95bc-87183a4489b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2937413048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2937413048
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2258206473
Short name T2890
Test name
Test status
Simulation time 41330756 ps
CPU time 0.69 seconds
Started Jul 30 05:10:29 PM PDT 24
Finished Jul 30 05:10:30 PM PDT 24
Peak memory 206396 kb
Host smart-d1dc1289-3e13-4fdd-9eee-f38bbd191972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2258206473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2258206473
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2848823280
Short name T2882
Test name
Test status
Simulation time 220495057 ps
CPU time 1.74 seconds
Started Jul 30 05:10:30 PM PDT 24
Finished Jul 30 05:10:32 PM PDT 24
Peak memory 206744 kb
Host smart-fe79c16d-030c-45bc-8763-445ca387cb69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2848823280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2848823280
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4262920764
Short name T2950
Test name
Test status
Simulation time 244842079 ps
CPU time 3.15 seconds
Started Jul 30 05:10:27 PM PDT 24
Finished Jul 30 05:10:30 PM PDT 24
Peak memory 219740 kb
Host smart-957b8c88-5715-46ea-9ac5-24b69745f43d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4262920764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.4262920764
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.326747100
Short name T2943
Test name
Test status
Simulation time 107254283 ps
CPU time 1.81 seconds
Started Jul 30 05:10:35 PM PDT 24
Finished Jul 30 05:10:37 PM PDT 24
Peak memory 214936 kb
Host smart-bf045e77-539d-446c-81f8-d76b71e9b92a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326747100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.326747100
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1538294451
Short name T263
Test name
Test status
Simulation time 46237203 ps
CPU time 0.77 seconds
Started Jul 30 05:10:28 PM PDT 24
Finished Jul 30 05:10:29 PM PDT 24
Peak memory 206512 kb
Host smart-6f1cc049-c9e2-4f65-8e64-98dffd1f101c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1538294451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1538294451
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3677510336
Short name T277
Test name
Test status
Simulation time 40137318 ps
CPU time 0.71 seconds
Started Jul 30 05:10:30 PM PDT 24
Finished Jul 30 05:10:31 PM PDT 24
Peak memory 206456 kb
Host smart-d943b960-fbc8-43c7-9f88-858a508c8c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3677510336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3677510336
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1176196239
Short name T270
Test name
Test status
Simulation time 227920340 ps
CPU time 1.62 seconds
Started Jul 30 05:10:28 PM PDT 24
Finished Jul 30 05:10:30 PM PDT 24
Peak memory 206700 kb
Host smart-220e2fdc-e2fb-4c4e-9728-4d3dbeaf56c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1176196239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1176196239
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1073897144
Short name T2972
Test name
Test status
Simulation time 94626748 ps
CPU time 2.44 seconds
Started Jul 30 05:10:30 PM PDT 24
Finished Jul 30 05:10:32 PM PDT 24
Peak memory 214860 kb
Host smart-d750d879-d0e8-4e9c-855d-79586e72ba6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1073897144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1073897144
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2368978227
Short name T294
Test name
Test status
Simulation time 871285780 ps
CPU time 4.39 seconds
Started Jul 30 05:10:28 PM PDT 24
Finished Jul 30 05:10:32 PM PDT 24
Peak memory 206664 kb
Host smart-24345487-d377-4c38-97ee-ea94866d5aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2368978227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2368978227
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.1624615570
Short name T1639
Test name
Test status
Simulation time 54743527 ps
CPU time 0.68 seconds
Started Jul 30 06:27:44 PM PDT 24
Finished Jul 30 06:27:45 PM PDT 24
Peak memory 207024 kb
Host smart-7dd86977-9db3-427f-8fdd-790c0cbdb0b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1624615570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1624615570
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1243605602
Short name T438
Test name
Test status
Simulation time 3620436532 ps
CPU time 6.32 seconds
Started Jul 30 06:27:23 PM PDT 24
Finished Jul 30 06:27:29 PM PDT 24
Peak memory 207072 kb
Host smart-66c9ceb1-3a13-4198-b674-295115ae0f57
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243605602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.1243605602
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.516136755
Short name T2553
Test name
Test status
Simulation time 13465416484 ps
CPU time 17.4 seconds
Started Jul 30 06:27:27 PM PDT 24
Finished Jul 30 06:27:45 PM PDT 24
Peak memory 207116 kb
Host smart-a5e4e29c-be0a-4343-8dea-440a2d8dc213
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=516136755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.516136755
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.1064585223
Short name T2072
Test name
Test status
Simulation time 23305571954 ps
CPU time 29.46 seconds
Started Jul 30 06:27:29 PM PDT 24
Finished Jul 30 06:27:58 PM PDT 24
Peak memory 207160 kb
Host smart-919ebc0f-c566-44e1-9383-c972db6bcb93
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064585223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.1064585223
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.137183782
Short name T1842
Test name
Test status
Simulation time 203279822 ps
CPU time 0.84 seconds
Started Jul 30 06:27:26 PM PDT 24
Finished Jul 30 06:27:27 PM PDT 24
Peak memory 206900 kb
Host smart-388be1d7-2ac0-4605-b40b-fc6a232cb00c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13718
3782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.137183782
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1116167171
Short name T714
Test name
Test status
Simulation time 152877298 ps
CPU time 0.81 seconds
Started Jul 30 06:27:28 PM PDT 24
Finished Jul 30 06:27:29 PM PDT 24
Peak memory 206940 kb
Host smart-8e101eb3-4de3-440f-9f65-5795425c5434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11161
67171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1116167171
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.602234310
Short name T91
Test name
Test status
Simulation time 434957318 ps
CPU time 1.61 seconds
Started Jul 30 06:27:33 PM PDT 24
Finished Jul 30 06:27:35 PM PDT 24
Peak memory 206936 kb
Host smart-068065fd-465b-4e13-b715-6b781aa4ef0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60223
4310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.602234310
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2731045672
Short name T2543
Test name
Test status
Simulation time 773093863 ps
CPU time 2.14 seconds
Started Jul 30 06:27:46 PM PDT 24
Finished Jul 30 06:27:48 PM PDT 24
Peak memory 207060 kb
Host smart-5463cd88-8cee-4782-bb75-6fb8ec27c362
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2731045672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2731045672
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3016673678
Short name T2434
Test name
Test status
Simulation time 7752943620 ps
CPU time 18.37 seconds
Started Jul 30 06:27:35 PM PDT 24
Finished Jul 30 06:27:54 PM PDT 24
Peak memory 207108 kb
Host smart-3ef5bae0-8a58-4739-aad0-8d577f188a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30166
73678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3016673678
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.1357671557
Short name T2794
Test name
Test status
Simulation time 2849070807 ps
CPU time 18.88 seconds
Started Jul 30 06:27:40 PM PDT 24
Finished Jul 30 06:27:59 PM PDT 24
Peak memory 207152 kb
Host smart-75f55fe5-b7ab-4872-b6bc-4c0a2c1d2413
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357671557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.1357671557
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3175795111
Short name T658
Test name
Test status
Simulation time 434594215 ps
CPU time 1.39 seconds
Started Jul 30 06:27:32 PM PDT 24
Finished Jul 30 06:27:33 PM PDT 24
Peak memory 206920 kb
Host smart-372d49ea-83d5-4e36-b9de-33e9b3ee2c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31757
95111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3175795111
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.4093254745
Short name T2820
Test name
Test status
Simulation time 146703064 ps
CPU time 0.83 seconds
Started Jul 30 06:27:32 PM PDT 24
Finished Jul 30 06:27:33 PM PDT 24
Peak memory 206924 kb
Host smart-e74d0552-5aa8-469d-a695-6a26405248e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40932
54745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.4093254745
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.854781519
Short name T2141
Test name
Test status
Simulation time 42847871 ps
CPU time 0.71 seconds
Started Jul 30 06:27:38 PM PDT 24
Finished Jul 30 06:27:39 PM PDT 24
Peak memory 206896 kb
Host smart-0a673bc0-cbdc-43e7-8a2a-7e6ffb5afcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85478
1519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.854781519
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3017627913
Short name T209
Test name
Test status
Simulation time 870729961 ps
CPU time 2.53 seconds
Started Jul 30 06:27:42 PM PDT 24
Finished Jul 30 06:27:45 PM PDT 24
Peak memory 207100 kb
Host smart-7b27c613-c964-4be1-82b9-2832b303c85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30176
27913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3017627913
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.2172772920
Short name T1308
Test name
Test status
Simulation time 118181152897 ps
CPU time 191.68 seconds
Started Jul 30 06:27:32 PM PDT 24
Finished Jul 30 06:30:44 PM PDT 24
Peak memory 207176 kb
Host smart-28d44628-f7ff-4844-9292-4eab296d6aa5
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2172772920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2172772920
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.1433075537
Short name T1523
Test name
Test status
Simulation time 105062828578 ps
CPU time 169.97 seconds
Started Jul 30 06:27:27 PM PDT 24
Finished Jul 30 06:30:17 PM PDT 24
Peak memory 207108 kb
Host smart-8890ebf4-1470-41fe-9dd2-0c9c13198097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433075537 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.1433075537
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.4233479937
Short name T2253
Test name
Test status
Simulation time 121115202176 ps
CPU time 221.11 seconds
Started Jul 30 06:27:34 PM PDT 24
Finished Jul 30 06:31:15 PM PDT 24
Peak memory 207088 kb
Host smart-461025fb-1235-4f97-9bb1-2fd6886121e3
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4233479937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.4233479937
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.2768110738
Short name T2556
Test name
Test status
Simulation time 110918206315 ps
CPU time 191.85 seconds
Started Jul 30 06:27:52 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 207112 kb
Host smart-10122131-b02d-46f0-8084-7a414c13347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768110738 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.2768110738
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.3319723462
Short name T2809
Test name
Test status
Simulation time 81140322448 ps
CPU time 131.6 seconds
Started Jul 30 06:27:38 PM PDT 24
Finished Jul 30 06:29:50 PM PDT 24
Peak memory 207124 kb
Host smart-80ccf73a-23ef-449e-9b63-4fcf3928b31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33197
23462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.3319723462
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.48310852
Short name T1970
Test name
Test status
Simulation time 183218032 ps
CPU time 0.96 seconds
Started Jul 30 06:27:32 PM PDT 24
Finished Jul 30 06:27:33 PM PDT 24
Peak memory 215256 kb
Host smart-8bd8ff1b-e8fd-443a-bdc0-c2b799e9402a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=48310852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.48310852
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2385595820
Short name T1607
Test name
Test status
Simulation time 183572105 ps
CPU time 0.87 seconds
Started Jul 30 06:27:30 PM PDT 24
Finished Jul 30 06:27:31 PM PDT 24
Peak memory 206948 kb
Host smart-5502d855-70be-4853-b3a5-f6dd15dac46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23855
95820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2385595820
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.4168090181
Short name T606
Test name
Test status
Simulation time 215981146 ps
CPU time 0.9 seconds
Started Jul 30 06:27:44 PM PDT 24
Finished Jul 30 06:27:45 PM PDT 24
Peak memory 206932 kb
Host smart-b4bad4b4-1283-40a3-b2d8-035bea38873c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41680
90181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.4168090181
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1129060372
Short name T208
Test name
Test status
Simulation time 7384377827 ps
CPU time 58.03 seconds
Started Jul 30 06:27:42 PM PDT 24
Finished Jul 30 06:28:40 PM PDT 24
Peak memory 216728 kb
Host smart-e8edec9d-6317-46ac-827f-3a6c291c1e9e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1129060372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1129060372
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.418155246
Short name T2078
Test name
Test status
Simulation time 7662367749 ps
CPU time 92.28 seconds
Started Jul 30 06:27:31 PM PDT 24
Finished Jul 30 06:29:03 PM PDT 24
Peak memory 207176 kb
Host smart-845161de-2e60-4b65-bec9-9132195b1e8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=418155246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.418155246
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.870247359
Short name T396
Test name
Test status
Simulation time 208866876 ps
CPU time 0.92 seconds
Started Jul 30 06:27:46 PM PDT 24
Finished Jul 30 06:27:47 PM PDT 24
Peak memory 206940 kb
Host smart-7618cddc-4f8f-4497-8c52-212309053a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87024
7359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.870247359
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.2259859764
Short name T59
Test name
Test status
Simulation time 537535943 ps
CPU time 1.6 seconds
Started Jul 30 06:27:36 PM PDT 24
Finished Jul 30 06:27:37 PM PDT 24
Peak memory 206920 kb
Host smart-691d6195-e991-4e10-a21e-f4552716cdb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22598
59764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.2259859764
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2817352278
Short name T1047
Test name
Test status
Simulation time 23269737134 ps
CPU time 28.14 seconds
Started Jul 30 06:27:37 PM PDT 24
Finished Jul 30 06:28:05 PM PDT 24
Peak memory 207116 kb
Host smart-4438a604-7f0f-4e24-991d-0597b2b36b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28173
52278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2817352278
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.4117922872
Short name T549
Test name
Test status
Simulation time 3306076296 ps
CPU time 5.14 seconds
Started Jul 30 06:27:48 PM PDT 24
Finished Jul 30 06:27:53 PM PDT 24
Peak memory 207052 kb
Host smart-9a5985d4-1713-46fc-8749-ec545a346707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41179
22872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.4117922872
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.794612345
Short name T2676
Test name
Test status
Simulation time 6601653758 ps
CPU time 46.97 seconds
Started Jul 30 06:27:47 PM PDT 24
Finished Jul 30 06:28:34 PM PDT 24
Peak memory 217144 kb
Host smart-bc82001f-687f-4ab4-b6d6-0c910bb7f8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79461
2345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.794612345
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3528979011
Short name T2303
Test name
Test status
Simulation time 4259679028 ps
CPU time 35.42 seconds
Started Jul 30 06:27:41 PM PDT 24
Finished Jul 30 06:28:17 PM PDT 24
Peak memory 207156 kb
Host smart-7156436b-c13f-4fdd-a759-713274c9e3a6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3528979011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3528979011
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.3106641438
Short name T2591
Test name
Test status
Simulation time 251754045 ps
CPU time 1.02 seconds
Started Jul 30 06:27:49 PM PDT 24
Finished Jul 30 06:27:50 PM PDT 24
Peak memory 206940 kb
Host smart-8e60654a-d4ed-43b8-9f0a-4b1357ca63a7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3106641438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3106641438
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.228084707
Short name T1370
Test name
Test status
Simulation time 193070258 ps
CPU time 0.91 seconds
Started Jul 30 06:27:47 PM PDT 24
Finished Jul 30 06:27:48 PM PDT 24
Peak memory 206876 kb
Host smart-0fb13ae3-6924-42b0-84c0-af217b277f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22808
4707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.228084707
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2935778086
Short name T643
Test name
Test status
Simulation time 5471939581 ps
CPU time 154.87 seconds
Started Jul 30 06:27:48 PM PDT 24
Finished Jul 30 06:30:23 PM PDT 24
Peak memory 215312 kb
Host smart-05f87844-92cf-4869-a60e-e83235c66acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29357
78086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2935778086
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.2571919685
Short name T2399
Test name
Test status
Simulation time 6203591650 ps
CPU time 49.6 seconds
Started Jul 30 06:27:37 PM PDT 24
Finished Jul 30 06:28:27 PM PDT 24
Peak memory 216956 kb
Host smart-7d673060-b0a6-489d-b547-e68557978295
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2571919685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.2571919685
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.3899471081
Short name T409
Test name
Test status
Simulation time 169123132 ps
CPU time 0.82 seconds
Started Jul 30 06:27:36 PM PDT 24
Finished Jul 30 06:27:37 PM PDT 24
Peak memory 206884 kb
Host smart-71495daa-b98a-4920-aee9-bad921ccc338
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3899471081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.3899471081
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2037232330
Short name T936
Test name
Test status
Simulation time 193956433 ps
CPU time 0.95 seconds
Started Jul 30 06:27:54 PM PDT 24
Finished Jul 30 06:27:55 PM PDT 24
Peak memory 206944 kb
Host smart-b32a0173-e741-4d3c-b953-41e069b133d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20372
32330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2037232330
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.4145184933
Short name T60
Test name
Test status
Simulation time 485126134 ps
CPU time 1.54 seconds
Started Jul 30 06:27:52 PM PDT 24
Finished Jul 30 06:27:53 PM PDT 24
Peak memory 206928 kb
Host smart-cf4cf990-dfc9-4b07-8a88-b4eac2b9a186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41451
84933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.4145184933
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.1196060576
Short name T2115
Test name
Test status
Simulation time 235067366 ps
CPU time 1.01 seconds
Started Jul 30 06:27:41 PM PDT 24
Finished Jul 30 06:27:42 PM PDT 24
Peak memory 206924 kb
Host smart-2f0e5564-54a9-418f-959a-c76b95059f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11960
60576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.1196060576
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2070237492
Short name T2812
Test name
Test status
Simulation time 191368805 ps
CPU time 0.96 seconds
Started Jul 30 06:27:50 PM PDT 24
Finished Jul 30 06:27:51 PM PDT 24
Peak memory 206928 kb
Host smart-7eda66ba-5efa-4eef-bbf2-e3e34264d69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20702
37492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2070237492
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2110674355
Short name T1902
Test name
Test status
Simulation time 200125699 ps
CPU time 0.87 seconds
Started Jul 30 06:27:44 PM PDT 24
Finished Jul 30 06:27:45 PM PDT 24
Peak memory 206944 kb
Host smart-96d003cf-b822-4598-bbfb-e39bc3d7d0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21106
74355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2110674355
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2860204896
Short name T1625
Test name
Test status
Simulation time 162643512 ps
CPU time 0.83 seconds
Started Jul 30 06:27:39 PM PDT 24
Finished Jul 30 06:27:40 PM PDT 24
Peak memory 206932 kb
Host smart-b8aa02ea-3d4a-4107-9bf1-e300d61a8ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28602
04896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2860204896
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.276911627
Short name T1261
Test name
Test status
Simulation time 187305130 ps
CPU time 0.91 seconds
Started Jul 30 06:27:39 PM PDT 24
Finished Jul 30 06:27:40 PM PDT 24
Peak memory 206912 kb
Host smart-cc036967-6a73-4295-9e2c-3adbf7cbaa08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27691
1627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.276911627
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.3605350997
Short name T457
Test name
Test status
Simulation time 220160971 ps
CPU time 1.03 seconds
Started Jul 30 06:27:46 PM PDT 24
Finished Jul 30 06:27:47 PM PDT 24
Peak memory 206904 kb
Host smart-f13be797-dfe8-49bd-b312-044d25978c32
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3605350997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.3605350997
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.4168458715
Short name T193
Test name
Test status
Simulation time 204596798 ps
CPU time 0.96 seconds
Started Jul 30 06:27:39 PM PDT 24
Finished Jul 30 06:27:40 PM PDT 24
Peak memory 206908 kb
Host smart-f559dc07-8b19-4fa2-bcb0-ff29e1291d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41684
58715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.4168458715
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.827671817
Short name T46
Test name
Test status
Simulation time 218063458 ps
CPU time 0.98 seconds
Started Jul 30 06:27:41 PM PDT 24
Finished Jul 30 06:27:42 PM PDT 24
Peak memory 206928 kb
Host smart-ad65ca94-1a9e-46dd-8435-9deecec243dc
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=827671817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.827671817
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2435988367
Short name T194
Test name
Test status
Simulation time 221576401 ps
CPU time 1.01 seconds
Started Jul 30 06:27:43 PM PDT 24
Finished Jul 30 06:27:45 PM PDT 24
Peak memory 206936 kb
Host smart-1aba12ed-d6ea-4fdb-a139-595917a2717a
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2435988367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.2435988367
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.298575759
Short name T2130
Test name
Test status
Simulation time 143445935 ps
CPU time 0.83 seconds
Started Jul 30 06:27:48 PM PDT 24
Finished Jul 30 06:27:49 PM PDT 24
Peak memory 206948 kb
Host smart-271c8911-0185-48cd-8301-c5ef41c7867b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29857
5759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.298575759
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3816301701
Short name T987
Test name
Test status
Simulation time 105299404 ps
CPU time 0.75 seconds
Started Jul 30 06:27:48 PM PDT 24
Finished Jul 30 06:27:49 PM PDT 24
Peak memory 206904 kb
Host smart-3008c998-faf2-4f7f-9dbb-d33fe2cc897a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38163
01701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3816301701
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3749234282
Short name T969
Test name
Test status
Simulation time 157568744 ps
CPU time 0.87 seconds
Started Jul 30 06:27:56 PM PDT 24
Finished Jul 30 06:27:57 PM PDT 24
Peak memory 206908 kb
Host smart-ddb8c635-77ec-4b00-933a-1919e469276d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37492
34282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3749234282
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1250548557
Short name T1418
Test name
Test status
Simulation time 238654761 ps
CPU time 0.96 seconds
Started Jul 30 06:27:39 PM PDT 24
Finished Jul 30 06:27:41 PM PDT 24
Peak memory 206908 kb
Host smart-3c13310c-57ad-4156-8f47-97eb706e5305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12505
48557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1250548557
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1412445296
Short name T2024
Test name
Test status
Simulation time 8591509704 ps
CPU time 227.74 seconds
Started Jul 30 06:27:54 PM PDT 24
Finished Jul 30 06:31:42 PM PDT 24
Peak memory 215380 kb
Host smart-6573e66c-3934-4d54-9881-3f0ea0526db1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1412445296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1412445296
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1587429923
Short name T914
Test name
Test status
Simulation time 17839255617 ps
CPU time 413.85 seconds
Started Jul 30 06:27:54 PM PDT 24
Finished Jul 30 06:34:48 PM PDT 24
Peak memory 215052 kb
Host smart-01100731-414d-409c-aebe-2fba6994785c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587429923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1587429923
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.2107056221
Short name T1823
Test name
Test status
Simulation time 198895627 ps
CPU time 0.91 seconds
Started Jul 30 06:27:48 PM PDT 24
Finished Jul 30 06:27:49 PM PDT 24
Peak memory 206916 kb
Host smart-17df1346-18fe-4862-9609-d14edf0f23b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21070
56221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.2107056221
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.4226184313
Short name T1375
Test name
Test status
Simulation time 189307808 ps
CPU time 0.98 seconds
Started Jul 30 06:27:46 PM PDT 24
Finished Jul 30 06:27:47 PM PDT 24
Peak memory 206928 kb
Host smart-6962a898-5800-40cf-bf5a-85721c3cbb3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42261
84313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.4226184313
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.2422819652
Short name T988
Test name
Test status
Simulation time 157386306 ps
CPU time 0.85 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:01 PM PDT 24
Peak memory 206924 kb
Host smart-c8d2c88f-b02b-42b1-affe-0f962cd0e288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24228
19652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.2422819652
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.3597108621
Short name T1141
Test name
Test status
Simulation time 248707798 ps
CPU time 1.05 seconds
Started Jul 30 06:27:46 PM PDT 24
Finished Jul 30 06:27:47 PM PDT 24
Peak memory 206912 kb
Host smart-cd4e1b3c-1bad-42f7-a26c-442baefb55ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35971
08621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.3597108621
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1289708138
Short name T2454
Test name
Test status
Simulation time 165033360 ps
CPU time 0.85 seconds
Started Jul 30 06:27:49 PM PDT 24
Finished Jul 30 06:27:50 PM PDT 24
Peak memory 206884 kb
Host smart-86072503-b20e-48e8-ae64-b750351664cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12897
08138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1289708138
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2910619585
Short name T1717
Test name
Test status
Simulation time 167694766 ps
CPU time 0.87 seconds
Started Jul 30 06:27:50 PM PDT 24
Finished Jul 30 06:27:51 PM PDT 24
Peak memory 206980 kb
Host smart-1a71fd76-254e-4fb3-8f3f-2d7956140507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29106
19585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2910619585
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.830509730
Short name T2376
Test name
Test status
Simulation time 280771219 ps
CPU time 1.17 seconds
Started Jul 30 06:27:47 PM PDT 24
Finished Jul 30 06:27:48 PM PDT 24
Peak memory 206928 kb
Host smart-6ace2b35-4777-427f-af9e-b508c6c23c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83050
9730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.830509730
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.3860420515
Short name T878
Test name
Test status
Simulation time 4482226279 ps
CPU time 132.85 seconds
Started Jul 30 06:27:46 PM PDT 24
Finished Jul 30 06:29:59 PM PDT 24
Peak memory 215360 kb
Host smart-742307ac-77fa-47b1-8f2b-7891bdeecb13
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3860420515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.3860420515
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.286768037
Short name T1514
Test name
Test status
Simulation time 181292633 ps
CPU time 0.89 seconds
Started Jul 30 06:27:45 PM PDT 24
Finished Jul 30 06:27:46 PM PDT 24
Peak memory 206928 kb
Host smart-9c3dd66c-2dde-41e8-a3ce-4f00ea67aa37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28676
8037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.286768037
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3847812624
Short name T2752
Test name
Test status
Simulation time 185162636 ps
CPU time 0.91 seconds
Started Jul 30 06:27:59 PM PDT 24
Finished Jul 30 06:28:00 PM PDT 24
Peak memory 206960 kb
Host smart-39117107-1dd3-43b5-9507-046a3b1debcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38478
12624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3847812624
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.2745236829
Short name T1475
Test name
Test status
Simulation time 1109123167 ps
CPU time 2.68 seconds
Started Jul 30 06:27:43 PM PDT 24
Finished Jul 30 06:27:46 PM PDT 24
Peak memory 207016 kb
Host smart-c8d564e8-6453-480d-afa4-10465b137941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27452
36829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.2745236829
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.1209239499
Short name T380
Test name
Test status
Simulation time 7938615926 ps
CPU time 79.79 seconds
Started Jul 30 06:27:49 PM PDT 24
Finished Jul 30 06:29:09 PM PDT 24
Peak memory 207152 kb
Host smart-ef5ca93c-cb38-4815-9626-9578ba744709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12092
39499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.1209239499
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.3439097521
Short name T2028
Test name
Test status
Simulation time 1546448923 ps
CPU time 13.11 seconds
Started Jul 30 06:27:31 PM PDT 24
Finished Jul 30 06:27:44 PM PDT 24
Peak memory 207036 kb
Host smart-af7aab5f-3ba8-4593-a58e-1023374fc2d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439097521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host
_handshake.3439097521
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.885222075
Short name T2171
Test name
Test status
Simulation time 34000537 ps
CPU time 0.68 seconds
Started Jul 30 06:28:07 PM PDT 24
Finished Jul 30 06:28:08 PM PDT 24
Peak memory 207028 kb
Host smart-32c551ba-bad8-44aa-a11d-32d87aedff8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=885222075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.885222075
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2981510106
Short name T426
Test name
Test status
Simulation time 3764021745 ps
CPU time 5.44 seconds
Started Jul 30 06:27:43 PM PDT 24
Finished Jul 30 06:27:49 PM PDT 24
Peak memory 207108 kb
Host smart-9df2b63c-b9db-4992-8675-840fa3e10304
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981510106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.2981510106
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.2926569423
Short name T1347
Test name
Test status
Simulation time 13382051708 ps
CPU time 15.92 seconds
Started Jul 30 06:27:42 PM PDT 24
Finished Jul 30 06:27:58 PM PDT 24
Peak memory 207188 kb
Host smart-f5040edb-af1d-40a7-b52b-da65978a895d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926569423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.2926569423
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1937680678
Short name T1654
Test name
Test status
Simulation time 23323807183 ps
CPU time 27.86 seconds
Started Jul 30 06:27:49 PM PDT 24
Finished Jul 30 06:28:17 PM PDT 24
Peak memory 207116 kb
Host smart-eb5d1c6b-8db5-4a6f-88fa-db12c43ea8b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937680678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.1937680678
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3117632307
Short name T1511
Test name
Test status
Simulation time 145716374 ps
CPU time 0.85 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:01 PM PDT 24
Peak memory 206976 kb
Host smart-c451acc5-41c8-4072-99bb-eacaab69cef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31176
32307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3117632307
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.378265593
Short name T1392
Test name
Test status
Simulation time 185783661 ps
CPU time 0.88 seconds
Started Jul 30 06:27:47 PM PDT 24
Finished Jul 30 06:27:48 PM PDT 24
Peak memory 206908 kb
Host smart-08e6ed9a-d63d-428d-8648-4f7d539c843b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37826
5593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.378265593
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.854531731
Short name T873
Test name
Test status
Simulation time 161808777 ps
CPU time 0.9 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:01 PM PDT 24
Peak memory 206888 kb
Host smart-348da2ef-d612-4a41-bc7c-02cb47d49613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85453
1731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.854531731
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.796971270
Short name T1330
Test name
Test status
Simulation time 280382865 ps
CPU time 1.14 seconds
Started Jul 30 06:27:49 PM PDT 24
Finished Jul 30 06:27:50 PM PDT 24
Peak memory 206908 kb
Host smart-639a1031-a0b8-4b9e-870a-6f9b4b80a736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79697
1270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.796971270
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1788840107
Short name T652
Test name
Test status
Simulation time 319993240 ps
CPU time 1.05 seconds
Started Jul 30 06:27:53 PM PDT 24
Finished Jul 30 06:27:55 PM PDT 24
Peak memory 206920 kb
Host smart-97f1db5a-489e-45f3-bb68-d17e8682f1b1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1788840107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1788840107
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2946078300
Short name T2104
Test name
Test status
Simulation time 20382679321 ps
CPU time 44.37 seconds
Started Jul 30 06:27:48 PM PDT 24
Finished Jul 30 06:28:33 PM PDT 24
Peak memory 207088 kb
Host smart-d2b1a48a-a3c8-4001-a8b0-cf285bce4796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29460
78300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2946078300
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.4012553812
Short name T391
Test name
Test status
Simulation time 4322858068 ps
CPU time 38.88 seconds
Started Jul 30 06:27:46 PM PDT 24
Finished Jul 30 06:28:25 PM PDT 24
Peak memory 207096 kb
Host smart-6692131c-b425-4029-aaec-ad889458e78f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012553812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.4012553812
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.1195681542
Short name T1815
Test name
Test status
Simulation time 472831171 ps
CPU time 1.57 seconds
Started Jul 30 06:27:47 PM PDT 24
Finished Jul 30 06:27:48 PM PDT 24
Peak memory 206928 kb
Host smart-62952425-4633-4eec-977a-d3da28bc0db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11956
81542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1195681542
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_enable.89279282
Short name T1973
Test name
Test status
Simulation time 31695874 ps
CPU time 0.77 seconds
Started Jul 30 06:28:01 PM PDT 24
Finished Jul 30 06:28:02 PM PDT 24
Peak memory 206872 kb
Host smart-3d3b579e-0dd2-4218-8c68-73330f7ed5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89279
282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.89279282
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.73644017
Short name T1322
Test name
Test status
Simulation time 827556847 ps
CPU time 2.27 seconds
Started Jul 30 06:27:50 PM PDT 24
Finished Jul 30 06:27:52 PM PDT 24
Peak memory 206992 kb
Host smart-4cd14db8-2b67-4a61-8c2d-d822fa4f1d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73644
017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.73644017
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1717554227
Short name T2403
Test name
Test status
Simulation time 407051737 ps
CPU time 2.6 seconds
Started Jul 30 06:27:49 PM PDT 24
Finished Jul 30 06:27:52 PM PDT 24
Peak memory 207032 kb
Host smart-2c0e00f4-eccb-442d-b3bb-32b04d81c793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17175
54227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1717554227
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.1410397880
Short name T1882
Test name
Test status
Simulation time 111227165724 ps
CPU time 160.88 seconds
Started Jul 30 06:27:54 PM PDT 24
Finished Jul 30 06:30:35 PM PDT 24
Peak memory 207144 kb
Host smart-8d38e9e3-e32e-42e7-a60f-1cfe04302d32
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1410397880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.1410397880
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.1420503185
Short name T934
Test name
Test status
Simulation time 87317881665 ps
CPU time 146.06 seconds
Started Jul 30 06:27:51 PM PDT 24
Finished Jul 30 06:30:17 PM PDT 24
Peak memory 207188 kb
Host smart-56724eeb-2d84-4656-baa1-14b027ee72cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420503185 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.1420503185
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.445400210
Short name T106
Test name
Test status
Simulation time 87135712752 ps
CPU time 135.79 seconds
Started Jul 30 06:27:49 PM PDT 24
Finished Jul 30 06:30:05 PM PDT 24
Peak memory 207176 kb
Host smart-08e4ebc1-e50a-4a93-b093-f03cb7616419
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=445400210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.445400210
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.3630091315
Short name T1073
Test name
Test status
Simulation time 121106713618 ps
CPU time 178.1 seconds
Started Jul 30 06:27:55 PM PDT 24
Finished Jul 30 06:30:53 PM PDT 24
Peak memory 207120 kb
Host smart-ec88bf88-04a7-43d4-b9df-f056323343c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36300
91315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.3630091315
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2166745831
Short name T1538
Test name
Test status
Simulation time 153978227 ps
CPU time 0.94 seconds
Started Jul 30 06:27:58 PM PDT 24
Finished Jul 30 06:27:59 PM PDT 24
Peak memory 206940 kb
Host smart-03959835-3d42-484f-b527-4fdd662adbdb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2166745831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2166745831
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.4005008032
Short name T1901
Test name
Test status
Simulation time 182207737 ps
CPU time 0.91 seconds
Started Jul 30 06:27:48 PM PDT 24
Finished Jul 30 06:27:49 PM PDT 24
Peak memory 206892 kb
Host smart-6d6e8d23-f770-4169-96ce-65bd9c7ca050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40050
08032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.4005008032
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.121427135
Short name T1462
Test name
Test status
Simulation time 233598372 ps
CPU time 0.99 seconds
Started Jul 30 06:27:52 PM PDT 24
Finished Jul 30 06:27:53 PM PDT 24
Peak memory 206980 kb
Host smart-a8491c35-eede-42e0-8fd8-658287b8c83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12142
7135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.121427135
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.2551005993
Short name T1401
Test name
Test status
Simulation time 5869629784 ps
CPU time 58.2 seconds
Started Jul 30 06:27:55 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 216592 kb
Host smart-13056e07-51d8-4326-b5ea-7b580008b4ff
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2551005993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2551005993
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.3132971195
Short name T1693
Test name
Test status
Simulation time 13734654163 ps
CPU time 105.25 seconds
Started Jul 30 06:27:53 PM PDT 24
Finished Jul 30 06:29:38 PM PDT 24
Peak memory 207156 kb
Host smart-32bda1e6-f0bc-40ad-8285-bc7c9bce8d77
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3132971195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.3132971195
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.1681297036
Short name T862
Test name
Test status
Simulation time 258575390 ps
CPU time 1.17 seconds
Started Jul 30 06:27:52 PM PDT 24
Finished Jul 30 06:27:53 PM PDT 24
Peak memory 206908 kb
Host smart-35b7ace3-9787-40b5-b09e-46bd666573c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16812
97036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1681297036
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.3533247506
Short name T1400
Test name
Test status
Simulation time 23319028001 ps
CPU time 32.04 seconds
Started Jul 30 06:27:52 PM PDT 24
Finished Jul 30 06:28:24 PM PDT 24
Peak memory 207112 kb
Host smart-f49a23d9-2ca6-4c2e-8eea-d48ff395955b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35332
47506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.3533247506
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1784516693
Short name T867
Test name
Test status
Simulation time 3315029275 ps
CPU time 4.9 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:05 PM PDT 24
Peak memory 207088 kb
Host smart-df83057c-6237-4b53-94db-18b50fdec6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17845
16693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1784516693
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2292667504
Short name T2052
Test name
Test status
Simulation time 9114920886 ps
CPU time 66.04 seconds
Started Jul 30 06:27:58 PM PDT 24
Finished Jul 30 06:29:05 PM PDT 24
Peak memory 223528 kb
Host smart-5fe99ae9-e20e-4aa3-90a8-e68ce203f9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22926
67504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2292667504
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1035566610
Short name T1782
Test name
Test status
Simulation time 6193260254 ps
CPU time 177.83 seconds
Started Jul 30 06:27:58 PM PDT 24
Finished Jul 30 06:30:56 PM PDT 24
Peak memory 215300 kb
Host smart-7f281af0-f8d4-46dd-9d57-cbee3f0f7cdf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1035566610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1035566610
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.3100674271
Short name T2864
Test name
Test status
Simulation time 237998116 ps
CPU time 1.02 seconds
Started Jul 30 06:27:52 PM PDT 24
Finished Jul 30 06:27:53 PM PDT 24
Peak memory 206976 kb
Host smart-9a09be27-0c2d-4971-ab08-ff44de4b5d03
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3100674271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3100674271
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2909615799
Short name T586
Test name
Test status
Simulation time 204964656 ps
CPU time 1 seconds
Started Jul 30 06:27:52 PM PDT 24
Finished Jul 30 06:27:53 PM PDT 24
Peak memory 206908 kb
Host smart-8541fb2b-51cf-4fa9-b074-4741ca0330e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29096
15799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2909615799
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.1117443084
Short name T1386
Test name
Test status
Simulation time 3969158715 ps
CPU time 114.71 seconds
Started Jul 30 06:27:54 PM PDT 24
Finished Jul 30 06:29:48 PM PDT 24
Peak memory 215328 kb
Host smart-2a5ff2bf-5cf7-4df9-857c-2bf4e59a8bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11174
43084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.1117443084
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3844028132
Short name T1725
Test name
Test status
Simulation time 3615527581 ps
CPU time 107.04 seconds
Started Jul 30 06:27:59 PM PDT 24
Finished Jul 30 06:29:46 PM PDT 24
Peak memory 215312 kb
Host smart-680d0de0-5546-4dee-a6b2-664a34859be3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3844028132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3844028132
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2201858024
Short name T2845
Test name
Test status
Simulation time 151075333 ps
CPU time 0.88 seconds
Started Jul 30 06:27:59 PM PDT 24
Finished Jul 30 06:28:00 PM PDT 24
Peak memory 206928 kb
Host smart-82916f23-4702-49db-9f65-c3802afaa334
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2201858024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2201858024
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.142081355
Short name T1713
Test name
Test status
Simulation time 154329328 ps
CPU time 0.85 seconds
Started Jul 30 06:27:56 PM PDT 24
Finished Jul 30 06:27:57 PM PDT 24
Peak memory 206912 kb
Host smart-a0201f6b-b684-49ee-8bdc-ce4c44adc227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14208
1355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.142081355
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1367370904
Short name T410
Test name
Test status
Simulation time 242635875 ps
CPU time 1.05 seconds
Started Jul 30 06:28:02 PM PDT 24
Finished Jul 30 06:28:04 PM PDT 24
Peak memory 206904 kb
Host smart-c9ab8299-d21b-4f6b-9bc6-bb2fd271c074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13673
70904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1367370904
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2472697200
Short name T507
Test name
Test status
Simulation time 199919249 ps
CPU time 0.96 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:02 PM PDT 24
Peak memory 206948 kb
Host smart-5b095ec0-b0e8-476f-87dd-e4b2a1d343d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24726
97200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2472697200
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1234686610
Short name T726
Test name
Test status
Simulation time 149680863 ps
CPU time 0.85 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:01 PM PDT 24
Peak memory 206928 kb
Host smart-96a8df4f-30c2-48f5-8434-702d7f6f9d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12346
86610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1234686610
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3015891345
Short name T2316
Test name
Test status
Simulation time 171859991 ps
CPU time 0.91 seconds
Started Jul 30 06:27:57 PM PDT 24
Finished Jul 30 06:27:58 PM PDT 24
Peak memory 206916 kb
Host smart-76def57b-0385-43e1-ad0a-8e865676e289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30158
91345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3015891345
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.825028077
Short name T1503
Test name
Test status
Simulation time 224088792 ps
CPU time 1.03 seconds
Started Jul 30 06:27:57 PM PDT 24
Finished Jul 30 06:27:58 PM PDT 24
Peak memory 206956 kb
Host smart-17947922-e0b6-407a-ac1a-a045906bb786
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=825028077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.825028077
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3793230952
Short name T2764
Test name
Test status
Simulation time 220943475 ps
CPU time 1 seconds
Started Jul 30 06:27:59 PM PDT 24
Finished Jul 30 06:28:01 PM PDT 24
Peak memory 206908 kb
Host smart-e01facd5-b1f1-40d2-aa07-4b8a9c67e26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37932
30952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3793230952
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.4263059047
Short name T1994
Test name
Test status
Simulation time 179852480 ps
CPU time 0.9 seconds
Started Jul 30 06:27:59 PM PDT 24
Finished Jul 30 06:28:00 PM PDT 24
Peak memory 206952 kb
Host smart-7a36fb52-4644-4091-88d9-24f87739f02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42630
59047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.4263059047
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3221390403
Short name T33
Test name
Test status
Simulation time 29798022 ps
CPU time 0.7 seconds
Started Jul 30 06:27:59 PM PDT 24
Finished Jul 30 06:28:00 PM PDT 24
Peak memory 206848 kb
Host smart-618c2bff-7f2d-43ea-8000-1f29a56345c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32213
90403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3221390403
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1136766003
Short name T1828
Test name
Test status
Simulation time 12829287006 ps
CPU time 36.17 seconds
Started Jul 30 06:27:59 PM PDT 24
Finished Jul 30 06:28:35 PM PDT 24
Peak memory 215416 kb
Host smart-4b9622fe-2255-48f9-b615-cb09893f6751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11367
66003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1136766003
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2244487245
Short name T2111
Test name
Test status
Simulation time 159947487 ps
CPU time 0.95 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:01 PM PDT 24
Peak memory 206720 kb
Host smart-c10e53d3-2fe0-4fd0-81e0-91790bb997cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22444
87245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2244487245
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1904621913
Short name T2371
Test name
Test status
Simulation time 267101712 ps
CPU time 0.99 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:01 PM PDT 24
Peak memory 206920 kb
Host smart-1521b0c8-7e97-446b-882f-5744abec3d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19046
21913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1904621913
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2752729376
Short name T168
Test name
Test status
Simulation time 9570175634 ps
CPU time 64.35 seconds
Started Jul 30 06:28:08 PM PDT 24
Finished Jul 30 06:29:12 PM PDT 24
Peak memory 218320 kb
Host smart-e810cdd6-d2f2-43f7-84b0-f89028248b30
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752729376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2752729376
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.139287800
Short name T2257
Test name
Test status
Simulation time 8320208164 ps
CPU time 138.31 seconds
Started Jul 30 06:28:01 PM PDT 24
Finished Jul 30 06:30:19 PM PDT 24
Peak memory 215336 kb
Host smart-ac31f756-d9d7-40bf-a9bf-20d8e385e940
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=139287800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.139287800
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.1783337812
Short name T557
Test name
Test status
Simulation time 8673790158 ps
CPU time 141.45 seconds
Started Jul 30 06:28:01 PM PDT 24
Finished Jul 30 06:30:22 PM PDT 24
Peak memory 215360 kb
Host smart-b67fa725-3276-4cdb-bc68-075494002ecd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783337812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.1783337812
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.1654489454
Short name T1674
Test name
Test status
Simulation time 162126432 ps
CPU time 0.89 seconds
Started Jul 30 06:28:08 PM PDT 24
Finished Jul 30 06:28:09 PM PDT 24
Peak memory 206912 kb
Host smart-06a09b95-837c-458a-b930-0cdaf8dee71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16544
89454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.1654489454
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.761118607
Short name T2360
Test name
Test status
Simulation time 172501779 ps
CPU time 0.88 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:01 PM PDT 24
Peak memory 206920 kb
Host smart-d79ff31c-227a-4969-a979-44aa935141a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76111
8607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.761118607
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.2834594485
Short name T2230
Test name
Test status
Simulation time 150795649 ps
CPU time 0.86 seconds
Started Jul 30 06:28:01 PM PDT 24
Finished Jul 30 06:28:02 PM PDT 24
Peak memory 206872 kb
Host smart-5f98c3eb-f3b9-4b4b-acce-0a97efc6b197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28345
94485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2834594485
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.1293317372
Short name T70
Test name
Test status
Simulation time 159046924 ps
CPU time 0.86 seconds
Started Jul 30 06:28:04 PM PDT 24
Finished Jul 30 06:28:05 PM PDT 24
Peak memory 206976 kb
Host smart-3ba0d338-8b20-4bf0-81f1-27abd8584483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12933
17372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.1293317372
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3844875740
Short name T184
Test name
Test status
Simulation time 263027513 ps
CPU time 1.11 seconds
Started Jul 30 06:28:12 PM PDT 24
Finished Jul 30 06:28:13 PM PDT 24
Peak memory 222956 kb
Host smart-bb69bf47-3d48-4d57-b5bf-fb5687369dd9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3844875740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3844875740
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.934044082
Short name T2418
Test name
Test status
Simulation time 427642714 ps
CPU time 1.63 seconds
Started Jul 30 06:28:03 PM PDT 24
Finished Jul 30 06:28:05 PM PDT 24
Peak memory 206932 kb
Host smart-cd43428f-940f-4b1d-b874-ce67283c5556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93404
4082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.934044082
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.807821635
Short name T1512
Test name
Test status
Simulation time 169737649 ps
CPU time 0.97 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:01 PM PDT 24
Peak memory 206736 kb
Host smart-18ec2a33-bf10-4e20-9d0d-93c61b6c830d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80782
1635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.807821635
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2226905240
Short name T2843
Test name
Test status
Simulation time 148372475 ps
CPU time 0.89 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:01 PM PDT 24
Peak memory 206888 kb
Host smart-e4b49f7d-9d21-4014-ad28-32f5ac61f564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22269
05240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2226905240
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2437671845
Short name T2138
Test name
Test status
Simulation time 148766376 ps
CPU time 0.84 seconds
Started Jul 30 06:28:03 PM PDT 24
Finished Jul 30 06:28:04 PM PDT 24
Peak memory 206980 kb
Host smart-8ef47a8d-5d55-47dd-8df3-3c5db3d9c7b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24376
71845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2437671845
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3048967844
Short name T2227
Test name
Test status
Simulation time 203887299 ps
CPU time 1 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:01 PM PDT 24
Peak memory 206912 kb
Host smart-20cfaa2f-0f03-4da4-87e7-f7dac41ae4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30489
67844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3048967844
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.1032990963
Short name T522
Test name
Test status
Simulation time 5932003082 ps
CPU time 43.97 seconds
Started Jul 30 06:28:02 PM PDT 24
Finished Jul 30 06:28:46 PM PDT 24
Peak memory 216756 kb
Host smart-663c7974-4915-4919-8d57-ac99c0c10fcb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1032990963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.1032990963
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.932101214
Short name T908
Test name
Test status
Simulation time 171892239 ps
CPU time 0.94 seconds
Started Jul 30 06:28:02 PM PDT 24
Finished Jul 30 06:28:03 PM PDT 24
Peak memory 206920 kb
Host smart-3780bb4c-7d23-4e77-8032-a7ddaecf4b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93210
1214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.932101214
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3484434955
Short name T499
Test name
Test status
Simulation time 183195124 ps
CPU time 0.94 seconds
Started Jul 30 06:28:04 PM PDT 24
Finished Jul 30 06:28:05 PM PDT 24
Peak memory 206980 kb
Host smart-9ad89b47-7630-4221-a900-933e755c8fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34844
34955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3484434955
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.1719321817
Short name T2223
Test name
Test status
Simulation time 627866384 ps
CPU time 1.93 seconds
Started Jul 30 06:28:00 PM PDT 24
Finished Jul 30 06:28:02 PM PDT 24
Peak memory 206888 kb
Host smart-f9a473b0-398a-4fde-8253-14f47ccebd48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17193
21817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.1719321817
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2080925734
Short name T910
Test name
Test status
Simulation time 4089482055 ps
CPU time 40.08 seconds
Started Jul 30 06:28:07 PM PDT 24
Finished Jul 30 06:28:48 PM PDT 24
Peak memory 216864 kb
Host smart-b4c18d4f-947d-4ee1-ba3f-d9a8e03744d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20809
25734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2080925734
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.1316401968
Short name T663
Test name
Test status
Simulation time 583861620 ps
CPU time 4.92 seconds
Started Jul 30 06:28:07 PM PDT 24
Finished Jul 30 06:28:13 PM PDT 24
Peak memory 207032 kb
Host smart-1bb882b1-ef94-4975-958f-51caa9c2be29
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316401968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.1316401968
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.181890787
Short name T2002
Test name
Test status
Simulation time 4005530818 ps
CPU time 5.32 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:29:35 PM PDT 24
Peak memory 207080 kb
Host smart-a2ed4aa6-8d10-42ef-85cb-93caa39ed71f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181890787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_ao
n_wake_disconnect.181890787
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1829012646
Short name T1858
Test name
Test status
Simulation time 13325151270 ps
CPU time 16.17 seconds
Started Jul 30 06:29:24 PM PDT 24
Finished Jul 30 06:29:40 PM PDT 24
Peak memory 207124 kb
Host smart-3c2a3406-7f89-4b38-a61b-7ff679475b11
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829012646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1829012646
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.2911171015
Short name T1090
Test name
Test status
Simulation time 23351876573 ps
CPU time 27.66 seconds
Started Jul 30 06:29:22 PM PDT 24
Finished Jul 30 06:29:50 PM PDT 24
Peak memory 207188 kb
Host smart-8b926302-992d-4236-8863-112b7bb2a80a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911171015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.2911171015
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2615516072
Short name T389
Test name
Test status
Simulation time 178641258 ps
CPU time 0.92 seconds
Started Jul 30 06:29:22 PM PDT 24
Finished Jul 30 06:29:23 PM PDT 24
Peak memory 206928 kb
Host smart-f86033cf-0191-4bf2-ac84-9f2217138742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26155
16072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2615516072
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.30866312
Short name T2562
Test name
Test status
Simulation time 178544765 ps
CPU time 0.85 seconds
Started Jul 30 06:29:24 PM PDT 24
Finished Jul 30 06:29:25 PM PDT 24
Peak memory 206844 kb
Host smart-416687e5-75b6-47ec-ba96-17dfbe14baf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30866
312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.30866312
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.389883547
Short name T579
Test name
Test status
Simulation time 469699202 ps
CPU time 1.64 seconds
Started Jul 30 06:29:21 PM PDT 24
Finished Jul 30 06:29:23 PM PDT 24
Peak memory 206916 kb
Host smart-604e76b9-35b0-4dc8-9322-cf5141549984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38988
3547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.389883547
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.423839546
Short name T1709
Test name
Test status
Simulation time 1266986891 ps
CPU time 3.43 seconds
Started Jul 30 06:29:21 PM PDT 24
Finished Jul 30 06:29:25 PM PDT 24
Peak memory 207056 kb
Host smart-17d6dbd3-e6bc-4472-9e4a-4f7b21552cd9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=423839546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.423839546
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.2183320092
Short name T2071
Test name
Test status
Simulation time 7190028250 ps
CPU time 14.83 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:29:44 PM PDT 24
Peak memory 207180 kb
Host smart-9a8df431-f495-4396-9b70-34b517087afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21833
20092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.2183320092
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.3278787697
Short name T790
Test name
Test status
Simulation time 854494357 ps
CPU time 5.75 seconds
Started Jul 30 06:29:23 PM PDT 24
Finished Jul 30 06:29:29 PM PDT 24
Peak memory 206992 kb
Host smart-642e2645-824d-4190-9a5e-566562e75dc4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278787697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.3278787697
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.452369911
Short name T888
Test name
Test status
Simulation time 451644396 ps
CPU time 1.46 seconds
Started Jul 30 06:29:25 PM PDT 24
Finished Jul 30 06:29:27 PM PDT 24
Peak memory 206908 kb
Host smart-31250b03-fd3c-443c-ae07-4a4ac6a7c2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45236
9911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.452369911
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.586837224
Short name T2248
Test name
Test status
Simulation time 140505307 ps
CPU time 0.87 seconds
Started Jul 30 06:29:24 PM PDT 24
Finished Jul 30 06:29:25 PM PDT 24
Peak memory 206884 kb
Host smart-4adf523c-806d-46c9-82b6-a669843c68dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58683
7224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.586837224
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.2383394933
Short name T1472
Test name
Test status
Simulation time 62879873 ps
CPU time 0.74 seconds
Started Jul 30 06:29:27 PM PDT 24
Finished Jul 30 06:29:28 PM PDT 24
Peak memory 206952 kb
Host smart-465687bd-5287-433a-a461-1e28966ccdcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23833
94933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2383394933
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2795261517
Short name T413
Test name
Test status
Simulation time 960342576 ps
CPU time 2.86 seconds
Started Jul 30 06:29:26 PM PDT 24
Finished Jul 30 06:29:29 PM PDT 24
Peak memory 207056 kb
Host smart-4fa094e2-2c99-44f1-892e-5f798ef77454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27952
61517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2795261517
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.103506765
Short name T2745
Test name
Test status
Simulation time 188917993 ps
CPU time 1.44 seconds
Started Jul 30 06:29:26 PM PDT 24
Finished Jul 30 06:29:28 PM PDT 24
Peak memory 207044 kb
Host smart-5747dbee-4a50-464e-9838-90375ef7bb83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10350
6765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.103506765
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3282827081
Short name T85
Test name
Test status
Simulation time 217497520 ps
CPU time 1.2 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:29:31 PM PDT 24
Peak memory 207024 kb
Host smart-3d674868-b384-41e0-9cde-e99c5637d223
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3282827081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3282827081
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3822915191
Short name T2836
Test name
Test status
Simulation time 159794713 ps
CPU time 0.86 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:29:30 PM PDT 24
Peak memory 206912 kb
Host smart-f8e5aa1c-2c4e-4576-81cf-d79ed4d90e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38229
15191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3822915191
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.431446246
Short name T1030
Test name
Test status
Simulation time 203657927 ps
CPU time 0.94 seconds
Started Jul 30 06:29:25 PM PDT 24
Finished Jul 30 06:29:26 PM PDT 24
Peak memory 206920 kb
Host smart-94a29c0f-51c1-43f5-8b4c-1d8541d371c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43144
6246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.431446246
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.3534707371
Short name T1178
Test name
Test status
Simulation time 11445686911 ps
CPU time 114.35 seconds
Started Jul 30 06:29:31 PM PDT 24
Finished Jul 30 06:31:26 PM PDT 24
Peak memory 207152 kb
Host smart-80fc4ac9-e4b4-4113-9431-a7c146d1024a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3534707371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.3534707371
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.2782939931
Short name T611
Test name
Test status
Simulation time 4802234310 ps
CPU time 33.36 seconds
Started Jul 30 06:29:28 PM PDT 24
Finished Jul 30 06:30:02 PM PDT 24
Peak memory 207108 kb
Host smart-736f0916-8540-495f-8e19-268d8c7d5c13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2782939931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.2782939931
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3191757030
Short name T685
Test name
Test status
Simulation time 248644893 ps
CPU time 0.98 seconds
Started Jul 30 06:29:27 PM PDT 24
Finished Jul 30 06:29:28 PM PDT 24
Peak memory 206988 kb
Host smart-6ff3418c-864d-43a8-9c56-748db248969f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31917
57030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3191757030
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.1396369025
Short name T2419
Test name
Test status
Simulation time 23430934563 ps
CPU time 28.67 seconds
Started Jul 30 06:29:26 PM PDT 24
Finished Jul 30 06:29:55 PM PDT 24
Peak memory 207072 kb
Host smart-bd347127-6c02-4f5d-8324-386175897b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13963
69025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.1396369025
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.2312442159
Short name T246
Test name
Test status
Simulation time 3296645051 ps
CPU time 5.11 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:29:35 PM PDT 24
Peak memory 207076 kb
Host smart-a04ed4d1-005b-49c1-8476-ef9dc744c74e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23124
42159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.2312442159
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2623990062
Short name T1899
Test name
Test status
Simulation time 6587415204 ps
CPU time 179.79 seconds
Started Jul 30 06:29:26 PM PDT 24
Finished Jul 30 06:32:26 PM PDT 24
Peak memory 215308 kb
Host smart-348166e5-74f4-476a-915f-0e7dbc7bac0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26239
90062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2623990062
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.912051902
Short name T2834
Test name
Test status
Simulation time 4701492887 ps
CPU time 139.11 seconds
Started Jul 30 06:29:28 PM PDT 24
Finished Jul 30 06:31:47 PM PDT 24
Peak memory 215372 kb
Host smart-5c96c993-b7a2-420f-af12-97a1ddeea99f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=912051902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.912051902
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.106118498
Short name T1923
Test name
Test status
Simulation time 254447957 ps
CPU time 0.97 seconds
Started Jul 30 06:29:25 PM PDT 24
Finished Jul 30 06:29:26 PM PDT 24
Peak memory 206944 kb
Host smart-eb71d2d4-413b-47ed-ab05-1b496d2c1995
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=106118498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.106118498
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.660774486
Short name T711
Test name
Test status
Simulation time 198545419 ps
CPU time 0.94 seconds
Started Jul 30 06:29:26 PM PDT 24
Finished Jul 30 06:29:27 PM PDT 24
Peak memory 206844 kb
Host smart-2eb1aa87-a7ac-4403-8cd4-767520dd781d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66077
4486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.660774486
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1755751744
Short name T2647
Test name
Test status
Simulation time 5132029902 ps
CPU time 53.19 seconds
Started Jul 30 06:29:26 PM PDT 24
Finished Jul 30 06:30:24 PM PDT 24
Peak memory 215304 kb
Host smart-92fb1b99-7b6f-4ecb-aee6-52fa4db55c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17557
51744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1755751744
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1550066643
Short name T2761
Test name
Test status
Simulation time 3148915101 ps
CPU time 29.99 seconds
Started Jul 30 06:29:26 PM PDT 24
Finished Jul 30 06:29:56 PM PDT 24
Peak memory 215348 kb
Host smart-f93fdbf8-9347-4e69-a5f0-9b91f5185e37
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1550066643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1550066643
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.892079880
Short name T2450
Test name
Test status
Simulation time 160783516 ps
CPU time 0.86 seconds
Started Jul 30 06:29:28 PM PDT 24
Finished Jul 30 06:29:29 PM PDT 24
Peak memory 206936 kb
Host smart-6ba7e994-aeb5-4052-b566-18ea94a07448
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=892079880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.892079880
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2343301392
Short name T857
Test name
Test status
Simulation time 159359277 ps
CPU time 0.86 seconds
Started Jul 30 06:29:25 PM PDT 24
Finished Jul 30 06:29:26 PM PDT 24
Peak memory 206924 kb
Host smart-fcdaf1cb-8a20-41b8-9df1-aef106841847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23433
01392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2343301392
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.3046127271
Short name T544
Test name
Test status
Simulation time 189128265 ps
CPU time 0.89 seconds
Started Jul 30 06:29:26 PM PDT 24
Finished Jul 30 06:29:28 PM PDT 24
Peak memory 206880 kb
Host smart-7ad52912-5ee8-4fa6-93f3-547d02935e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30461
27271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.3046127271
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3298525562
Short name T1811
Test name
Test status
Simulation time 191740182 ps
CPU time 0.89 seconds
Started Jul 30 06:29:24 PM PDT 24
Finished Jul 30 06:29:25 PM PDT 24
Peak memory 206972 kb
Host smart-c735b68a-6cb7-4dee-990b-bdb17952a9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32985
25562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3298525562
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1478447174
Short name T1027
Test name
Test status
Simulation time 249098114 ps
CPU time 0.96 seconds
Started Jul 30 06:29:26 PM PDT 24
Finished Jul 30 06:29:27 PM PDT 24
Peak memory 206832 kb
Host smart-ae1033fd-3599-4692-bcc3-0eeda5d8b18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14784
47174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1478447174
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.2768327480
Short name T2668
Test name
Test status
Simulation time 164643001 ps
CPU time 0.94 seconds
Started Jul 30 06:29:26 PM PDT 24
Finished Jul 30 06:29:27 PM PDT 24
Peak memory 206976 kb
Host smart-486f093a-9f60-4fbb-96f7-cbf1467b7406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27683
27480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.2768327480
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.3722831272
Short name T633
Test name
Test status
Simulation time 207835484 ps
CPU time 0.98 seconds
Started Jul 30 06:29:26 PM PDT 24
Finished Jul 30 06:29:27 PM PDT 24
Peak memory 206920 kb
Host smart-066b6e3d-3bcc-42cf-bc23-0f42eff87600
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3722831272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.3722831272
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.4226247329
Short name T1064
Test name
Test status
Simulation time 147598682 ps
CPU time 0.88 seconds
Started Jul 30 06:29:25 PM PDT 24
Finished Jul 30 06:29:26 PM PDT 24
Peak memory 206888 kb
Host smart-35582782-963f-4e81-9d58-3788499c0ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42262
47329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.4226247329
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3530339447
Short name T26
Test name
Test status
Simulation time 36602074 ps
CPU time 0.72 seconds
Started Jul 30 06:29:27 PM PDT 24
Finished Jul 30 06:29:28 PM PDT 24
Peak memory 206952 kb
Host smart-4f10a285-6006-4d23-9acd-f058f039f2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35303
39447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3530339447
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1414562493
Short name T2741
Test name
Test status
Simulation time 21988861408 ps
CPU time 53.15 seconds
Started Jul 30 06:29:26 PM PDT 24
Finished Jul 30 06:30:19 PM PDT 24
Peak memory 215408 kb
Host smart-5b297396-adb9-4300-95a9-3e4539f0c8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14145
62493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1414562493
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3106733013
Short name T1320
Test name
Test status
Simulation time 200056137 ps
CPU time 0.95 seconds
Started Jul 30 06:29:47 PM PDT 24
Finished Jul 30 06:29:48 PM PDT 24
Peak memory 206944 kb
Host smart-dfd58cba-2ad1-42e2-9840-d9e2d090120e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31067
33013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3106733013
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1979059529
Short name T2389
Test name
Test status
Simulation time 216069541 ps
CPU time 0.92 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:29:30 PM PDT 24
Peak memory 206912 kb
Host smart-f0a2384c-7fc4-412d-ba11-648dbdc85272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19790
59529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1979059529
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.389368859
Short name T2415
Test name
Test status
Simulation time 234623626 ps
CPU time 1.01 seconds
Started Jul 30 06:29:34 PM PDT 24
Finished Jul 30 06:29:35 PM PDT 24
Peak memory 206888 kb
Host smart-756adf8e-852d-4565-8b24-69b34ec850e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38936
8859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.389368859
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.4139648566
Short name T478
Test name
Test status
Simulation time 160184137 ps
CPU time 0.85 seconds
Started Jul 30 06:29:48 PM PDT 24
Finished Jul 30 06:29:49 PM PDT 24
Peak memory 206912 kb
Host smart-4b27f577-a45b-42e1-ba23-72b2b0d11098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41396
48566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.4139648566
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3550988825
Short name T1932
Test name
Test status
Simulation time 170625348 ps
CPU time 0.84 seconds
Started Jul 30 06:29:30 PM PDT 24
Finished Jul 30 06:29:31 PM PDT 24
Peak memory 206884 kb
Host smart-f1ba4878-fe65-43a9-9ae9-cc8a9e23744e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35509
88825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3550988825
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3710828679
Short name T655
Test name
Test status
Simulation time 167259335 ps
CPU time 0.83 seconds
Started Jul 30 06:29:38 PM PDT 24
Finished Jul 30 06:29:39 PM PDT 24
Peak memory 206876 kb
Host smart-3d352f6e-1e92-44aa-aa7a-5c64aae8b8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37108
28679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3710828679
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_smoke.406829677
Short name T450
Test name
Test status
Simulation time 276652721 ps
CPU time 1.04 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:29:30 PM PDT 24
Peak memory 206924 kb
Host smart-0a7140be-c4f5-40ba-9f32-f7cbdd8e5aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40682
9677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.406829677
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.3382935825
Short name T174
Test name
Test status
Simulation time 5236357150 ps
CPU time 154.46 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:32:04 PM PDT 24
Peak memory 215304 kb
Host smart-94d82d5b-d485-46d1-b418-d44835bba4f5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3382935825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.3382935825
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3136823657
Short name T2671
Test name
Test status
Simulation time 187911905 ps
CPU time 0.91 seconds
Started Jul 30 06:29:40 PM PDT 24
Finished Jul 30 06:29:41 PM PDT 24
Peak memory 206940 kb
Host smart-8dcfe6a1-6f10-4bdf-933f-22257e3a1cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31368
23657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3136823657
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3717880147
Short name T2704
Test name
Test status
Simulation time 207709638 ps
CPU time 0.88 seconds
Started Jul 30 06:29:30 PM PDT 24
Finished Jul 30 06:29:31 PM PDT 24
Peak memory 206928 kb
Host smart-d6f0971f-fa6d-4e0e-aecb-1cceaa7d290d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37178
80147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3717880147
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.3048199078
Short name T395
Test name
Test status
Simulation time 942316066 ps
CPU time 2.61 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:29:32 PM PDT 24
Peak memory 207076 kb
Host smart-4ee39c81-09d1-458a-8f15-d0d8e36130fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30481
99078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.3048199078
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.1433546612
Short name T2451
Test name
Test status
Simulation time 4898156002 ps
CPU time 37.16 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:30:06 PM PDT 24
Peak memory 216820 kb
Host smart-b92a15af-4395-444c-a058-db601851b62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14335
46612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1433546612
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.1411075935
Short name T1074
Test name
Test status
Simulation time 3441713016 ps
CPU time 30.35 seconds
Started Jul 30 06:29:20 PM PDT 24
Finished Jul 30 06:29:50 PM PDT 24
Peak memory 207120 kb
Host smart-3ba6920b-0a0e-4f9b-b94f-4b5aaba9259f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411075935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.1411075935
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.1881250108
Short name T1806
Test name
Test status
Simulation time 51807733 ps
CPU time 0.7 seconds
Started Jul 30 06:29:37 PM PDT 24
Finished Jul 30 06:29:38 PM PDT 24
Peak memory 207016 kb
Host smart-8bb445a7-4ba7-4eab-87f6-658a05013388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1881250108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.1881250108
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3710466758
Short name T1092
Test name
Test status
Simulation time 4366720559 ps
CPU time 6.22 seconds
Started Jul 30 06:29:31 PM PDT 24
Finished Jul 30 06:29:37 PM PDT 24
Peak memory 207084 kb
Host smart-b94dd9a2-98b7-460e-8758-19a54a127041
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710466758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.3710466758
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2349146104
Short name T777
Test name
Test status
Simulation time 13439616924 ps
CPU time 16.71 seconds
Started Jul 30 06:29:49 PM PDT 24
Finished Jul 30 06:30:06 PM PDT 24
Peak memory 207120 kb
Host smart-12436f11-f8d4-49b7-a0c4-0e23830c9d07
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349146104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2349146104
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3236469470
Short name T770
Test name
Test status
Simulation time 23417217197 ps
CPU time 28.18 seconds
Started Jul 30 06:29:32 PM PDT 24
Finished Jul 30 06:30:00 PM PDT 24
Peak memory 207116 kb
Host smart-aa4cb548-385e-4d3b-8f90-06dc07178630
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236469470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.3236469470
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.294087347
Short name T2264
Test name
Test status
Simulation time 196991925 ps
CPU time 0.87 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:29:30 PM PDT 24
Peak memory 206920 kb
Host smart-288a5b25-49e7-43ed-abe6-461bcae3da74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29408
7347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.294087347
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.3335754424
Short name T885
Test name
Test status
Simulation time 195630676 ps
CPU time 0.93 seconds
Started Jul 30 06:29:30 PM PDT 24
Finished Jul 30 06:29:31 PM PDT 24
Peak memory 206948 kb
Host smart-5311f6eb-64a7-4fe7-acb6-5c645219d1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33357
54424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.3335754424
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.3261098515
Short name T1931
Test name
Test status
Simulation time 600532621 ps
CPU time 1.76 seconds
Started Jul 30 06:29:41 PM PDT 24
Finished Jul 30 06:29:43 PM PDT 24
Peak memory 206944 kb
Host smart-47230383-e0c0-4b72-ba69-08f7160434a1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3261098515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.3261098515
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.2122261792
Short name T2855
Test name
Test status
Simulation time 14178074899 ps
CPU time 33.21 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:30:03 PM PDT 24
Peak memory 207104 kb
Host smart-f1ae3b4b-e947-4da6-b6b0-9f9c91820e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21222
61792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2122261792
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.1065157832
Short name T1100
Test name
Test status
Simulation time 9777749492 ps
CPU time 66.39 seconds
Started Jul 30 06:29:32 PM PDT 24
Finished Jul 30 06:30:38 PM PDT 24
Peak memory 207216 kb
Host smart-41416d5a-4d6c-4df9-ad42-55170912a8c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065157832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.1065157832
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.479553352
Short name T2615
Test name
Test status
Simulation time 474648290 ps
CPU time 1.42 seconds
Started Jul 30 06:29:30 PM PDT 24
Finished Jul 30 06:29:32 PM PDT 24
Peak memory 206876 kb
Host smart-09d4887f-a04b-4b72-a899-38730af3fa1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47955
3352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.479553352
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1944220160
Short name T1431
Test name
Test status
Simulation time 147398266 ps
CPU time 0.82 seconds
Started Jul 30 06:29:34 PM PDT 24
Finished Jul 30 06:29:35 PM PDT 24
Peak memory 206892 kb
Host smart-a3482de1-780b-44a5-83d3-98ced7e4ef9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19442
20160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1944220160
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3211864331
Short name T1219
Test name
Test status
Simulation time 60206013 ps
CPU time 0.73 seconds
Started Jul 30 06:29:33 PM PDT 24
Finished Jul 30 06:29:34 PM PDT 24
Peak memory 206904 kb
Host smart-b2ceb09e-004b-4155-aa3f-4bc0bef0f340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32118
64331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3211864331
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1169029920
Short name T2413
Test name
Test status
Simulation time 819073142 ps
CPU time 2.34 seconds
Started Jul 30 06:29:32 PM PDT 24
Finished Jul 30 06:29:34 PM PDT 24
Peak memory 207004 kb
Host smart-09c0345b-a7a8-44cb-a94f-98a4e8d5148d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11690
29920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1169029920
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1225936762
Short name T2170
Test name
Test status
Simulation time 217935896 ps
CPU time 1.7 seconds
Started Jul 30 06:29:29 PM PDT 24
Finished Jul 30 06:29:31 PM PDT 24
Peak memory 207012 kb
Host smart-040a9d6c-bded-47c6-9b04-dd00066543d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12259
36762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1225936762
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2768023577
Short name T1247
Test name
Test status
Simulation time 199092475 ps
CPU time 1.05 seconds
Started Jul 30 06:29:31 PM PDT 24
Finished Jul 30 06:29:32 PM PDT 24
Peak memory 207060 kb
Host smart-f6871164-38b3-416a-99ee-acee74221b18
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2768023577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2768023577
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3933061985
Short name T893
Test name
Test status
Simulation time 185541927 ps
CPU time 0.86 seconds
Started Jul 30 06:29:32 PM PDT 24
Finished Jul 30 06:29:33 PM PDT 24
Peak memory 206884 kb
Host smart-9bc30308-9a16-40e9-9b68-059fa7a8c0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39330
61985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3933061985
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1130273975
Short name T1884
Test name
Test status
Simulation time 204749562 ps
CPU time 0.97 seconds
Started Jul 30 06:29:30 PM PDT 24
Finished Jul 30 06:29:32 PM PDT 24
Peak memory 206876 kb
Host smart-2c1fb65c-8a6c-4ec4-b930-dbd7b81a9574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11302
73975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1130273975
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.3471599395
Short name T1909
Test name
Test status
Simulation time 8783519393 ps
CPU time 67.24 seconds
Started Jul 30 06:29:31 PM PDT 24
Finished Jul 30 06:30:38 PM PDT 24
Peak memory 215316 kb
Host smart-fc020959-f761-47f4-9d2e-fc38f90499f8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3471599395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.3471599395
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.4245019441
Short name T2637
Test name
Test status
Simulation time 7855681260 ps
CPU time 59 seconds
Started Jul 30 06:29:32 PM PDT 24
Finished Jul 30 06:30:32 PM PDT 24
Peak memory 207108 kb
Host smart-fa58e401-6fed-49e7-8c51-57c35b512e7f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4245019441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.4245019441
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1877082738
Short name T1859
Test name
Test status
Simulation time 158715526 ps
CPU time 0.85 seconds
Started Jul 30 06:29:32 PM PDT 24
Finished Jul 30 06:29:33 PM PDT 24
Peak memory 206944 kb
Host smart-b798f322-b227-47df-9592-2707fc613ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18770
82738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1877082738
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.686852384
Short name T2796
Test name
Test status
Simulation time 23340162303 ps
CPU time 25.81 seconds
Started Jul 30 06:29:33 PM PDT 24
Finished Jul 30 06:29:59 PM PDT 24
Peak memory 207136 kb
Host smart-ebfae591-61e8-425d-b663-8fdbf9c2e328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68685
2384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.686852384
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2088082437
Short name T1250
Test name
Test status
Simulation time 3337359092 ps
CPU time 4.81 seconds
Started Jul 30 06:29:41 PM PDT 24
Finished Jul 30 06:29:46 PM PDT 24
Peak memory 207060 kb
Host smart-2c050223-3b67-4d3a-9e9e-b4f6c9f34665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20880
82437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2088082437
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.3232433900
Short name T1917
Test name
Test status
Simulation time 7719039694 ps
CPU time 219.94 seconds
Started Jul 30 06:29:33 PM PDT 24
Finished Jul 30 06:33:13 PM PDT 24
Peak memory 215320 kb
Host smart-12b14eb0-82e1-4b14-8698-c7e04bfef005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32324
33900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3232433900
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.2071079166
Short name T1652
Test name
Test status
Simulation time 4494777550 ps
CPU time 46.3 seconds
Started Jul 30 06:29:34 PM PDT 24
Finished Jul 30 06:30:21 PM PDT 24
Peak memory 207172 kb
Host smart-5fe527b5-99dc-4f93-9b79-478f010a62ff
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2071079166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.2071079166
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1913382926
Short name T2785
Test name
Test status
Simulation time 263039638 ps
CPU time 1 seconds
Started Jul 30 06:29:42 PM PDT 24
Finished Jul 30 06:29:43 PM PDT 24
Peak memory 206944 kb
Host smart-6569c1f2-c375-4470-a79a-a137460fa0bf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1913382926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1913382926
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1747763051
Short name T2760
Test name
Test status
Simulation time 193075485 ps
CPU time 0.94 seconds
Started Jul 30 06:29:36 PM PDT 24
Finished Jul 30 06:29:37 PM PDT 24
Peak memory 206936 kb
Host smart-1d185607-859b-4bb9-a50f-9d94cfdef3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17477
63051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1747763051
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.1142958580
Short name T2684
Test name
Test status
Simulation time 4454716200 ps
CPU time 124.81 seconds
Started Jul 30 06:29:36 PM PDT 24
Finished Jul 30 06:31:41 PM PDT 24
Peak memory 215356 kb
Host smart-0ec206d4-3ce4-4d60-8749-5acb02edbed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11429
58580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1142958580
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.1311417523
Short name T2254
Test name
Test status
Simulation time 4428354871 ps
CPU time 34.28 seconds
Started Jul 30 06:29:34 PM PDT 24
Finished Jul 30 06:30:09 PM PDT 24
Peak memory 216696 kb
Host smart-93e0b876-c22a-4a6c-ae84-550e1ac0ace1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1311417523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.1311417523
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2907483204
Short name T1991
Test name
Test status
Simulation time 161328751 ps
CPU time 0.84 seconds
Started Jul 30 06:29:34 PM PDT 24
Finished Jul 30 06:29:35 PM PDT 24
Peak memory 206932 kb
Host smart-fa73b5de-58ca-4952-9147-b2750f044bc1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2907483204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2907483204
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.653551779
Short name T717
Test name
Test status
Simulation time 170752904 ps
CPU time 0.88 seconds
Started Jul 30 06:29:35 PM PDT 24
Finished Jul 30 06:29:36 PM PDT 24
Peak memory 206920 kb
Host smart-3c9c4351-00c6-4629-8194-05e6bd22aef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65355
1779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.653551779
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.346090772
Short name T2300
Test name
Test status
Simulation time 160326231 ps
CPU time 0.89 seconds
Started Jul 30 06:29:33 PM PDT 24
Finished Jul 30 06:29:34 PM PDT 24
Peak memory 206932 kb
Host smart-b5609c05-b66c-44aa-a737-4c9b8814a0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34609
0772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.346090772
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1551821459
Short name T1049
Test name
Test status
Simulation time 195278957 ps
CPU time 0.88 seconds
Started Jul 30 06:29:42 PM PDT 24
Finished Jul 30 06:29:43 PM PDT 24
Peak memory 206936 kb
Host smart-166343d7-d4fc-4345-8486-520cff9872ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15518
21459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1551821459
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2358679133
Short name T2317
Test name
Test status
Simulation time 225031236 ps
CPU time 0.93 seconds
Started Jul 30 06:29:33 PM PDT 24
Finished Jul 30 06:29:34 PM PDT 24
Peak memory 206908 kb
Host smart-c79f44fd-ddd3-41e9-9aec-d3270319c0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23586
79133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2358679133
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3756528714
Short name T2862
Test name
Test status
Simulation time 154186562 ps
CPU time 0.85 seconds
Started Jul 30 06:29:40 PM PDT 24
Finished Jul 30 06:29:41 PM PDT 24
Peak memory 206944 kb
Host smart-34c8d656-4add-4c48-97a7-8a56d03f751f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37565
28714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3756528714
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.2869340042
Short name T1949
Test name
Test status
Simulation time 221415102 ps
CPU time 1.11 seconds
Started Jul 30 06:29:38 PM PDT 24
Finished Jul 30 06:29:39 PM PDT 24
Peak memory 206912 kb
Host smart-56819d8f-221f-4f4e-86bb-fec209d5d885
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2869340042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.2869340042
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.153843509
Short name T1008
Test name
Test status
Simulation time 156615732 ps
CPU time 0.84 seconds
Started Jul 30 06:29:34 PM PDT 24
Finished Jul 30 06:29:35 PM PDT 24
Peak memory 206896 kb
Host smart-14f54e00-8aed-46bc-addc-6957d9e6fc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15384
3509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.153843509
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3866344927
Short name T2208
Test name
Test status
Simulation time 100888595 ps
CPU time 0.77 seconds
Started Jul 30 06:29:34 PM PDT 24
Finished Jul 30 06:29:35 PM PDT 24
Peak memory 206872 kb
Host smart-6910271c-805b-4999-a3b0-f9961d043ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38663
44927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3866344927
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.338530815
Short name T251
Test name
Test status
Simulation time 19781290145 ps
CPU time 52.41 seconds
Started Jul 30 06:29:48 PM PDT 24
Finished Jul 30 06:30:40 PM PDT 24
Peak memory 215312 kb
Host smart-e2be3c0c-848d-4d6a-96df-5f1202c61848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33853
0815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.338530815
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.384868769
Short name T748
Test name
Test status
Simulation time 195277736 ps
CPU time 0.85 seconds
Started Jul 30 06:29:39 PM PDT 24
Finished Jul 30 06:29:40 PM PDT 24
Peak memory 206924 kb
Host smart-a691b336-8321-4f0c-bdcc-522ab6ad20b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38486
8769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.384868769
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3034006391
Short name T2558
Test name
Test status
Simulation time 232270954 ps
CPU time 0.94 seconds
Started Jul 30 06:29:33 PM PDT 24
Finished Jul 30 06:29:35 PM PDT 24
Peak memory 206896 kb
Host smart-dbe9853d-6587-47f0-acec-ba79654442be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30340
06391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3034006391
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.4253408311
Short name T2677
Test name
Test status
Simulation time 271510020 ps
CPU time 1.03 seconds
Started Jul 30 06:29:36 PM PDT 24
Finished Jul 30 06:29:37 PM PDT 24
Peak memory 206912 kb
Host smart-bf2f0b6b-680a-4c75-89ab-9ce9444441ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42534
08311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.4253408311
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.1457945789
Short name T485
Test name
Test status
Simulation time 158884902 ps
CPU time 0.9 seconds
Started Jul 30 06:29:32 PM PDT 24
Finished Jul 30 06:29:33 PM PDT 24
Peak memory 206904 kb
Host smart-e727bd4f-413a-4d9b-9a13-8805a606b26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14579
45789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.1457945789
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1513085441
Short name T603
Test name
Test status
Simulation time 141698841 ps
CPU time 0.86 seconds
Started Jul 30 06:29:48 PM PDT 24
Finished Jul 30 06:29:49 PM PDT 24
Peak memory 206856 kb
Host smart-537fcc93-e000-48e7-b75f-7600c9989d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15130
85441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1513085441
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1684085546
Short name T428
Test name
Test status
Simulation time 148590006 ps
CPU time 0.84 seconds
Started Jul 30 06:29:34 PM PDT 24
Finished Jul 30 06:29:35 PM PDT 24
Peak memory 206876 kb
Host smart-fc724284-a6be-4b84-9122-86f20ae6d612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16840
85546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1684085546
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3330314685
Short name T2650
Test name
Test status
Simulation time 152446654 ps
CPU time 0.86 seconds
Started Jul 30 06:29:34 PM PDT 24
Finished Jul 30 06:29:35 PM PDT 24
Peak memory 206920 kb
Host smart-18f5439a-2e0f-49a3-b0d8-c13e386849cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33303
14685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3330314685
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.406135048
Short name T2479
Test name
Test status
Simulation time 216105497 ps
CPU time 1.04 seconds
Started Jul 30 06:29:33 PM PDT 24
Finished Jul 30 06:29:35 PM PDT 24
Peak memory 206912 kb
Host smart-f92f6cbd-170a-4d16-8efa-e1b6f9458c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40613
5048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.406135048
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.3155601512
Short name T1727
Test name
Test status
Simulation time 6362350026 ps
CPU time 48.14 seconds
Started Jul 30 06:29:37 PM PDT 24
Finished Jul 30 06:30:25 PM PDT 24
Peak memory 216784 kb
Host smart-cd6be6bd-7524-4244-8d93-b73808a209bd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3155601512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3155601512
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3545133927
Short name T2025
Test name
Test status
Simulation time 167101078 ps
CPU time 0.91 seconds
Started Jul 30 06:29:45 PM PDT 24
Finished Jul 30 06:29:46 PM PDT 24
Peak memory 206908 kb
Host smart-f844ae96-ea53-4537-8e26-b5505ef52fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35451
33927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3545133927
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2125954338
Short name T2305
Test name
Test status
Simulation time 160729920 ps
CPU time 0.83 seconds
Started Jul 30 06:29:36 PM PDT 24
Finished Jul 30 06:29:37 PM PDT 24
Peak memory 206920 kb
Host smart-09ec6354-3edd-4e49-a025-9cc99928f9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21259
54338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2125954338
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.1311160408
Short name T644
Test name
Test status
Simulation time 690687560 ps
CPU time 2.1 seconds
Started Jul 30 06:29:35 PM PDT 24
Finished Jul 30 06:29:37 PM PDT 24
Peak memory 206876 kb
Host smart-c3acc3e9-51a7-4963-b7f5-030b13cb1989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13111
60408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.1311160408
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.4759066
Short name T437
Test name
Test status
Simulation time 8045454255 ps
CPU time 224.72 seconds
Started Jul 30 06:29:33 PM PDT 24
Finished Jul 30 06:33:18 PM PDT 24
Peak memory 215348 kb
Host smart-d3d15f3b-2efe-4b6b-8fb9-bbba4ecb2657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47590
66 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.4759066
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.3285742197
Short name T2377
Test name
Test status
Simulation time 4924805760 ps
CPU time 31.94 seconds
Started Jul 30 06:29:31 PM PDT 24
Finished Jul 30 06:30:03 PM PDT 24
Peak memory 207080 kb
Host smart-d63fb40e-c65f-41b7-b22d-f5bb3ef0070c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285742197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.3285742197
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.2220108027
Short name T354
Test name
Test status
Simulation time 91506662 ps
CPU time 0.74 seconds
Started Jul 30 06:29:47 PM PDT 24
Finished Jul 30 06:29:47 PM PDT 24
Peak memory 207064 kb
Host smart-b3cb8ba9-a2f9-4755-b1da-dffe5fdd0a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2220108027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.2220108027
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1731784056
Short name T2641
Test name
Test status
Simulation time 4276989751 ps
CPU time 6.64 seconds
Started Jul 30 06:29:34 PM PDT 24
Finished Jul 30 06:29:41 PM PDT 24
Peak memory 207080 kb
Host smart-843b478f-e801-4e7e-9a21-640ee524f0da
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731784056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_disconnect.1731784056
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1366101391
Short name T684
Test name
Test status
Simulation time 13307473933 ps
CPU time 15.26 seconds
Started Jul 30 06:29:36 PM PDT 24
Finished Jul 30 06:29:51 PM PDT 24
Peak memory 207140 kb
Host smart-611016ef-4a9d-462d-9cad-618eac0ffb02
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366101391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1366101391
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.144829472
Short name T681
Test name
Test status
Simulation time 23320553079 ps
CPU time 36.31 seconds
Started Jul 30 06:29:34 PM PDT 24
Finished Jul 30 06:30:10 PM PDT 24
Peak memory 207136 kb
Host smart-812c21e6-2b3b-4638-ab5c-777c08b56ea1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144829472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ao
n_wake_resume.144829472
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1866538634
Short name T1814
Test name
Test status
Simulation time 167499541 ps
CPU time 0.91 seconds
Started Jul 30 06:29:33 PM PDT 24
Finished Jul 30 06:29:34 PM PDT 24
Peak memory 206948 kb
Host smart-1dd07071-cf12-4665-b571-627be76ede50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18665
38634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1866538634
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.4031049199
Short name T1421
Test name
Test status
Simulation time 161648790 ps
CPU time 0.91 seconds
Started Jul 30 06:29:37 PM PDT 24
Finished Jul 30 06:29:38 PM PDT 24
Peak memory 206880 kb
Host smart-f4967722-9b63-48a5-a0df-c85b72d83c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40310
49199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.4031049199
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3402565167
Short name T1534
Test name
Test status
Simulation time 209382276 ps
CPU time 1.03 seconds
Started Jul 30 06:29:39 PM PDT 24
Finished Jul 30 06:29:40 PM PDT 24
Peak memory 206912 kb
Host smart-10db5f4e-7d1d-4db2-8101-8f8a624a0fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34025
65167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3402565167
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.2104410354
Short name T2001
Test name
Test status
Simulation time 984016539 ps
CPU time 2.75 seconds
Started Jul 30 06:29:47 PM PDT 24
Finished Jul 30 06:29:49 PM PDT 24
Peak memory 207024 kb
Host smart-c994e5e3-65db-479d-a14e-b6404a39d074
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2104410354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2104410354
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1632299083
Short name T1565
Test name
Test status
Simulation time 15125385140 ps
CPU time 32.06 seconds
Started Jul 30 06:29:49 PM PDT 24
Finished Jul 30 06:30:22 PM PDT 24
Peak memory 207116 kb
Host smart-9904d21e-6020-4f03-98b2-f8ccdfbad42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16322
99083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1632299083
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.2415834837
Short name T792
Test name
Test status
Simulation time 3892921705 ps
CPU time 34.71 seconds
Started Jul 30 06:29:44 PM PDT 24
Finished Jul 30 06:30:19 PM PDT 24
Peak memory 207148 kb
Host smart-d28ba4d4-6f18-4119-a5ba-ea964d146fa0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415834837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.2415834837
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3864703041
Short name T300
Test name
Test status
Simulation time 493677490 ps
CPU time 1.65 seconds
Started Jul 30 06:29:51 PM PDT 24
Finished Jul 30 06:29:52 PM PDT 24
Peak memory 206904 kb
Host smart-185a6a80-4034-490c-a4d8-5ca50721bd99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38647
03041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3864703041
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.21115349
Short name T2803
Test name
Test status
Simulation time 147414977 ps
CPU time 0.78 seconds
Started Jul 30 06:29:38 PM PDT 24
Finished Jul 30 06:29:38 PM PDT 24
Peak memory 206868 kb
Host smart-5d6921ff-0ced-44ca-8e56-a2b7b8832f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21115
349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.21115349
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.2847967012
Short name T620
Test name
Test status
Simulation time 104786906 ps
CPU time 0.76 seconds
Started Jul 30 06:29:37 PM PDT 24
Finished Jul 30 06:29:38 PM PDT 24
Peak memory 206868 kb
Host smart-b41a03a2-a5c4-4b91-a940-2a7add639e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28479
67012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2847967012
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2052618562
Short name T1865
Test name
Test status
Simulation time 867785536 ps
CPU time 2.62 seconds
Started Jul 30 06:29:56 PM PDT 24
Finished Jul 30 06:29:59 PM PDT 24
Peak memory 207024 kb
Host smart-f5065710-b833-4a01-97a8-87b2acded1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20526
18562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2052618562
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2672144767
Short name T1840
Test name
Test status
Simulation time 376983361 ps
CPU time 2.45 seconds
Started Jul 30 06:29:55 PM PDT 24
Finished Jul 30 06:29:57 PM PDT 24
Peak memory 206976 kb
Host smart-b6828460-ee45-4403-b675-45247dde9956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26721
44767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2672144767
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3468298903
Short name T562
Test name
Test status
Simulation time 150974275 ps
CPU time 0.85 seconds
Started Jul 30 06:29:38 PM PDT 24
Finished Jul 30 06:29:39 PM PDT 24
Peak memory 206944 kb
Host smart-a140d968-a9af-4ff9-9309-6134f18d3124
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3468298903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3468298903
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.4095741691
Short name T905
Test name
Test status
Simulation time 159896379 ps
CPU time 0.86 seconds
Started Jul 30 06:29:38 PM PDT 24
Finished Jul 30 06:29:39 PM PDT 24
Peak memory 206900 kb
Host smart-ce1dfed4-f5a2-4182-b6ab-91e1239cc630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40957
41691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.4095741691
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3196868970
Short name T2614
Test name
Test status
Simulation time 157340525 ps
CPU time 0.89 seconds
Started Jul 30 06:29:38 PM PDT 24
Finished Jul 30 06:29:39 PM PDT 24
Peak memory 206924 kb
Host smart-99d4ebb6-a810-4d1b-b377-6b703461489d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31968
68970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3196868970
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.1444795855
Short name T1599
Test name
Test status
Simulation time 6260105578 ps
CPU time 47.28 seconds
Started Jul 30 06:29:40 PM PDT 24
Finished Jul 30 06:30:32 PM PDT 24
Peak memory 215288 kb
Host smart-8dd7b7ec-ad78-49a1-997d-89a4a05bd46c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1444795855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1444795855
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.1201073324
Short name T1324
Test name
Test status
Simulation time 7271549499 ps
CPU time 89.48 seconds
Started Jul 30 06:29:51 PM PDT 24
Finished Jul 30 06:31:20 PM PDT 24
Peak memory 207084 kb
Host smart-d41c8bf3-1c8d-4cc6-8f06-d3932aba3103
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1201073324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.1201073324
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.4078312302
Short name T2643
Test name
Test status
Simulation time 198675180 ps
CPU time 0.96 seconds
Started Jul 30 06:29:44 PM PDT 24
Finished Jul 30 06:29:45 PM PDT 24
Peak memory 206912 kb
Host smart-f8796a2c-061a-42fa-be79-ce6882da0254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40783
12302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.4078312302
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.3493842549
Short name T31
Test name
Test status
Simulation time 23339403591 ps
CPU time 34.62 seconds
Started Jul 30 06:29:51 PM PDT 24
Finished Jul 30 06:30:26 PM PDT 24
Peak memory 207132 kb
Host smart-3c3fbe5e-6a40-4ecb-8e35-db87f50214f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34938
42549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.3493842549
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2198702588
Short name T399
Test name
Test status
Simulation time 3294895887 ps
CPU time 5.45 seconds
Started Jul 30 06:29:39 PM PDT 24
Finished Jul 30 06:29:45 PM PDT 24
Peak memory 207108 kb
Host smart-1065f1ba-7c80-45d9-b047-a9c4ec569a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21987
02588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2198702588
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2057835413
Short name T2027
Test name
Test status
Simulation time 6522024145 ps
CPU time 64.69 seconds
Started Jul 30 06:29:41 PM PDT 24
Finished Jul 30 06:30:46 PM PDT 24
Peak memory 216920 kb
Host smart-dadc7b63-f891-469b-ab5a-d8febec0ce52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20578
35413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2057835413
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.882422655
Short name T446
Test name
Test status
Simulation time 7770922584 ps
CPU time 238.14 seconds
Started Jul 30 06:29:41 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 215364 kb
Host smart-7f07a151-8193-4564-9039-39f67cc8e59e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=882422655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.882422655
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.2268665523
Short name T2584
Test name
Test status
Simulation time 263043966 ps
CPU time 0.99 seconds
Started Jul 30 06:29:50 PM PDT 24
Finished Jul 30 06:29:51 PM PDT 24
Peak memory 206920 kb
Host smart-8b175c87-c045-45d5-bd18-6e9a7ba7cf5f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2268665523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.2268665523
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2330915179
Short name T1767
Test name
Test status
Simulation time 187584799 ps
CPU time 0.92 seconds
Started Jul 30 06:29:48 PM PDT 24
Finished Jul 30 06:29:49 PM PDT 24
Peak memory 206908 kb
Host smart-51140822-f3de-452f-90c4-a89283eaa80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23309
15179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2330915179
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2031659539
Short name T37
Test name
Test status
Simulation time 5424474059 ps
CPU time 43.75 seconds
Started Jul 30 06:29:38 PM PDT 24
Finished Jul 30 06:30:22 PM PDT 24
Peak memory 216776 kb
Host smart-fbb1da09-c6a4-4bd4-8341-abeff6c81b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20316
59539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2031659539
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.2829698499
Short name T2517
Test name
Test status
Simulation time 5319975688 ps
CPU time 151.32 seconds
Started Jul 30 06:29:58 PM PDT 24
Finished Jul 30 06:32:29 PM PDT 24
Peak memory 215372 kb
Host smart-c888d54b-9ddb-4452-9e8e-9a5039d62769
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2829698499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.2829698499
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.1807815290
Short name T2114
Test name
Test status
Simulation time 143990599 ps
CPU time 0.84 seconds
Started Jul 30 06:29:41 PM PDT 24
Finished Jul 30 06:29:42 PM PDT 24
Peak memory 206948 kb
Host smart-9b7a3d70-8cfc-4a94-8c18-d7f22d890d08
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1807815290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.1807815290
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.707673337
Short name T1617
Test name
Test status
Simulation time 148278225 ps
CPU time 0.81 seconds
Started Jul 30 06:29:46 PM PDT 24
Finished Jul 30 06:29:47 PM PDT 24
Peak memory 206952 kb
Host smart-90af9703-d062-46c0-8f2a-9f36f5506489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70767
3337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.707673337
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3031614054
Short name T130
Test name
Test status
Simulation time 244137939 ps
CPU time 1.03 seconds
Started Jul 30 06:29:37 PM PDT 24
Finished Jul 30 06:29:38 PM PDT 24
Peak memory 206976 kb
Host smart-8f7b31a0-030d-4641-8aea-03b1f4acf14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30316
14054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3031614054
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.1982386544
Short name T971
Test name
Test status
Simulation time 160963702 ps
CPU time 0.95 seconds
Started Jul 30 06:29:51 PM PDT 24
Finished Jul 30 06:29:52 PM PDT 24
Peak memory 206912 kb
Host smart-d06d6d4e-2a61-4249-9c65-0ffd8e71f084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19823
86544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.1982386544
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3644569485
Short name T1552
Test name
Test status
Simulation time 198432556 ps
CPU time 0.91 seconds
Started Jul 30 06:29:52 PM PDT 24
Finished Jul 30 06:29:52 PM PDT 24
Peak memory 206924 kb
Host smart-7ccdd10d-3113-4914-9b72-50fc1c110a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36445
69485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3644569485
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.2010417766
Short name T835
Test name
Test status
Simulation time 241392495 ps
CPU time 1.06 seconds
Started Jul 30 06:29:46 PM PDT 24
Finished Jul 30 06:29:47 PM PDT 24
Peak memory 206952 kb
Host smart-6c9ce4f9-865e-405f-bc5d-d8170a527e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20104
17766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2010417766
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2624419790
Short name T172
Test name
Test status
Simulation time 161213916 ps
CPU time 0.85 seconds
Started Jul 30 06:29:39 PM PDT 24
Finished Jul 30 06:29:40 PM PDT 24
Peak memory 206904 kb
Host smart-08710f46-e9d5-4331-a14d-b7cdd37bec76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26244
19790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2624419790
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.569351108
Short name T1221
Test name
Test status
Simulation time 239203467 ps
CPU time 1.06 seconds
Started Jul 30 06:29:40 PM PDT 24
Finished Jul 30 06:29:41 PM PDT 24
Peak memory 206944 kb
Host smart-527c5ea7-488f-4164-a476-25dbe8bd911c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=569351108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.569351108
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.707020075
Short name T1927
Test name
Test status
Simulation time 136960540 ps
CPU time 0.89 seconds
Started Jul 30 06:29:43 PM PDT 24
Finished Jul 30 06:29:44 PM PDT 24
Peak memory 206928 kb
Host smart-de6a00a4-82c2-4f71-8173-172d741427d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70702
0075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.707020075
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.1670481085
Short name T2370
Test name
Test status
Simulation time 41943999 ps
CPU time 0.7 seconds
Started Jul 30 06:29:44 PM PDT 24
Finished Jul 30 06:29:45 PM PDT 24
Peak memory 206884 kb
Host smart-bc2abc2d-d4d0-48fc-8304-cc33fb2f8339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16704
81085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1670481085
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3243206331
Short name T255
Test name
Test status
Simulation time 7534435821 ps
CPU time 22.14 seconds
Started Jul 30 06:29:45 PM PDT 24
Finished Jul 30 06:30:07 PM PDT 24
Peak memory 219120 kb
Host smart-e09a14ec-38c1-44ad-8275-b810e8c165bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32432
06331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3243206331
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3503289887
Short name T1035
Test name
Test status
Simulation time 186373439 ps
CPU time 0.96 seconds
Started Jul 30 06:29:55 PM PDT 24
Finished Jul 30 06:29:56 PM PDT 24
Peak memory 206932 kb
Host smart-50366b41-c508-4691-8c3e-ca82a48ebc38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35032
89887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3503289887
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1189552736
Short name T995
Test name
Test status
Simulation time 201300030 ps
CPU time 0.92 seconds
Started Jul 30 06:29:42 PM PDT 24
Finished Jul 30 06:29:43 PM PDT 24
Peak memory 206964 kb
Host smart-ea171862-40e7-4f69-a689-9bed595e913f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11895
52736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1189552736
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1112562737
Short name T1854
Test name
Test status
Simulation time 230832245 ps
CPU time 1.03 seconds
Started Jul 30 06:29:48 PM PDT 24
Finished Jul 30 06:29:49 PM PDT 24
Peak memory 206916 kb
Host smart-7caf962d-6030-4350-9c15-77bc32ec5b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11125
62737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1112562737
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.527529193
Short name T349
Test name
Test status
Simulation time 165907049 ps
CPU time 0.86 seconds
Started Jul 30 06:29:43 PM PDT 24
Finished Jul 30 06:29:44 PM PDT 24
Peak memory 206972 kb
Host smart-9cb4c250-298c-4e48-b4a1-6eb5ca163b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52752
9193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.527529193
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.1643468460
Short name T1581
Test name
Test status
Simulation time 166976298 ps
CPU time 0.88 seconds
Started Jul 30 06:29:56 PM PDT 24
Finished Jul 30 06:29:57 PM PDT 24
Peak memory 206988 kb
Host smart-3f848cbe-e888-469b-b9a8-36c92d329b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16434
68460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.1643468460
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2598350647
Short name T1764
Test name
Test status
Simulation time 151358461 ps
CPU time 0.82 seconds
Started Jul 30 06:29:57 PM PDT 24
Finished Jul 30 06:29:57 PM PDT 24
Peak memory 206844 kb
Host smart-a10b1e61-601b-435e-96a7-87a73c7e1988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25983
50647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2598350647
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.721517524
Short name T1184
Test name
Test status
Simulation time 153868537 ps
CPU time 0.87 seconds
Started Jul 30 06:29:43 PM PDT 24
Finished Jul 30 06:29:45 PM PDT 24
Peak memory 206912 kb
Host smart-a84cd853-7046-4588-8b83-2a53dbc4f17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72151
7524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.721517524
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1360181742
Short name T2010
Test name
Test status
Simulation time 251317459 ps
CPU time 1.04 seconds
Started Jul 30 06:29:53 PM PDT 24
Finished Jul 30 06:29:54 PM PDT 24
Peak memory 206920 kb
Host smart-7c4db2a2-c4fb-4e7b-bd90-ee19d9ae2e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13601
81742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1360181742
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2526120700
Short name T923
Test name
Test status
Simulation time 5425321124 ps
CPU time 52.88 seconds
Started Jul 30 06:29:42 PM PDT 24
Finished Jul 30 06:30:35 PM PDT 24
Peak memory 216428 kb
Host smart-358b4543-5aba-4867-8635-62fa1f800b36
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2526120700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2526120700
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1934094223
Short name T2218
Test name
Test status
Simulation time 180309095 ps
CPU time 0.92 seconds
Started Jul 30 06:29:42 PM PDT 24
Finished Jul 30 06:29:43 PM PDT 24
Peak memory 206944 kb
Host smart-397511af-2651-4dcc-a1db-e51042ae070d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19340
94223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1934094223
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.333441419
Short name T2750
Test name
Test status
Simulation time 145039907 ps
CPU time 0.8 seconds
Started Jul 30 06:29:42 PM PDT 24
Finished Jul 30 06:29:43 PM PDT 24
Peak memory 206972 kb
Host smart-fdf9a4d5-50b6-452c-9a7e-70d404a465bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
1419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.333441419
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.217224254
Short name T865
Test name
Test status
Simulation time 337611022 ps
CPU time 1.18 seconds
Started Jul 30 06:29:49 PM PDT 24
Finished Jul 30 06:29:51 PM PDT 24
Peak memory 206880 kb
Host smart-c0ba28a3-5e05-4f75-a120-d39707e69d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21722
4254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.217224254
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.550875892
Short name T2609
Test name
Test status
Simulation time 5893585364 ps
CPU time 44.67 seconds
Started Jul 30 06:29:46 PM PDT 24
Finished Jul 30 06:30:30 PM PDT 24
Peak memory 207152 kb
Host smart-039c4279-b0f5-42c4-bc72-df27c6d52336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55087
5892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.550875892
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.3382116147
Short name T699
Test name
Test status
Simulation time 3371263305 ps
CPU time 28.29 seconds
Started Jul 30 06:29:38 PM PDT 24
Finished Jul 30 06:30:07 PM PDT 24
Peak memory 207128 kb
Host smart-07ca0267-17d7-453f-97cf-04cf7f45788f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382116147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.3382116147
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.3659617810
Short name T2847
Test name
Test status
Simulation time 42140949 ps
CPU time 0.65 seconds
Started Jul 30 06:29:56 PM PDT 24
Finished Jul 30 06:29:56 PM PDT 24
Peak memory 207020 kb
Host smart-fbbaf604-7dcd-4d5a-935f-7bf6bc486aaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3659617810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.3659617810
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.4180365928
Short name T676
Test name
Test status
Simulation time 3538218895 ps
CPU time 5.41 seconds
Started Jul 30 06:29:57 PM PDT 24
Finished Jul 30 06:30:03 PM PDT 24
Peak memory 207100 kb
Host smart-fe85bbad-e1d3-4358-8701-bd1a70badead
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180365928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.4180365928
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.4029300288
Short name T217
Test name
Test status
Simulation time 13383721923 ps
CPU time 17.82 seconds
Started Jul 30 06:29:45 PM PDT 24
Finished Jul 30 06:30:03 PM PDT 24
Peak memory 207152 kb
Host smart-10c6efab-57a2-40fa-9ded-555ee4fab321
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029300288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.4029300288
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.199716534
Short name T1983
Test name
Test status
Simulation time 23383666948 ps
CPU time 32.82 seconds
Started Jul 30 06:29:50 PM PDT 24
Finished Jul 30 06:30:23 PM PDT 24
Peak memory 207104 kb
Host smart-15df2669-6c31-42b3-9785-d06dbcfdf51d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199716534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_ao
n_wake_resume.199716534
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.73401931
Short name T1886
Test name
Test status
Simulation time 174971156 ps
CPU time 0.87 seconds
Started Jul 30 06:29:59 PM PDT 24
Finished Jul 30 06:30:00 PM PDT 24
Peak memory 206980 kb
Host smart-090f97b9-dc06-43e8-ba2f-fc268ca6e318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73401
931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.73401931
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3061143086
Short name T1378
Test name
Test status
Simulation time 146958647 ps
CPU time 0.85 seconds
Started Jul 30 06:30:00 PM PDT 24
Finished Jul 30 06:30:01 PM PDT 24
Peak memory 206876 kb
Host smart-80a11f34-2bd2-4b85-8229-42ac1b04bf0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30611
43086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3061143086
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2822643695
Short name T1255
Test name
Test status
Simulation time 328462425 ps
CPU time 1.23 seconds
Started Jul 30 06:29:57 PM PDT 24
Finished Jul 30 06:29:58 PM PDT 24
Peak memory 206960 kb
Host smart-3233d4ff-78a4-4325-a31f-1b3ca10d3412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28226
43695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2822643695
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.4214450103
Short name T721
Test name
Test status
Simulation time 743751047 ps
CPU time 2.07 seconds
Started Jul 30 06:29:46 PM PDT 24
Finished Jul 30 06:29:48 PM PDT 24
Peak memory 207024 kb
Host smart-dd79eca2-4f58-47d0-984b-c59f3174cbb0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4214450103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.4214450103
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.3836318267
Short name T1468
Test name
Test status
Simulation time 10202537367 ps
CPU time 24.2 seconds
Started Jul 30 06:29:50 PM PDT 24
Finished Jul 30 06:30:14 PM PDT 24
Peak memory 207128 kb
Host smart-a8f69840-06cb-40cc-a56a-0fc74f3c8a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38363
18267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.3836318267
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.3484106609
Short name T415
Test name
Test status
Simulation time 615334775 ps
CPU time 11.96 seconds
Started Jul 30 06:29:53 PM PDT 24
Finished Jul 30 06:30:05 PM PDT 24
Peak memory 207012 kb
Host smart-fae8d556-35c8-4ad1-856d-431f18130a2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484106609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.3484106609
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.909138678
Short name T2204
Test name
Test status
Simulation time 446133492 ps
CPU time 1.48 seconds
Started Jul 30 06:29:57 PM PDT 24
Finished Jul 30 06:29:58 PM PDT 24
Peak memory 206872 kb
Host smart-b0fc8fa2-c10f-4718-bd0c-0ff713ef9af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90913
8678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.909138678
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.1007893656
Short name T461
Test name
Test status
Simulation time 150836260 ps
CPU time 0.8 seconds
Started Jul 30 06:29:54 PM PDT 24
Finished Jul 30 06:29:55 PM PDT 24
Peak memory 206872 kb
Host smart-f755702c-3c65-4c51-ace7-d88b918a035e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10078
93656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1007893656
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.527326387
Short name T2494
Test name
Test status
Simulation time 79322353 ps
CPU time 0.73 seconds
Started Jul 30 06:29:45 PM PDT 24
Finished Jul 30 06:29:46 PM PDT 24
Peak memory 206868 kb
Host smart-1c56fdec-f89b-461c-b41f-4a23c6e4a948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52732
6387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.527326387
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2397964221
Short name T665
Test name
Test status
Simulation time 833477664 ps
CPU time 2.48 seconds
Started Jul 30 06:29:50 PM PDT 24
Finished Jul 30 06:29:53 PM PDT 24
Peak memory 206992 kb
Host smart-d544cea1-e018-4f59-ad7c-e9f944ee2467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23979
64221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2397964221
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2987568631
Short name T851
Test name
Test status
Simulation time 271374465 ps
CPU time 1.83 seconds
Started Jul 30 06:29:48 PM PDT 24
Finished Jul 30 06:29:50 PM PDT 24
Peak memory 207048 kb
Host smart-7bcad1e2-cf5b-4402-b19e-0e0c70b8b38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29875
68631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2987568631
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.4174626508
Short name T1686
Test name
Test status
Simulation time 243070831 ps
CPU time 1.27 seconds
Started Jul 30 06:30:01 PM PDT 24
Finished Jul 30 06:30:03 PM PDT 24
Peak memory 215212 kb
Host smart-4a29e2f0-d45f-4135-82e4-0d6aaaed7b1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4174626508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.4174626508
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1425324978
Short name T1202
Test name
Test status
Simulation time 161579418 ps
CPU time 0.88 seconds
Started Jul 30 06:29:58 PM PDT 24
Finished Jul 30 06:29:59 PM PDT 24
Peak memory 206948 kb
Host smart-95bc9cac-61e1-4ec0-a975-a2b784788fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14253
24978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1425324978
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1727787128
Short name T2538
Test name
Test status
Simulation time 248187257 ps
CPU time 1 seconds
Started Jul 30 06:29:46 PM PDT 24
Finished Jul 30 06:29:47 PM PDT 24
Peak memory 206980 kb
Host smart-2b2da62d-6831-4cb6-bc61-2280b71de897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17277
87128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1727787128
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.1778126602
Short name T2603
Test name
Test status
Simulation time 4782019382 ps
CPU time 36.12 seconds
Started Jul 30 06:29:56 PM PDT 24
Finished Jul 30 06:30:32 PM PDT 24
Peak memory 216900 kb
Host smart-d4e71210-3981-4a31-b21c-1a42c2b7f4df
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1778126602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.1778126602
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.624903901
Short name T1229
Test name
Test status
Simulation time 13242494501 ps
CPU time 93.53 seconds
Started Jul 30 06:29:50 PM PDT 24
Finished Jul 30 06:31:23 PM PDT 24
Peak memory 207088 kb
Host smart-3defde50-87ae-4ca4-b5e0-aa002976b504
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=624903901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.624903901
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2440378768
Short name T1665
Test name
Test status
Simulation time 178010783 ps
CPU time 0.88 seconds
Started Jul 30 06:29:48 PM PDT 24
Finished Jul 30 06:29:48 PM PDT 24
Peak memory 206920 kb
Host smart-7ec18a32-985d-4d10-8e87-828582b22a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24403
78768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2440378768
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.1865384073
Short name T2730
Test name
Test status
Simulation time 23326086696 ps
CPU time 31.63 seconds
Started Jul 30 06:29:52 PM PDT 24
Finished Jul 30 06:30:24 PM PDT 24
Peak memory 207144 kb
Host smart-14d73d6b-0130-440f-960b-6d403d283382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18653
84073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.1865384073
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.1417547138
Short name T749
Test name
Test status
Simulation time 3262493098 ps
CPU time 5.33 seconds
Started Jul 30 06:29:59 PM PDT 24
Finished Jul 30 06:30:04 PM PDT 24
Peak memory 207064 kb
Host smart-a2d13aad-1699-4941-8c10-e9087d128785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14175
47138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.1417547138
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.3180659877
Short name T498
Test name
Test status
Simulation time 7452689612 ps
CPU time 71.52 seconds
Started Jul 30 06:30:00 PM PDT 24
Finished Jul 30 06:31:12 PM PDT 24
Peak memory 217404 kb
Host smart-d1df21b0-7a42-4cfd-b31e-bd97597404db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31806
59877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.3180659877
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.4267323240
Short name T595
Test name
Test status
Simulation time 3998319321 ps
CPU time 106.52 seconds
Started Jul 30 06:30:07 PM PDT 24
Finished Jul 30 06:31:53 PM PDT 24
Peak memory 215360 kb
Host smart-49504a7a-00b6-4cba-840e-6de173deb6e0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4267323240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.4267323240
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1747989867
Short name T1215
Test name
Test status
Simulation time 256512221 ps
CPU time 0.98 seconds
Started Jul 30 06:29:55 PM PDT 24
Finished Jul 30 06:29:56 PM PDT 24
Peak memory 206956 kb
Host smart-9833cae0-1fb3-48a8-b037-c56277c04129
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1747989867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1747989867
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.4092004423
Short name T1546
Test name
Test status
Simulation time 212197542 ps
CPU time 1 seconds
Started Jul 30 06:30:03 PM PDT 24
Finished Jul 30 06:30:04 PM PDT 24
Peak memory 206920 kb
Host smart-5733b903-9091-4ce2-ab2b-a07996f4e51a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40920
04423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.4092004423
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2207699855
Short name T654
Test name
Test status
Simulation time 4309448177 ps
CPU time 128.34 seconds
Started Jul 30 06:29:50 PM PDT 24
Finished Jul 30 06:31:58 PM PDT 24
Peak memory 215316 kb
Host smart-7ad52409-e5ee-4f15-b2d2-f40e4495c23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22076
99855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2207699855
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.210967218
Short name T2632
Test name
Test status
Simulation time 3513392272 ps
CPU time 97.74 seconds
Started Jul 30 06:30:03 PM PDT 24
Finished Jul 30 06:31:41 PM PDT 24
Peak memory 215336 kb
Host smart-897b696b-9af3-4622-bc9b-bb70df6df427
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=210967218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.210967218
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.3181660953
Short name T1997
Test name
Test status
Simulation time 220838728 ps
CPU time 1 seconds
Started Jul 30 06:29:50 PM PDT 24
Finished Jul 30 06:29:51 PM PDT 24
Peak memory 206908 kb
Host smart-345a3b7f-736f-425b-b0e3-d608cb26dec6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3181660953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.3181660953
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1406692142
Short name T1135
Test name
Test status
Simulation time 174501276 ps
CPU time 0.85 seconds
Started Jul 30 06:29:54 PM PDT 24
Finished Jul 30 06:29:55 PM PDT 24
Peak memory 206928 kb
Host smart-80449a55-3530-4b9c-a9b8-2566adb0f268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14066
92142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1406692142
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.323583878
Short name T1829
Test name
Test status
Simulation time 247132510 ps
CPU time 0.98 seconds
Started Jul 30 06:29:59 PM PDT 24
Finished Jul 30 06:30:00 PM PDT 24
Peak memory 206952 kb
Host smart-f1dff02c-2a6b-4f32-8ea1-969b37d7dd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32358
3878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.323583878
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.3294108269
Short name T378
Test name
Test status
Simulation time 185659020 ps
CPU time 0.96 seconds
Started Jul 30 06:29:59 PM PDT 24
Finished Jul 30 06:30:00 PM PDT 24
Peak memory 206916 kb
Host smart-08192f25-9bb8-4ffe-afa2-fe7d8b9e853c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32941
08269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3294108269
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.302320231
Short name T2791
Test name
Test status
Simulation time 170459996 ps
CPU time 0.89 seconds
Started Jul 30 06:29:51 PM PDT 24
Finished Jul 30 06:29:52 PM PDT 24
Peak memory 206908 kb
Host smart-ad543862-e320-4475-83dc-295f92f364b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30232
0231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.302320231
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1302772547
Short name T2734
Test name
Test status
Simulation time 203716238 ps
CPU time 0.86 seconds
Started Jul 30 06:29:59 PM PDT 24
Finished Jul 30 06:30:00 PM PDT 24
Peak memory 206928 kb
Host smart-036cfc6f-74b6-4bbd-bd89-26b82da126b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13027
72547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1302772547
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2764546178
Short name T2214
Test name
Test status
Simulation time 164433964 ps
CPU time 0.84 seconds
Started Jul 30 06:29:57 PM PDT 24
Finished Jul 30 06:29:58 PM PDT 24
Peak memory 206928 kb
Host smart-442f0595-4f6c-43ac-8aff-e3b4653a4607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27645
46178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2764546178
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.387793228
Short name T1
Test name
Test status
Simulation time 219440177 ps
CPU time 1.03 seconds
Started Jul 30 06:29:52 PM PDT 24
Finished Jul 30 06:29:53 PM PDT 24
Peak memory 206908 kb
Host smart-413302b6-6ee0-49c3-88d0-65e6b66a8ce1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=387793228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.387793228
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1264055295
Short name T1592
Test name
Test status
Simulation time 137637744 ps
CPU time 0.86 seconds
Started Jul 30 06:29:59 PM PDT 24
Finished Jul 30 06:30:00 PM PDT 24
Peak memory 206896 kb
Host smart-6b5c2a33-70f1-4391-9c67-2b1600a908da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12640
55295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1264055295
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.742401612
Short name T896
Test name
Test status
Simulation time 44084290 ps
CPU time 0.67 seconds
Started Jul 30 06:30:06 PM PDT 24
Finished Jul 30 06:30:07 PM PDT 24
Peak memory 206888 kb
Host smart-0bd7074b-657a-4621-8509-841388c45be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74240
1612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.742401612
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2854849909
Short name T1031
Test name
Test status
Simulation time 15003180508 ps
CPU time 37.92 seconds
Started Jul 30 06:29:58 PM PDT 24
Finished Jul 30 06:30:36 PM PDT 24
Peak memory 215420 kb
Host smart-332cc5ba-ebaf-4e80-85d5-588902b8e8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28548
49909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2854849909
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.933668533
Short name T2040
Test name
Test status
Simulation time 195646549 ps
CPU time 0.93 seconds
Started Jul 30 06:30:00 PM PDT 24
Finished Jul 30 06:30:02 PM PDT 24
Peak memory 206908 kb
Host smart-34c321b2-d631-4481-9041-d9bf06b837a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93366
8533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.933668533
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1712435679
Short name T323
Test name
Test status
Simulation time 239361557 ps
CPU time 0.98 seconds
Started Jul 30 06:30:01 PM PDT 24
Finished Jul 30 06:30:02 PM PDT 24
Peak memory 206908 kb
Host smart-b64ae4c1-4499-4bc6-aba4-6fdd2edf5fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17124
35679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1712435679
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.4225395450
Short name T951
Test name
Test status
Simulation time 164336739 ps
CPU time 0.88 seconds
Started Jul 30 06:29:54 PM PDT 24
Finished Jul 30 06:29:55 PM PDT 24
Peak memory 206876 kb
Host smart-115106af-b2d1-4ec3-bc8f-365debec07e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42253
95450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.4225395450
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.2033442621
Short name T826
Test name
Test status
Simulation time 188527646 ps
CPU time 0.89 seconds
Started Jul 30 06:29:54 PM PDT 24
Finished Jul 30 06:29:55 PM PDT 24
Peak memory 206928 kb
Host smart-a0914c4a-28dc-4b37-9552-228b73d6105b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20334
42621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.2033442621
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3360939217
Short name T1001
Test name
Test status
Simulation time 231751352 ps
CPU time 0.93 seconds
Started Jul 30 06:30:04 PM PDT 24
Finished Jul 30 06:30:05 PM PDT 24
Peak memory 206924 kb
Host smart-835dbfc9-8fa3-4882-944f-b8d345c76c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33609
39217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3360939217
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3675959041
Short name T1880
Test name
Test status
Simulation time 157273938 ps
CPU time 0.88 seconds
Started Jul 30 06:30:04 PM PDT 24
Finished Jul 30 06:30:05 PM PDT 24
Peak memory 206872 kb
Host smart-aadf9cbd-ce04-4878-a2d4-a9f03e29b482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36759
59041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3675959041
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.657750227
Short name T1285
Test name
Test status
Simulation time 154956851 ps
CPU time 0.87 seconds
Started Jul 30 06:29:57 PM PDT 24
Finished Jul 30 06:29:58 PM PDT 24
Peak memory 206976 kb
Host smart-25f50676-b3b1-476e-aa66-c648ceec553f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65775
0227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.657750227
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2007381167
Short name T2381
Test name
Test status
Simulation time 184252955 ps
CPU time 1.07 seconds
Started Jul 30 06:30:03 PM PDT 24
Finished Jul 30 06:30:04 PM PDT 24
Peak memory 206932 kb
Host smart-cb1acfbe-3951-4b60-b848-7342c2efcca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20073
81167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2007381167
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.815761456
Short name T2793
Test name
Test status
Simulation time 6712687142 ps
CPU time 195.56 seconds
Started Jul 30 06:30:01 PM PDT 24
Finished Jul 30 06:33:17 PM PDT 24
Peak memory 215376 kb
Host smart-3f8e1a93-8cd6-43af-8024-c5da85e6e46b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=815761456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.815761456
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.3118287881
Short name T2106
Test name
Test status
Simulation time 173356749 ps
CPU time 0.83 seconds
Started Jul 30 06:30:02 PM PDT 24
Finished Jul 30 06:30:03 PM PDT 24
Peak memory 206940 kb
Host smart-d65107b4-df4a-4d59-8011-7fdea52bcf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31182
87881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.3118287881
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.722458816
Short name T1731
Test name
Test status
Simulation time 185785418 ps
CPU time 0.94 seconds
Started Jul 30 06:29:58 PM PDT 24
Finished Jul 30 06:29:59 PM PDT 24
Peak memory 206912 kb
Host smart-38f28c09-62cc-401b-81b8-a88bf33a3a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72245
8816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.722458816
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.2310365966
Short name T1802
Test name
Test status
Simulation time 789331391 ps
CPU time 2.03 seconds
Started Jul 30 06:30:05 PM PDT 24
Finished Jul 30 06:30:07 PM PDT 24
Peak memory 206880 kb
Host smart-9795d9c2-1210-49fa-9f01-378eb18cd95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23103
65966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.2310365966
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.904801467
Short name T2105
Test name
Test status
Simulation time 4135738617 ps
CPU time 40.3 seconds
Started Jul 30 06:30:03 PM PDT 24
Finished Jul 30 06:30:43 PM PDT 24
Peak memory 207080 kb
Host smart-01b80452-25e8-45e0-addd-999e1b2baba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90480
1467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.904801467
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.3228838070
Short name T504
Test name
Test status
Simulation time 6686622302 ps
CPU time 46.68 seconds
Started Jul 30 06:29:47 PM PDT 24
Finished Jul 30 06:30:33 PM PDT 24
Peak memory 207152 kb
Host smart-b0e2df45-be83-4604-bcaa-7cb5837975e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228838070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.3228838070
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2247682422
Short name T2168
Test name
Test status
Simulation time 68703726 ps
CPU time 0.7 seconds
Started Jul 30 06:30:07 PM PDT 24
Finished Jul 30 06:30:08 PM PDT 24
Peak memory 207064 kb
Host smart-ffec38f1-97de-40b1-95de-0e95ec369daa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2247682422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2247682422
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.609840298
Short name T2757
Test name
Test status
Simulation time 3611524152 ps
CPU time 5.32 seconds
Started Jul 30 06:29:58 PM PDT 24
Finished Jul 30 06:30:04 PM PDT 24
Peak memory 207080 kb
Host smart-d82c42ed-74bb-4aec-be5b-880af1998b78
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609840298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_ao
n_wake_disconnect.609840298
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2805547577
Short name T1271
Test name
Test status
Simulation time 13373976131 ps
CPU time 14.67 seconds
Started Jul 30 06:29:59 PM PDT 24
Finished Jul 30 06:30:13 PM PDT 24
Peak memory 207136 kb
Host smart-bcbc9edd-994b-4705-b639-7285eb6f8ef9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805547577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2805547577
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1144474467
Short name T1771
Test name
Test status
Simulation time 23437518090 ps
CPU time 28.7 seconds
Started Jul 30 06:30:00 PM PDT 24
Finished Jul 30 06:30:29 PM PDT 24
Peak memory 207200 kb
Host smart-32479638-1385-4363-b63f-faaf1ac90937
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144474467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.1144474467
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2870910272
Short name T2610
Test name
Test status
Simulation time 245919826 ps
CPU time 1.02 seconds
Started Jul 30 06:30:06 PM PDT 24
Finished Jul 30 06:30:07 PM PDT 24
Peak memory 206948 kb
Host smart-15160b2c-2b37-422b-b564-5a046029e8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28709
10272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2870910272
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.1554781607
Short name T1122
Test name
Test status
Simulation time 165082493 ps
CPU time 0.83 seconds
Started Jul 30 06:30:04 PM PDT 24
Finished Jul 30 06:30:05 PM PDT 24
Peak memory 206952 kb
Host smart-1c712cd5-f89b-4fad-854d-77fbef771179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15547
81607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.1554781607
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.1468860372
Short name T1894
Test name
Test status
Simulation time 315017169 ps
CPU time 1.26 seconds
Started Jul 30 06:29:59 PM PDT 24
Finished Jul 30 06:30:00 PM PDT 24
Peak memory 206904 kb
Host smart-02892627-db5b-40c2-b11b-788cbaa8d470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14688
60372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.1468860372
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2763801390
Short name T2051
Test name
Test status
Simulation time 1121133726 ps
CPU time 2.88 seconds
Started Jul 30 06:30:07 PM PDT 24
Finished Jul 30 06:30:10 PM PDT 24
Peak memory 206992 kb
Host smart-2469b561-cfdd-4293-b2e3-348f1504ff9a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2763801390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2763801390
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.1644249246
Short name T1568
Test name
Test status
Simulation time 20992325857 ps
CPU time 48.39 seconds
Started Jul 30 06:30:05 PM PDT 24
Finished Jul 30 06:30:53 PM PDT 24
Peak memory 207140 kb
Host smart-6cd6b208-abc6-4a6b-be86-c130667cb7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16442
49246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.1644249246
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.2276531867
Short name T1491
Test name
Test status
Simulation time 3655661632 ps
CPU time 23.23 seconds
Started Jul 30 06:29:58 PM PDT 24
Finished Jul 30 06:30:22 PM PDT 24
Peak memory 207164 kb
Host smart-0eff6b13-98b0-46b7-9d39-036ca99ef8d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276531867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.2276531867
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.1737449670
Short name T1456
Test name
Test status
Simulation time 492435029 ps
CPU time 1.65 seconds
Started Jul 30 06:30:04 PM PDT 24
Finished Jul 30 06:30:06 PM PDT 24
Peak memory 206952 kb
Host smart-1c620eb8-f82c-4148-b395-0f09ed575b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17374
49670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.1737449670
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2858543158
Short name T581
Test name
Test status
Simulation time 141787400 ps
CPU time 0.82 seconds
Started Jul 30 06:30:00 PM PDT 24
Finished Jul 30 06:30:01 PM PDT 24
Peak memory 206876 kb
Host smart-be887b3b-5e9b-4a81-95ea-d14ed7f2c678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28585
43158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2858543158
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.3403373740
Short name T1862
Test name
Test status
Simulation time 76051766 ps
CPU time 0.73 seconds
Started Jul 30 06:30:08 PM PDT 24
Finished Jul 30 06:30:08 PM PDT 24
Peak memory 206948 kb
Host smart-2d48cee6-e4db-4fd9-a941-beaebddf7532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34033
73740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3403373740
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1086007427
Short name T1411
Test name
Test status
Simulation time 890282717 ps
CPU time 2.3 seconds
Started Jul 30 06:30:13 PM PDT 24
Finished Jul 30 06:30:15 PM PDT 24
Peak memory 207072 kb
Host smart-9a045181-aec4-4269-94b0-b1d397a09703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10860
07427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1086007427
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.4120224348
Short name T733
Test name
Test status
Simulation time 369431884 ps
CPU time 2.61 seconds
Started Jul 30 06:29:57 PM PDT 24
Finished Jul 30 06:29:59 PM PDT 24
Peak memory 206988 kb
Host smart-3d7827f7-0811-4147-8ce5-873f4076f466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41202
24348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.4120224348
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1276469699
Short name T1241
Test name
Test status
Simulation time 236673022 ps
CPU time 1.22 seconds
Started Jul 30 06:30:02 PM PDT 24
Finished Jul 30 06:30:04 PM PDT 24
Peak memory 215232 kb
Host smart-cbc696b0-c7e6-47e9-9fde-885d5705002e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1276469699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1276469699
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2347409794
Short name T796
Test name
Test status
Simulation time 169063134 ps
CPU time 0.82 seconds
Started Jul 30 06:29:59 PM PDT 24
Finished Jul 30 06:29:59 PM PDT 24
Peak memory 206916 kb
Host smart-8aea5d8f-4d38-4701-8234-d4f6488247fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23474
09794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2347409794
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1571730611
Short name T379
Test name
Test status
Simulation time 249759384 ps
CPU time 1.07 seconds
Started Jul 30 06:30:05 PM PDT 24
Finished Jul 30 06:30:06 PM PDT 24
Peak memory 206916 kb
Host smart-9d3774aa-fdb5-4abd-a335-3e753d3ac27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15717
30611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1571730611
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.2358357452
Short name T467
Test name
Test status
Simulation time 5130923524 ps
CPU time 146 seconds
Started Jul 30 06:30:02 PM PDT 24
Finished Jul 30 06:32:28 PM PDT 24
Peak memory 215288 kb
Host smart-d8a69ae5-88b1-44c6-b611-56a2982c602d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2358357452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.2358357452
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.3030108688
Short name T1399
Test name
Test status
Simulation time 7025627619 ps
CPU time 51.42 seconds
Started Jul 30 06:30:08 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 207116 kb
Host smart-0842043f-c468-4bc2-86f6-69f6b5325b63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3030108688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.3030108688
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.767602522
Short name T2557
Test name
Test status
Simulation time 229298885 ps
CPU time 0.98 seconds
Started Jul 30 06:29:58 PM PDT 24
Finished Jul 30 06:29:59 PM PDT 24
Peak memory 206904 kb
Host smart-91130397-9791-4564-aadb-39ac0e9f0adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76760
2522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.767602522
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.2868786620
Short name T2068
Test name
Test status
Simulation time 23300366366 ps
CPU time 30.62 seconds
Started Jul 30 06:30:07 PM PDT 24
Finished Jul 30 06:30:38 PM PDT 24
Peak memory 207120 kb
Host smart-0521de01-5208-483d-88b8-e4e467b83e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28687
86620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.2868786620
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.2411554856
Short name T326
Test name
Test status
Simulation time 3317312457 ps
CPU time 5.33 seconds
Started Jul 30 06:30:01 PM PDT 24
Finished Jul 30 06:30:06 PM PDT 24
Peak memory 207064 kb
Host smart-c4c1c59c-1575-4acc-bb22-f75246cd14ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24115
54856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2411554856
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.2845188120
Short name T1013
Test name
Test status
Simulation time 9679931367 ps
CPU time 268.22 seconds
Started Jul 30 06:30:05 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 215340 kb
Host smart-d8c7cb96-97bb-4bb3-9421-2a0221edd1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28451
88120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.2845188120
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.1611152450
Short name T2275
Test name
Test status
Simulation time 7592928008 ps
CPU time 212.17 seconds
Started Jul 30 06:30:14 PM PDT 24
Finished Jul 30 06:33:47 PM PDT 24
Peak memory 215324 kb
Host smart-ee9d6e13-3435-4ebc-ae7a-d4ce30efe9f9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1611152450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1611152450
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.4251656420
Short name T2688
Test name
Test status
Simulation time 242302798 ps
CPU time 1.11 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:12 PM PDT 24
Peak memory 206920 kb
Host smart-e38ae8ed-d02b-491a-bb72-0754b8abed73
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4251656420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.4251656420
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.954323635
Short name T2654
Test name
Test status
Simulation time 191769075 ps
CPU time 0.96 seconds
Started Jul 30 06:30:14 PM PDT 24
Finished Jul 30 06:30:15 PM PDT 24
Peak memory 206948 kb
Host smart-cd7a3715-13c0-4f7c-b544-b7afdeac2a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95432
3635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.954323635
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.1336354938
Short name T1690
Test name
Test status
Simulation time 7121495986 ps
CPU time 211.44 seconds
Started Jul 30 06:30:01 PM PDT 24
Finished Jul 30 06:33:32 PM PDT 24
Peak memory 215288 kb
Host smart-70743640-5533-434e-ab22-6e17b63e9895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13363
54938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.1336354938
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.3304999082
Short name T2770
Test name
Test status
Simulation time 4091537553 ps
CPU time 38.79 seconds
Started Jul 30 06:30:09 PM PDT 24
Finished Jul 30 06:30:48 PM PDT 24
Peak memory 207148 kb
Host smart-548a7c42-056f-4492-9b77-68bd02a7c997
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3304999082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.3304999082
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.3731640871
Short name T1264
Test name
Test status
Simulation time 162655247 ps
CPU time 0.89 seconds
Started Jul 30 06:30:14 PM PDT 24
Finished Jul 30 06:30:15 PM PDT 24
Peak memory 206952 kb
Host smart-83728d96-eccf-4bed-8329-9d51134bcfa9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3731640871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.3731640871
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1188191230
Short name T443
Test name
Test status
Simulation time 156637389 ps
CPU time 0.84 seconds
Started Jul 30 06:30:12 PM PDT 24
Finished Jul 30 06:30:13 PM PDT 24
Peak memory 206980 kb
Host smart-70298304-1d5d-4aaf-85be-7eb4fef26349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11881
91230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1188191230
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3026829232
Short name T2863
Test name
Test status
Simulation time 178288913 ps
CPU time 0.92 seconds
Started Jul 30 06:30:14 PM PDT 24
Finished Jul 30 06:30:15 PM PDT 24
Peak memory 206940 kb
Host smart-0c55bef9-8e8a-4240-a2b1-e68488b33260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30268
29232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3026829232
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.4229995212
Short name T816
Test name
Test status
Simulation time 244818852 ps
CPU time 1.05 seconds
Started Jul 30 06:30:01 PM PDT 24
Finished Jul 30 06:30:02 PM PDT 24
Peak memory 206672 kb
Host smart-f2065c91-be6e-4f6f-b3be-9332c689d582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42299
95212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.4229995212
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.539192245
Short name T2211
Test name
Test status
Simulation time 169545139 ps
CPU time 0.9 seconds
Started Jul 30 06:30:02 PM PDT 24
Finished Jul 30 06:30:03 PM PDT 24
Peak memory 206916 kb
Host smart-a7830a69-a2ab-494f-9ad6-f8bfdcbcf2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53919
2245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.539192245
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2298191183
Short name T1067
Test name
Test status
Simulation time 175830881 ps
CPU time 0.89 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 206916 kb
Host smart-2d0e2ee7-6fc0-495b-a02b-12fe09369104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22981
91183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2298191183
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.4029695561
Short name T1982
Test name
Test status
Simulation time 154890582 ps
CPU time 0.88 seconds
Started Jul 30 06:30:11 PM PDT 24
Finished Jul 30 06:30:12 PM PDT 24
Peak memory 206912 kb
Host smart-a53bcf5a-0b42-4ec4-a3a0-6bd6ac53b5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40296
95561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.4029695561
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.1542895663
Short name T335
Test name
Test status
Simulation time 301711808 ps
CPU time 1.16 seconds
Started Jul 30 06:30:14 PM PDT 24
Finished Jul 30 06:30:16 PM PDT 24
Peak memory 206912 kb
Host smart-1fd88606-fbae-4dd0-9349-1522e9215e48
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1542895663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1542895663
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2762795698
Short name T470
Test name
Test status
Simulation time 162829371 ps
CPU time 0.85 seconds
Started Jul 30 06:30:02 PM PDT 24
Finished Jul 30 06:30:03 PM PDT 24
Peak memory 206908 kb
Host smart-ec75ffd4-8b20-43aa-913a-a07f55eeae8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27627
95698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2762795698
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2233295605
Short name T1360
Test name
Test status
Simulation time 36969832 ps
CPU time 0.71 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 206880 kb
Host smart-c8c0bb37-f989-44d5-bcd6-561b44307345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22332
95605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2233295605
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3650362392
Short name T1315
Test name
Test status
Simulation time 18263513120 ps
CPU time 45.53 seconds
Started Jul 30 06:30:12 PM PDT 24
Finished Jul 30 06:30:58 PM PDT 24
Peak memory 215312 kb
Host smart-7b316da7-3ab5-4541-b710-6ff78c3a53b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36503
62392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3650362392
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.4042005459
Short name T1319
Test name
Test status
Simulation time 216702197 ps
CPU time 0.93 seconds
Started Jul 30 06:30:04 PM PDT 24
Finished Jul 30 06:30:05 PM PDT 24
Peak memory 206964 kb
Host smart-d7da4e19-df97-4fb8-a1a7-362ab81f100c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40420
05459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4042005459
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3375222277
Short name T2724
Test name
Test status
Simulation time 240383375 ps
CPU time 0.97 seconds
Started Jul 30 06:30:05 PM PDT 24
Finished Jul 30 06:30:06 PM PDT 24
Peak memory 206916 kb
Host smart-75d25f5f-8340-4276-a117-74f0f96f44dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33752
22277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3375222277
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.784433564
Short name T2207
Test name
Test status
Simulation time 227544717 ps
CPU time 1.01 seconds
Started Jul 30 06:30:11 PM PDT 24
Finished Jul 30 06:30:12 PM PDT 24
Peak memory 206912 kb
Host smart-4c43cbfb-0f9e-4da2-8a9f-f01a53c4909f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78443
3564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.784433564
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.2999254918
Short name T2818
Test name
Test status
Simulation time 188478173 ps
CPU time 0.87 seconds
Started Jul 30 06:30:14 PM PDT 24
Finished Jul 30 06:30:15 PM PDT 24
Peak memory 206948 kb
Host smart-c6bbdc6d-7185-458a-9086-9c2c10e212b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29992
54918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2999254918
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3053563326
Short name T1390
Test name
Test status
Simulation time 140945196 ps
CPU time 0.83 seconds
Started Jul 30 06:30:12 PM PDT 24
Finished Jul 30 06:30:13 PM PDT 24
Peak memory 206888 kb
Host smart-8a1d7ea5-a712-44c1-a544-1e92febc12d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30535
63326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3053563326
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.727204224
Short name T704
Test name
Test status
Simulation time 158938778 ps
CPU time 0.84 seconds
Started Jul 30 06:30:01 PM PDT 24
Finished Jul 30 06:30:02 PM PDT 24
Peak memory 206876 kb
Host smart-d3b727d4-cf14-4cf7-be3b-83e6ed185839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72720
4224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.727204224
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.587195808
Short name T1950
Test name
Test status
Simulation time 186061338 ps
CPU time 0.86 seconds
Started Jul 30 06:30:11 PM PDT 24
Finished Jul 30 06:30:12 PM PDT 24
Peak memory 206672 kb
Host smart-0c6d3fd0-475a-414f-aeee-7b6c8f2ff5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58719
5808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.587195808
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1488132045
Short name T1369
Test name
Test status
Simulation time 240269272 ps
CPU time 1.06 seconds
Started Jul 30 06:29:59 PM PDT 24
Finished Jul 30 06:30:00 PM PDT 24
Peak memory 206960 kb
Host smart-f68ce722-d9d6-4783-aa2b-4ef14eb33474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14881
32045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1488132045
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.197243573
Short name T2240
Test name
Test status
Simulation time 4061313149 ps
CPU time 111.23 seconds
Started Jul 30 06:30:03 PM PDT 24
Finished Jul 30 06:31:54 PM PDT 24
Peak memory 215364 kb
Host smart-801df740-a4ae-4dc2-bb91-f0dfaa5ee369
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=197243573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.197243573
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.1107946676
Short name T146
Test name
Test status
Simulation time 177450370 ps
CPU time 0.87 seconds
Started Jul 30 06:30:04 PM PDT 24
Finished Jul 30 06:30:05 PM PDT 24
Peak memory 206932 kb
Host smart-5c48515a-3cf0-45e2-905b-e3bb31fe98a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11079
46676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.1107946676
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.2865307744
Short name T1485
Test name
Test status
Simulation time 184149494 ps
CPU time 0.88 seconds
Started Jul 30 06:30:14 PM PDT 24
Finished Jul 30 06:30:15 PM PDT 24
Peak memory 206952 kb
Host smart-8ab9abc2-939f-400c-8801-2a67b455c11b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28653
07744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2865307744
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.1607513200
Short name T1432
Test name
Test status
Simulation time 1171524472 ps
CPU time 2.9 seconds
Started Jul 30 06:30:09 PM PDT 24
Finished Jul 30 06:30:12 PM PDT 24
Peak memory 207008 kb
Host smart-d9498f52-374f-4ac3-870f-ac695cdee225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16075
13200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.1607513200
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.1142165284
Short name T1662
Test name
Test status
Simulation time 5664415765 ps
CPU time 167.06 seconds
Started Jul 30 06:30:16 PM PDT 24
Finished Jul 30 06:33:03 PM PDT 24
Peak memory 215400 kb
Host smart-1e554068-e4f5-407d-954d-25d0b590ea05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11421
65284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1142165284
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.2976317047
Short name T1113
Test name
Test status
Simulation time 1063345744 ps
CPU time 21.29 seconds
Started Jul 30 06:30:01 PM PDT 24
Finished Jul 30 06:30:22 PM PDT 24
Peak memory 206992 kb
Host smart-073fc80f-a97d-4eb2-8ee2-08a2834a01a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976317047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.2976317047
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.3570431997
Short name T759
Test name
Test status
Simulation time 97185898 ps
CPU time 0.69 seconds
Started Jul 30 06:30:21 PM PDT 24
Finished Jul 30 06:30:22 PM PDT 24
Peak memory 207004 kb
Host smart-412281cb-7a6a-43e2-b25a-2a6c87eabfc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3570431997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.3570431997
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2851885127
Short name T1129
Test name
Test status
Simulation time 3504922411 ps
CPU time 5.49 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:16 PM PDT 24
Peak memory 207076 kb
Host smart-acfa47bc-930d-44f3-8166-fe7811401fad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851885127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.2851885127
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.3579530961
Short name T641
Test name
Test status
Simulation time 13353773173 ps
CPU time 16.89 seconds
Started Jul 30 06:30:07 PM PDT 24
Finished Jul 30 06:30:24 PM PDT 24
Peak memory 207200 kb
Host smart-a4125d98-4949-4db1-a25a-21718fd88f56
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579530961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.3579530961
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2203752634
Short name T1721
Test name
Test status
Simulation time 23318644119 ps
CPU time 28.93 seconds
Started Jul 30 06:30:12 PM PDT 24
Finished Jul 30 06:30:41 PM PDT 24
Peak memory 207128 kb
Host smart-1afcb5d1-648d-4f1c-8969-f7a28934fc0f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203752634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.2203752634
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2510868924
Short name T2496
Test name
Test status
Simulation time 175549949 ps
CPU time 0.94 seconds
Started Jul 30 06:30:05 PM PDT 24
Finished Jul 30 06:30:06 PM PDT 24
Peak memory 206952 kb
Host smart-437fdda2-45f0-40aa-8ca8-59e4bcd31e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25108
68924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2510868924
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.699128022
Short name T622
Test name
Test status
Simulation time 142766416 ps
CPU time 0.87 seconds
Started Jul 30 06:30:16 PM PDT 24
Finished Jul 30 06:30:17 PM PDT 24
Peak memory 206848 kb
Host smart-0809100b-f705-493b-89b9-02507144f2a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69912
8022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.699128022
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.3689600631
Short name T2047
Test name
Test status
Simulation time 312214763 ps
CPU time 1.33 seconds
Started Jul 30 06:30:07 PM PDT 24
Finished Jul 30 06:30:08 PM PDT 24
Peak memory 206968 kb
Host smart-e02389af-acf8-4622-92d1-77e1f27bf270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36896
00631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.3689600631
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1993605646
Short name T874
Test name
Test status
Simulation time 982378510 ps
CPU time 2.49 seconds
Started Jul 30 06:30:07 PM PDT 24
Finished Jul 30 06:30:09 PM PDT 24
Peak memory 207076 kb
Host smart-e4553b77-6f95-4a12-93a9-2ab431484641
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1993605646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1993605646
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.595509688
Short name T2321
Test name
Test status
Simulation time 12330664808 ps
CPU time 29.15 seconds
Started Jul 30 06:30:06 PM PDT 24
Finished Jul 30 06:30:36 PM PDT 24
Peak memory 207116 kb
Host smart-fcdce446-aac2-4fad-9cc4-2eddab7323f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59550
9688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.595509688
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.3923054136
Short name T3
Test name
Test status
Simulation time 4305497325 ps
CPU time 37.87 seconds
Started Jul 30 06:30:05 PM PDT 24
Finished Jul 30 06:30:43 PM PDT 24
Peak memory 207092 kb
Host smart-3ccb7b6a-be2c-466a-882a-7eb403a8067a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923054136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.3923054136
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3118549424
Short name T2797
Test name
Test status
Simulation time 358289197 ps
CPU time 1.38 seconds
Started Jul 30 06:30:09 PM PDT 24
Finished Jul 30 06:30:10 PM PDT 24
Peak memory 206916 kb
Host smart-f91376ce-0169-48ac-9e70-960c3adc68a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31185
49424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3118549424
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.3344425346
Short name T1844
Test name
Test status
Simulation time 146471030 ps
CPU time 0.87 seconds
Started Jul 30 06:30:05 PM PDT 24
Finished Jul 30 06:30:06 PM PDT 24
Peak memory 206896 kb
Host smart-6f368eff-26c8-404a-beba-b2b8c23816bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33444
25346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3344425346
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.2964150222
Short name T2427
Test name
Test status
Simulation time 50890334 ps
CPU time 0.74 seconds
Started Jul 30 06:30:07 PM PDT 24
Finished Jul 30 06:30:08 PM PDT 24
Peak memory 206872 kb
Host smart-57fe0df0-7ad0-4487-93fc-d832aeec6a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29641
50222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2964150222
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.2962641475
Short name T2075
Test name
Test status
Simulation time 833873553 ps
CPU time 2.2 seconds
Started Jul 30 06:30:09 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 207004 kb
Host smart-2fbf0098-3219-4095-a8e5-55d26a0bc924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29626
41475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2962641475
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.373688295
Short name T558
Test name
Test status
Simulation time 167487120 ps
CPU time 1.87 seconds
Started Jul 30 06:30:07 PM PDT 24
Finished Jul 30 06:30:09 PM PDT 24
Peak memory 206988 kb
Host smart-0a39a03f-d641-41e0-a33d-981095b123be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37368
8295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.373688295
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1630194286
Short name T481
Test name
Test status
Simulation time 196012725 ps
CPU time 1.08 seconds
Started Jul 30 06:30:07 PM PDT 24
Finished Jul 30 06:30:08 PM PDT 24
Peak memory 207056 kb
Host smart-889e691e-76f8-4df3-b2a9-6166b46eb700
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1630194286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1630194286
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1513820772
Short name T1112
Test name
Test status
Simulation time 170564384 ps
CPU time 0.93 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 206944 kb
Host smart-44f912e6-c531-401b-9583-c15072e12398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15138
20772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1513820772
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2847713491
Short name T2363
Test name
Test status
Simulation time 221141589 ps
CPU time 1.01 seconds
Started Jul 30 06:30:12 PM PDT 24
Finished Jul 30 06:30:13 PM PDT 24
Peak memory 206932 kb
Host smart-22ed1212-4bb7-4629-9c66-91c5d13b6695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28477
13491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2847713491
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.3183684155
Short name T823
Test name
Test status
Simulation time 6478800305 ps
CPU time 65.41 seconds
Started Jul 30 06:30:05 PM PDT 24
Finished Jul 30 06:31:11 PM PDT 24
Peak memory 216956 kb
Host smart-bfd95b26-708d-4977-8c4f-3ea78c0e1eed
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3183684155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3183684155
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.3556076635
Short name T424
Test name
Test status
Simulation time 7318384037 ps
CPU time 51.78 seconds
Started Jul 30 06:30:06 PM PDT 24
Finished Jul 30 06:30:58 PM PDT 24
Peak memory 207152 kb
Host smart-d07ff850-c241-4eeb-a2e3-56dea3211be9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3556076635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.3556076635
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.711345452
Short name T1423
Test name
Test status
Simulation time 182777554 ps
CPU time 0.88 seconds
Started Jul 30 06:30:08 PM PDT 24
Finished Jul 30 06:30:09 PM PDT 24
Peak memory 206876 kb
Host smart-6cbf04f5-6634-4706-ae7d-488ccc53a380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71134
5452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.711345452
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.601073711
Short name T1600
Test name
Test status
Simulation time 23375420270 ps
CPU time 29.87 seconds
Started Jul 30 06:30:12 PM PDT 24
Finished Jul 30 06:30:42 PM PDT 24
Peak memory 207096 kb
Host smart-100ed398-3e56-4902-b341-c52ddfef4e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60107
3711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.601073711
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.1962151247
Short name T2167
Test name
Test status
Simulation time 3328313647 ps
CPU time 5.04 seconds
Started Jul 30 06:30:06 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 207124 kb
Host smart-462551ae-b87a-4a15-b673-6368f8bdd6ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19621
51247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.1962151247
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.4130392485
Short name T1947
Test name
Test status
Simulation time 5913757075 ps
CPU time 166.53 seconds
Started Jul 30 06:30:06 PM PDT 24
Finished Jul 30 06:32:53 PM PDT 24
Peak memory 215404 kb
Host smart-5fa6af3c-e48b-41ed-8bd8-36e5325bdf71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41303
92485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.4130392485
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.199099391
Short name T659
Test name
Test status
Simulation time 5686583925 ps
CPU time 43.55 seconds
Started Jul 30 06:30:09 PM PDT 24
Finished Jul 30 06:30:53 PM PDT 24
Peak memory 215332 kb
Host smart-9fe1905a-43e1-45e9-bbe7-b519aa1b719b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=199099391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.199099391
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.1344474520
Short name T351
Test name
Test status
Simulation time 242973515 ps
CPU time 0.97 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 206908 kb
Host smart-b810e587-3123-4303-9b39-0be17e9d54e6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1344474520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.1344474520
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1266668398
Short name T614
Test name
Test status
Simulation time 187836216 ps
CPU time 0.92 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 206940 kb
Host smart-6e8c0ac1-222b-4c66-8471-031fcdb0db0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12666
68398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1266668398
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.829374181
Short name T1831
Test name
Test status
Simulation time 5030440079 ps
CPU time 152.39 seconds
Started Jul 30 06:30:12 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 215400 kb
Host smart-9d647bec-43e5-4732-8d4c-868fc2b51b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82937
4181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.829374181
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1324852308
Short name T2306
Test name
Test status
Simulation time 5747559620 ps
CPU time 55.87 seconds
Started Jul 30 06:30:15 PM PDT 24
Finished Jul 30 06:31:11 PM PDT 24
Peak memory 207176 kb
Host smart-4c833f10-1da8-43ee-b6fb-f32227d9891c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1324852308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1324852308
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.2099313736
Short name T1813
Test name
Test status
Simulation time 166369849 ps
CPU time 0.84 seconds
Started Jul 30 06:30:11 PM PDT 24
Finished Jul 30 06:30:12 PM PDT 24
Peak memory 206932 kb
Host smart-47573060-1f70-4267-9ba5-86a25806ab41
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2099313736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.2099313736
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1084989596
Short name T1969
Test name
Test status
Simulation time 142289277 ps
CPU time 0.88 seconds
Started Jul 30 06:30:13 PM PDT 24
Finished Jul 30 06:30:14 PM PDT 24
Peak memory 206928 kb
Host smart-0e7b3e0f-9dd0-4566-b404-8a6f0badee31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10849
89596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1084989596
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.545984439
Short name T1483
Test name
Test status
Simulation time 182935459 ps
CPU time 0.86 seconds
Started Jul 30 06:30:11 PM PDT 24
Finished Jul 30 06:30:12 PM PDT 24
Peak memory 206952 kb
Host smart-75053ce7-ba96-47e7-8303-a83a721319f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54598
4439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.545984439
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1014584176
Short name T1131
Test name
Test status
Simulation time 167639673 ps
CPU time 0.88 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 206920 kb
Host smart-dc02a895-01ef-4b98-9d5f-47f84df5f703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10145
84176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1014584176
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.661848848
Short name T279
Test name
Test status
Simulation time 185719409 ps
CPU time 0.89 seconds
Started Jul 30 06:30:09 PM PDT 24
Finished Jul 30 06:30:10 PM PDT 24
Peak memory 206948 kb
Host smart-4adfa4c2-6c64-49c2-b73a-11aae581b153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66184
8848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.661848848
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2149123261
Short name T1846
Test name
Test status
Simulation time 179355522 ps
CPU time 0.87 seconds
Started Jul 30 06:30:11 PM PDT 24
Finished Jul 30 06:30:12 PM PDT 24
Peak memory 206900 kb
Host smart-abd12ce0-cb35-4314-bbb5-df9c9bcfc829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21491
23261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2149123261
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.361843671
Short name T1311
Test name
Test status
Simulation time 268637459 ps
CPU time 1.1 seconds
Started Jul 30 06:30:13 PM PDT 24
Finished Jul 30 06:30:14 PM PDT 24
Peak memory 206932 kb
Host smart-79adc097-cd4f-45aa-bb6d-4b2abb75ee17
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=361843671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.361843671
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3686168521
Short name T506
Test name
Test status
Simulation time 139526993 ps
CPU time 0.83 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 206864 kb
Host smart-42790b75-d4cf-4014-84e4-c0d3756b24ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36861
68521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3686168521
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1627188731
Short name T27
Test name
Test status
Simulation time 32313353 ps
CPU time 0.7 seconds
Started Jul 30 06:30:16 PM PDT 24
Finished Jul 30 06:30:17 PM PDT 24
Peak memory 206952 kb
Host smart-4a8419bd-e872-499c-9e6a-944f15b33781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16271
88731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1627188731
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.389687772
Short name T252
Test name
Test status
Simulation time 12709833365 ps
CPU time 31.07 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:42 PM PDT 24
Peak memory 215400 kb
Host smart-75042022-a310-4301-9f1a-3f8de073af6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38968
7772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.389687772
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2941807156
Short name T2143
Test name
Test status
Simulation time 187628095 ps
CPU time 0.93 seconds
Started Jul 30 06:30:12 PM PDT 24
Finished Jul 30 06:30:13 PM PDT 24
Peak memory 206920 kb
Host smart-c57f251d-dcf5-4170-8711-3d04ec1b879e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29418
07156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2941807156
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.560333177
Short name T743
Test name
Test status
Simulation time 242927126 ps
CPU time 0.96 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:12 PM PDT 24
Peak memory 206908 kb
Host smart-cc2eb5bc-46db-4be0-bf2f-ef3b0fd96916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56033
3177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.560333177
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.2082798811
Short name T1070
Test name
Test status
Simulation time 188126822 ps
CPU time 0.94 seconds
Started Jul 30 06:30:12 PM PDT 24
Finished Jul 30 06:30:14 PM PDT 24
Peak memory 206916 kb
Host smart-ffb2985e-4a51-4bce-a7af-f2fd8c2e0205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20827
98811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.2082798811
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2610353477
Short name T273
Test name
Test status
Simulation time 232053363 ps
CPU time 1.06 seconds
Started Jul 30 06:30:11 PM PDT 24
Finished Jul 30 06:30:12 PM PDT 24
Peak memory 206904 kb
Host smart-4e977849-798f-41f1-a00d-9821463f0110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26103
53477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2610353477
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3851832391
Short name T61
Test name
Test status
Simulation time 174316056 ps
CPU time 0.85 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 206876 kb
Host smart-01ea773b-e133-494d-ac44-1d7957d61592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38518
32391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3851832391
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.4256519135
Short name T983
Test name
Test status
Simulation time 168832943 ps
CPU time 0.84 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 206904 kb
Host smart-183fc56f-cc38-4318-a1a7-b636a257b610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42565
19135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.4256519135
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2892950969
Short name T1354
Test name
Test status
Simulation time 165370446 ps
CPU time 0.84 seconds
Started Jul 30 06:30:11 PM PDT 24
Finished Jul 30 06:30:12 PM PDT 24
Peak memory 206920 kb
Host smart-e699d088-879c-41d0-8668-8a26f4b59fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28929
50969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2892950969
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1260387306
Short name T149
Test name
Test status
Simulation time 203800333 ps
CPU time 1.01 seconds
Started Jul 30 06:30:10 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 206904 kb
Host smart-0b36e1d1-d25c-4c00-87cc-6dcc87223d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12603
87306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1260387306
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.3080284804
Short name T1646
Test name
Test status
Simulation time 4423141060 ps
CPU time 33.71 seconds
Started Jul 30 06:30:12 PM PDT 24
Finished Jul 30 06:30:45 PM PDT 24
Peak memory 216948 kb
Host smart-006f28d9-49b8-49ec-a75d-e4bca2b2f3a5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3080284804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.3080284804
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2442767977
Short name T1545
Test name
Test status
Simulation time 159088201 ps
CPU time 0.92 seconds
Started Jul 30 06:30:11 PM PDT 24
Finished Jul 30 06:30:12 PM PDT 24
Peak memory 206948 kb
Host smart-da298caf-1249-49e8-8655-e09566e8db52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24427
67977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2442767977
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3025330866
Short name T2157
Test name
Test status
Simulation time 243864108 ps
CPU time 0.97 seconds
Started Jul 30 06:30:13 PM PDT 24
Finished Jul 30 06:30:15 PM PDT 24
Peak memory 206916 kb
Host smart-cb9dcc21-919f-4fca-b501-2979d0039b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30253
30866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3025330866
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.190573571
Short name T355
Test name
Test status
Simulation time 1257973872 ps
CPU time 3.14 seconds
Started Jul 30 06:30:17 PM PDT 24
Finished Jul 30 06:30:20 PM PDT 24
Peak memory 207032 kb
Host smart-519c9b8e-c32a-4abb-b9a2-859e8f4ace8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19057
3571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.190573571
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.2378105527
Short name T2191
Test name
Test status
Simulation time 4599835700 ps
CPU time 35.42 seconds
Started Jul 30 06:30:14 PM PDT 24
Finished Jul 30 06:30:50 PM PDT 24
Peak memory 216596 kb
Host smart-720e9bd2-d464-447d-b265-81881d251a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23781
05527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.2378105527
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.785957950
Short name T703
Test name
Test status
Simulation time 2075563390 ps
CPU time 17.82 seconds
Started Jul 30 06:30:11 PM PDT 24
Finished Jul 30 06:30:29 PM PDT 24
Peak memory 207048 kb
Host smart-24f12fb6-112d-4a00-9ce3-707298151a63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785957950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_host
_handshake.785957950
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.3189966099
Short name T1685
Test name
Test status
Simulation time 29188474 ps
CPU time 0.67 seconds
Started Jul 30 06:30:22 PM PDT 24
Finished Jul 30 06:30:23 PM PDT 24
Peak memory 207064 kb
Host smart-ca0ba27c-668d-423a-841b-9c63ea3cede3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3189966099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.3189966099
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.687697356
Short name T1237
Test name
Test status
Simulation time 3840121604 ps
CPU time 6 seconds
Started Jul 30 06:30:17 PM PDT 24
Finished Jul 30 06:30:23 PM PDT 24
Peak memory 207052 kb
Host smart-54d7361e-a0a7-44dd-91e1-27d73d3df3c7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687697356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_ao
n_wake_disconnect.687697356
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2204131095
Short name T1634
Test name
Test status
Simulation time 13387743555 ps
CPU time 15.52 seconds
Started Jul 30 06:30:15 PM PDT 24
Finished Jul 30 06:30:30 PM PDT 24
Peak memory 207128 kb
Host smart-7f817f96-3f66-4567-8c1a-07b2a6c4f7f9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204131095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2204131095
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.3222253111
Short name T1017
Test name
Test status
Simulation time 23373280942 ps
CPU time 32 seconds
Started Jul 30 06:30:17 PM PDT 24
Finished Jul 30 06:30:49 PM PDT 24
Peak memory 207156 kb
Host smart-da1d7220-ad24-492b-a5f3-0484314676d0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222253111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.3222253111
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.4175284258
Short name T2714
Test name
Test status
Simulation time 145997349 ps
CPU time 0.8 seconds
Started Jul 30 06:30:15 PM PDT 24
Finished Jul 30 06:30:16 PM PDT 24
Peak memory 206948 kb
Host smart-c774d6c2-f8fa-4407-8915-fc5b9f1f4ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41752
84258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.4175284258
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3713484809
Short name T1773
Test name
Test status
Simulation time 152882665 ps
CPU time 0.85 seconds
Started Jul 30 06:30:22 PM PDT 24
Finished Jul 30 06:30:23 PM PDT 24
Peak memory 206868 kb
Host smart-4560f987-65d0-450d-8b03-10ab8762336a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37134
84809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3713484809
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.738671663
Short name T2701
Test name
Test status
Simulation time 217126417 ps
CPU time 1.1 seconds
Started Jul 30 06:30:15 PM PDT 24
Finished Jul 30 06:30:16 PM PDT 24
Peak memory 206920 kb
Host smart-1fec2b54-0842-4424-b4f7-8c23badd392c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73867
1663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.738671663
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.2279447340
Short name T991
Test name
Test status
Simulation time 1000311721 ps
CPU time 2.49 seconds
Started Jul 30 06:30:16 PM PDT 24
Finished Jul 30 06:30:18 PM PDT 24
Peak memory 206968 kb
Host smart-19e9b1ba-67f5-4338-a3b2-ac21a9563ba2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2279447340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.2279447340
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3271891648
Short name T309
Test name
Test status
Simulation time 21224649088 ps
CPU time 44.53 seconds
Started Jul 30 06:30:14 PM PDT 24
Finished Jul 30 06:30:58 PM PDT 24
Peak memory 207132 kb
Host smart-8b03b7e8-883f-4622-ab34-8a74f97b333a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32718
91648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3271891648
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.1543253681
Short name T852
Test name
Test status
Simulation time 2254528804 ps
CPU time 14.13 seconds
Started Jul 30 06:30:15 PM PDT 24
Finished Jul 30 06:30:29 PM PDT 24
Peak memory 207096 kb
Host smart-43f886e6-96d0-40f5-88c3-717454891876
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543253681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.1543253681
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3553657497
Short name T2194
Test name
Test status
Simulation time 482718425 ps
CPU time 1.48 seconds
Started Jul 30 06:30:12 PM PDT 24
Finished Jul 30 06:30:14 PM PDT 24
Peak memory 206892 kb
Host smart-f49131c4-fe0c-4a1c-a748-80a52d3b11eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35536
57497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3553657497
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2438503343
Short name T2283
Test name
Test status
Simulation time 157184636 ps
CPU time 0.83 seconds
Started Jul 30 06:30:16 PM PDT 24
Finished Jul 30 06:30:17 PM PDT 24
Peak memory 206948 kb
Host smart-5e21c264-b3fb-42f5-a883-615a4b5b3692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24385
03343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2438503343
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.444509789
Short name T2711
Test name
Test status
Simulation time 108052496 ps
CPU time 0.78 seconds
Started Jul 30 06:30:17 PM PDT 24
Finished Jul 30 06:30:17 PM PDT 24
Peak memory 206884 kb
Host smart-aa2f956e-aa74-4015-bb72-6c7c81dd8e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44450
9789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.444509789
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2020206262
Short name T2780
Test name
Test status
Simulation time 861663364 ps
CPU time 2.51 seconds
Started Jul 30 06:30:14 PM PDT 24
Finished Jul 30 06:30:16 PM PDT 24
Peak memory 207024 kb
Host smart-9ccae2df-f6ea-473a-86bd-7e387306dbd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20202
06262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2020206262
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.1120425220
Short name T1688
Test name
Test status
Simulation time 293920087 ps
CPU time 1.9 seconds
Started Jul 30 06:30:16 PM PDT 24
Finished Jul 30 06:30:18 PM PDT 24
Peak memory 206996 kb
Host smart-6bc47d83-cc49-4f9a-909e-ad671e600160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11204
25220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.1120425220
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.2639315884
Short name T1266
Test name
Test status
Simulation time 194467515 ps
CPU time 1.06 seconds
Started Jul 30 06:30:19 PM PDT 24
Finished Jul 30 06:30:20 PM PDT 24
Peak memory 207056 kb
Host smart-7d7870fb-32bb-4997-8edf-b1c51a524496
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2639315884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.2639315884
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3584658420
Short name T2512
Test name
Test status
Simulation time 135829691 ps
CPU time 0.82 seconds
Started Jul 30 06:30:14 PM PDT 24
Finished Jul 30 06:30:15 PM PDT 24
Peak memory 206900 kb
Host smart-ab7ef680-d48e-4fd8-bde6-5ab2be3ec407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35846
58420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3584658420
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1237947586
Short name T2590
Test name
Test status
Simulation time 209466617 ps
CPU time 0.96 seconds
Started Jul 30 06:30:17 PM PDT 24
Finished Jul 30 06:30:18 PM PDT 24
Peak memory 206904 kb
Host smart-b028ae06-4a18-4596-bd84-c6b234b74378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12379
47586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1237947586
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.1074137488
Short name T2147
Test name
Test status
Simulation time 6464788943 ps
CPU time 65.31 seconds
Started Jul 30 06:30:14 PM PDT 24
Finished Jul 30 06:31:20 PM PDT 24
Peak memory 215376 kb
Host smart-d5672e1a-e4e8-4441-aadd-7a2b20af9475
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1074137488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.1074137488
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.2073960962
Short name T2604
Test name
Test status
Simulation time 10448146937 ps
CPU time 71.63 seconds
Started Jul 30 06:30:22 PM PDT 24
Finished Jul 30 06:31:34 PM PDT 24
Peak memory 206720 kb
Host smart-25964e21-7f34-4f74-aa57-b99acadd334e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2073960962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.2073960962
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3081877119
Short name T818
Test name
Test status
Simulation time 219615975 ps
CPU time 0.98 seconds
Started Jul 30 06:30:22 PM PDT 24
Finished Jul 30 06:30:23 PM PDT 24
Peak memory 206892 kb
Host smart-78116689-0ffd-46e1-8e71-9c4cd3970e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30818
77119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3081877119
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3023079597
Short name T1334
Test name
Test status
Simulation time 23316431130 ps
CPU time 35.2 seconds
Started Jul 30 06:30:13 PM PDT 24
Finished Jul 30 06:30:48 PM PDT 24
Peak memory 207124 kb
Host smart-2b61a52c-dad7-4904-8cbc-27d19f398817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30230
79597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3023079597
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.981276431
Short name T2353
Test name
Test status
Simulation time 3258251222 ps
CPU time 4.74 seconds
Started Jul 30 06:30:21 PM PDT 24
Finished Jul 30 06:30:26 PM PDT 24
Peak memory 207048 kb
Host smart-beb74051-3110-4f7b-99ef-ea0e51fc64ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98127
6431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.981276431
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.1978334756
Short name T2606
Test name
Test status
Simulation time 9537767243 ps
CPU time 272.73 seconds
Started Jul 30 06:30:20 PM PDT 24
Finished Jul 30 06:34:53 PM PDT 24
Peak memory 215328 kb
Host smart-7e43fcfd-e4c0-4e8b-8428-f36f20054dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19783
34756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.1978334756
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1341009791
Short name T36
Test name
Test status
Simulation time 6048944217 ps
CPU time 62.24 seconds
Started Jul 30 06:30:19 PM PDT 24
Finished Jul 30 06:31:22 PM PDT 24
Peak memory 215300 kb
Host smart-44b9a140-c7b8-42b5-a504-a061d67c2d5d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1341009791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1341009791
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.3423965147
Short name T2580
Test name
Test status
Simulation time 235240026 ps
CPU time 1.05 seconds
Started Jul 30 06:30:22 PM PDT 24
Finished Jul 30 06:30:24 PM PDT 24
Peak memory 206920 kb
Host smart-30181ca5-f887-4b16-8c44-11d4e4c9e0b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3423965147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.3423965147
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.668782149
Short name T667
Test name
Test status
Simulation time 210285599 ps
CPU time 0.96 seconds
Started Jul 30 06:30:19 PM PDT 24
Finished Jul 30 06:30:20 PM PDT 24
Peak memory 206920 kb
Host smart-196e74ec-14aa-4770-bb42-531c53b6e3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66878
2149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.668782149
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.90616023
Short name T373
Test name
Test status
Simulation time 5842703289 ps
CPU time 45.57 seconds
Started Jul 30 06:30:22 PM PDT 24
Finished Jul 30 06:31:07 PM PDT 24
Peak memory 216904 kb
Host smart-999f5a90-13f7-4d2f-aaf9-0600b792c0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90616
023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.90616023
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3432734831
Short name T1766
Test name
Test status
Simulation time 7434586508 ps
CPU time 72.52 seconds
Started Jul 30 06:30:17 PM PDT 24
Finished Jul 30 06:31:30 PM PDT 24
Peak memory 207172 kb
Host smart-7900b62a-3edd-4d6a-a2ae-149bd656c50f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3432734831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3432734831
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.1500752028
Short name T634
Test name
Test status
Simulation time 161183885 ps
CPU time 0.86 seconds
Started Jul 30 06:30:17 PM PDT 24
Finished Jul 30 06:30:18 PM PDT 24
Peak memory 206940 kb
Host smart-ff4f2961-3e34-4c97-94a0-af1628b2272b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1500752028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.1500752028
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1836354340
Short name T729
Test name
Test status
Simulation time 154234939 ps
CPU time 0.86 seconds
Started Jul 30 06:30:19 PM PDT 24
Finished Jul 30 06:30:20 PM PDT 24
Peak memory 206924 kb
Host smart-59a28818-ee06-4e4c-84ad-4525b388a01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18363
54340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1836354340
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1434828705
Short name T2359
Test name
Test status
Simulation time 216512226 ps
CPU time 0.93 seconds
Started Jul 30 06:30:19 PM PDT 24
Finished Jul 30 06:30:20 PM PDT 24
Peak memory 206984 kb
Host smart-32ea3bf6-96b8-4b93-a8eb-3f886ee0cda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14348
28705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1434828705
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1891644716
Short name T2480
Test name
Test status
Simulation time 174946038 ps
CPU time 0.87 seconds
Started Jul 30 06:30:19 PM PDT 24
Finished Jul 30 06:30:20 PM PDT 24
Peak memory 206920 kb
Host smart-392e1fcf-cf6d-4905-a198-ab2eb47e5e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18916
44716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1891644716
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3890957246
Short name T1425
Test name
Test status
Simulation time 174246455 ps
CPU time 0.91 seconds
Started Jul 30 06:30:21 PM PDT 24
Finished Jul 30 06:30:22 PM PDT 24
Peak memory 206912 kb
Host smart-2cb5501f-0b1c-455c-bfe4-b94d66473b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38909
57246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3890957246
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.236580107
Short name T1734
Test name
Test status
Simulation time 167650117 ps
CPU time 0.88 seconds
Started Jul 30 06:30:20 PM PDT 24
Finished Jul 30 06:30:21 PM PDT 24
Peak memory 206908 kb
Host smart-e9ca6a9d-6d7b-4240-88db-9dfe0afdd2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23658
0107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.236580107
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.3595814202
Short name T521
Test name
Test status
Simulation time 253152274 ps
CPU time 1.02 seconds
Started Jul 30 06:30:18 PM PDT 24
Finished Jul 30 06:30:19 PM PDT 24
Peak memory 206940 kb
Host smart-cf131a77-3efd-47aa-a5b0-8b73a657809b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3595814202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.3595814202
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3868899795
Short name T1328
Test name
Test status
Simulation time 158774167 ps
CPU time 0.82 seconds
Started Jul 30 06:30:22 PM PDT 24
Finished Jul 30 06:30:23 PM PDT 24
Peak memory 206556 kb
Host smart-f3a9d138-17e5-4940-a318-685e5872cf6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38688
99795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3868899795
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.595305073
Short name T2435
Test name
Test status
Simulation time 40324743 ps
CPU time 0.69 seconds
Started Jul 30 06:30:20 PM PDT 24
Finished Jul 30 06:30:21 PM PDT 24
Peak memory 206952 kb
Host smart-56dcb0d3-a608-4455-ada9-2b651cd78ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59530
5073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.595305073
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3197480413
Short name T1689
Test name
Test status
Simulation time 22492958088 ps
CPU time 53.55 seconds
Started Jul 30 06:30:19 PM PDT 24
Finished Jul 30 06:31:12 PM PDT 24
Peak memory 215308 kb
Host smart-25ddc87c-a1b9-4bf8-8e5e-ebaf9ae82130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31974
80413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3197480413
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3413986267
Short name T1872
Test name
Test status
Simulation time 174843046 ps
CPU time 0.95 seconds
Started Jul 30 06:30:19 PM PDT 24
Finished Jul 30 06:30:20 PM PDT 24
Peak memory 206956 kb
Host smart-4479d7ce-f3d0-4368-bffb-7d8aec03a073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34139
86267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3413986267
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3877970896
Short name T1028
Test name
Test status
Simulation time 250302376 ps
CPU time 0.95 seconds
Started Jul 30 06:30:18 PM PDT 24
Finished Jul 30 06:30:19 PM PDT 24
Peak memory 206916 kb
Host smart-2e49e7a0-bff0-4e6c-bc4e-c4b44b04412d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38779
70896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3877970896
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.2178850512
Short name T1125
Test name
Test status
Simulation time 161905012 ps
CPU time 0.85 seconds
Started Jul 30 06:30:17 PM PDT 24
Finished Jul 30 06:30:18 PM PDT 24
Peak memory 206924 kb
Host smart-df4bbccb-94e6-48fd-a521-ecb629fab03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21788
50512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.2178850512
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.39359552
Short name T2259
Test name
Test status
Simulation time 177789300 ps
CPU time 1 seconds
Started Jul 30 06:30:23 PM PDT 24
Finished Jul 30 06:30:24 PM PDT 24
Peak memory 206912 kb
Host smart-d1917f91-74f4-43fb-b8af-f231dd9da18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39359
552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.39359552
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3078308322
Short name T935
Test name
Test status
Simulation time 186161478 ps
CPU time 0.87 seconds
Started Jul 30 06:30:25 PM PDT 24
Finished Jul 30 06:30:26 PM PDT 24
Peak memory 206944 kb
Host smart-1c889830-d294-4a12-888d-ef17c05eb488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30783
08322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3078308322
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1166098282
Short name T572
Test name
Test status
Simulation time 174311200 ps
CPU time 0.88 seconds
Started Jul 30 06:30:21 PM PDT 24
Finished Jul 30 06:30:22 PM PDT 24
Peak memory 206900 kb
Host smart-0dfaff3f-3337-4ef8-aad5-dcaca3135e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11660
98282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1166098282
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2404858008
Short name T448
Test name
Test status
Simulation time 150020640 ps
CPU time 0.88 seconds
Started Jul 30 06:30:23 PM PDT 24
Finished Jul 30 06:30:24 PM PDT 24
Peak memory 206924 kb
Host smart-4fef10d0-bb6b-48cb-9a05-8d0eb3c9f599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24048
58008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2404858008
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1925811613
Short name T882
Test name
Test status
Simulation time 230972658 ps
CPU time 1.02 seconds
Started Jul 30 06:30:24 PM PDT 24
Finished Jul 30 06:30:26 PM PDT 24
Peak memory 206908 kb
Host smart-6ac1910f-059f-4df3-97d3-7697e0a9c016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19258
11613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1925811613
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.1432601628
Short name T2439
Test name
Test status
Simulation time 4579486176 ps
CPU time 45.96 seconds
Started Jul 30 06:30:25 PM PDT 24
Finished Jul 30 06:31:11 PM PDT 24
Peak memory 216488 kb
Host smart-eabe7f93-d86d-442c-9551-c2133a83df46
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1432601628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.1432601628
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1926055355
Short name T1539
Test name
Test status
Simulation time 147079043 ps
CPU time 0.83 seconds
Started Jul 30 06:30:24 PM PDT 24
Finished Jul 30 06:30:25 PM PDT 24
Peak memory 206904 kb
Host smart-cb8fb824-524a-43c4-81a4-9299680c8f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19260
55355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1926055355
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2812440777
Short name T700
Test name
Test status
Simulation time 184714335 ps
CPU time 0.92 seconds
Started Jul 30 06:30:25 PM PDT 24
Finished Jul 30 06:30:26 PM PDT 24
Peak memory 206928 kb
Host smart-d6101fa6-c7ec-44da-8a7d-477b6219a22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28124
40777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2812440777
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.2695968137
Short name T2449
Test name
Test status
Simulation time 1098612143 ps
CPU time 2.68 seconds
Started Jul 30 06:30:24 PM PDT 24
Finished Jul 30 06:30:26 PM PDT 24
Peak memory 206956 kb
Host smart-dcd05fef-1510-44ce-80d7-ee761f6091ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26959
68137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.2695968137
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.3634703831
Short name T1429
Test name
Test status
Simulation time 6281382661 ps
CPU time 180.08 seconds
Started Jul 30 06:30:26 PM PDT 24
Finished Jul 30 06:33:26 PM PDT 24
Peak memory 215332 kb
Host smart-a5aa8776-b8ee-47ee-9285-09867f20d77e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36347
03831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.3634703831
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.447364296
Short name T734
Test name
Test status
Simulation time 2194103645 ps
CPU time 15.32 seconds
Started Jul 30 06:30:12 PM PDT 24
Finished Jul 30 06:30:28 PM PDT 24
Peak memory 207088 kb
Host smart-96f9813b-f901-4919-a54c-e99431494fda
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447364296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_host
_handshake.447364296
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.3258731164
Short name T362
Test name
Test status
Simulation time 32640547 ps
CPU time 0.63 seconds
Started Jul 30 06:30:37 PM PDT 24
Finished Jul 30 06:30:38 PM PDT 24
Peak memory 207020 kb
Host smart-141e7fe6-a41b-4a85-843d-f6c84fba1153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3258731164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3258731164
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.616476294
Short name T2166
Test name
Test status
Simulation time 3494081550 ps
CPU time 5.55 seconds
Started Jul 30 06:30:24 PM PDT 24
Finished Jul 30 06:30:30 PM PDT 24
Peak memory 207076 kb
Host smart-cf9eebfe-cfc2-452f-969d-fa9c00c2cc3b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616476294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_ao
n_wake_disconnect.616476294
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.1358464129
Short name T672
Test name
Test status
Simulation time 13380335047 ps
CPU time 16.66 seconds
Started Jul 30 06:30:25 PM PDT 24
Finished Jul 30 06:30:42 PM PDT 24
Peak memory 207120 kb
Host smart-73316d98-f357-4881-be26-783366281215
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358464129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1358464129
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.157749582
Short name T2529
Test name
Test status
Simulation time 23336344331 ps
CPU time 29.78 seconds
Started Jul 30 06:30:22 PM PDT 24
Finished Jul 30 06:30:52 PM PDT 24
Peak memory 207160 kb
Host smart-8dba7db2-3d12-478c-9733-3d1fee7de86c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157749582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_ao
n_wake_resume.157749582
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.893593050
Short name T559
Test name
Test status
Simulation time 156960475 ps
CPU time 0.88 seconds
Started Jul 30 06:30:24 PM PDT 24
Finished Jul 30 06:30:25 PM PDT 24
Peak memory 206904 kb
Host smart-e65eaddf-bc96-47f5-afae-1ba240c02951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89359
3050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.893593050
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.2422157844
Short name T371
Test name
Test status
Simulation time 159244943 ps
CPU time 0.83 seconds
Started Jul 30 06:30:21 PM PDT 24
Finished Jul 30 06:30:22 PM PDT 24
Peak memory 206868 kb
Host smart-34105dcd-bb19-47b5-8a83-94c9eacc0461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24221
57844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.2422157844
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1026677631
Short name T1537
Test name
Test status
Simulation time 408095700 ps
CPU time 1.36 seconds
Started Jul 30 06:30:25 PM PDT 24
Finished Jul 30 06:30:26 PM PDT 24
Peak memory 206912 kb
Host smart-7f9bf004-dc7e-47f7-ab27-07f19fc4faf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10266
77631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1026677631
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2462466334
Short name T560
Test name
Test status
Simulation time 416995268 ps
CPU time 1.32 seconds
Started Jul 30 06:30:24 PM PDT 24
Finished Jul 30 06:30:25 PM PDT 24
Peak memory 206960 kb
Host smart-b91c2474-581f-483b-a38d-1a83d084cd0d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2462466334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2462466334
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.737593282
Short name T1395
Test name
Test status
Simulation time 1129874796 ps
CPU time 25.46 seconds
Started Jul 30 06:30:25 PM PDT 24
Finished Jul 30 06:30:51 PM PDT 24
Peak memory 206984 kb
Host smart-cb6aca0e-36f9-47b7-9208-7edb14e78454
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737593282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.737593282
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.4126443947
Short name T798
Test name
Test status
Simulation time 290119684 ps
CPU time 1.15 seconds
Started Jul 30 06:30:27 PM PDT 24
Finished Jul 30 06:30:28 PM PDT 24
Peak memory 206876 kb
Host smart-6a444a67-cdec-4a86-bcfa-bac92e6ac2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41264
43947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.4126443947
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.1566354260
Short name T2445
Test name
Test status
Simulation time 139506284 ps
CPU time 0.84 seconds
Started Jul 30 06:30:49 PM PDT 24
Finished Jul 30 06:30:50 PM PDT 24
Peak memory 206920 kb
Host smart-7a343886-3d69-4438-8000-10e069812556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15663
54260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1566354260
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2377366542
Short name T1478
Test name
Test status
Simulation time 32183261 ps
CPU time 0.69 seconds
Started Jul 30 06:30:26 PM PDT 24
Finished Jul 30 06:30:27 PM PDT 24
Peak memory 206864 kb
Host smart-89f77cc1-1d08-4246-a992-70c4dbc7805f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23773
66542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2377366542
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.3772225740
Short name T2198
Test name
Test status
Simulation time 1074653962 ps
CPU time 3.03 seconds
Started Jul 30 06:30:30 PM PDT 24
Finished Jul 30 06:30:33 PM PDT 24
Peak memory 207024 kb
Host smart-1062dea4-2c69-4ce4-9461-cbef5b75779b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37722
25740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.3772225740
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1172473019
Short name T1521
Test name
Test status
Simulation time 419454781 ps
CPU time 2.96 seconds
Started Jul 30 06:30:28 PM PDT 24
Finished Jul 30 06:30:31 PM PDT 24
Peak memory 206960 kb
Host smart-a655e37a-c559-4efb-b6a6-55bbffed7187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11724
73019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1172473019
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1520116500
Short name T1487
Test name
Test status
Simulation time 194195269 ps
CPU time 1.01 seconds
Started Jul 30 06:30:28 PM PDT 24
Finished Jul 30 06:30:29 PM PDT 24
Peak memory 215200 kb
Host smart-a41e672f-85bd-4a11-8e7d-226907e97880
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1520116500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1520116500
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.717523943
Short name T2329
Test name
Test status
Simulation time 185855989 ps
CPU time 0.94 seconds
Started Jul 30 06:30:28 PM PDT 24
Finished Jul 30 06:30:29 PM PDT 24
Peak memory 206872 kb
Host smart-19765940-1952-4a6d-94f6-f20640c05124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71752
3943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.717523943
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3026893694
Short name T381
Test name
Test status
Simulation time 159856263 ps
CPU time 0.88 seconds
Started Jul 30 06:30:28 PM PDT 24
Finished Jul 30 06:30:29 PM PDT 24
Peak memory 206948 kb
Host smart-2e66c665-c78c-45b2-ac8d-6bb857c934f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30268
93694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3026893694
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.1507259412
Short name T1477
Test name
Test status
Simulation time 10221909095 ps
CPU time 76.9 seconds
Started Jul 30 06:30:27 PM PDT 24
Finished Jul 30 06:31:44 PM PDT 24
Peak memory 215348 kb
Host smart-c86ed8b3-ee19-4748-9ac5-ef73245c443b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1507259412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.1507259412
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.741948814
Short name T2817
Test name
Test status
Simulation time 5122400428 ps
CPU time 33.1 seconds
Started Jul 30 06:30:27 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 207108 kb
Host smart-a42a95ad-7c53-4459-9ed1-e309be4db12f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=741948814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.741948814
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.784683185
Short name T2123
Test name
Test status
Simulation time 238441975 ps
CPU time 0.97 seconds
Started Jul 30 06:30:28 PM PDT 24
Finished Jul 30 06:30:29 PM PDT 24
Peak memory 206884 kb
Host smart-8b454436-3625-4c29-aca8-f86a30d8e833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78468
3185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.784683185
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.1774054536
Short name T836
Test name
Test status
Simulation time 23350741414 ps
CPU time 31.55 seconds
Started Jul 30 06:30:28 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 207164 kb
Host smart-d230f312-4874-4da0-9954-213fffa8a6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17740
54536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.1774054536
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.3827318160
Short name T1238
Test name
Test status
Simulation time 3322474473 ps
CPU time 5.49 seconds
Started Jul 30 06:30:27 PM PDT 24
Finished Jul 30 06:30:33 PM PDT 24
Peak memory 207048 kb
Host smart-2066a9ef-1e2b-4696-a5a1-659ef208b692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38273
18160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3827318160
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.3451545355
Short name T2428
Test name
Test status
Simulation time 4680466928 ps
CPU time 133.69 seconds
Started Jul 30 06:30:27 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 215388 kb
Host smart-d786599f-3030-447f-a738-6d0c3ffcb65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34515
45355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.3451545355
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1015146707
Short name T2491
Test name
Test status
Simulation time 4122575678 ps
CPU time 32.44 seconds
Started Jul 30 06:30:28 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 207120 kb
Host smart-d97d38e7-0c10-46a2-aaed-b969b035adb0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1015146707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1015146707
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.2101149885
Short name T2097
Test name
Test status
Simulation time 310465632 ps
CPU time 1.06 seconds
Started Jul 30 06:30:29 PM PDT 24
Finished Jul 30 06:30:30 PM PDT 24
Peak memory 206944 kb
Host smart-de595acc-fe3f-42ea-84cc-37d655691b7f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2101149885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.2101149885
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1724081805
Short name T997
Test name
Test status
Simulation time 248351399 ps
CPU time 1 seconds
Started Jul 30 06:30:27 PM PDT 24
Finished Jul 30 06:30:28 PM PDT 24
Peak memory 206904 kb
Host smart-9c76085d-369e-46d3-9fb8-ccf5b8d7a259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17240
81805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1724081805
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.2337856276
Short name T1995
Test name
Test status
Simulation time 3438850880 ps
CPU time 103.31 seconds
Started Jul 30 06:30:28 PM PDT 24
Finished Jul 30 06:32:12 PM PDT 24
Peak memory 215328 kb
Host smart-32cb4854-807c-46e1-bac6-dd2bbecd2eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23378
56276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.2337856276
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1854490111
Short name T550
Test name
Test status
Simulation time 6747094804 ps
CPU time 200.62 seconds
Started Jul 30 06:30:32 PM PDT 24
Finished Jul 30 06:33:53 PM PDT 24
Peak memory 215284 kb
Host smart-718745be-3bf2-4b43-b556-5dfef5761580
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1854490111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1854490111
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.23725178
Short name T2458
Test name
Test status
Simulation time 148278521 ps
CPU time 0.87 seconds
Started Jul 30 06:30:31 PM PDT 24
Finished Jul 30 06:30:32 PM PDT 24
Peak memory 206956 kb
Host smart-649e3bc4-a986-485e-ab8c-24ab636a96cd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=23725178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.23725178
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3723447622
Short name T2179
Test name
Test status
Simulation time 150132662 ps
CPU time 0.87 seconds
Started Jul 30 06:30:31 PM PDT 24
Finished Jul 30 06:30:32 PM PDT 24
Peak memory 206984 kb
Host smart-215cc9e9-3e43-4d82-b60d-6c76cfd09ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37234
47622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3723447622
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1825577363
Short name T122
Test name
Test status
Simulation time 176056074 ps
CPU time 0.99 seconds
Started Jul 30 06:30:33 PM PDT 24
Finished Jul 30 06:30:34 PM PDT 24
Peak memory 206948 kb
Host smart-389a4ca8-4042-469b-b939-4725101ce9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18255
77363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1825577363
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.4148299570
Short name T2555
Test name
Test status
Simulation time 189173138 ps
CPU time 0.93 seconds
Started Jul 30 06:30:33 PM PDT 24
Finished Jul 30 06:30:34 PM PDT 24
Peak memory 206916 kb
Host smart-04a9d68f-16c8-4e5b-b53f-69c7fdf71edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41482
99570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.4148299570
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2225981384
Short name T2087
Test name
Test status
Simulation time 172227505 ps
CPU time 0.87 seconds
Started Jul 30 06:30:33 PM PDT 24
Finished Jul 30 06:30:34 PM PDT 24
Peak memory 206928 kb
Host smart-69c986ae-a576-4297-8cd7-edce16632f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22259
81384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2225981384
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.371008642
Short name T1197
Test name
Test status
Simulation time 155471870 ps
CPU time 0.92 seconds
Started Jul 30 06:30:54 PM PDT 24
Finished Jul 30 06:30:55 PM PDT 24
Peak memory 206984 kb
Host smart-b470e57d-025c-45b3-8bb7-0d5199406252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37100
8642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.371008642
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1645768889
Short name T2733
Test name
Test status
Simulation time 171553823 ps
CPU time 0.9 seconds
Started Jul 30 06:30:35 PM PDT 24
Finished Jul 30 06:30:36 PM PDT 24
Peak memory 206908 kb
Host smart-4e5fe44c-fd0c-4d17-a90a-8c0960b2c70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16457
68889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1645768889
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.3656016831
Short name T1198
Test name
Test status
Simulation time 226692855 ps
CPU time 1.02 seconds
Started Jul 30 06:30:31 PM PDT 24
Finished Jul 30 06:30:32 PM PDT 24
Peak memory 206912 kb
Host smart-587059bb-7c6c-4fc9-a7a7-ec37605d7645
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3656016831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.3656016831
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3593116485
Short name T1774
Test name
Test status
Simulation time 68269964 ps
CPU time 0.76 seconds
Started Jul 30 06:30:41 PM PDT 24
Finished Jul 30 06:30:41 PM PDT 24
Peak memory 206892 kb
Host smart-2d31b8ce-5e58-40ea-bfce-d7e3b52b9c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35931
16485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3593116485
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2749073667
Short name T249
Test name
Test status
Simulation time 16349513338 ps
CPU time 44.81 seconds
Started Jul 30 06:30:32 PM PDT 24
Finished Jul 30 06:31:17 PM PDT 24
Peak memory 223524 kb
Host smart-769d8454-ff7e-4f96-8555-5e29997c25bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27490
73667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2749073667
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1076904214
Short name T2278
Test name
Test status
Simulation time 193751053 ps
CPU time 0.96 seconds
Started Jul 30 06:30:30 PM PDT 24
Finished Jul 30 06:30:31 PM PDT 24
Peak memory 206916 kb
Host smart-250390c1-0e15-465b-aa83-8a666c3de6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10769
04214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1076904214
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2705991440
Short name T536
Test name
Test status
Simulation time 183111590 ps
CPU time 0.96 seconds
Started Jul 30 06:30:35 PM PDT 24
Finished Jul 30 06:30:36 PM PDT 24
Peak memory 206844 kb
Host smart-bdfcfc31-bf98-4baf-9e09-65e9ec6247f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27059
91440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2705991440
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.3886070477
Short name T1119
Test name
Test status
Simulation time 216170794 ps
CPU time 1 seconds
Started Jul 30 06:30:33 PM PDT 24
Finished Jul 30 06:30:34 PM PDT 24
Peak memory 206908 kb
Host smart-cd6477e0-d811-4f10-85b0-574ddccaa5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38860
70477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.3886070477
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.3725892630
Short name T1736
Test name
Test status
Simulation time 180472173 ps
CPU time 0.96 seconds
Started Jul 30 06:30:32 PM PDT 24
Finished Jul 30 06:30:33 PM PDT 24
Peak memory 206984 kb
Host smart-26280f89-a2b6-4a7f-ab05-a9b32efc05ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37258
92630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.3725892630
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2625452718
Short name T1127
Test name
Test status
Simulation time 198665085 ps
CPU time 0.88 seconds
Started Jul 30 06:30:34 PM PDT 24
Finished Jul 30 06:30:35 PM PDT 24
Peak memory 206912 kb
Host smart-f6a95422-20f5-4699-a780-d3f2f36658d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26254
52718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2625452718
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.582661766
Short name T822
Test name
Test status
Simulation time 149901628 ps
CPU time 0.86 seconds
Started Jul 30 06:30:35 PM PDT 24
Finished Jul 30 06:30:36 PM PDT 24
Peak memory 206812 kb
Host smart-a3ab1414-da93-432c-97e2-b516da5d6c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58266
1766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.582661766
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3077566729
Short name T1984
Test name
Test status
Simulation time 178055990 ps
CPU time 0.9 seconds
Started Jul 30 06:30:31 PM PDT 24
Finished Jul 30 06:30:32 PM PDT 24
Peak memory 206912 kb
Host smart-c3a93d7f-798b-40b9-b436-89696df5569c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30775
66729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3077566729
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.4196080525
Short name T716
Test name
Test status
Simulation time 265975237 ps
CPU time 1.12 seconds
Started Jul 30 06:30:34 PM PDT 24
Finished Jul 30 06:30:36 PM PDT 24
Peak memory 206876 kb
Host smart-2fb0676d-410a-4822-8c99-ae3c49fbc1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41960
80525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.4196080525
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.521943985
Short name T2594
Test name
Test status
Simulation time 168706259 ps
CPU time 0.91 seconds
Started Jul 30 06:30:30 PM PDT 24
Finished Jul 30 06:30:31 PM PDT 24
Peak memory 206904 kb
Host smart-031d153a-854f-4d61-9ea9-b8a8ff27990f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52194
3985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.521943985
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.3734975524
Short name T2327
Test name
Test status
Simulation time 187969961 ps
CPU time 0.94 seconds
Started Jul 30 06:30:34 PM PDT 24
Finished Jul 30 06:30:36 PM PDT 24
Peak memory 206984 kb
Host smart-ac7ada4e-31d6-4c1d-9094-2b167ad9ed9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37349
75524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3734975524
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.2054493779
Short name T211
Test name
Test status
Simulation time 1382576833 ps
CPU time 3.47 seconds
Started Jul 30 06:30:33 PM PDT 24
Finished Jul 30 06:30:37 PM PDT 24
Peak memory 206936 kb
Host smart-4f82cc10-0388-47f4-aea6-de412bb65fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20544
93779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.2054493779
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.1416558184
Short name T1336
Test name
Test status
Simulation time 3825120784 ps
CPU time 30.74 seconds
Started Jul 30 06:30:46 PM PDT 24
Finished Jul 30 06:31:17 PM PDT 24
Peak memory 216796 kb
Host smart-a50bdb76-85f8-40a6-b5eb-5abf4d35c02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14165
58184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.1416558184
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.2642557817
Short name T1953
Test name
Test status
Simulation time 1684206242 ps
CPU time 39.87 seconds
Started Jul 30 06:30:24 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 207092 kb
Host smart-44a006b5-f992-4ab8-979b-f3d54be35d50
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642557817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_hos
t_handshake.2642557817
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.3754381371
Short name T525
Test name
Test status
Simulation time 29781163 ps
CPU time 0.63 seconds
Started Jul 30 06:30:44 PM PDT 24
Finished Jul 30 06:30:44 PM PDT 24
Peak memory 207036 kb
Host smart-2e9a61a2-a8c3-4504-952c-d0793b7b3d60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3754381371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.3754381371
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.536867092
Short name T933
Test name
Test status
Simulation time 3782488877 ps
CPU time 5.5 seconds
Started Jul 30 06:30:35 PM PDT 24
Finished Jul 30 06:30:40 PM PDT 24
Peak memory 207068 kb
Host smart-3d032c6a-4465-408c-8c81-8070a63da641
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536867092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_ao
n_wake_disconnect.536867092
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2348534644
Short name T891
Test name
Test status
Simulation time 13327371334 ps
CPU time 15.7 seconds
Started Jul 30 06:30:41 PM PDT 24
Finished Jul 30 06:30:57 PM PDT 24
Peak memory 207160 kb
Host smart-21c4ef47-ba7a-41aa-8333-9407b833ea3b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348534644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2348534644
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.2243826512
Short name T1946
Test name
Test status
Simulation time 23393639930 ps
CPU time 33.3 seconds
Started Jul 30 06:30:33 PM PDT 24
Finished Jul 30 06:31:07 PM PDT 24
Peak memory 207160 kb
Host smart-b73e07f0-42f9-4733-a494-8186a9501bcf
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243826512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.2243826512
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.113299108
Short name T1259
Test name
Test status
Simulation time 147808639 ps
CPU time 0.83 seconds
Started Jul 30 06:30:35 PM PDT 24
Finished Jul 30 06:30:36 PM PDT 24
Peak memory 206920 kb
Host smart-52a1ca7c-9db0-4e70-bd22-b5a18c814eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11329
9108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.113299108
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.35567962
Short name T600
Test name
Test status
Simulation time 145320588 ps
CPU time 0.86 seconds
Started Jul 30 06:30:43 PM PDT 24
Finished Jul 30 06:30:44 PM PDT 24
Peak memory 206872 kb
Host smart-9ab05cdd-484c-4f62-a37f-1b7ccc71827f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35567
962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.35567962
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.1215473220
Short name T385
Test name
Test status
Simulation time 235350558 ps
CPU time 1.04 seconds
Started Jul 30 06:30:35 PM PDT 24
Finished Jul 30 06:30:37 PM PDT 24
Peak memory 206980 kb
Host smart-16d17cd4-c104-403c-b1b9-dbc7dfddd3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12154
73220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.1215473220
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.252577723
Short name T2486
Test name
Test status
Simulation time 408691755 ps
CPU time 1.32 seconds
Started Jul 30 06:30:35 PM PDT 24
Finished Jul 30 06:30:36 PM PDT 24
Peak memory 206924 kb
Host smart-9d3323ee-b67c-46c9-9387-7c15de9e8765
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=252577723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.252577723
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.3291384831
Short name T1608
Test name
Test status
Simulation time 14475356629 ps
CPU time 29.1 seconds
Started Jul 30 06:30:42 PM PDT 24
Finished Jul 30 06:31:12 PM PDT 24
Peak memory 207136 kb
Host smart-0d2ae86c-aba9-45b9-9cab-ca6cf9282f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32913
84831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.3291384831
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.3032238793
Short name T508
Test name
Test status
Simulation time 960278440 ps
CPU time 20.07 seconds
Started Jul 30 06:30:36 PM PDT 24
Finished Jul 30 06:30:56 PM PDT 24
Peak memory 206960 kb
Host smart-ec689b58-b977-463d-9c13-264fffd9852a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032238793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.3032238793
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.710898746
Short name T2164
Test name
Test status
Simulation time 473517790 ps
CPU time 1.5 seconds
Started Jul 30 06:30:41 PM PDT 24
Finished Jul 30 06:30:43 PM PDT 24
Peak memory 206888 kb
Host smart-0a3eed14-5321-4a1e-94af-7cc14fcbc6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71089
8746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.710898746
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.1791367707
Short name T468
Test name
Test status
Simulation time 149820650 ps
CPU time 0.87 seconds
Started Jul 30 06:30:38 PM PDT 24
Finished Jul 30 06:30:38 PM PDT 24
Peak memory 206880 kb
Host smart-5d486e2d-4ecb-47b1-ad69-022e17add554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17913
67707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1791367707
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1851706967
Short name T2498
Test name
Test status
Simulation time 38610126 ps
CPU time 0.71 seconds
Started Jul 30 06:30:43 PM PDT 24
Finished Jul 30 06:30:44 PM PDT 24
Peak memory 206876 kb
Host smart-7afcc02a-d95a-4b46-b119-a38661a4de8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18517
06967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1851706967
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.582161222
Short name T148
Test name
Test status
Simulation time 995217231 ps
CPU time 2.56 seconds
Started Jul 30 06:30:42 PM PDT 24
Finished Jul 30 06:30:45 PM PDT 24
Peak memory 207008 kb
Host smart-395d7656-4c15-4afc-b902-a6dbb010e806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58216
1222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.582161222
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1338809703
Short name T2251
Test name
Test status
Simulation time 291182699 ps
CPU time 2.05 seconds
Started Jul 30 06:30:35 PM PDT 24
Finished Jul 30 06:30:37 PM PDT 24
Peak memory 207008 kb
Host smart-5fb14ead-1532-42ba-b7cd-e4e2a26cdf46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13388
09703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1338809703
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.839507584
Short name T1702
Test name
Test status
Simulation time 192815811 ps
CPU time 1.05 seconds
Started Jul 30 06:30:42 PM PDT 24
Finished Jul 30 06:30:44 PM PDT 24
Peak memory 206992 kb
Host smart-10d8b37c-db58-4dd2-9559-8fac57867e7a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=839507584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.839507584
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1058233972
Short name T1004
Test name
Test status
Simulation time 184268362 ps
CPU time 0.88 seconds
Started Jul 30 06:30:35 PM PDT 24
Finished Jul 30 06:30:36 PM PDT 24
Peak memory 206884 kb
Host smart-3880bda2-b0f1-439c-8a67-653e56afa2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10582
33972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1058233972
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2720755402
Short name T974
Test name
Test status
Simulation time 160259782 ps
CPU time 0.89 seconds
Started Jul 30 06:30:42 PM PDT 24
Finished Jul 30 06:30:43 PM PDT 24
Peak memory 206916 kb
Host smart-21dab3fb-7e31-4e18-8142-1890f9dbc49d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27207
55402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2720755402
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.3582376910
Short name T1169
Test name
Test status
Simulation time 8365228046 ps
CPU time 246.46 seconds
Started Jul 30 06:30:35 PM PDT 24
Finished Jul 30 06:34:42 PM PDT 24
Peak memory 215320 kb
Host smart-37d1442e-0fc7-41c2-a7f3-e6b2ba874696
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3582376910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.3582376910
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.688792481
Short name T756
Test name
Test status
Simulation time 11856027879 ps
CPU time 85.87 seconds
Started Jul 30 06:30:39 PM PDT 24
Finished Jul 30 06:32:05 PM PDT 24
Peak memory 207168 kb
Host smart-5eab2fbd-e33b-40f1-aec9-67974851e0d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=688792481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.688792481
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3596946132
Short name T710
Test name
Test status
Simulation time 236263223 ps
CPU time 0.98 seconds
Started Jul 30 06:30:40 PM PDT 24
Finished Jul 30 06:30:41 PM PDT 24
Peak memory 206932 kb
Host smart-d613422c-cbdc-4ab8-9470-35753fe27829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35969
46132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3596946132
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1549135375
Short name T1638
Test name
Test status
Simulation time 23302871229 ps
CPU time 28.38 seconds
Started Jul 30 06:30:43 PM PDT 24
Finished Jul 30 06:31:11 PM PDT 24
Peak memory 207160 kb
Host smart-316a3c1b-2b59-4da9-9463-079155bcc24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15491
35375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1549135375
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.2472526316
Short name T1941
Test name
Test status
Simulation time 3300730988 ps
CPU time 4.78 seconds
Started Jul 30 06:30:39 PM PDT 24
Finished Jul 30 06:30:44 PM PDT 24
Peak memory 207120 kb
Host smart-49a5aa48-94ff-4e65-88b4-61d58120239d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24725
26316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2472526316
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.539697260
Short name T1885
Test name
Test status
Simulation time 8271391979 ps
CPU time 63.93 seconds
Started Jul 30 06:30:37 PM PDT 24
Finished Jul 30 06:31:41 PM PDT 24
Peak memory 216520 kb
Host smart-bd5a567b-f68d-4d1b-b76b-5e116a7e36a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53969
7260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.539697260
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.2463721799
Short name T767
Test name
Test status
Simulation time 4356115067 ps
CPU time 125.19 seconds
Started Jul 30 06:30:52 PM PDT 24
Finished Jul 30 06:32:57 PM PDT 24
Peak memory 215340 kb
Host smart-05e7cc9a-fa2f-44d3-ae33-72387e387bfe
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2463721799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.2463721799
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.914007033
Short name T2810
Test name
Test status
Simulation time 266420781 ps
CPU time 1.1 seconds
Started Jul 30 06:30:45 PM PDT 24
Finished Jul 30 06:30:46 PM PDT 24
Peak memory 206972 kb
Host smart-1ce06705-9275-4a38-9e6c-7a78d105990a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=914007033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.914007033
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2948079922
Short name T1770
Test name
Test status
Simulation time 189069283 ps
CPU time 0.92 seconds
Started Jul 30 06:30:49 PM PDT 24
Finished Jul 30 06:30:51 PM PDT 24
Peak memory 206928 kb
Host smart-ae94dd73-5307-43d5-af29-0d1092970277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29480
79922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2948079922
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.3667434838
Short name T1959
Test name
Test status
Simulation time 3304379789 ps
CPU time 94.78 seconds
Started Jul 30 06:30:53 PM PDT 24
Finished Jul 30 06:32:28 PM PDT 24
Peak memory 215296 kb
Host smart-d028be47-b02c-4883-91bd-698164a0c92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36674
34838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.3667434838
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.2532669934
Short name T2670
Test name
Test status
Simulation time 6365037312 ps
CPU time 68.15 seconds
Started Jul 30 06:30:46 PM PDT 24
Finished Jul 30 06:31:55 PM PDT 24
Peak memory 207088 kb
Host smart-263e0ebd-bf59-444f-916b-80ff691290aa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2532669934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.2532669934
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.344030247
Short name T1763
Test name
Test status
Simulation time 173887282 ps
CPU time 0.94 seconds
Started Jul 30 06:30:40 PM PDT 24
Finished Jul 30 06:30:42 PM PDT 24
Peak memory 206996 kb
Host smart-1c0923f4-b5dd-4e09-97ed-cfd26de354a5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=344030247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.344030247
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.4058224531
Short name T1016
Test name
Test status
Simulation time 189712789 ps
CPU time 0.9 seconds
Started Jul 30 06:30:45 PM PDT 24
Finished Jul 30 06:30:46 PM PDT 24
Peak memory 206944 kb
Host smart-89c3d158-a02f-491d-8f78-92e919f0850f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40582
24531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.4058224531
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.891571818
Short name T1719
Test name
Test status
Simulation time 236408205 ps
CPU time 1.02 seconds
Started Jul 30 06:30:52 PM PDT 24
Finished Jul 30 06:30:53 PM PDT 24
Peak memory 206984 kb
Host smart-f494b173-375a-4e1f-9484-08fa0858483e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89157
1818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.891571818
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2111677962
Short name T431
Test name
Test status
Simulation time 147191822 ps
CPU time 0.84 seconds
Started Jul 30 06:30:50 PM PDT 24
Finished Jul 30 06:30:51 PM PDT 24
Peak memory 206928 kb
Host smart-44c2c814-b1e3-4b98-b5f7-61a24b0e0e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21116
77962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2111677962
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1588440174
Short name T275
Test name
Test status
Simulation time 176307626 ps
CPU time 0.87 seconds
Started Jul 30 06:30:43 PM PDT 24
Finished Jul 30 06:30:44 PM PDT 24
Peak memory 206944 kb
Host smart-8eb13233-5521-4c0f-b26d-4d5403a01f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15884
40174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1588440174
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.400995919
Short name T160
Test name
Test status
Simulation time 165466812 ps
CPU time 0.88 seconds
Started Jul 30 06:30:46 PM PDT 24
Finished Jul 30 06:30:47 PM PDT 24
Peak memory 206908 kb
Host smart-6f3e4717-78e8-488e-87c5-436b9cc20788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40099
5919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.400995919
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.2840313443
Short name T2176
Test name
Test status
Simulation time 217015028 ps
CPU time 1.01 seconds
Started Jul 30 06:30:46 PM PDT 24
Finished Jul 30 06:30:47 PM PDT 24
Peak memory 206920 kb
Host smart-e0985c07-8dc4-4c54-8d53-d9dd78cb5cb5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2840313443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.2840313443
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.249464241
Short name T1783
Test name
Test status
Simulation time 162027672 ps
CPU time 0.88 seconds
Started Jul 30 06:30:53 PM PDT 24
Finished Jul 30 06:30:54 PM PDT 24
Peak memory 206892 kb
Host smart-8ec6fbd3-d798-40b1-b8df-810568e0812b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24946
4241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.249464241
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2483648332
Short name T236
Test name
Test status
Simulation time 19204738427 ps
CPU time 47.58 seconds
Started Jul 30 06:30:40 PM PDT 24
Finished Jul 30 06:31:28 PM PDT 24
Peak memory 215364 kb
Host smart-d17e740c-b9d9-47c9-9384-273c74ef697a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24836
48332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2483648332
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2129518717
Short name T1417
Test name
Test status
Simulation time 169259751 ps
CPU time 0.99 seconds
Started Jul 30 06:30:56 PM PDT 24
Finished Jul 30 06:30:57 PM PDT 24
Peak memory 206924 kb
Host smart-9941f7c4-00d6-4cf1-9ee3-0c088d39962a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21295
18717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2129518717
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.4190724573
Short name T1408
Test name
Test status
Simulation time 195895223 ps
CPU time 0.94 seconds
Started Jul 30 06:30:45 PM PDT 24
Finished Jul 30 06:30:46 PM PDT 24
Peak memory 206892 kb
Host smart-ba621304-967f-424f-bc76-03ca7c283d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41907
24573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.4190724573
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3514393781
Short name T554
Test name
Test status
Simulation time 184184451 ps
CPU time 0.92 seconds
Started Jul 30 06:30:50 PM PDT 24
Finished Jul 30 06:30:52 PM PDT 24
Peak memory 206944 kb
Host smart-d0dbc511-b4da-429d-874c-ba57c4ebbb94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35143
93781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3514393781
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.800594160
Short name T688
Test name
Test status
Simulation time 208769927 ps
CPU time 0.95 seconds
Started Jul 30 06:30:52 PM PDT 24
Finished Jul 30 06:30:54 PM PDT 24
Peak memory 206916 kb
Host smart-737b1d76-b4ac-4c8f-9e1e-1ece374832a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80059
4160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.800594160
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1562402771
Short name T901
Test name
Test status
Simulation time 137868327 ps
CPU time 0.83 seconds
Started Jul 30 06:30:45 PM PDT 24
Finished Jul 30 06:30:46 PM PDT 24
Peak memory 206876 kb
Host smart-c764a7e3-2325-4f40-b65c-cf330e84a980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15624
02771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1562402771
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.428225764
Short name T571
Test name
Test status
Simulation time 164985361 ps
CPU time 0.86 seconds
Started Jul 30 06:30:45 PM PDT 24
Finished Jul 30 06:30:46 PM PDT 24
Peak memory 206908 kb
Host smart-54915ec6-442d-496e-bc66-e7374826fd8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42822
5764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.428225764
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.4008872979
Short name T2140
Test name
Test status
Simulation time 145175217 ps
CPU time 0.86 seconds
Started Jul 30 06:30:47 PM PDT 24
Finished Jul 30 06:30:48 PM PDT 24
Peak memory 206928 kb
Host smart-d407b92f-7bd4-4973-aea9-fa9c5de14ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40088
72979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.4008872979
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3184986706
Short name T2633
Test name
Test status
Simulation time 273379861 ps
CPU time 1.06 seconds
Started Jul 30 06:30:50 PM PDT 24
Finished Jul 30 06:30:51 PM PDT 24
Peak memory 206904 kb
Host smart-13ecfbee-95e0-4d98-aa8d-da02cea19515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31849
86706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3184986706
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.2475799550
Short name T5
Test name
Test status
Simulation time 5057117977 ps
CPU time 154.29 seconds
Started Jul 30 06:30:46 PM PDT 24
Finished Jul 30 06:33:20 PM PDT 24
Peak memory 215316 kb
Host smart-5fef019c-9015-4e12-9df1-325a5a472c1a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2475799550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.2475799550
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.485054306
Short name T973
Test name
Test status
Simulation time 191999193 ps
CPU time 0.9 seconds
Started Jul 30 06:30:45 PM PDT 24
Finished Jul 30 06:30:46 PM PDT 24
Peak memory 206916 kb
Host smart-4a64647f-d6fb-496b-b23a-fbc6fe0c9034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48505
4306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.485054306
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2448655463
Short name T615
Test name
Test status
Simulation time 198457610 ps
CPU time 0.92 seconds
Started Jul 30 06:30:51 PM PDT 24
Finished Jul 30 06:30:52 PM PDT 24
Peak memory 206924 kb
Host smart-7f18c4fe-8531-4f51-a0ef-3e1d4756b844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24486
55463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2448655463
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.1558828471
Short name T2756
Test name
Test status
Simulation time 1320820414 ps
CPU time 3.44 seconds
Started Jul 30 06:30:45 PM PDT 24
Finished Jul 30 06:30:49 PM PDT 24
Peak memory 206948 kb
Host smart-ecc0b48f-a128-4fb2-a681-ec34c69b3c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15588
28471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.1558828471
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1230710903
Short name T1939
Test name
Test status
Simulation time 5040428168 ps
CPU time 38.34 seconds
Started Jul 30 06:30:44 PM PDT 24
Finished Jul 30 06:31:22 PM PDT 24
Peak memory 215392 kb
Host smart-c72eb97a-ff66-44d3-ae3d-5e60daf204d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12307
10903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1230710903
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.2896732440
Short name T2383
Test name
Test status
Simulation time 831079824 ps
CPU time 5.37 seconds
Started Jul 30 06:30:46 PM PDT 24
Finished Jul 30 06:30:51 PM PDT 24
Peak memory 207036 kb
Host smart-3396e143-6786-415d-a259-525a5201a6c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896732440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_hos
t_handshake.2896732440
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.950439970
Short name T1162
Test name
Test status
Simulation time 55166312 ps
CPU time 0.67 seconds
Started Jul 30 06:30:52 PM PDT 24
Finished Jul 30 06:30:52 PM PDT 24
Peak memory 207024 kb
Host smart-ba6d989e-436b-48e9-a4ee-ee301034e31b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=950439970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.950439970
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.3117567511
Short name T2195
Test name
Test status
Simulation time 4309191614 ps
CPU time 6.36 seconds
Started Jul 30 06:30:50 PM PDT 24
Finished Jul 30 06:30:56 PM PDT 24
Peak memory 207144 kb
Host smart-a16e0c13-9f0d-4302-bbc0-6308dbdab768
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117567511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.3117567511
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.899580890
Short name T807
Test name
Test status
Simulation time 13339756700 ps
CPU time 16.92 seconds
Started Jul 30 06:30:55 PM PDT 24
Finished Jul 30 06:31:12 PM PDT 24
Peak memory 207152 kb
Host smart-7d58891f-9c25-4351-a5eb-6b8c2522d4e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=899580890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.899580890
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.3053229112
Short name T1208
Test name
Test status
Simulation time 23321705729 ps
CPU time 28.06 seconds
Started Jul 30 06:30:51 PM PDT 24
Finished Jul 30 06:31:19 PM PDT 24
Peak memory 207116 kb
Host smart-7cee5d97-1daf-44e7-825c-2bb112fe8086
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053229112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_resume.3053229112
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.827086477
Short name T1146
Test name
Test status
Simulation time 157531019 ps
CPU time 0.84 seconds
Started Jul 30 06:30:51 PM PDT 24
Finished Jul 30 06:30:52 PM PDT 24
Peak memory 206916 kb
Host smart-79ad6d94-58f5-47b8-8cf2-5a2c6b2999a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82708
6477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.827086477
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1976457999
Short name T1419
Test name
Test status
Simulation time 150485601 ps
CPU time 0.83 seconds
Started Jul 30 06:30:54 PM PDT 24
Finished Jul 30 06:30:55 PM PDT 24
Peak memory 206920 kb
Host smart-f9b5974f-f4a5-433c-94e4-528fa49f43c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19764
57999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1976457999
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1778105620
Short name T1101
Test name
Test status
Simulation time 344640728 ps
CPU time 1.41 seconds
Started Jul 30 06:30:48 PM PDT 24
Finished Jul 30 06:30:49 PM PDT 24
Peak memory 206940 kb
Host smart-0fbaf470-0480-4838-b076-73838ca391c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17781
05620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1778105620
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2810645903
Short name T1156
Test name
Test status
Simulation time 409232508 ps
CPU time 1.4 seconds
Started Jul 30 06:30:53 PM PDT 24
Finished Jul 30 06:30:55 PM PDT 24
Peak memory 206944 kb
Host smart-0e84ce87-1b09-4178-a0bd-65a3acd15268
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2810645903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2810645903
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.862905346
Short name T1905
Test name
Test status
Simulation time 16183813941 ps
CPU time 33.96 seconds
Started Jul 30 06:30:51 PM PDT 24
Finished Jul 30 06:31:25 PM PDT 24
Peak memory 207124 kb
Host smart-71fe8ab2-8f3d-40dd-b448-b460ff2ccbb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86290
5346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.862905346
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.1634289438
Short name T2694
Test name
Test status
Simulation time 3433703661 ps
CPU time 28.77 seconds
Started Jul 30 06:30:47 PM PDT 24
Finished Jul 30 06:31:16 PM PDT 24
Peak memory 207148 kb
Host smart-46fc5051-9279-4946-be38-8611aaff89bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634289438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.1634289438
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.976444230
Short name T2611
Test name
Test status
Simulation time 489459601 ps
CPU time 1.73 seconds
Started Jul 30 06:30:47 PM PDT 24
Finished Jul 30 06:30:49 PM PDT 24
Peak memory 206884 kb
Host smart-c075d544-c07a-46f9-bbd4-c4a564a3f2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97644
4230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.976444230
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.456390926
Short name T1362
Test name
Test status
Simulation time 159728022 ps
CPU time 0.84 seconds
Started Jul 30 06:30:48 PM PDT 24
Finished Jul 30 06:30:49 PM PDT 24
Peak memory 206872 kb
Host smart-f288ee16-f031-4dd7-9d81-8d4d9552bff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45639
0926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.456390926
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2429540721
Short name T1583
Test name
Test status
Simulation time 76462371 ps
CPU time 0.75 seconds
Started Jul 30 06:30:50 PM PDT 24
Finished Jul 30 06:30:51 PM PDT 24
Peak memory 206892 kb
Host smart-fcf125bc-5cc5-4fde-973f-433a6e9e9bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24295
40721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2429540721
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.2779837082
Short name T539
Test name
Test status
Simulation time 911430320 ps
CPU time 2.41 seconds
Started Jul 30 06:30:49 PM PDT 24
Finished Jul 30 06:30:52 PM PDT 24
Peak memory 206996 kb
Host smart-a067bdb4-c7b8-435b-8799-03da5ad4987a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27798
37082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.2779837082
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1468077883
Short name T2844
Test name
Test status
Simulation time 189450115 ps
CPU time 1.74 seconds
Started Jul 30 06:30:48 PM PDT 24
Finished Jul 30 06:30:50 PM PDT 24
Peak memory 207052 kb
Host smart-92602a5d-7c20-44f1-8443-a9d5f08ee316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14680
77883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1468077883
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2084886236
Short name T2599
Test name
Test status
Simulation time 178385575 ps
CPU time 0.9 seconds
Started Jul 30 06:30:49 PM PDT 24
Finished Jul 30 06:30:50 PM PDT 24
Peak memory 206928 kb
Host smart-e5923a78-4b7f-48be-a4a9-6f2fe2fc1750
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2084886236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2084886236
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.290404467
Short name T1961
Test name
Test status
Simulation time 172280722 ps
CPU time 0.81 seconds
Started Jul 30 06:30:46 PM PDT 24
Finished Jul 30 06:30:47 PM PDT 24
Peak memory 206936 kb
Host smart-c9047004-be65-4d8f-b1c3-a366209d4118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29040
4467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.290404467
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.355883158
Short name T2857
Test name
Test status
Simulation time 232269909 ps
CPU time 0.96 seconds
Started Jul 30 06:30:47 PM PDT 24
Finished Jul 30 06:30:49 PM PDT 24
Peak memory 206916 kb
Host smart-b7bd389f-4ece-42c6-be44-165023d7efa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35588
3158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.355883158
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.2705700057
Short name T1945
Test name
Test status
Simulation time 6318066803 ps
CPU time 188.1 seconds
Started Jul 30 06:30:52 PM PDT 24
Finished Jul 30 06:34:01 PM PDT 24
Peak memory 215300 kb
Host smart-595ea814-6a15-410d-8600-251210f98f52
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2705700057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.2705700057
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.2542385416
Short name T2534
Test name
Test status
Simulation time 11406627806 ps
CPU time 76.56 seconds
Started Jul 30 06:30:47 PM PDT 24
Finished Jul 30 06:32:04 PM PDT 24
Peak memory 207096 kb
Host smart-70d19d93-23fa-46a5-a885-05de37250c99
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2542385416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.2542385416
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1977196808
Short name T1586
Test name
Test status
Simulation time 240644106 ps
CPU time 1.02 seconds
Started Jul 30 06:30:47 PM PDT 24
Finished Jul 30 06:30:49 PM PDT 24
Peak memory 206920 kb
Host smart-50cf817a-9fab-4901-9615-9d82a13b9fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19771
96808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1977196808
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.199568686
Short name T2719
Test name
Test status
Simulation time 23283092864 ps
CPU time 26.65 seconds
Started Jul 30 06:30:48 PM PDT 24
Finished Jul 30 06:31:15 PM PDT 24
Peak memory 207096 kb
Host smart-3b5d548d-c6a4-4412-8608-d6a6d9292f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19956
8686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.199568686
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2864016590
Short name T1557
Test name
Test status
Simulation time 3335379300 ps
CPU time 5.32 seconds
Started Jul 30 06:30:49 PM PDT 24
Finished Jul 30 06:30:54 PM PDT 24
Peak memory 207072 kb
Host smart-a88a893f-8578-4f46-8f0f-464d3bc6ad42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28640
16590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2864016590
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1173072418
Short name T2336
Test name
Test status
Simulation time 8510364693 ps
CPU time 85.91 seconds
Started Jul 30 06:30:48 PM PDT 24
Finished Jul 30 06:32:15 PM PDT 24
Peak memory 215344 kb
Host smart-06f32878-04d0-4973-8afa-a9123019acf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11730
72418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1173072418
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2315675742
Short name T2210
Test name
Test status
Simulation time 3820039131 ps
CPU time 112.38 seconds
Started Jul 30 06:30:51 PM PDT 24
Finished Jul 30 06:32:43 PM PDT 24
Peak memory 215308 kb
Host smart-f2e12757-5061-4441-ba13-f02a5583bea7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2315675742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2315675742
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.2329910035
Short name T2472
Test name
Test status
Simulation time 262560941 ps
CPU time 1.04 seconds
Started Jul 30 06:30:57 PM PDT 24
Finished Jul 30 06:30:59 PM PDT 24
Peak memory 206920 kb
Host smart-3b46954f-cf02-467d-a074-74a025f1bc98
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2329910035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.2329910035
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.4249200949
Short name T1071
Test name
Test status
Simulation time 221114100 ps
CPU time 0.95 seconds
Started Jul 30 06:30:57 PM PDT 24
Finished Jul 30 06:30:58 PM PDT 24
Peak memory 206980 kb
Host smart-cb11ed4c-8702-47c1-937f-1df06440c5c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42492
00949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.4249200949
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1269068675
Short name T1305
Test name
Test status
Simulation time 4987739319 ps
CPU time 49.49 seconds
Started Jul 30 06:30:55 PM PDT 24
Finished Jul 30 06:31:45 PM PDT 24
Peak memory 215328 kb
Host smart-8af03018-c43e-4e72-8409-4488cd5aae64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12690
68675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1269068675
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.87059972
Short name T1908
Test name
Test status
Simulation time 6197777602 ps
CPU time 62.54 seconds
Started Jul 30 06:30:47 PM PDT 24
Finished Jul 30 06:31:50 PM PDT 24
Peak memory 207204 kb
Host smart-9f31c97b-1ba7-401e-9e9a-379b4de5accb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=87059972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.87059972
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.4146295947
Short name T29
Test name
Test status
Simulation time 149744004 ps
CPU time 0.84 seconds
Started Jul 30 06:30:51 PM PDT 24
Finished Jul 30 06:30:52 PM PDT 24
Peak memory 206944 kb
Host smart-8d873b35-4d73-45d3-a876-48e1d1e4c3dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4146295947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.4146295947
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3176426931
Short name T1232
Test name
Test status
Simulation time 158744528 ps
CPU time 0.85 seconds
Started Jul 30 06:30:59 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 206960 kb
Host smart-b9f7c853-d2f7-48b3-b4ed-509d1ed13f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31764
26931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3176426931
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1261784158
Short name T134
Test name
Test status
Simulation time 216088091 ps
CPU time 1.01 seconds
Started Jul 30 06:30:47 PM PDT 24
Finished Jul 30 06:30:48 PM PDT 24
Peak memory 206928 kb
Host smart-a01fd856-ebc2-444c-a8e1-4a64423f577f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12617
84158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1261784158
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2742227834
Short name T1928
Test name
Test status
Simulation time 175996674 ps
CPU time 0.9 seconds
Started Jul 30 06:30:56 PM PDT 24
Finished Jul 30 06:30:57 PM PDT 24
Peak memory 206956 kb
Host smart-8f9256bb-432a-4657-984d-40efd19f2480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422
27834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2742227834
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2378180665
Short name T2833
Test name
Test status
Simulation time 146781094 ps
CPU time 0.81 seconds
Started Jul 30 06:30:49 PM PDT 24
Finished Jul 30 06:30:50 PM PDT 24
Peak memory 206940 kb
Host smart-91baf0da-5f1b-417f-90eb-87f9bca427a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23781
80665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2378180665
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1373328159
Short name T1225
Test name
Test status
Simulation time 146928536 ps
CPU time 0.87 seconds
Started Jul 30 06:30:54 PM PDT 24
Finished Jul 30 06:30:55 PM PDT 24
Peak memory 206916 kb
Host smart-2b782cb9-6ad0-4b34-8313-38d6a2f55f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13733
28159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1373328159
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2300750772
Short name T1502
Test name
Test status
Simulation time 157669444 ps
CPU time 0.9 seconds
Started Jul 30 06:30:52 PM PDT 24
Finished Jul 30 06:30:54 PM PDT 24
Peak memory 206912 kb
Host smart-2e8d0dc9-7afd-4716-bad9-bed899027c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23007
50772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2300750772
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.587458592
Short name T1936
Test name
Test status
Simulation time 236293786 ps
CPU time 1.04 seconds
Started Jul 30 06:30:52 PM PDT 24
Finished Jul 30 06:30:53 PM PDT 24
Peak memory 206916 kb
Host smart-bd15d773-fc87-40f2-a7d2-ba0bddfb8e6a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=587458592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.587458592
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3347502044
Short name T1420
Test name
Test status
Simulation time 196303487 ps
CPU time 1.03 seconds
Started Jul 30 06:30:47 PM PDT 24
Finished Jul 30 06:30:49 PM PDT 24
Peak memory 206892 kb
Host smart-1985ebdd-f5a9-4e37-bb89-fd82ec612163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33475
02044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3347502044
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3676323922
Short name T674
Test name
Test status
Simulation time 89643742 ps
CPU time 0.76 seconds
Started Jul 30 06:30:51 PM PDT 24
Finished Jul 30 06:30:52 PM PDT 24
Peak memory 206848 kb
Host smart-4e8c5b32-9052-4ee6-a78c-a128cf139df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36763
23922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3676323922
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1157119510
Short name T1740
Test name
Test status
Simulation time 19414547020 ps
CPU time 49.84 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 215384 kb
Host smart-ae884ba7-f057-4885-bca5-f8e60f4de9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11571
19510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1157119510
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3727562970
Short name T1793
Test name
Test status
Simulation time 163704942 ps
CPU time 0.88 seconds
Started Jul 30 06:30:53 PM PDT 24
Finished Jul 30 06:30:54 PM PDT 24
Peak memory 206952 kb
Host smart-770accde-68fe-4213-8813-b81dcb2fbd33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37275
62970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3727562970
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2965977393
Short name T225
Test name
Test status
Simulation time 165135961 ps
CPU time 0.93 seconds
Started Jul 30 06:30:48 PM PDT 24
Finished Jul 30 06:30:49 PM PDT 24
Peak memory 206940 kb
Host smart-2b146f11-3144-4c77-a41a-2c817908d6d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29659
77393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2965977393
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3863670932
Short name T2089
Test name
Test status
Simulation time 180949218 ps
CPU time 0.91 seconds
Started Jul 30 06:30:51 PM PDT 24
Finished Jul 30 06:30:52 PM PDT 24
Peak memory 206948 kb
Host smart-28ab2cce-7b23-48a8-be50-ed26d9a3a862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38636
70932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3863670932
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.588207622
Short name T1161
Test name
Test status
Simulation time 179936298 ps
CPU time 0.91 seconds
Started Jul 30 06:30:57 PM PDT 24
Finished Jul 30 06:30:58 PM PDT 24
Peak memory 206956 kb
Host smart-cf9ed501-f72c-4797-b59b-075ed4297825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58820
7622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.588207622
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.164827355
Short name T1302
Test name
Test status
Simulation time 180695035 ps
CPU time 0.9 seconds
Started Jul 30 06:30:52 PM PDT 24
Finished Jul 30 06:30:54 PM PDT 24
Peak memory 206924 kb
Host smart-5351e454-a862-475c-8534-04882867bab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16482
7355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.164827355
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2212560465
Short name T1437
Test name
Test status
Simulation time 248780407 ps
CPU time 0.92 seconds
Started Jul 30 06:30:51 PM PDT 24
Finished Jul 30 06:30:52 PM PDT 24
Peak memory 206876 kb
Host smart-847fd704-3ace-4799-af18-8978f5f6599b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22125
60465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2212560465
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.4190454956
Short name T2497
Test name
Test status
Simulation time 159496250 ps
CPU time 0.84 seconds
Started Jul 30 06:30:57 PM PDT 24
Finished Jul 30 06:30:58 PM PDT 24
Peak memory 206964 kb
Host smart-9942dc12-330d-4a63-94b0-1c99b28dd65d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41904
54956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.4190454956
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1236673320
Short name T1524
Test name
Test status
Simulation time 224289741 ps
CPU time 1 seconds
Started Jul 30 06:30:51 PM PDT 24
Finished Jul 30 06:30:53 PM PDT 24
Peak memory 206944 kb
Host smart-ff01ae91-ce1b-42de-bb7f-9fb71671f3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12366
73320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1236673320
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.1111214176
Short name T2274
Test name
Test status
Simulation time 5747084760 ps
CPU time 41.86 seconds
Started Jul 30 06:30:57 PM PDT 24
Finished Jul 30 06:31:39 PM PDT 24
Peak memory 216732 kb
Host smart-04877d2e-b6b6-498b-b93c-ca8f21ccdcdf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1111214176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.1111214176
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3075003897
Short name T2581
Test name
Test status
Simulation time 160895743 ps
CPU time 0.83 seconds
Started Jul 30 06:30:57 PM PDT 24
Finished Jul 30 06:30:58 PM PDT 24
Peak memory 206880 kb
Host smart-3e132349-b800-4459-8868-2622385cc274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30750
03897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3075003897
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1342302115
Short name T1473
Test name
Test status
Simulation time 185975206 ps
CPU time 0.9 seconds
Started Jul 30 06:30:56 PM PDT 24
Finished Jul 30 06:30:57 PM PDT 24
Peak memory 206916 kb
Host smart-15d3207a-84d4-4d3e-911a-d8e456b6d91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13423
02115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1342302115
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.2982022004
Short name T2384
Test name
Test status
Simulation time 720127510 ps
CPU time 1.94 seconds
Started Jul 30 06:30:53 PM PDT 24
Finished Jul 30 06:30:55 PM PDT 24
Peak memory 206912 kb
Host smart-4e9e3373-1e8e-4af4-b414-5eaaa7fb0a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29820
22004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.2982022004
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1155278103
Short name T545
Test name
Test status
Simulation time 7237028650 ps
CPU time 69.89 seconds
Started Jul 30 06:30:57 PM PDT 24
Finished Jul 30 06:32:07 PM PDT 24
Peak memory 207140 kb
Host smart-a9c1db5f-c46a-4e07-8fea-92a901bfccbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11552
78103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1155278103
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.2344978255
Short name T1733
Test name
Test status
Simulation time 5666090290 ps
CPU time 37.81 seconds
Started Jul 30 06:30:57 PM PDT 24
Finished Jul 30 06:31:35 PM PDT 24
Peak memory 207096 kb
Host smart-c25b2bf5-c453-43ea-88d3-770b0f92a3e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344978255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.2344978255
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.122531916
Short name T206
Test name
Test status
Simulation time 70000272 ps
CPU time 0.68 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:28:12 PM PDT 24
Peak memory 207008 kb
Host smart-54ffb736-eccd-473a-ba58-bc544d9d6cf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=122531916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.122531916
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.3299704762
Short name T2066
Test name
Test status
Simulation time 13365872494 ps
CPU time 16.06 seconds
Started Jul 30 06:28:10 PM PDT 24
Finished Jul 30 06:28:26 PM PDT 24
Peak memory 207144 kb
Host smart-08d983aa-0288-489b-8b82-370fe21b365a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299704762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.3299704762
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1856121640
Short name T887
Test name
Test status
Simulation time 23318424185 ps
CPU time 31.51 seconds
Started Jul 30 06:28:05 PM PDT 24
Finished Jul 30 06:28:37 PM PDT 24
Peak memory 207160 kb
Host smart-a32b766e-9247-4052-9edf-d4c80de41cff
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856121640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.1856121640
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2532412227
Short name T765
Test name
Test status
Simulation time 154734467 ps
CPU time 0.91 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:17 PM PDT 24
Peak memory 206896 kb
Host smart-7ba8fd21-626a-482a-8eb3-f02e1a42cc84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25324
12227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2532412227
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.3533040391
Short name T49
Test name
Test status
Simulation time 147670744 ps
CPU time 0.88 seconds
Started Jul 30 06:28:10 PM PDT 24
Finished Jul 30 06:28:11 PM PDT 24
Peak memory 206928 kb
Host smart-53ad9091-fb83-4294-8ba4-33da9d945839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35330
40391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.3533040391
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.4179746884
Short name T52
Test name
Test status
Simulation time 130708922 ps
CPU time 0.83 seconds
Started Jul 30 06:28:07 PM PDT 24
Finished Jul 30 06:28:08 PM PDT 24
Peak memory 206864 kb
Host smart-eed855eb-0cb3-44ba-9d12-ccd02c774d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41797
46884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.4179746884
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3963615695
Short name T2627
Test name
Test status
Simulation time 136050555 ps
CPU time 0.78 seconds
Started Jul 30 06:28:06 PM PDT 24
Finished Jul 30 06:28:07 PM PDT 24
Peak memory 206852 kb
Host smart-bd9ed813-789c-42ac-af36-00918e51b338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39636
15695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3963615695
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.3822129446
Short name T2029
Test name
Test status
Simulation time 313263627 ps
CPU time 1.32 seconds
Started Jul 30 06:28:07 PM PDT 24
Finished Jul 30 06:28:09 PM PDT 24
Peak memory 206904 kb
Host smart-8b9a2f52-1ad2-42ce-b2e6-4aa9d3c902b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38221
29446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.3822129446
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.2288297741
Short name T722
Test name
Test status
Simulation time 1054339384 ps
CPU time 2.83 seconds
Started Jul 30 06:28:05 PM PDT 24
Finished Jul 30 06:28:08 PM PDT 24
Peak memory 207028 kb
Host smart-f3095496-c61d-4e50-9595-8afb68d35038
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2288297741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.2288297741
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.1720732117
Short name T1819
Test name
Test status
Simulation time 5897701252 ps
CPU time 12.96 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:29 PM PDT 24
Peak memory 207136 kb
Host smart-188cc2f4-0fad-4049-a002-62492b7886ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17207
32117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1720732117
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.2195918697
Short name T1072
Test name
Test status
Simulation time 6782373410 ps
CPU time 45.7 seconds
Started Jul 30 06:28:04 PM PDT 24
Finished Jul 30 06:28:50 PM PDT 24
Peak memory 207168 kb
Host smart-b5072dcc-d283-4361-9792-a352daa03823
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195918697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.2195918697
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.3074790911
Short name T1152
Test name
Test status
Simulation time 336859070 ps
CPU time 1.23 seconds
Started Jul 30 06:28:07 PM PDT 24
Finished Jul 30 06:28:09 PM PDT 24
Peak memory 206880 kb
Host smart-dd565d27-77c4-4198-b737-9d2490a85e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30747
90911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.3074790911
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2558258
Short name T827
Test name
Test status
Simulation time 133825293 ps
CPU time 0.8 seconds
Started Jul 30 06:28:09 PM PDT 24
Finished Jul 30 06:28:10 PM PDT 24
Peak memory 206880 kb
Host smart-c1311461-55d9-43bb-8ca3-74935254ccaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25582
58 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2558258
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2098997554
Short name T2293
Test name
Test status
Simulation time 40198889 ps
CPU time 0.67 seconds
Started Jul 30 06:28:06 PM PDT 24
Finished Jul 30 06:28:07 PM PDT 24
Peak memory 206880 kb
Host smart-64d9ed27-aa3a-4a28-97b9-10ea2a3c6ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20989
97554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2098997554
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1301018154
Short name T1624
Test name
Test status
Simulation time 856312777 ps
CPU time 2.25 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:28:15 PM PDT 24
Peak memory 207016 kb
Host smart-a330354d-d8b3-4a35-8b51-ad801349d06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13010
18154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1301018154
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.930505951
Short name T2618
Test name
Test status
Simulation time 173210724 ps
CPU time 1.92 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 206948 kb
Host smart-143b19a3-19ec-4e98-b918-e2a90fbafdf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93050
5951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.930505951
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1938725681
Short name T30
Test name
Test status
Simulation time 110196633938 ps
CPU time 179.47 seconds
Started Jul 30 06:28:04 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 207140 kb
Host smart-144e5586-698a-4eb6-baff-ad0f531a0b3e
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1938725681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1938725681
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.1889302868
Short name T1130
Test name
Test status
Simulation time 118466051507 ps
CPU time 209.97 seconds
Started Jul 30 06:28:05 PM PDT 24
Finished Jul 30 06:31:35 PM PDT 24
Peak memory 207224 kb
Host smart-bb7e62e4-e8ef-4c7b-974c-b58e8e9fe33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889302868 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.1889302868
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.315006380
Short name T584
Test name
Test status
Simulation time 114150198804 ps
CPU time 178.93 seconds
Started Jul 30 06:28:07 PM PDT 24
Finished Jul 30 06:31:06 PM PDT 24
Peak memory 207164 kb
Host smart-939b45f0-163d-486f-8038-96ab02266113
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=315006380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.315006380
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1639590907
Short name T1967
Test name
Test status
Simulation time 105969376335 ps
CPU time 190.78 seconds
Started Jul 30 06:28:08 PM PDT 24
Finished Jul 30 06:31:19 PM PDT 24
Peak memory 206992 kb
Host smart-1f8b6eb1-fafa-4ce4-9fc6-d365ea8fb99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639590907 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1639590907
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.2174417358
Short name T1095
Test name
Test status
Simulation time 82121138450 ps
CPU time 145.41 seconds
Started Jul 30 06:28:08 PM PDT 24
Finished Jul 30 06:30:33 PM PDT 24
Peak memory 207152 kb
Host smart-f7cc99a0-1e5e-4f3e-8ed6-9d14a4f816f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21744
17358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.2174417358
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1823824151
Short name T2310
Test name
Test status
Simulation time 197306468 ps
CPU time 1 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:17 PM PDT 24
Peak memory 206920 kb
Host smart-ed880a09-de58-479d-a946-ffd2e64cdf4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1823824151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1823824151
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2477618217
Short name T694
Test name
Test status
Simulation time 143075495 ps
CPU time 0.83 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:28:14 PM PDT 24
Peak memory 206872 kb
Host smart-308c4e64-04ff-4d7b-a2c1-895c492b1c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24776
18217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2477618217
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2784508021
Short name T1194
Test name
Test status
Simulation time 236290844 ps
CPU time 1.01 seconds
Started Jul 30 06:28:08 PM PDT 24
Finished Jul 30 06:28:09 PM PDT 24
Peak memory 206908 kb
Host smart-e465c075-d98b-4ece-b9d2-7550d2d4f799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27845
08021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2784508021
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.765629541
Short name T1382
Test name
Test status
Simulation time 8658011434 ps
CPU time 244.43 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:32:20 PM PDT 24
Peak memory 215356 kb
Host smart-da8441ac-1d93-4864-ac22-7672c778218e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=765629541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.765629541
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.163438321
Short name T2099
Test name
Test status
Simulation time 231041983 ps
CPU time 1.04 seconds
Started Jul 30 06:28:09 PM PDT 24
Finished Jul 30 06:28:10 PM PDT 24
Peak memory 206916 kb
Host smart-8d5e04a2-9de0-4e06-80dc-f70ef08860f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16343
8321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.163438321
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.3842825087
Short name T2722
Test name
Test status
Simulation time 23293394439 ps
CPU time 29.57 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:28:40 PM PDT 24
Peak memory 207116 kb
Host smart-cd5ecd28-8955-4f3f-a01b-2e2ed9a117e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38428
25087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.3842825087
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.2542999047
Short name T1956
Test name
Test status
Simulation time 3332163013 ps
CPU time 4.63 seconds
Started Jul 30 06:28:09 PM PDT 24
Finished Jul 30 06:28:14 PM PDT 24
Peak memory 207060 kb
Host smart-08b1cb1e-175e-4fb2-b3a7-25f44212ffaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25429
99047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2542999047
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.3279389120
Short name T1730
Test name
Test status
Simulation time 5466591296 ps
CPU time 157.07 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:30:53 PM PDT 24
Peak memory 215380 kb
Host smart-1527e8b6-1baf-4838-b1ca-1808816c727d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32793
89120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.3279389120
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.1774495672
Short name T1530
Test name
Test status
Simulation time 6679826212 ps
CPU time 50.67 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:29:02 PM PDT 24
Peak memory 207128 kb
Host smart-855f3a89-a5d6-42dc-a368-4f59eef4bfb4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1774495672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.1774495672
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.1087375407
Short name T1224
Test name
Test status
Simulation time 247100831 ps
CPU time 1.03 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:28:12 PM PDT 24
Peak memory 206936 kb
Host smart-2d5d522f-11ac-4beb-b61e-cdc263e7e8ff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1087375407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.1087375407
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.4124588577
Short name T2401
Test name
Test status
Simulation time 192140703 ps
CPU time 0.93 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:28:12 PM PDT 24
Peak memory 206932 kb
Host smart-b4d71fcc-821d-4be1-8f8f-a68e6d2ca2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41245
88577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.4124588577
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.4230243948
Short name T1620
Test name
Test status
Simulation time 4792218674 ps
CPU time 47.42 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:29:03 PM PDT 24
Peak memory 216544 kb
Host smart-b93098c4-b316-43ea-8233-5950e08dc256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42302
43948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.4230243948
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1667624633
Short name T2180
Test name
Test status
Simulation time 3191512861 ps
CPU time 31.96 seconds
Started Jul 30 06:28:06 PM PDT 24
Finished Jul 30 06:28:38 PM PDT 24
Peak memory 216424 kb
Host smart-07d97507-71e4-4182-b32e-8b5e5b215e50
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1667624633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1667624633
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1402216516
Short name T2827
Test name
Test status
Simulation time 175603693 ps
CPU time 0.89 seconds
Started Jul 30 06:28:09 PM PDT 24
Finished Jul 30 06:28:10 PM PDT 24
Peak memory 206920 kb
Host smart-540a2571-6cf3-46b7-b199-1bbced1e8160
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1402216516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1402216516
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.608161972
Short name T844
Test name
Test status
Simulation time 219747539 ps
CPU time 0.94 seconds
Started Jul 30 06:28:08 PM PDT 24
Finished Jul 30 06:28:09 PM PDT 24
Peak memory 206908 kb
Host smart-ebc349ac-44ce-4197-90b4-ef22a1e8462d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60816
1972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.608161972
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.4019629771
Short name T1722
Test name
Test status
Simulation time 200022537 ps
CPU time 0.87 seconds
Started Jul 30 06:28:07 PM PDT 24
Finished Jul 30 06:28:08 PM PDT 24
Peak memory 206888 kb
Host smart-9caa0c89-29dd-4c1d-b656-c1696e5c6ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40196
29771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.4019629771
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.3631872582
Short name T1944
Test name
Test status
Simulation time 142015416 ps
CPU time 0.91 seconds
Started Jul 30 06:28:08 PM PDT 24
Finished Jul 30 06:28:09 PM PDT 24
Peak memory 206904 kb
Host smart-7593f856-eec0-438d-a789-03e704bf8a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36318
72582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.3631872582
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.572234786
Short name T1254
Test name
Test status
Simulation time 183442454 ps
CPU time 0.89 seconds
Started Jul 30 06:28:09 PM PDT 24
Finished Jul 30 06:28:10 PM PDT 24
Peak memory 206912 kb
Host smart-acd3673c-6de1-45fb-8642-3c5d494f4fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57223
4786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.572234786
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1889368690
Short name T2222
Test name
Test status
Simulation time 169896624 ps
CPU time 0.82 seconds
Started Jul 30 06:28:07 PM PDT 24
Finished Jul 30 06:28:08 PM PDT 24
Peak memory 206888 kb
Host smart-2ccf744a-f80b-40ad-8b1b-80c0631826f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18893
68690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1889368690
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1365694495
Short name T159
Test name
Test status
Simulation time 189763714 ps
CPU time 0.86 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:28:12 PM PDT 24
Peak memory 206920 kb
Host smart-0c8f0071-2060-4e22-a096-add05a045647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13656
94495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1365694495
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2518676202
Short name T1563
Test name
Test status
Simulation time 236400184 ps
CPU time 1.04 seconds
Started Jul 30 06:28:10 PM PDT 24
Finished Jul 30 06:28:11 PM PDT 24
Peak memory 206932 kb
Host smart-34c93f65-de43-4c24-a07d-57199dad7f84
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2518676202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2518676202
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1361644964
Short name T533
Test name
Test status
Simulation time 167162095 ps
CPU time 0.89 seconds
Started Jul 30 06:28:15 PM PDT 24
Finished Jul 30 06:28:17 PM PDT 24
Peak memory 206956 kb
Host smart-ae6cfa91-f596-41c7-9019-4c16eebf8736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13616
44964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1361644964
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3797384805
Short name T1023
Test name
Test status
Simulation time 142123567 ps
CPU time 0.8 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:17 PM PDT 24
Peak memory 206884 kb
Host smart-10407339-8243-492f-bdc0-3942d5ec5442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37973
84805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3797384805
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3617273697
Short name T690
Test name
Test status
Simulation time 282572920 ps
CPU time 1.07 seconds
Started Jul 30 06:28:14 PM PDT 24
Finished Jul 30 06:28:15 PM PDT 24
Peak memory 206912 kb
Host smart-dbd0da3f-0d38-4467-aec8-e0fdaf32f81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36172
73697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3617273697
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3740022683
Short name T175
Test name
Test status
Simulation time 12081214666 ps
CPU time 87.83 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:29:41 PM PDT 24
Peak memory 217264 kb
Host smart-0c4ffd2a-b242-42ed-bcba-fbe7b6e9102b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740022683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3740022683
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1661683010
Short name T161
Test name
Test status
Simulation time 9724110873 ps
CPU time 182.93 seconds
Started Jul 30 06:28:12 PM PDT 24
Finished Jul 30 06:31:15 PM PDT 24
Peak memory 215380 kb
Host smart-8268f057-363e-48fe-a45b-f27b549beb9b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1661683010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1661683010
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2886122271
Short name T2358
Test name
Test status
Simulation time 11632334961 ps
CPU time 241.06 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:32:17 PM PDT 24
Peak memory 215376 kb
Host smart-778618d4-86d6-476a-9d15-54d8e9d5262d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886122271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2886122271
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.908960811
Short name T1924
Test name
Test status
Simulation time 170704278 ps
CPU time 0.85 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 206952 kb
Host smart-da17678d-eebc-4b5a-8bc6-9f7b05080897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90896
0811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.908960811
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.1778651009
Short name T325
Test name
Test status
Simulation time 205975453 ps
CPU time 0.87 seconds
Started Jul 30 06:28:12 PM PDT 24
Finished Jul 30 06:28:13 PM PDT 24
Peak memory 206916 kb
Host smart-126b3b8f-4933-4590-ab24-0bc46394646e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17786
51009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.1778651009
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.2762871559
Short name T1380
Test name
Test status
Simulation time 138827107 ps
CPU time 0.82 seconds
Started Jul 30 06:28:12 PM PDT 24
Finished Jul 30 06:28:13 PM PDT 24
Peak memory 206880 kb
Host smart-f8786613-54fe-43cb-9e52-02dff74a8f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27628
71559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.2762871559
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1209309541
Short name T69
Test name
Test status
Simulation time 150082387 ps
CPU time 0.83 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:17 PM PDT 24
Peak memory 206940 kb
Host smart-fe5190bf-708a-4b04-9ccf-e7714128ee04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12093
09541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1209309541
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2153898137
Short name T186
Test name
Test status
Simulation time 342532496 ps
CPU time 1.19 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:28:12 PM PDT 24
Peak memory 222944 kb
Host smart-83bd9bf2-f222-4718-8ce9-5b4b132c3a30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2153898137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2153898137
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.3924289554
Short name T44
Test name
Test status
Simulation time 416442661 ps
CPU time 1.51 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:28:13 PM PDT 24
Peak memory 206872 kb
Host smart-28f24a8f-3629-4488-ab0b-7c932a1798c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39242
89554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3924289554
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.2955655928
Short name T1999
Test name
Test status
Simulation time 161601463 ps
CPU time 0.88 seconds
Started Jul 30 06:28:10 PM PDT 24
Finished Jul 30 06:28:11 PM PDT 24
Peak memory 206880 kb
Host smart-d0e5f807-ad18-4646-a850-6790fd2d58a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29556
55928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.2955655928
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3706616606
Short name T1594
Test name
Test status
Simulation time 166592525 ps
CPU time 0.92 seconds
Started Jul 30 06:28:14 PM PDT 24
Finished Jul 30 06:28:15 PM PDT 24
Peak memory 206904 kb
Host smart-72cef2bb-6aa1-48c1-914e-21c959af0405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37066
16606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3706616606
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3174299264
Short name T977
Test name
Test status
Simulation time 151902625 ps
CPU time 0.81 seconds
Started Jul 30 06:28:10 PM PDT 24
Finished Jul 30 06:28:11 PM PDT 24
Peak memory 206940 kb
Host smart-e0d8ad27-9822-45f6-a652-16cc814e7894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31742
99264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3174299264
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2124983496
Short name T1176
Test name
Test status
Simulation time 223043626 ps
CPU time 1.01 seconds
Started Jul 30 06:28:10 PM PDT 24
Finished Jul 30 06:28:11 PM PDT 24
Peak memory 206972 kb
Host smart-2ccad865-985d-4257-9b92-a688e8a7b8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21249
83496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2124983496
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.4157313121
Short name T2367
Test name
Test status
Simulation time 4489564678 ps
CPU time 33.94 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:28:45 PM PDT 24
Peak memory 216784 kb
Host smart-3bf68625-8246-4ebf-bba5-6a60f07615d3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4157313121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.4157313121
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3481279395
Short name T1387
Test name
Test status
Simulation time 180561730 ps
CPU time 0.91 seconds
Started Jul 30 06:28:10 PM PDT 24
Finished Jul 30 06:28:12 PM PDT 24
Peak memory 206920 kb
Host smart-d73d04cb-c6c1-469f-85b6-90b1dae6d010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34812
79395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3481279395
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2183845238
Short name T386
Test name
Test status
Simulation time 162828294 ps
CPU time 0.91 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:17 PM PDT 24
Peak memory 206908 kb
Host smart-0d7ed2ba-7573-4ca6-9876-5d4b35eac74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21838
45238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2183845238
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.4045906161
Short name T2009
Test name
Test status
Simulation time 647751013 ps
CPU time 1.85 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:20 PM PDT 24
Peak memory 206888 kb
Host smart-c7dd7ded-620b-431d-8af3-91071bbe5611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40459
06161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.4045906161
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.1115942974
Short name T1068
Test name
Test status
Simulation time 6670870514 ps
CPU time 195.11 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:31:26 PM PDT 24
Peak memory 215300 kb
Host smart-52508302-965d-4102-94ad-d9c3006dfa49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11159
42974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.1115942974
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.547340305
Short name T916
Test name
Test status
Simulation time 3862148527 ps
CPU time 31.83 seconds
Started Jul 30 06:28:06 PM PDT 24
Finished Jul 30 06:28:38 PM PDT 24
Peak memory 207148 kb
Host smart-cd97ae50-5bc4-461a-9169-60924a5da19c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547340305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host_
handshake.547340305
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3629872713
Short name T2492
Test name
Test status
Simulation time 41681874 ps
CPU time 0.7 seconds
Started Jul 30 06:31:04 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 206936 kb
Host smart-4a1c2494-ac6e-4846-8a01-6b6bd37eb3aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3629872713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3629872713
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.519479259
Short name T528
Test name
Test status
Simulation time 4296385683 ps
CPU time 6.16 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 207168 kb
Host smart-0979b3fa-bd2b-49c4-aebf-b249e3a53418
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519479259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_ao
n_wake_disconnect.519479259
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1138738903
Short name T713
Test name
Test status
Simulation time 13334752199 ps
CPU time 14.79 seconds
Started Jul 30 06:30:48 PM PDT 24
Finished Jul 30 06:31:03 PM PDT 24
Peak memory 207124 kb
Host smart-4d527f44-43a8-446e-85ef-1fa3833d8e64
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138738903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1138738903
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.866143589
Short name T1045
Test name
Test status
Simulation time 23425845502 ps
CPU time 28.75 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:31:28 PM PDT 24
Peak memory 207128 kb
Host smart-618f7d68-89e6-4f84-934e-b9a4c4d03ff8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866143589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_ao
n_wake_resume.866143589
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3999975179
Short name T731
Test name
Test status
Simulation time 183522457 ps
CPU time 1.02 seconds
Started Jul 30 06:30:50 PM PDT 24
Finished Jul 30 06:30:51 PM PDT 24
Peak memory 206932 kb
Host smart-478b85b5-050f-476f-8893-3147e4cfcbec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39999
75179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3999975179
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.2770876276
Short name T661
Test name
Test status
Simulation time 151060838 ps
CPU time 0.8 seconds
Started Jul 30 06:30:51 PM PDT 24
Finished Jul 30 06:30:52 PM PDT 24
Peak memory 206876 kb
Host smart-a7249a01-00c2-4651-a0d5-5aebe45728ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27708
76276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.2770876276
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.295746999
Short name T2767
Test name
Test status
Simulation time 274920985 ps
CPU time 1.11 seconds
Started Jul 30 06:30:56 PM PDT 24
Finished Jul 30 06:30:58 PM PDT 24
Peak memory 206960 kb
Host smart-1546be76-1a11-4940-832e-8967b112e56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29574
6999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.295746999
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2628235414
Short name T902
Test name
Test status
Simulation time 355300244 ps
CPU time 1.36 seconds
Started Jul 30 06:30:57 PM PDT 24
Finished Jul 30 06:30:59 PM PDT 24
Peak memory 206944 kb
Host smart-0b0c1004-b65b-43bb-924d-f76fd2d40b8d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2628235414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2628235414
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.190767581
Short name T886
Test name
Test status
Simulation time 17390697724 ps
CPU time 33.88 seconds
Started Jul 30 06:30:55 PM PDT 24
Finished Jul 30 06:31:29 PM PDT 24
Peak memory 207192 kb
Host smart-f08384bf-595f-4239-b879-35a15b1171b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19076
7581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.190767581
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.2177788594
Short name T2532
Test name
Test status
Simulation time 291407365 ps
CPU time 4.64 seconds
Started Jul 30 06:30:59 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 206988 kb
Host smart-fa772118-5abf-4daf-b24d-e0cb8ce09f09
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177788594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.2177788594
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.1273784289
Short name T1168
Test name
Test status
Simulation time 350878938 ps
CPU time 1.27 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 206872 kb
Host smart-2053d9ce-7cd3-418a-ad26-a8deeda80c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12737
84289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.1273784289
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2156608421
Short name T1671
Test name
Test status
Simulation time 141665369 ps
CPU time 0.94 seconds
Started Jul 30 06:31:00 PM PDT 24
Finished Jul 30 06:31:02 PM PDT 24
Peak memory 206916 kb
Host smart-4a4a401a-89d9-4a10-a185-90db349339d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21566
08421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2156608421
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3281574608
Short name T2067
Test name
Test status
Simulation time 84730239 ps
CPU time 0.79 seconds
Started Jul 30 06:31:00 PM PDT 24
Finished Jul 30 06:31:01 PM PDT 24
Peak memory 206952 kb
Host smart-2cd552c1-2e2e-4ac5-8ad3-52a2a27ca46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32815
74608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3281574608
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3842728456
Short name T638
Test name
Test status
Simulation time 880979651 ps
CPU time 2.31 seconds
Started Jul 30 06:30:55 PM PDT 24
Finished Jul 30 06:30:57 PM PDT 24
Peak memory 206964 kb
Host smart-4d435a15-e6bb-4b19-9531-f0ea33521aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38427
28456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3842728456
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.65442462
Short name T1772
Test name
Test status
Simulation time 236944678 ps
CPU time 1.64 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 206992 kb
Host smart-f3bdfda8-731e-4a28-b4c4-80f3c6aa4711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65442
462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.65442462
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.4278168284
Short name T942
Test name
Test status
Simulation time 273028405 ps
CPU time 1.25 seconds
Started Jul 30 06:30:57 PM PDT 24
Finished Jul 30 06:30:59 PM PDT 24
Peak memory 207000 kb
Host smart-fc0d06fb-9efe-4eac-a81f-3116ac3be624
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4278168284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.4278168284
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.143725610
Short name T1257
Test name
Test status
Simulation time 155166176 ps
CPU time 0.88 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 206896 kb
Host smart-5244321d-a6bf-4238-b594-a09bb4ff7858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14372
5610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.143725610
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1802862688
Short name T687
Test name
Test status
Simulation time 194739100 ps
CPU time 0.93 seconds
Started Jul 30 06:31:01 PM PDT 24
Finished Jul 30 06:31:02 PM PDT 24
Peak memory 206904 kb
Host smart-c5645557-9759-4240-870a-c1f1afe77f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18028
62688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1802862688
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.912154813
Short name T1201
Test name
Test status
Simulation time 10521441154 ps
CPU time 114.42 seconds
Started Jul 30 06:31:04 PM PDT 24
Finished Jul 30 06:32:58 PM PDT 24
Peak memory 216860 kb
Host smart-53650d6e-8acc-42fd-ae58-f840bbbfbaab
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=912154813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.912154813
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.2011565882
Short name T2832
Test name
Test status
Simulation time 3429728877 ps
CPU time 44.54 seconds
Started Jul 30 06:30:52 PM PDT 24
Finished Jul 30 06:31:37 PM PDT 24
Peak memory 207120 kb
Host smart-bc9d9777-4350-4ada-85d8-1be6f90b2284
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2011565882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.2011565882
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.470110486
Short name T2540
Test name
Test status
Simulation time 208770997 ps
CPU time 0.97 seconds
Started Jul 30 06:30:59 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 206944 kb
Host smart-3cd6b682-a05f-40dd-89e3-b6fc7a23b154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47011
0486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.470110486
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.3368955025
Short name T2135
Test name
Test status
Simulation time 23271339437 ps
CPU time 29.41 seconds
Started Jul 30 06:31:00 PM PDT 24
Finished Jul 30 06:31:30 PM PDT 24
Peak memory 207108 kb
Host smart-f9e842a4-f7bf-4a96-864b-00a744a7a5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33689
55025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.3368955025
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.1213164244
Short name T492
Test name
Test status
Simulation time 3309815036 ps
CPU time 5.45 seconds
Started Jul 30 06:30:57 PM PDT 24
Finished Jul 30 06:31:03 PM PDT 24
Peak memory 207028 kb
Host smart-04e73329-7a68-41f0-a42b-c1bc36dae00c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12131
64244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1213164244
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.4218881076
Short name T1200
Test name
Test status
Simulation time 5324080740 ps
CPU time 37.99 seconds
Started Jul 30 06:30:59 PM PDT 24
Finished Jul 30 06:31:37 PM PDT 24
Peak memory 223252 kb
Host smart-d9e5e8a2-4192-4a29-b945-87e362d19267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42188
81076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.4218881076
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2066409197
Short name T1470
Test name
Test status
Simulation time 5981308793 ps
CPU time 62.09 seconds
Started Jul 30 06:31:04 PM PDT 24
Finished Jul 30 06:32:06 PM PDT 24
Peak memory 207100 kb
Host smart-3033950c-afb6-4457-9779-578d140b9731
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2066409197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2066409197
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.3998275935
Short name T2784
Test name
Test status
Simulation time 240397280 ps
CPU time 1 seconds
Started Jul 30 06:30:54 PM PDT 24
Finished Jul 30 06:30:55 PM PDT 24
Peak memory 206956 kb
Host smart-dab6d778-1a9e-44ec-afd2-99315962513c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3998275935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.3998275935
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.939116956
Short name T1055
Test name
Test status
Simulation time 194187426 ps
CPU time 0.95 seconds
Started Jul 30 06:31:14 PM PDT 24
Finished Jul 30 06:31:15 PM PDT 24
Peak memory 206928 kb
Host smart-79b9bfc8-85bd-4d2c-a5c4-5d5c353f7c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93911
6956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.939116956
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.294538403
Short name T543
Test name
Test status
Simulation time 3446239005 ps
CPU time 99.1 seconds
Started Jul 30 06:30:54 PM PDT 24
Finished Jul 30 06:32:34 PM PDT 24
Peak memory 215400 kb
Host smart-b84f84af-0527-425d-9259-677ab62976d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29453
8403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.294538403
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2369419878
Short name T406
Test name
Test status
Simulation time 7083569348 ps
CPU time 68.16 seconds
Started Jul 30 06:30:54 PM PDT 24
Finished Jul 30 06:32:02 PM PDT 24
Peak memory 207124 kb
Host smart-8556b61a-f0ba-4ef2-91c7-ed10695e597b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2369419878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2369419878
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.3788755914
Short name T1735
Test name
Test status
Simulation time 158574833 ps
CPU time 0.91 seconds
Started Jul 30 06:30:55 PM PDT 24
Finished Jul 30 06:30:56 PM PDT 24
Peak memory 206924 kb
Host smart-ce074d5f-3324-4657-82fd-af57f9baddec
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3788755914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.3788755914
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1078052517
Short name T1989
Test name
Test status
Simulation time 161410067 ps
CPU time 0.85 seconds
Started Jul 30 06:31:08 PM PDT 24
Finished Jul 30 06:31:09 PM PDT 24
Peak memory 206904 kb
Host smart-2b1eb276-6319-4986-88e7-59806bcb87f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10780
52517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1078052517
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2603966003
Short name T1889
Test name
Test status
Simulation time 174140367 ps
CPU time 0.88 seconds
Started Jul 30 06:30:54 PM PDT 24
Finished Jul 30 06:30:55 PM PDT 24
Peak memory 206968 kb
Host smart-3be43934-7ba1-4c62-ac14-0d879fefe6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26039
66003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2603966003
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1178106524
Short name T592
Test name
Test status
Simulation time 195802303 ps
CPU time 1 seconds
Started Jul 30 06:30:57 PM PDT 24
Finished Jul 30 06:30:58 PM PDT 24
Peak memory 206908 kb
Host smart-eae91dfd-e0f7-444e-a3eb-dca6f6113eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11781
06524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1178106524
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.656813525
Short name T1748
Test name
Test status
Simulation time 255872021 ps
CPU time 0.96 seconds
Started Jul 30 06:31:03 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 206964 kb
Host smart-d93362aa-8d8c-46aa-afbc-67e2e814a035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65681
3525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.656813525
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.4213700373
Short name T1585
Test name
Test status
Simulation time 153997821 ps
CPU time 0.83 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:30:59 PM PDT 24
Peak memory 206916 kb
Host smart-3c6b9738-62d5-41e2-b6ad-a9f37747ebc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42137
00373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.4213700373
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.1800509866
Short name T1567
Test name
Test status
Simulation time 252241676 ps
CPU time 1.05 seconds
Started Jul 30 06:30:55 PM PDT 24
Finished Jul 30 06:30:57 PM PDT 24
Peak memory 206920 kb
Host smart-b24ba47d-5a0a-4b24-ac61-5b748acc02c9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1800509866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.1800509866
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3064140074
Short name T244
Test name
Test status
Simulation time 232864098 ps
CPU time 0.94 seconds
Started Jul 30 06:31:02 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 206892 kb
Host smart-7d578761-7a23-40ee-acad-3dd9fa106863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30641
40074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3064140074
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.496700013
Short name T1391
Test name
Test status
Simulation time 45517958 ps
CPU time 0.71 seconds
Started Jul 30 06:31:02 PM PDT 24
Finished Jul 30 06:31:03 PM PDT 24
Peak memory 206872 kb
Host smart-734d5c6a-668c-438e-9c0f-bb07f5abb032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49670
0013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.496700013
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.262511831
Short name T254
Test name
Test status
Simulation time 17046324737 ps
CPU time 42.45 seconds
Started Jul 30 06:31:00 PM PDT 24
Finished Jul 30 06:31:43 PM PDT 24
Peak memory 215432 kb
Host smart-47c04baa-745c-4cf7-a8f1-5e6084d89dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26251
1831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.262511831
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.4269881262
Short name T287
Test name
Test status
Simulation time 161849818 ps
CPU time 0.87 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:30:59 PM PDT 24
Peak memory 206920 kb
Host smart-69262c62-1248-41f1-a796-917e1a9f6dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42698
81262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.4269881262
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2816656751
Short name T1207
Test name
Test status
Simulation time 202904431 ps
CPU time 0.9 seconds
Started Jul 30 06:31:03 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 206952 kb
Host smart-da3793c0-9499-496b-bfce-78216725b191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28166
56751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2816656751
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3712729162
Short name T1957
Test name
Test status
Simulation time 244943676 ps
CPU time 0.99 seconds
Started Jul 30 06:31:00 PM PDT 24
Finished Jul 30 06:31:01 PM PDT 24
Peak memory 206904 kb
Host smart-aebc1bb2-bf10-4ef4-bf20-3f7c02f24944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37127
29162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3712729162
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.2729178761
Short name T705
Test name
Test status
Simulation time 202015501 ps
CPU time 0.92 seconds
Started Jul 30 06:31:03 PM PDT 24
Finished Jul 30 06:31:05 PM PDT 24
Peak memory 206908 kb
Host smart-0aa8ba6b-7c03-482e-a007-46c1222882c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27291
78761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.2729178761
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.56510329
Short name T783
Test name
Test status
Simulation time 166192954 ps
CPU time 0.91 seconds
Started Jul 30 06:31:03 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 206916 kb
Host smart-68052345-bbfb-4da1-9355-a9c8d1796902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56510
329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.56510329
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2534447724
Short name T1610
Test name
Test status
Simulation time 151819692 ps
CPU time 0.91 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:30:59 PM PDT 24
Peak memory 206872 kb
Host smart-acf0a7ac-9121-45ce-9a40-7ade209cf5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25344
47724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2534447724
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1286854270
Short name T1500
Test name
Test status
Simulation time 157031620 ps
CPU time 0.83 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:30:59 PM PDT 24
Peak memory 206912 kb
Host smart-d2d17098-b6fc-4f26-9556-9de53121dba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12868
54270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1286854270
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1260628145
Short name T619
Test name
Test status
Simulation time 241464473 ps
CPU time 1.06 seconds
Started Jul 30 06:30:55 PM PDT 24
Finished Jul 30 06:30:56 PM PDT 24
Peak memory 206916 kb
Host smart-17de3231-e425-4988-b6d1-13a318fe7f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12606
28145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1260628145
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1587425355
Short name T784
Test name
Test status
Simulation time 4685977425 ps
CPU time 142 seconds
Started Jul 30 06:30:59 PM PDT 24
Finished Jul 30 06:33:21 PM PDT 24
Peak memory 215372 kb
Host smart-6c874bbc-ab96-4124-80aa-c64bc266e5f4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1587425355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1587425355
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1519173477
Short name T698
Test name
Test status
Simulation time 153666213 ps
CPU time 0.85 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:30:59 PM PDT 24
Peak memory 206980 kb
Host smart-fb2d63a7-e30b-4e5d-bc05-f506af6f74f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15191
73477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1519173477
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1957169744
Short name T653
Test name
Test status
Simulation time 174340845 ps
CPU time 0.89 seconds
Started Jul 30 06:30:59 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 206908 kb
Host smart-43d4ed41-e6ad-45cf-b06b-a81a647830c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19571
69744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1957169744
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.3390112735
Short name T1833
Test name
Test status
Simulation time 562908220 ps
CPU time 1.68 seconds
Started Jul 30 06:31:01 PM PDT 24
Finished Jul 30 06:31:03 PM PDT 24
Peak memory 206928 kb
Host smart-f94dea1f-d276-46c4-a743-4d980dceca64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33901
12735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.3390112735
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.3983510214
Short name T1469
Test name
Test status
Simulation time 4375623096 ps
CPU time 44.26 seconds
Started Jul 30 06:31:00 PM PDT 24
Finished Jul 30 06:31:44 PM PDT 24
Peak memory 216804 kb
Host smart-98b3a30f-93d3-4e52-bd14-4555fd509a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39835
10214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.3983510214
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.2794568622
Short name T310
Test name
Test status
Simulation time 2922505738 ps
CPU time 18.3 seconds
Started Jul 30 06:30:52 PM PDT 24
Finished Jul 30 06:31:10 PM PDT 24
Peak memory 207148 kb
Host smart-123564b8-d285-4dcf-9812-dc08444b3aba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794568622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.2794568622
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.2940898488
Short name T1465
Test name
Test status
Simulation time 56820375 ps
CPU time 0.68 seconds
Started Jul 30 06:31:08 PM PDT 24
Finished Jul 30 06:31:09 PM PDT 24
Peak memory 206944 kb
Host smart-bd4de4f4-2544-4452-8082-35e24c2558d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2940898488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.2940898488
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.765962287
Short name T1313
Test name
Test status
Simulation time 4157343120 ps
CPU time 6.37 seconds
Started Jul 30 06:31:05 PM PDT 24
Finished Jul 30 06:31:12 PM PDT 24
Peak memory 207040 kb
Host smart-15b02226-c2d1-44c5-a121-2606484ccf42
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765962287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_ao
n_wake_disconnect.765962287
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.2624240029
Short name T2337
Test name
Test status
Simulation time 13353795684 ps
CPU time 14.45 seconds
Started Jul 30 06:30:55 PM PDT 24
Finished Jul 30 06:31:09 PM PDT 24
Peak memory 207108 kb
Host smart-f38ad6c1-f36a-41f7-b88b-287bc3a5ac3d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624240029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2624240029
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.4045191292
Short name T610
Test name
Test status
Simulation time 23383423543 ps
CPU time 27.57 seconds
Started Jul 30 06:30:55 PM PDT 24
Finished Jul 30 06:31:23 PM PDT 24
Peak memory 207104 kb
Host smart-b4c0e4b2-18ce-4d32-a79a-e18886b2cdd7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045191292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.4045191292
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.217802356
Short name T2266
Test name
Test status
Simulation time 204190407 ps
CPU time 0.98 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:30:59 PM PDT 24
Peak memory 206976 kb
Host smart-911e2f4d-03f1-41cc-8e0c-ba2b797ff565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21780
2356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.217802356
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.4271660711
Short name T1666
Test name
Test status
Simulation time 139703582 ps
CPU time 0.83 seconds
Started Jul 30 06:31:02 PM PDT 24
Finished Jul 30 06:31:03 PM PDT 24
Peak memory 206952 kb
Host smart-bd880071-477e-43fd-8407-d29ebc7bbdfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42716
60711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.4271660711
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.3243936427
Short name T1759
Test name
Test status
Simulation time 198778885 ps
CPU time 1 seconds
Started Jul 30 06:31:00 PM PDT 24
Finished Jul 30 06:31:02 PM PDT 24
Peak memory 206948 kb
Host smart-5300641a-621c-47b0-b319-e287a91bf7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32439
36427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.3243936427
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.1838852586
Short name T1761
Test name
Test status
Simulation time 1225279975 ps
CPU time 3.29 seconds
Started Jul 30 06:30:58 PM PDT 24
Finished Jul 30 06:31:02 PM PDT 24
Peak memory 207056 kb
Host smart-9f30c443-ca11-4365-be60-e811cd28b5b4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1838852586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.1838852586
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.141167445
Short name T1515
Test name
Test status
Simulation time 6266484139 ps
CPU time 14.71 seconds
Started Jul 30 06:30:55 PM PDT 24
Finished Jul 30 06:31:09 PM PDT 24
Peak memory 207164 kb
Host smart-c456920e-0159-451a-b511-79bda7cd0587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14116
7445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.141167445
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.1843887934
Short name T2190
Test name
Test status
Simulation time 5624480589 ps
CPU time 36.72 seconds
Started Jul 30 06:31:04 PM PDT 24
Finished Jul 30 06:31:41 PM PDT 24
Peak memory 207140 kb
Host smart-db19389f-d6e6-4e33-a8d4-7f91110d5009
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843887934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.1843887934
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.648908363
Short name T376
Test name
Test status
Simulation time 347704525 ps
CPU time 1.32 seconds
Started Jul 30 06:31:00 PM PDT 24
Finished Jul 30 06:31:02 PM PDT 24
Peak memory 206872 kb
Host smart-6d1c17c1-d71a-4259-9aa9-56cd17e6aff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64890
8363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.648908363
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.2704513728
Short name T2579
Test name
Test status
Simulation time 205614864 ps
CPU time 0.96 seconds
Started Jul 30 06:31:05 PM PDT 24
Finished Jul 30 06:31:07 PM PDT 24
Peak memory 206880 kb
Host smart-646efb1c-c45e-496f-a516-7d2e4de72fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27045
13728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.2704513728
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1630549503
Short name T1412
Test name
Test status
Simulation time 91352430 ps
CPU time 0.78 seconds
Started Jul 30 06:30:59 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 206872 kb
Host smart-c9e90d0c-b852-4a38-a2b5-a98a79719b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16305
49503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1630549503
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3976745903
Short name T2004
Test name
Test status
Simulation time 973022866 ps
CPU time 2.57 seconds
Started Jul 30 06:31:03 PM PDT 24
Finished Jul 30 06:31:06 PM PDT 24
Peak memory 207056 kb
Host smart-6c3251bd-ff18-4a8f-8eca-414853e5601b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39767
45903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3976745903
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1240295915
Short name T511
Test name
Test status
Simulation time 195762415 ps
CPU time 1.6 seconds
Started Jul 30 06:30:59 PM PDT 24
Finished Jul 30 06:31:01 PM PDT 24
Peak memory 206996 kb
Host smart-e8aa1099-9b8c-4285-85ca-d01ab11857e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12402
95915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1240295915
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.158948310
Short name T2425
Test name
Test status
Simulation time 210943731 ps
CPU time 1.13 seconds
Started Jul 30 06:31:01 PM PDT 24
Finished Jul 30 06:31:02 PM PDT 24
Peak memory 215208 kb
Host smart-284a50af-67c2-4948-9719-e8003bec594e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=158948310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.158948310
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.572083354
Short name T1191
Test name
Test status
Simulation time 152831513 ps
CPU time 0.83 seconds
Started Jul 30 06:31:04 PM PDT 24
Finished Jul 30 06:31:05 PM PDT 24
Peak memory 206480 kb
Host smart-20c2d22e-bb23-4c87-960f-4a79cab724dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57208
3354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.572083354
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.346073300
Short name T1672
Test name
Test status
Simulation time 188858880 ps
CPU time 0.93 seconds
Started Jul 30 06:30:59 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 206980 kb
Host smart-845f2a04-dbfa-4052-b540-f9a989167e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34607
3300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.346073300
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.539682591
Short name T1165
Test name
Test status
Simulation time 7914407128 ps
CPU time 225.16 seconds
Started Jul 30 06:31:04 PM PDT 24
Finished Jul 30 06:34:49 PM PDT 24
Peak memory 215360 kb
Host smart-9cc883bf-fa1b-464e-a0fa-38bee5591a18
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=539682591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.539682591
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.4025130589
Short name T1133
Test name
Test status
Simulation time 5920766269 ps
CPU time 72.26 seconds
Started Jul 30 06:31:02 PM PDT 24
Finished Jul 30 06:32:15 PM PDT 24
Peak memory 207168 kb
Host smart-b0373bba-e0e6-4209-9d3e-24429a9bc4c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4025130589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.4025130589
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.245681807
Short name T1020
Test name
Test status
Simulation time 181703073 ps
CPU time 1.07 seconds
Started Jul 30 06:31:02 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 206908 kb
Host smart-f2338e42-7985-4609-a07b-97025762d1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24568
1807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.245681807
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.596908049
Short name T702
Test name
Test status
Simulation time 23369987761 ps
CPU time 29.13 seconds
Started Jul 30 06:30:59 PM PDT 24
Finished Jul 30 06:31:28 PM PDT 24
Peak memory 207164 kb
Host smart-0a7ee523-003d-4ec4-9446-d9ec2e595f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59690
8049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.596908049
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.450104250
Short name T1164
Test name
Test status
Simulation time 3262237311 ps
CPU time 5.19 seconds
Started Jul 30 06:31:02 PM PDT 24
Finished Jul 30 06:31:07 PM PDT 24
Peak memory 207112 kb
Host smart-086eeb8e-a310-4bb8-86ca-2c3416415a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45010
4250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.450104250
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.506000414
Short name T1278
Test name
Test status
Simulation time 5322341552 ps
CPU time 151.34 seconds
Started Jul 30 06:30:59 PM PDT 24
Finished Jul 30 06:33:31 PM PDT 24
Peak memory 215352 kb
Host smart-81ea5567-147f-473e-95ab-dd7d2bf27c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50600
0414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.506000414
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2798124164
Short name T2362
Test name
Test status
Simulation time 7169096462 ps
CPU time 73.09 seconds
Started Jul 30 06:31:03 PM PDT 24
Finished Jul 30 06:32:17 PM PDT 24
Peak memory 207172 kb
Host smart-35f26878-24e9-42cd-aa49-67d4edfc03c0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2798124164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2798124164
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.4011362859
Short name T2116
Test name
Test status
Simulation time 241415565 ps
CPU time 1.13 seconds
Started Jul 30 06:31:02 PM PDT 24
Finished Jul 30 06:31:03 PM PDT 24
Peak memory 206976 kb
Host smart-05ef72d4-df8a-4e10-a793-4ee6eccaaa2a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4011362859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.4011362859
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2090514996
Short name T357
Test name
Test status
Simulation time 202712658 ps
CPU time 0.95 seconds
Started Jul 30 06:31:04 PM PDT 24
Finished Jul 30 06:31:06 PM PDT 24
Peak memory 206916 kb
Host smart-d069f51d-c9e0-4907-9b53-49ef433422cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20905
14996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2090514996
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.834960714
Short name T400
Test name
Test status
Simulation time 5325139444 ps
CPU time 53.09 seconds
Started Jul 30 06:31:08 PM PDT 24
Finished Jul 30 06:32:01 PM PDT 24
Peak memory 216752 kb
Host smart-9b1ecbdd-6c54-455f-a352-a3b80d3385c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83496
0714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.834960714
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1963615221
Short name T2149
Test name
Test status
Simulation time 6903117311 ps
CPU time 201.84 seconds
Started Jul 30 06:31:05 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 215328 kb
Host smart-85558b9f-7a35-4817-b315-47b8e0e3098b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1963615221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1963615221
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.3646686043
Short name T1695
Test name
Test status
Simulation time 148733561 ps
CPU time 0.87 seconds
Started Jul 30 06:31:00 PM PDT 24
Finished Jul 30 06:31:01 PM PDT 24
Peak memory 206960 kb
Host smart-fb596503-04ad-4406-aac0-c2e029e04770
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3646686043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.3646686043
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3974400741
Short name T715
Test name
Test status
Simulation time 162601000 ps
CPU time 0.9 seconds
Started Jul 30 06:31:04 PM PDT 24
Finished Jul 30 06:31:05 PM PDT 24
Peak memory 206940 kb
Host smart-1bd71477-832b-49e8-9d3a-f727d6882953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39744
00741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3974400741
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.4224348611
Short name T2258
Test name
Test status
Simulation time 280507499 ps
CPU time 1 seconds
Started Jul 30 06:31:04 PM PDT 24
Finished Jul 30 06:31:05 PM PDT 24
Peak memory 206436 kb
Host smart-ab4b82a5-8cad-4fd3-9a57-f62e0ca470d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42243
48611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.4224348611
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2330073140
Short name T1307
Test name
Test status
Simulation time 209261366 ps
CPU time 0.91 seconds
Started Jul 30 06:30:59 PM PDT 24
Finished Jul 30 06:31:00 PM PDT 24
Peak memory 206716 kb
Host smart-8631b069-b563-48b1-8e6c-2029ac3895ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23300
73140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2330073140
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.612286817
Short name T1026
Test name
Test status
Simulation time 181845772 ps
CPU time 0.86 seconds
Started Jul 30 06:31:04 PM PDT 24
Finished Jul 30 06:31:05 PM PDT 24
Peak memory 206896 kb
Host smart-6746c0e8-8939-4f0f-9fcc-1f3a3f6b5cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61228
6817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.612286817
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.4128514547
Short name T2236
Test name
Test status
Simulation time 188192514 ps
CPU time 0.91 seconds
Started Jul 30 06:31:06 PM PDT 24
Finished Jul 30 06:31:07 PM PDT 24
Peak memory 206912 kb
Host smart-942c52f7-f7dd-487a-839a-17f274873565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41285
14547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.4128514547
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.255320158
Short name T2612
Test name
Test status
Simulation time 201074064 ps
CPU time 0.93 seconds
Started Jul 30 06:31:03 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 206908 kb
Host smart-4b534f55-4669-46ec-a99c-ebcb2a47ec4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25532
0158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.255320158
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.2355541008
Short name T625
Test name
Test status
Simulation time 269388513 ps
CPU time 1.03 seconds
Started Jul 30 06:31:02 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 206936 kb
Host smart-2fae3317-e615-444b-9b8e-ae1f0b40b158
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2355541008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2355541008
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1637190609
Short name T345
Test name
Test status
Simulation time 212802488 ps
CPU time 0.91 seconds
Started Jul 30 06:31:05 PM PDT 24
Finished Jul 30 06:31:07 PM PDT 24
Peak memory 206884 kb
Host smart-85ab9a7f-9d02-4af3-9e3e-b569cb8c70fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16371
90609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1637190609
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3229535458
Short name T1916
Test name
Test status
Simulation time 28561899 ps
CPU time 0.69 seconds
Started Jul 30 06:31:04 PM PDT 24
Finished Jul 30 06:31:05 PM PDT 24
Peak memory 206904 kb
Host smart-a5100e43-54f8-4aff-bf6c-a3e1a7d88e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32295
35458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3229535458
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.390522656
Short name T253
Test name
Test status
Simulation time 14395187076 ps
CPU time 34.41 seconds
Started Jul 30 06:31:06 PM PDT 24
Finished Jul 30 06:31:41 PM PDT 24
Peak memory 215328 kb
Host smart-9f71d254-d557-40b8-9936-48ee33688b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39052
2656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.390522656
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2174028920
Short name T1520
Test name
Test status
Simulation time 197226102 ps
CPU time 0.94 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:14 PM PDT 24
Peak memory 207080 kb
Host smart-59b2ecf2-bda5-4610-a856-42eee9d59886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21740
28920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2174028920
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2598923613
Short name T1144
Test name
Test status
Simulation time 217212005 ps
CPU time 0.96 seconds
Started Jul 30 06:31:05 PM PDT 24
Finished Jul 30 06:31:06 PM PDT 24
Peak memory 206888 kb
Host smart-1d53feb0-3239-4db7-b7e9-2974085e3361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25989
23613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2598923613
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.3663455820
Short name T1577
Test name
Test status
Simulation time 192623957 ps
CPU time 0.97 seconds
Started Jul 30 06:31:03 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 206916 kb
Host smart-5de7244a-7de8-40e6-ac68-096414265cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36634
55820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.3663455820
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3574059103
Short name T1933
Test name
Test status
Simulation time 176976983 ps
CPU time 0.95 seconds
Started Jul 30 06:31:03 PM PDT 24
Finished Jul 30 06:31:05 PM PDT 24
Peak memory 206988 kb
Host smart-e16fde27-ed60-4625-96cf-60c31914c8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35740
59103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3574059103
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.4015127104
Short name T2411
Test name
Test status
Simulation time 202089277 ps
CPU time 0.9 seconds
Started Jul 30 06:31:03 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 206908 kb
Host smart-a6c5215c-3ad1-4f4c-9e44-6d755d4c555f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40151
27104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.4015127104
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2309135002
Short name T2838
Test name
Test status
Simulation time 180774408 ps
CPU time 0.88 seconds
Started Jul 30 06:31:06 PM PDT 24
Finished Jul 30 06:31:07 PM PDT 24
Peak memory 206888 kb
Host smart-1beb5afd-ec35-47c1-8685-44602c6306e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23091
35002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2309135002
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.899559425
Short name T2121
Test name
Test status
Simulation time 190132090 ps
CPU time 0.9 seconds
Started Jul 30 06:31:05 PM PDT 24
Finished Jul 30 06:31:06 PM PDT 24
Peak memory 206904 kb
Host smart-8b8b82bd-d4e4-409c-82c7-72b26dccb9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89955
9425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.899559425
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.371699962
Short name T1158
Test name
Test status
Simulation time 233034059 ps
CPU time 1.05 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:14 PM PDT 24
Peak memory 206800 kb
Host smart-803e2a9d-f4f7-4eb5-b550-8e4916bef886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37169
9962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.371699962
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.820871922
Short name T2655
Test name
Test status
Simulation time 5266558486 ps
CPU time 51.28 seconds
Started Jul 30 06:31:02 PM PDT 24
Finished Jul 30 06:31:53 PM PDT 24
Peak memory 215356 kb
Host smart-ad761128-251b-4eae-a57b-99c1a77b030d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=820871922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.820871922
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1094062132
Short name T1754
Test name
Test status
Simulation time 173629301 ps
CPU time 0.94 seconds
Started Jul 30 06:31:05 PM PDT 24
Finished Jul 30 06:31:06 PM PDT 24
Peak memory 206904 kb
Host smart-253d3804-667b-4cf8-a5d8-7fd2fdab1ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10940
62132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1094062132
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.106552555
Short name T1036
Test name
Test status
Simulation time 182153464 ps
CPU time 0.89 seconds
Started Jul 30 06:31:04 PM PDT 24
Finished Jul 30 06:31:05 PM PDT 24
Peak memory 206908 kb
Host smart-5808589b-5ae5-4b26-a39d-6662d8a40de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10655
2555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.106552555
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.2418928040
Short name T992
Test name
Test status
Simulation time 1309425900 ps
CPU time 3.04 seconds
Started Jul 30 06:31:03 PM PDT 24
Finished Jul 30 06:31:07 PM PDT 24
Peak memory 207092 kb
Host smart-433b64fe-06ce-4e27-82bd-7c3a342f5981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24189
28040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.2418928040
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.187239362
Short name T1343
Test name
Test status
Simulation time 7343598380 ps
CPU time 74.79 seconds
Started Jul 30 06:31:05 PM PDT 24
Finished Jul 30 06:32:20 PM PDT 24
Peak memory 207088 kb
Host smart-dff86c9b-9eb4-47d6-aeeb-89aa31348dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18723
9362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.187239362
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.1960724162
Short name T436
Test name
Test status
Simulation time 143795696 ps
CPU time 0.86 seconds
Started Jul 30 06:31:02 PM PDT 24
Finished Jul 30 06:31:03 PM PDT 24
Peak memory 206900 kb
Host smart-fc4d3111-439c-43f6-8864-86ed4b713121
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960724162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.1960724162
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.3373851455
Short name T520
Test name
Test status
Simulation time 92302195 ps
CPU time 0.72 seconds
Started Jul 30 06:31:14 PM PDT 24
Finished Jul 30 06:31:15 PM PDT 24
Peak memory 207028 kb
Host smart-5d0f262b-a3d2-4db6-8cc0-ca21d3c11af7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3373851455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.3373851455
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.4217127754
Short name T1405
Test name
Test status
Simulation time 3538082881 ps
CPU time 4.83 seconds
Started Jul 30 06:31:09 PM PDT 24
Finished Jul 30 06:31:13 PM PDT 24
Peak memory 207060 kb
Host smart-9abe1ccc-c582-44a3-8f5f-005b43e10d6c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217127754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.4217127754
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.938116378
Short name T183
Test name
Test status
Simulation time 13402454202 ps
CPU time 16.56 seconds
Started Jul 30 06:31:07 PM PDT 24
Finished Jul 30 06:31:23 PM PDT 24
Peak memory 207148 kb
Host smart-48508ad5-3b83-489e-ae51-f1f3cedf3bc9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=938116378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.938116378
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.588356929
Short name T2572
Test name
Test status
Simulation time 23355252363 ps
CPU time 27.39 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:41 PM PDT 24
Peak memory 207264 kb
Host smart-f22d9ad1-d243-422d-b251-7137ef2a470f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588356929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ao
n_wake_resume.588356929
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3193628597
Short name T1541
Test name
Test status
Simulation time 162250577 ps
CPU time 0.87 seconds
Started Jul 30 06:31:07 PM PDT 24
Finished Jul 30 06:31:08 PM PDT 24
Peak memory 206924 kb
Host smart-2dc33df5-0aec-4deb-8a1f-ad4b784d84d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31936
28597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3193628597
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3528023634
Short name T2
Test name
Test status
Simulation time 162046085 ps
CPU time 0.89 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:14 PM PDT 24
Peak memory 206700 kb
Host smart-512ae2f4-4d42-4e85-a694-66fe6eeebd85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35280
23634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3528023634
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.3550614339
Short name T2539
Test name
Test status
Simulation time 231286294 ps
CPU time 1.07 seconds
Started Jul 30 06:31:07 PM PDT 24
Finished Jul 30 06:31:08 PM PDT 24
Peak memory 206888 kb
Host smart-30fe2525-a6b6-4a1f-9b0b-4adf124c84c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35506
14339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3550614339
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2042757289
Short name T2622
Test name
Test status
Simulation time 758107687 ps
CPU time 2.12 seconds
Started Jul 30 06:31:08 PM PDT 24
Finished Jul 30 06:31:10 PM PDT 24
Peak memory 207056 kb
Host smart-6f972900-1254-4443-b510-8609d627422a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2042757289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2042757289
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.128150051
Short name T281
Test name
Test status
Simulation time 20239701096 ps
CPU time 44.57 seconds
Started Jul 30 06:31:10 PM PDT 24
Finished Jul 30 06:31:55 PM PDT 24
Peak memory 207116 kb
Host smart-50500f24-aa7b-4b14-b2af-e17d2b4caac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12815
0051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.128150051
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.1002297152
Short name T892
Test name
Test status
Simulation time 6382018773 ps
CPU time 39.99 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:53 PM PDT 24
Peak memory 207232 kb
Host smart-9ad6bf57-cd8b-492b-ae68-17fbf56e22ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002297152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.1002297152
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.922408558
Short name T2703
Test name
Test status
Simulation time 476203083 ps
CPU time 1.59 seconds
Started Jul 30 06:31:10 PM PDT 24
Finished Jul 30 06:31:12 PM PDT 24
Peak memory 206864 kb
Host smart-fb638608-3d8a-4f34-974b-ac1b92999d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92240
8558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.922408558
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2645139545
Short name T1912
Test name
Test status
Simulation time 141673674 ps
CPU time 0.82 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:14 PM PDT 24
Peak memory 206880 kb
Host smart-2cbb34d2-dcd9-4ca3-87d5-3670f33e26d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26451
39545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2645139545
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1159962675
Short name T1367
Test name
Test status
Simulation time 74463574 ps
CPU time 0.72 seconds
Started Jul 30 06:31:08 PM PDT 24
Finished Jul 30 06:31:09 PM PDT 24
Peak memory 206916 kb
Host smart-860608a3-2cac-4e18-a15e-34ea56d6d604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11599
62675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1159962675
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1114886736
Short name T745
Test name
Test status
Simulation time 1032607869 ps
CPU time 2.77 seconds
Started Jul 30 06:31:08 PM PDT 24
Finished Jul 30 06:31:10 PM PDT 24
Peak memory 206996 kb
Host smart-34002323-4966-4847-9bc1-48965e1b0973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11148
86736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1114886736
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1227312987
Short name T1248
Test name
Test status
Simulation time 238096377 ps
CPU time 1.64 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:15 PM PDT 24
Peak memory 206964 kb
Host smart-bfddaf5d-9969-4871-9d00-a31f6dec8746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12273
12987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1227312987
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1337070304
Short name T515
Test name
Test status
Simulation time 204931107 ps
CPU time 1.09 seconds
Started Jul 30 06:31:09 PM PDT 24
Finished Jul 30 06:31:10 PM PDT 24
Peak memory 215196 kb
Host smart-717bc197-45c7-4312-bf9e-5bd6c0f2c8a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1337070304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1337070304
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3840804703
Short name T2252
Test name
Test status
Simulation time 144089294 ps
CPU time 0.84 seconds
Started Jul 30 06:31:07 PM PDT 24
Finished Jul 30 06:31:08 PM PDT 24
Peak memory 206884 kb
Host smart-61f3a768-c99f-4670-aa70-51907dbb3de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38408
04703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3840804703
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.4252111734
Short name T980
Test name
Test status
Simulation time 204238085 ps
CPU time 0.96 seconds
Started Jul 30 06:31:07 PM PDT 24
Finished Jul 30 06:31:08 PM PDT 24
Peak memory 206888 kb
Host smart-a07e99a3-11fc-46a7-92df-f735de2e3a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42521
11734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.4252111734
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.2432592021
Short name T452
Test name
Test status
Simulation time 6597367289 ps
CPU time 51.07 seconds
Started Jul 30 06:31:07 PM PDT 24
Finished Jul 30 06:31:58 PM PDT 24
Peak memory 216900 kb
Host smart-cc8c77b7-c254-4e26-a2fe-9a20cb9194f9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2432592021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.2432592021
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.660539860
Short name T1992
Test name
Test status
Simulation time 6137443089 ps
CPU time 40.43 seconds
Started Jul 30 06:31:06 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 207136 kb
Host smart-7bdfc654-861d-4b15-b3b4-459225a563c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=660539860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.660539860
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3615907860
Short name T692
Test name
Test status
Simulation time 236849729 ps
CPU time 1.03 seconds
Started Jul 30 06:31:10 PM PDT 24
Finished Jul 30 06:31:11 PM PDT 24
Peak memory 206892 kb
Host smart-bc7149ef-676c-4606-986c-8cbed36672b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36159
07860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3615907860
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.305270263
Short name T820
Test name
Test status
Simulation time 23295180402 ps
CPU time 28.02 seconds
Started Jul 30 06:31:11 PM PDT 24
Finished Jul 30 06:31:39 PM PDT 24
Peak memory 207088 kb
Host smart-50ecd1d6-978a-4cd4-88f7-25655e230ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30527
0263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.305270263
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2577283432
Short name T706
Test name
Test status
Simulation time 3310358087 ps
CPU time 5.12 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:18 PM PDT 24
Peak memory 207076 kb
Host smart-f0b64f31-91d2-476b-b9ad-dd875d824c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25772
83432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2577283432
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.3657539606
Short name T574
Test name
Test status
Simulation time 7233383278 ps
CPU time 213.9 seconds
Started Jul 30 06:31:12 PM PDT 24
Finished Jul 30 06:34:46 PM PDT 24
Peak memory 215284 kb
Host smart-3acca053-71ad-43f7-ac5c-c43e3cd873e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36575
39606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.3657539606
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.328771105
Short name T2702
Test name
Test status
Simulation time 3383427238 ps
CPU time 94.16 seconds
Started Jul 30 06:31:12 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 215316 kb
Host smart-57a318c6-40fc-4894-b484-cf085d021d45
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=328771105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.328771105
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3793695357
Short name T1128
Test name
Test status
Simulation time 240058813 ps
CPU time 0.99 seconds
Started Jul 30 06:31:10 PM PDT 24
Finished Jul 30 06:31:11 PM PDT 24
Peak memory 206936 kb
Host smart-917d0dd2-452f-4894-a086-8f28164544b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3793695357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3793695357
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1215238630
Short name T875
Test name
Test status
Simulation time 185234682 ps
CPU time 0.91 seconds
Started Jul 30 06:31:10 PM PDT 24
Finished Jul 30 06:31:11 PM PDT 24
Peak memory 206912 kb
Host smart-5efeceb7-25b2-46af-bdb7-5d0796fc96cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12152
38630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1215238630
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.1525603126
Short name T2765
Test name
Test status
Simulation time 4038991684 ps
CPU time 32.78 seconds
Started Jul 30 06:31:10 PM PDT 24
Finished Jul 30 06:31:42 PM PDT 24
Peak memory 215316 kb
Host smart-d4f01a19-b8ec-4de5-9312-509a7ba5a522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15256
03126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.1525603126
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.910462541
Short name T430
Test name
Test status
Simulation time 3129594518 ps
CPU time 90.48 seconds
Started Jul 30 06:31:14 PM PDT 24
Finished Jul 30 06:32:44 PM PDT 24
Peak memory 215308 kb
Host smart-bdaa2bb1-fe79-44f3-bd18-dbadf879be02
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=910462541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.910462541
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1049701807
Short name T2000
Test name
Test status
Simulation time 192999532 ps
CPU time 0.9 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:14 PM PDT 24
Peak memory 206936 kb
Host smart-e43056a7-b912-42fd-b76f-e2a1827cd3d6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1049701807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1049701807
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.406098944
Short name T2467
Test name
Test status
Simulation time 176189124 ps
CPU time 0.93 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:14 PM PDT 24
Peak memory 206924 kb
Host smart-e2bc8c38-cfd9-4b72-9430-e0c8fb2fb923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40609
8944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.406098944
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2784481644
Short name T114
Test name
Test status
Simulation time 244386092 ps
CPU time 1.03 seconds
Started Jul 30 06:31:14 PM PDT 24
Finished Jul 30 06:31:15 PM PDT 24
Peak memory 206932 kb
Host smart-dfaa1fa1-8a73-4a06-9073-b45bc2e0d882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27844
81644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2784481644
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3474382416
Short name T2152
Test name
Test status
Simulation time 195210814 ps
CPU time 0.97 seconds
Started Jul 30 06:31:11 PM PDT 24
Finished Jul 30 06:31:12 PM PDT 24
Peak memory 206908 kb
Host smart-a501ede7-38e3-4863-a388-a19ee336a754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34743
82416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3474382416
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.27430349
Short name T401
Test name
Test status
Simulation time 185619440 ps
CPU time 0.96 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:14 PM PDT 24
Peak memory 206908 kb
Host smart-ab01255a-b3aa-491b-9dff-b0bfe23a3d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27430
349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.27430349
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2700083437
Short name T1000
Test name
Test status
Simulation time 217458110 ps
CPU time 0.92 seconds
Started Jul 30 06:31:10 PM PDT 24
Finished Jul 30 06:31:11 PM PDT 24
Peak memory 206916 kb
Host smart-99e0ce4b-aacc-4078-bd32-5a0bf646fd32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27000
83437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2700083437
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1614210270
Short name T547
Test name
Test status
Simulation time 147228400 ps
CPU time 0.84 seconds
Started Jul 30 06:31:12 PM PDT 24
Finished Jul 30 06:31:13 PM PDT 24
Peak memory 206952 kb
Host smart-9da7f216-744b-422c-8065-3c360beffc4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16142
10270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1614210270
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.2272214416
Short name T1595
Test name
Test status
Simulation time 234060865 ps
CPU time 1.01 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:14 PM PDT 24
Peak memory 206928 kb
Host smart-cf2f6aa5-2b45-4b2b-9bd5-dfc68220c657
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2272214416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.2272214416
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2101667503
Short name T20
Test name
Test status
Simulation time 150682469 ps
CPU time 0.85 seconds
Started Jul 30 06:31:17 PM PDT 24
Finished Jul 30 06:31:18 PM PDT 24
Peak memory 206952 kb
Host smart-fd48c4e3-761a-49e5-a8c6-b38cb925ed97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21016
67503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2101667503
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1160488339
Short name T1974
Test name
Test status
Simulation time 146654703 ps
CPU time 0.78 seconds
Started Jul 30 06:31:10 PM PDT 24
Finished Jul 30 06:31:11 PM PDT 24
Peak memory 206908 kb
Host smart-213bbb57-fd9d-4c0c-b17f-7686eca4bce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11604
88339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1160488339
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.3391071333
Short name T2799
Test name
Test status
Simulation time 9509782222 ps
CPU time 23.42 seconds
Started Jul 30 06:31:12 PM PDT 24
Finished Jul 30 06:31:36 PM PDT 24
Peak memory 219768 kb
Host smart-623119d5-1e9e-4aab-ac8f-5ba2dbb4e731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33910
71333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3391071333
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2958141213
Short name T1630
Test name
Test status
Simulation time 172927102 ps
CPU time 0.91 seconds
Started Jul 30 06:31:17 PM PDT 24
Finished Jul 30 06:31:18 PM PDT 24
Peak memory 206984 kb
Host smart-0015d1e4-cb89-4ce9-8e99-421fafbdeafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29581
41213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2958141213
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.539153550
Short name T1137
Test name
Test status
Simulation time 205613936 ps
CPU time 0.9 seconds
Started Jul 30 06:31:11 PM PDT 24
Finished Jul 30 06:31:12 PM PDT 24
Peak memory 206932 kb
Host smart-bc68150d-7a31-489b-bfaf-850eb9d79257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53915
3550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.539153550
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.303916595
Short name T868
Test name
Test status
Simulation time 204950718 ps
CPU time 0.92 seconds
Started Jul 30 06:31:10 PM PDT 24
Finished Jul 30 06:31:11 PM PDT 24
Peak memory 206904 kb
Host smart-6f1b5322-be3d-4e52-9912-91d9cf1cf4c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30391
6595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.303916595
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1548362127
Short name T2574
Test name
Test status
Simulation time 199768263 ps
CPU time 0.88 seconds
Started Jul 30 06:31:11 PM PDT 24
Finished Jul 30 06:31:12 PM PDT 24
Peak memory 206952 kb
Host smart-9c9301f2-c0b9-49d9-b942-fa77459a9245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15483
62127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1548362127
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.2395682426
Short name T2294
Test name
Test status
Simulation time 192004022 ps
CPU time 0.85 seconds
Started Jul 30 06:31:15 PM PDT 24
Finished Jul 30 06:31:16 PM PDT 24
Peak memory 206924 kb
Host smart-4989dfb7-51c8-4f48-b3e7-6cc25099d23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23956
82426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.2395682426
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.1245465978
Short name T2212
Test name
Test status
Simulation time 165445347 ps
CPU time 0.86 seconds
Started Jul 30 06:31:17 PM PDT 24
Finished Jul 30 06:31:18 PM PDT 24
Peak memory 206952 kb
Host smart-34b6314a-fb46-48c1-8fb7-bf4b52fce4e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12454
65978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.1245465978
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3221001026
Short name T2431
Test name
Test status
Simulation time 198918940 ps
CPU time 0.94 seconds
Started Jul 30 06:31:14 PM PDT 24
Finished Jul 30 06:31:15 PM PDT 24
Peak memory 206964 kb
Host smart-174bc7ae-9f1f-4d06-ad12-49d4c124066d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32210
01026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3221001026
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1397904354
Short name T2260
Test name
Test status
Simulation time 227701220 ps
CPU time 1.06 seconds
Started Jul 30 06:31:16 PM PDT 24
Finished Jul 30 06:31:17 PM PDT 24
Peak memory 206876 kb
Host smart-210bce2c-baa6-4a47-8a26-442342448c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13979
04354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1397904354
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.1568470607
Short name T1087
Test name
Test status
Simulation time 4699197218 ps
CPU time 138.46 seconds
Started Jul 30 06:31:14 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 215360 kb
Host smart-f55a3045-7f5c-4f95-9b25-087b90763cff
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1568470607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.1568470607
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.785424995
Short name T2016
Test name
Test status
Simulation time 202005031 ps
CPU time 0.88 seconds
Started Jul 30 06:31:14 PM PDT 24
Finished Jul 30 06:31:15 PM PDT 24
Peak memory 206956 kb
Host smart-17727dca-0585-4c4b-a03d-f24605f00120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78542
4995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.785424995
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2553072755
Short name T2461
Test name
Test status
Simulation time 197997725 ps
CPU time 0.91 seconds
Started Jul 30 06:31:19 PM PDT 24
Finished Jul 30 06:31:20 PM PDT 24
Peak memory 206908 kb
Host smart-67b3ac2c-8e71-4d63-a9a6-84fd7e33383e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25530
72755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2553072755
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.2949143370
Short name T2729
Test name
Test status
Simulation time 628592038 ps
CPU time 1.73 seconds
Started Jul 30 06:31:14 PM PDT 24
Finished Jul 30 06:31:16 PM PDT 24
Peak memory 206884 kb
Host smart-cee45a54-3dfd-4d81-9541-c2e3d7e11475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29491
43370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.2949143370
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.937349360
Short name T1980
Test name
Test status
Simulation time 5414136478 ps
CPU time 41 seconds
Started Jul 30 06:31:15 PM PDT 24
Finished Jul 30 06:31:56 PM PDT 24
Peak memory 216688 kb
Host smart-e56cdb36-9b2d-4f7a-bed6-7f58cae5d6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93734
9360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.937349360
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.3817986946
Short name T1355
Test name
Test status
Simulation time 1104396512 ps
CPU time 9.28 seconds
Started Jul 30 06:31:13 PM PDT 24
Finished Jul 30 06:31:23 PM PDT 24
Peak memory 207148 kb
Host smart-e2ed172e-ece8-4beb-bdcb-16cec58e8bae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817986946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.3817986946
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.2255405819
Short name T1118
Test name
Test status
Simulation time 37214596 ps
CPU time 0.68 seconds
Started Jul 30 06:31:33 PM PDT 24
Finished Jul 30 06:31:34 PM PDT 24
Peak memory 207064 kb
Host smart-426bf262-19a0-4dce-9aba-de33eaf51569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2255405819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2255405819
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2207747636
Short name T1402
Test name
Test status
Simulation time 4428768547 ps
CPU time 6.45 seconds
Started Jul 30 06:31:15 PM PDT 24
Finished Jul 30 06:31:21 PM PDT 24
Peak memory 207132 kb
Host smart-f97fe21b-240d-45a9-9edc-46d41890f7a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207747636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.2207747636
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.1716618712
Short name T2206
Test name
Test status
Simulation time 13318981311 ps
CPU time 15.95 seconds
Started Jul 30 06:31:16 PM PDT 24
Finished Jul 30 06:31:32 PM PDT 24
Peak memory 207144 kb
Host smart-e99841b6-daaf-4429-aa81-a79507b6f827
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716618712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.1716618712
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1875385903
Short name T952
Test name
Test status
Simulation time 23361232089 ps
CPU time 32.57 seconds
Started Jul 30 06:31:15 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 207168 kb
Host smart-77a8bf9a-9c68-4c99-9f5b-07e4f464f4f0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875385903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.1875385903
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2537407046
Short name T1680
Test name
Test status
Simulation time 161052227 ps
CPU time 0.84 seconds
Started Jul 30 06:31:19 PM PDT 24
Finished Jul 30 06:31:20 PM PDT 24
Peak memory 206924 kb
Host smart-eb8a73ae-c443-447c-b03e-e7af539414fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25374
07046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2537407046
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.2565530411
Short name T1570
Test name
Test status
Simulation time 159173337 ps
CPU time 0.83 seconds
Started Jul 30 06:31:21 PM PDT 24
Finished Jul 30 06:31:22 PM PDT 24
Peak memory 206876 kb
Host smart-d1011b8d-3531-43f4-b76a-6f50d407a592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25655
30411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.2565530411
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.11960846
Short name T1866
Test name
Test status
Simulation time 301420036 ps
CPU time 1.18 seconds
Started Jul 30 06:31:19 PM PDT 24
Finished Jul 30 06:31:20 PM PDT 24
Peak memory 206932 kb
Host smart-9c93a42f-e163-4beb-b5fe-6cd7f2ea486b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11960
846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.11960846
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2007970450
Short name T1479
Test name
Test status
Simulation time 365667628 ps
CPU time 1.18 seconds
Started Jul 30 06:31:22 PM PDT 24
Finished Jul 30 06:31:23 PM PDT 24
Peak memory 206924 kb
Host smart-09252f2f-e5ca-435a-87d5-b8e1d3a88af0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2007970450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2007970450
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2127552900
Short name T2787
Test name
Test status
Simulation time 11173273331 ps
CPU time 24.2 seconds
Started Jul 30 06:31:20 PM PDT 24
Finished Jul 30 06:31:44 PM PDT 24
Peak memory 207148 kb
Host smart-a519b94a-491a-42b0-8b73-8c5c02133a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21275
52900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2127552900
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.2980179791
Short name T629
Test name
Test status
Simulation time 3871044869 ps
CPU time 35.81 seconds
Started Jul 30 06:31:21 PM PDT 24
Finished Jul 30 06:31:57 PM PDT 24
Peak memory 207148 kb
Host smart-0bf09ecc-ab26-46d0-8e62-c0c13f21ed71
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980179791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.2980179791
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.1789704550
Short name T2471
Test name
Test status
Simulation time 381395292 ps
CPU time 1.37 seconds
Started Jul 30 06:31:19 PM PDT 24
Finished Jul 30 06:31:21 PM PDT 24
Peak memory 206952 kb
Host smart-f9609478-879c-4a3b-925c-a16e7a75b93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17897
04550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.1789704550
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2579282678
Short name T38
Test name
Test status
Simulation time 178101329 ps
CPU time 0.83 seconds
Started Jul 30 06:31:18 PM PDT 24
Finished Jul 30 06:31:19 PM PDT 24
Peak memory 206880 kb
Host smart-45af51a1-7fc8-49c0-8f40-9aeca1abed3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25792
82678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2579282678
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.1535076265
Short name T1971
Test name
Test status
Simulation time 41151820 ps
CPU time 0.74 seconds
Started Jul 30 06:31:20 PM PDT 24
Finished Jul 30 06:31:21 PM PDT 24
Peak memory 206872 kb
Host smart-2805ec1f-54d8-4a7e-bc38-cd38f8b32d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15350
76265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1535076265
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.2977416406
Short name T1220
Test name
Test status
Simulation time 761698352 ps
CPU time 2.3 seconds
Started Jul 30 06:31:20 PM PDT 24
Finished Jul 30 06:31:22 PM PDT 24
Peak memory 207052 kb
Host smart-5cb1f027-1f8f-4123-88d0-1d6d66c66979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29774
16406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2977416406
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.212813382
Short name T178
Test name
Test status
Simulation time 242695015 ps
CPU time 1.9 seconds
Started Jul 30 06:31:19 PM PDT 24
Finished Jul 30 06:31:21 PM PDT 24
Peak memory 207004 kb
Host smart-8af87796-bd4c-4fbe-9d2c-c2f4f6022457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21281
3382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.212813382
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1616450568
Short name T2416
Test name
Test status
Simulation time 266782641 ps
CPU time 1.14 seconds
Started Jul 30 06:31:20 PM PDT 24
Finished Jul 30 06:31:21 PM PDT 24
Peak memory 215192 kb
Host smart-94435bc8-dd70-488e-a09d-7e5ef17d6f4b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1616450568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1616450568
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3712405621
Short name T513
Test name
Test status
Simulation time 139216580 ps
CPU time 0.84 seconds
Started Jul 30 06:31:19 PM PDT 24
Finished Jul 30 06:31:20 PM PDT 24
Peak memory 206880 kb
Host smart-2f6687b2-a14d-4018-ae4a-d935c3ada072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37124
05621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3712405621
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1104568310
Short name T2693
Test name
Test status
Simulation time 227055867 ps
CPU time 0.97 seconds
Started Jul 30 06:31:18 PM PDT 24
Finished Jul 30 06:31:19 PM PDT 24
Peak memory 206912 kb
Host smart-b93eee6a-53b6-4aa9-9420-de8de7c16a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11045
68310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1104568310
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.1068030774
Short name T1356
Test name
Test status
Simulation time 9912653842 ps
CPU time 80.33 seconds
Started Jul 30 06:31:20 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 216056 kb
Host smart-59d7a6eb-b239-4a92-b6db-eb880308687e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1068030774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.1068030774
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.1990722878
Short name T1821
Test name
Test status
Simulation time 10508261660 ps
CPU time 79.12 seconds
Started Jul 30 06:31:19 PM PDT 24
Finished Jul 30 06:32:39 PM PDT 24
Peak memory 207096 kb
Host smart-db5cf9ee-dde6-4f12-82ef-f05a7a8a105c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1990722878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.1990722878
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.728252544
Short name T968
Test name
Test status
Simulation time 269646673 ps
CPU time 1.13 seconds
Started Jul 30 06:31:21 PM PDT 24
Finished Jul 30 06:31:23 PM PDT 24
Peak memory 206908 kb
Host smart-c960533d-7a04-4695-a1ce-5f45b4d8638d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72825
2544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.728252544
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.881682850
Short name T2683
Test name
Test status
Simulation time 23356270564 ps
CPU time 30.29 seconds
Started Jul 30 06:31:19 PM PDT 24
Finished Jul 30 06:31:50 PM PDT 24
Peak memory 207160 kb
Host smart-5757564c-ebd7-4ea3-8eaf-f35899a1ee24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88168
2850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.881682850
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3718396899
Short name T1707
Test name
Test status
Simulation time 3312388785 ps
CPU time 5.67 seconds
Started Jul 30 06:31:21 PM PDT 24
Finished Jul 30 06:31:27 PM PDT 24
Peak memory 207072 kb
Host smart-cf240c0b-ca8e-4400-bf88-dc028c8bf74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37183
96899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3718396899
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.62013651
Short name T2053
Test name
Test status
Simulation time 6833154982 ps
CPU time 198.71 seconds
Started Jul 30 06:31:23 PM PDT 24
Finished Jul 30 06:34:42 PM PDT 24
Peak memory 215368 kb
Host smart-5a2462ad-bbf8-490f-af02-91d2ad64bcc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62013
651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.62013651
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.315712448
Short name T1864
Test name
Test status
Simulation time 7043426008 ps
CPU time 200.36 seconds
Started Jul 30 06:31:23 PM PDT 24
Finished Jul 30 06:34:43 PM PDT 24
Peak memory 215360 kb
Host smart-802bf6d2-c83f-4a35-aa67-dcda38b5341d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=315712448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.315712448
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.2286932132
Short name T1559
Test name
Test status
Simulation time 243480977 ps
CPU time 1.02 seconds
Started Jul 30 06:31:24 PM PDT 24
Finished Jul 30 06:31:25 PM PDT 24
Peak memory 206924 kb
Host smart-b1446e20-0032-4f6b-af11-200129af8956
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2286932132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.2286932132
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.685629111
Short name T2070
Test name
Test status
Simulation time 197434143 ps
CPU time 0.93 seconds
Started Jul 30 06:31:22 PM PDT 24
Finished Jul 30 06:31:23 PM PDT 24
Peak memory 206980 kb
Host smart-7f1e8dd4-510f-42f7-9a27-7b063549445a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68562
9111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.685629111
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.497785254
Short name T2444
Test name
Test status
Simulation time 3618477425 ps
CPU time 27.99 seconds
Started Jul 30 06:31:26 PM PDT 24
Finished Jul 30 06:31:54 PM PDT 24
Peak memory 215360 kb
Host smart-69911ed1-6d34-4636-8608-840da4c7d955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49778
5254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.497785254
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.125277313
Short name T2718
Test name
Test status
Simulation time 5488937243 ps
CPU time 55.84 seconds
Started Jul 30 06:31:34 PM PDT 24
Finished Jul 30 06:32:30 PM PDT 24
Peak memory 207276 kb
Host smart-1edc4f5b-0e02-405d-a36b-65ff2b9279a1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=125277313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.125277313
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.939715669
Short name T2124
Test name
Test status
Simulation time 162847193 ps
CPU time 0.87 seconds
Started Jul 30 06:31:27 PM PDT 24
Finished Jul 30 06:31:28 PM PDT 24
Peak memory 206924 kb
Host smart-9169cd24-853b-4979-a0a2-8d989bd73635
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=939715669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.939715669
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1768111271
Short name T2073
Test name
Test status
Simulation time 168198165 ps
CPU time 0.9 seconds
Started Jul 30 06:31:38 PM PDT 24
Finished Jul 30 06:31:39 PM PDT 24
Peak memory 206912 kb
Host smart-556207ff-aeca-40b9-b28b-5d440c29ab0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17681
11271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1768111271
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.4268153123
Short name T142
Test name
Test status
Simulation time 228944661 ps
CPU time 0.97 seconds
Started Jul 30 06:31:23 PM PDT 24
Finished Jul 30 06:31:24 PM PDT 24
Peak memory 206924 kb
Host smart-fe9df08d-9acd-4715-915d-f48f00046b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42681
53123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.4268153123
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.219445546
Short name T2751
Test name
Test status
Simulation time 196763749 ps
CPU time 0.96 seconds
Started Jul 30 06:31:24 PM PDT 24
Finished Jul 30 06:31:25 PM PDT 24
Peak memory 206972 kb
Host smart-20f18f14-f661-45f5-8cb6-cce351c6d1fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21944
5546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.219445546
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3930747391
Short name T1223
Test name
Test status
Simulation time 199442010 ps
CPU time 0.92 seconds
Started Jul 30 06:31:23 PM PDT 24
Finished Jul 30 06:31:24 PM PDT 24
Peak memory 206920 kb
Host smart-564ed10c-c5bc-4e2f-88a4-d0a785e4f920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39307
47391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3930747391
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3000702499
Short name T2420
Test name
Test status
Simulation time 209240043 ps
CPU time 0.96 seconds
Started Jul 30 06:31:22 PM PDT 24
Finished Jul 30 06:31:23 PM PDT 24
Peak memory 206988 kb
Host smart-a8e43b50-78d2-47ae-9e80-f28388bd231e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30007
02499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3000702499
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2852014863
Short name T2414
Test name
Test status
Simulation time 165153722 ps
CPU time 0.94 seconds
Started Jul 30 06:31:37 PM PDT 24
Finished Jul 30 06:31:39 PM PDT 24
Peak memory 206912 kb
Host smart-3958c33f-e9c8-40e2-ba90-1e54f59c4be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28520
14863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2852014863
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.2216413254
Short name T2083
Test name
Test status
Simulation time 219761094 ps
CPU time 1.04 seconds
Started Jul 30 06:31:27 PM PDT 24
Finished Jul 30 06:31:29 PM PDT 24
Peak memory 206976 kb
Host smart-74090a8c-9b9d-4d1d-9154-7b065e36427b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2216413254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.2216413254
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2187571804
Short name T2330
Test name
Test status
Simulation time 139808658 ps
CPU time 0.84 seconds
Started Jul 30 06:31:22 PM PDT 24
Finished Jul 30 06:31:23 PM PDT 24
Peak memory 206892 kb
Host smart-40d5fc93-ff4b-4487-aecd-82258c9f932b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21875
71804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2187571804
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3615350939
Short name T2328
Test name
Test status
Simulation time 49217176 ps
CPU time 0.69 seconds
Started Jul 30 06:31:28 PM PDT 24
Finished Jul 30 06:31:28 PM PDT 24
Peak memory 206884 kb
Host smart-376742a7-6c00-421d-a932-dd28b008ef1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36153
50939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3615350939
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.188485085
Short name T1309
Test name
Test status
Simulation time 15128588360 ps
CPU time 39.3 seconds
Started Jul 30 06:31:24 PM PDT 24
Finished Jul 30 06:32:03 PM PDT 24
Peak memory 219512 kb
Host smart-c4ac3162-73b5-4df7-a40d-dc1fcf60bbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18848
5085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.188485085
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2623041478
Short name T1544
Test name
Test status
Simulation time 193275401 ps
CPU time 0.95 seconds
Started Jul 30 06:31:24 PM PDT 24
Finished Jul 30 06:31:25 PM PDT 24
Peak memory 206912 kb
Host smart-cc204558-7f50-464f-909b-96188f8f1006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26230
41478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2623041478
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.712206224
Short name T2679
Test name
Test status
Simulation time 180343778 ps
CPU time 0.93 seconds
Started Jul 30 06:31:24 PM PDT 24
Finished Jul 30 06:31:25 PM PDT 24
Peak memory 206948 kb
Host smart-df3b838b-e872-4cb4-99af-3e21144ee1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71220
6224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.712206224
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.1651151028
Short name T2466
Test name
Test status
Simulation time 227468764 ps
CPU time 0.97 seconds
Started Jul 30 06:31:25 PM PDT 24
Finished Jul 30 06:31:26 PM PDT 24
Peak memory 206908 kb
Host smart-e4f5fb8f-c1b3-44ec-8519-767cbf63d96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16511
51028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.1651151028
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.1761387527
Short name T1304
Test name
Test status
Simulation time 165050211 ps
CPU time 0.86 seconds
Started Jul 30 06:31:22 PM PDT 24
Finished Jul 30 06:31:23 PM PDT 24
Peak memory 206928 kb
Host smart-20aaf71e-bcf6-46ed-9e4c-bf6335a83e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17613
87527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.1761387527
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.3969882499
Short name T1294
Test name
Test status
Simulation time 141516789 ps
CPU time 0.84 seconds
Started Jul 30 06:31:22 PM PDT 24
Finished Jul 30 06:31:23 PM PDT 24
Peak memory 206884 kb
Host smart-3263b97c-21da-433c-902a-33b48bba9397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39698
82499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.3969882499
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3298497602
Short name T1747
Test name
Test status
Simulation time 178622029 ps
CPU time 0.85 seconds
Started Jul 30 06:31:37 PM PDT 24
Finished Jul 30 06:31:38 PM PDT 24
Peak memory 207048 kb
Host smart-d94bad48-d268-42da-9fb3-69442e9424fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32984
97602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3298497602
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.204374611
Short name T278
Test name
Test status
Simulation time 209250618 ps
CPU time 0.91 seconds
Started Jul 30 06:31:25 PM PDT 24
Finished Jul 30 06:31:26 PM PDT 24
Peak memory 206928 kb
Host smart-e0a8f6eb-7175-4d8d-81f2-0189fc322bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20437
4611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.204374611
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.651244870
Short name T1871
Test name
Test status
Simulation time 235023925 ps
CPU time 1.06 seconds
Started Jul 30 06:31:26 PM PDT 24
Finished Jul 30 06:31:27 PM PDT 24
Peak memory 206912 kb
Host smart-e317f255-4c34-45ba-9208-5749b4d5242d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65124
4870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.651244870
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1303191470
Short name T1231
Test name
Test status
Simulation time 3879002719 ps
CPU time 31.68 seconds
Started Jul 30 06:31:25 PM PDT 24
Finished Jul 30 06:31:57 PM PDT 24
Peak memory 216676 kb
Host smart-b8fa0170-cefc-46e6-8ee7-550f57d28296
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1303191470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1303191470
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.526120620
Short name T2120
Test name
Test status
Simulation time 188265134 ps
CPU time 0.91 seconds
Started Jul 30 06:31:30 PM PDT 24
Finished Jul 30 06:31:31 PM PDT 24
Peak memory 206944 kb
Host smart-8c50dbf2-c369-44aa-9836-c3f29ff115f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52612
0620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.526120620
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.147142404
Short name T2515
Test name
Test status
Simulation time 174437743 ps
CPU time 0.89 seconds
Started Jul 30 06:31:23 PM PDT 24
Finished Jul 30 06:31:24 PM PDT 24
Peak memory 206908 kb
Host smart-4285936a-303a-44a0-9431-8cbc648ddcd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14714
2404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.147142404
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.526682519
Short name T274
Test name
Test status
Simulation time 1025605933 ps
CPU time 2.43 seconds
Started Jul 30 06:31:39 PM PDT 24
Finished Jul 30 06:31:42 PM PDT 24
Peak memory 207012 kb
Host smart-d2d7925e-3e14-4fde-bbbc-6db7d818b115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52668
2519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.526682519
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.1215456316
Short name T1206
Test name
Test status
Simulation time 6456271681 ps
CPU time 193.37 seconds
Started Jul 30 06:31:23 PM PDT 24
Finished Jul 30 06:34:36 PM PDT 24
Peak memory 215312 kb
Host smart-2fa53a10-8725-4826-b34f-d95d8070bafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12154
56316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.1215456316
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.907534021
Short name T2488
Test name
Test status
Simulation time 5637878455 ps
CPU time 37.34 seconds
Started Jul 30 06:31:21 PM PDT 24
Finished Jul 30 06:31:58 PM PDT 24
Peak memory 207184 kb
Host smart-78319ee5-61cb-4650-99d0-b1cf64ce8dc1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907534021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_host
_handshake.907534021
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.2468688169
Short name T180
Test name
Test status
Simulation time 44688232 ps
CPU time 0.68 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 207000 kb
Host smart-09f5fca2-7890-40cd-8632-782547d667fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2468688169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.2468688169
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.1056778259
Short name T1900
Test name
Test status
Simulation time 4337128555 ps
CPU time 6.74 seconds
Started Jul 30 06:31:37 PM PDT 24
Finished Jul 30 06:31:44 PM PDT 24
Peak memory 207132 kb
Host smart-871a4d70-44d9-4485-af24-7f79eb5b720e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056778259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_disconnect.1056778259
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.490465956
Short name T2015
Test name
Test status
Simulation time 23469159595 ps
CPU time 30.48 seconds
Started Jul 30 06:31:38 PM PDT 24
Finished Jul 30 06:32:09 PM PDT 24
Peak memory 207160 kb
Host smart-47781561-949e-46ed-9920-d8b857b0b42c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490465956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ao
n_wake_resume.490465956
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2034124299
Short name T2265
Test name
Test status
Simulation time 177461810 ps
CPU time 0.89 seconds
Started Jul 30 06:31:28 PM PDT 24
Finished Jul 30 06:31:29 PM PDT 24
Peak memory 206912 kb
Host smart-acdee0cb-947f-4945-84c0-14c8b18a68eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20341
24299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2034124299
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.1618200470
Short name T1139
Test name
Test status
Simulation time 152048929 ps
CPU time 0.81 seconds
Started Jul 30 06:31:38 PM PDT 24
Finished Jul 30 06:31:39 PM PDT 24
Peak memory 206872 kb
Host smart-cae34257-e76a-4bcf-b4fc-fe0921dc64a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16182
00470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.1618200470
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1188496812
Short name T1845
Test name
Test status
Simulation time 397689487 ps
CPU time 1.42 seconds
Started Jul 30 06:31:29 PM PDT 24
Finished Jul 30 06:31:30 PM PDT 24
Peak memory 206956 kb
Host smart-6c0c8797-cc49-4f11-a404-d58a74b46f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11884
96812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1188496812
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3630653182
Short name T1527
Test name
Test status
Simulation time 739965637 ps
CPU time 2.21 seconds
Started Jul 30 06:31:41 PM PDT 24
Finished Jul 30 06:31:43 PM PDT 24
Peak memory 206996 kb
Host smart-e4daddcd-b5b3-42bc-bc38-cebebd55a9f4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3630653182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3630653182
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.879917908
Short name T1189
Test name
Test status
Simulation time 6460352909 ps
CPU time 16.01 seconds
Started Jul 30 06:31:27 PM PDT 24
Finished Jul 30 06:31:43 PM PDT 24
Peak memory 207156 kb
Host smart-44fa5d07-40f5-43ff-a4bb-e8867cc7e5ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87991
7908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.879917908
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.2840294565
Short name T2672
Test name
Test status
Simulation time 911484320 ps
CPU time 18.07 seconds
Started Jul 30 06:31:28 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 207008 kb
Host smart-1c314e05-ee70-4d4a-877e-c5d32c4ba2ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840294565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.2840294565
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.554741516
Short name T1350
Test name
Test status
Simulation time 400855278 ps
CPU time 1.39 seconds
Started Jul 30 06:31:34 PM PDT 24
Finished Jul 30 06:31:36 PM PDT 24
Peak memory 206892 kb
Host smart-7b4dffea-435c-4ab7-9625-14c8fb39a99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55474
1516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.554741516
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3916510556
Short name T824
Test name
Test status
Simulation time 160726954 ps
CPU time 0.81 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206912 kb
Host smart-39f4be84-83e3-465e-a883-ed1271490077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39165
10556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3916510556
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.1836895391
Short name T780
Test name
Test status
Simulation time 95787054 ps
CPU time 0.8 seconds
Started Jul 30 06:31:39 PM PDT 24
Finished Jul 30 06:31:40 PM PDT 24
Peak memory 206872 kb
Host smart-64048679-7ecb-4a72-b044-5ec989640f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18368
95391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1836895391
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.618515538
Short name T1371
Test name
Test status
Simulation time 745169926 ps
CPU time 2.46 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:31:49 PM PDT 24
Peak memory 206996 kb
Host smart-f14bd9ba-5364-4189-be99-9405de44a24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61851
5538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.618515538
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1916882892
Short name T1987
Test name
Test status
Simulation time 184839632 ps
CPU time 1.94 seconds
Started Jul 30 06:31:34 PM PDT 24
Finished Jul 30 06:31:36 PM PDT 24
Peak memory 206964 kb
Host smart-dac12b8e-af60-456c-a720-98da13ff0f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19168
82892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1916882892
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.674662962
Short name T861
Test name
Test status
Simulation time 241324427 ps
CPU time 1.18 seconds
Started Jul 30 06:31:27 PM PDT 24
Finished Jul 30 06:31:28 PM PDT 24
Peak memory 207016 kb
Host smart-4e91e655-264a-4e4e-8624-6df25ad0a493
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=674662962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.674662962
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.19238327
Short name T2301
Test name
Test status
Simulation time 143834230 ps
CPU time 0.82 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206872 kb
Host smart-903b3ca3-b490-482a-8783-06fbe2f744c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19238
327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.19238327
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1071409795
Short name T1547
Test name
Test status
Simulation time 240517842 ps
CPU time 0.99 seconds
Started Jul 30 06:31:43 PM PDT 24
Finished Jul 30 06:31:44 PM PDT 24
Peak memory 206916 kb
Host smart-de684c2c-0281-49a2-b506-6cde2496ff5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10714
09795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1071409795
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.838618844
Short name T2578
Test name
Test status
Simulation time 8065824937 ps
CPU time 80.88 seconds
Started Jul 30 06:31:34 PM PDT 24
Finished Jul 30 06:32:55 PM PDT 24
Peak memory 215352 kb
Host smart-66f30355-37e1-4d01-9cee-5f7be6dd4655
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=838618844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.838618844
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3807285900
Short name T2653
Test name
Test status
Simulation time 166601728 ps
CPU time 0.92 seconds
Started Jul 30 06:31:30 PM PDT 24
Finished Jul 30 06:31:32 PM PDT 24
Peak memory 206924 kb
Host smart-2b7af297-31c2-4922-af01-700bfd50b8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38072
85900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3807285900
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.2589902224
Short name T1495
Test name
Test status
Simulation time 23329927964 ps
CPU time 31.92 seconds
Started Jul 30 06:31:40 PM PDT 24
Finished Jul 30 06:32:12 PM PDT 24
Peak memory 207104 kb
Host smart-f0d49f9b-2857-4920-8ec1-a426b1cbe2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25899
02224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.2589902224
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2985951517
Short name T2585
Test name
Test status
Simulation time 3305753258 ps
CPU time 5.05 seconds
Started Jul 30 06:31:27 PM PDT 24
Finished Jul 30 06:31:32 PM PDT 24
Peak memory 207056 kb
Host smart-2cf387f0-26d6-4232-9e26-6209d0e54ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29859
51517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2985951517
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.2190692845
Short name T1775
Test name
Test status
Simulation time 7771535695 ps
CPU time 227.9 seconds
Started Jul 30 06:31:32 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 215332 kb
Host smart-1228bab5-2157-4ee8-9857-425cb04b239e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21906
92845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.2190692845
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.202150131
Short name T332
Test name
Test status
Simulation time 7716596534 ps
CPU time 238.38 seconds
Started Jul 30 06:31:29 PM PDT 24
Finished Jul 30 06:35:28 PM PDT 24
Peak memory 215344 kb
Host smart-807959c6-bd05-4033-9bf6-b8ac1b822a6b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=202150131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.202150131
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1409352615
Short name T1452
Test name
Test status
Simulation time 281696765 ps
CPU time 1.06 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:47 PM PDT 24
Peak memory 206920 kb
Host smart-6baac304-7089-486e-9946-58a983404d11
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1409352615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1409352615
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.719241226
Short name T1124
Test name
Test status
Simulation time 264782127 ps
CPU time 1.04 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:47 PM PDT 24
Peak memory 206904 kb
Host smart-c4adcc4e-e72c-4aca-9e57-855fe4464979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71924
1226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.719241226
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.4140322321
Short name T737
Test name
Test status
Simulation time 5034290975 ps
CPU time 51.86 seconds
Started Jul 30 06:31:41 PM PDT 24
Finished Jul 30 06:32:33 PM PDT 24
Peak memory 215356 kb
Host smart-55015fbe-9c35-4e67-a8e7-8e65b8f3347a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41403
22321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.4140322321
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.476911253
Short name T1373
Test name
Test status
Simulation time 4140112381 ps
CPU time 119.76 seconds
Started Jul 30 06:31:27 PM PDT 24
Finished Jul 30 06:33:27 PM PDT 24
Peak memory 215332 kb
Host smart-83e4f87b-8d79-4054-81a9-0c455325e8a7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=476911253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.476911253
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.2849054223
Short name T2690
Test name
Test status
Simulation time 171396585 ps
CPU time 0.88 seconds
Started Jul 30 06:31:40 PM PDT 24
Finished Jul 30 06:31:41 PM PDT 24
Peak memory 206924 kb
Host smart-2d40e94e-2cd7-4928-87f3-2a7720450b30
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2849054223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.2849054223
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3570443119
Short name T582
Test name
Test status
Simulation time 163145179 ps
CPU time 0.84 seconds
Started Jul 30 06:31:42 PM PDT 24
Finished Jul 30 06:31:43 PM PDT 24
Peak memory 206920 kb
Host smart-eac2be30-fb1d-492b-8373-20ad690d8879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35704
43119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3570443119
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2430269584
Short name T117
Test name
Test status
Simulation time 278242184 ps
CPU time 1.01 seconds
Started Jul 30 06:31:39 PM PDT 24
Finished Jul 30 06:31:40 PM PDT 24
Peak memory 206904 kb
Host smart-0f864ecd-202f-45af-8e9f-3ee16f2bd554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24302
69584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2430269584
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.702250656
Short name T2440
Test name
Test status
Simulation time 149367641 ps
CPU time 0.84 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:31:47 PM PDT 24
Peak memory 206968 kb
Host smart-800698d9-8a3e-422b-ada5-123775417fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70225
0656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.702250656
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1535607809
Short name T417
Test name
Test status
Simulation time 174961240 ps
CPU time 0.94 seconds
Started Jul 30 06:31:36 PM PDT 24
Finished Jul 30 06:31:37 PM PDT 24
Peak memory 206944 kb
Host smart-8d29b4c2-6eaa-4505-ae89-771635754722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15356
07809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1535607809
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1638377195
Short name T1172
Test name
Test status
Simulation time 152857271 ps
CPU time 0.83 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 206976 kb
Host smart-bb637fdf-07af-458a-b6e6-645bcacbd0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16383
77195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1638377195
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.399900504
Short name T577
Test name
Test status
Simulation time 152685740 ps
CPU time 0.8 seconds
Started Jul 30 06:31:39 PM PDT 24
Finished Jul 30 06:31:40 PM PDT 24
Peak memory 206936 kb
Host smart-86a504f7-2dc7-4c5c-ba2d-ec89ef271fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39990
0504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.399900504
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3567967459
Short name T2642
Test name
Test status
Simulation time 216851927 ps
CPU time 1.02 seconds
Started Jul 30 06:31:41 PM PDT 24
Finished Jul 30 06:31:42 PM PDT 24
Peak memory 206944 kb
Host smart-19afe1d5-2b96-4edb-b8ec-bc95bf2337ad
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3567967459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3567967459
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2849245671
Short name T422
Test name
Test status
Simulation time 155493804 ps
CPU time 0.84 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206912 kb
Host smart-975dab43-374d-48d7-a016-3ead7adcdec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28492
45671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2849245671
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2587067777
Short name T1832
Test name
Test status
Simulation time 41396841 ps
CPU time 0.71 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 206892 kb
Host smart-f7b92571-a753-4153-85ce-d11f6f089515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25870
67777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2587067777
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2209854098
Short name T2736
Test name
Test status
Simulation time 19930294964 ps
CPU time 48.84 seconds
Started Jul 30 06:31:49 PM PDT 24
Finished Jul 30 06:32:38 PM PDT 24
Peak memory 223492 kb
Host smart-30d694a4-714a-45c4-ae87-f90926311a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22098
54098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2209854098
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1149770113
Short name T1906
Test name
Test status
Simulation time 159176594 ps
CPU time 0.87 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206916 kb
Host smart-122129d7-0c6d-4ee4-852a-cc72dbf2c72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11497
70113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1149770113
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3851745187
Short name T1705
Test name
Test status
Simulation time 230665393 ps
CPU time 0.98 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206892 kb
Host smart-ae81182a-2352-447d-a946-45225c21d6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38517
45187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3851745187
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.751968172
Short name T207
Test name
Test status
Simulation time 227746222 ps
CPU time 0.92 seconds
Started Jul 30 06:31:41 PM PDT 24
Finished Jul 30 06:31:42 PM PDT 24
Peak memory 206984 kb
Host smart-e991126f-011b-40a2-a64f-53e3b3c5a573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75196
8172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.751968172
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2720259221
Short name T1267
Test name
Test status
Simulation time 217250468 ps
CPU time 1.2 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206948 kb
Host smart-770bb255-9ed4-4bf1-bc39-4d6cf7d88a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202
59221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2720259221
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.4049502927
Short name T1787
Test name
Test status
Simulation time 158836173 ps
CPU time 0.87 seconds
Started Jul 30 06:31:40 PM PDT 24
Finished Jul 30 06:31:41 PM PDT 24
Peak memory 206980 kb
Host smart-59d77a65-f243-4c12-b7f3-fe246cbb9ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40495
02927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.4049502927
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2464210429
Short name T2398
Test name
Test status
Simulation time 189016075 ps
CPU time 0.89 seconds
Started Jul 30 06:31:44 PM PDT 24
Finished Jul 30 06:31:45 PM PDT 24
Peak memory 206880 kb
Host smart-c0376542-1b4e-4958-92ed-e4378b81ccf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24642
10429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2464210429
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2862954280
Short name T2851
Test name
Test status
Simulation time 150739959 ps
CPU time 0.82 seconds
Started Jul 30 06:31:43 PM PDT 24
Finished Jul 30 06:31:44 PM PDT 24
Peak memory 206920 kb
Host smart-2d904f17-90d9-4c07-b669-b7487faf18d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28629
54280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2862954280
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3742301170
Short name T2576
Test name
Test status
Simulation time 285635991 ps
CPU time 1.05 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 206944 kb
Host smart-5bf2cb8b-f5ef-4c6c-ba0b-c43370752382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37423
01170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3742301170
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.3874056052
Short name T1389
Test name
Test status
Simulation time 4641720736 ps
CPU time 142.39 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:34:17 PM PDT 24
Peak memory 215304 kb
Host smart-ad2ce40f-3157-414b-aeab-8e91b9e08271
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3874056052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3874056052
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3811772470
Short name T2285
Test name
Test status
Simulation time 158141028 ps
CPU time 0.83 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:31:49 PM PDT 24
Peak memory 206972 kb
Host smart-e692aef6-db86-469a-9c8e-abe145b631e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38117
72470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3811772470
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3853311075
Short name T2569
Test name
Test status
Simulation time 140831395 ps
CPU time 0.8 seconds
Started Jul 30 06:31:40 PM PDT 24
Finished Jul 30 06:31:41 PM PDT 24
Peak memory 206932 kb
Host smart-401cfd24-bd6e-4327-8300-2d243a318840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38533
11075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3853311075
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.3821026444
Short name T2031
Test name
Test status
Simulation time 395129652 ps
CPU time 1.42 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:47 PM PDT 24
Peak memory 206904 kb
Host smart-71c8c903-b485-4a59-9ff1-1802cbe4b91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38210
26444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.3821026444
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.2237113195
Short name T2664
Test name
Test status
Simulation time 4096524548 ps
CPU time 41.24 seconds
Started Jul 30 06:31:37 PM PDT 24
Finished Jul 30 06:32:19 PM PDT 24
Peak memory 215300 kb
Host smart-dc5379d6-3fa8-409e-b517-7d94f7722f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22371
13195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.2237113195
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.979317149
Short name T2134
Test name
Test status
Simulation time 612081751 ps
CPU time 5.12 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:50 PM PDT 24
Peak memory 207060 kb
Host smart-5ef9317b-e973-409a-8d55-6bab546002bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979317149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_host
_handshake.979317149
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2609874632
Short name T1590
Test name
Test status
Simulation time 38673117 ps
CPU time 0.69 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:52 PM PDT 24
Peak memory 207064 kb
Host smart-2a34ed0e-b400-4eb3-97e6-7fecc042d9e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2609874632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2609874632
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.4219226897
Short name T2621
Test name
Test status
Simulation time 13439808366 ps
CPU time 16.16 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:32:01 PM PDT 24
Peak memory 207128 kb
Host smart-c3d12581-07d7-4049-a6b8-f1fda0fb0b5f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219226897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.4219226897
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.1372523206
Short name T1589
Test name
Test status
Simulation time 23371024920 ps
CPU time 30.83 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:32:17 PM PDT 24
Peak memory 207136 kb
Host smart-b5b8e185-eb07-4a1b-ad4e-628e7e3a4f14
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372523206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.1372523206
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.207231766
Short name T1383
Test name
Test status
Simulation time 186557396 ps
CPU time 0.94 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 206924 kb
Host smart-4ed32b05-bd8d-4f17-9cf5-50b12dc4a9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20723
1766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.207231766
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.1300740619
Short name T675
Test name
Test status
Simulation time 147037539 ps
CPU time 0.81 seconds
Started Jul 30 06:31:41 PM PDT 24
Finished Jul 30 06:31:42 PM PDT 24
Peak memory 206904 kb
Host smart-0e7c0027-a921-450a-8a39-3c263683d156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13007
40619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.1300740619
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.1786921901
Short name T802
Test name
Test status
Simulation time 363935624 ps
CPU time 1.38 seconds
Started Jul 30 06:31:52 PM PDT 24
Finished Jul 30 06:31:54 PM PDT 24
Peak memory 206924 kb
Host smart-1d59b281-4886-41b5-b9f0-b9c3ac00944f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17869
21901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.1786921901
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1605047442
Short name T76
Test name
Test status
Simulation time 912249677 ps
CPU time 2.29 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 207032 kb
Host smart-36ff545d-7cac-4f02-a4f8-598efb07a537
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1605047442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1605047442
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.2240021471
Short name T170
Test name
Test status
Simulation time 19032180833 ps
CPU time 43.87 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:32:29 PM PDT 24
Peak memory 207140 kb
Host smart-f7bfc701-a96e-49c4-baaf-cdbd5ba912d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22400
21471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.2240021471
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.497946503
Short name T2382
Test name
Test status
Simulation time 1507102703 ps
CPU time 10.09 seconds
Started Jul 30 06:31:38 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 207016 kb
Host smart-ef21614d-c409-4edc-8fb4-08e8089f795a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497946503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.497946503
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.1398194605
Short name T21
Test name
Test status
Simulation time 396061402 ps
CPU time 1.37 seconds
Started Jul 30 06:31:44 PM PDT 24
Finished Jul 30 06:31:45 PM PDT 24
Peak memory 206936 kb
Host smart-3100fd46-d535-42f6-8bfc-e2549f25943b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13981
94605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.1398194605
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1420998579
Short name T2738
Test name
Test status
Simulation time 155458901 ps
CPU time 0.82 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206920 kb
Host smart-8319bebc-fc21-4de7-a450-b9d14aa0cb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14209
98579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1420998579
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1258539460
Short name T2088
Test name
Test status
Simulation time 44784730 ps
CPU time 0.69 seconds
Started Jul 30 06:31:43 PM PDT 24
Finished Jul 30 06:31:43 PM PDT 24
Peak memory 206876 kb
Host smart-0cfc9a5e-49e6-49b2-b0e3-523d45d66311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12585
39460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1258539460
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1656125559
Short name T2402
Test name
Test status
Simulation time 1051117739 ps
CPU time 3.03 seconds
Started Jul 30 06:31:55 PM PDT 24
Finished Jul 30 06:31:58 PM PDT 24
Peak memory 207108 kb
Host smart-572b2ff7-567a-4c16-844e-2fb4605df5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16561
25559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1656125559
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2702776839
Short name T839
Test name
Test status
Simulation time 307271106 ps
CPU time 1.94 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206956 kb
Host smart-b1efc655-20fd-4492-9961-697e88430753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27027
76839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2702776839
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2434844118
Short name T2410
Test name
Test status
Simulation time 211924844 ps
CPU time 1.08 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206996 kb
Host smart-efc804d2-361c-4bc4-abdd-6627d4d1c042
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2434844118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2434844118
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3348337931
Short name T530
Test name
Test status
Simulation time 179544979 ps
CPU time 0.86 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206888 kb
Host smart-5c22610e-cce1-4dbc-b5cf-94a036fd1b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33483
37931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3348337931
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2535098645
Short name T2035
Test name
Test status
Simulation time 234299239 ps
CPU time 1.04 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:31:49 PM PDT 24
Peak memory 206956 kb
Host smart-29928296-478a-4f56-a82f-3da65e1339cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25350
98645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2535098645
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.1815531880
Short name T2318
Test name
Test status
Simulation time 8262579952 ps
CPU time 242.62 seconds
Started Jul 30 06:31:52 PM PDT 24
Finished Jul 30 06:35:55 PM PDT 24
Peak memory 215380 kb
Host smart-61672d1f-250b-4bf5-9d71-0127ac8995f1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1815531880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.1815531880
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.2731027717
Short name T664
Test name
Test status
Simulation time 11777347998 ps
CPU time 77.16 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:33:04 PM PDT 24
Peak memory 207100 kb
Host smart-d78d1924-ab3e-4d4f-9f3a-9e800f66c506
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2731027717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.2731027717
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.185013745
Short name T2483
Test name
Test status
Simulation time 221367312 ps
CPU time 0.93 seconds
Started Jul 30 06:31:42 PM PDT 24
Finished Jul 30 06:31:43 PM PDT 24
Peak memory 206904 kb
Host smart-0d0a3d20-47e6-4915-a6d7-41ce9d36746e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18501
3745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.185013745
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.2640189061
Short name T182
Test name
Test status
Simulation time 23361162343 ps
CPU time 30.26 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:32:16 PM PDT 24
Peak memory 207100 kb
Host smart-a23feee1-1df7-42ae-868b-28bc2541500f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26401
89061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.2640189061
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1840755864
Short name T363
Test name
Test status
Simulation time 3378560947 ps
CPU time 4.87 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:31:51 PM PDT 24
Peak memory 207064 kb
Host smart-7a669a52-4226-4e7e-a8a4-03dbfc0f630d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18407
55864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1840755864
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.213458743
Short name T2800
Test name
Test status
Simulation time 6121426540 ps
CPU time 44.77 seconds
Started Jul 30 06:31:44 PM PDT 24
Finished Jul 30 06:32:28 PM PDT 24
Peak memory 217244 kb
Host smart-3d0fa489-9b31-4ac7-92fe-393377b134fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21345
8743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.213458743
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.2103354554
Short name T1424
Test name
Test status
Simulation time 6607756638 ps
CPU time 68.42 seconds
Started Jul 30 06:31:44 PM PDT 24
Finished Jul 30 06:32:52 PM PDT 24
Peak memory 207164 kb
Host smart-83b7a4c6-8367-482d-9bd4-f565c1f1be7d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2103354554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.2103354554
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.4127517641
Short name T758
Test name
Test status
Simulation time 242110576 ps
CPU time 1.21 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:52 PM PDT 24
Peak memory 206980 kb
Host smart-c0285e8c-1024-486a-b038-28dae6ad9c1b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4127517641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.4127517641
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.4112799516
Short name T2233
Test name
Test status
Simulation time 270354454 ps
CPU time 1.08 seconds
Started Jul 30 06:31:50 PM PDT 24
Finished Jul 30 06:31:52 PM PDT 24
Peak memory 206936 kb
Host smart-cf9049af-4a10-408a-ba86-4d2ef9773f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41127
99516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.4112799516
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.3317450363
Short name T2717
Test name
Test status
Simulation time 4358852692 ps
CPU time 31.02 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:32:16 PM PDT 24
Peak memory 215368 kb
Host smart-1523808a-e4be-47b3-bec7-00f75d0d0279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33174
50363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.3317450363
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.3284367937
Short name T1448
Test name
Test status
Simulation time 4238657014 ps
CPU time 43.86 seconds
Started Jul 30 06:31:43 PM PDT 24
Finished Jul 30 06:32:28 PM PDT 24
Peak memory 216656 kb
Host smart-6bd559b9-9506-4d74-b8d5-7ce060ccad1a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3284367937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.3284367937
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.4101987727
Short name T2853
Test name
Test status
Simulation time 152874675 ps
CPU time 0.83 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206980 kb
Host smart-8471b3e5-9c88-43b4-8966-6290cd4908e2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4101987727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.4101987727
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1867259335
Short name T1528
Test name
Test status
Simulation time 184075950 ps
CPU time 0.89 seconds
Started Jul 30 06:31:44 PM PDT 24
Finished Jul 30 06:31:45 PM PDT 24
Peak memory 206924 kb
Host smart-e4003c81-d131-4f13-8d26-567a75cfcf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18672
59335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1867259335
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1689317555
Short name T213
Test name
Test status
Simulation time 143172890 ps
CPU time 0.83 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:31:47 PM PDT 24
Peak memory 206976 kb
Host smart-0cf3bc18-7df9-40af-acee-b2e7af839a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16893
17555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1689317555
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3977383487
Short name T1218
Test name
Test status
Simulation time 172780896 ps
CPU time 0.93 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:31:49 PM PDT 24
Peak memory 206916 kb
Host smart-53ca5bc5-8be6-4111-a41d-140dd8735a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39773
83487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3977383487
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2542158411
Short name T871
Test name
Test status
Simulation time 158863976 ps
CPU time 0.85 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:31:47 PM PDT 24
Peak memory 206920 kb
Host smart-90c2c95d-bee6-47a2-bf3c-75f173db9488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25421
58411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2542158411
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.299337052
Short name T922
Test name
Test status
Simulation time 149669807 ps
CPU time 0.84 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 206908 kb
Host smart-74a34be4-fee1-49a9-a394-e99af2c44215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29933
7052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.299337052
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.743570736
Short name T2112
Test name
Test status
Simulation time 211568360 ps
CPU time 0.96 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 206924 kb
Host smart-3f8cdb05-dd99-4e07-869e-71df37592817
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=743570736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.743570736
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1278230623
Short name T2201
Test name
Test status
Simulation time 145310357 ps
CPU time 0.87 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:31:47 PM PDT 24
Peak memory 206848 kb
Host smart-99409903-4ce2-43f9-ac91-e9602943fb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12782
30623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1278230623
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2627317107
Short name T979
Test name
Test status
Simulation time 80070422 ps
CPU time 0.73 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:31:49 PM PDT 24
Peak memory 206916 kb
Host smart-b7eb1cef-130d-46c1-a560-abee099e8457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26273
17107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2627317107
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2802580053
Short name T2349
Test name
Test status
Simulation time 10844667495 ps
CPU time 28.92 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:32:16 PM PDT 24
Peak memory 215328 kb
Host smart-3f2fd2b4-4f86-423a-8263-eeae753102cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28025
80053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2802580053
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1640984103
Short name T1613
Test name
Test status
Simulation time 176401280 ps
CPU time 0.94 seconds
Started Jul 30 06:31:49 PM PDT 24
Finished Jul 30 06:31:50 PM PDT 24
Peak memory 206984 kb
Host smart-6d05ec5a-8ba4-4f9c-abb4-3eb0ae16987a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16409
84103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1640984103
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1518905400
Short name T1522
Test name
Test status
Simulation time 219186031 ps
CPU time 1.03 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:31:47 PM PDT 24
Peak memory 206944 kb
Host smart-cd389c05-d915-4e5e-99b1-5adea1451b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15189
05400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1518905400
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3389910691
Short name T2695
Test name
Test status
Simulation time 251077418 ps
CPU time 1.04 seconds
Started Jul 30 06:31:41 PM PDT 24
Finished Jul 30 06:31:42 PM PDT 24
Peak memory 206920 kb
Host smart-642e602d-011f-40b6-a2ee-f50ce0ec9c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33899
10691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3389910691
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.3540569602
Short name T924
Test name
Test status
Simulation time 177169193 ps
CPU time 0.88 seconds
Started Jul 30 06:31:43 PM PDT 24
Finished Jul 30 06:31:44 PM PDT 24
Peak memory 206920 kb
Host smart-68eaacdc-a6ce-4ec0-a028-c22ed46786a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35405
69602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3540569602
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3595395230
Short name T673
Test name
Test status
Simulation time 174634053 ps
CPU time 0.89 seconds
Started Jul 30 06:31:52 PM PDT 24
Finished Jul 30 06:31:53 PM PDT 24
Peak memory 206856 kb
Host smart-0c0974d1-6022-48cb-b2d3-cfbb409940bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35953
95230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3595395230
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.622513703
Short name T617
Test name
Test status
Simulation time 153205589 ps
CPU time 0.84 seconds
Started Jul 30 06:31:44 PM PDT 24
Finished Jul 30 06:31:45 PM PDT 24
Peak memory 206880 kb
Host smart-c288a6a4-5234-4ac4-a850-6110d3149beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62251
3703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.622513703
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2492317793
Short name T1089
Test name
Test status
Simulation time 155520083 ps
CPU time 0.85 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:31:49 PM PDT 24
Peak memory 206948 kb
Host smart-43498ec8-0d8a-44bd-a50f-f1873651b20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24923
17793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2492317793
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3562893525
Short name T708
Test name
Test status
Simulation time 213044473 ps
CPU time 1.03 seconds
Started Jul 30 06:31:41 PM PDT 24
Finished Jul 30 06:31:42 PM PDT 24
Peak memory 206928 kb
Host smart-88412920-b3f2-4e99-9c33-0103354175f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35628
93525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3562893525
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.723241369
Short name T2708
Test name
Test status
Simulation time 6904818540 ps
CPU time 52.54 seconds
Started Jul 30 06:31:43 PM PDT 24
Finished Jul 30 06:32:36 PM PDT 24
Peak memory 216816 kb
Host smart-29001016-263c-44ad-bff7-ce401e0649f4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=723241369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.723241369
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3345433958
Short name T1345
Test name
Test status
Simulation time 175991970 ps
CPU time 0.91 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:31:49 PM PDT 24
Peak memory 206916 kb
Host smart-3f4fab59-c694-4bc4-aa08-523585f0b99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33454
33958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3345433958
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2883813957
Short name T440
Test name
Test status
Simulation time 178010935 ps
CPU time 0.92 seconds
Started Jul 30 06:31:44 PM PDT 24
Finished Jul 30 06:31:45 PM PDT 24
Peak memory 206916 kb
Host smart-b1b9b763-189c-4d28-ae69-041440adf949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28838
13957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2883813957
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.3451329308
Short name T2464
Test name
Test status
Simulation time 901752913 ps
CPU time 2.07 seconds
Started Jul 30 06:31:41 PM PDT 24
Finished Jul 30 06:31:43 PM PDT 24
Peak memory 206996 kb
Host smart-0faa852e-11bc-4b3f-9c75-14aa47a447fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34513
29308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.3451329308
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.4189608342
Short name T864
Test name
Test status
Simulation time 5918486343 ps
CPU time 46.1 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:32:34 PM PDT 24
Peak memory 216680 kb
Host smart-f0b649a4-941f-425a-a94b-9c98d1307ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41896
08342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.4189608342
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.3200634013
Short name T1430
Test name
Test status
Simulation time 2554742782 ps
CPU time 22.34 seconds
Started Jul 30 06:31:49 PM PDT 24
Finished Jul 30 06:32:11 PM PDT 24
Peak memory 207132 kb
Host smart-25876358-16e4-4fb6-a1ef-dc025e0a5c14
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200634013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.3200634013
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2587917935
Short name T1765
Test name
Test status
Simulation time 100905326 ps
CPU time 0.77 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:52 PM PDT 24
Peak memory 206996 kb
Host smart-9b1afdb3-772b-40b2-ac3d-be06741b6f65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2587917935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2587917935
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.3628749024
Short name T2548
Test name
Test status
Simulation time 3901734694 ps
CPU time 6.65 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:32:00 PM PDT 24
Peak memory 207052 kb
Host smart-0ea6ae15-2af2-40b0-95c3-1307ca3e3104
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628749024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_disconnect.3628749024
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2384970619
Short name T482
Test name
Test status
Simulation time 13285700530 ps
CPU time 16.66 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:32:05 PM PDT 24
Peak memory 207128 kb
Host smart-4857d536-ccc4-40ca-a7d2-be925a911fbd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384970619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2384970619
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2008446301
Short name T1855
Test name
Test status
Simulation time 23391837512 ps
CPU time 28 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:32:15 PM PDT 24
Peak memory 207124 kb
Host smart-dfa65abb-fa2d-4028-839a-4f6346094647
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008446301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.2008446301
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2356269259
Short name T2697
Test name
Test status
Simulation time 147386927 ps
CPU time 0.83 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 206888 kb
Host smart-4539ee5c-1d0e-4890-a89f-4a79b3ab6303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23562
69259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2356269259
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1153521740
Short name T2213
Test name
Test status
Simulation time 177893556 ps
CPU time 0.86 seconds
Started Jul 30 06:31:44 PM PDT 24
Finished Jul 30 06:31:45 PM PDT 24
Peak memory 206888 kb
Host smart-eca8bd5e-3b4a-40d7-acf2-09bc4e9f3b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11535
21740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1153521740
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.1499991123
Short name T245
Test name
Test status
Simulation time 478056021 ps
CPU time 1.57 seconds
Started Jul 30 06:31:49 PM PDT 24
Finished Jul 30 06:31:50 PM PDT 24
Peak memory 206900 kb
Host smart-26d89db8-ce7a-415e-a87e-81ec241bbb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14999
91123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.1499991123
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.990579342
Short name T1580
Test name
Test status
Simulation time 417075500 ps
CPU time 1.32 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:52 PM PDT 24
Peak memory 206888 kb
Host smart-ead3db48-27a5-43a3-8294-7d32c014b10c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=990579342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.990579342
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.1024390705
Short name T164
Test name
Test status
Simulation time 7310736312 ps
CPU time 16.85 seconds
Started Jul 30 06:31:50 PM PDT 24
Finished Jul 30 06:32:07 PM PDT 24
Peak memory 207088 kb
Host smart-394bda1d-82db-4faf-90f5-c0fd0e54f5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10243
90705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1024390705
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.2890723076
Short name T575
Test name
Test status
Simulation time 3897913322 ps
CPU time 33.68 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:32:25 PM PDT 24
Peak memory 207216 kb
Host smart-dfd60fd5-254a-4cd9-b7be-eb0ee41a7ade
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890723076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.2890723076
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.291103344
Short name T1822
Test name
Test status
Simulation time 396745650 ps
CPU time 1.3 seconds
Started Jul 30 06:31:53 PM PDT 24
Finished Jul 30 06:31:55 PM PDT 24
Peak memory 206912 kb
Host smart-d7b736fd-c0b4-475d-b166-02fadb62c6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29110
3344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.291103344
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.364468791
Short name T1711
Test name
Test status
Simulation time 164707500 ps
CPU time 0.84 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:31:49 PM PDT 24
Peak memory 206928 kb
Host smart-e4013e27-42e7-42e3-9967-06ea113f2625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36446
8791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.364468791
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.3050079959
Short name T604
Test name
Test status
Simulation time 82324940 ps
CPU time 0.77 seconds
Started Jul 30 06:31:50 PM PDT 24
Finished Jul 30 06:31:51 PM PDT 24
Peak memory 206872 kb
Host smart-9ef3d39f-3791-479e-af5f-f9e0c9520dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30500
79959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3050079959
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2302630462
Short name T669
Test name
Test status
Simulation time 884534052 ps
CPU time 2.5 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 207044 kb
Host smart-38eb8bd6-f952-4aea-a406-6acf9e65f54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23026
30462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2302630462
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3034162594
Short name T2081
Test name
Test status
Simulation time 242939809 ps
CPU time 1.71 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:31:50 PM PDT 24
Peak memory 207024 kb
Host smart-1d34df54-1abd-4c53-8f6c-ea67ef0bc608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30341
62594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3034162594
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.4016045957
Short name T938
Test name
Test status
Simulation time 175384687 ps
CPU time 0.91 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 215164 kb
Host smart-3ea4134a-99fc-4c72-9af7-7961294d2a8c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4016045957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.4016045957
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1687877725
Short name T2626
Test name
Test status
Simulation time 150313059 ps
CPU time 0.9 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:52 PM PDT 24
Peak memory 206872 kb
Host smart-b21bffce-0658-42b5-b61d-6ef6c9f13e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16878
77725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1687877725
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.805463246
Short name T2060
Test name
Test status
Simulation time 237624039 ps
CPU time 1.03 seconds
Started Jul 30 06:31:41 PM PDT 24
Finished Jul 30 06:31:42 PM PDT 24
Peak memory 206908 kb
Host smart-a7b55332-b918-4000-98e9-78cdfcbab654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80546
3246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.805463246
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.4039141227
Short name T314
Test name
Test status
Simulation time 4803182373 ps
CPU time 48.46 seconds
Started Jul 30 06:31:46 PM PDT 24
Finished Jul 30 06:32:34 PM PDT 24
Peak memory 215356 kb
Host smart-421a8e33-b671-4900-a81b-fcffcc5a925c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4039141227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.4039141227
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.2034850311
Short name T1561
Test name
Test status
Simulation time 10300158294 ps
CPU time 126.77 seconds
Started Jul 30 06:31:52 PM PDT 24
Finished Jul 30 06:33:58 PM PDT 24
Peak memory 207104 kb
Host smart-67c891bf-f86b-4c8b-8fb4-9d3e2d938edb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2034850311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.2034850311
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3580507887
Short name T741
Test name
Test status
Simulation time 300684837 ps
CPU time 1.11 seconds
Started Jul 30 06:31:49 PM PDT 24
Finished Jul 30 06:31:50 PM PDT 24
Peak memory 206908 kb
Host smart-341afc02-6099-4f3c-a66b-8de8d1523e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35805
07887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3580507887
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.819785008
Short name T2178
Test name
Test status
Simulation time 23301972239 ps
CPU time 34.93 seconds
Started Jul 30 06:31:49 PM PDT 24
Finished Jul 30 06:32:24 PM PDT 24
Peak memory 207164 kb
Host smart-4e30ef2c-65bc-4f51-955e-5a1363a835a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81978
5008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.819785008
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.718433518
Short name T2331
Test name
Test status
Simulation time 3313395083 ps
CPU time 4.97 seconds
Started Jul 30 06:31:53 PM PDT 24
Finished Jul 30 06:31:58 PM PDT 24
Peak memory 207072 kb
Host smart-080097de-df67-422e-b844-e889262b9141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71843
3518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.718433518
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.3798330840
Short name T1014
Test name
Test status
Simulation time 5748859086 ps
CPU time 57.04 seconds
Started Jul 30 06:31:50 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 216948 kb
Host smart-c07a7276-55c9-420e-9664-799fe18ac93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37983
30840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.3798330840
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.3723222293
Short name T2298
Test name
Test status
Simulation time 6232229890 ps
CPU time 46.2 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:32:34 PM PDT 24
Peak memory 207140 kb
Host smart-0ed13dc6-b4d4-4206-851f-be1cd782b696
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3723222293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.3723222293
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.103255537
Short name T2846
Test name
Test status
Simulation time 243902884 ps
CPU time 1.01 seconds
Started Jul 30 06:31:50 PM PDT 24
Finished Jul 30 06:31:51 PM PDT 24
Peak memory 206932 kb
Host smart-cafced9e-3962-4d7c-a44f-219723d992f2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=103255537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.103255537
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.4068748684
Short name T1851
Test name
Test status
Simulation time 198600600 ps
CPU time 0.93 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206916 kb
Host smart-1feb112b-b041-4223-be7b-8765cae5acd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40687
48684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.4068748684
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.4103912847
Short name T555
Test name
Test status
Simulation time 5642090637 ps
CPU time 160.78 seconds
Started Jul 30 06:31:50 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 215312 kb
Host smart-8412c4ba-a050-4e9e-b860-cb4e03510f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41039
12847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.4103912847
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.900797011
Short name T496
Test name
Test status
Simulation time 4812233916 ps
CPU time 39.93 seconds
Started Jul 30 06:31:52 PM PDT 24
Finished Jul 30 06:32:32 PM PDT 24
Peak memory 216468 kb
Host smart-7ee546a0-febb-4a2a-b388-0253f492354f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=900797011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.900797011
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.1454609201
Short name T2798
Test name
Test status
Simulation time 151560104 ps
CPU time 0.85 seconds
Started Jul 30 06:31:53 PM PDT 24
Finished Jul 30 06:31:54 PM PDT 24
Peak memory 206944 kb
Host smart-d564c20c-4f3c-4dcf-8828-cde5ec6d7ae6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1454609201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.1454609201
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.74215072
Short name T416
Test name
Test status
Simulation time 146106348 ps
CPU time 0.86 seconds
Started Jul 30 06:31:49 PM PDT 24
Finished Jul 30 06:31:50 PM PDT 24
Peak memory 206952 kb
Host smart-48547927-fc5f-427c-8c3e-2f31a4fdf3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74215
072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.74215072
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3975235273
Short name T121
Test name
Test status
Simulation time 216596496 ps
CPU time 0.97 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 206956 kb
Host smart-1e876695-c6b9-4af5-bfee-0334c18a6e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39752
35273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3975235273
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3224740464
Short name T849
Test name
Test status
Simulation time 186775460 ps
CPU time 0.95 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:31:55 PM PDT 24
Peak memory 206952 kb
Host smart-6ef36e30-5a43-4ca7-9055-989ead0bc3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32247
40464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3224740464
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3367820413
Short name T2237
Test name
Test status
Simulation time 208434745 ps
CPU time 0.9 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:52 PM PDT 24
Peak memory 206976 kb
Host smart-e304ef4b-842d-4b18-a1b3-533571b910cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33678
20413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3367820413
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.845661715
Short name T1436
Test name
Test status
Simulation time 208850190 ps
CPU time 0.96 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206944 kb
Host smart-a2ce8e3d-2963-4468-a482-9f43d69211d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84566
1715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.845661715
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3874460007
Short name T156
Test name
Test status
Simulation time 175637601 ps
CPU time 0.85 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:52 PM PDT 24
Peak memory 206920 kb
Host smart-cdd909c8-29e4-4baa-ba80-836d012285f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38744
60007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3874460007
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1324475571
Short name T2197
Test name
Test status
Simulation time 230098483 ps
CPU time 0.94 seconds
Started Jul 30 06:31:53 PM PDT 24
Finished Jul 30 06:31:54 PM PDT 24
Peak memory 206988 kb
Host smart-a88a4c6e-3113-4b0e-b2ef-04cb3ec917f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1324475571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1324475571
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.3273245700
Short name T18
Test name
Test status
Simulation time 151675901 ps
CPU time 0.86 seconds
Started Jul 30 06:31:52 PM PDT 24
Finished Jul 30 06:31:53 PM PDT 24
Peak memory 206920 kb
Host smart-39356bdd-9e17-4a23-8e90-fd95e4f68b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32732
45700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.3273245700
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.81161265
Short name T2030
Test name
Test status
Simulation time 32711095 ps
CPU time 0.69 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:31:55 PM PDT 24
Peak memory 206876 kb
Host smart-a4db0015-1fe6-4c1c-b002-9c0f6705576b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81161
265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.81161265
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3906708901
Short name T1397
Test name
Test status
Simulation time 21143022669 ps
CPU time 52.73 seconds
Started Jul 30 06:31:55 PM PDT 24
Finished Jul 30 06:32:48 PM PDT 24
Peak memory 223532 kb
Host smart-5a002389-a2e1-45b8-aa70-68e26e1d4db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39067
08901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3906708901
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2928731621
Short name T949
Test name
Test status
Simulation time 175237459 ps
CPU time 0.89 seconds
Started Jul 30 06:31:50 PM PDT 24
Finished Jul 30 06:31:51 PM PDT 24
Peak memory 206912 kb
Host smart-a8de3323-79f4-4e4c-8b68-48173a685ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29287
31621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2928731621
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2939272697
Short name T2692
Test name
Test status
Simulation time 235792985 ps
CPU time 0.98 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:31:49 PM PDT 24
Peak memory 206892 kb
Host smart-87e1791b-44a4-4f13-b094-dbcf57a52ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29392
72697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2939272697
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2059126036
Short name T1234
Test name
Test status
Simulation time 174506472 ps
CPU time 0.98 seconds
Started Jul 30 06:31:52 PM PDT 24
Finished Jul 30 06:31:53 PM PDT 24
Peak memory 206948 kb
Host smart-dcf38596-0ffc-47e4-b317-d9029d96711c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20591
26036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2059126036
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.2721161116
Short name T747
Test name
Test status
Simulation time 198408933 ps
CPU time 0.92 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:52 PM PDT 24
Peak memory 206980 kb
Host smart-454d2062-0d0a-4421-9a1f-6776f972bd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27211
61116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.2721161116
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1525229224
Short name T775
Test name
Test status
Simulation time 160333063 ps
CPU time 0.9 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:31:55 PM PDT 24
Peak memory 206956 kb
Host smart-20277f3e-7a3c-4d56-ad5d-eef5a43c3c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15252
29224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1525229224
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1072475061
Short name T2342
Test name
Test status
Simulation time 163279776 ps
CPU time 0.89 seconds
Started Jul 30 06:31:56 PM PDT 24
Finished Jul 30 06:31:57 PM PDT 24
Peak memory 206948 kb
Host smart-19f99c24-31ef-4f78-ade0-666ff5b79ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10724
75061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1072475061
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2618831939
Short name T439
Test name
Test status
Simulation time 150346029 ps
CPU time 0.85 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:31:55 PM PDT 24
Peak memory 206988 kb
Host smart-4b0e2069-ed07-48ed-99a1-ce37c24e7cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26188
31939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2618831939
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.4046299090
Short name T679
Test name
Test status
Simulation time 246920823 ps
CPU time 1.06 seconds
Started Jul 30 06:31:45 PM PDT 24
Finished Jul 30 06:31:46 PM PDT 24
Peak memory 206912 kb
Host smart-eac20256-ec53-4d70-ab64-2fb812f49aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40462
99090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4046299090
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.4018955417
Short name T2768
Test name
Test status
Simulation time 3888838657 ps
CPU time 39.97 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:32:31 PM PDT 24
Peak memory 216396 kb
Host smart-b8fae6dc-83f9-43c0-80f3-e31efbbdb59e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4018955417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.4018955417
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1922740395
Short name T945
Test name
Test status
Simulation time 197430228 ps
CPU time 1.01 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:31:48 PM PDT 24
Peak memory 206968 kb
Host smart-414739e9-0a33-4490-9001-9468b7046fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19227
40395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1922740395
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1015119256
Short name T469
Test name
Test status
Simulation time 188569006 ps
CPU time 0.88 seconds
Started Jul 30 06:31:50 PM PDT 24
Finished Jul 30 06:31:51 PM PDT 24
Peak memory 206952 kb
Host smart-5e0911a8-a8ec-4099-8e7a-e6f616011683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10151
19256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1015119256
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.1895567353
Short name T1298
Test name
Test status
Simulation time 435466015 ps
CPU time 1.31 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:31:56 PM PDT 24
Peak memory 206932 kb
Host smart-22805b66-90b7-4c79-a519-89e6f8eedcd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18955
67353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.1895567353
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.4289996298
Short name T524
Test name
Test status
Simulation time 3415958413 ps
CPU time 101.95 seconds
Started Jul 30 06:31:50 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 215292 kb
Host smart-561a1269-5eea-40d1-ae63-2c9a62f796a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42899
96298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.4289996298
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.1640347648
Short name T917
Test name
Test status
Simulation time 2573612766 ps
CPU time 17.87 seconds
Started Jul 30 06:31:49 PM PDT 24
Finished Jul 30 06:32:07 PM PDT 24
Peak memory 207160 kb
Host smart-5fc3eeac-33b8-45da-8f58-1b1df7728453
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640347648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.1640347648
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.2732508772
Short name T2033
Test name
Test status
Simulation time 34190752 ps
CPU time 0.69 seconds
Started Jul 30 06:32:01 PM PDT 24
Finished Jul 30 06:32:02 PM PDT 24
Peak memory 207032 kb
Host smart-ba7ec5d5-cb50-4caa-9a5c-88d2a79fa352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2732508772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.2732508772
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.2664254874
Short name T829
Test name
Test status
Simulation time 4360371423 ps
CPU time 6.75 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:58 PM PDT 24
Peak memory 207124 kb
Host smart-e1bf891f-e5c0-4105-a411-0112b1690eff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664254874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.2664254874
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.423746292
Short name T1179
Test name
Test status
Simulation time 13341287674 ps
CPU time 16.05 seconds
Started Jul 30 06:31:53 PM PDT 24
Finished Jul 30 06:32:09 PM PDT 24
Peak memory 207136 kb
Host smart-97afe3a7-4e89-4815-8aa1-c81e26e95326
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=423746292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.423746292
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.515863374
Short name T1114
Test name
Test status
Simulation time 23364372954 ps
CPU time 28.09 seconds
Started Jul 30 06:31:59 PM PDT 24
Finished Jul 30 06:32:27 PM PDT 24
Peak memory 207208 kb
Host smart-f52e70a6-10ee-471a-b029-34cbac5ae3ea
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515863374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_ao
n_wake_resume.515863374
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.82664709
Short name T2261
Test name
Test status
Simulation time 200107875 ps
CPU time 0.92 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:31:55 PM PDT 24
Peak memory 206908 kb
Host smart-6bbde134-6598-4d1c-9092-b6d4e7c6b2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82664
709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.82664709
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.1326376171
Short name T1914
Test name
Test status
Simulation time 149029417 ps
CPU time 0.88 seconds
Started Jul 30 06:31:57 PM PDT 24
Finished Jul 30 06:31:58 PM PDT 24
Peak memory 206916 kb
Host smart-e4a7ee52-4db8-4467-94a0-277418d5caad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13263
76171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.1326376171
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.3984589996
Short name T1683
Test name
Test status
Simulation time 638640246 ps
CPU time 2.28 seconds
Started Jul 30 06:31:50 PM PDT 24
Finished Jul 30 06:31:53 PM PDT 24
Peak memory 207016 kb
Host smart-c22e02ef-33a6-4c02-b797-30164fb488d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39845
89996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.3984589996
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2678712224
Short name T1205
Test name
Test status
Simulation time 329333316 ps
CPU time 1.09 seconds
Started Jul 30 06:31:58 PM PDT 24
Finished Jul 30 06:31:59 PM PDT 24
Peak memory 206980 kb
Host smart-f634fa19-f221-4f23-88b6-ce4ad6cfcdaa
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2678712224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2678712224
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.3257209070
Short name T763
Test name
Test status
Simulation time 12145666392 ps
CPU time 24.43 seconds
Started Jul 30 06:32:03 PM PDT 24
Finished Jul 30 06:32:28 PM PDT 24
Peak memory 207132 kb
Host smart-f2da7fac-cb97-41bb-a53e-95a9f908c536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32572
09070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.3257209070
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.3139171675
Short name T2721
Test name
Test status
Simulation time 1565387634 ps
CPU time 10.13 seconds
Started Jul 30 06:31:58 PM PDT 24
Finished Jul 30 06:32:08 PM PDT 24
Peak memory 207044 kb
Host smart-71b806d0-b255-4f15-854f-8a6d2a747a59
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139171675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.3139171675
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.756469020
Short name T95
Test name
Test status
Simulation time 359050356 ps
CPU time 1.26 seconds
Started Jul 30 06:32:01 PM PDT 24
Finished Jul 30 06:32:02 PM PDT 24
Peak memory 206884 kb
Host smart-d5b68454-f506-45fd-aced-56221d7dc3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75646
9020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.756469020
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.4146683227
Short name T2478
Test name
Test status
Simulation time 134960803 ps
CPU time 0.84 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:52 PM PDT 24
Peak memory 206916 kb
Host smart-dcd27487-584c-4fde-bd20-e244c1f2e171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41466
83227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.4146683227
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.825506477
Short name T2455
Test name
Test status
Simulation time 74592078 ps
CPU time 0.72 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:52 PM PDT 24
Peak memory 206896 kb
Host smart-ca89fdcf-86b6-43b9-a915-c1aa5a861676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82550
6477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.825506477
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.890370083
Short name T725
Test name
Test status
Simulation time 953397554 ps
CPU time 2.33 seconds
Started Jul 30 06:31:57 PM PDT 24
Finished Jul 30 06:31:59 PM PDT 24
Peak memory 207112 kb
Host smart-c01d34b8-9f5b-4877-ad3b-4f9bd6ad2aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89037
0083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.890370083
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3222248984
Short name T981
Test name
Test status
Simulation time 333546672 ps
CPU time 2.23 seconds
Started Jul 30 06:31:56 PM PDT 24
Finished Jul 30 06:31:58 PM PDT 24
Peak memory 206944 kb
Host smart-2971c7a6-e693-45ef-8d73-d25882a0be92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32222
48984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3222248984
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.3702172518
Short name T1447
Test name
Test status
Simulation time 219045958 ps
CPU time 1.09 seconds
Started Jul 30 06:31:59 PM PDT 24
Finished Jul 30 06:32:01 PM PDT 24
Peak memory 215216 kb
Host smart-d0fbed33-31df-44a6-96ca-9c4fb7aec333
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3702172518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3702172518
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.4001997592
Short name T921
Test name
Test status
Simulation time 144217036 ps
CPU time 0.82 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:51 PM PDT 24
Peak memory 206872 kb
Host smart-dfe7d915-0a13-4a48-8f7c-70a0124c3056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40019
97592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.4001997592
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3096951794
Short name T1228
Test name
Test status
Simulation time 219808002 ps
CPU time 0.97 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:31:49 PM PDT 24
Peak memory 206900 kb
Host smart-6090dadd-a3f6-44fb-a265-09af76d062b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30969
51794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3096951794
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.1723557789
Short name T1138
Test name
Test status
Simulation time 8429355404 ps
CPU time 253.99 seconds
Started Jul 30 06:32:00 PM PDT 24
Finished Jul 30 06:36:14 PM PDT 24
Peak memory 216736 kb
Host smart-d678a3da-7f16-4f87-a720-8581cac2dee2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1723557789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.1723557789
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.126329309
Short name T2608
Test name
Test status
Simulation time 5467139144 ps
CPU time 69.01 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:32:58 PM PDT 24
Peak memory 207148 kb
Host smart-27216a1d-a3f6-4604-b213-d297b0be3aae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=126329309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.126329309
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2752398732
Short name T909
Test name
Test status
Simulation time 274263462 ps
CPU time 1.03 seconds
Started Jul 30 06:31:55 PM PDT 24
Finished Jul 30 06:31:56 PM PDT 24
Peak memory 206944 kb
Host smart-ac64be79-4591-4bb1-860b-d28fa56ff757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27523
98732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2752398732
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.1669016132
Short name T2322
Test name
Test status
Simulation time 23381974549 ps
CPU time 34.64 seconds
Started Jul 30 06:31:55 PM PDT 24
Finished Jul 30 06:32:29 PM PDT 24
Peak memory 207164 kb
Host smart-902823f8-a28a-41a0-a4df-2f63ef8d3065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16690
16132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.1669016132
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2682094436
Short name T1435
Test name
Test status
Simulation time 3307336692 ps
CPU time 5.64 seconds
Started Jul 30 06:31:55 PM PDT 24
Finished Jul 30 06:32:01 PM PDT 24
Peak memory 207072 kb
Host smart-502084b6-d8f5-4401-abf0-43b49787d4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26820
94436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2682094436
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.610670293
Short name T2302
Test name
Test status
Simulation time 7081288757 ps
CPU time 68.13 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:33:02 PM PDT 24
Peak memory 223568 kb
Host smart-8707b104-5caf-4853-882c-824184b4f37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61067
0293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.610670293
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.3535930608
Short name T1903
Test name
Test status
Simulation time 5726724040 ps
CPU time 170.22 seconds
Started Jul 30 06:31:55 PM PDT 24
Finished Jul 30 06:34:46 PM PDT 24
Peak memory 215288 kb
Host smart-23d24a51-7dd4-46c5-9e33-8b9f62320193
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3535930608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3535930608
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1103741544
Short name T647
Test name
Test status
Simulation time 245920339 ps
CPU time 1.04 seconds
Started Jul 30 06:31:49 PM PDT 24
Finished Jul 30 06:31:50 PM PDT 24
Peak memory 206952 kb
Host smart-45d2a5a0-64a2-4a15-8249-d32dfccacc76
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1103741544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1103741544
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.4198728736
Short name T762
Test name
Test status
Simulation time 209873926 ps
CPU time 0.97 seconds
Started Jul 30 06:32:02 PM PDT 24
Finished Jul 30 06:32:04 PM PDT 24
Peak memory 206940 kb
Host smart-653fc9dc-c3bc-48a5-866a-bbfaf0027182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41987
28736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.4198728736
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.1574121878
Short name T2408
Test name
Test status
Simulation time 6868608284 ps
CPU time 52.14 seconds
Started Jul 30 06:31:47 PM PDT 24
Finished Jul 30 06:32:39 PM PDT 24
Peak memory 216864 kb
Host smart-6fbe5aa3-3d25-47ba-9501-564043abeb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15741
21878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.1574121878
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.620673190
Short name T2638
Test name
Test status
Simulation time 4340826013 ps
CPU time 126.84 seconds
Started Jul 30 06:31:56 PM PDT 24
Finished Jul 30 06:34:03 PM PDT 24
Peak memory 215324 kb
Host smart-10957d71-8978-4508-b18b-126e9bbeb666
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=620673190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.620673190
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.2638892927
Short name T870
Test name
Test status
Simulation time 155584378 ps
CPU time 0.84 seconds
Started Jul 30 06:31:49 PM PDT 24
Finished Jul 30 06:31:50 PM PDT 24
Peak memory 206944 kb
Host smart-21bee111-7f0c-43a4-b7be-5a610273d718
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2638892927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.2638892927
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2222164722
Short name T1838
Test name
Test status
Simulation time 164339883 ps
CPU time 0.89 seconds
Started Jul 30 06:31:49 PM PDT 24
Finished Jul 30 06:31:50 PM PDT 24
Peak memory 206912 kb
Host smart-f5113bad-a554-47cd-b97a-22056dfbb627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22221
64722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2222164722
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.4123852173
Short name T566
Test name
Test status
Simulation time 165834460 ps
CPU time 0.88 seconds
Started Jul 30 06:31:56 PM PDT 24
Finished Jul 30 06:31:57 PM PDT 24
Peak memory 206908 kb
Host smart-b3162ac2-25fb-4f4b-a2ab-c22196ee6b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41238
52173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.4123852173
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.240392158
Short name T1836
Test name
Test status
Simulation time 194225682 ps
CPU time 0.84 seconds
Started Jul 30 06:31:58 PM PDT 24
Finished Jul 30 06:31:59 PM PDT 24
Peak memory 206940 kb
Host smart-0048df38-9fe5-450f-9f71-2baec4ed942d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24039
2158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.240392158
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1089824923
Short name T2600
Test name
Test status
Simulation time 171808815 ps
CPU time 0.85 seconds
Started Jul 30 06:31:48 PM PDT 24
Finished Jul 30 06:31:49 PM PDT 24
Peak memory 206980 kb
Host smart-79c69ef6-33b6-4629-8799-b75fddbd1fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10898
24923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1089824923
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.4262221132
Short name T2039
Test name
Test status
Simulation time 153164877 ps
CPU time 0.85 seconds
Started Jul 30 06:32:05 PM PDT 24
Finished Jul 30 06:32:06 PM PDT 24
Peak memory 206912 kb
Host smart-7d35f0df-d5c1-4317-8c15-9bdeab03c846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42622
21132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.4262221132
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.518742379
Short name T526
Test name
Test status
Simulation time 177541911 ps
CPU time 0.88 seconds
Started Jul 30 06:31:51 PM PDT 24
Finished Jul 30 06:31:52 PM PDT 24
Peak memory 206968 kb
Host smart-e26e02d0-0ed4-403c-b2af-8b606cbb2d75
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=518742379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.518742379
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.4134516285
Short name T546
Test name
Test status
Simulation time 182147755 ps
CPU time 0.9 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:31:55 PM PDT 24
Peak memory 206896 kb
Host smart-6aafe026-6901-41e0-bf80-b3e5cf56bc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41345
16285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.4134516285
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.898623126
Short name T2174
Test name
Test status
Simulation time 34357847 ps
CPU time 0.69 seconds
Started Jul 30 06:31:56 PM PDT 24
Finished Jul 30 06:31:57 PM PDT 24
Peak memory 206880 kb
Host smart-45307039-a594-49fc-bae6-5e4b4d88be40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89862
3126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.898623126
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2478533315
Short name T2577
Test name
Test status
Simulation time 23629962386 ps
CPU time 58.71 seconds
Started Jul 30 06:31:57 PM PDT 24
Finished Jul 30 06:32:56 PM PDT 24
Peak memory 215308 kb
Host smart-b650af4a-7aaf-4e05-b27c-6b65cd6fdebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24785
33315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2478533315
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3357586467
Short name T2181
Test name
Test status
Simulation time 196384084 ps
CPU time 1.01 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:31:55 PM PDT 24
Peak memory 206936 kb
Host smart-b076a0fe-13e9-4156-87e6-ec20f8b2519b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33575
86467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3357586467
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.358262658
Short name T1329
Test name
Test status
Simulation time 153622036 ps
CPU time 0.87 seconds
Started Jul 30 06:31:55 PM PDT 24
Finished Jul 30 06:31:56 PM PDT 24
Peak memory 206888 kb
Host smart-cf1b15cd-4c7a-48ed-b828-6304d99757b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35826
2658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.358262658
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.3390658372
Short name T1529
Test name
Test status
Simulation time 209479704 ps
CPU time 0.97 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:31:55 PM PDT 24
Peak memory 206952 kb
Host smart-30a7eede-1214-417c-b12e-5ac6846fc006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33906
58372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.3390658372
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.1567443063
Short name T1108
Test name
Test status
Simulation time 153430686 ps
CPU time 0.85 seconds
Started Jul 30 06:32:00 PM PDT 24
Finished Jul 30 06:32:01 PM PDT 24
Peak memory 206940 kb
Host smart-85b7bbed-a163-4aab-9830-829860a72e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15674
43063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.1567443063
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.2645131618
Short name T388
Test name
Test status
Simulation time 191824881 ps
CPU time 0.97 seconds
Started Jul 30 06:32:00 PM PDT 24
Finished Jul 30 06:32:01 PM PDT 24
Peak memory 206908 kb
Host smart-4b66aae9-5c3f-4330-b52b-5ec7c3a3e7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26451
31618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.2645131618
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1491886177
Short name T2743
Test name
Test status
Simulation time 148434958 ps
CPU time 0.86 seconds
Started Jul 30 06:32:01 PM PDT 24
Finished Jul 30 06:32:02 PM PDT 24
Peak memory 206896 kb
Host smart-6a0fa1a3-13e1-4b97-ab13-876917dbe8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14918
86177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1491886177
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2591381132
Short name T1891
Test name
Test status
Simulation time 176481795 ps
CPU time 0.95 seconds
Started Jul 30 06:31:54 PM PDT 24
Finished Jul 30 06:31:55 PM PDT 24
Peak memory 206944 kb
Host smart-e1f36709-a84c-42bb-a4b6-500a22736ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25913
81132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2591381132
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1083556314
Short name T1148
Test name
Test status
Simulation time 286201957 ps
CPU time 1.18 seconds
Started Jul 30 06:31:56 PM PDT 24
Finished Jul 30 06:31:58 PM PDT 24
Peak memory 206920 kb
Host smart-b37d20fc-6270-41a7-804c-8ba7c796d7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10835
56314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1083556314
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.1429975926
Short name T947
Test name
Test status
Simulation time 5208339692 ps
CPU time 40.18 seconds
Started Jul 30 06:31:58 PM PDT 24
Finished Jul 30 06:32:38 PM PDT 24
Peak memory 216864 kb
Host smart-c3d26df5-4df9-494d-8ae6-b1fb04a4adb6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1429975926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.1429975926
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.872194212
Short name T394
Test name
Test status
Simulation time 178775432 ps
CPU time 0.92 seconds
Started Jul 30 06:31:58 PM PDT 24
Finished Jul 30 06:31:59 PM PDT 24
Peak memory 206916 kb
Host smart-8c8e86f1-dca3-4750-9bfe-4f2afbcaaf3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87219
4212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.872194212
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1818658580
Short name T1494
Test name
Test status
Simulation time 197949657 ps
CPU time 0.91 seconds
Started Jul 30 06:31:53 PM PDT 24
Finished Jul 30 06:31:54 PM PDT 24
Peak memory 206876 kb
Host smart-f617f673-4946-4997-8c02-7684305025e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18186
58580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1818658580
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.205511382
Short name T2790
Test name
Test status
Simulation time 730464401 ps
CPU time 1.96 seconds
Started Jul 30 06:31:55 PM PDT 24
Finished Jul 30 06:31:58 PM PDT 24
Peak memory 206880 kb
Host smart-b57518b9-25ea-4c3c-b943-4c57b072b021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20551
1382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.205511382
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.2521166474
Short name T2280
Test name
Test status
Simulation time 6268718726 ps
CPU time 50.22 seconds
Started Jul 30 06:32:00 PM PDT 24
Finished Jul 30 06:32:51 PM PDT 24
Peak memory 207116 kb
Host smart-1778bae0-fe8e-47b4-9d5c-97c8357808f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25211
66474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.2521166474
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.4087039256
Short name T1558
Test name
Test status
Simulation time 1075857464 ps
CPU time 8.92 seconds
Started Jul 30 06:31:50 PM PDT 24
Finished Jul 30 06:31:59 PM PDT 24
Peak memory 207028 kb
Host smart-2963a9b4-ae50-4bf2-9c43-b7b12653536f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087039256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.4087039256
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.2757630504
Short name T2651
Test name
Test status
Simulation time 42157376 ps
CPU time 0.66 seconds
Started Jul 30 06:32:05 PM PDT 24
Finished Jul 30 06:32:06 PM PDT 24
Peak memory 207000 kb
Host smart-6f249da4-e7f9-485e-8a51-2f09f7b7e755
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2757630504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.2757630504
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.394872102
Short name T219
Test name
Test status
Simulation time 3972755583 ps
CPU time 5.77 seconds
Started Jul 30 06:32:00 PM PDT 24
Finished Jul 30 06:32:06 PM PDT 24
Peak memory 207088 kb
Host smart-aa1af1e6-d636-46fd-ba60-d32a7706dc51
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394872102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_ao
n_wake_disconnect.394872102
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.2652323951
Short name T2297
Test name
Test status
Simulation time 13492075889 ps
CPU time 15.49 seconds
Started Jul 30 06:32:01 PM PDT 24
Finished Jul 30 06:32:16 PM PDT 24
Peak memory 207156 kb
Host smart-e99b3997-2567-4357-aa73-199b2d7cada0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652323951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.2652323951
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.2666220740
Short name T587
Test name
Test status
Simulation time 23371629795 ps
CPU time 28.13 seconds
Started Jul 30 06:31:55 PM PDT 24
Finished Jul 30 06:32:23 PM PDT 24
Peak memory 207104 kb
Host smart-2a57ed22-3f64-48dc-b093-c01caa164cf7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666220740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.2666220740
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2344800528
Short name T2226
Test name
Test status
Simulation time 159120910 ps
CPU time 0.9 seconds
Started Jul 30 06:32:09 PM PDT 24
Finished Jul 30 06:32:10 PM PDT 24
Peak memory 206920 kb
Host smart-393554d7-6403-457e-b646-d8afae8811c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23448
00528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2344800528
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3459561447
Short name T2161
Test name
Test status
Simulation time 174590895 ps
CPU time 0.85 seconds
Started Jul 30 06:31:56 PM PDT 24
Finished Jul 30 06:31:57 PM PDT 24
Peak memory 206904 kb
Host smart-91fc713c-7f7a-4f8c-a695-6a28ee7a23c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34595
61447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3459561447
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.1771472608
Short name T1409
Test name
Test status
Simulation time 284670620 ps
CPU time 1.06 seconds
Started Jul 30 06:32:09 PM PDT 24
Finished Jul 30 06:32:10 PM PDT 24
Peak memory 206924 kb
Host smart-20e56af1-691c-44a0-9410-9a5aecbd7ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17714
72608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.1771472608
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.4078818404
Short name T1167
Test name
Test status
Simulation time 492982503 ps
CPU time 1.64 seconds
Started Jul 30 06:32:01 PM PDT 24
Finished Jul 30 06:32:03 PM PDT 24
Peak memory 206924 kb
Host smart-94c6dfd7-4b48-4c13-8d4e-90af5b906fb9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4078818404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.4078818404
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.2973467313
Short name T333
Test name
Test status
Simulation time 273180083 ps
CPU time 4.5 seconds
Started Jul 30 06:32:04 PM PDT 24
Finished Jul 30 06:32:08 PM PDT 24
Peak memory 207032 kb
Host smart-940e4415-58d1-4bc7-af96-ab2e0ab11fd9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973467313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.2973467313
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.215729225
Short name T454
Test name
Test status
Simulation time 438936583 ps
CPU time 1.45 seconds
Started Jul 30 06:31:56 PM PDT 24
Finished Jul 30 06:31:58 PM PDT 24
Peak memory 206896 kb
Host smart-b6696c07-71c7-4b4e-8212-1f5cd49e9694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21572
9225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.215729225
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1152052260
Short name T984
Test name
Test status
Simulation time 150116976 ps
CPU time 0.81 seconds
Started Jul 30 06:31:56 PM PDT 24
Finished Jul 30 06:31:57 PM PDT 24
Peak memory 206880 kb
Host smart-001d1562-f1e1-40f0-b730-111cdbe7b979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11520
52260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1152052260
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.913599508
Short name T2542
Test name
Test status
Simulation time 34896748 ps
CPU time 0.73 seconds
Started Jul 30 06:31:59 PM PDT 24
Finished Jul 30 06:32:00 PM PDT 24
Peak memory 206892 kb
Host smart-db630dab-948e-4a9a-8b70-85557d5e4b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91359
9508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.913599508
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.533044339
Short name T890
Test name
Test status
Simulation time 800695096 ps
CPU time 2.11 seconds
Started Jul 30 06:32:02 PM PDT 24
Finished Jul 30 06:32:04 PM PDT 24
Peak memory 207064 kb
Host smart-915189b6-07f3-45d6-bc56-5d71645637fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53304
4339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.533044339
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.566335841
Short name T1818
Test name
Test status
Simulation time 165308716 ps
CPU time 1.5 seconds
Started Jul 30 06:32:00 PM PDT 24
Finished Jul 30 06:32:02 PM PDT 24
Peak memory 207000 kb
Host smart-340d0114-2461-42f4-b139-dbd62d122579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56633
5841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.566335841
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1063411567
Short name T1896
Test name
Test status
Simulation time 199489182 ps
CPU time 1.07 seconds
Started Jul 30 06:31:59 PM PDT 24
Finished Jul 30 06:32:00 PM PDT 24
Peak memory 215208 kb
Host smart-6d4e6945-87f6-4905-a426-9e1505f547b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1063411567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1063411567
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.546568717
Short name T2620
Test name
Test status
Simulation time 176182477 ps
CPU time 0.87 seconds
Started Jul 30 06:31:58 PM PDT 24
Finished Jul 30 06:31:59 PM PDT 24
Peak memory 206876 kb
Host smart-af31db10-f012-4d6d-be38-f494b41eadda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54656
8717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.546568717
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2481667652
Short name T718
Test name
Test status
Simulation time 271187931 ps
CPU time 1.07 seconds
Started Jul 30 06:32:00 PM PDT 24
Finished Jul 30 06:32:02 PM PDT 24
Peak memory 206920 kb
Host smart-8699e0e3-4b74-4cad-99e5-6f00a90e3403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
67652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2481667652
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.658309095
Short name T2390
Test name
Test status
Simulation time 9112669520 ps
CPU time 65.64 seconds
Started Jul 30 06:32:04 PM PDT 24
Finished Jul 30 06:33:10 PM PDT 24
Peak memory 215320 kb
Host smart-162e63ae-3e98-4efc-ac7f-84dd07b14c15
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=658309095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.658309095
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.784536952
Short name T1136
Test name
Test status
Simulation time 4291349631 ps
CPU time 29.21 seconds
Started Jul 30 06:31:56 PM PDT 24
Finished Jul 30 06:32:25 PM PDT 24
Peak memory 207112 kb
Host smart-5a3f0ce1-ed03-4f3a-a23e-fcdf353d6b07
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=784536952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.784536952
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2438901517
Short name T50
Test name
Test status
Simulation time 190685732 ps
CPU time 0.9 seconds
Started Jul 30 06:31:58 PM PDT 24
Finished Jul 30 06:31:59 PM PDT 24
Peak memory 206904 kb
Host smart-3d73aa96-b9a1-4077-8c9b-cd9132c4c50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24389
01517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2438901517
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.3492882012
Short name T441
Test name
Test status
Simulation time 23339076311 ps
CPU time 28.75 seconds
Started Jul 30 06:31:59 PM PDT 24
Finished Jul 30 06:32:28 PM PDT 24
Peak memory 207156 kb
Host smart-8a0e2338-e698-4df9-a4ca-a97395b911b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34928
82012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.3492882012
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.2671885402
Short name T1753
Test name
Test status
Simulation time 3357710060 ps
CPU time 4.93 seconds
Started Jul 30 06:31:59 PM PDT 24
Finished Jul 30 06:32:04 PM PDT 24
Peak memory 207028 kb
Host smart-82f50da8-4d1b-4561-9613-5006b8a334b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26718
85402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2671885402
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.2716311230
Short name T306
Test name
Test status
Simulation time 7787271645 ps
CPU time 55.98 seconds
Started Jul 30 06:32:04 PM PDT 24
Finished Jul 30 06:33:00 PM PDT 24
Peak memory 223520 kb
Host smart-470b0e23-abbe-4073-bfeb-65fbb26143d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27163
11230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.2716311230
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.4247209498
Short name T1094
Test name
Test status
Simulation time 3409434116 ps
CPU time 29 seconds
Started Jul 30 06:31:58 PM PDT 24
Finished Jul 30 06:32:27 PM PDT 24
Peak memory 216504 kb
Host smart-a70354f2-709d-4b7d-a3f1-276bf49eb786
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4247209498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.4247209498
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.965243828
Short name T1482
Test name
Test status
Simulation time 302904001 ps
CPU time 1.03 seconds
Started Jul 30 06:32:01 PM PDT 24
Finished Jul 30 06:32:02 PM PDT 24
Peak memory 206932 kb
Host smart-be3520dd-5968-4860-b512-1dc33b84f830
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=965243828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.965243828
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2451946972
Short name T832
Test name
Test status
Simulation time 219758369 ps
CPU time 1.02 seconds
Started Jul 30 06:32:00 PM PDT 24
Finished Jul 30 06:32:01 PM PDT 24
Peak memory 206940 kb
Host smart-8d9bd43c-f0fc-499a-83a4-9dadfd7c0460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24519
46972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2451946972
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.4015786439
Short name T2405
Test name
Test status
Simulation time 3901949439 ps
CPU time 109.97 seconds
Started Jul 30 06:31:58 PM PDT 24
Finished Jul 30 06:33:48 PM PDT 24
Peak memory 215320 kb
Host smart-0f087e46-3370-482e-80bd-20c27ec2020e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40157
86439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.4015786439
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.730711492
Short name T618
Test name
Test status
Simulation time 5572372226 ps
CPU time 56.86 seconds
Started Jul 30 06:32:01 PM PDT 24
Finished Jul 30 06:32:58 PM PDT 24
Peak memory 216560 kb
Host smart-87a44c73-dfe5-4e9e-a265-f0634208a7bc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=730711492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.730711492
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.1114016440
Short name T411
Test name
Test status
Simulation time 175286394 ps
CPU time 0.91 seconds
Started Jul 30 06:32:05 PM PDT 24
Finished Jul 30 06:32:06 PM PDT 24
Peak memory 206944 kb
Host smart-ca38fc33-ab14-47e5-b705-e724280c8911
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1114016440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.1114016440
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.144025597
Short name T1157
Test name
Test status
Simulation time 162383695 ps
CPU time 0.81 seconds
Started Jul 30 06:32:04 PM PDT 24
Finished Jul 30 06:32:05 PM PDT 24
Peak memory 206924 kb
Host smart-41f2898f-d3ad-4cd1-beee-887702577e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14402
5597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.144025597
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3397890898
Short name T123
Test name
Test status
Simulation time 212343174 ps
CPU time 0.94 seconds
Started Jul 30 06:32:02 PM PDT 24
Finished Jul 30 06:32:03 PM PDT 24
Peak memory 206948 kb
Host smart-67ec41f1-d5ae-4810-811e-8938cb4fe160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33978
90898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3397890898
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.1865337065
Short name T928
Test name
Test status
Simulation time 200322146 ps
CPU time 0.93 seconds
Started Jul 30 06:32:04 PM PDT 24
Finished Jul 30 06:32:05 PM PDT 24
Peak memory 206908 kb
Host smart-6d61efa4-3413-4588-8c7f-346ef4cf54d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18653
37065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1865337065
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1520997061
Short name T761
Test name
Test status
Simulation time 167647898 ps
CPU time 0.89 seconds
Started Jul 30 06:32:04 PM PDT 24
Finished Jul 30 06:32:05 PM PDT 24
Peak memory 206916 kb
Host smart-dd0d2cf1-5f40-4f2e-8dcf-5179d63029f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15209
97061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1520997061
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.541884249
Short name T1918
Test name
Test status
Simulation time 184827943 ps
CPU time 0.91 seconds
Started Jul 30 06:32:01 PM PDT 24
Finished Jul 30 06:32:02 PM PDT 24
Peak memory 206908 kb
Host smart-1c053445-47e1-41ac-ae61-92c9a80c78dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54188
4249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.541884249
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2609079925
Short name T889
Test name
Test status
Simulation time 157446368 ps
CPU time 0.84 seconds
Started Jul 30 06:32:01 PM PDT 24
Finished Jul 30 06:32:02 PM PDT 24
Peak memory 206904 kb
Host smart-34701069-763a-40af-a6ef-c7ae1ed65b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26090
79925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2609079925
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.4034759493
Short name T455
Test name
Test status
Simulation time 209931192 ps
CPU time 1.02 seconds
Started Jul 30 06:32:01 PM PDT 24
Finished Jul 30 06:32:02 PM PDT 24
Peak memory 206928 kb
Host smart-ca77bf75-da93-4ba8-a0b2-7d337d29aa34
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4034759493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.4034759493
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1129239978
Short name T319
Test name
Test status
Simulation time 156756340 ps
CPU time 0.87 seconds
Started Jul 30 06:32:03 PM PDT 24
Finished Jul 30 06:32:04 PM PDT 24
Peak memory 206892 kb
Host smart-abb871e8-7584-4f2d-a356-9a18e04660b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11292
39978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1129239978
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.4065498025
Short name T34
Test name
Test status
Simulation time 34148483 ps
CPU time 0.73 seconds
Started Jul 30 06:32:07 PM PDT 24
Finished Jul 30 06:32:08 PM PDT 24
Peak memory 206872 kb
Host smart-0d10179e-4e78-4e3f-9b06-a79288d90d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40654
98025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.4065498025
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2448934746
Short name T966
Test name
Test status
Simulation time 15079805985 ps
CPU time 39.27 seconds
Started Jul 30 06:32:01 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 215304 kb
Host smart-8e94ed27-16fe-4b62-86e9-665648ccdeb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24489
34746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2448934746
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3665042755
Short name T1227
Test name
Test status
Simulation time 155865415 ps
CPU time 0.89 seconds
Started Jul 30 06:32:02 PM PDT 24
Finished Jul 30 06:32:03 PM PDT 24
Peak memory 206976 kb
Host smart-46467c2a-227f-423a-8b09-15bb62ace02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36650
42755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3665042755
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1529682245
Short name T2235
Test name
Test status
Simulation time 229426411 ps
CPU time 0.96 seconds
Started Jul 30 06:32:07 PM PDT 24
Finished Jul 30 06:32:08 PM PDT 24
Peak memory 206916 kb
Host smart-55502f6d-02e7-486f-a194-52e9de0c9b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15296
82245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1529682245
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.3912586973
Short name T327
Test name
Test status
Simulation time 170995348 ps
CPU time 0.88 seconds
Started Jul 30 06:32:04 PM PDT 24
Finished Jul 30 06:32:05 PM PDT 24
Peak memory 206908 kb
Host smart-cce26752-65f3-4f5a-92aa-7db04078c963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39125
86973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.3912586973
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1555477507
Short name T2098
Test name
Test status
Simulation time 152109167 ps
CPU time 0.85 seconds
Started Jul 30 06:32:04 PM PDT 24
Finished Jul 30 06:32:05 PM PDT 24
Peak memory 206948 kb
Host smart-7c9424f8-f6a7-4db9-8843-726d68ac9f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15554
77507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1555477507
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3407771802
Short name T22
Test name
Test status
Simulation time 144811490 ps
CPU time 0.9 seconds
Started Jul 30 06:32:03 PM PDT 24
Finished Jul 30 06:32:04 PM PDT 24
Peak memory 206880 kb
Host smart-e077bac0-cc84-4828-b337-9ba574630bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34077
71802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3407771802
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1611875980
Short name T742
Test name
Test status
Simulation time 163937367 ps
CPU time 0.87 seconds
Started Jul 30 06:32:01 PM PDT 24
Finished Jul 30 06:32:02 PM PDT 24
Peak memory 206892 kb
Host smart-0bdbf409-3110-427b-b70c-bf87d80420b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16118
75980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1611875980
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1998124931
Short name T1076
Test name
Test status
Simulation time 166761773 ps
CPU time 0.9 seconds
Started Jul 30 06:32:06 PM PDT 24
Finished Jul 30 06:32:07 PM PDT 24
Peak memory 206912 kb
Host smart-40ad330f-3696-47f8-bde9-5115a8589b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19981
24931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1998124931
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2259341186
Short name T1750
Test name
Test status
Simulation time 233085210 ps
CPU time 1.1 seconds
Started Jul 30 06:32:04 PM PDT 24
Finished Jul 30 06:32:05 PM PDT 24
Peak memory 206916 kb
Host smart-3a94775e-bdca-4a10-9f2d-a383782cfe2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22593
41186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2259341186
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1753892627
Short name T2589
Test name
Test status
Simulation time 5538931878 ps
CPU time 42.17 seconds
Started Jul 30 06:32:06 PM PDT 24
Finished Jul 30 06:32:48 PM PDT 24
Peak memory 216432 kb
Host smart-402edc09-f921-4346-adf1-2e1b4bc19abb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1753892627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1753892627
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1492016194
Short name T1183
Test name
Test status
Simulation time 163800730 ps
CPU time 0.94 seconds
Started Jul 30 06:32:06 PM PDT 24
Finished Jul 30 06:32:07 PM PDT 24
Peak memory 206880 kb
Host smart-6db744ea-87e1-4dd9-9297-6301fe0066db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14920
16194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1492016194
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2650775415
Short name T2657
Test name
Test status
Simulation time 173378140 ps
CPU time 0.9 seconds
Started Jul 30 06:32:06 PM PDT 24
Finished Jul 30 06:32:07 PM PDT 24
Peak memory 206904 kb
Host smart-56d46b47-f48e-40ee-b68f-f74dfcfe4c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26507
75415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2650775415
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.3950051281
Short name T1372
Test name
Test status
Simulation time 1144300356 ps
CPU time 2.71 seconds
Started Jul 30 06:32:15 PM PDT 24
Finished Jul 30 06:32:18 PM PDT 24
Peak memory 207104 kb
Host smart-47d448e7-4b5f-47da-988b-b55eda421295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39500
51281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.3950051281
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3976392733
Short name T1433
Test name
Test status
Simulation time 6656456127 ps
CPU time 193.07 seconds
Started Jul 30 06:32:07 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 215356 kb
Host smart-3cef61bd-521c-4b1f-bfc3-2c101e397494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39763
92733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3976392733
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.1115825975
Short name T1843
Test name
Test status
Simulation time 570462687 ps
CPU time 11.46 seconds
Started Jul 30 06:31:59 PM PDT 24
Finished Jul 30 06:32:10 PM PDT 24
Peak memory 207028 kb
Host smart-77623517-4d33-43ab-a595-73fad6bd9942
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115825975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.1115825975
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.1159844507
Short name T2749
Test name
Test status
Simulation time 58840479 ps
CPU time 0.71 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:32:42 PM PDT 24
Peak memory 207024 kb
Host smart-9a2d83a6-cad7-4092-b015-2c54c6c72dc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1159844507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.1159844507
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1247740951
Short name T218
Test name
Test status
Simulation time 4396912925 ps
CPU time 6.65 seconds
Started Jul 30 06:32:06 PM PDT 24
Finished Jul 30 06:32:13 PM PDT 24
Peak memory 207116 kb
Host smart-22345e38-cfe7-4e8e-b1f7-4fb7649a04f5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247740951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_disconnect.1247740951
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2017713092
Short name T2861
Test name
Test status
Simulation time 13307251852 ps
CPU time 15.29 seconds
Started Jul 30 06:32:06 PM PDT 24
Finished Jul 30 06:32:22 PM PDT 24
Peak memory 207184 kb
Host smart-ce1b2f90-6e8b-4fad-8a22-32503b3d0258
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017713092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2017713092
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2861968519
Short name T2229
Test name
Test status
Simulation time 23425136237 ps
CPU time 28.26 seconds
Started Jul 30 06:32:05 PM PDT 24
Finished Jul 30 06:32:34 PM PDT 24
Peak memory 207128 kb
Host smart-82675e89-b466-4f63-ba1f-be11d1a32cf1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861968519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_resume.2861968519
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2970031038
Short name T1576
Test name
Test status
Simulation time 156146827 ps
CPU time 0.85 seconds
Started Jul 30 06:32:11 PM PDT 24
Finished Jul 30 06:32:12 PM PDT 24
Peak memory 206912 kb
Host smart-19a65852-de17-4843-9898-17c4721f38b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29700
31038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2970031038
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.701113750
Short name T678
Test name
Test status
Simulation time 141464722 ps
CPU time 0.81 seconds
Started Jul 30 06:32:09 PM PDT 24
Finished Jul 30 06:32:10 PM PDT 24
Peak memory 206888 kb
Host smart-0647f199-5bc1-4b66-a6b4-1da09261f68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70111
3750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.701113750
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.638838586
Short name T432
Test name
Test status
Simulation time 243711255 ps
CPU time 1.09 seconds
Started Jul 30 06:32:07 PM PDT 24
Finished Jul 30 06:32:08 PM PDT 24
Peak memory 206932 kb
Host smart-e9de6c0d-a713-40a4-a0dc-8508d2f2101e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63883
8586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.638838586
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2388081268
Short name T2117
Test name
Test status
Simulation time 1063822747 ps
CPU time 2.76 seconds
Started Jul 30 06:32:10 PM PDT 24
Finished Jul 30 06:32:13 PM PDT 24
Peak memory 207080 kb
Host smart-13f0d391-9b87-404f-965e-dd793ead33c0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2388081268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2388081268
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1848281501
Short name T1365
Test name
Test status
Simulation time 9678788079 ps
CPU time 19.64 seconds
Started Jul 30 06:32:11 PM PDT 24
Finished Jul 30 06:32:31 PM PDT 24
Peak memory 207156 kb
Host smart-cd5c656b-b887-470d-86d3-58d7395b3dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18482
81501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1848281501
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.836815000
Short name T1677
Test name
Test status
Simulation time 3834041077 ps
CPU time 24.51 seconds
Started Jul 30 06:32:09 PM PDT 24
Finished Jul 30 06:32:33 PM PDT 24
Peak memory 207196 kb
Host smart-c2c0a339-3971-456c-bc74-99dfbaa5549b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836815000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.836815000
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.4170888680
Short name T1177
Test name
Test status
Simulation time 393756558 ps
CPU time 1.38 seconds
Started Jul 30 06:32:09 PM PDT 24
Finished Jul 30 06:32:11 PM PDT 24
Peak memory 206948 kb
Host smart-d6cff1c5-30f4-40c1-9721-247eb1c1686d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41708
88680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.4170888680
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.143730624
Short name T490
Test name
Test status
Simulation time 209850889 ps
CPU time 0.84 seconds
Started Jul 30 06:32:09 PM PDT 24
Finished Jul 30 06:32:10 PM PDT 24
Peak memory 206888 kb
Host smart-d879670a-786b-4404-bf61-bef97c3c071f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14373
0624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.143730624
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1596406214
Short name T1893
Test name
Test status
Simulation time 44456178 ps
CPU time 0.72 seconds
Started Jul 30 06:32:10 PM PDT 24
Finished Jul 30 06:32:11 PM PDT 24
Peak memory 206888 kb
Host smart-7aaba0cf-cc10-4e1a-81e0-03d03638e15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15964
06214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1596406214
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.2829385583
Short name T1791
Test name
Test status
Simulation time 788624840 ps
CPU time 2.39 seconds
Started Jul 30 06:32:11 PM PDT 24
Finished Jul 30 06:32:13 PM PDT 24
Peak memory 207008 kb
Host smart-9eeb6d01-a871-46d6-a267-86d10239ab4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28293
85583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.2829385583
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2885834359
Short name T1123
Test name
Test status
Simulation time 210287849 ps
CPU time 1.47 seconds
Started Jul 30 06:32:09 PM PDT 24
Finished Jul 30 06:32:11 PM PDT 24
Peak memory 206968 kb
Host smart-0c8f8b8f-126d-4d76-a849-5bfead97c0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858
34359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2885834359
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.284315844
Short name T1159
Test name
Test status
Simulation time 208495651 ps
CPU time 1.1 seconds
Started Jul 30 06:32:12 PM PDT 24
Finished Jul 30 06:32:13 PM PDT 24
Peak memory 207020 kb
Host smart-597ab59c-2b06-4c56-ac06-11ffe5deb56e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=284315844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.284315844
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.269453629
Short name T529
Test name
Test status
Simulation time 188784462 ps
CPU time 0.91 seconds
Started Jul 30 06:32:09 PM PDT 24
Finished Jul 30 06:32:10 PM PDT 24
Peak memory 206884 kb
Host smart-ac738d20-d27d-48b3-925c-d328a6045115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26945
3629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.269453629
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1697673017
Short name T1426
Test name
Test status
Simulation time 243144799 ps
CPU time 1.04 seconds
Started Jul 30 06:32:10 PM PDT 24
Finished Jul 30 06:32:11 PM PDT 24
Peak memory 206908 kb
Host smart-ea1faefe-9754-4b5c-b7ac-15ce8119eae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16976
73017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1697673017
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.2480874669
Short name T2792
Test name
Test status
Simulation time 8840663273 ps
CPU time 83.19 seconds
Started Jul 30 06:32:12 PM PDT 24
Finished Jul 30 06:33:35 PM PDT 24
Peak memory 215360 kb
Host smart-923b6338-848c-49a9-b38a-7bd26c870a60
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2480874669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.2480874669
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.423489041
Short name T1171
Test name
Test status
Simulation time 5526163231 ps
CPU time 66.53 seconds
Started Jul 30 06:32:11 PM PDT 24
Finished Jul 30 06:33:18 PM PDT 24
Peak memory 207156 kb
Host smart-ae27fed1-e824-4f59-9162-4826c856f0eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=423489041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.423489041
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.674827419
Short name T537
Test name
Test status
Simulation time 194665952 ps
CPU time 1.01 seconds
Started Jul 30 06:32:13 PM PDT 24
Finished Jul 30 06:32:14 PM PDT 24
Peak memory 206952 kb
Host smart-28fb90fd-39a1-47fd-a39c-4123a3c486d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67482
7419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.674827419
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1011111215
Short name T1631
Test name
Test status
Simulation time 23300517549 ps
CPU time 28.11 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:33:06 PM PDT 24
Peak memory 207108 kb
Host smart-d82976f8-bb86-4814-9741-5e130e447a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10111
11215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1011111215
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.541416776
Short name T1664
Test name
Test status
Simulation time 3374714630 ps
CPU time 5.3 seconds
Started Jul 30 06:32:14 PM PDT 24
Finished Jul 30 06:32:20 PM PDT 24
Peak memory 207072 kb
Host smart-e9caaae9-12d4-4ccd-b7bc-67bd8e214b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54141
6776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.541416776
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.1169281786
Short name T2779
Test name
Test status
Simulation time 5713763654 ps
CPU time 166.98 seconds
Started Jul 30 06:32:36 PM PDT 24
Finished Jul 30 06:35:24 PM PDT 24
Peak memory 215284 kb
Host smart-6c1005d1-832c-405b-8eb5-9ff093daf82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11692
81786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.1169281786
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.1222032541
Short name T1849
Test name
Test status
Simulation time 5274904772 ps
CPU time 40.09 seconds
Started Jul 30 06:32:14 PM PDT 24
Finished Jul 30 06:32:54 PM PDT 24
Peak memory 207144 kb
Host smart-57f243c4-c760-41cd-8787-e2eeeb1380f9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1222032541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.1222032541
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.3354289713
Short name T730
Test name
Test status
Simulation time 242854968 ps
CPU time 1.01 seconds
Started Jul 30 06:32:22 PM PDT 24
Finished Jul 30 06:32:24 PM PDT 24
Peak memory 206988 kb
Host smart-15d4c9f1-3d8a-4a0f-8ffb-042ee779dcf2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3354289713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.3354289713
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3016746406
Short name T1410
Test name
Test status
Simulation time 195819924 ps
CPU time 0.91 seconds
Started Jul 30 06:32:31 PM PDT 24
Finished Jul 30 06:32:32 PM PDT 24
Peak memory 206928 kb
Host smart-82a58dcb-5bf3-4888-b819-035944e20068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30167
46406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3016746406
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3539649154
Short name T1786
Test name
Test status
Simulation time 4370714540 ps
CPU time 43.92 seconds
Started Jul 30 06:32:22 PM PDT 24
Finished Jul 30 06:33:06 PM PDT 24
Peak memory 215320 kb
Host smart-d897e294-f2ad-4cb1-af3a-62d424ee2aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35396
49154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3539649154
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.2402407685
Short name T2357
Test name
Test status
Simulation time 5091726967 ps
CPU time 40.68 seconds
Started Jul 30 06:32:15 PM PDT 24
Finished Jul 30 06:32:56 PM PDT 24
Peak memory 216528 kb
Host smart-6274d34b-37c0-488a-80c4-2003325b647e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2402407685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.2402407685
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.194586906
Short name T338
Test name
Test status
Simulation time 154464355 ps
CPU time 0.85 seconds
Started Jul 30 06:32:18 PM PDT 24
Finished Jul 30 06:32:19 PM PDT 24
Peak memory 206920 kb
Host smart-1e7bfb76-d848-40e4-9b31-542f634642ed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=194586906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.194586906
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3634253146
Short name T1571
Test name
Test status
Simulation time 148716225 ps
CPU time 0.87 seconds
Started Jul 30 06:32:30 PM PDT 24
Finished Jul 30 06:32:31 PM PDT 24
Peak memory 206912 kb
Host smart-88d10263-0df9-4f59-b5a6-2fceeb958d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36342
53146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3634253146
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3867164393
Short name T1985
Test name
Test status
Simulation time 164994678 ps
CPU time 0.83 seconds
Started Jul 30 06:32:24 PM PDT 24
Finished Jul 30 06:32:25 PM PDT 24
Peak memory 206960 kb
Host smart-fb560cff-840c-4828-ab17-3015f0c6e043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38671
64393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3867164393
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2350983090
Short name T2246
Test name
Test status
Simulation time 165081472 ps
CPU time 0.89 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:32:38 PM PDT 24
Peak memory 206904 kb
Host smart-05144acc-ad9f-496d-ae4c-415ac2e904a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23509
83090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2350983090
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.4240718083
Short name T1642
Test name
Test status
Simulation time 174017843 ps
CPU time 0.88 seconds
Started Jul 30 06:32:15 PM PDT 24
Finished Jul 30 06:32:17 PM PDT 24
Peak memory 206964 kb
Host smart-0a53bf4f-b8ce-4d05-9cd0-725e9658ba67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42407
18083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.4240718083
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1253397326
Short name T808
Test name
Test status
Simulation time 174270629 ps
CPU time 0.96 seconds
Started Jul 30 06:32:19 PM PDT 24
Finished Jul 30 06:32:20 PM PDT 24
Peak memory 206908 kb
Host smart-937825a9-2974-46c0-9939-64dabbe1c981
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1253397326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1253397326
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1637658432
Short name T2290
Test name
Test status
Simulation time 173303568 ps
CPU time 0.86 seconds
Started Jul 30 06:32:14 PM PDT 24
Finished Jul 30 06:32:15 PM PDT 24
Peak memory 206872 kb
Host smart-ee50e418-4b4c-4d09-b438-92a882279fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16376
58432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1637658432
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2564790163
Short name T1180
Test name
Test status
Simulation time 43872514 ps
CPU time 0.7 seconds
Started Jul 30 06:32:30 PM PDT 24
Finished Jul 30 06:32:31 PM PDT 24
Peak memory 206948 kb
Host smart-1b925673-89b2-4d4a-be05-d8f4d779a303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25647
90163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2564790163
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2367112452
Short name T1958
Test name
Test status
Simulation time 11441911681 ps
CPU time 27.2 seconds
Started Jul 30 06:32:24 PM PDT 24
Finished Jul 30 06:32:52 PM PDT 24
Peak memory 215348 kb
Host smart-a3f33cf9-edab-4645-94fd-7d88881b15fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23671
12452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2367112452
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1988204097
Short name T937
Test name
Test status
Simulation time 215633601 ps
CPU time 0.98 seconds
Started Jul 30 06:32:36 PM PDT 24
Finished Jul 30 06:32:37 PM PDT 24
Peak memory 207080 kb
Host smart-b936f8ca-bfa3-4c05-9c84-02843de6fb42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19882
04097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1988204097
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.359806388
Short name T2487
Test name
Test status
Simulation time 183866607 ps
CPU time 0.91 seconds
Started Jul 30 06:32:12 PM PDT 24
Finished Jul 30 06:32:13 PM PDT 24
Peak memory 206924 kb
Host smart-32691798-51f7-4865-bafc-a9392d273863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35980
6388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.359806388
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.681147862
Short name T1300
Test name
Test status
Simulation time 250684204 ps
CPU time 0.98 seconds
Started Jul 30 06:32:15 PM PDT 24
Finished Jul 30 06:32:16 PM PDT 24
Peak memory 206912 kb
Host smart-d40fe7dc-f7f8-47e8-bee2-3b0b577750b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68114
7862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.681147862
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.3231939984
Short name T2788
Test name
Test status
Simulation time 178325321 ps
CPU time 0.9 seconds
Started Jul 30 06:32:14 PM PDT 24
Finished Jul 30 06:32:15 PM PDT 24
Peak memory 206904 kb
Host smart-599f8de5-819f-487f-9f02-4c81d0f246a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32319
39984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3231939984
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.3542654535
Short name T1210
Test name
Test status
Simulation time 171869784 ps
CPU time 0.88 seconds
Started Jul 30 06:32:32 PM PDT 24
Finished Jul 30 06:32:33 PM PDT 24
Peak memory 206904 kb
Host smart-13623125-1072-423c-aa5c-37bcdc5547c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35426
54535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.3542654535
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2998123369
Short name T2163
Test name
Test status
Simulation time 151200755 ps
CPU time 0.87 seconds
Started Jul 30 06:32:15 PM PDT 24
Finished Jul 30 06:32:16 PM PDT 24
Peak memory 206920 kb
Host smart-5a3bff36-fdb6-4a7e-8fd9-3f79b2db21ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29981
23369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2998123369
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2156127008
Short name T1226
Test name
Test status
Simulation time 154485578 ps
CPU time 0.87 seconds
Started Jul 30 06:32:36 PM PDT 24
Finished Jul 30 06:32:37 PM PDT 24
Peak memory 207080 kb
Host smart-88898302-4209-4db0-a2f4-482938b00a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21561
27008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2156127008
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1817483480
Short name T2526
Test name
Test status
Simulation time 227784058 ps
CPU time 1.07 seconds
Started Jul 30 06:32:20 PM PDT 24
Finished Jul 30 06:32:22 PM PDT 24
Peak memory 206912 kb
Host smart-deae8317-3c67-42f0-a4f8-2ccf5db683a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18174
83480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1817483480
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.1874814159
Short name T1943
Test name
Test status
Simulation time 5850517076 ps
CPU time 60.24 seconds
Started Jul 30 06:32:33 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 216544 kb
Host smart-dcab1b3d-39cb-41ee-bf23-3776200b4a8d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1874814159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.1874814159
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1234561540
Short name T1627
Test name
Test status
Simulation time 174144079 ps
CPU time 0.9 seconds
Started Jul 30 06:32:28 PM PDT 24
Finished Jul 30 06:32:29 PM PDT 24
Peak memory 207076 kb
Host smart-50a25738-8535-4a9d-a0ec-e9141e97248c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12345
61540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1234561540
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.3670260648
Short name T996
Test name
Test status
Simulation time 209752787 ps
CPU time 0.91 seconds
Started Jul 30 06:32:33 PM PDT 24
Finished Jul 30 06:32:34 PM PDT 24
Peak memory 206960 kb
Host smart-ab9b9df1-da63-442f-87b7-811e0620f3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36702
60648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.3670260648
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.2249776146
Short name T1061
Test name
Test status
Simulation time 324732785 ps
CPU time 1.14 seconds
Started Jul 30 06:32:18 PM PDT 24
Finished Jul 30 06:32:19 PM PDT 24
Peak memory 206916 kb
Host smart-7f1ae02b-06f6-4e56-8315-f281440ff5fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22497
76146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.2249776146
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.749988864
Short name T1643
Test name
Test status
Simulation time 3576138406 ps
CPU time 97.73 seconds
Started Jul 30 06:32:36 PM PDT 24
Finished Jul 30 06:34:14 PM PDT 24
Peak memory 215316 kb
Host smart-75ad4a75-7200-4235-b67d-c5bfa9d5603d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74998
8864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.749988864
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.305790716
Short name T2728
Test name
Test status
Simulation time 836929152 ps
CPU time 5.36 seconds
Started Jul 30 06:32:14 PM PDT 24
Finished Jul 30 06:32:19 PM PDT 24
Peak memory 207048 kb
Host smart-f364e2c5-2b04-4c6a-8511-03c9049751b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305790716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_host
_handshake.305790716
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.3066870280
Short name T179
Test name
Test status
Simulation time 34615013 ps
CPU time 0.66 seconds
Started Jul 30 06:28:15 PM PDT 24
Finished Jul 30 06:28:16 PM PDT 24
Peak memory 207016 kb
Host smart-9da3b3c3-5855-411c-8027-341bd63bd7fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3066870280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.3066870280
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3005156234
Short name T1246
Test name
Test status
Simulation time 3761194833 ps
CPU time 5.7 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:24 PM PDT 24
Peak memory 207076 kb
Host smart-60a3782a-6258-422d-bac0-dd976cc53409
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005156234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.3005156234
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.3688205052
Short name T744
Test name
Test status
Simulation time 13382251018 ps
CPU time 18.58 seconds
Started Jul 30 06:28:12 PM PDT 24
Finished Jul 30 06:28:31 PM PDT 24
Peak memory 207184 kb
Host smart-9d6729d5-8122-4ba0-b55a-b04b2ac0f285
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688205052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.3688205052
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3622951083
Short name T1805
Test name
Test status
Simulation time 23308523313 ps
CPU time 28.96 seconds
Started Jul 30 06:28:15 PM PDT 24
Finished Jul 30 06:28:44 PM PDT 24
Peak memory 207140 kb
Host smart-6200a097-ed5c-4276-90c9-a77197623f54
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622951083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.3622951083
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1302539626
Short name T1954
Test name
Test status
Simulation time 222054064 ps
CPU time 0.94 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:28:14 PM PDT 24
Peak memory 206956 kb
Host smart-58dcf2de-ef7d-4adc-aeb2-040670b7367c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13025
39626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1302539626
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.3692299841
Short name T48
Test name
Test status
Simulation time 153447958 ps
CPU time 0.97 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:28:14 PM PDT 24
Peak memory 206920 kb
Host smart-1de3f5e5-cda4-431b-83d5-7b972a9f2b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36922
99841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.3692299841
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.2272008360
Short name T2811
Test name
Test status
Simulation time 136743904 ps
CPU time 0.87 seconds
Started Jul 30 06:28:10 PM PDT 24
Finished Jul 30 06:28:11 PM PDT 24
Peak memory 206928 kb
Host smart-92d45dbe-e198-474f-9c2c-7b8d8cc70b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22720
08360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2272008360
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.4286801958
Short name T2183
Test name
Test status
Simulation time 158485334 ps
CPU time 0.82 seconds
Started Jul 30 06:28:09 PM PDT 24
Finished Jul 30 06:28:10 PM PDT 24
Peak memory 206940 kb
Host smart-1ca25d81-1db6-4493-a91d-ff5f19f11ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42868
01958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.4286801958
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.4251532883
Short name T994
Test name
Test status
Simulation time 211696614 ps
CPU time 0.99 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:20 PM PDT 24
Peak memory 206928 kb
Host smart-09782fdb-d4a4-4538-83c6-faa9dfa7ed78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42515
32883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.4251532883
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1517779412
Short name T2502
Test name
Test status
Simulation time 711949475 ps
CPU time 1.99 seconds
Started Jul 30 06:28:19 PM PDT 24
Finished Jul 30 06:28:21 PM PDT 24
Peak memory 207016 kb
Host smart-145f3ef1-001e-4c8f-9d08-979abd54070a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1517779412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1517779412
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.1489074262
Short name T1678
Test name
Test status
Simulation time 8519699011 ps
CPU time 19.88 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:28:33 PM PDT 24
Peak memory 207148 kb
Host smart-2ae4d0a0-9107-48a2-86c5-5f4a485d192e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14890
74262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1489074262
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.3469458517
Short name T1105
Test name
Test status
Simulation time 1978086150 ps
CPU time 16.04 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:35 PM PDT 24
Peak memory 206936 kb
Host smart-37058f6b-ac9d-4691-a6ed-ea02a8f49e59
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469458517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.3469458517
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.2064875459
Short name T2505
Test name
Test status
Simulation time 356829381 ps
CPU time 1.23 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:17 PM PDT 24
Peak memory 206888 kb
Host smart-573e8f62-1833-47d7-a196-7c599d6dde08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20648
75459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.2064875459
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1170287928
Short name T1649
Test name
Test status
Simulation time 198419850 ps
CPU time 0.87 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 206816 kb
Host smart-85ecfa2d-964e-4553-b0fb-4ea18ae87d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11702
87928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1170287928
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.105292304
Short name T458
Test name
Test status
Simulation time 46028371 ps
CPU time 0.7 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:20 PM PDT 24
Peak memory 206908 kb
Host smart-8308b785-eac7-44ed-b018-9021b22a2d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10529
2304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.105292304
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.742789630
Short name T1103
Test name
Test status
Simulation time 921825023 ps
CPU time 2.65 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 207048 kb
Host smart-bcb7bb39-bb24-4571-a714-2c3956e57126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74278
9630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.742789630
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3793605160
Short name T2706
Test name
Test status
Simulation time 319620526 ps
CPU time 2.57 seconds
Started Jul 30 06:28:12 PM PDT 24
Finished Jul 30 06:28:15 PM PDT 24
Peak memory 207004 kb
Host smart-e768c299-9492-46ac-9c27-d1a691a6b484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37936
05160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3793605160
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.2357827042
Short name T932
Test name
Test status
Simulation time 120202815457 ps
CPU time 197.31 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:31:30 PM PDT 24
Peak memory 207224 kb
Host smart-fbec030e-1b7e-47b4-aaaa-5669dc4fcd5a
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2357827042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.2357827042
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.4081935247
Short name T2036
Test name
Test status
Simulation time 109173392470 ps
CPU time 183.41 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:31:32 PM PDT 24
Peak memory 207092 kb
Host smart-0eb1a2c1-63c6-41ad-aa6e-3c69f67a41f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081935247 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.4081935247
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.213485917
Short name T1656
Test name
Test status
Simulation time 83063079481 ps
CPU time 135.7 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:30:32 PM PDT 24
Peak memory 207092 kb
Host smart-af4044a2-4daa-4bc1-9d59-197c48a560c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213485917 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.213485917
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.2998517018
Short name T317
Test name
Test status
Simulation time 109213658673 ps
CPU time 161.51 seconds
Started Jul 30 06:28:19 PM PDT 24
Finished Jul 30 06:31:01 PM PDT 24
Peak memory 207120 kb
Host smart-86a99670-5b6c-4782-97df-431b26553721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29985
17018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.2998517018
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1451705957
Short name T1346
Test name
Test status
Simulation time 205692333 ps
CPU time 1.07 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:28:12 PM PDT 24
Peak memory 215192 kb
Host smart-5bcd607e-8d21-4054-b721-b2d05f970644
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1451705957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1451705957
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1369247974
Short name T1121
Test name
Test status
Simulation time 147882278 ps
CPU time 0.79 seconds
Started Jul 30 06:28:19 PM PDT 24
Finished Jul 30 06:28:20 PM PDT 24
Peak memory 206912 kb
Host smart-794fa5fb-6dd5-43d0-98b3-55f2c0d68b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13692
47974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1369247974
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3862165902
Short name T1752
Test name
Test status
Simulation time 248740673 ps
CPU time 0.99 seconds
Started Jul 30 06:28:19 PM PDT 24
Finished Jul 30 06:28:20 PM PDT 24
Peak memory 206948 kb
Host smart-fa4c27dc-bbd2-4479-8041-59aafff277b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38621
65902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3862165902
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.3555094061
Short name T542
Test name
Test status
Simulation time 7815664096 ps
CPU time 77.6 seconds
Started Jul 30 06:28:11 PM PDT 24
Finished Jul 30 06:29:28 PM PDT 24
Peak memory 216552 kb
Host smart-6ca3ff82-9399-418b-a83a-207e66fdaf63
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3555094061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3555094061
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.2229336892
Short name T1499
Test name
Test status
Simulation time 8949490226 ps
CPU time 63.87 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:29:17 PM PDT 24
Peak memory 207100 kb
Host smart-e07c006f-803a-4601-af3c-cdacf720e45f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2229336892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.2229336892
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1021546137
Short name T462
Test name
Test status
Simulation time 249706968 ps
CPU time 0.94 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:20 PM PDT 24
Peak memory 206956 kb
Host smart-face763c-167e-42b3-a3d0-543a40e6b64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10215
46137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1021546137
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.1410058750
Short name T939
Test name
Test status
Simulation time 23370515480 ps
CPU time 28.1 seconds
Started Jul 30 06:28:19 PM PDT 24
Finished Jul 30 06:28:48 PM PDT 24
Peak memory 207136 kb
Host smart-e297400f-fb94-49b5-9467-50ef20fe920b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14100
58750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1410058750
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.3512797050
Short name T953
Test name
Test status
Simulation time 3352294476 ps
CPU time 5.25 seconds
Started Jul 30 06:28:10 PM PDT 24
Finished Jul 30 06:28:15 PM PDT 24
Peak memory 207060 kb
Host smart-19ef1284-56db-443c-ae02-0d0ee8bed2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35127
97050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.3512797050
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1138399536
Short name T221
Test name
Test status
Simulation time 4423242644 ps
CPU time 119.52 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:30:16 PM PDT 24
Peak memory 215332 kb
Host smart-789c363d-97f1-4f90-9ad7-b528ef2aed3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11383
99536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1138399536
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.2052194219
Short name T353
Test name
Test status
Simulation time 6396706700 ps
CPU time 63.29 seconds
Started Jul 30 06:28:09 PM PDT 24
Finished Jul 30 06:29:13 PM PDT 24
Peak memory 207168 kb
Host smart-c4847a2e-4744-45ce-a3d2-ca1d54272a39
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2052194219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.2052194219
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.2952723009
Short name T2516
Test name
Test status
Simulation time 231422841 ps
CPU time 0.93 seconds
Started Jul 30 06:28:10 PM PDT 24
Finished Jul 30 06:28:12 PM PDT 24
Peak memory 206936 kb
Host smart-21948022-dbe4-4409-ac34-a1d62ba4d764
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2952723009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.2952723009
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.4098926331
Short name T805
Test name
Test status
Simulation time 218815663 ps
CPU time 0.94 seconds
Started Jul 30 06:28:09 PM PDT 24
Finished Jul 30 06:28:11 PM PDT 24
Peak memory 206932 kb
Host smart-30bfb9b5-befd-4abc-95e1-19c2d010c6cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40989
26331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.4098926331
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3531541649
Short name T329
Test name
Test status
Simulation time 5324009572 ps
CPU time 41.19 seconds
Started Jul 30 06:28:19 PM PDT 24
Finished Jul 30 06:29:00 PM PDT 24
Peak memory 215332 kb
Host smart-675ae045-381c-4583-bd08-17480eaba5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35315
41649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3531541649
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.2334811458
Short name T403
Test name
Test status
Simulation time 3680459071 ps
CPU time 104.93 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:29:58 PM PDT 24
Peak memory 215352 kb
Host smart-6e57f569-c0e2-4346-9655-dad342b17cad
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2334811458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.2334811458
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.1588556008
Short name T1235
Test name
Test status
Simulation time 155103714 ps
CPU time 0.9 seconds
Started Jul 30 06:28:15 PM PDT 24
Finished Jul 30 06:28:16 PM PDT 24
Peak memory 206916 kb
Host smart-45657244-7e27-4249-8a46-0d89204e3048
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1588556008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.1588556008
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2245177712
Short name T1716
Test name
Test status
Simulation time 174603285 ps
CPU time 0.9 seconds
Started Jul 30 06:28:15 PM PDT 24
Finished Jul 30 06:28:16 PM PDT 24
Peak memory 206924 kb
Host smart-0ede5df4-e80e-416f-a341-bb894b4cc8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22451
77712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2245177712
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.874073830
Short name T119
Test name
Test status
Simulation time 182508944 ps
CPU time 0.88 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 206956 kb
Host smart-2e08b621-e73f-46bd-bfaa-75fd199c9879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87407
3830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.874073830
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.990739260
Short name T1825
Test name
Test status
Simulation time 164535881 ps
CPU time 0.85 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:17 PM PDT 24
Peak memory 206904 kb
Host smart-b09953fa-bf45-4857-9d20-6b09257c73af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99073
9260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.990739260
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.1227170458
Short name T2509
Test name
Test status
Simulation time 185077642 ps
CPU time 0.93 seconds
Started Jul 30 06:28:14 PM PDT 24
Finished Jul 30 06:28:15 PM PDT 24
Peak memory 206908 kb
Host smart-1eec91ed-eedd-4239-a358-94a5f697cacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12271
70458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.1227170458
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3227245718
Short name T2268
Test name
Test status
Simulation time 194903363 ps
CPU time 0.9 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 206984 kb
Host smart-b378492a-3c32-4d3d-a5bb-4c50d2248e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32272
45718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3227245718
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3407922106
Short name T2433
Test name
Test status
Simulation time 196692729 ps
CPU time 0.9 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 206916 kb
Host smart-00fa181c-957c-45a3-beb6-14a061c96857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34079
22106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3407922106
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.3501047841
Short name T1117
Test name
Test status
Simulation time 223809597 ps
CPU time 1.03 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:28:14 PM PDT 24
Peak memory 206920 kb
Host smart-44563ef2-bfa5-435f-bc5b-1542b532fabc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3501047841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.3501047841
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.395274865
Short name T1706
Test name
Test status
Simulation time 236086138 ps
CPU time 1.01 seconds
Started Jul 30 06:28:19 PM PDT 24
Finished Jul 30 06:28:20 PM PDT 24
Peak memory 206920 kb
Host smart-850078e8-51a3-491b-8a5c-405cdf3438b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39527
4865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.395274865
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2075712251
Short name T601
Test name
Test status
Simulation time 139592894 ps
CPU time 0.81 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 206888 kb
Host smart-9093842a-266b-4dd7-ac4a-00c3d7a681cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20757
12251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2075712251
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3503936376
Short name T2380
Test name
Test status
Simulation time 36415983 ps
CPU time 0.64 seconds
Started Jul 30 06:28:12 PM PDT 24
Finished Jul 30 06:28:13 PM PDT 24
Peak memory 206880 kb
Host smart-51b21ab7-ca87-4dfd-a806-6ca09593566c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35039
36376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3503936376
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.3810122844
Short name T2567
Test name
Test status
Simulation time 202878885 ps
CPU time 0.91 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:17 PM PDT 24
Peak memory 206984 kb
Host smart-9f2cf81a-e053-47a8-a178-75aabc6d8e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38101
22844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3810122844
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3220826634
Short name T2522
Test name
Test status
Simulation time 270953062 ps
CPU time 1 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 206948 kb
Host smart-9b636550-73ee-4824-961e-3e2efb46732a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32208
26634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3220826634
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3822494212
Short name T165
Test name
Test status
Simulation time 7530043807 ps
CPU time 191.73 seconds
Started Jul 30 06:28:19 PM PDT 24
Finished Jul 30 06:31:33 PM PDT 24
Peak memory 215320 kb
Host smart-8e4a62d4-8618-4113-9ae4-2c35af6b676d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822494212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3822494212
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.1555926983
Short name T153
Test name
Test status
Simulation time 7813439964 ps
CPU time 127.39 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:30:24 PM PDT 24
Peak memory 215324 kb
Host smart-9ff11386-ec66-4606-a0dd-1d9c0d72e017
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1555926983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.1555926983
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.609523346
Short name T1353
Test name
Test status
Simulation time 12900717340 ps
CPU time 97.22 seconds
Started Jul 30 06:28:14 PM PDT 24
Finished Jul 30 06:29:52 PM PDT 24
Peak memory 217224 kb
Host smart-a3dc17d7-9c60-44b8-a1ec-543f94b7bf87
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=609523346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.609523346
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.45878441
Short name T1708
Test name
Test status
Simulation time 211378617 ps
CPU time 0.94 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 206948 kb
Host smart-0fb54855-2801-4c8d-9921-d7343864d8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45878
441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.45878441
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.2113931434
Short name T94
Test name
Test status
Simulation time 226565822 ps
CPU time 1 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 206956 kb
Host smart-d631adc6-818c-4969-b83f-d4338f0c5047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21139
31434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.2113931434
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2549422057
Short name T1270
Test name
Test status
Simulation time 149696592 ps
CPU time 0.8 seconds
Started Jul 30 06:28:21 PM PDT 24
Finished Jul 30 06:28:22 PM PDT 24
Peak memory 206948 kb
Host smart-e473f3dc-3089-40aa-85b6-199ec10a2052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25494
22057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2549422057
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.2289788610
Short name T68
Test name
Test status
Simulation time 171545111 ps
CPU time 0.92 seconds
Started Jul 30 06:28:14 PM PDT 24
Finished Jul 30 06:28:15 PM PDT 24
Peak memory 206928 kb
Host smart-2e592c8f-2b8a-478b-a476-23405aa553c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22897
88610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.2289788610
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1331472671
Short name T204
Test name
Test status
Simulation time 491829065 ps
CPU time 1.32 seconds
Started Jul 30 06:28:14 PM PDT 24
Finished Jul 30 06:28:15 PM PDT 24
Peak memory 222948 kb
Host smart-31719983-ca94-487a-b727-01783010c6dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1331472671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1331472671
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1075998169
Short name T1601
Test name
Test status
Simulation time 384768509 ps
CPU time 1.43 seconds
Started Jul 30 06:28:13 PM PDT 24
Finished Jul 30 06:28:15 PM PDT 24
Peak memory 206912 kb
Host smart-4b25ad22-f700-46b6-8771-18dc3988fb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10759
98169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1075998169
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.1423493848
Short name T89
Test name
Test status
Simulation time 188328396 ps
CPU time 0.96 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 206952 kb
Host smart-1e2310b0-c2f2-4c91-a41e-a97f2a5ecf5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14234
93848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.1423493848
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1087889405
Short name T810
Test name
Test status
Simulation time 169374778 ps
CPU time 0.88 seconds
Started Jul 30 06:28:20 PM PDT 24
Finished Jul 30 06:28:21 PM PDT 24
Peak memory 206872 kb
Host smart-c91d1dd2-55ec-42f8-8a58-c0500da94869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10878
89405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1087889405
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.295094786
Short name T588
Test name
Test status
Simulation time 160060559 ps
CPU time 0.93 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:23 PM PDT 24
Peak memory 206876 kb
Host smart-92fca3f6-8373-48f8-9272-ccf3a036499e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29509
4786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.295094786
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3006756452
Short name T607
Test name
Test status
Simulation time 308068838 ps
CPU time 1.11 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 206916 kb
Host smart-ef1d57cf-e217-4f43-bdfd-ca32a535f597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30067
56452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3006756452
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3107818643
Short name T736
Test name
Test status
Simulation time 4075969082 ps
CPU time 30.59 seconds
Started Jul 30 06:28:20 PM PDT 24
Finished Jul 30 06:28:51 PM PDT 24
Peak memory 215292 kb
Host smart-70a0e280-2252-4e57-990e-c46278f042f2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3107818643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3107818643
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2923695969
Short name T447
Test name
Test status
Simulation time 217792413 ps
CPU time 0.94 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 206980 kb
Host smart-055f2cf3-c33d-477e-a1b5-320dcf72e8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29236
95969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2923695969
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2678231639
Short name T2689
Test name
Test status
Simulation time 154920304 ps
CPU time 0.87 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 206956 kb
Host smart-7b1a076f-36ae-40bf-a9ec-5e0ac3283667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26782
31639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2678231639
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.1395992113
Short name T1751
Test name
Test status
Simulation time 254125661 ps
CPU time 1.03 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 206932 kb
Host smart-25de82d7-6ba7-458a-b969-4c3f255bb676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13959
92113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.1395992113
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.1171543874
Short name T1876
Test name
Test status
Simulation time 4586045403 ps
CPU time 131.09 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:30:28 PM PDT 24
Peak memory 215284 kb
Host smart-4a4bb89e-2af7-4cac-82b4-2e89a7548fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11715
43874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.1171543874
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.239004504
Short name T67
Test name
Test status
Simulation time 17070759182 ps
CPU time 400.2 seconds
Started Jul 30 06:28:21 PM PDT 24
Finished Jul 30 06:35:01 PM PDT 24
Peak memory 215276 kb
Host smart-a3f2b9b2-90d8-4af7-8143-8f42ed5b18e2
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239004504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.239004504
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.2146289831
Short name T1723
Test name
Test status
Simulation time 6672912281 ps
CPU time 49.02 seconds
Started Jul 30 06:28:14 PM PDT 24
Finished Jul 30 06:29:03 PM PDT 24
Peak memory 207132 kb
Host smart-bbc22662-e15f-44c2-84a0-89b7e892bccb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146289831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.2146289831
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.320131749
Short name T1587
Test name
Test status
Simulation time 38436945 ps
CPU time 0.65 seconds
Started Jul 30 06:32:34 PM PDT 24
Finished Jul 30 06:32:35 PM PDT 24
Peak memory 207012 kb
Host smart-6c9f3cfa-0cdb-4fed-8662-70063a3f9cdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=320131749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.320131749
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.781661008
Short name T1948
Test name
Test status
Simulation time 4029963707 ps
CPU time 6.05 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 207088 kb
Host smart-a8d39934-c23f-40c2-a722-b645821c7014
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781661008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_ao
n_wake_disconnect.781661008
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2583199763
Short name T2441
Test name
Test status
Simulation time 13311626565 ps
CPU time 15.44 seconds
Started Jul 30 06:32:36 PM PDT 24
Finished Jul 30 06:32:51 PM PDT 24
Peak memory 207124 kb
Host smart-245f81c1-5d34-4de3-a742-e51c1f3e12ce
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583199763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2583199763
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.900778617
Short name T1104
Test name
Test status
Simulation time 23499220230 ps
CPU time 28.68 seconds
Started Jul 30 06:32:30 PM PDT 24
Finished Jul 30 06:32:58 PM PDT 24
Peak memory 207148 kb
Host smart-ea1151df-4b46-4e77-8053-6361250b648a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900778617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_ao
n_wake_resume.900778617
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2749912771
Short name T1869
Test name
Test status
Simulation time 180965446 ps
CPU time 0.89 seconds
Started Jul 30 06:32:31 PM PDT 24
Finished Jul 30 06:32:32 PM PDT 24
Peak memory 206916 kb
Host smart-6b48c4e9-dfce-410e-9630-584d2d49d231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27499
12771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2749912771
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.2452015060
Short name T2710
Test name
Test status
Simulation time 198153849 ps
CPU time 0.93 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:32:43 PM PDT 24
Peak memory 206876 kb
Host smart-a31f9949-b161-4ed5-8870-5b6190401fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24520
15060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.2452015060
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1710175880
Short name T2350
Test name
Test status
Simulation time 672151375 ps
CPU time 2.05 seconds
Started Jul 30 06:32:38 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 207012 kb
Host smart-23349323-263f-498e-87c6-2065bf9c11b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17101
75880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1710175880
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3538412376
Short name T2333
Test name
Test status
Simulation time 474529460 ps
CPU time 1.42 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 206944 kb
Host smart-773f156f-63b9-47d6-b0be-2fc66acfa06d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3538412376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3538412376
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.1628972909
Short name T2592
Test name
Test status
Simulation time 6367280220 ps
CPU time 13.37 seconds
Started Jul 30 06:32:31 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 207124 kb
Host smart-e90b580b-c1ed-49f6-8217-f7c4e3eec23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16289
72909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.1628972909
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.2081097703
Short name T2660
Test name
Test status
Simulation time 864543099 ps
CPU time 5.45 seconds
Started Jul 30 06:32:25 PM PDT 24
Finished Jul 30 06:32:31 PM PDT 24
Peak memory 206948 kb
Host smart-049d6187-fe9a-4167-b9b8-b5dac257dd8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081097703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.2081097703
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1680529595
Short name T107
Test name
Test status
Simulation time 417770132 ps
CPU time 1.51 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:32:39 PM PDT 24
Peak memory 206908 kb
Host smart-6dc3c2f7-79df-4062-a2a8-4e4b02e4dabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16805
29595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1680529595
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.117779118
Short name T398
Test name
Test status
Simulation time 155060849 ps
CPU time 0.81 seconds
Started Jul 30 06:32:38 PM PDT 24
Finished Jul 30 06:32:39 PM PDT 24
Peak memory 206892 kb
Host smart-5b08d1b9-5c98-4938-93b5-2347007dba74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11777
9118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.117779118
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.940924752
Short name T2059
Test name
Test status
Simulation time 46544147 ps
CPU time 0.69 seconds
Started Jul 30 06:32:28 PM PDT 24
Finished Jul 30 06:32:29 PM PDT 24
Peak memory 206896 kb
Host smart-dafa194a-dbeb-440b-aaff-893c8c9ab809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94092
4752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.940924752
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3575430133
Short name T2630
Test name
Test status
Simulation time 823984511 ps
CPU time 2.17 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:32:38 PM PDT 24
Peak memory 207016 kb
Host smart-1e79c197-32be-46c5-a6de-332e7bbe3c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35754
30133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3575430133
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.430239747
Short name T489
Test name
Test status
Simulation time 403584009 ps
CPU time 2.92 seconds
Started Jul 30 06:32:27 PM PDT 24
Finished Jul 30 06:32:30 PM PDT 24
Peak memory 206956 kb
Host smart-e0ea1c3e-a2de-4921-8a2c-5d7229d197e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43023
9747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.430239747
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1477003534
Short name T1394
Test name
Test status
Simulation time 189984120 ps
CPU time 1.04 seconds
Started Jul 30 06:32:26 PM PDT 24
Finished Jul 30 06:32:27 PM PDT 24
Peak memory 207004 kb
Host smart-868cd80c-5bbb-4344-b805-51f2a03ede5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1477003534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1477003534
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1163012017
Short name T2570
Test name
Test status
Simulation time 164593964 ps
CPU time 0.86 seconds
Started Jul 30 06:32:30 PM PDT 24
Finished Jul 30 06:32:31 PM PDT 24
Peak memory 206884 kb
Host smart-6e2429e0-351f-4bde-aa04-c977cf565ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11630
12017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1163012017
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1926394436
Short name T1149
Test name
Test status
Simulation time 226835192 ps
CPU time 1.01 seconds
Started Jul 30 06:32:40 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 206988 kb
Host smart-305661b3-e9a0-4c48-ad28-3013c7b1c879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19263
94436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1926394436
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.3154134989
Short name T2537
Test name
Test status
Simulation time 6893344414 ps
CPU time 71.51 seconds
Started Jul 30 06:32:33 PM PDT 24
Finished Jul 30 06:33:45 PM PDT 24
Peak memory 216668 kb
Host smart-21f15b47-f218-4844-9c91-9775c536f9ff
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3154134989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.3154134989
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.571682692
Short name T1827
Test name
Test status
Simulation time 5251517334 ps
CPU time 63.64 seconds
Started Jul 30 06:32:27 PM PDT 24
Finished Jul 30 06:33:31 PM PDT 24
Peak memory 207100 kb
Host smart-2c57ccd3-6e5c-49a6-afc0-6e13e277ec94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=571682692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.571682692
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.78217836
Short name T2826
Test name
Test status
Simulation time 179154924 ps
CPU time 0.9 seconds
Started Jul 30 06:32:40 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 206988 kb
Host smart-ed6b36d8-a204-48b4-ac1a-5458bafa81e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78217
836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.78217836
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.1939185551
Short name T1323
Test name
Test status
Simulation time 23309801057 ps
CPU time 29.14 seconds
Started Jul 30 06:32:30 PM PDT 24
Finished Jul 30 06:32:59 PM PDT 24
Peak memory 207112 kb
Host smart-9df32fb9-3152-4d5c-a2ca-d974992fec53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19391
85551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.1939185551
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.4161348725
Short name T1463
Test name
Test status
Simulation time 3362002677 ps
CPU time 5.34 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 207084 kb
Host smart-7f7f268f-0263-46d6-88e3-bce8b388604e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41613
48725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.4161348725
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.2505214170
Short name T1867
Test name
Test status
Simulation time 6792304708 ps
CPU time 65.03 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 215292 kb
Host smart-a9c77d19-647c-4983-9a7c-05bfbdcb3ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25052
14170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.2505214170
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.3968257680
Short name T2456
Test name
Test status
Simulation time 5643494108 ps
CPU time 157.62 seconds
Started Jul 30 06:32:36 PM PDT 24
Finished Jul 30 06:35:14 PM PDT 24
Peak memory 215452 kb
Host smart-734a2168-e940-426a-b7b0-b8673536244d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3968257680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.3968257680
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2348880628
Short name T1647
Test name
Test status
Simulation time 250230933 ps
CPU time 1.06 seconds
Started Jul 30 06:32:28 PM PDT 24
Finished Jul 30 06:32:29 PM PDT 24
Peak memory 206924 kb
Host smart-fa31263b-8828-4503-81eb-d96409f7d1f0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2348880628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2348880628
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3324760362
Short name T2080
Test name
Test status
Simulation time 200245326 ps
CPU time 0.97 seconds
Started Jul 30 06:32:33 PM PDT 24
Finished Jul 30 06:32:34 PM PDT 24
Peak memory 206908 kb
Host smart-9b0dcb4a-bd2f-4d26-9d24-7be3fd669eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33247
60362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3324760362
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.3231966854
Short name T1173
Test name
Test status
Simulation time 3915295145 ps
CPU time 109.22 seconds
Started Jul 30 06:32:34 PM PDT 24
Finished Jul 30 06:34:23 PM PDT 24
Peak memory 215384 kb
Host smart-656f68c7-e65a-40e8-9daf-ec9fa29035a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32319
66854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.3231966854
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1602075317
Short name T2640
Test name
Test status
Simulation time 5873107591 ps
CPU time 47.14 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:33:28 PM PDT 24
Peak memory 216804 kb
Host smart-42042dd0-4e92-4fb8-96cb-61ec5c0c0c46
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1602075317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1602075317
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.1892273375
Short name T2465
Test name
Test status
Simulation time 150768604 ps
CPU time 0.82 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:32:36 PM PDT 24
Peak memory 206928 kb
Host smart-7d5f268a-03e1-4a51-b148-495c4d7365f6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1892273375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1892273375
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.181673271
Short name T2535
Test name
Test status
Simulation time 160624780 ps
CPU time 0.91 seconds
Started Jul 30 06:32:34 PM PDT 24
Finished Jul 30 06:32:35 PM PDT 24
Peak memory 206900 kb
Host smart-f5b339dd-7737-49d2-b7bb-42060a4b105c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18167
3271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.181673271
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1747990091
Short name T136
Test name
Test status
Simulation time 195916948 ps
CPU time 0.93 seconds
Started Jul 30 06:32:36 PM PDT 24
Finished Jul 30 06:32:37 PM PDT 24
Peak memory 206916 kb
Host smart-a1bf5952-e2c1-459d-91f2-0592e9a5d482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17479
90091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1747990091
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.684634740
Short name T2388
Test name
Test status
Simulation time 174494914 ps
CPU time 0.92 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:32:36 PM PDT 24
Peak memory 206948 kb
Host smart-baa749f4-fe57-4b70-9611-f599b768bfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68463
4740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.684634740
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3507265272
Short name T2270
Test name
Test status
Simulation time 179454417 ps
CPU time 0.89 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 206912 kb
Host smart-59a4c2de-a414-40cf-b3dc-766de9b37a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35072
65272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3507265272
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1242877799
Short name T1975
Test name
Test status
Simulation time 154113536 ps
CPU time 0.84 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:32:36 PM PDT 24
Peak memory 206948 kb
Host smart-3566f61c-b1a5-4272-9578-ef85531f556a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12428
77799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1242877799
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3921176870
Short name T548
Test name
Test status
Simulation time 154717759 ps
CPU time 0.84 seconds
Started Jul 30 06:32:40 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 206960 kb
Host smart-1f0dc2c2-c37d-480b-a444-140e8d0bc629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39211
76870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3921176870
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.2166833099
Short name T337
Test name
Test status
Simulation time 234276213 ps
CPU time 1.13 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 206928 kb
Host smart-f84257df-28ca-4b4e-b29e-54c3a92a046b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2166833099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.2166833099
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3045883385
Short name T1682
Test name
Test status
Simulation time 158166782 ps
CPU time 0.87 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 206892 kb
Host smart-9db9ded6-aff1-4d3e-b952-4c9667abed1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30458
83385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3045883385
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1279059350
Short name T2550
Test name
Test status
Simulation time 76571054 ps
CPU time 0.73 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:32:42 PM PDT 24
Peak memory 206940 kb
Host smart-8407161f-efc4-4b59-83de-74df6f0ced4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12790
59350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1279059350
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.11640727
Short name T2485
Test name
Test status
Simulation time 16685152810 ps
CPU time 44.68 seconds
Started Jul 30 06:32:34 PM PDT 24
Finished Jul 30 06:33:19 PM PDT 24
Peak memory 219040 kb
Host smart-42138b8b-4432-40c7-b56d-3cce44292221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11640
727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.11640727
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1603561621
Short name T2155
Test name
Test status
Simulation time 226454292 ps
CPU time 0.94 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:32:36 PM PDT 24
Peak memory 206908 kb
Host smart-f5a63897-a755-4b77-8803-ee071f0ab8e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16035
61621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1603561621
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.643729445
Short name T383
Test name
Test status
Simulation time 170313234 ps
CPU time 0.87 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 206860 kb
Host smart-3c2e1832-f9e8-4124-ae97-6ace5b83f5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64372
9445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.643729445
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.2119175578
Short name T2835
Test name
Test status
Simulation time 162544945 ps
CPU time 0.84 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 206924 kb
Host smart-3c960ae2-75dd-487b-a5f4-ca76eefba59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
75578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.2119175578
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.2558968953
Short name T1569
Test name
Test status
Simulation time 173931014 ps
CPU time 0.95 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:32:38 PM PDT 24
Peak memory 206920 kb
Host smart-fa6a456b-2b94-4bc4-b2e7-7a871c1047c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25589
68953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.2558968953
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3448328295
Short name T838
Test name
Test status
Simulation time 133625981 ps
CPU time 0.8 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:32:42 PM PDT 24
Peak memory 206908 kb
Host smart-5d5f2cfa-a48a-4133-92f3-9fd7394400c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34483
28295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3448328295
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.731264671
Short name T368
Test name
Test status
Simulation time 155227342 ps
CPU time 0.85 seconds
Started Jul 30 06:32:32 PM PDT 24
Finished Jul 30 06:32:33 PM PDT 24
Peak memory 206896 kb
Host smart-1672279a-7956-47cb-a297-05eb768719d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73126
4671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.731264671
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.4183705203
Short name T2276
Test name
Test status
Simulation time 176178236 ps
CPU time 0.89 seconds
Started Jul 30 06:32:32 PM PDT 24
Finished Jul 30 06:32:33 PM PDT 24
Peak memory 206928 kb
Host smart-3ddea561-f8d9-4bde-9b51-14e330fbf390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41837
05203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.4183705203
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3620037996
Short name T2175
Test name
Test status
Simulation time 209890531 ps
CPU time 1 seconds
Started Jul 30 06:32:29 PM PDT 24
Finished Jul 30 06:32:30 PM PDT 24
Peak memory 206920 kb
Host smart-fe4d9905-ec56-46bc-bb97-c2cbe45b88a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36200
37996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3620037996
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.1927843138
Short name T2828
Test name
Test status
Simulation time 3157022830 ps
CPU time 24.94 seconds
Started Jul 30 06:32:36 PM PDT 24
Finished Jul 30 06:33:01 PM PDT 24
Peak memory 215280 kb
Host smart-7b93fedf-2c9e-4fa2-8121-e8eae8e57e3d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1927843138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.1927843138
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3978761987
Short name T1037
Test name
Test status
Simulation time 177918708 ps
CPU time 0.87 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 206908 kb
Host smart-a900a4f0-eeeb-433c-a73a-4530b39db0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39787
61987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3978761987
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1171324163
Short name T630
Test name
Test status
Simulation time 199881011 ps
CPU time 0.89 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:32:42 PM PDT 24
Peak memory 206928 kb
Host smart-1fb3fda0-6d7f-4ed9-a767-6f0c0ce23a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11713
24163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1171324163
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.2013128105
Short name T750
Test name
Test status
Simulation time 1153013662 ps
CPU time 2.72 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 207072 kb
Host smart-6a47f99c-43a1-4ba9-a276-2cd6739f384a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20131
28105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.2013128105
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.355867685
Short name T2789
Test name
Test status
Simulation time 1021337020 ps
CPU time 22.22 seconds
Started Jul 30 06:32:31 PM PDT 24
Finished Jul 30 06:32:53 PM PDT 24
Peak memory 207084 kb
Host smart-f3b1bdaf-09ac-429b-8837-621ef63ed996
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355867685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_host
_handshake.355867685
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.3089445048
Short name T2239
Test name
Test status
Simulation time 52278546 ps
CPU time 0.75 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:32:38 PM PDT 24
Peak memory 207036 kb
Host smart-0dc7d69c-b115-4c6f-b9f3-db588cb5d58f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3089445048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.3089445048
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.524956148
Short name T788
Test name
Test status
Simulation time 4115036965 ps
CPU time 5.77 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 207096 kb
Host smart-32a08d4a-993f-4c48-931a-134d1abec474
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524956148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_ao
n_wake_disconnect.524956148
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2604056247
Short name T948
Test name
Test status
Simulation time 13395441988 ps
CPU time 16.23 seconds
Started Jul 30 06:32:34 PM PDT 24
Finished Jul 30 06:32:51 PM PDT 24
Peak memory 207156 kb
Host smart-b3a0dba9-a948-496e-bc3c-590b0f67557b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604056247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2604056247
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2067727917
Short name T1213
Test name
Test status
Simulation time 23316892489 ps
CPU time 29.25 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:33:09 PM PDT 24
Peak memory 207104 kb
Host smart-cb2983dd-03bf-4769-9769-2e45207acf45
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067727917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.2067727917
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1521272448
Short name T845
Test name
Test status
Simulation time 162836591 ps
CPU time 0.9 seconds
Started Jul 30 06:32:28 PM PDT 24
Finished Jul 30 06:32:29 PM PDT 24
Peak memory 206904 kb
Host smart-ee2e10ba-f65a-4086-ace0-b9c9d4a5ecbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15212
72448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1521272448
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.3579165094
Short name T63
Test name
Test status
Simulation time 158127082 ps
CPU time 0.85 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:32:36 PM PDT 24
Peak memory 206932 kb
Host smart-ceb5fcbf-a909-452c-8ea4-de84ba240a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35791
65094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3579165094
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.2725537432
Short name T1058
Test name
Test status
Simulation time 445399833 ps
CPU time 1.6 seconds
Started Jul 30 06:32:38 PM PDT 24
Finished Jul 30 06:32:39 PM PDT 24
Peak memory 206912 kb
Host smart-1ed7c520-d315-412a-bc1d-3dc8fba05115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27255
37432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.2725537432
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3012448386
Short name T2026
Test name
Test status
Simulation time 960830731 ps
CPU time 2.47 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:32:43 PM PDT 24
Peak memory 207024 kb
Host smart-1907ce35-0b35-48a7-96ba-d40e08eef975
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3012448386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3012448386
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.213592899
Short name T2205
Test name
Test status
Simulation time 12413881198 ps
CPU time 27.77 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:33:02 PM PDT 24
Peak memory 207116 kb
Host smart-fc9a00ae-1885-46fd-ba6c-a610865b4379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21359
2899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.213592899
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.2999812120
Short name T83
Test name
Test status
Simulation time 295113536 ps
CPU time 4.59 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206960 kb
Host smart-3ce06e7a-bc27-4c07-b364-b2b97ea78d85
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999812120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.2999812120
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3652617848
Short name T2245
Test name
Test status
Simulation time 521988830 ps
CPU time 1.47 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 206888 kb
Host smart-a3355c78-bf4d-4e02-972f-0dd69ba10841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36526
17848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3652617848
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2245508398
Short name T1788
Test name
Test status
Simulation time 147611200 ps
CPU time 0.84 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206892 kb
Host smart-7b075b50-1291-4942-94a7-5f4f8013f7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22455
08398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2245508398
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3496609181
Short name T585
Test name
Test status
Simulation time 47349873 ps
CPU time 0.74 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:32:43 PM PDT 24
Peak memory 206800 kb
Host smart-b2e76feb-4658-4908-9db2-c028270f8111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34966
09181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3496609181
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2943039802
Short name T809
Test name
Test status
Simulation time 858963292 ps
CPU time 2.39 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:32:39 PM PDT 24
Peak memory 207004 kb
Host smart-a3861d87-7d6b-4b3e-a2e4-9f84c1fbebe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29430
39802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2943039802
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3070174456
Short name T2696
Test name
Test status
Simulation time 251255452 ps
CPU time 1.61 seconds
Started Jul 30 06:32:33 PM PDT 24
Finished Jul 30 06:32:34 PM PDT 24
Peak memory 207008 kb
Host smart-ce1942b3-07cc-4d67-b12a-510199e821a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30701
74456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3070174456
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.926800622
Short name T863
Test name
Test status
Simulation time 225850567 ps
CPU time 1.16 seconds
Started Jul 30 06:32:33 PM PDT 24
Finished Jul 30 06:32:34 PM PDT 24
Peak memory 215212 kb
Host smart-936a1341-1a8a-4871-8c27-ca6034068ca3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=926800622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.926800622
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2032358486
Short name T1466
Test name
Test status
Simulation time 157269072 ps
CPU time 0.88 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:32:38 PM PDT 24
Peak memory 206888 kb
Host smart-6617cfe0-a853-4999-9dff-a205543a916f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20323
58486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2032358486
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.610465927
Short name T815
Test name
Test status
Simulation time 195133056 ps
CPU time 0.94 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:32:43 PM PDT 24
Peak memory 206948 kb
Host smart-a0518f53-c3ab-4478-b2fd-d1a5550509ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61046
5927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.610465927
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.896823546
Short name T2365
Test name
Test status
Simulation time 6650855407 ps
CPU time 47.8 seconds
Started Jul 30 06:32:34 PM PDT 24
Finished Jul 30 06:33:22 PM PDT 24
Peak memory 215364 kb
Host smart-ef761031-4e76-475c-957f-3c418ae08be7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=896823546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.896823546
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.888525903
Short name T1268
Test name
Test status
Simulation time 14140777189 ps
CPU time 96.59 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:34:18 PM PDT 24
Peak memory 207120 kb
Host smart-732a22d7-0e8a-440c-951b-b013a9abc36e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=888525903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.888525903
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3450094410
Short name T927
Test name
Test status
Simulation time 172379328 ps
CPU time 0.91 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:32:38 PM PDT 24
Peak memory 206916 kb
Host smart-5b235714-1c11-49f1-80c5-6606f9231e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34500
94410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3450094410
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.1402241024
Short name T1442
Test name
Test status
Simulation time 23390940953 ps
CPU time 27.71 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:33:05 PM PDT 24
Peak memory 207116 kb
Host smart-a5ab2540-5bdb-4d4d-9574-968e0ab3c11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14022
41024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1402241024
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1431591752
Short name T2216
Test name
Test status
Simulation time 3283464039 ps
CPU time 5.85 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:32:48 PM PDT 24
Peak memory 206972 kb
Host smart-745663e8-6187-4759-a60c-d38d98b7e86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14315
91752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1431591752
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.3862234196
Short name T2544
Test name
Test status
Simulation time 4966094596 ps
CPU time 46.82 seconds
Started Jul 30 06:32:31 PM PDT 24
Finished Jul 30 06:33:18 PM PDT 24
Peak memory 217352 kb
Host smart-c2c111d2-3b91-4de3-ba1b-5222539d3bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
34196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.3862234196
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1533689056
Short name T1043
Test name
Test status
Simulation time 4149614174 ps
CPU time 117.63 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:34:40 PM PDT 24
Peak memory 215312 kb
Host smart-7157c292-8746-43cc-bfc3-f24e09c40145
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1533689056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1533689056
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.1483941650
Short name T1286
Test name
Test status
Simulation time 271057079 ps
CPU time 1.09 seconds
Started Jul 30 06:32:36 PM PDT 24
Finished Jul 30 06:32:38 PM PDT 24
Peak memory 206924 kb
Host smart-6fb06942-fd7c-4192-9503-49a0c86f26ea
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1483941650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.1483941650
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.802051583
Short name T1111
Test name
Test status
Simulation time 261139956 ps
CPU time 1.07 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 206944 kb
Host smart-f3087b49-3fc0-4320-b456-76c329ba7135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80205
1583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.802051583
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.3952065435
Short name T1317
Test name
Test status
Simulation time 6839735545 ps
CPU time 202.15 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:36:04 PM PDT 24
Peak memory 215336 kb
Host smart-5beb0ca9-c1a6-4baa-a570-68cebf05efe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39520
65435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.3952065435
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3915283853
Short name T1053
Test name
Test status
Simulation time 7058888614 ps
CPU time 72.93 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:33:56 PM PDT 24
Peak memory 207156 kb
Host smart-e919b529-55cd-459f-b02f-7d5970d0ff70
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3915283853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3915283853
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1118001591
Short name T1883
Test name
Test status
Simulation time 157509512 ps
CPU time 0.86 seconds
Started Jul 30 06:32:31 PM PDT 24
Finished Jul 30 06:32:32 PM PDT 24
Peak memory 206928 kb
Host smart-17b097a4-eabd-4102-8f41-aceb38e27596
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1118001591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1118001591
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1800402468
Short name T369
Test name
Test status
Simulation time 166056134 ps
CPU time 0.86 seconds
Started Jul 30 06:32:38 PM PDT 24
Finished Jul 30 06:32:39 PM PDT 24
Peak memory 206880 kb
Host smart-70e8f988-0ef9-4c84-8700-67b5ee4da230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18004
02468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1800402468
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.611511194
Short name T1658
Test name
Test status
Simulation time 213065238 ps
CPU time 1 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:32:38 PM PDT 24
Peak memory 206944 kb
Host smart-afda4454-b57e-426e-920d-3ee8add4aa17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61151
1194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.611511194
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3416763743
Short name T2156
Test name
Test status
Simulation time 179527034 ps
CPU time 0.88 seconds
Started Jul 30 06:32:38 PM PDT 24
Finished Jul 30 06:32:39 PM PDT 24
Peak memory 206916 kb
Host smart-7075128b-0942-41cf-abba-5e632460f902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34167
63743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3416763743
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3798401772
Short name T1794
Test name
Test status
Simulation time 189220593 ps
CPU time 0.93 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 206920 kb
Host smart-4a53eb80-eaf6-4234-8607-e1adc8046694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37984
01772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3798401772
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3865679847
Short name T2332
Test name
Test status
Simulation time 166494044 ps
CPU time 0.91 seconds
Started Jul 30 06:32:36 PM PDT 24
Finished Jul 30 06:32:37 PM PDT 24
Peak memory 206968 kb
Host smart-c699dfbe-aa1c-4927-9260-23c2ec2f49d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38656
79847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3865679847
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2387510432
Short name T2821
Test name
Test status
Simulation time 189231991 ps
CPU time 0.89 seconds
Started Jul 30 06:32:33 PM PDT 24
Finished Jul 30 06:32:34 PM PDT 24
Peak memory 206912 kb
Host smart-d6ceef14-31dc-4fb2-9c02-263f6341b5b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23875
10432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2387510432
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.2791643222
Short name T474
Test name
Test status
Simulation time 224199552 ps
CPU time 1.01 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:32:36 PM PDT 24
Peak memory 206916 kb
Host smart-ceb7786b-1302-4bf4-a2b0-084065c84d73
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2791643222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.2791643222
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2918231379
Short name T1856
Test name
Test status
Simulation time 147554738 ps
CPU time 0.83 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:32:36 PM PDT 24
Peak memory 206908 kb
Host smart-517ee5cb-2789-4ecf-80ff-b58e3e0006d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29182
31379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2918231379
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2036949145
Short name T32
Test name
Test status
Simulation time 49033951 ps
CPU time 0.74 seconds
Started Jul 30 06:32:38 PM PDT 24
Finished Jul 30 06:32:39 PM PDT 24
Peak memory 206876 kb
Host smart-195c8d3d-797a-4000-a448-0600cb7d6d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20369
49145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2036949145
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.3224706837
Short name T999
Test name
Test status
Simulation time 213610461 ps
CPU time 0.87 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:32:42 PM PDT 24
Peak memory 206980 kb
Host smart-a42df134-1ae4-4cf5-b2f8-682a235bad6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32247
06837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3224706837
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2899916952
Short name T483
Test name
Test status
Simulation time 184193456 ps
CPU time 0.95 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:44 PM PDT 24
Peak memory 206920 kb
Host smart-c83689ed-5bf6-4208-81c6-52f2c1c1297a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28999
16952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2899916952
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2153244930
Short name T352
Test name
Test status
Simulation time 231761724 ps
CPU time 0.95 seconds
Started Jul 30 06:32:46 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 206900 kb
Host smart-5ff67712-e614-4217-9f9f-49f27523fe41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21532
44930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2153244930
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3961084318
Short name T2735
Test name
Test status
Simulation time 154856344 ps
CPU time 0.86 seconds
Started Jul 30 06:32:40 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 206908 kb
Host smart-0188a4aa-34ba-4bfe-a6b0-1017170155fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39610
84318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3961084318
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3133729796
Short name T2669
Test name
Test status
Simulation time 141972968 ps
CPU time 0.88 seconds
Started Jul 30 06:32:40 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 206900 kb
Host smart-2bb7c9d9-2435-46b3-ab4e-2b0495b62d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31337
29796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3133729796
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2748781271
Short name T1427
Test name
Test status
Simulation time 149350024 ps
CPU time 0.85 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 206944 kb
Host smart-18ebdbfd-ba97-4f1a-ac02-4368c93709ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27487
81271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2748781271
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2231520416
Short name T842
Test name
Test status
Simulation time 158793399 ps
CPU time 0.85 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:32:38 PM PDT 24
Peak memory 206916 kb
Host smart-3ec4a95b-14b9-420f-b6c1-b8115498a9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22315
20416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2231520416
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1688406935
Short name T2348
Test name
Test status
Simulation time 262933838 ps
CPU time 1.06 seconds
Started Jul 30 06:32:40 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 206928 kb
Host smart-25386cb4-6725-4295-81c1-7949a3e34a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16884
06935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1688406935
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.2235939321
Short name T1438
Test name
Test status
Simulation time 4280256189 ps
CPU time 32.75 seconds
Started Jul 30 06:32:40 PM PDT 24
Finished Jul 30 06:33:13 PM PDT 24
Peak memory 216912 kb
Host smart-b71e0edb-9516-4e0d-a9fd-e7b7238bc198
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2235939321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.2235939321
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1162523919
Short name T2470
Test name
Test status
Simulation time 207792580 ps
CPU time 0.92 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 206940 kb
Host smart-372cf002-a868-4571-a5d5-0bc78b53dab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11625
23919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1162523919
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2014902138
Short name T2616
Test name
Test status
Simulation time 150698441 ps
CPU time 0.84 seconds
Started Jul 30 06:32:38 PM PDT 24
Finished Jul 30 06:32:39 PM PDT 24
Peak memory 206948 kb
Host smart-e0f82078-e919-4ede-86dd-b20219fc930f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20149
02138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2014902138
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.1688475161
Short name T801
Test name
Test status
Simulation time 427926147 ps
CPU time 1.36 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:32:36 PM PDT 24
Peak memory 206884 kb
Host smart-32e8ba4b-d6da-4aaf-97c3-dbdca6e0358f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16884
75161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.1688475161
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1350798472
Short name T1809
Test name
Test status
Simulation time 5577337705 ps
CPU time 57.24 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:33:36 PM PDT 24
Peak memory 215368 kb
Host smart-82169c65-74ba-4f6c-8168-8c4c9e2837e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13507
98472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1350798472
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.2852185525
Short name T847
Test name
Test status
Simulation time 839591829 ps
CPU time 5.36 seconds
Started Jul 30 06:32:33 PM PDT 24
Finished Jul 30 06:32:38 PM PDT 24
Peak memory 206992 kb
Host smart-a36c4a14-ace2-40cd-a84d-d3251f4b7267
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852185525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.2852185525
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.1858005872
Short name T1860
Test name
Test status
Simulation time 45841729 ps
CPU time 0.7 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:32:42 PM PDT 24
Peak memory 207060 kb
Host smart-1b8f21ff-cde8-4198-bd93-027f3ae40115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1858005872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.1858005872
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.120794230
Short name T1290
Test name
Test status
Simulation time 3977124371 ps
CPU time 6.53 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:32:42 PM PDT 24
Peak memory 207044 kb
Host smart-80b36654-aac3-4caf-8e82-e23fdd8d3321
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120794230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_ao
n_wake_disconnect.120794230
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.380763599
Short name T1126
Test name
Test status
Simulation time 13408176578 ps
CPU time 16.38 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:32:53 PM PDT 24
Peak memory 207156 kb
Host smart-bdbe9c52-c9d3-4442-9cc2-014e4b18f81e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=380763599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.380763599
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.1074165109
Short name T2429
Test name
Test status
Simulation time 23322000765 ps
CPU time 28.66 seconds
Started Jul 30 06:32:35 PM PDT 24
Finished Jul 30 06:33:04 PM PDT 24
Peak memory 207160 kb
Host smart-8fbe9d2e-122c-4b2e-b154-534394e6b524
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074165109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.1074165109
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1487322365
Short name T1542
Test name
Test status
Simulation time 153305283 ps
CPU time 0.89 seconds
Started Jul 30 06:32:36 PM PDT 24
Finished Jul 30 06:32:37 PM PDT 24
Peak memory 206912 kb
Host smart-6beeb408-0475-4916-91e3-c58708997713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14873
22365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1487322365
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.1345484771
Short name T656
Test name
Test status
Simulation time 171137546 ps
CPU time 0.86 seconds
Started Jul 30 06:32:34 PM PDT 24
Finished Jul 30 06:32:35 PM PDT 24
Peak memory 206884 kb
Host smart-edda7b67-e35a-4b42-8bfc-34ffbc1c035b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13454
84771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.1345484771
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.4276741368
Short name T1644
Test name
Test status
Simulation time 228884361 ps
CPU time 1.03 seconds
Started Jul 30 06:32:37 PM PDT 24
Finished Jul 30 06:32:39 PM PDT 24
Peak memory 206928 kb
Host smart-f8178ea8-ec8d-4959-a38d-a099c6af6a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42767
41368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.4276741368
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2466288998
Short name T1160
Test name
Test status
Simulation time 860809623 ps
CPU time 2.61 seconds
Started Jul 30 06:32:34 PM PDT 24
Finished Jul 30 06:32:36 PM PDT 24
Peak memory 207040 kb
Host smart-a25932c0-27ac-4b08-9d15-05c01f0ec9aa
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2466288998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2466288998
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.2878945427
Short name T105
Test name
Test status
Simulation time 17550994933 ps
CPU time 33.9 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:33:13 PM PDT 24
Peak memory 207220 kb
Host smart-fd1414c4-26b2-473a-9dda-c657e3ccabdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28789
45427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.2878945427
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.2799534023
Short name T2320
Test name
Test status
Simulation time 4752781899 ps
CPU time 44.4 seconds
Started Jul 30 06:32:32 PM PDT 24
Finished Jul 30 06:33:17 PM PDT 24
Peak memory 207132 kb
Host smart-d987f443-0362-49e5-8c8a-7d1acd193719
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799534023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.2799534023
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.837189568
Short name T1063
Test name
Test status
Simulation time 411823999 ps
CPU time 1.36 seconds
Started Jul 30 06:32:48 PM PDT 24
Finished Jul 30 06:32:49 PM PDT 24
Peak memory 206876 kb
Host smart-01a31d37-7afe-4da7-b27d-a8eef2731e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83718
9568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.837189568
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.82896171
Short name T628
Test name
Test status
Simulation time 153892495 ps
CPU time 0.89 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 206920 kb
Host smart-285de42f-4fec-4e10-b822-70b39bc79397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82896
171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.82896171
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2950101894
Short name T463
Test name
Test status
Simulation time 29293052 ps
CPU time 0.69 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:44 PM PDT 24
Peak memory 206912 kb
Host smart-38d390fa-181a-4fad-af10-ef2c44228fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29501
01894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2950101894
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3795545899
Short name T2422
Test name
Test status
Simulation time 944426166 ps
CPU time 2.38 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 206988 kb
Host smart-5a8331af-2d9b-497c-bca2-a14bc0971af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37955
45899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3795545899
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3370392683
Short name T2196
Test name
Test status
Simulation time 171377671 ps
CPU time 1.78 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206928 kb
Host smart-bc218cef-a37f-4dae-bac0-6f68294db91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33703
92683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3370392683
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1573023495
Short name T1817
Test name
Test status
Simulation time 189824510 ps
CPU time 1.03 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 206864 kb
Host smart-7d41a92e-2438-4eed-91ca-fa3543ca4302
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1573023495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1573023495
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3429751639
Short name T88
Test name
Test status
Simulation time 162689745 ps
CPU time 0.87 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:32:42 PM PDT 24
Peak memory 206888 kb
Host smart-6e0d106c-07ff-4a7b-bade-3f2671bed67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34297
51639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3429751639
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.225311432
Short name T1972
Test name
Test status
Simulation time 178061124 ps
CPU time 0.91 seconds
Started Jul 30 06:32:40 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 206912 kb
Host smart-83b7573a-3c91-4b93-9315-f6f66294100f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22531
1432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.225311432
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.1260609223
Short name T459
Test name
Test status
Simulation time 6372750146 ps
CPU time 52.75 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 216748 kb
Host smart-d5793b30-712a-4d41-b6ae-38ff11f2e972
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1260609223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1260609223
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.2644356443
Short name T1508
Test name
Test status
Simulation time 4748294464 ps
CPU time 32.2 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:33:16 PM PDT 24
Peak memory 207084 kb
Host smart-8b5dc1d0-b22f-4fd4-998d-7fd09162ff2c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2644356443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.2644356443
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2495485016
Short name T73
Test name
Test status
Simulation time 207076460 ps
CPU time 0.93 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:44 PM PDT 24
Peak memory 206908 kb
Host smart-72aba8e6-6673-4371-96b5-555cf62d8066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24954
85016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2495485016
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2628580051
Short name T2018
Test name
Test status
Simulation time 23326428205 ps
CPU time 28.03 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:33:09 PM PDT 24
Peak memory 207148 kb
Host smart-50d3fb86-d2f4-45df-8118-b189d5f66c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26285
80051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2628580051
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1969726544
Short name T2473
Test name
Test status
Simulation time 3280544808 ps
CPU time 5.46 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:49 PM PDT 24
Peak memory 207092 kb
Host smart-a04e9c81-c2c7-4f95-a913-7341888a3320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19697
26544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1969726544
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.1815861826
Short name T405
Test name
Test status
Simulation time 4983878554 ps
CPU time 146.62 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:35:11 PM PDT 24
Peak memory 215308 kb
Host smart-09380508-2ee7-47b5-adef-06d0c6d741fc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1815861826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.1815861826
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.908116216
Short name T473
Test name
Test status
Simulation time 314631472 ps
CPU time 1.07 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 206944 kb
Host smart-b46e6475-4328-44e1-ab03-81629a9942a2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=908116216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.908116216
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.4165926803
Short name T2531
Test name
Test status
Simulation time 206322993 ps
CPU time 0.99 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:32:43 PM PDT 24
Peak memory 206988 kb
Host smart-5ff95c02-8b60-4b0c-a0f6-2c383d99515b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41659
26803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.4165926803
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.2051565190
Short name T487
Test name
Test status
Simulation time 5792591036 ps
CPU time 47.25 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:33:26 PM PDT 24
Peak memory 216448 kb
Host smart-4a61e6e4-10a4-4bbf-8dfd-779c0dfe1494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20515
65190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.2051565190
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1910052345
Short name T793
Test name
Test status
Simulation time 6146307111 ps
CPU time 183.95 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:35:45 PM PDT 24
Peak memory 215292 kb
Host smart-f8915408-f902-403a-b3f2-9ddc5a8b6749
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1910052345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1910052345
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2285589041
Short name T1532
Test name
Test status
Simulation time 152825369 ps
CPU time 0.84 seconds
Started Jul 30 06:32:47 PM PDT 24
Finished Jul 30 06:32:48 PM PDT 24
Peak memory 206952 kb
Host smart-4898a5ce-7919-4120-9228-e4c4a3fc85e2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2285589041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2285589041
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2129931387
Short name T2624
Test name
Test status
Simulation time 223402515 ps
CPU time 0.95 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206920 kb
Host smart-c3e7b512-a6cb-4eeb-baf8-c297880ce7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21299
31387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2129931387
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1990857418
Short name T115
Test name
Test status
Simulation time 182454866 ps
CPU time 0.91 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206952 kb
Host smart-02e7bc34-60f6-4928-8004-4e735ffdf6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19908
57418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1990857418
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.4250927750
Short name T2563
Test name
Test status
Simulation time 203579279 ps
CPU time 0.96 seconds
Started Jul 30 06:32:46 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 206916 kb
Host smart-1e22959c-999d-4582-91cc-f98bc9d71afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42509
27750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.4250927750
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.758410775
Short name T1143
Test name
Test status
Simulation time 148672836 ps
CPU time 0.84 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206924 kb
Host smart-1eb4b570-f526-46f9-9e01-4c64625ff9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75841
0775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.758410775
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1272663503
Short name T1670
Test name
Test status
Simulation time 165311941 ps
CPU time 0.88 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 206904 kb
Host smart-3e83ac53-b81d-4c59-b0f0-83397368e0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
63503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1272663503
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2426063698
Short name T1422
Test name
Test status
Simulation time 145806149 ps
CPU time 0.87 seconds
Started Jul 30 06:32:40 PM PDT 24
Finished Jul 30 06:32:41 PM PDT 24
Peak memory 206960 kb
Host smart-f8ae0f2f-08b4-4c41-a871-2e7b798e4081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24260
63698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2426063698
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.245297016
Short name T2307
Test name
Test status
Simulation time 261406179 ps
CPU time 1.06 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:44 PM PDT 24
Peak memory 206904 kb
Host smart-2e90292d-bad7-40d9-8102-adabc530163b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=245297016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.245297016
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3315968134
Short name T2132
Test name
Test status
Simulation time 140151899 ps
CPU time 0.8 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:32:42 PM PDT 24
Peak memory 206908 kb
Host smart-e65e6cd5-043b-400d-8dce-6854b92915fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33159
68134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3315968134
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2939160241
Short name T2242
Test name
Test status
Simulation time 39604318 ps
CPU time 0.74 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:32:43 PM PDT 24
Peak memory 206876 kb
Host smart-5caf9914-8bfe-4a1d-b2d4-0ad5b2da415e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29391
60241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2939160241
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2703423858
Short name T1301
Test name
Test status
Simulation time 10745516143 ps
CPU time 26.22 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:33:12 PM PDT 24
Peak memory 215296 kb
Host smart-9436ff9d-d37d-4274-945f-bac7d18187f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27034
23858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2703423858
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.4108035987
Short name T1877
Test name
Test status
Simulation time 181645144 ps
CPU time 0.94 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206988 kb
Host smart-8b538bcc-2914-4228-9edd-f8c322031ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41080
35987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.4108035987
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2837564940
Short name T1703
Test name
Test status
Simulation time 223096941 ps
CPU time 1 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:32:43 PM PDT 24
Peak memory 206952 kb
Host smart-cbd444cb-67d0-4bfa-a801-e9489e6d2d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28375
64940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2837564940
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.4246247103
Short name T343
Test name
Test status
Simulation time 169389492 ps
CPU time 0.88 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:44 PM PDT 24
Peak memory 206988 kb
Host smart-ca7c4947-c9de-45aa-ba23-56165379b01b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42462
47103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.4246247103
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2013998487
Short name T772
Test name
Test status
Simulation time 164516030 ps
CPU time 0.86 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206956 kb
Host smart-f1d9bb82-8db0-42eb-b1c5-55e600cf634b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20139
98487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2013998487
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.248680022
Short name T1543
Test name
Test status
Simulation time 172522040 ps
CPU time 0.91 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 206980 kb
Host smart-fef4d7ea-0be6-4252-8003-4718aca87484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24868
0022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.248680022
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2777535893
Short name T2074
Test name
Test status
Simulation time 177967631 ps
CPU time 0.88 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206916 kb
Host smart-bf72e444-0bfa-4265-90d2-6b11a5b6122b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27775
35893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2777535893
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2525604116
Short name T1279
Test name
Test status
Simulation time 148284886 ps
CPU time 0.87 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206912 kb
Host smart-28ec40e1-2b6d-4cf3-bd9b-a44a17624a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25256
04116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2525604116
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1681681867
Short name T1263
Test name
Test status
Simulation time 199031254 ps
CPU time 0.95 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:44 PM PDT 24
Peak memory 206904 kb
Host smart-91251bb5-6af5-4657-8f55-401f4bbd1edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16816
81867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1681681867
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2016861354
Short name T651
Test name
Test status
Simulation time 4996081713 ps
CPU time 151.3 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:35:16 PM PDT 24
Peak memory 215316 kb
Host smart-00b03998-4d4e-4d1a-87fb-d04686671e4c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2016861354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2016861354
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1083482720
Short name T621
Test name
Test status
Simulation time 213510085 ps
CPU time 0.91 seconds
Started Jul 30 06:32:54 PM PDT 24
Finished Jul 30 06:32:55 PM PDT 24
Peak memory 206952 kb
Host smart-88a56f08-666e-44ad-bd02-3696eb786d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10834
82720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1083482720
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1667779662
Short name T1406
Test name
Test status
Simulation time 208616563 ps
CPU time 1.04 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 206988 kb
Host smart-46ee8c1c-3bef-41dd-8b85-d7307350b668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16677
79662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1667779662
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.947612832
Short name T2378
Test name
Test status
Simulation time 1316400476 ps
CPU time 3.07 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:48 PM PDT 24
Peak memory 206960 kb
Host smart-a50acb6e-013e-408f-8a17-67be546f6ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94761
2832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.947612832
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2961373600
Short name T1252
Test name
Test status
Simulation time 3085049124 ps
CPU time 30.92 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:33:12 PM PDT 24
Peak memory 215316 kb
Host smart-fb8e8958-09d7-4224-9c53-a8411e79877e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29613
73600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2961373600
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.345528736
Short name T1566
Test name
Test status
Simulation time 866146507 ps
CPU time 5.48 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 207056 kb
Host smart-27561e4d-8642-4331-84b6-0bc02fcaf7b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345528736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_host
_handshake.345528736
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.3544238241
Short name T640
Test name
Test status
Simulation time 56427507 ps
CPU time 0.65 seconds
Started Jul 30 06:32:49 PM PDT 24
Finished Jul 30 06:32:50 PM PDT 24
Peak memory 207016 kb
Host smart-2b2e29d4-59aa-477b-9361-5690a0e8c6c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3544238241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3544238241
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2905126115
Short name T1363
Test name
Test status
Simulation time 3731805541 ps
CPU time 6.6 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:32:48 PM PDT 24
Peak memory 207084 kb
Host smart-e1a9bcd0-eab2-403a-a5da-3e9b063f0214
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905126115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_disconnect.2905126115
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.496280603
Short name T13
Test name
Test status
Simulation time 13309169610 ps
CPU time 17.65 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:33:00 PM PDT 24
Peak memory 207264 kb
Host smart-0fde951c-44cf-4b2f-9df8-d91978d9459e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=496280603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.496280603
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.4149014215
Short name T2032
Test name
Test status
Simulation time 23355825614 ps
CPU time 28.9 seconds
Started Jul 30 06:32:49 PM PDT 24
Finished Jul 30 06:33:18 PM PDT 24
Peak memory 207164 kb
Host smart-dd462879-c0ad-4f89-8401-d2bdf68f0df3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149014215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.4149014215
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3454533641
Short name T475
Test name
Test status
Simulation time 171357403 ps
CPU time 0.97 seconds
Started Jul 30 06:32:48 PM PDT 24
Finished Jul 30 06:32:49 PM PDT 24
Peak memory 206900 kb
Host smart-50184333-8858-4d04-9339-4b521c3050af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34545
33641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3454533641
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.306799257
Short name T1756
Test name
Test status
Simulation time 186794698 ps
CPU time 0.86 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 206876 kb
Host smart-0fe25db1-c825-4850-ad25-2711afd61188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30679
9257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.306799257
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.2292262468
Short name T2421
Test name
Test status
Simulation time 358175111 ps
CPU time 1.3 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206900 kb
Host smart-2b46c2a7-1ddb-4c3f-a051-f2d67183eeb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22922
62468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.2292262468
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.213632528
Short name T1216
Test name
Test status
Simulation time 1197617307 ps
CPU time 3.23 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 207052 kb
Host smart-162407b4-dc02-42a8-aa44-be6745ced5ea
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=213632528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.213632528
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.4036321680
Short name T2082
Test name
Test status
Simulation time 12059872203 ps
CPU time 31.53 seconds
Started Jul 30 06:32:47 PM PDT 24
Finished Jul 30 06:33:18 PM PDT 24
Peak memory 207088 kb
Host smart-d98a584a-9cea-4d29-aaff-5922eb7ea093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40363
21680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.4036321680
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.380765162
Short name T1714
Test name
Test status
Simulation time 620397240 ps
CPU time 4.97 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 207040 kb
Host smart-6d32f8df-7d3b-4cdf-b417-336cbdfaec2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380765162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.380765162
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.585708957
Short name T1965
Test name
Test status
Simulation time 431979601 ps
CPU time 1.4 seconds
Started Jul 30 06:32:48 PM PDT 24
Finished Jul 30 06:32:50 PM PDT 24
Peak memory 206876 kb
Host smart-2097175c-6d7a-4965-a961-58a915fb0d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58570
8957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.585708957
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.4077614331
Short name T2781
Test name
Test status
Simulation time 169861764 ps
CPU time 0.88 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 206920 kb
Host smart-eaa0acc0-64b3-48a2-8d30-a1d34a2b57c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40776
14331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.4077614331
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1902263730
Short name T1540
Test name
Test status
Simulation time 39859944 ps
CPU time 0.7 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206920 kb
Host smart-24d05da8-0c82-4628-b975-e5612aa241d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19022
63730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1902263730
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1902009368
Short name T2019
Test name
Test status
Simulation time 982472133 ps
CPU time 2.63 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 206880 kb
Host smart-40bbaa7b-e1dd-4e70-a09c-78432343775b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19020
09368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1902009368
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.23881495
Short name T2319
Test name
Test status
Simulation time 251913263 ps
CPU time 1.98 seconds
Started Jul 30 06:32:48 PM PDT 24
Finished Jul 30 06:32:51 PM PDT 24
Peak memory 206952 kb
Host smart-75e4c5a5-8344-40b1-abd5-7e16b2f46da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23881
495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.23881495
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2579540259
Short name T2044
Test name
Test status
Simulation time 259421030 ps
CPU time 1.2 seconds
Started Jul 30 06:32:41 PM PDT 24
Finished Jul 30 06:32:42 PM PDT 24
Peak memory 215196 kb
Host smart-78d6b1d1-7de3-406d-b493-8e18d155930c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2579540259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2579540259
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1622663098
Short name T331
Test name
Test status
Simulation time 208156624 ps
CPU time 0.93 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 206904 kb
Host smart-f8fb7401-911e-4933-9720-835891982b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16226
63098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1622663098
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1817928413
Short name T1272
Test name
Test status
Simulation time 210537832 ps
CPU time 0.96 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:32:43 PM PDT 24
Peak memory 206908 kb
Host smart-61b22511-08c2-4a6c-91ab-ae8a83e24cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18179
28413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1817928413
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.1615032520
Short name T1310
Test name
Test status
Simulation time 6582433620 ps
CPU time 198.43 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:36:00 PM PDT 24
Peak memory 215380 kb
Host smart-39dbc55e-e35d-4b18-ad42-c62f2eac387a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1615032520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1615032520
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.3761793157
Short name T2774
Test name
Test status
Simulation time 11681156147 ps
CPU time 145.54 seconds
Started Jul 30 06:32:39 PM PDT 24
Finished Jul 30 06:35:05 PM PDT 24
Peak memory 207128 kb
Host smart-c5ba5b76-472a-4a0a-93fb-e01f010efb04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3761793157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.3761793157
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2837706573
Short name T360
Test name
Test status
Simulation time 198576309 ps
CPU time 0.91 seconds
Started Jul 30 06:32:50 PM PDT 24
Finished Jul 30 06:32:51 PM PDT 24
Peak memory 206980 kb
Host smart-96ece798-61db-4b25-85c2-b39512055cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28377
06573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2837706573
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1127765031
Short name T1737
Test name
Test status
Simulation time 23350294218 ps
CPU time 34.12 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:33:19 PM PDT 24
Peak memory 207148 kb
Host smart-2c2651f6-1ee2-40b5-aadd-76b55cc30490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11277
65031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1127765031
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.315588419
Short name T1289
Test name
Test status
Simulation time 3354548494 ps
CPU time 5.11 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:49 PM PDT 24
Peak memory 207092 kb
Host smart-f6a9dc1f-6590-4c6c-9bbd-941042949fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31558
8419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.315588419
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.2662665863
Short name T1327
Test name
Test status
Simulation time 9144024089 ps
CPU time 69.94 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:33:52 PM PDT 24
Peak memory 215296 kb
Host smart-7d0ed58e-cf25-4161-b12d-a55e6be2adf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26626
65863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.2662665863
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1853273881
Short name T943
Test name
Test status
Simulation time 7177625560 ps
CPU time 53.2 seconds
Started Jul 30 06:32:48 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 207152 kb
Host smart-c014b900-3925-4e08-a82c-a4e002740f6f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1853273881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1853273881
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1623476141
Short name T1510
Test name
Test status
Simulation time 255872177 ps
CPU time 1.01 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206916 kb
Host smart-6155f378-e068-412b-9694-ff185c50a9e2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1623476141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1623476141
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.259893643
Short name T491
Test name
Test status
Simulation time 264339851 ps
CPU time 1.02 seconds
Started Jul 30 06:32:53 PM PDT 24
Finished Jul 30 06:32:54 PM PDT 24
Peak memory 206896 kb
Host smart-aedc6a06-da2d-48b8-a76f-6cc2ea4bcadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25989
3643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.259893643
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.793021541
Short name T1938
Test name
Test status
Simulation time 4727682162 ps
CPU time 45.3 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:33:27 PM PDT 24
Peak memory 215352 kb
Host smart-cd69ace3-12fb-4d35-b694-f3440b457cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79302
1541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.793021541
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.4116512350
Short name T954
Test name
Test status
Simulation time 4213996494 ps
CPU time 42.66 seconds
Started Jul 30 06:32:50 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 215396 kb
Host smart-16f420b5-b94f-4470-8802-05284e167c60
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4116512350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.4116512350
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3232758542
Short name T2605
Test name
Test status
Simulation time 156209124 ps
CPU time 0.86 seconds
Started Jul 30 06:32:51 PM PDT 24
Finished Jul 30 06:32:52 PM PDT 24
Peak memory 207004 kb
Host smart-9f14bd68-70d7-41a4-acea-57994c822bcd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3232758542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3232758542
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3656031092
Short name T2037
Test name
Test status
Simulation time 155107624 ps
CPU time 0.87 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:44 PM PDT 24
Peak memory 207076 kb
Host smart-e4216c89-4086-4fef-bf1c-95f9e31103d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36560
31092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3656031092
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3636298405
Short name T135
Test name
Test status
Simulation time 199048699 ps
CPU time 1.01 seconds
Started Jul 30 06:32:49 PM PDT 24
Finished Jul 30 06:32:50 PM PDT 24
Peak memory 206912 kb
Host smart-97bfe8ac-ea8a-4d5f-907c-82f0c50a120c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36362
98405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3636298405
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2999948768
Short name T109
Test name
Test status
Simulation time 168504572 ps
CPU time 0.86 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 206968 kb
Host smart-6f329422-e90b-4de4-8dfc-a86a9476f9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29999
48768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2999948768
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2631014971
Short name T701
Test name
Test status
Simulation time 186012973 ps
CPU time 0.93 seconds
Started Jul 30 06:32:46 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 206940 kb
Host smart-27907a24-03c0-420b-9652-8d8e2035f070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26310
14971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2631014971
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3891457661
Short name T1097
Test name
Test status
Simulation time 156734697 ps
CPU time 0.85 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206976 kb
Host smart-341ae311-8f3f-41d1-a731-fe4fb2d465f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38914
57661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3891457661
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1601938067
Short name T1193
Test name
Test status
Simulation time 171976771 ps
CPU time 0.88 seconds
Started Jul 30 06:32:48 PM PDT 24
Finished Jul 30 06:32:49 PM PDT 24
Peak memory 206916 kb
Host smart-340a74ac-5a8a-4970-b479-972693e8b1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16019
38067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1601938067
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.603152320
Short name T1863
Test name
Test status
Simulation time 190372528 ps
CPU time 1.11 seconds
Started Jul 30 06:32:53 PM PDT 24
Finished Jul 30 06:32:54 PM PDT 24
Peak memory 206908 kb
Host smart-fc64d445-3633-485a-b674-cdb6738396f5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=603152320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.603152320
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.4290870036
Short name T563
Test name
Test status
Simulation time 144132919 ps
CPU time 0.84 seconds
Started Jul 30 06:32:46 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 206892 kb
Host smart-3fb7ee3e-a2aa-4ee4-a8c6-83dd2f1439e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42908
70036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.4290870036
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3635023635
Short name T2292
Test name
Test status
Simulation time 89905007 ps
CPU time 0.75 seconds
Started Jul 30 06:32:46 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 206904 kb
Host smart-62bcd38d-5e6a-4659-869f-1111955f3db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36350
23635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3635023635
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1164891973
Short name T976
Test name
Test status
Simulation time 19843979054 ps
CPU time 49.49 seconds
Started Jul 30 06:32:46 PM PDT 24
Finished Jul 30 06:33:35 PM PDT 24
Peak memory 223472 kb
Host smart-3b991536-bdb9-48be-9946-3576ec72c292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11648
91973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1164891973
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3967468462
Short name T2193
Test name
Test status
Simulation time 155981012 ps
CPU time 0.83 seconds
Started Jul 30 06:32:46 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 206912 kb
Host smart-bb1b0a16-67a3-4edf-b04a-5d3d483d32ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39674
68462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3967468462
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2119197684
Short name T2102
Test name
Test status
Simulation time 221347631 ps
CPU time 1.02 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 206912 kb
Host smart-86ce1271-e491-4dae-b1be-ac8dab04f3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
97684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2119197684
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.493711636
Short name T1548
Test name
Test status
Simulation time 188307393 ps
CPU time 0.9 seconds
Started Jul 30 06:32:47 PM PDT 24
Finished Jul 30 06:32:48 PM PDT 24
Peak memory 206944 kb
Host smart-f91db3c2-fee1-4012-827b-3849b856c74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49371
1636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.493711636
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.2903258025
Short name T965
Test name
Test status
Simulation time 157593139 ps
CPU time 0.82 seconds
Started Jul 30 06:32:46 PM PDT 24
Finished Jul 30 06:32:46 PM PDT 24
Peak memory 206940 kb
Host smart-b04ee3e0-dba6-4ee7-9a8b-25a2452a2034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29032
58025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.2903258025
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2087681858
Short name T2326
Test name
Test status
Simulation time 203327112 ps
CPU time 0.92 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 206924 kb
Host smart-65f0176f-0033-4a17-b496-d97c8849e829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20876
81858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2087681858
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.624859359
Short name T642
Test name
Test status
Simulation time 161024825 ps
CPU time 0.85 seconds
Started Jul 30 06:32:42 PM PDT 24
Finished Jul 30 06:32:43 PM PDT 24
Peak memory 206876 kb
Host smart-46e38e58-4989-46a8-b2af-8fde7aede318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62485
9359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.624859359
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.673142938
Short name T2554
Test name
Test status
Simulation time 148488126 ps
CPU time 0.86 seconds
Started Jul 30 06:32:43 PM PDT 24
Finished Jul 30 06:32:44 PM PDT 24
Peak memory 206920 kb
Host smart-ec210435-508a-44ac-9184-5f690219450d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67314
2938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.673142938
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2429749645
Short name T1963
Test name
Test status
Simulation time 218683901 ps
CPU time 1 seconds
Started Jul 30 06:32:48 PM PDT 24
Finished Jul 30 06:32:49 PM PDT 24
Peak memory 206944 kb
Host smart-0cc99a57-c9b5-4612-8e0a-45b94799fde7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24297
49645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2429749645
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2115575824
Short name T1704
Test name
Test status
Simulation time 184773648 ps
CPU time 0.92 seconds
Started Jul 30 06:32:48 PM PDT 24
Finished Jul 30 06:32:49 PM PDT 24
Peak memory 206928 kb
Host smart-ab61c5b6-2a4e-4b24-a593-a6064ab0b8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21155
75824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2115575824
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.4031802056
Short name T2182
Test name
Test status
Simulation time 142891642 ps
CPU time 0.86 seconds
Started Jul 30 06:32:46 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 206908 kb
Host smart-ac776738-58fc-4151-a5ec-679afcb014cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40318
02056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.4031802056
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.1477731356
Short name T1812
Test name
Test status
Simulation time 510028689 ps
CPU time 1.55 seconds
Started Jul 30 06:32:49 PM PDT 24
Finished Jul 30 06:32:51 PM PDT 24
Peak memory 206912 kb
Host smart-42a8b7ce-66c8-4dd8-aa1a-9aeea901138c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14777
31356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1477731356
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1615539851
Short name T1032
Test name
Test status
Simulation time 6859888799 ps
CPU time 206.06 seconds
Started Jul 30 06:32:48 PM PDT 24
Finished Jul 30 06:36:14 PM PDT 24
Peak memory 215316 kb
Host smart-6cdc3d0c-df96-4f65-ac2d-a58b67d4374b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16155
39851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1615539851
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.2863300795
Short name T1385
Test name
Test status
Simulation time 317381157 ps
CPU time 4.55 seconds
Started Jul 30 06:32:46 PM PDT 24
Finished Jul 30 06:32:51 PM PDT 24
Peak memory 207088 kb
Host smart-af26ed7a-d356-4cd1-b93e-ab2caceb7ae7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863300795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.2863300795
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.1821671544
Short name T181
Test name
Test status
Simulation time 97080533 ps
CPU time 0.79 seconds
Started Jul 30 06:32:56 PM PDT 24
Finished Jul 30 06:32:57 PM PDT 24
Peak memory 207004 kb
Host smart-ac429ddd-fcfc-46ef-91e9-442d62788c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1821671544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.1821671544
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2337172471
Short name T1498
Test name
Test status
Simulation time 3837253688 ps
CPU time 6.64 seconds
Started Jul 30 06:32:53 PM PDT 24
Finished Jul 30 06:33:00 PM PDT 24
Peak memory 207072 kb
Host smart-14706994-3ce0-41e7-8a36-b0ed8d52d9c3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337172471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.2337172471
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3044972824
Short name T16
Test name
Test status
Simulation time 13466896613 ps
CPU time 17.25 seconds
Started Jul 30 06:32:49 PM PDT 24
Finished Jul 30 06:33:06 PM PDT 24
Peak memory 207188 kb
Host smart-02ecb557-a984-4985-ae1b-c0c4c0d6fd88
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044972824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3044972824
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1281376890
Short name T421
Test name
Test status
Simulation time 23302290227 ps
CPU time 26.2 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:33:10 PM PDT 24
Peak memory 207124 kb
Host smart-4ace8c97-5907-4ad2-b997-ea0a75ba03ac
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281376890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.1281376890
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2436726849
Short name T1560
Test name
Test status
Simulation time 157219587 ps
CPU time 0.87 seconds
Started Jul 30 06:32:44 PM PDT 24
Finished Jul 30 06:32:45 PM PDT 24
Peak memory 206904 kb
Host smart-a4a73861-311a-4dc0-b33b-6afad3cf8746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24367
26849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2436726849
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.813939110
Short name T509
Test name
Test status
Simulation time 152415217 ps
CPU time 0.92 seconds
Started Jul 30 06:32:48 PM PDT 24
Finished Jul 30 06:32:49 PM PDT 24
Peak memory 206912 kb
Host smart-310dded0-4235-4a8d-9205-a660c0042730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81393
9110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.813939110
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.2059813
Short name T2061
Test name
Test status
Simulation time 513871101 ps
CPU time 1.65 seconds
Started Jul 30 06:32:54 PM PDT 24
Finished Jul 30 06:32:56 PM PDT 24
Peak memory 206908 kb
Host smart-4596e102-1c2e-4796-84f2-e2d285b37142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20598
13 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.2059813
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.4049210588
Short name T1684
Test name
Test status
Simulation time 552270525 ps
CPU time 1.61 seconds
Started Jul 30 06:32:47 PM PDT 24
Finished Jul 30 06:32:49 PM PDT 24
Peak memory 206924 kb
Host smart-49a3a133-db1f-4082-8c37-9e5bc596ad72
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4049210588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.4049210588
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.1607420888
Short name T556
Test name
Test status
Simulation time 1993846853 ps
CPU time 17.61 seconds
Started Jul 30 06:32:51 PM PDT 24
Finished Jul 30 06:33:09 PM PDT 24
Peak memory 207064 kb
Host smart-5a6e395a-d5dd-44ab-a110-f2d32a8d5d61
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607420888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.1607420888
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.2729203969
Short name T358
Test name
Test status
Simulation time 431435771 ps
CPU time 1.52 seconds
Started Jul 30 06:32:49 PM PDT 24
Finished Jul 30 06:32:51 PM PDT 24
Peak memory 206896 kb
Host smart-9d189f99-3020-40ab-86ed-dbfa559f228b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27292
03969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.2729203969
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.721111208
Short name T1611
Test name
Test status
Simulation time 149970950 ps
CPU time 0.79 seconds
Started Jul 30 06:32:49 PM PDT 24
Finished Jul 30 06:32:49 PM PDT 24
Peak memory 206892 kb
Host smart-f407360a-6399-4ba8-a43e-e911355adde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72111
1208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.721111208
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.2278216778
Short name T2667
Test name
Test status
Simulation time 87548762 ps
CPU time 0.73 seconds
Started Jul 30 06:32:57 PM PDT 24
Finished Jul 30 06:32:58 PM PDT 24
Peak memory 206880 kb
Host smart-68372155-6732-4fba-955f-9ce072622ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22782
16778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2278216778
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.2960371579
Short name T301
Test name
Test status
Simulation time 936716208 ps
CPU time 2.5 seconds
Started Jul 30 06:32:46 PM PDT 24
Finished Jul 30 06:32:49 PM PDT 24
Peak memory 207092 kb
Host smart-895966ba-79c9-485e-94dc-4300a181e165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29603
71579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2960371579
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3025495642
Short name T1593
Test name
Test status
Simulation time 188418274 ps
CPU time 1.48 seconds
Started Jul 30 06:32:51 PM PDT 24
Finished Jul 30 06:32:52 PM PDT 24
Peak memory 207020 kb
Host smart-1f04de25-a0dd-4042-8dc6-e38a09be870e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30254
95642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3025495642
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.1342767559
Short name T1283
Test name
Test status
Simulation time 213382109 ps
CPU time 1.14 seconds
Started Jul 30 06:32:52 PM PDT 24
Finished Jul 30 06:32:53 PM PDT 24
Peak memory 215164 kb
Host smart-a5160990-fbba-43b7-b72c-dbcfc6f885a9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1342767559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1342767559
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1171457377
Short name T578
Test name
Test status
Simulation time 139777067 ps
CPU time 0.83 seconds
Started Jul 30 06:32:54 PM PDT 24
Finished Jul 30 06:32:55 PM PDT 24
Peak memory 206912 kb
Host smart-70720981-4803-45c5-95af-0ec232134111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11714
57377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1171457377
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1955092787
Short name T2436
Test name
Test status
Simulation time 180386287 ps
CPU time 0.96 seconds
Started Jul 30 06:32:49 PM PDT 24
Finished Jul 30 06:32:50 PM PDT 24
Peak memory 206944 kb
Host smart-ba64b8b6-533b-48bb-b64d-ce79a0d9cc8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19550
92787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1955092787
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.3482148931
Short name T2602
Test name
Test status
Simulation time 9977558846 ps
CPU time 101.21 seconds
Started Jul 30 06:32:53 PM PDT 24
Finished Jul 30 06:34:34 PM PDT 24
Peak memory 215324 kb
Host smart-eca294a9-90f8-4b4b-a738-6b9830abb54f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3482148931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.3482148931
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.3477447204
Short name T1051
Test name
Test status
Simulation time 14162036400 ps
CPU time 90.54 seconds
Started Jul 30 06:32:47 PM PDT 24
Finished Jul 30 06:34:18 PM PDT 24
Peak memory 207096 kb
Host smart-2e82b1ca-dd00-4550-9d69-b1ec650b9807
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3477447204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.3477447204
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3199301471
Short name T2023
Test name
Test status
Simulation time 217696105 ps
CPU time 0.95 seconds
Started Jul 30 06:32:57 PM PDT 24
Finished Jul 30 06:32:58 PM PDT 24
Peak memory 206916 kb
Host smart-49542996-b29f-42dd-8d2a-0a73762128e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31993
01471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3199301471
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.2057553928
Short name T975
Test name
Test status
Simulation time 23355559495 ps
CPU time 33.36 seconds
Started Jul 30 06:32:51 PM PDT 24
Finished Jul 30 06:33:25 PM PDT 24
Peak memory 207128 kb
Host smart-1ae6f8f0-4fbf-4569-ae79-1b9a5f1adf63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20575
53928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.2057553928
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2739030962
Short name T340
Test name
Test status
Simulation time 3318770118 ps
CPU time 5.07 seconds
Started Jul 30 06:32:52 PM PDT 24
Finished Jul 30 06:32:57 PM PDT 24
Peak memory 207128 kb
Host smart-7b840b1c-85df-4819-ab77-5da65fa96af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27390
30962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2739030962
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2311676746
Short name T561
Test name
Test status
Simulation time 8507668062 ps
CPU time 243.17 seconds
Started Jul 30 06:32:58 PM PDT 24
Finished Jul 30 06:37:01 PM PDT 24
Peak memory 215304 kb
Host smart-095f5091-dd0b-4983-b545-e2f70d4cc167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23116
76746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2311676746
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3161846773
Short name T1535
Test name
Test status
Simulation time 7807316007 ps
CPU time 59.16 seconds
Started Jul 30 06:32:47 PM PDT 24
Finished Jul 30 06:33:46 PM PDT 24
Peak memory 207160 kb
Host smart-d214a35b-bf5c-4d03-af39-69179a42e092
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3161846773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3161846773
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.817999599
Short name T2658
Test name
Test status
Simulation time 233699374 ps
CPU time 1.01 seconds
Started Jul 30 06:32:58 PM PDT 24
Finished Jul 30 06:32:59 PM PDT 24
Peak memory 206928 kb
Host smart-b3beb74b-a2da-4d7b-8f55-f56a24dfe17c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=817999599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.817999599
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.729553233
Short name T1531
Test name
Test status
Simulation time 209303380 ps
CPU time 1.02 seconds
Started Jul 30 06:32:52 PM PDT 24
Finished Jul 30 06:32:54 PM PDT 24
Peak memory 206972 kb
Host smart-05ac3d61-6b91-4795-8417-be23a5d0a0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72955
3233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.729553233
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.3614013125
Short name T365
Test name
Test status
Simulation time 6749328135 ps
CPU time 200.35 seconds
Started Jul 30 06:32:56 PM PDT 24
Finished Jul 30 06:36:16 PM PDT 24
Peak memory 215288 kb
Host smart-843a4c2c-60e8-488c-97de-c07d8e5233f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36140
13125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.3614013125
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.2551085043
Short name T1868
Test name
Test status
Simulation time 3416902731 ps
CPU time 98.72 seconds
Started Jul 30 06:32:53 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 215324 kb
Host smart-b3bab55e-12a9-4b65-8c30-2866d6ab33ac
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2551085043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.2551085043
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.3581697005
Short name T2663
Test name
Test status
Simulation time 156560984 ps
CPU time 0.95 seconds
Started Jul 30 06:32:58 PM PDT 24
Finished Jul 30 06:32:59 PM PDT 24
Peak memory 206940 kb
Host smart-a445c641-b740-4ebc-b647-c119d5c9333b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3581697005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.3581697005
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3968374222
Short name T1086
Test name
Test status
Simulation time 154275853 ps
CPU time 0.92 seconds
Started Jul 30 06:32:53 PM PDT 24
Finished Jul 30 06:32:54 PM PDT 24
Peak memory 206972 kb
Host smart-34f149c7-8e51-4c2f-a04d-f79efa913145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39683
74222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3968374222
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3354742633
Short name T1935
Test name
Test status
Simulation time 214287794 ps
CPU time 0.99 seconds
Started Jul 30 06:32:58 PM PDT 24
Finished Jul 30 06:32:59 PM PDT 24
Peak memory 206912 kb
Host smart-a8f8b965-ce78-4bf0-9ad4-fd20acf91f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33547
42633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3354742633
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1567350375
Short name T2744
Test name
Test status
Simulation time 183948168 ps
CPU time 0.92 seconds
Started Jul 30 06:32:53 PM PDT 24
Finished Jul 30 06:32:54 PM PDT 24
Peak memory 206880 kb
Host smart-760e15c0-10b7-46b2-98b9-a2196806586f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15673
50375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1567350375
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3156181941
Short name T1276
Test name
Test status
Simulation time 156620318 ps
CPU time 0.85 seconds
Started Jul 30 06:32:52 PM PDT 24
Finished Jul 30 06:32:53 PM PDT 24
Peak memory 206932 kb
Host smart-f1bc87df-d692-49f6-a15d-8736757de173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31561
81941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3156181941
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3102804575
Short name T2541
Test name
Test status
Simulation time 143928243 ps
CPU time 0.89 seconds
Started Jul 30 06:32:52 PM PDT 24
Finished Jul 30 06:32:53 PM PDT 24
Peak memory 206952 kb
Host smart-9f9bb3f5-0db7-48c9-aecc-77a55734937a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31028
04575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3102804575
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2589588182
Short name T1066
Test name
Test status
Simulation time 213928018 ps
CPU time 0.95 seconds
Started Jul 30 06:32:54 PM PDT 24
Finished Jul 30 06:32:55 PM PDT 24
Peak memory 206928 kb
Host smart-214ef8e7-304c-4e95-bba2-f7444346664c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25895
88182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2589588182
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.3618940376
Short name T1619
Test name
Test status
Simulation time 272042929 ps
CPU time 1.11 seconds
Started Jul 30 06:32:51 PM PDT 24
Finished Jul 30 06:32:52 PM PDT 24
Peak memory 206932 kb
Host smart-24ca76c1-cb22-4fab-8899-ac1eec8d5b7e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3618940376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.3618940376
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2927296366
Short name T429
Test name
Test status
Simulation time 176244650 ps
CPU time 0.85 seconds
Started Jul 30 06:32:51 PM PDT 24
Finished Jul 30 06:32:52 PM PDT 24
Peak memory 206892 kb
Host smart-1b7b18ee-b265-443a-9791-8f13ba5b16a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29272
96366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2927296366
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2475520366
Short name T911
Test name
Test status
Simulation time 49121252 ps
CPU time 0.77 seconds
Started Jul 30 06:32:53 PM PDT 24
Finished Jul 30 06:32:54 PM PDT 24
Peak memory 206940 kb
Host smart-681d5cf6-64f7-4576-89f4-54a7ff2c664d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24755
20366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2475520366
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.717902864
Short name T2573
Test name
Test status
Simulation time 16564313965 ps
CPU time 40.03 seconds
Started Jul 30 06:32:58 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 223508 kb
Host smart-24a3e7a2-6fc8-4a27-8e1a-612c7a85b756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71790
2864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.717902864
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1818413070
Short name T1562
Test name
Test status
Simulation time 178688864 ps
CPU time 0.89 seconds
Started Jul 30 06:32:52 PM PDT 24
Finished Jul 30 06:32:53 PM PDT 24
Peak memory 206920 kb
Host smart-054c98f8-78df-4890-96f0-7e6993d5c3c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18184
13070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1818413070
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.4136923648
Short name T2249
Test name
Test status
Simulation time 224190357 ps
CPU time 0.95 seconds
Started Jul 30 06:32:57 PM PDT 24
Finished Jul 30 06:32:58 PM PDT 24
Peak memory 206912 kb
Host smart-7c58d089-3330-461c-983f-f3368c62dfcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41369
23648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.4136923648
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.4269779830
Short name T1746
Test name
Test status
Simulation time 177265256 ps
CPU time 0.9 seconds
Started Jul 30 06:32:54 PM PDT 24
Finished Jul 30 06:32:55 PM PDT 24
Peak memory 206932 kb
Host smart-e64d623f-e23d-4d43-8744-1032e2c18ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42697
79830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.4269779830
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2449284244
Short name T2659
Test name
Test status
Simulation time 164298429 ps
CPU time 0.89 seconds
Started Jul 30 06:32:53 PM PDT 24
Finished Jul 30 06:32:54 PM PDT 24
Peak memory 206908 kb
Host smart-ebfe1fcd-f611-427b-90ac-d1b8e3d9a086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24492
84244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2449284244
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.820284931
Short name T2623
Test name
Test status
Simulation time 201677568 ps
CPU time 0.89 seconds
Started Jul 30 06:32:51 PM PDT 24
Finished Jul 30 06:32:52 PM PDT 24
Peak memory 206908 kb
Host smart-871c16c7-254e-4f02-a46f-645b0bb8404d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82028
4931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.820284931
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.4166587626
Short name T1679
Test name
Test status
Simulation time 166606797 ps
CPU time 0.85 seconds
Started Jul 30 06:32:57 PM PDT 24
Finished Jul 30 06:32:58 PM PDT 24
Peak memory 206896 kb
Host smart-5539b70c-ce5f-4fe0-af42-10531c32d15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41665
87626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.4166587626
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3368952450
Short name T897
Test name
Test status
Simulation time 181095422 ps
CPU time 0.87 seconds
Started Jul 30 06:32:58 PM PDT 24
Finished Jul 30 06:32:59 PM PDT 24
Peak memory 206920 kb
Host smart-284d644c-2e38-4839-aa1d-a932a8523bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33689
52450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3368952450
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.4017054521
Short name T2523
Test name
Test status
Simulation time 256257169 ps
CPU time 1.07 seconds
Started Jul 30 06:32:52 PM PDT 24
Finished Jul 30 06:32:53 PM PDT 24
Peak memory 206908 kb
Host smart-30cdfbbf-bf06-42b7-8f73-0e50cd57daff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40170
54521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.4017054521
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2402468689
Short name T1533
Test name
Test status
Simulation time 5662684392 ps
CPU time 58.82 seconds
Started Jul 30 06:32:54 PM PDT 24
Finished Jul 30 06:33:53 PM PDT 24
Peak memory 216624 kb
Host smart-c98e3d1c-c880-42bf-8ee4-2b3e63a1482e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2402468689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2402468689
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1806280547
Short name T895
Test name
Test status
Simulation time 167622829 ps
CPU time 0.96 seconds
Started Jul 30 06:32:56 PM PDT 24
Finished Jul 30 06:32:57 PM PDT 24
Peak memory 206908 kb
Host smart-d814bed0-da36-43b8-af32-a996e3242b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18062
80547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1806280547
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1155069542
Short name T1187
Test name
Test status
Simulation time 204303489 ps
CPU time 0.96 seconds
Started Jul 30 06:32:59 PM PDT 24
Finished Jul 30 06:33:00 PM PDT 24
Peak memory 206920 kb
Host smart-e36347e8-4b9c-49a5-8efe-66b411a55fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11550
69542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1155069542
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.3419108614
Short name T2499
Test name
Test status
Simulation time 812825446 ps
CPU time 2.28 seconds
Started Jul 30 06:32:55 PM PDT 24
Finished Jul 30 06:32:57 PM PDT 24
Peak memory 206884 kb
Host smart-ff4a316a-6b5c-44f4-963a-397fc085a4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34191
08614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.3419108614
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1058543003
Short name T2804
Test name
Test status
Simulation time 4783881139 ps
CPU time 46.96 seconds
Started Jul 30 06:32:57 PM PDT 24
Finished Jul 30 06:33:44 PM PDT 24
Peak memory 207196 kb
Host smart-f65ead4f-c8af-4346-bba1-35c840cb9efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10585
43003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1058543003
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.4266986545
Short name T551
Test name
Test status
Simulation time 8393645069 ps
CPU time 55.66 seconds
Started Jul 30 06:32:45 PM PDT 24
Finished Jul 30 06:33:41 PM PDT 24
Peak memory 207128 kb
Host smart-8d45aa3d-f7d1-4d81-9ea4-962156831ca7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266986545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos
t_handshake.4266986545
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.800323532
Short name T1790
Test name
Test status
Simulation time 52209101 ps
CPU time 0.69 seconds
Started Jul 30 06:33:13 PM PDT 24
Finished Jul 30 06:33:14 PM PDT 24
Peak memory 207016 kb
Host smart-c5303457-cb4e-43b4-93dc-2ad710c32d33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=800323532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.800323532
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.892734972
Short name T830
Test name
Test status
Simulation time 3881998186 ps
CPU time 5.6 seconds
Started Jul 30 06:32:58 PM PDT 24
Finished Jul 30 06:33:04 PM PDT 24
Peak memory 207080 kb
Host smart-3553cfa9-c943-4a0b-90c2-24f63d4b1903
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892734972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ao
n_wake_disconnect.892734972
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3164675348
Short name T1660
Test name
Test status
Simulation time 13309289921 ps
CPU time 15.56 seconds
Started Jul 30 06:32:57 PM PDT 24
Finished Jul 30 06:33:12 PM PDT 24
Peak memory 207128 kb
Host smart-357274be-fb59-4167-9c3c-632a98ff9b95
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164675348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3164675348
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.2013423754
Short name T10
Test name
Test status
Simulation time 23360647820 ps
CPU time 32.82 seconds
Started Jul 30 06:32:55 PM PDT 24
Finished Jul 30 06:33:28 PM PDT 24
Peak memory 207128 kb
Host smart-2c5e5558-8759-4402-a911-4e4efa0eae83
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013423754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_resume.2013423754
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.30172634
Short name T833
Test name
Test status
Simulation time 171681615 ps
CPU time 0.96 seconds
Started Jul 30 06:32:54 PM PDT 24
Finished Jul 30 06:32:55 PM PDT 24
Peak memory 206880 kb
Host smart-5a006e53-7657-4824-9e58-3de50378bb93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30172
634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.30172634
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.1981374188
Short name T972
Test name
Test status
Simulation time 155547704 ps
CPU time 0.88 seconds
Started Jul 30 06:32:56 PM PDT 24
Finished Jul 30 06:32:57 PM PDT 24
Peak memory 206888 kb
Host smart-47b5fabd-cd96-48ff-b94c-b2093f0cb64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19813
74188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1981374188
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.3589966555
Short name T735
Test name
Test status
Simulation time 393133106 ps
CPU time 1.36 seconds
Started Jul 30 06:32:55 PM PDT 24
Finished Jul 30 06:32:56 PM PDT 24
Peak memory 206924 kb
Host smart-d3ec3e87-e928-497f-a845-7f62a17c1136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35899
66555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.3589966555
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3404086511
Short name T2815
Test name
Test status
Simulation time 349394261 ps
CPU time 1.21 seconds
Started Jul 30 06:32:59 PM PDT 24
Finished Jul 30 06:33:00 PM PDT 24
Peak memory 206912 kb
Host smart-a1fcebf1-bfb1-4379-9e07-27d40f771179
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3404086511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3404086511
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.1359227664
Short name T82
Test name
Test status
Simulation time 13124549817 ps
CPU time 29.23 seconds
Started Jul 30 06:32:59 PM PDT 24
Finished Jul 30 06:33:28 PM PDT 24
Peak memory 207116 kb
Host smart-ae070bf8-7fe1-47b1-aa14-0f33dcb7514d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13592
27664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.1359227664
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.3615680732
Short name T2022
Test name
Test status
Simulation time 439543086 ps
CPU time 7.9 seconds
Started Jul 30 06:32:59 PM PDT 24
Finished Jul 30 06:33:07 PM PDT 24
Peak memory 207004 kb
Host smart-3d9e8863-8e80-4a69-8ba8-d2135433a328
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615680732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.3615680732
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.311054234
Short name T1895
Test name
Test status
Simulation time 442183025 ps
CPU time 1.47 seconds
Started Jul 30 06:33:00 PM PDT 24
Finished Jul 30 06:33:02 PM PDT 24
Peak memory 206908 kb
Host smart-4c8bf356-1ca8-4ba7-b407-c062e13d724f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31105
4234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.311054234
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3843230592
Short name T746
Test name
Test status
Simulation time 163196534 ps
CPU time 0.84 seconds
Started Jul 30 06:32:58 PM PDT 24
Finished Jul 30 06:32:59 PM PDT 24
Peak memory 206920 kb
Host smart-01cea537-c3e8-417d-aa90-9e36ceed9f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38432
30592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3843230592
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3828423340
Short name T2460
Test name
Test status
Simulation time 33308901 ps
CPU time 0.69 seconds
Started Jul 30 06:32:59 PM PDT 24
Finished Jul 30 06:33:00 PM PDT 24
Peak memory 206888 kb
Host smart-82900773-e449-4200-9b74-8ab18860a92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38284
23340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3828423340
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1700459270
Short name T814
Test name
Test status
Simulation time 783172376 ps
CPU time 2.11 seconds
Started Jul 30 06:32:58 PM PDT 24
Finished Jul 30 06:33:00 PM PDT 24
Peak memory 206992 kb
Host smart-110c934e-18b4-4369-8fd9-a319c75b80e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17004
59270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1700459270
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.258149887
Short name T456
Test name
Test status
Simulation time 198045796 ps
CPU time 2.47 seconds
Started Jul 30 06:32:59 PM PDT 24
Finished Jul 30 06:33:01 PM PDT 24
Peak memory 207012 kb
Host smart-f9994c93-1b94-4ec7-8f5e-1828dd4380aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25814
9887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.258149887
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.565045053
Short name T1978
Test name
Test status
Simulation time 195458856 ps
CPU time 1.01 seconds
Started Jul 30 06:33:06 PM PDT 24
Finished Jul 30 06:33:07 PM PDT 24
Peak memory 207064 kb
Host smart-43407348-efda-4e61-a959-956d807bdb8a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=565045053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.565045053
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.869870270
Short name T1096
Test name
Test status
Simulation time 141976507 ps
CPU time 0.83 seconds
Started Jul 30 06:33:09 PM PDT 24
Finished Jul 30 06:33:10 PM PDT 24
Peak memory 206940 kb
Host smart-d556d24e-d11d-4596-8c76-f4a81d13677f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86987
0270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.869870270
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3045391678
Short name T1240
Test name
Test status
Simulation time 151558186 ps
CPU time 0.89 seconds
Started Jul 30 06:33:04 PM PDT 24
Finished Jul 30 06:33:05 PM PDT 24
Peak memory 206960 kb
Host smart-29e6fba8-8541-4627-89b6-268914c10ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30453
91678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3045391678
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.2121427250
Short name T789
Test name
Test status
Simulation time 9761702251 ps
CPU time 99.43 seconds
Started Jul 30 06:33:06 PM PDT 24
Finished Jul 30 06:34:46 PM PDT 24
Peak memory 215816 kb
Host smart-6d1d1ce7-9da9-473a-944c-1466dad4c6bc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2121427250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.2121427250
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.3718311942
Short name T1768
Test name
Test status
Simulation time 9586637006 ps
CPU time 105.87 seconds
Started Jul 30 06:33:03 PM PDT 24
Finished Jul 30 06:34:49 PM PDT 24
Peak memory 207096 kb
Host smart-448967cd-ecf8-4584-a29c-427a76b0efc3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3718311942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.3718311942
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.495649698
Short name T2209
Test name
Test status
Simulation time 222419415 ps
CPU time 0.98 seconds
Started Jul 30 06:33:05 PM PDT 24
Finished Jul 30 06:33:06 PM PDT 24
Peak memory 206972 kb
Host smart-2362899f-1e39-4a5f-8412-4b79d603b608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49564
9698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.495649698
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.2365435410
Short name T2386
Test name
Test status
Simulation time 23323790211 ps
CPU time 34.74 seconds
Started Jul 30 06:33:04 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 207112 kb
Host smart-32bce652-5099-4c21-a89a-83d92f73e5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23654
35410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.2365435410
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.3751621362
Short name T1318
Test name
Test status
Simulation time 3319251180 ps
CPU time 5.94 seconds
Started Jul 30 06:33:07 PM PDT 24
Finished Jul 30 06:33:13 PM PDT 24
Peak memory 207088 kb
Host smart-751ba4c5-d690-4868-b6ea-61bda8c94900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37516
21362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3751621362
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.2556517980
Short name T2748
Test name
Test status
Simulation time 9847115109 ps
CPU time 100.07 seconds
Started Jul 30 06:33:06 PM PDT 24
Finished Jul 30 06:34:51 PM PDT 24
Peak memory 217460 kb
Host smart-51f4ad71-e99d-4176-82d4-6fa183e1c451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25565
17980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.2556517980
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.203733510
Short name T899
Test name
Test status
Simulation time 6565445806 ps
CPU time 52.63 seconds
Started Jul 30 06:33:06 PM PDT 24
Finished Jul 30 06:33:59 PM PDT 24
Peak memory 206504 kb
Host smart-2451c3ba-c3af-453b-bd10-81ec972b1add
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=203733510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.203733510
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.431676887
Short name T668
Test name
Test status
Simulation time 241435904 ps
CPU time 0.99 seconds
Started Jul 30 06:33:04 PM PDT 24
Finished Jul 30 06:33:06 PM PDT 24
Peak memory 206920 kb
Host smart-00b45aca-b3e0-4a7c-8955-43e7597ad206
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=431676887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.431676887
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.499594418
Short name T1022
Test name
Test status
Simulation time 198141994 ps
CPU time 1 seconds
Started Jul 30 06:33:04 PM PDT 24
Finished Jul 30 06:33:10 PM PDT 24
Peak memory 206948 kb
Host smart-1a4871fe-b6e7-4b83-8edc-5edae6af2b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49959
4418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.499594418
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.745428529
Short name T2188
Test name
Test status
Simulation time 6262948211 ps
CPU time 179.36 seconds
Started Jul 30 06:33:03 PM PDT 24
Finished Jul 30 06:36:03 PM PDT 24
Peak memory 215344 kb
Host smart-8594c5f5-591a-4089-bb8d-0aaa6d63c756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74542
8529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.745428529
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2820858518
Short name T1712
Test name
Test status
Simulation time 4985674255 ps
CPU time 145.87 seconds
Started Jul 30 06:33:04 PM PDT 24
Finished Jul 30 06:35:30 PM PDT 24
Peak memory 215312 kb
Host smart-434ad75d-bcf4-4199-833a-55b697d3cf72
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2820858518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2820858518
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.4059747132
Short name T2437
Test name
Test status
Simulation time 201100624 ps
CPU time 0.96 seconds
Started Jul 30 06:33:05 PM PDT 24
Finished Jul 30 06:33:06 PM PDT 24
Peak memory 206916 kb
Host smart-20e15e65-0760-467d-9b69-c74d6d193bde
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4059747132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.4059747132
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.498787257
Short name T803
Test name
Test status
Simulation time 145938707 ps
CPU time 0.84 seconds
Started Jul 30 06:33:04 PM PDT 24
Finished Jul 30 06:33:05 PM PDT 24
Peak memory 206952 kb
Host smart-38775252-4eed-4305-a7a0-93908c62e009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49878
7257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.498787257
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.395458336
Short name T139
Test name
Test status
Simulation time 214543948 ps
CPU time 1.07 seconds
Started Jul 30 06:33:04 PM PDT 24
Finished Jul 30 06:33:06 PM PDT 24
Peak memory 206904 kb
Host smart-6459e42b-e8e8-4268-bd44-d816fa996d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39545
8336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.395458336
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.3985685296
Short name T2565
Test name
Test status
Simulation time 159784984 ps
CPU time 0.9 seconds
Started Jul 30 06:33:04 PM PDT 24
Finished Jul 30 06:33:05 PM PDT 24
Peak memory 206884 kb
Host smart-eb59392f-0294-4676-8850-cbc430060a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39856
85296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3985685296
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1765282234
Short name T1651
Test name
Test status
Simulation time 159751981 ps
CPU time 0.88 seconds
Started Jul 30 06:33:02 PM PDT 24
Finished Jul 30 06:33:03 PM PDT 24
Peak memory 206908 kb
Host smart-3c230e74-050b-4348-9e25-d8761f9e5ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17652
82234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1765282234
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.453218703
Short name T1056
Test name
Test status
Simulation time 205877178 ps
CPU time 0.98 seconds
Started Jul 30 06:33:03 PM PDT 24
Finished Jul 30 06:33:04 PM PDT 24
Peak memory 206928 kb
Host smart-32842cea-a095-4cbd-b109-9100f442dafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45321
8703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.453218703
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1609421494
Short name T881
Test name
Test status
Simulation time 221684096 ps
CPU time 0.99 seconds
Started Jul 30 06:33:03 PM PDT 24
Finished Jul 30 06:33:05 PM PDT 24
Peak memory 206908 kb
Host smart-44bfa86c-8711-44a8-8918-b61badad6246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16094
21494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1609421494
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.3138207694
Short name T1892
Test name
Test status
Simulation time 269738479 ps
CPU time 1.09 seconds
Started Jul 30 06:33:04 PM PDT 24
Finished Jul 30 06:33:05 PM PDT 24
Peak memory 206924 kb
Host smart-56e54621-f6ad-4f01-914f-6c5429e07ae9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3138207694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.3138207694
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2296989776
Short name T78
Test name
Test status
Simulation time 183016413 ps
CPU time 0.87 seconds
Started Jul 30 06:33:03 PM PDT 24
Finished Jul 30 06:33:04 PM PDT 24
Peak memory 206880 kb
Host smart-043e87d8-8691-42af-a6db-15af2c679dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22969
89776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2296989776
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1743224593
Short name T2549
Test name
Test status
Simulation time 65043703 ps
CPU time 0.73 seconds
Started Jul 30 06:33:09 PM PDT 24
Finished Jul 30 06:33:10 PM PDT 24
Peak memory 206876 kb
Host smart-ec2fcd29-5eb6-4e96-9ed0-b4481119d6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17432
24593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1743224593
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.3410535620
Short name T2247
Test name
Test status
Simulation time 6204037810 ps
CPU time 17.46 seconds
Started Jul 30 06:33:11 PM PDT 24
Finished Jul 30 06:33:29 PM PDT 24
Peak memory 215348 kb
Host smart-7d2ca140-5326-41fa-86a0-a72fce72ecc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34105
35620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.3410535620
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.558720324
Short name T1797
Test name
Test status
Simulation time 197138021 ps
CPU time 0.89 seconds
Started Jul 30 06:33:18 PM PDT 24
Finished Jul 30 06:33:19 PM PDT 24
Peak memory 206928 kb
Host smart-715ea365-79fc-4453-bd8a-2aa27b4013a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55872
0324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.558720324
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2506633862
Short name T2100
Test name
Test status
Simulation time 245309069 ps
CPU time 1.04 seconds
Started Jul 30 06:33:22 PM PDT 24
Finished Jul 30 06:33:23 PM PDT 24
Peak memory 206928 kb
Host smart-4ec6536d-0a0e-426a-89b9-14a8e199e821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25066
33862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2506633862
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.347871517
Short name T1321
Test name
Test status
Simulation time 163783735 ps
CPU time 0.86 seconds
Started Jul 30 06:33:28 PM PDT 24
Finished Jul 30 06:33:29 PM PDT 24
Peak memory 206944 kb
Host smart-59d6bd08-e692-4b26-9f71-7eb375f2ba24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34787
1517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.347871517
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2705664185
Short name T723
Test name
Test status
Simulation time 186840454 ps
CPU time 0.94 seconds
Started Jul 30 06:33:07 PM PDT 24
Finished Jul 30 06:33:08 PM PDT 24
Peak memory 206932 kb
Host smart-eaa59efc-58a7-40bb-b345-5d4818571d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27056
64185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2705664185
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.821664059
Short name T2355
Test name
Test status
Simulation time 190939961 ps
CPU time 0.9 seconds
Started Jul 30 06:33:06 PM PDT 24
Finished Jul 30 06:33:07 PM PDT 24
Peak memory 206924 kb
Host smart-3cf0f4ab-f97d-44e9-9a22-a0e857298e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82166
4059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.821664059
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.94533635
Short name T2782
Test name
Test status
Simulation time 177517334 ps
CPU time 0.89 seconds
Started Jul 30 06:33:13 PM PDT 24
Finished Jul 30 06:33:14 PM PDT 24
Peak memory 206880 kb
Host smart-c4e110fe-1925-48f8-ad86-902d053035fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94533
635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.94533635
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.605071600
Short name T1274
Test name
Test status
Simulation time 150287247 ps
CPU time 0.82 seconds
Started Jul 30 06:33:18 PM PDT 24
Finished Jul 30 06:33:20 PM PDT 24
Peak memory 206908 kb
Host smart-ab26c21c-71b0-43c6-b62d-c972ab3f66d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60507
1600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.605071600
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1162622305
Short name T96
Test name
Test status
Simulation time 229947904 ps
CPU time 1.04 seconds
Started Jul 30 06:33:27 PM PDT 24
Finished Jul 30 06:33:28 PM PDT 24
Peak memory 206912 kb
Host smart-4cc0e407-85b1-4e0a-a0d0-f54977d4ef80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11626
22305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1162622305
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.174477753
Short name T1273
Test name
Test status
Simulation time 3606236758 ps
CPU time 100.8 seconds
Started Jul 30 06:33:19 PM PDT 24
Finished Jul 30 06:35:00 PM PDT 24
Peak memory 215288 kb
Host smart-2476c766-2b89-4d0a-87ba-500cb6b5346a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=174477753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.174477753
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3198644572
Short name T2808
Test name
Test status
Simulation time 206561853 ps
CPU time 0.93 seconds
Started Jul 30 06:33:06 PM PDT 24
Finished Jul 30 06:33:07 PM PDT 24
Peak memory 206888 kb
Host smart-6785b322-f9bd-4ef5-9b71-eac77dbc484f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31986
44572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3198644572
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.3114780693
Short name T1701
Test name
Test status
Simulation time 750368047 ps
CPU time 2.08 seconds
Started Jul 30 06:33:08 PM PDT 24
Finished Jul 30 06:33:10 PM PDT 24
Peak memory 206884 kb
Host smart-dc1655e4-f6a5-4b22-836e-380b4072f9ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31147
80693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.3114780693
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.3208655440
Short name T1414
Test name
Test status
Simulation time 4721866947 ps
CPU time 48.99 seconds
Started Jul 30 06:33:29 PM PDT 24
Finished Jul 30 06:34:18 PM PDT 24
Peak memory 207168 kb
Host smart-6fad7ed5-24ba-4bfd-bc2b-5bef894ddd44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32086
55440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.3208655440
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.878745470
Short name T1873
Test name
Test status
Simulation time 1128224258 ps
CPU time 24.74 seconds
Started Jul 30 06:32:59 PM PDT 24
Finished Jul 30 06:33:24 PM PDT 24
Peak memory 207036 kb
Host smart-609ca7b3-c5fe-4d74-b246-f1281f699e2b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878745470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_host
_handshake.878745470
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.2167072678
Short name T407
Test name
Test status
Simulation time 62090117 ps
CPU time 0.77 seconds
Started Jul 30 06:33:29 PM PDT 24
Finished Jul 30 06:33:30 PM PDT 24
Peak memory 207064 kb
Host smart-315754ac-4d14-426e-8292-3fe04b93b524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2167072678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.2167072678
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2056688102
Short name T2519
Test name
Test status
Simulation time 4085969909 ps
CPU time 6.47 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 207108 kb
Host smart-90477d1b-ea61-46b7-8ab6-2f782aa04119
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056688102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.2056688102
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.1250511281
Short name T1960
Test name
Test status
Simulation time 13369926040 ps
CPU time 14.74 seconds
Started Jul 30 06:33:08 PM PDT 24
Finished Jul 30 06:33:23 PM PDT 24
Peak memory 207184 kb
Host smart-1bdb9411-f0e8-40d3-904b-8af9a28ae735
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250511281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.1250511281
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.1039317050
Short name T2369
Test name
Test status
Simulation time 23438000104 ps
CPU time 33.74 seconds
Started Jul 30 06:33:28 PM PDT 24
Finished Jul 30 06:34:02 PM PDT 24
Peak memory 207264 kb
Host smart-71d677ce-6728-4d36-a1aa-24df28060da2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039317050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.1039317050
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1259469137
Short name T2475
Test name
Test status
Simulation time 164866118 ps
CPU time 0.89 seconds
Started Jul 30 06:33:18 PM PDT 24
Finished Jul 30 06:33:19 PM PDT 24
Peak memory 206956 kb
Host smart-90630f4e-7f3b-4fcd-86c9-716515d9f7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12594
69137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1259469137
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.2702107677
Short name T1339
Test name
Test status
Simulation time 159310956 ps
CPU time 0.87 seconds
Started Jul 30 06:33:07 PM PDT 24
Finished Jul 30 06:33:08 PM PDT 24
Peak memory 206888 kb
Host smart-68352d46-25e9-46ba-b140-2b6010ae491e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27021
07677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.2702107677
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3094910820
Short name T660
Test name
Test status
Simulation time 587789775 ps
CPU time 1.86 seconds
Started Jul 30 06:33:25 PM PDT 24
Finished Jul 30 06:33:27 PM PDT 24
Peak memory 207084 kb
Host smart-b1a78473-dc78-407f-a65d-dbb5392b38af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30949
10820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3094910820
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3279689828
Short name T1212
Test name
Test status
Simulation time 1075485899 ps
CPU time 2.77 seconds
Started Jul 30 06:33:28 PM PDT 24
Finished Jul 30 06:33:31 PM PDT 24
Peak memory 207032 kb
Host smart-b2d53891-47bf-4e35-adc6-b55f959ebc75
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3279689828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3279689828
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.4028904621
Short name T573
Test name
Test status
Simulation time 1527988919 ps
CPU time 13.22 seconds
Started Jul 30 06:33:15 PM PDT 24
Finished Jul 30 06:33:28 PM PDT 24
Peak memory 207040 kb
Host smart-2c87914f-0f26-44cb-841b-719c257492ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028904621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.4028904621
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.353102074
Short name T1107
Test name
Test status
Simulation time 418585696 ps
CPU time 1.41 seconds
Started Jul 30 06:33:12 PM PDT 24
Finished Jul 30 06:33:13 PM PDT 24
Peak memory 206892 kb
Host smart-61972011-5d88-431a-ae04-9729f068c8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35310
2074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.353102074
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1003462346
Short name T1174
Test name
Test status
Simulation time 192319507 ps
CPU time 0.97 seconds
Started Jul 30 06:33:10 PM PDT 24
Finished Jul 30 06:33:16 PM PDT 24
Peak memory 206876 kb
Host smart-43364d90-48cd-40e2-a4eb-a47ffc482f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10034
62346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1003462346
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.2281927824
Short name T2288
Test name
Test status
Simulation time 38656469 ps
CPU time 0.7 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:31 PM PDT 24
Peak memory 206872 kb
Host smart-b1b45a3c-a678-4d6e-b36e-c693998bfe08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22819
27824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2281927824
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.4250900264
Short name T1728
Test name
Test status
Simulation time 816277479 ps
CPU time 2.37 seconds
Started Jul 30 06:33:18 PM PDT 24
Finished Jul 30 06:33:20 PM PDT 24
Peak memory 207048 kb
Host smart-556e2310-2a99-4e95-950e-2283c42cd974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42509
00264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.4250900264
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.4229216047
Short name T1282
Test name
Test status
Simulation time 172851938 ps
CPU time 1.23 seconds
Started Jul 30 06:33:20 PM PDT 24
Finished Jul 30 06:33:21 PM PDT 24
Peak memory 206960 kb
Host smart-5c6b1e48-637a-48cd-9f8a-8699bed891ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42292
16047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.4229216047
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2609524187
Short name T1715
Test name
Test status
Simulation time 227232874 ps
CPU time 1.11 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 207016 kb
Host smart-4600c08f-9b26-426b-a23f-a314e26238b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2609524187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2609524187
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1150393012
Short name T2726
Test name
Test status
Simulation time 139509044 ps
CPU time 0.83 seconds
Started Jul 30 06:33:27 PM PDT 24
Finished Jul 30 06:33:28 PM PDT 24
Peak memory 206884 kb
Host smart-a564f208-eeb1-4337-b8e4-39eb1c0dc51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11503
93012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1150393012
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.640117479
Short name T2432
Test name
Test status
Simulation time 260913910 ps
CPU time 0.99 seconds
Started Jul 30 06:33:24 PM PDT 24
Finished Jul 30 06:33:25 PM PDT 24
Peak memory 206948 kb
Host smart-ac74161f-ae5a-4061-b588-cf470e65afaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64011
7479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.640117479
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.1499112896
Short name T2698
Test name
Test status
Simulation time 10090807556 ps
CPU time 312.87 seconds
Started Jul 30 06:33:26 PM PDT 24
Finished Jul 30 06:38:39 PM PDT 24
Peak memory 215388 kb
Host smart-5f4e1db2-0c11-4243-9bb2-a7d8181f5ab9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1499112896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.1499112896
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.1628432224
Short name T2634
Test name
Test status
Simulation time 8089682410 ps
CPU time 115.26 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 207132 kb
Host smart-6867b492-e6e8-4219-969d-6fe7db5608c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1628432224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.1628432224
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.381217191
Short name T1460
Test name
Test status
Simulation time 247396093 ps
CPU time 1.03 seconds
Started Jul 30 06:33:23 PM PDT 24
Finished Jul 30 06:33:24 PM PDT 24
Peak memory 206912 kb
Host smart-d4766987-9a56-4311-805b-28cec038bf2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38121
7191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.381217191
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.2944525191
Short name T2042
Test name
Test status
Simulation time 23310753666 ps
CPU time 32.76 seconds
Started Jul 30 06:33:28 PM PDT 24
Finished Jul 30 06:34:01 PM PDT 24
Peak memory 207288 kb
Host smart-1427c0ab-bf82-4ff8-b5cd-a46e34a6cc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29445
25191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.2944525191
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.3758823071
Short name T1052
Test name
Test status
Simulation time 3320541282 ps
CPU time 4.98 seconds
Started Jul 30 06:33:27 PM PDT 24
Finished Jul 30 06:33:32 PM PDT 24
Peak memory 207064 kb
Host smart-a00195e5-4b52-40b0-ad4c-5859ff02fd28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37588
23071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3758823071
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.835541147
Short name T552
Test name
Test status
Simulation time 6484339079 ps
CPU time 62.62 seconds
Started Jul 30 06:33:26 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 215372 kb
Host smart-bc7f8c47-de29-48e8-96d6-e810669a8607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83554
1147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.835541147
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3114651744
Short name T1857
Test name
Test status
Simulation time 7229348678 ps
CPU time 210.84 seconds
Started Jul 30 06:33:22 PM PDT 24
Finished Jul 30 06:36:53 PM PDT 24
Peak memory 215316 kb
Host smart-54584c99-9ea5-4452-b556-4952f9a40b7a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3114651744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3114651744
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.3454206249
Short name T2802
Test name
Test status
Simulation time 266074191 ps
CPU time 1.02 seconds
Started Jul 30 06:33:18 PM PDT 24
Finished Jul 30 06:33:19 PM PDT 24
Peak memory 206936 kb
Host smart-e66f9638-79b5-4a12-af38-b8eadc375931
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3454206249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.3454206249
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1613195897
Short name T1554
Test name
Test status
Simulation time 185950317 ps
CPU time 0.95 seconds
Started Jul 30 06:33:26 PM PDT 24
Finished Jul 30 06:33:27 PM PDT 24
Peak memory 206916 kb
Host smart-cb2c8f52-158f-4f1f-b136-c3107a678b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16131
95897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1613195897
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.2588589130
Short name T2118
Test name
Test status
Simulation time 5045791398 ps
CPU time 50.62 seconds
Started Jul 30 06:33:23 PM PDT 24
Finished Jul 30 06:34:14 PM PDT 24
Peak memory 216892 kb
Host smart-df25b985-4715-45b7-a999-0815ab9addc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25885
89130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.2588589130
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1319493724
Short name T2131
Test name
Test status
Simulation time 6072270208 ps
CPU time 61.1 seconds
Started Jul 30 06:33:24 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 207128 kb
Host smart-96c7ad86-46a6-4382-8164-ac7c4d871829
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1319493724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1319493724
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.1650973963
Short name T727
Test name
Test status
Simulation time 186910844 ps
CPU time 0.96 seconds
Started Jul 30 06:33:26 PM PDT 24
Finished Jul 30 06:33:28 PM PDT 24
Peak memory 206920 kb
Host smart-c01af204-1505-40e7-b7ee-21359c74d0f0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1650973963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.1650973963
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2745380958
Short name T2561
Test name
Test status
Simulation time 211879381 ps
CPU time 0.91 seconds
Started Jul 30 06:33:28 PM PDT 24
Finished Jul 30 06:33:29 PM PDT 24
Peak memory 206912 kb
Host smart-6342f623-03a2-4536-9124-9e59ee70445f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27453
80958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2745380958
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2488342024
Short name T1966
Test name
Test status
Simulation time 236057539 ps
CPU time 1.02 seconds
Started Jul 30 06:33:20 PM PDT 24
Finished Jul 30 06:33:21 PM PDT 24
Peak memory 206956 kb
Host smart-15fda2c7-9f92-495f-b033-15e87c4d0b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24883
42024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2488342024
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.199330641
Short name T1260
Test name
Test status
Simulation time 213672187 ps
CPU time 0.95 seconds
Started Jul 30 06:33:27 PM PDT 24
Finished Jul 30 06:33:28 PM PDT 24
Peak memory 206912 kb
Host smart-7a5c73b7-5c3a-4068-9ad4-92b13dc1168c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19933
0641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.199330641
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2723874271
Short name T1033
Test name
Test status
Simulation time 181102910 ps
CPU time 0.88 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:33:32 PM PDT 24
Peak memory 206912 kb
Host smart-6b42bf89-7166-4937-9a8b-42011443edff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27238
74271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2723874271
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.4174940561
Short name T1681
Test name
Test status
Simulation time 179534131 ps
CPU time 0.87 seconds
Started Jul 30 06:33:24 PM PDT 24
Finished Jul 30 06:33:25 PM PDT 24
Peak memory 206912 kb
Host smart-ac2f00ad-4d3d-4596-9a24-362a3635949a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41749
40561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.4174940561
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2612825313
Short name T1738
Test name
Test status
Simulation time 141186223 ps
CPU time 0.86 seconds
Started Jul 30 06:33:18 PM PDT 24
Finished Jul 30 06:33:19 PM PDT 24
Peak memory 206948 kb
Host smart-c3fd3843-85f6-4517-b435-009f59660323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26128
25313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2612825313
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.2929394694
Short name T869
Test name
Test status
Simulation time 272843723 ps
CPU time 1.03 seconds
Started Jul 30 06:33:23 PM PDT 24
Finished Jul 30 06:33:24 PM PDT 24
Peak memory 206952 kb
Host smart-a3040096-8ff4-4a5d-a8da-cd4d67f30867
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2929394694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.2929394694
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1374688048
Short name T2625
Test name
Test status
Simulation time 148885938 ps
CPU time 0.88 seconds
Started Jul 30 06:33:33 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206928 kb
Host smart-56f61d5f-c533-45f9-9ca3-e3bbbf5ad141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13746
88048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1374688048
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3613229800
Short name T1151
Test name
Test status
Simulation time 42074728 ps
CPU time 0.69 seconds
Started Jul 30 06:33:38 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 206884 kb
Host smart-16c69b56-98c3-4deb-b5da-77b08ed978cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36132
29800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3613229800
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3500451684
Short name T2238
Test name
Test status
Simulation time 19182463198 ps
CPU time 52.13 seconds
Started Jul 30 06:33:20 PM PDT 24
Finished Jul 30 06:34:12 PM PDT 24
Peak memory 223532 kb
Host smart-7bcc0f67-a857-46a4-8d69-8e9efa2a6be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35004
51684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3500451684
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3319741202
Short name T751
Test name
Test status
Simulation time 190608022 ps
CPU time 0.91 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:35 PM PDT 24
Peak memory 206916 kb
Host smart-e31b0601-936d-403f-a45a-99203029284d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33197
41202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3319741202
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2989019517
Short name T404
Test name
Test status
Simulation time 211352733 ps
CPU time 0.93 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:32 PM PDT 24
Peak memory 206924 kb
Host smart-387193ce-56bc-4270-8009-eeda3a53befb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29890
19517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2989019517
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.2351636133
Short name T1968
Test name
Test status
Simulation time 214979333 ps
CPU time 1.03 seconds
Started Jul 30 06:33:23 PM PDT 24
Finished Jul 30 06:33:24 PM PDT 24
Peak memory 206904 kb
Host smart-080ea445-cc00-4f37-a1b9-b89ed251274f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23516
36133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.2351636133
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.3656388887
Short name T570
Test name
Test status
Simulation time 199422834 ps
CPU time 0.98 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:31 PM PDT 24
Peak memory 206924 kb
Host smart-3041d724-363b-4f21-8952-1b95056c6c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36563
88887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.3656388887
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3719416344
Short name T1214
Test name
Test status
Simulation time 181026883 ps
CPU time 0.9 seconds
Started Jul 30 06:33:26 PM PDT 24
Finished Jul 30 06:33:27 PM PDT 24
Peak memory 206908 kb
Host smart-98bf0aa8-a8e4-4744-883a-6635a850b1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37194
16344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3719416344
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.4134931972
Short name T2177
Test name
Test status
Simulation time 152840973 ps
CPU time 0.85 seconds
Started Jul 30 06:33:12 PM PDT 24
Finished Jul 30 06:33:13 PM PDT 24
Peak memory 206888 kb
Host smart-0b946e88-0389-43ea-ade8-6f7ec90a14d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41349
31972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.4134931972
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3560555577
Short name T19
Test name
Test status
Simulation time 154841796 ps
CPU time 0.86 seconds
Started Jul 30 06:33:25 PM PDT 24
Finished Jul 30 06:33:26 PM PDT 24
Peak memory 206944 kb
Host smart-28fed3ec-0441-4b24-af70-4c6e70c99eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35605
55577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3560555577
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.143127451
Short name T1021
Test name
Test status
Simulation time 229627718 ps
CPU time 0.97 seconds
Started Jul 30 06:33:26 PM PDT 24
Finished Jul 30 06:33:27 PM PDT 24
Peak memory 206916 kb
Host smart-122294a7-de03-43d2-babf-9c5e01353c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14312
7451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.143127451
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.4126180250
Short name T2763
Test name
Test status
Simulation time 5401349085 ps
CPU time 158.96 seconds
Started Jul 30 06:33:28 PM PDT 24
Finished Jul 30 06:36:07 PM PDT 24
Peak memory 215276 kb
Host smart-f1d2c1ea-6786-408c-8e11-66bfa6c55918
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4126180250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.4126180250
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.4014592904
Short name T1413
Test name
Test status
Simulation time 164874765 ps
CPU time 0.9 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206908 kb
Host smart-90861107-9381-4d0a-905f-db49d8444376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40145
92904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.4014592904
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.42230878
Short name T532
Test name
Test status
Simulation time 168245665 ps
CPU time 0.9 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206904 kb
Host smart-468d0cf2-727e-4cfc-9e57-1e3fbec0f67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42230
878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.42230878
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.2729655822
Short name T449
Test name
Test status
Simulation time 223167457 ps
CPU time 1 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:33:32 PM PDT 24
Peak memory 206852 kb
Host smart-9d680195-e51c-4bfe-a77c-304254cc4205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27296
55822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.2729655822
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.3093303825
Short name T1609
Test name
Test status
Simulation time 4448687746 ps
CPU time 45.14 seconds
Started Jul 30 06:33:28 PM PDT 24
Finished Jul 30 06:34:13 PM PDT 24
Peak memory 216720 kb
Host smart-d9954598-b4aa-4d8f-a8b9-499cc0a7b5a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30933
03825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.3093303825
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.4181707555
Short name T1150
Test name
Test status
Simulation time 2972367617 ps
CPU time 25.13 seconds
Started Jul 30 06:33:08 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 207180 kb
Host smart-19b24ba0-c570-4e05-9a93-3aa7ad12fe88
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181707555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.4181707555
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.479979255
Short name T2674
Test name
Test status
Simulation time 93089361 ps
CPU time 0.72 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 207024 kb
Host smart-4df63dcc-1c77-45e2-86a7-6b3343418f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=479979255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.479979255
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3914473825
Short name T212
Test name
Test status
Simulation time 4181237820 ps
CPU time 5.76 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:41 PM PDT 24
Peak memory 207088 kb
Host smart-a1ec652b-4f59-4d3e-84e8-48fc896521a0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914473825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.3914473825
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.1002135154
Short name T2038
Test name
Test status
Simulation time 13346360937 ps
CPU time 14.34 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:47 PM PDT 24
Peak memory 207160 kb
Host smart-4f82b15f-b1a9-49f2-ba85-fe1887a8edd3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002135154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.1002135154
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.200781364
Short name T1243
Test name
Test status
Simulation time 23458400690 ps
CPU time 27.8 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:34:03 PM PDT 24
Peak memory 207128 kb
Host smart-08c4f77b-0aec-4865-b85d-6aa3f664cfd0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200781364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ao
n_wake_resume.200781364
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3920499897
Short name T370
Test name
Test status
Simulation time 155927195 ps
CPU time 0.91 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:35 PM PDT 24
Peak memory 206912 kb
Host smart-d1ef649a-1a63-4bbb-b3b3-875b797caf39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39204
99897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3920499897
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.854567702
Short name T1258
Test name
Test status
Simulation time 167968049 ps
CPU time 0.82 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 206872 kb
Host smart-f3d7561f-607f-44d3-8856-678a432094cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85456
7702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.854567702
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.1797378310
Short name T480
Test name
Test status
Simulation time 421208265 ps
CPU time 1.6 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:33:32 PM PDT 24
Peak memory 206924 kb
Host smart-ee5a2e53-fea6-4760-947e-53611a80a830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17973
78310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.1797378310
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2766470458
Short name T2773
Test name
Test status
Simulation time 755047953 ps
CPU time 2.06 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206960 kb
Host smart-4cdde5d7-680d-4599-870d-524a9a7f0435
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2766470458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2766470458
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.1618790040
Short name T2468
Test name
Test status
Simulation time 10622484522 ps
CPU time 21.42 seconds
Started Jul 30 06:33:33 PM PDT 24
Finished Jul 30 06:33:55 PM PDT 24
Peak memory 207084 kb
Host smart-9ec24ec4-27e8-4b92-a373-77df842ac8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16187
90040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1618790040
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.2833236142
Short name T1875
Test name
Test status
Simulation time 265231955 ps
CPU time 4.09 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206996 kb
Host smart-6b45af02-4681-42ae-bf63-00bfde6aff63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833236142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.2833236142
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2202931454
Short name T1739
Test name
Test status
Simulation time 392786946 ps
CPU time 1.32 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206892 kb
Host smart-762d6785-8f2b-45df-bb56-ca2c101cd858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22029
31454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2202931454
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2214747045
Short name T860
Test name
Test status
Simulation time 144271664 ps
CPU time 0.83 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 206896 kb
Host smart-539bf29d-9696-4b5b-863a-c1858cdca5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22147
47045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2214747045
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2755988142
Short name T918
Test name
Test status
Simulation time 44380482 ps
CPU time 0.7 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:32 PM PDT 24
Peak memory 206868 kb
Host smart-82b448b7-130e-4ca3-8745-a4de757e7bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27559
88142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2755988142
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.1503659810
Short name T1784
Test name
Test status
Simulation time 762104163 ps
CPU time 2.09 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:32 PM PDT 24
Peak memory 207000 kb
Host smart-03d524cd-9a34-40f8-857f-6b08ee54e66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15036
59810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.1503659810
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1777007068
Short name T680
Test name
Test status
Simulation time 294631331 ps
CPU time 2.43 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 206984 kb
Host smart-de4d32c0-912e-40be-9313-4c45866a539a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17770
07068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1777007068
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.978794120
Short name T87
Test name
Test status
Simulation time 183864992 ps
CPU time 1.02 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:31 PM PDT 24
Peak memory 207020 kb
Host smart-32bb161f-0b55-4ee9-bb25-2e9b4823ffbc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=978794120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.978794120
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.4236928496
Short name T1443
Test name
Test status
Simulation time 148363686 ps
CPU time 0.86 seconds
Started Jul 30 06:33:33 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206888 kb
Host smart-d0ec8ae7-efca-490d-99fc-dbb189d493b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42369
28496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.4236928496
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.80282032
Short name T2430
Test name
Test status
Simulation time 181560120 ps
CPU time 0.9 seconds
Started Jul 30 06:33:28 PM PDT 24
Finished Jul 30 06:33:30 PM PDT 24
Peak memory 206952 kb
Host smart-45a6a851-41fd-40fb-aade-7e33f9458bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80282
032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.80282032
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.2372948265
Short name T1981
Test name
Test status
Simulation time 8828282057 ps
CPU time 249.85 seconds
Started Jul 30 06:33:27 PM PDT 24
Finished Jul 30 06:37:37 PM PDT 24
Peak memory 215316 kb
Host smart-d17396d3-3dd3-427b-a6fe-14aa6103e492
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2372948265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.2372948265
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.1705773091
Short name T501
Test name
Test status
Simulation time 8262420257 ps
CPU time 54.46 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:34:25 PM PDT 24
Peak memory 207120 kb
Host smart-809aaeda-8db8-40cd-a779-ef4768ded3f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1705773091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.1705773091
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.288796305
Short name T930
Test name
Test status
Simulation time 222984980 ps
CPU time 0.95 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:35 PM PDT 24
Peak memory 206900 kb
Host smart-01e0d7f1-8544-4d1a-b049-e04fbe70c8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28879
6305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.288796305
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.1762360061
Short name T531
Test name
Test status
Simulation time 23335851207 ps
CPU time 27.27 seconds
Started Jul 30 06:33:29 PM PDT 24
Finished Jul 30 06:33:57 PM PDT 24
Peak memory 207104 kb
Host smart-7014da7a-c3cd-43e9-a359-685a1276b73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17623
60061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1762360061
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2823767583
Short name T1920
Test name
Test status
Simulation time 3286753652 ps
CPU time 5.3 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:35 PM PDT 24
Peak memory 207060 kb
Host smart-86883eba-f2cf-41b8-a874-e1b565b27d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28237
67583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2823767583
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.1371180065
Short name T568
Test name
Test status
Simulation time 7215969654 ps
CPU time 53.08 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 217188 kb
Host smart-a545e1c9-b5a8-41e7-a8ba-07f1ae58f999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13711
80065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.1371180065
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.2477517657
Short name T1507
Test name
Test status
Simulation time 4844749013 ps
CPU time 40.65 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:34:18 PM PDT 24
Peak memory 216520 kb
Host smart-01d09b34-fe49-4c67-88fe-2939dcdb03ff
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2477517657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.2477517657
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1428953051
Short name T2754
Test name
Test status
Simulation time 247593507 ps
CPU time 1.08 seconds
Started Jul 30 06:33:23 PM PDT 24
Finished Jul 30 06:33:25 PM PDT 24
Peak memory 206944 kb
Host smart-53bf7f2e-b79e-499c-b587-7c8a9bc6482b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1428953051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1428953051
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1118238332
Short name T1623
Test name
Test status
Simulation time 190683072 ps
CPU time 0.94 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206900 kb
Host smart-2eb9f48a-f36b-471f-807a-bb4c6e71e353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11182
38332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1118238332
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.3962620992
Short name T1986
Test name
Test status
Simulation time 3350931976 ps
CPU time 25.31 seconds
Started Jul 30 06:33:29 PM PDT 24
Finished Jul 30 06:33:55 PM PDT 24
Peak memory 216652 kb
Host smart-949ebb72-ea2d-426e-802f-308c1f85460a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39626
20992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.3962620992
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.3703812214
Short name T2064
Test name
Test status
Simulation time 6401784607 ps
CPU time 48.02 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 207112 kb
Host smart-e85198e1-f315-4f92-8c38-8390d2fcef74
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3703812214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.3703812214
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1732991138
Short name T1407
Test name
Test status
Simulation time 154159278 ps
CPU time 0.87 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 206952 kb
Host smart-c315d606-9274-4f9f-8907-f862d37d1bc0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1732991138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1732991138
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.217600788
Short name T1364
Test name
Test status
Simulation time 163571218 ps
CPU time 0.87 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206908 kb
Host smart-8be5f6e8-890b-4d3c-874d-2c812e375468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21760
0788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.217600788
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.556508043
Short name T112
Test name
Test status
Simulation time 195739476 ps
CPU time 0.88 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 206924 kb
Host smart-76d8a51f-5dfd-4867-91ca-fd6db7e28b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55650
8043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.556508043
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2852156672
Short name T93
Test name
Test status
Simulation time 183853157 ps
CPU time 0.94 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:33:32 PM PDT 24
Peak memory 206928 kb
Host smart-3a8a0f00-0a15-4e3d-a5c3-8813936f9929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28521
56672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2852156672
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.793021808
Short name T2506
Test name
Test status
Simulation time 208638960 ps
CPU time 0.91 seconds
Started Jul 30 06:33:22 PM PDT 24
Finished Jul 30 06:33:23 PM PDT 24
Peak memory 206948 kb
Host smart-dccdb2eb-d7b2-48f6-bfc3-ac570bf0a966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79302
1808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.793021808
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3428054705
Short name T2530
Test name
Test status
Simulation time 154996131 ps
CPU time 0.86 seconds
Started Jul 30 06:33:27 PM PDT 24
Finished Jul 30 06:33:28 PM PDT 24
Peak memory 206908 kb
Host smart-079fee6e-8603-4f21-b997-148f59084b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34280
54705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3428054705
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1833239833
Short name T2448
Test name
Test status
Simulation time 156155725 ps
CPU time 0.88 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:35 PM PDT 24
Peak memory 206912 kb
Host smart-611388a8-4903-4fa8-b5a8-2f60f5fbce23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18332
39833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1833239833
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.2099345908
Short name T1612
Test name
Test status
Simulation time 239796160 ps
CPU time 1.07 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 206924 kb
Host smart-658aedc1-2c23-4c5f-b244-b95d8011143f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2099345908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.2099345908
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.4274017943
Short name T2691
Test name
Test status
Simulation time 148044600 ps
CPU time 0.82 seconds
Started Jul 30 06:33:29 PM PDT 24
Finished Jul 30 06:33:30 PM PDT 24
Peak memory 206888 kb
Host smart-6ec5a356-e19b-46d6-90ff-4e83fdae45f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42740
17943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.4274017943
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2708882164
Short name T2776
Test name
Test status
Simulation time 78218437 ps
CPU time 0.76 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:33:32 PM PDT 24
Peak memory 206880 kb
Host smart-c932dc20-7a5a-45b1-8cbe-31e7747f3546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27088
82164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2708882164
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.898367229
Short name T484
Test name
Test status
Simulation time 6356427485 ps
CPU time 16.21 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:46 PM PDT 24
Peak memory 215328 kb
Host smart-8f8dbfaa-4530-48d1-9742-f384783f20bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89836
7229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.898367229
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.784233565
Short name T728
Test name
Test status
Simulation time 235566402 ps
CPU time 0.95 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206904 kb
Host smart-e062e731-fc88-43c8-b0a0-d1b4ddd9536c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78423
3565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.784233565
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.4111625421
Short name T2525
Test name
Test status
Simulation time 186533590 ps
CPU time 0.87 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:33:32 PM PDT 24
Peak memory 206908 kb
Host smart-bb97efe7-3525-457c-ba66-bc314f1cc898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41116
25421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.4111625421
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2637085679
Short name T2309
Test name
Test status
Simulation time 191411652 ps
CPU time 0.94 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 206904 kb
Host smart-e45554b1-b5a0-482c-9b0c-1425af40e5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26370
85679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2637085679
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.263538725
Short name T1635
Test name
Test status
Simulation time 172417796 ps
CPU time 0.93 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:31 PM PDT 24
Peak memory 206904 kb
Host smart-34ee4a97-d9c0-48d4-98fd-99317e8cec5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26353
8725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.263538725
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.1017018817
Short name T1769
Test name
Test status
Simulation time 143555520 ps
CPU time 0.82 seconds
Started Jul 30 06:33:26 PM PDT 24
Finished Jul 30 06:33:27 PM PDT 24
Peak memory 206888 kb
Host smart-4fb2421c-851c-447b-b17c-b60374b5ad14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10170
18817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1017018817
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.256199376
Short name T2661
Test name
Test status
Simulation time 151629038 ps
CPU time 0.84 seconds
Started Jul 30 06:33:27 PM PDT 24
Finished Jul 30 06:33:28 PM PDT 24
Peak memory 206872 kb
Host smart-17453d9e-b1d9-4c51-9bce-210a782f2f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25619
9376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.256199376
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1270118131
Short name T1314
Test name
Test status
Simulation time 155563224 ps
CPU time 0.92 seconds
Started Jul 30 06:33:33 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206920 kb
Host smart-07f285e3-44d5-493d-b33f-9e0fdbf5db73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12701
18131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1270118131
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2548794160
Short name T1780
Test name
Test status
Simulation time 209310568 ps
CPU time 1.04 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206896 kb
Host smart-eab10307-9f5c-4eed-a785-0686ddbd2bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25487
94160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2548794160
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.4027470057
Short name T1911
Test name
Test status
Simulation time 5406255836 ps
CPU time 44.87 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:34:15 PM PDT 24
Peak memory 215360 kb
Host smart-8d0e6a50-1266-4e84-8cf1-77a1aad9e0e5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4027470057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.4027470057
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.135949113
Short name T2848
Test name
Test status
Simulation time 181765575 ps
CPU time 0.95 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 206988 kb
Host smart-81673ea3-4e10-49de-a749-c8519303b8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13594
9113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.135949113
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1924921207
Short name T2375
Test name
Test status
Simulation time 197115796 ps
CPU time 0.93 seconds
Started Jul 30 06:33:20 PM PDT 24
Finished Jul 30 06:33:21 PM PDT 24
Peak memory 206908 kb
Host smart-754d7f02-ca1a-44a7-85e4-7793a7d31f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19249
21207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1924921207
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.2794699297
Short name T859
Test name
Test status
Simulation time 782367786 ps
CPU time 2.22 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:40 PM PDT 24
Peak memory 206880 kb
Host smart-69f2b762-7416-4b18-b842-48a5a9603832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27946
99297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.2794699297
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.849374439
Short name T2759
Test name
Test status
Simulation time 6006431635 ps
CPU time 168.08 seconds
Started Jul 30 06:33:25 PM PDT 24
Finished Jul 30 06:36:13 PM PDT 24
Peak memory 215448 kb
Host smart-71368704-85bf-42c2-89cd-a0a1f70e2e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84937
4439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.849374439
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.1315417960
Short name T328
Test name
Test status
Simulation time 1029999578 ps
CPU time 22.34 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:54 PM PDT 24
Peak memory 207148 kb
Host smart-d516c8dc-a22c-485b-b3ad-7a393cd6a854
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315417960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_hos
t_handshake.1315417960
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.2681042365
Short name T1874
Test name
Test status
Simulation time 104117494 ps
CPU time 0.7 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:36 PM PDT 24
Peak memory 207056 kb
Host smart-d4bca054-4751-4fb0-8030-973d2aac038f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2681042365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.2681042365
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2296653912
Short name T686
Test name
Test status
Simulation time 3547183849 ps
CPU time 5.05 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:35 PM PDT 24
Peak memory 207088 kb
Host smart-20086294-5e3e-432c-ae47-205cfa6d91be
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296653912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.2296653912
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.2339594693
Short name T2842
Test name
Test status
Simulation time 13547358427 ps
CPU time 15.77 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:53 PM PDT 24
Peak memory 207132 kb
Host smart-5da7ead5-b270-4c64-81d0-d90f8687064e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339594693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.2339594693
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.3084470856
Short name T2707
Test name
Test status
Simulation time 23340757994 ps
CPU time 25.75 seconds
Started Jul 30 06:33:25 PM PDT 24
Finished Jul 30 06:33:51 PM PDT 24
Peak memory 207156 kb
Host smart-ac8aed9a-fc35-48b9-8a4b-0c8ff45e6682
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084470856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_resume.3084470856
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3160420045
Short name T1292
Test name
Test status
Simulation time 177422752 ps
CPU time 0.85 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206956 kb
Host smart-2c9e7c64-4b39-425c-a40e-61426c7a0763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31604
20045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3160420045
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.3655633750
Short name T1700
Test name
Test status
Simulation time 418068592 ps
CPU time 1.53 seconds
Started Jul 30 06:33:29 PM PDT 24
Finished Jul 30 06:33:31 PM PDT 24
Peak memory 206916 kb
Host smart-5610a9e7-fddd-4e4b-9a23-fcc64990bdb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36556
33750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.3655633750
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3955883431
Short name T444
Test name
Test status
Simulation time 559385922 ps
CPU time 1.67 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 206916 kb
Host smart-2ae7ac9f-d4b5-47bd-a8ae-257ee6f4fd69
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3955883431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3955883431
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.971320900
Short name T167
Test name
Test status
Simulation time 10716208467 ps
CPU time 24.68 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:59 PM PDT 24
Peak memory 207184 kb
Host smart-634454f1-5466-41c8-8b06-11eeeee8c8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97132
0900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.971320900
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.3042899577
Short name T650
Test name
Test status
Simulation time 1813768056 ps
CPU time 44.31 seconds
Started Jul 30 06:33:33 PM PDT 24
Finished Jul 30 06:34:18 PM PDT 24
Peak memory 206992 kb
Host smart-c27a5e84-97be-4f39-a503-c75a6c038dbc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042899577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.3042899577
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.1415796049
Short name T2153
Test name
Test status
Simulation time 390779276 ps
CPU time 1.48 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 206944 kb
Host smart-71c74156-cae4-4c56-9334-3fa5d11d9d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14157
96049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.1415796049
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.515566571
Short name T1496
Test name
Test status
Simulation time 162360288 ps
CPU time 0.84 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:35 PM PDT 24
Peak memory 206952 kb
Host smart-1178441a-d04e-44d1-aeba-4bfc59c5057f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51556
6571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.515566571
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.229877537
Short name T1878
Test name
Test status
Simulation time 52306590 ps
CPU time 0.74 seconds
Started Jul 30 06:33:28 PM PDT 24
Finished Jul 30 06:33:29 PM PDT 24
Peak memory 206868 kb
Host smart-e3d31027-eabf-4f42-8a5f-424412316bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22987
7537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.229877537
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.873034675
Short name T2232
Test name
Test status
Simulation time 719022914 ps
CPU time 2.22 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 207024 kb
Host smart-a3f7c23c-ea7b-41eb-8d7d-2585eea6c679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87303
4675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.873034675
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3711211121
Short name T2391
Test name
Test status
Simulation time 267236136 ps
CPU time 2.09 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 206956 kb
Host smart-1050ae75-ef93-4f38-9f55-14df4b334731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37112
11121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3711211121
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2293107760
Short name T460
Test name
Test status
Simulation time 230400876 ps
CPU time 1.17 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 207024 kb
Host smart-8078e951-2dc2-40dc-be48-ff25e8fe51be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2293107760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2293107760
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.846893808
Short name T324
Test name
Test status
Simulation time 212881262 ps
CPU time 0.96 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:33:32 PM PDT 24
Peak memory 206916 kb
Host smart-1ae6109a-144d-46a8-be01-4e925dd56fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84689
3808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.846893808
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.578131142
Short name T1655
Test name
Test status
Simulation time 190947288 ps
CPU time 0.96 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206936 kb
Host smart-23d8a40b-a946-4908-9b94-e62c4fb87620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57813
1142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.578131142
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.1181595063
Short name T990
Test name
Test status
Simulation time 9320188332 ps
CPU time 273 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:38:09 PM PDT 24
Peak memory 215316 kb
Host smart-9f38e865-94f8-415a-9c8e-0e49cc022f48
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1181595063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.1181595063
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.110063977
Short name T2043
Test name
Test status
Simulation time 13498912312 ps
CPU time 90.06 seconds
Started Jul 30 06:33:38 PM PDT 24
Finished Jul 30 06:35:08 PM PDT 24
Peak memory 207088 kb
Host smart-cbe6b8c0-2b78-4087-8da8-3533ea15847a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=110063977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.110063977
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.1848169695
Short name T2325
Test name
Test status
Simulation time 162577704 ps
CPU time 0.85 seconds
Started Jul 30 06:33:33 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206952 kb
Host smart-f7af9ede-cedc-4a1e-b272-0c5adfde9bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18481
69695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1848169695
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1862433251
Short name T1331
Test name
Test status
Simulation time 23338612974 ps
CPU time 27.09 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:34:03 PM PDT 24
Peak memory 207128 kb
Host smart-3fff59a7-25f8-4831-b954-330fc18c1b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18624
33251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1862433251
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.4016045620
Short name T1762
Test name
Test status
Simulation time 3326689939 ps
CPU time 5.74 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:43 PM PDT 24
Peak memory 207124 kb
Host smart-5bc172f6-9b2e-400d-af21-3cfee9330ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40160
45620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.4016045620
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.2406167874
Short name T305
Test name
Test status
Simulation time 8980230967 ps
CPU time 263.44 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:37:58 PM PDT 24
Peak memory 215384 kb
Host smart-24aa9747-78b7-4c2d-aa0a-8d94ecfc6e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24061
67874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2406167874
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2121898503
Short name T1659
Test name
Test status
Simulation time 5451389637 ps
CPU time 40.54 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:34:18 PM PDT 24
Peak memory 207156 kb
Host smart-b9d63dd1-a987-4629-b089-8787be4cc658
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2121898503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2121898503
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.2350561340
Short name T2017
Test name
Test status
Simulation time 250484011 ps
CPU time 1.01 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:36 PM PDT 24
Peak memory 206940 kb
Host smart-b2513a01-afc5-475c-8816-246ad831fe8f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2350561340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.2350561340
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1668671521
Short name T2069
Test name
Test status
Simulation time 186782383 ps
CPU time 0.89 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:31 PM PDT 24
Peak memory 206920 kb
Host smart-edeb421d-562a-4ca7-aebb-810eb2c46dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16686
71521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1668671521
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1058137026
Short name T2159
Test name
Test status
Simulation time 3566072020 ps
CPU time 102.91 seconds
Started Jul 30 06:33:33 PM PDT 24
Finished Jul 30 06:35:16 PM PDT 24
Peak memory 215296 kb
Host smart-1c045429-12b3-417e-b1a2-ca77b2f02a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10581
37026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1058137026
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2732935209
Short name T1186
Test name
Test status
Simulation time 4875225787 ps
CPU time 48.4 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 216820 kb
Host smart-d8fdcff9-fd46-4b9a-8d8d-7441385bd719
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2732935209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2732935209
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.3997011123
Short name T1676
Test name
Test status
Simulation time 214884211 ps
CPU time 0.89 seconds
Started Jul 30 06:33:28 PM PDT 24
Finished Jul 30 06:33:30 PM PDT 24
Peak memory 206952 kb
Host smart-d550c877-dd5d-4abd-ad20-b9a26f838cbf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3997011123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.3997011123
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.279186375
Short name T697
Test name
Test status
Simulation time 158669510 ps
CPU time 0.85 seconds
Started Jul 30 06:33:39 PM PDT 24
Finished Jul 30 06:33:40 PM PDT 24
Peak memory 206940 kb
Host smart-1eab4078-c1d4-411d-abab-49117de499ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27918
6375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.279186375
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2068278828
Short name T131
Test name
Test status
Simulation time 219444020 ps
CPU time 0.98 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 206984 kb
Host smart-4f9e14e2-a55c-4b84-a537-1fd084002c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20682
78828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2068278828
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2572598947
Short name T1758
Test name
Test status
Simulation time 153210099 ps
CPU time 0.83 seconds
Started Jul 30 06:33:29 PM PDT 24
Finished Jul 30 06:33:30 PM PDT 24
Peak memory 206976 kb
Host smart-f1e99b93-4e92-485d-9725-bd3d86983a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25725
98947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2572598947
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3453893245
Short name T1018
Test name
Test status
Simulation time 195837436 ps
CPU time 0.97 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:36 PM PDT 24
Peak memory 206908 kb
Host smart-fb28d1ed-ad15-4759-9405-624fddc86663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34538
93245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3453893245
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.766674666
Short name T2593
Test name
Test status
Simulation time 179797033 ps
CPU time 0.9 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206988 kb
Host smart-d723b2c6-97e6-4d99-9c4a-94f184721957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76667
4666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.766674666
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2156473990
Short name T963
Test name
Test status
Simulation time 153862439 ps
CPU time 0.87 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206944 kb
Host smart-208950a8-c635-437b-b243-de2edff161dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21564
73990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2156473990
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.3098798234
Short name T982
Test name
Test status
Simulation time 206055810 ps
CPU time 1.01 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:36 PM PDT 24
Peak memory 206924 kb
Host smart-030ec358-49e5-4917-a629-fb4243b48caf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3098798234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.3098798234
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.347046793
Short name T1351
Test name
Test status
Simulation time 154256779 ps
CPU time 0.83 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:36 PM PDT 24
Peak memory 206952 kb
Host smart-972632bd-2abb-461c-a79c-e82be73bc26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34704
6793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.347046793
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1499522684
Short name T1578
Test name
Test status
Simulation time 42935175 ps
CPU time 0.69 seconds
Started Jul 30 06:33:33 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206872 kb
Host smart-072ca649-5076-485d-b00d-0c61e0f587de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14995
22684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1499522684
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1651969163
Short name T1696
Test name
Test status
Simulation time 21719607881 ps
CPU time 56.3 seconds
Started Jul 30 06:33:38 PM PDT 24
Finished Jul 30 06:34:34 PM PDT 24
Peak memory 215312 kb
Host smart-810e3164-fffd-421b-840a-b6d6bd82b57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16519
69163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1651969163
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.141217529
Short name T757
Test name
Test status
Simulation time 190041548 ps
CPU time 0.95 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:33:31 PM PDT 24
Peak memory 206924 kb
Host smart-bd5b7dc4-9d83-4432-9491-a2a3f767aea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14121
7529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.141217529
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1066588381
Short name T1379
Test name
Test status
Simulation time 200024626 ps
CPU time 0.96 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 206888 kb
Host smart-1847337a-26f5-4a72-ba63-fad39f97da63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10665
88381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1066588381
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.1205267394
Short name T2282
Test name
Test status
Simulation time 245207667 ps
CPU time 0.94 seconds
Started Jul 30 06:33:39 PM PDT 24
Finished Jul 30 06:33:40 PM PDT 24
Peak memory 206936 kb
Host smart-ffb74a82-3dc8-4f93-86cc-9a0754404bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12052
67394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.1205267394
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.1915361790
Short name T1745
Test name
Test status
Simulation time 165102850 ps
CPU time 0.9 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:35 PM PDT 24
Peak memory 206912 kb
Host smart-123c629c-783a-41f4-b25b-5a977e362fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19153
61790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1915361790
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3440424094
Short name T2125
Test name
Test status
Simulation time 140087829 ps
CPU time 0.81 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 206880 kb
Host smart-4c696db6-c7ab-407d-9ffb-cf5b17c7e345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34404
24094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3440424094
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.407451930
Short name T366
Test name
Test status
Simulation time 151620605 ps
CPU time 0.87 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206880 kb
Host smart-1ad24089-0dc7-4f27-8d27-777213dbb77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40745
1930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.407451930
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.4213088470
Short name T2008
Test name
Test status
Simulation time 150497820 ps
CPU time 0.84 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206916 kb
Host smart-8c7d856d-95db-45a5-bbec-bcc0afe64807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42130
88470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.4213088470
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2760180123
Short name T1493
Test name
Test status
Simulation time 223166225 ps
CPU time 1.02 seconds
Started Jul 30 06:33:39 PM PDT 24
Finished Jul 30 06:33:40 PM PDT 24
Peak memory 206980 kb
Host smart-b86a7d11-b5a0-4e0b-bd25-a94c96943682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27601
80123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2760180123
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.404665062
Short name T1604
Test name
Test status
Simulation time 3500018794 ps
CPU time 98.28 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:35:14 PM PDT 24
Peak memory 215348 kb
Host smart-3cdaa15d-e79b-4d35-aebb-10d06af24000
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=404665062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.404665062
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1132676110
Short name T2315
Test name
Test status
Simulation time 180437188 ps
CPU time 0.86 seconds
Started Jul 30 06:33:40 PM PDT 24
Finished Jul 30 06:33:41 PM PDT 24
Peak memory 206824 kb
Host smart-ffa2941a-3a8b-458a-8ce9-ffd3dae2267b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11326
76110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1132676110
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2633233900
Short name T670
Test name
Test status
Simulation time 173610162 ps
CPU time 0.83 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:36 PM PDT 24
Peak memory 206980 kb
Host smart-d2a567b6-3000-4090-a0fc-54a369fa8432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26332
33900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2633233900
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.4083275894
Short name T712
Test name
Test status
Simulation time 594130227 ps
CPU time 1.6 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206880 kb
Host smart-9f679062-8ad4-4e96-a7f8-ff315de6c6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40832
75894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.4083275894
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.1534841869
Short name T2839
Test name
Test status
Simulation time 4933956464 ps
CPU time 144.06 seconds
Started Jul 30 06:33:32 PM PDT 24
Finished Jul 30 06:35:56 PM PDT 24
Peak memory 215300 kb
Host smart-b414db1f-a251-4d81-84af-87b7e32ac3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15348
41869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.1534841869
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.2017052010
Short name T356
Test name
Test status
Simulation time 300871917 ps
CPU time 4.6 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:41 PM PDT 24
Peak memory 206980 kb
Host smart-10e30141-0ed8-4978-96b8-c3a1692a97e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017052010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.2017052010
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.332730667
Short name T696
Test name
Test status
Simulation time 42211025 ps
CPU time 0.67 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 207004 kb
Host smart-69c32f03-37b1-4777-9aaf-98ae09d75e3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=332730667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.332730667
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1769124312
Short name T2014
Test name
Test status
Simulation time 4105929633 ps
CPU time 5.54 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:43 PM PDT 24
Peak memory 207128 kb
Host smart-1a4622e8-c9aa-4dd5-9ea4-6e3b5f650f7c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769124312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.1769124312
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3346000609
Short name T1839
Test name
Test status
Simulation time 13365929418 ps
CPU time 16.27 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:53 PM PDT 24
Peak memory 207152 kb
Host smart-46a4d719-510c-4a51-aada-ab7b94fe6cec
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346000609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3346000609
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.4041465626
Short name T689
Test name
Test status
Simulation time 23462202113 ps
CPU time 33.91 seconds
Started Jul 30 06:33:30 PM PDT 24
Finished Jul 30 06:34:04 PM PDT 24
Peak memory 207136 kb
Host smart-a812f181-3fa5-4b77-a668-fdc62a31e91e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041465626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.4041465626
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1596244093
Short name T84
Test name
Test status
Simulation time 148022667 ps
CPU time 0.82 seconds
Started Jul 30 06:33:41 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 206984 kb
Host smart-da8778a1-8d53-41f7-9041-8fcb4bdccd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15962
44093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1596244093
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.3150246926
Short name T1348
Test name
Test status
Simulation time 144385617 ps
CPU time 0.85 seconds
Started Jul 30 06:33:33 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206880 kb
Host smart-20d86d36-6567-49bb-be48-a46d1c1a494d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31502
46926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.3150246926
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1431212909
Short name T445
Test name
Test status
Simulation time 487174745 ps
CPU time 1.72 seconds
Started Jul 30 06:33:39 PM PDT 24
Finished Jul 30 06:33:41 PM PDT 24
Peak memory 206900 kb
Host smart-eacdd654-471b-452a-8cf7-97257e8027f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14312
12909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1431212909
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.161693381
Short name T2687
Test name
Test status
Simulation time 443027155 ps
CPU time 1.43 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206940 kb
Host smart-90bee88e-2407-4590-9d08-e1bc6c1f69f1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=161693381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.161693381
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.1013533647
Short name T2324
Test name
Test status
Simulation time 1352672739 ps
CPU time 8.98 seconds
Started Jul 30 06:33:38 PM PDT 24
Finished Jul 30 06:33:48 PM PDT 24
Peak memory 207132 kb
Host smart-6b8a5d1b-b28b-40dc-8695-7ead9534e572
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013533647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.1013533647
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1674477137
Short name T2648
Test name
Test status
Simulation time 499704288 ps
CPU time 1.67 seconds
Started Jul 30 06:33:39 PM PDT 24
Finished Jul 30 06:33:41 PM PDT 24
Peak memory 206880 kb
Host smart-9e7e0f14-5fce-4dbb-9c0e-d109014c15c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16744
77137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1674477137
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3189884151
Short name T1792
Test name
Test status
Simulation time 140214140 ps
CPU time 0.82 seconds
Started Jul 30 06:33:39 PM PDT 24
Finished Jul 30 06:33:40 PM PDT 24
Peak memory 206892 kb
Host smart-986b6e18-d4e2-47f8-8619-23f760017350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31898
84151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3189884151
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.424299525
Short name T517
Test name
Test status
Simulation time 46751153 ps
CPU time 0.71 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206868 kb
Host smart-0f069002-c1bf-4383-9113-7daa3be46126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42429
9525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.424299525
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.2928540280
Short name T1518
Test name
Test status
Simulation time 988429201 ps
CPU time 2.76 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:40 PM PDT 24
Peak memory 207092 kb
Host smart-c7dc7b7b-55d3-412b-80bd-6b9ff42ff355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29285
40280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.2928540280
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.228274918
Short name T423
Test name
Test status
Simulation time 359866004 ps
CPU time 2.41 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 207072 kb
Host smart-3ed0c0da-8880-46a7-8cc1-722a1cf7c705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22827
4918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.228274918
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.887084643
Short name T1934
Test name
Test status
Simulation time 234082915 ps
CPU time 1.19 seconds
Started Jul 30 06:33:41 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 215212 kb
Host smart-b9725dc2-36c3-4dd0-b380-d0d6d80d36a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=887084643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.887084643
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.4183606932
Short name T2281
Test name
Test status
Simulation time 134338449 ps
CPU time 0.82 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:36 PM PDT 24
Peak memory 206880 kb
Host smart-3288f6be-7a8c-4ab1-a0e7-a47441e3dd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41836
06932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.4183606932
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2785969493
Short name T576
Test name
Test status
Simulation time 194792141 ps
CPU time 0.96 seconds
Started Jul 30 06:33:33 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206956 kb
Host smart-c7c0d468-d919-4b30-8ee0-55ac60f35515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27859
69493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2785969493
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.396642208
Short name T900
Test name
Test status
Simulation time 8618425109 ps
CPU time 90.72 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:35:05 PM PDT 24
Peak memory 216484 kb
Host smart-797475ba-7509-4a11-8f38-b1428f89e046
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=396642208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.396642208
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.1844303898
Short name T2084
Test name
Test status
Simulation time 4158879618 ps
CPU time 52.15 seconds
Started Jul 30 06:33:38 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 207100 kb
Host smart-95aa63b4-97a7-49fd-af8e-78b9a30f7d1f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1844303898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.1844303898
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.572308057
Short name T1887
Test name
Test status
Simulation time 173724053 ps
CPU time 0.85 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 206960 kb
Host smart-3f75d54f-a874-4d40-8b4d-27492ca39548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57230
8057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.572308057
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.2845701169
Short name T2107
Test name
Test status
Simulation time 23277102619 ps
CPU time 31.44 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:34:08 PM PDT 24
Peak memory 207084 kb
Host smart-dfe2f23c-0d01-4dd7-a964-2ab36d3400ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28457
01169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.2845701169
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.4138363516
Short name T2146
Test name
Test status
Simulation time 3309849656 ps
CPU time 4.89 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 207052 kb
Host smart-0badafaf-cf65-4d3f-bae0-0b3a3a3180ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41383
63516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.4138363516
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2599641781
Short name T2495
Test name
Test status
Simulation time 5668858780 ps
CPU time 168.86 seconds
Started Jul 30 06:33:33 PM PDT 24
Finished Jul 30 06:36:22 PM PDT 24
Peak memory 215364 kb
Host smart-49b5f2c4-51fc-4380-96ea-cf8d99e28bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25996
41781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2599641781
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.1045256999
Short name T382
Test name
Test status
Simulation time 5716206646 ps
CPU time 57.49 seconds
Started Jul 30 06:33:40 PM PDT 24
Finished Jul 30 06:34:38 PM PDT 24
Peak memory 216780 kb
Host smart-a818cb10-06bd-42fd-80bc-d8495d5c4f70
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1045256999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.1045256999
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.131341851
Short name T2151
Test name
Test status
Simulation time 238702199 ps
CPU time 1.06 seconds
Started Jul 30 06:33:40 PM PDT 24
Finished Jul 30 06:33:41 PM PDT 24
Peak memory 206860 kb
Host smart-1759a20d-f412-4766-93ed-54999652b09a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=131341851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.131341851
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1407456162
Short name T961
Test name
Test status
Simulation time 192367100 ps
CPU time 1 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206924 kb
Host smart-9328910c-3117-4c38-8bbb-902f37b03e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14074
56162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1407456162
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.4255168943
Short name T1497
Test name
Test status
Simulation time 6173647151 ps
CPU time 181.88 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:36:36 PM PDT 24
Peak memory 215284 kb
Host smart-b7288ba1-c17f-4945-98c6-e2019766e1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42551
68943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.4255168943
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3307800984
Short name T781
Test name
Test status
Simulation time 3298649437 ps
CPU time 93.49 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:35:10 PM PDT 24
Peak memory 215348 kb
Host smart-9bd2e85b-4892-4bd5-91d5-be9d3e08607a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3307800984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3307800984
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.3811273932
Short name T1079
Test name
Test status
Simulation time 157541592 ps
CPU time 0.83 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206924 kb
Host smart-aa07f559-b9c0-459a-a41a-e1c42c732525
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3811273932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3811273932
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3709761577
Short name T627
Test name
Test status
Simulation time 160687747 ps
CPU time 0.9 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206952 kb
Host smart-e069c6b5-8057-4a62-8634-942c1493b7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37097
61577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3709761577
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2078515642
Short name T138
Test name
Test status
Simulation time 236484341 ps
CPU time 1.05 seconds
Started Jul 30 06:33:39 PM PDT 24
Finished Jul 30 06:33:40 PM PDT 24
Peak memory 206908 kb
Host smart-89c982ac-a47c-4dbc-a91a-c8c267ea6f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20785
15642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2078515642
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2139492850
Short name T1458
Test name
Test status
Simulation time 175167081 ps
CPU time 0.92 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 206920 kb
Host smart-bb804ac4-498b-49c3-b67a-a60d3bdbe7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21394
92850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2139492850
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1774595496
Short name T1667
Test name
Test status
Simulation time 164772440 ps
CPU time 0.84 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 206868 kb
Host smart-4c12724d-48b1-4cb5-996a-bfec05d4ab30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17745
95496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1774595496
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3938475076
Short name T2295
Test name
Test status
Simulation time 145799157 ps
CPU time 0.84 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:36 PM PDT 24
Peak memory 206956 kb
Host smart-7ba04a66-696c-400a-b6ef-b557f80ba8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39384
75076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3938475076
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.2232856364
Short name T1244
Test name
Test status
Simulation time 182286699 ps
CPU time 0.9 seconds
Started Jul 30 06:33:38 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 206932 kb
Host smart-a541ad20-3eea-436d-9875-71fafd84ceed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22328
56364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.2232856364
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3349791442
Short name T623
Test name
Test status
Simulation time 206289674 ps
CPU time 0.92 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:36 PM PDT 24
Peak memory 206928 kb
Host smart-e7d091ee-414c-4b5a-9608-ceefd67ad6d4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3349791442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3349791442
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.4234807908
Short name T346
Test name
Test status
Simulation time 140514292 ps
CPU time 0.8 seconds
Started Jul 30 06:33:38 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 206848 kb
Host smart-a42fa559-86a7-4346-b600-c17fd29acbfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42348
07908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.4234807908
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.160287066
Short name T1415
Test name
Test status
Simulation time 103450642 ps
CPU time 0.76 seconds
Started Jul 30 06:33:40 PM PDT 24
Finished Jul 30 06:33:41 PM PDT 24
Peak memory 206900 kb
Host smart-3cf6e727-d7ca-460f-8b95-a0cd710feb79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16028
7066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.160287066
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1942977588
Short name T831
Test name
Test status
Simulation time 9279066035 ps
CPU time 25.97 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:34:04 PM PDT 24
Peak memory 215372 kb
Host smart-c70e6a77-76c9-4eac-8bad-1058cbf8503d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19429
77588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1942977588
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2959892674
Short name T205
Test name
Test status
Simulation time 170128361 ps
CPU time 0.87 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:33:46 PM PDT 24
Peak memory 206908 kb
Host smart-154a7035-5980-48db-84f3-5fc2b12473a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29598
92674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2959892674
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.236381312
Short name T512
Test name
Test status
Simulation time 246150633 ps
CPU time 0.97 seconds
Started Jul 30 06:33:40 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 206924 kb
Host smart-7ba0faa1-40a0-4d42-87d9-b24cd5c5cd1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23638
1312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.236381312
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.53877399
Short name T1455
Test name
Test status
Simulation time 218108581 ps
CPU time 0.95 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:35 PM PDT 24
Peak memory 206920 kb
Host smart-85e2419b-8bfc-4564-9ba5-9e7dc9e7b6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53877
399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.53877399
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2032367694
Short name T2144
Test name
Test status
Simulation time 196763520 ps
CPU time 0.9 seconds
Started Jul 30 06:33:41 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 206928 kb
Host smart-7f99d257-ad14-4756-b08f-65b40a67e010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20323
67694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2032367694
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.16706596
Short name T311
Test name
Test status
Simulation time 160273545 ps
CPU time 0.81 seconds
Started Jul 30 06:33:33 PM PDT 24
Finished Jul 30 06:33:34 PM PDT 24
Peak memory 206916 kb
Host smart-47d9fe28-008e-4b53-87e2-5b83f644844e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16706
596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.16706596
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2306038943
Short name T243
Test name
Test status
Simulation time 142676831 ps
CPU time 0.87 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:36 PM PDT 24
Peak memory 206944 kb
Host smart-c3eeb146-81a9-4a00-86e4-7768f96a0d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23060
38943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2306038943
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3207231934
Short name T392
Test name
Test status
Simulation time 156985079 ps
CPU time 0.9 seconds
Started Jul 30 06:33:40 PM PDT 24
Finished Jul 30 06:33:41 PM PDT 24
Peak memory 206948 kb
Host smart-be438167-24e6-4778-8ca0-bae91861e1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32072
31934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3207231934
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3019520545
Short name T774
Test name
Test status
Simulation time 198232761 ps
CPU time 0.99 seconds
Started Jul 30 06:33:41 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 206940 kb
Host smart-f081f652-1a75-4ae8-9828-4f12c5ccdee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30195
20545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3019520545
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.1727811945
Short name T2055
Test name
Test status
Simulation time 3985660967 ps
CPU time 30.55 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:34:16 PM PDT 24
Peak memory 216872 kb
Host smart-a223ee83-4d4b-42e6-a41c-1aa16c167701
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1727811945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.1727811945
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3834292623
Short name T828
Test name
Test status
Simulation time 172070380 ps
CPU time 0.93 seconds
Started Jul 30 06:33:43 PM PDT 24
Finished Jul 30 06:33:45 PM PDT 24
Peak memory 206904 kb
Host smart-b7efb526-cbff-433c-a9bc-921b9b677e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38342
92623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3834292623
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1665893737
Short name T2635
Test name
Test status
Simulation time 175295304 ps
CPU time 0.88 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 206908 kb
Host smart-682cc7c6-7826-4ebe-a386-53566694f753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16658
93737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1665893737
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3180710118
Short name T2518
Test name
Test status
Simulation time 576465592 ps
CPU time 1.71 seconds
Started Jul 30 06:33:39 PM PDT 24
Finished Jul 30 06:33:41 PM PDT 24
Peak memory 206904 kb
Host smart-4441baf1-851d-4036-9e1f-753e9f5ec0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31807
10118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3180710118
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.1570531021
Short name T1192
Test name
Test status
Simulation time 5262864951 ps
CPU time 40.7 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:34:16 PM PDT 24
Peak memory 207152 kb
Host smart-b47cf284-7b28-4910-b23f-e9cb32c62aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15705
31021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1570531021
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.1138025573
Short name T1459
Test name
Test status
Simulation time 884208635 ps
CPU time 18.99 seconds
Started Jul 30 06:33:39 PM PDT 24
Finished Jul 30 06:33:58 PM PDT 24
Peak memory 206972 kb
Host smart-4cb59b92-8de7-4b2e-b1d9-6c646f3d3f2a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138025573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos
t_handshake.1138025573
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.493370586
Short name T502
Test name
Test status
Simulation time 37818495 ps
CPU time 0.68 seconds
Started Jul 30 06:28:27 PM PDT 24
Finished Jul 30 06:28:28 PM PDT 24
Peak memory 207008 kb
Host smart-dd15a3e3-bf13-4bf4-aaab-8e893fd4003d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=493370586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.493370586
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.3402945426
Short name T1284
Test name
Test status
Simulation time 4442474315 ps
CPU time 6.65 seconds
Started Jul 30 06:28:20 PM PDT 24
Finished Jul 30 06:28:27 PM PDT 24
Peak memory 207128 kb
Host smart-55b28294-77a3-4981-be68-fb08ac3bb0c7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402945426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.3402945426
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.89977279
Short name T1293
Test name
Test status
Simulation time 13395510738 ps
CPU time 15.87 seconds
Started Jul 30 06:28:24 PM PDT 24
Finished Jul 30 06:28:39 PM PDT 24
Peak memory 207140 kb
Host smart-fb24d6fc-e5f4-4f8c-8be6-c93fac17b2db
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=89977279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.89977279
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3631514765
Short name T420
Test name
Test status
Simulation time 23368793697 ps
CPU time 32.39 seconds
Started Jul 30 06:28:15 PM PDT 24
Finished Jul 30 06:28:48 PM PDT 24
Peak memory 207112 kb
Host smart-157f7b19-f01d-41d2-8583-7b2a8646e84f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631514765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.3631514765
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.405482514
Short name T776
Test name
Test status
Simulation time 196866905 ps
CPU time 0.9 seconds
Started Jul 30 06:28:12 PM PDT 24
Finished Jul 30 06:28:13 PM PDT 24
Peak memory 206924 kb
Host smart-20e8c538-f49f-4031-ac98-829278b9372e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40548
2514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.405482514
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.439926443
Short name T47
Test name
Test status
Simulation time 155818150 ps
CPU time 0.83 seconds
Started Jul 30 06:28:15 PM PDT 24
Finished Jul 30 06:28:16 PM PDT 24
Peak memory 206896 kb
Host smart-2f5e08ed-5756-4e33-8194-1a4124493500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43992
6443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.439926443
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2330527924
Short name T98
Test name
Test status
Simulation time 180862136 ps
CPU time 0.88 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 206836 kb
Host smart-824e90de-315f-4482-b8e5-5cd3e7391195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23305
27924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2330527924
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.1509665402
Short name T2805
Test name
Test status
Simulation time 142427528 ps
CPU time 0.8 seconds
Started Jul 30 06:28:14 PM PDT 24
Finished Jul 30 06:28:15 PM PDT 24
Peak memory 206888 kb
Host smart-a6095ad5-d0a7-4f3c-bda4-f84b52afffe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096
65402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.1509665402
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.3769868489
Short name T2564
Test name
Test status
Simulation time 446969921 ps
CPU time 1.48 seconds
Started Jul 30 06:28:14 PM PDT 24
Finished Jul 30 06:28:16 PM PDT 24
Peak memory 206932 kb
Host smart-27d3ea0b-0761-40c7-82b2-f05bc9402c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37698
68489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.3769868489
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2152506504
Short name T993
Test name
Test status
Simulation time 725447805 ps
CPU time 2.04 seconds
Started Jul 30 06:28:14 PM PDT 24
Finished Jul 30 06:28:16 PM PDT 24
Peak memory 207028 kb
Host smart-42b66527-a8e2-4f7f-bffd-a8e338a4e4fa
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2152506504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2152506504
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.2984425878
Short name T2686
Test name
Test status
Simulation time 22129977978 ps
CPU time 51.75 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:29:08 PM PDT 24
Peak memory 207080 kb
Host smart-1316b7d2-8d0c-45a1-9a1c-f85bc6d094e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29844
25878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2984425878
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.1668842832
Short name T2396
Test name
Test status
Simulation time 279355174 ps
CPU time 4.43 seconds
Started Jul 30 06:28:19 PM PDT 24
Finished Jul 30 06:28:26 PM PDT 24
Peak memory 207028 kb
Host smart-125c3ee0-2ccb-4961-a683-c570c3d3b7f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668842832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.1668842832
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.3028818360
Short name T2854
Test name
Test status
Simulation time 435156242 ps
CPU time 1.56 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 206880 kb
Host smart-2088f9b6-5104-4b38-8390-a38fb9803a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30288
18360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.3028818360
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3956616283
Short name T913
Test name
Test status
Simulation time 143223821 ps
CPU time 0.88 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 206876 kb
Host smart-dba642b5-2463-4725-afc1-be8819b7ec81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39566
16283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3956616283
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.4158557634
Short name T1661
Test name
Test status
Simulation time 42820449 ps
CPU time 0.7 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 206920 kb
Host smart-4ccb5232-acb6-4dd4-a7d0-313107ec4b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41585
57634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.4158557634
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.57279577
Short name T695
Test name
Test status
Simulation time 707142367 ps
CPU time 2.17 seconds
Started Jul 30 06:28:19 PM PDT 24
Finished Jul 30 06:28:21 PM PDT 24
Peak memory 207120 kb
Host smart-eb4fb7e5-724d-48f6-8a05-d4692391fadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57279
577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.57279577
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.613926478
Short name T177
Test name
Test status
Simulation time 272891084 ps
CPU time 2.14 seconds
Started Jul 30 06:28:20 PM PDT 24
Finished Jul 30 06:28:22 PM PDT 24
Peak memory 207004 kb
Host smart-5842d884-17ea-4088-b8d0-7e2f6a2debb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61392
6478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.613926478
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.1853969838
Short name T2513
Test name
Test status
Simulation time 111189823205 ps
CPU time 194.15 seconds
Started Jul 30 06:28:20 PM PDT 24
Finished Jul 30 06:31:34 PM PDT 24
Peak memory 207164 kb
Host smart-f6ecc222-6c89-4a37-950c-a33af2aae0f4
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1853969838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.1853969838
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.2228830126
Short name T453
Test name
Test status
Simulation time 116425808185 ps
CPU time 189.55 seconds
Started Jul 30 06:28:21 PM PDT 24
Finished Jul 30 06:31:31 PM PDT 24
Peak memory 207072 kb
Host smart-0173994c-7c6d-40d5-bcf0-f73cc63bd372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228830126 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.2228830126
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.2751938568
Short name T2169
Test name
Test status
Simulation time 110097932775 ps
CPU time 165.79 seconds
Started Jul 30 06:28:21 PM PDT 24
Finished Jul 30 06:31:07 PM PDT 24
Peak memory 207056 kb
Host smart-e16cc7df-bca7-4168-aaf8-8dc741fd4501
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2751938568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.2751938568
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.733195303
Short name T2727
Test name
Test status
Simulation time 108274544911 ps
CPU time 167.37 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:31:05 PM PDT 24
Peak memory 207164 kb
Host smart-74cec9fb-f5da-4b2f-b2bf-3dd7b462fc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733195303 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.733195303
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.290970211
Short name T1303
Test name
Test status
Simulation time 111181201189 ps
CPU time 166.96 seconds
Started Jul 30 06:28:19 PM PDT 24
Finished Jul 30 06:31:06 PM PDT 24
Peak memory 207144 kb
Host smart-79dfee75-a0cd-41db-92fa-939e42d21c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29097
0211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.290970211
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1488448615
Short name T912
Test name
Test status
Simulation time 259965037 ps
CPU time 1.12 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 207084 kb
Host smart-1d66dd20-ea9a-49a1-81db-8920cacc121b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1488448615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1488448615
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.4096581623
Short name T1778
Test name
Test status
Simulation time 146584017 ps
CPU time 0.83 seconds
Started Jul 30 06:28:24 PM PDT 24
Finished Jul 30 06:28:25 PM PDT 24
Peak memory 206884 kb
Host smart-92a0f971-3312-4f41-b8d0-7ffafce9a83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40965
81623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.4096581623
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3031067352
Short name T2520
Test name
Test status
Simulation time 234100911 ps
CPU time 0.99 seconds
Started Jul 30 06:28:20 PM PDT 24
Finished Jul 30 06:28:21 PM PDT 24
Peak memory 206908 kb
Host smart-885de07f-fe9d-4ca1-be91-d86e8b1e9353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30310
67352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3031067352
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.1696603274
Short name T104
Test name
Test status
Simulation time 6005310220 ps
CPU time 177.51 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:31:13 PM PDT 24
Peak memory 215344 kb
Host smart-69cd2a39-f9a6-48b9-87d3-533fa13466e8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1696603274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.1696603274
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.1830979289
Short name T103
Test name
Test status
Simulation time 13628771266 ps
CPU time 178.14 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:31:17 PM PDT 24
Peak memory 207104 kb
Host smart-23777c62-2a9c-4c56-873f-c80b8c5a3c38
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1830979289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.1830979289
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.68649197
Short name T2139
Test name
Test status
Simulation time 163454699 ps
CPU time 0.92 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 206928 kb
Host smart-15facb9b-02ae-460d-8260-dca664b374f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68649
197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.68649197
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.1089477567
Short name T1288
Test name
Test status
Simulation time 23331601082 ps
CPU time 29.44 seconds
Started Jul 30 06:28:22 PM PDT 24
Finished Jul 30 06:28:51 PM PDT 24
Peak memory 207076 kb
Host smart-abd4b2fa-b7b1-4813-9484-9457e5318b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
77567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.1089477567
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3158010140
Short name T1091
Test name
Test status
Simulation time 3362574533 ps
CPU time 4.86 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:23 PM PDT 24
Peak memory 207100 kb
Host smart-71c2cbcf-0696-4bc6-a746-cbc6433ef22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31580
10140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3158010140
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.2259618005
Short name T1553
Test name
Test status
Simulation time 9047791760 ps
CPU time 72.8 seconds
Started Jul 30 06:28:20 PM PDT 24
Finished Jul 30 06:29:33 PM PDT 24
Peak memory 217516 kb
Host smart-e32e2787-a41c-4b1c-b6ba-e842fff0379d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22596
18005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.2259618005
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2874431552
Short name T2392
Test name
Test status
Simulation time 3600200852 ps
CPU time 32.71 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:52 PM PDT 24
Peak memory 216720 kb
Host smart-fa2d6de5-30bd-4090-a469-dfcab01e5e77
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2874431552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2874431552
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.200320208
Short name T2742
Test name
Test status
Simulation time 239645018 ps
CPU time 1.07 seconds
Started Jul 30 06:28:24 PM PDT 24
Finished Jul 30 06:28:25 PM PDT 24
Peak memory 206920 kb
Host smart-8abf0d8b-a5bd-4c91-8215-4bbfd250f005
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=200320208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.200320208
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3770642741
Short name T2202
Test name
Test status
Simulation time 192072706 ps
CPU time 0.91 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 206908 kb
Host smart-be926d8c-aa69-4608-b067-df8c5e2024e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37706
42741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3770642741
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.4195407804
Short name T2173
Test name
Test status
Simulation time 3383964375 ps
CPU time 98.46 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:29:57 PM PDT 24
Peak memory 215280 kb
Host smart-5bfee5a1-075d-403f-a405-561eb8c548f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41954
07804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.4195407804
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2329336751
Short name T1964
Test name
Test status
Simulation time 4906422520 ps
CPU time 36.06 seconds
Started Jul 30 06:28:20 PM PDT 24
Finished Jul 30 06:28:57 PM PDT 24
Peak memory 216664 kb
Host smart-5af1a503-11ae-427c-8ec7-6d6aa2c407bd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2329336751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2329336751
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.4210625985
Short name T2225
Test name
Test status
Simulation time 161381690 ps
CPU time 0.89 seconds
Started Jul 30 06:28:24 PM PDT 24
Finished Jul 30 06:28:25 PM PDT 24
Peak memory 206920 kb
Host smart-903a75e1-4f54-4382-a93e-b22762bda6dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4210625985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.4210625985
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2537891527
Short name T2291
Test name
Test status
Simulation time 221742628 ps
CPU time 0.9 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 206912 kb
Host smart-77decb83-c810-4108-9752-676143bb6137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25378
91527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2537891527
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3748353921
Short name T2186
Test name
Test status
Simulation time 251861230 ps
CPU time 0.97 seconds
Started Jul 30 06:28:16 PM PDT 24
Finished Jul 30 06:28:18 PM PDT 24
Peak memory 206908 kb
Host smart-601aaba8-972e-4642-b61f-052d342a358e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37483
53921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3748353921
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1579957165
Short name T2289
Test name
Test status
Simulation time 169530653 ps
CPU time 0.88 seconds
Started Jul 30 06:28:21 PM PDT 24
Finished Jul 30 06:28:22 PM PDT 24
Peak memory 206872 kb
Host smart-9b454524-adfb-49a9-b3d0-98b0fe71f67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15799
57165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1579957165
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3390436478
Short name T486
Test name
Test status
Simulation time 173850226 ps
CPU time 0.82 seconds
Started Jul 30 06:28:24 PM PDT 24
Finished Jul 30 06:28:25 PM PDT 24
Peak memory 206900 kb
Host smart-f88545af-49ef-426d-9ad7-9e12a58a6815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33904
36478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3390436478
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.4274867496
Short name T497
Test name
Test status
Simulation time 191228150 ps
CPU time 0.85 seconds
Started Jul 30 06:28:18 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 206920 kb
Host smart-53b5833c-9245-45e8-aeb3-c3fe12432f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42748
67496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.4274867496
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2635680440
Short name T155
Test name
Test status
Simulation time 152898716 ps
CPU time 0.85 seconds
Started Jul 30 06:28:19 PM PDT 24
Finished Jul 30 06:28:20 PM PDT 24
Peak memory 206956 kb
Host smart-32ec5b57-ff09-49ba-84e3-4dd901ea783a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26356
80440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2635680440
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2884748066
Short name T1481
Test name
Test status
Simulation time 223363527 ps
CPU time 0.99 seconds
Started Jul 30 06:28:20 PM PDT 24
Finished Jul 30 06:28:22 PM PDT 24
Peak memory 206916 kb
Host smart-5e12fbfc-16a7-47aa-a99c-452b7d4dc0c9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2884748066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2884748066
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2316168609
Short name T195
Test name
Test status
Simulation time 217862741 ps
CPU time 1 seconds
Started Jul 30 06:28:35 PM PDT 24
Finished Jul 30 06:28:36 PM PDT 24
Peak memory 206924 kb
Host smart-5f9a2eb4-f3e8-4a35-85f2-762e16222d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23161
68609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2316168609
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.3389724807
Short name T693
Test name
Test status
Simulation time 149038088 ps
CPU time 0.83 seconds
Started Jul 30 06:28:22 PM PDT 24
Finished Jul 30 06:28:23 PM PDT 24
Peak memory 206868 kb
Host smart-247af924-1f71-4724-879e-ec656c55162d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33897
24807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.3389724807
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3761725954
Short name T1145
Test name
Test status
Simulation time 84255627 ps
CPU time 0.79 seconds
Started Jul 30 06:28:26 PM PDT 24
Finished Jul 30 06:28:27 PM PDT 24
Peak memory 206876 kb
Host smart-f9ca53d1-d135-4ae9-a2a9-7150d13a99f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37617
25954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3761725954
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3389315433
Short name T1175
Test name
Test status
Simulation time 15799784701 ps
CPU time 39.12 seconds
Started Jul 30 06:28:26 PM PDT 24
Finished Jul 30 06:29:05 PM PDT 24
Peak memory 215368 kb
Host smart-31f3dc83-b076-49aa-b675-d0502ac10785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33893
15433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3389315433
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1284712921
Short name T1377
Test name
Test status
Simulation time 174775700 ps
CPU time 0.92 seconds
Started Jul 30 06:28:22 PM PDT 24
Finished Jul 30 06:28:23 PM PDT 24
Peak memory 206908 kb
Host smart-b0429806-1ae3-46d7-b937-5c498307f140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12847
12921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1284712921
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1232575605
Short name T471
Test name
Test status
Simulation time 167558342 ps
CPU time 0.9 seconds
Started Jul 30 06:28:21 PM PDT 24
Finished Jul 30 06:28:22 PM PDT 24
Peak memory 206952 kb
Host smart-df0f3025-83de-4806-aeb3-3d951b5e8a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12325
75605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1232575605
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1338344785
Short name T2255
Test name
Test status
Simulation time 11338026143 ps
CPU time 241.16 seconds
Started Jul 30 06:28:20 PM PDT 24
Finished Jul 30 06:32:21 PM PDT 24
Peak memory 215324 kb
Host smart-a290821b-91ff-45e6-b8a6-a2a6c114452d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338344785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1338344785
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.4192465025
Short name T162
Test name
Test status
Simulation time 5953318277 ps
CPU time 162.18 seconds
Started Jul 30 06:28:21 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 215348 kb
Host smart-b35ed0ac-4890-46a8-ae24-5af7c8e6bbda
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4192465025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.4192465025
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.3208698126
Short name T1692
Test name
Test status
Simulation time 7161450783 ps
CPU time 33.1 seconds
Started Jul 30 06:28:27 PM PDT 24
Finished Jul 30 06:29:00 PM PDT 24
Peak memory 223488 kb
Host smart-639ba3ea-25a4-4642-9517-8cb8663e4179
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208698126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.3208698126
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1878955615
Short name T2113
Test name
Test status
Simulation time 291013400 ps
CPU time 1.06 seconds
Started Jul 30 06:28:44 PM PDT 24
Finished Jul 30 06:28:45 PM PDT 24
Peak memory 206896 kb
Host smart-e42340b5-4aa5-43e9-b04c-00883b1e7a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18789
55615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1878955615
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1373573006
Short name T1190
Test name
Test status
Simulation time 207319368 ps
CPU time 0.98 seconds
Started Jul 30 06:28:25 PM PDT 24
Finished Jul 30 06:28:26 PM PDT 24
Peak memory 206868 kb
Host smart-4fd8f2cc-852b-4781-8602-b6362f02b74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13735
73006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1373573006
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1066079261
Short name T1060
Test name
Test status
Simulation time 169622004 ps
CPU time 0.85 seconds
Started Jul 30 06:28:27 PM PDT 24
Finished Jul 30 06:28:28 PM PDT 24
Peak memory 206968 kb
Host smart-0c86768a-a339-4d05-a5b6-ffdee19953e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10660
79261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1066079261
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.3514911268
Short name T2013
Test name
Test status
Simulation time 165719338 ps
CPU time 0.87 seconds
Started Jul 30 06:28:28 PM PDT 24
Finished Jul 30 06:28:29 PM PDT 24
Peak memory 206912 kb
Host smart-202d4b3f-d032-4732-9fd0-5bd3fcf49b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35149
11268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.3514911268
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3540669151
Short name T185
Test name
Test status
Simulation time 476096414 ps
CPU time 1.33 seconds
Started Jul 30 06:28:46 PM PDT 24
Finished Jul 30 06:28:47 PM PDT 24
Peak memory 224000 kb
Host smart-b232d6c7-1c66-4d88-a86b-3866c0e15f3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3540669151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3540669151
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.4096451275
Short name T43
Test name
Test status
Simulation time 410892935 ps
CPU time 1.47 seconds
Started Jul 30 06:28:25 PM PDT 24
Finished Jul 30 06:28:27 PM PDT 24
Peak memory 206896 kb
Host smart-1616636c-996e-4148-9626-152260781803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40964
51275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.4096451275
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.302270315
Short name T1467
Test name
Test status
Simulation time 294238363 ps
CPU time 1.01 seconds
Started Jul 30 06:28:21 PM PDT 24
Finished Jul 30 06:28:22 PM PDT 24
Peak memory 206916 kb
Host smart-eb6bd725-53fa-46be-9922-ecdaf7d671ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30227
0315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.302270315
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.76652863
Short name T476
Test name
Test status
Simulation time 166089680 ps
CPU time 0.87 seconds
Started Jul 30 06:28:38 PM PDT 24
Finished Jul 30 06:28:39 PM PDT 24
Peak memory 206872 kb
Host smart-dad6f406-d435-4df8-a1e8-be537616425a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76652
863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.76652863
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3976734896
Short name T1729
Test name
Test status
Simulation time 147564100 ps
CPU time 0.84 seconds
Started Jul 30 06:28:41 PM PDT 24
Finished Jul 30 06:28:42 PM PDT 24
Peak memory 206908 kb
Host smart-b7b84518-b68c-4ac9-96be-2337919a5238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39767
34896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3976734896
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3710216894
Short name T819
Test name
Test status
Simulation time 233574352 ps
CPU time 1.08 seconds
Started Jul 30 06:28:43 PM PDT 24
Finished Jul 30 06:28:44 PM PDT 24
Peak memory 206904 kb
Host smart-53ca3513-369f-4755-9025-f35c3bfe068a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37102
16894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3710216894
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.844497354
Short name T299
Test name
Test status
Simulation time 4004092346 ps
CPU time 38.6 seconds
Started Jul 30 06:28:28 PM PDT 24
Finished Jul 30 06:29:06 PM PDT 24
Peak memory 207144 kb
Host smart-b19e9be6-bb65-4b79-8e20-b0ce0f84b03b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=844497354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.844497354
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.2901736462
Short name T903
Test name
Test status
Simulation time 169728624 ps
CPU time 0.93 seconds
Started Jul 30 06:28:21 PM PDT 24
Finished Jul 30 06:28:22 PM PDT 24
Peak memory 206904 kb
Host smart-576b54e8-b659-41e6-ad06-6bdce6560423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29017
36462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.2901736462
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1961419531
Short name T2823
Test name
Test status
Simulation time 239871572 ps
CPU time 0.98 seconds
Started Jul 30 06:28:43 PM PDT 24
Finished Jul 30 06:28:44 PM PDT 24
Peak memory 206908 kb
Host smart-794df514-270a-459e-87a0-b7a5e14d8ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19614
19531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1961419531
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.246940980
Short name T2649
Test name
Test status
Simulation time 1017800983 ps
CPU time 2.38 seconds
Started Jul 30 06:28:20 PM PDT 24
Finished Jul 30 06:28:23 PM PDT 24
Peak memory 207012 kb
Host smart-ff10529b-e72c-442d-9347-4aea7a5c52d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24694
0980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.246940980
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.3162704351
Short name T1536
Test name
Test status
Simulation time 3785794467 ps
CPU time 30.5 seconds
Started Jul 30 06:28:34 PM PDT 24
Finished Jul 30 06:29:05 PM PDT 24
Peak memory 215288 kb
Host smart-c54def42-bf73-4542-9e8a-ac7b05d8487b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31627
04351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.3162704351
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.2575938551
Short name T75
Test name
Test status
Simulation time 15659901405 ps
CPU time 423.36 seconds
Started Jul 30 06:28:25 PM PDT 24
Finished Jul 30 06:35:29 PM PDT 24
Peak memory 215276 kb
Host smart-1c3f8067-40d5-4bac-9c48-599f368afef2
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575938551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.2575938551
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.108271949
Short name T2287
Test name
Test status
Simulation time 1020128432 ps
CPU time 22.99 seconds
Started Jul 30 06:28:17 PM PDT 24
Finished Jul 30 06:28:40 PM PDT 24
Peak memory 207052 kb
Host smart-4e60a553-d8ec-41db-ad07-35a5773f3ded
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108271949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host_
handshake.108271949
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.270316620
Short name T1388
Test name
Test status
Simulation time 85010940 ps
CPU time 0.72 seconds
Started Jul 30 06:33:41 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 207024 kb
Host smart-dcd17a61-e049-4de5-8659-0e991f55abc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=270316620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.270316620
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.978040872
Short name T1919
Test name
Test status
Simulation time 3521279163 ps
CPU time 5.32 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 207072 kb
Host smart-17b607e9-d49e-49c8-813a-aa85444352ca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978040872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_ao
n_wake_disconnect.978040872
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2373982020
Short name T2012
Test name
Test status
Simulation time 13322783911 ps
CPU time 16.09 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:54 PM PDT 24
Peak memory 207156 kb
Host smart-400fd347-3743-4369-9c2a-790523205293
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373982020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2373982020
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.2339105812
Short name T210
Test name
Test status
Simulation time 23441032689 ps
CPU time 29.14 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:34:05 PM PDT 24
Peak memory 207124 kb
Host smart-cc9c71bd-903e-4294-b20d-189fb17cb312
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339105812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.2339105812
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2890386835
Short name T1663
Test name
Test status
Simulation time 152633482 ps
CPU time 0.92 seconds
Started Jul 30 06:33:39 PM PDT 24
Finished Jul 30 06:33:40 PM PDT 24
Peak memory 206940 kb
Host smart-edb8fe1e-2d20-407b-9244-061828981e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28903
86835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2890386835
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.764199975
Short name T64
Test name
Test status
Simulation time 143727616 ps
CPU time 0.83 seconds
Started Jul 30 06:33:43 PM PDT 24
Finished Jul 30 06:33:44 PM PDT 24
Peak memory 206912 kb
Host smart-abedd611-a743-4a93-b3ff-01ce80de5d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76419
9975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.764199975
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2734374018
Short name T90
Test name
Test status
Simulation time 174045191 ps
CPU time 0.9 seconds
Started Jul 30 06:33:31 PM PDT 24
Finished Jul 30 06:33:33 PM PDT 24
Peak memory 206948 kb
Host smart-696b16eb-f123-46c9-a374-c0c5a4518240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27343
74018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2734374018
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2943971729
Short name T1930
Test name
Test status
Simulation time 831573205 ps
CPU time 2.17 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 207052 kb
Host smart-308f825b-6f31-4aef-8203-11b82cfbbb08
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2943971729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2943971729
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.4208480258
Short name T773
Test name
Test status
Simulation time 8483006129 ps
CPU time 18.28 seconds
Started Jul 30 06:33:39 PM PDT 24
Finished Jul 30 06:33:57 PM PDT 24
Peak memory 207176 kb
Host smart-e901ffa7-b6a5-4947-a3f8-6d00e6a5d136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42084
80258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.4208480258
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.12863596
Short name T941
Test name
Test status
Simulation time 1210139551 ps
CPU time 25.66 seconds
Started Jul 30 06:33:36 PM PDT 24
Finished Jul 30 06:34:02 PM PDT 24
Peak memory 206968 kb
Host smart-b8543b91-2964-436e-a505-1a5480073848
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12863596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.12863596
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2889180344
Short name T1403
Test name
Test status
Simulation time 448617973 ps
CPU time 1.47 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 206544 kb
Host smart-21c9016a-a64b-4603-8411-bc1ef45f2a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28891
80344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2889180344
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.3500641235
Short name T1603
Test name
Test status
Simulation time 139820098 ps
CPU time 0.78 seconds
Started Jul 30 06:33:35 PM PDT 24
Finished Jul 30 06:33:37 PM PDT 24
Peak memory 206880 kb
Host smart-96c811e8-21d5-419b-9b1f-31241664761d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35006
41235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3500641235
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.3306650300
Short name T1358
Test name
Test status
Simulation time 36950439 ps
CPU time 0.71 seconds
Started Jul 30 06:33:40 PM PDT 24
Finished Jul 30 06:33:41 PM PDT 24
Peak memory 206888 kb
Host smart-d7268c7f-ab87-4cf5-beee-1392bbec2f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33066
50300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3306650300
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3315874286
Short name T1525
Test name
Test status
Simulation time 920080044 ps
CPU time 2.44 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:33:48 PM PDT 24
Peak memory 207024 kb
Host smart-c70d7ba2-82bc-446d-a9cb-717152396943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33158
74286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3315874286
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1988621914
Short name T2366
Test name
Test status
Simulation time 265337539 ps
CPU time 2.06 seconds
Started Jul 30 06:33:38 PM PDT 24
Finished Jul 30 06:33:40 PM PDT 24
Peak memory 206936 kb
Host smart-568ec43e-fd76-48b3-9b69-03d3a8b6d3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19886
21914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1988621914
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3012158433
Short name T86
Test name
Test status
Simulation time 236245344 ps
CPU time 1.25 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:33:46 PM PDT 24
Peak memory 214940 kb
Host smart-7d794281-5dda-4c58-b856-8e5ad823e167
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3012158433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3012158433
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1674432959
Short name T500
Test name
Test status
Simulation time 140735601 ps
CPU time 0.81 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206920 kb
Host smart-00296d8c-5dcd-40e0-9718-6a8023707ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16744
32959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1674432959
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1066520483
Short name T1596
Test name
Test status
Simulation time 212744797 ps
CPU time 0.98 seconds
Started Jul 30 06:33:38 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 206900 kb
Host smart-4957625a-71b5-4609-8f0b-3c50a3072dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10665
20483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1066520483
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.1036475037
Short name T1694
Test name
Test status
Simulation time 7926870522 ps
CPU time 244.78 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:37:50 PM PDT 24
Peak memory 215356 kb
Host smart-67577088-d151-4459-8de3-fe782ab2b45a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1036475037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.1036475037
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.2890888933
Short name T2533
Test name
Test status
Simulation time 7583206947 ps
CPU time 54.11 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:34:39 PM PDT 24
Peak memory 207128 kb
Host smart-6dc245a0-9a58-4f43-a93f-44d82188019a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2890888933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.2890888933
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1963875712
Short name T1741
Test name
Test status
Simulation time 205445991 ps
CPU time 0.94 seconds
Started Jul 30 06:33:42 PM PDT 24
Finished Jul 30 06:33:43 PM PDT 24
Peak memory 206672 kb
Host smart-5cca3e54-b126-4af2-b7d9-5631d5c1b66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19638
75712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1963875712
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.76182723
Short name T451
Test name
Test status
Simulation time 23274538838 ps
CPU time 26.89 seconds
Started Jul 30 06:33:44 PM PDT 24
Finished Jul 30 06:34:11 PM PDT 24
Peak memory 207136 kb
Host smart-2be727b9-ee9e-403e-abd1-31a64b6da5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76182
723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.76182723
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.364491940
Short name T1042
Test name
Test status
Simulation time 3262181580 ps
CPU time 5.15 seconds
Started Jul 30 06:33:44 PM PDT 24
Finished Jul 30 06:33:49 PM PDT 24
Peak memory 207096 kb
Host smart-02f04567-a4eb-4fe9-b411-53d7a7745946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36449
1940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.364491940
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1947301743
Short name T1450
Test name
Test status
Simulation time 5410043882 ps
CPU time 52.96 seconds
Started Jul 30 06:33:43 PM PDT 24
Finished Jul 30 06:34:36 PM PDT 24
Peak memory 216868 kb
Host smart-3f53cdea-b7b9-4d58-a753-dfc970b3338c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19473
01743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1947301743
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2250047285
Short name T1038
Test name
Test status
Simulation time 3007141649 ps
CPU time 84.81 seconds
Started Jul 30 06:33:41 PM PDT 24
Finished Jul 30 06:35:06 PM PDT 24
Peak memory 215324 kb
Host smart-925898e7-e143-48ce-9424-4810ae7d0bea
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2250047285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2250047285
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2962266887
Short name T1550
Test name
Test status
Simulation time 241374889 ps
CPU time 1.03 seconds
Started Jul 30 06:33:44 PM PDT 24
Finished Jul 30 06:33:45 PM PDT 24
Peak memory 206932 kb
Host smart-436b5f60-79e9-4cbe-847a-4acb03f7cbc5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2962266887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2962266887
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1341180852
Short name T2830
Test name
Test status
Simulation time 193081990 ps
CPU time 0.94 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206672 kb
Host smart-d99d0dd8-c312-4c19-8075-5644295ad532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13411
80852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1341180852
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1613614219
Short name T2463
Test name
Test status
Simulation time 3528667674 ps
CPU time 96.58 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:35:14 PM PDT 24
Peak memory 215076 kb
Host smart-016fdb86-29a7-452f-b2b7-9e3cdece7318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16136
14219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1613614219
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.2105251323
Short name T1445
Test name
Test status
Simulation time 3517327763 ps
CPU time 102.71 seconds
Started Jul 30 06:33:40 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 215348 kb
Host smart-a4a60d53-37e8-486d-8c6b-c3050e0e1ae8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2105251323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.2105251323
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.835624089
Short name T2682
Test name
Test status
Simulation time 153412541 ps
CPU time 0.84 seconds
Started Jul 30 06:33:37 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 206912 kb
Host smart-cd9dec46-3880-4fa5-bdd6-9e964e4eb77c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=835624089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.835624089
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3685817347
Short name T1352
Test name
Test status
Simulation time 139789610 ps
CPU time 0.87 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:36 PM PDT 24
Peak memory 206976 kb
Host smart-37609998-d3ab-479d-8bea-00d2fff79f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36858
17347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3685817347
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.495239873
Short name T132
Test name
Test status
Simulation time 231092505 ps
CPU time 0.98 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:33:46 PM PDT 24
Peak memory 206792 kb
Host smart-70595109-28b3-4bf7-ac24-e0d3adc1f484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49523
9873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.495239873
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.2316202657
Short name T2373
Test name
Test status
Simulation time 182091179 ps
CPU time 0.89 seconds
Started Jul 30 06:33:42 PM PDT 24
Finished Jul 30 06:33:43 PM PDT 24
Peak memory 206968 kb
Host smart-b78301cd-f092-4b26-9ad9-8d6b1ccf5703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23162
02657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2316202657
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1826660768
Short name T242
Test name
Test status
Simulation time 189349539 ps
CPU time 0.92 seconds
Started Jul 30 06:33:41 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 206916 kb
Host smart-8fafa548-f2e1-4b30-b340-85e0bd95afe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18266
60768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1826660768
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.318581861
Short name T1979
Test name
Test status
Simulation time 158087043 ps
CPU time 0.87 seconds
Started Jul 30 06:33:44 PM PDT 24
Finished Jul 30 06:33:45 PM PDT 24
Peak memory 206908 kb
Host smart-8eaed429-a4e0-4019-beab-92f450b06e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31858
1861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.318581861
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.4293478111
Short name T1277
Test name
Test status
Simulation time 147283314 ps
CPU time 0.84 seconds
Started Jul 30 06:33:43 PM PDT 24
Finished Jul 30 06:33:44 PM PDT 24
Peak memory 206936 kb
Host smart-c52c7626-9a66-4849-bc88-8c05dcc0ceab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42934
78111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.4293478111
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.2546411466
Short name T846
Test name
Test status
Simulation time 202135963 ps
CPU time 1.02 seconds
Started Jul 30 06:33:38 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 206912 kb
Host smart-0a1ebff7-bc8e-456e-a45a-447e0aa77fe0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2546411466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.2546411466
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1334076607
Short name T624
Test name
Test status
Simulation time 135758442 ps
CPU time 0.79 seconds
Started Jul 30 06:33:43 PM PDT 24
Finished Jul 30 06:33:44 PM PDT 24
Peak memory 206896 kb
Host smart-ded8b4b4-f0d6-4d07-9241-897762c6c830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13340
76607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1334076607
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.4090686450
Short name T1110
Test name
Test status
Simulation time 40568565 ps
CPU time 0.7 seconds
Started Jul 30 06:33:38 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 206848 kb
Host smart-d8dfe637-514e-40fe-b838-4775d9c32d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40906
86450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.4090686450
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3128642930
Short name T2351
Test name
Test status
Simulation time 7345816792 ps
CPU time 19.46 seconds
Started Jul 30 06:33:40 PM PDT 24
Finished Jul 30 06:34:00 PM PDT 24
Peak memory 215400 kb
Host smart-545f5ea6-4f0c-4f34-8fb8-c0e0837586a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31286
42930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3128642930
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.819242926
Short name T877
Test name
Test status
Simulation time 162960184 ps
CPU time 0.88 seconds
Started Jul 30 06:33:41 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 206916 kb
Host smart-889a8955-ee35-4f4a-a846-a020a80d5003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81924
2926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.819242926
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.175465619
Short name T2723
Test name
Test status
Simulation time 169504684 ps
CPU time 0.92 seconds
Started Jul 30 06:33:38 PM PDT 24
Finished Jul 30 06:33:39 PM PDT 24
Peak memory 206884 kb
Host smart-b80dfd92-c045-4b45-879f-c0fe5fb9b7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17546
5619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.175465619
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.3528852948
Short name T1628
Test name
Test status
Simulation time 246597049 ps
CPU time 1.04 seconds
Started Jul 30 06:33:44 PM PDT 24
Finished Jul 30 06:33:45 PM PDT 24
Peak memory 206880 kb
Host smart-3b04f3b5-424a-4580-81c6-a623c9736b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35288
52948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.3528852948
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.3458214174
Short name T2085
Test name
Test status
Simulation time 205682541 ps
CPU time 0.91 seconds
Started Jul 30 06:33:43 PM PDT 24
Finished Jul 30 06:33:44 PM PDT 24
Peak memory 206912 kb
Host smart-37f5ce85-4aac-4826-98b1-b09604c0498b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34582
14174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.3458214174
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.866410120
Short name T2063
Test name
Test status
Simulation time 148102797 ps
CPU time 0.83 seconds
Started Jul 30 06:33:39 PM PDT 24
Finished Jul 30 06:33:40 PM PDT 24
Peak memory 206976 kb
Host smart-b061cd32-8aaa-4dac-9842-3f029350e05f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86641
0120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.866410120
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1054182
Short name T1622
Test name
Test status
Simulation time 153270503 ps
CPU time 0.85 seconds
Started Jul 30 06:33:43 PM PDT 24
Finished Jul 30 06:33:44 PM PDT 24
Peak memory 206888 kb
Host smart-10d05143-2ef2-41db-994b-e2f4d6b03d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10541
82 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1054182
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.4245108106
Short name T2263
Test name
Test status
Simulation time 216565969 ps
CPU time 0.88 seconds
Started Jul 30 06:33:47 PM PDT 24
Finished Jul 30 06:33:48 PM PDT 24
Peak memory 206912 kb
Host smart-2ca81409-a539-49f0-bd32-1087e3d42a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42451
08106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.4245108106
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3054218790
Short name T1188
Test name
Test status
Simulation time 238420144 ps
CPU time 1.02 seconds
Started Jul 30 06:33:46 PM PDT 24
Finished Jul 30 06:33:47 PM PDT 24
Peak memory 206924 kb
Host smart-a4f67fe7-a9f8-49f1-9d21-583ffc013f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30542
18790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3054218790
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2843221766
Short name T1109
Test name
Test status
Simulation time 4234730226 ps
CPU time 121.88 seconds
Started Jul 30 06:33:41 PM PDT 24
Finished Jul 30 06:35:43 PM PDT 24
Peak memory 215352 kb
Host smart-1988d910-55c2-4cb8-9e93-0b4127d6f393
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2843221766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2843221766
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.3033393208
Short name T1077
Test name
Test status
Simulation time 213301795 ps
CPU time 0.98 seconds
Started Jul 30 06:33:44 PM PDT 24
Finished Jul 30 06:33:45 PM PDT 24
Peak memory 206912 kb
Host smart-d29cbcdf-b7f1-4542-b50a-4bd8e4f5aa56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30333
93208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.3033393208
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.292029687
Short name T1505
Test name
Test status
Simulation time 176818462 ps
CPU time 0.85 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:33:46 PM PDT 24
Peak memory 206940 kb
Host smart-5a9212ae-7599-439c-bc77-6dcd4bc12d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29202
9687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.292029687
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.933059769
Short name T2601
Test name
Test status
Simulation time 1162359779 ps
CPU time 2.59 seconds
Started Jul 30 06:33:44 PM PDT 24
Finished Jul 30 06:33:47 PM PDT 24
Peak memory 207036 kb
Host smart-fd88442b-e5f5-4694-916c-32c45713105a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93305
9769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.933059769
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3855803634
Short name T2279
Test name
Test status
Simulation time 5737288224 ps
CPU time 165.96 seconds
Started Jul 30 06:33:44 PM PDT 24
Finished Jul 30 06:36:30 PM PDT 24
Peak memory 215496 kb
Host smart-874933b5-9e9b-4f82-81db-853b1adc95b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38558
03634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3855803634
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.3423384338
Short name T925
Test name
Test status
Simulation time 636373597 ps
CPU time 11.48 seconds
Started Jul 30 06:33:34 PM PDT 24
Finished Jul 30 06:33:46 PM PDT 24
Peak memory 207028 kb
Host smart-f338098a-7cf5-4721-bac6-b30842d2b841
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423384338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.3423384338
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.2914705444
Short name T2837
Test name
Test status
Simulation time 57299674 ps
CPU time 0.69 seconds
Started Jul 30 06:34:11 PM PDT 24
Finished Jul 30 06:34:12 PM PDT 24
Peak memory 207024 kb
Host smart-65fc734a-6d03-41a6-a6c1-9eacfdbce3a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2914705444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.2914705444
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.93455869
Short name T466
Test name
Test status
Simulation time 3559028506 ps
CPU time 6.01 seconds
Started Jul 30 06:33:41 PM PDT 24
Finished Jul 30 06:33:47 PM PDT 24
Peak memory 207060 kb
Host smart-70b5703f-1a86-4376-87af-ab1272fd06cc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93455869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon
_wake_disconnect.93455869
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3223831649
Short name T1804
Test name
Test status
Simulation time 13335503473 ps
CPU time 16.28 seconds
Started Jul 30 06:33:42 PM PDT 24
Finished Jul 30 06:33:58 PM PDT 24
Peak memory 207152 kb
Host smart-f915e2cc-976a-4d2d-a34a-6ac416f502cd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223831649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3223831649
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2869037374
Short name T1236
Test name
Test status
Simulation time 23371543662 ps
CPU time 25.56 seconds
Started Jul 30 06:33:50 PM PDT 24
Finished Jul 30 06:34:15 PM PDT 24
Peak memory 207112 kb
Host smart-5136d4a8-088e-4ba5-81c9-926ae781b1cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869037374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.2869037374
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.136308931
Short name T2507
Test name
Test status
Simulation time 180747049 ps
CPU time 0.9 seconds
Started Jul 30 06:33:48 PM PDT 24
Finished Jul 30 06:33:54 PM PDT 24
Peak memory 206916 kb
Host smart-25c266aa-1279-4e46-87a0-41214722942d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13630
8931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.136308931
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2294288911
Short name T985
Test name
Test status
Simulation time 193449366 ps
CPU time 0.86 seconds
Started Jul 30 06:33:41 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 206880 kb
Host smart-321618b5-c2a0-46be-b30e-4aa8baef814f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22942
88911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2294288911
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.220723249
Short name T2503
Test name
Test status
Simulation time 240745203 ps
CPU time 1 seconds
Started Jul 30 06:33:43 PM PDT 24
Finished Jul 30 06:33:44 PM PDT 24
Peak memory 206912 kb
Host smart-45342bd0-08e5-4915-b70f-f7983f039de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22072
3249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.220723249
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_device_address.959718577
Short name T169
Test name
Test status
Simulation time 8949503785 ps
CPU time 19.69 seconds
Started Jul 30 06:33:43 PM PDT 24
Finished Jul 30 06:34:03 PM PDT 24
Peak memory 207116 kb
Host smart-a2a8c570-34a5-42bd-8190-d31046f7004b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95971
8577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.959718577
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.4000604833
Short name T1059
Test name
Test status
Simulation time 4895931114 ps
CPU time 31.78 seconds
Started Jul 30 06:33:50 PM PDT 24
Finished Jul 30 06:34:22 PM PDT 24
Peak memory 207168 kb
Host smart-05ce9f12-f0b5-40e2-8dde-73c39fc89956
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000604833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.4000604833
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.129236281
Short name T2731
Test name
Test status
Simulation time 447544437 ps
CPU time 1.5 seconds
Started Jul 30 06:33:44 PM PDT 24
Finished Jul 30 06:33:51 PM PDT 24
Peak memory 206876 kb
Host smart-2df0fbb7-b469-49f5-a31a-708513a7c527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12923
6281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.129236281
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.897102970
Short name T2521
Test name
Test status
Simulation time 148160660 ps
CPU time 0.82 seconds
Started Jul 30 06:33:43 PM PDT 24
Finished Jul 30 06:33:44 PM PDT 24
Peak memory 206908 kb
Host smart-f84ef83f-552b-417f-8663-e148dbbf0cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89710
2970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.897102970
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.1801515366
Short name T387
Test name
Test status
Simulation time 35280095 ps
CPU time 0.69 seconds
Started Jul 30 06:33:42 PM PDT 24
Finished Jul 30 06:33:43 PM PDT 24
Peak memory 206880 kb
Host smart-26a9b00e-77ba-474b-bb56-a19667e2d77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18015
15366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1801515366
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.1689214938
Short name T1850
Test name
Test status
Simulation time 1001836452 ps
CPU time 2.67 seconds
Started Jul 30 06:33:43 PM PDT 24
Finished Jul 30 06:33:46 PM PDT 24
Peak memory 207216 kb
Host smart-bab82beb-8590-4b9e-abd4-9e066b3cd530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16892
14938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.1689214938
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1940748229
Short name T2406
Test name
Test status
Simulation time 291851448 ps
CPU time 2.05 seconds
Started Jul 30 06:33:44 PM PDT 24
Finished Jul 30 06:33:46 PM PDT 24
Peak memory 206996 kb
Host smart-10eb7f46-fc41-4be1-bca2-ec5ad549abfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19407
48229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1940748229
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.2965532630
Short name T1615
Test name
Test status
Simulation time 241795861 ps
CPU time 1.26 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:33:46 PM PDT 24
Peak memory 207060 kb
Host smart-9454a646-3b1f-4f3a-b717-c82f11809969
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2965532630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.2965532630
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.405320653
Short name T1005
Test name
Test status
Simulation time 161560076 ps
CPU time 0.86 seconds
Started Jul 30 06:33:48 PM PDT 24
Finished Jul 30 06:33:49 PM PDT 24
Peak memory 206880 kb
Host smart-6760fec5-f555-42c0-9334-f24ab546cd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40532
0653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.405320653
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1063166231
Short name T2824
Test name
Test status
Simulation time 203807557 ps
CPU time 0.92 seconds
Started Jul 30 06:33:46 PM PDT 24
Finished Jul 30 06:33:47 PM PDT 24
Peak memory 206916 kb
Host smart-b8c9fa2a-da42-4841-9d96-5e95ed7871f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10631
66231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1063166231
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.4134826661
Short name T709
Test name
Test status
Simulation time 5468232399 ps
CPU time 158.48 seconds
Started Jul 30 06:33:48 PM PDT 24
Finished Jul 30 06:36:27 PM PDT 24
Peak memory 215312 kb
Host smart-c698d169-457e-4e93-83bd-4cb3324ab980
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4134826661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.4134826661
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.801802844
Short name T2644
Test name
Test status
Simulation time 12464449451 ps
CPU time 80.84 seconds
Started Jul 30 06:33:46 PM PDT 24
Finished Jul 30 06:35:07 PM PDT 24
Peak memory 207128 kb
Host smart-67b7da60-6cd5-47c8-93db-cdbe77378923
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=801802844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.801802844
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.1114856516
Short name T1621
Test name
Test status
Simulation time 230174059 ps
CPU time 0.95 seconds
Started Jul 30 06:33:50 PM PDT 24
Finished Jul 30 06:33:51 PM PDT 24
Peak memory 206916 kb
Host smart-085d9e7d-bdc9-4fca-b18a-5ab362ec0fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11148
56516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.1114856516
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.1859576898
Short name T1341
Test name
Test status
Simulation time 23298176532 ps
CPU time 33.23 seconds
Started Jul 30 06:33:47 PM PDT 24
Finished Jul 30 06:34:20 PM PDT 24
Peak memory 207104 kb
Host smart-0efe6359-46fb-47e3-96c1-72f34953e8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18595
76898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.1859576898
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1946226732
Short name T2356
Test name
Test status
Simulation time 3277506786 ps
CPU time 4.63 seconds
Started Jul 30 06:33:46 PM PDT 24
Finished Jul 30 06:33:51 PM PDT 24
Peak memory 207060 kb
Host smart-36f141de-8932-49d6-8268-65849da9212a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19462
26732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1946226732
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.248440116
Short name T782
Test name
Test status
Simulation time 6626964970 ps
CPU time 50.55 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:34:35 PM PDT 24
Peak memory 223548 kb
Host smart-adcf3bd9-acab-449f-9387-aca370e37b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24844
0116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.248440116
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3851488705
Short name T2477
Test name
Test status
Simulation time 5831340620 ps
CPU time 166.67 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:36:31 PM PDT 24
Peak memory 215268 kb
Host smart-a804579e-097e-4359-85f0-43841cc36743
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3851488705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3851488705
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1981628027
Short name T1486
Test name
Test status
Simulation time 241897763 ps
CPU time 0.99 seconds
Started Jul 30 06:33:46 PM PDT 24
Finished Jul 30 06:33:47 PM PDT 24
Peak memory 206936 kb
Host smart-54db33a6-e25f-478e-b8cf-ad0c1b9c8ee5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1981628027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1981628027
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.590736464
Short name T2595
Test name
Test status
Simulation time 189925042 ps
CPU time 0.95 seconds
Started Jul 30 06:33:46 PM PDT 24
Finished Jul 30 06:33:47 PM PDT 24
Peak memory 206944 kb
Host smart-6ee19362-fd22-47af-82d0-8210b6aa7186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59073
6464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.590736464
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3735406281
Short name T1718
Test name
Test status
Simulation time 3744574976 ps
CPU time 29.18 seconds
Started Jul 30 06:33:46 PM PDT 24
Finished Jul 30 06:34:16 PM PDT 24
Peak memory 215332 kb
Host smart-7f6e691f-1055-4055-98a3-a989f83bd1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37354
06281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3735406281
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2961943721
Short name T464
Test name
Test status
Simulation time 4140188001 ps
CPU time 33.91 seconds
Started Jul 30 06:33:45 PM PDT 24
Finished Jul 30 06:34:19 PM PDT 24
Peak memory 216676 kb
Host smart-d5cbe133-be55-460b-836f-025e9db277f1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2961943721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2961943721
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.2240511857
Short name T920
Test name
Test status
Simulation time 183423384 ps
CPU time 0.96 seconds
Started Jul 30 06:33:46 PM PDT 24
Finished Jul 30 06:33:47 PM PDT 24
Peak memory 206944 kb
Host smart-e698f5fe-57b6-46b0-8ee6-4b51423d77f2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2240511857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.2240511857
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.4145159326
Short name T1163
Test name
Test status
Simulation time 146429303 ps
CPU time 0.85 seconds
Started Jul 30 06:33:49 PM PDT 24
Finished Jul 30 06:33:50 PM PDT 24
Peak memory 206976 kb
Host smart-8a99ab82-e13c-46e4-ab49-82cfef045570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41451
59326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.4145159326
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.697340955
Short name T2628
Test name
Test status
Simulation time 217746410 ps
CPU time 0.95 seconds
Started Jul 30 06:33:50 PM PDT 24
Finished Jul 30 06:33:51 PM PDT 24
Peak memory 206916 kb
Host smart-26a5da41-2598-438a-a00a-7c2b0866271f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69734
0955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.697340955
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1496960825
Short name T359
Test name
Test status
Simulation time 212151504 ps
CPU time 1 seconds
Started Jul 30 06:33:51 PM PDT 24
Finished Jul 30 06:33:52 PM PDT 24
Peak memory 206952 kb
Host smart-f5464cc0-5178-4c05-a25a-799a537eb4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14969
60825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1496960825
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1395116891
Short name T646
Test name
Test status
Simulation time 197834601 ps
CPU time 0.95 seconds
Started Jul 30 06:33:53 PM PDT 24
Finished Jul 30 06:33:54 PM PDT 24
Peak memory 206888 kb
Host smart-1ccfce41-b3db-49f9-852c-07b6d3a1073a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13951
16891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1395116891
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3967861081
Short name T2034
Test name
Test status
Simulation time 158494616 ps
CPU time 0.86 seconds
Started Jul 30 06:33:52 PM PDT 24
Finished Jul 30 06:33:53 PM PDT 24
Peak memory 206976 kb
Host smart-b7a6ffae-9177-481f-ac59-7ddc1e835660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39678
61081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3967861081
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.21791438
Short name T173
Test name
Test status
Simulation time 166371027 ps
CPU time 0.92 seconds
Started Jul 30 06:33:50 PM PDT 24
Finished Jul 30 06:33:51 PM PDT 24
Peak memory 206908 kb
Host smart-201ee7ce-dc8c-4b9c-9a6e-a95ead3fdcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21791
438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.21791438
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.2529020410
Short name T2221
Test name
Test status
Simulation time 244910758 ps
CPU time 1.19 seconds
Started Jul 30 06:33:53 PM PDT 24
Finished Jul 30 06:33:54 PM PDT 24
Peak memory 206924 kb
Host smart-cad778cc-8b8c-4859-a418-745f4052c6b9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2529020410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.2529020410
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1958404340
Short name T1003
Test name
Test status
Simulation time 178666376 ps
CPU time 0.85 seconds
Started Jul 30 06:33:54 PM PDT 24
Finished Jul 30 06:33:55 PM PDT 24
Peak memory 206864 kb
Host smart-74d57fa5-a6d9-461c-bba6-14119401e665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19584
04340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1958404340
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.978026936
Short name T2347
Test name
Test status
Simulation time 43278294 ps
CPU time 0.67 seconds
Started Jul 30 06:33:51 PM PDT 24
Finished Jul 30 06:33:52 PM PDT 24
Peak memory 206932 kb
Host smart-8a531db5-b140-4218-8572-a888d7fb4373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97802
6936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.978026936
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1408614814
Short name T2103
Test name
Test status
Simulation time 21332161188 ps
CPU time 59.93 seconds
Started Jul 30 06:33:49 PM PDT 24
Finished Jul 30 06:34:49 PM PDT 24
Peak memory 215356 kb
Host smart-b59bbe1a-9ee0-4b77-94af-8c0e7132cb16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14086
14814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1408614814
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1583434428
Short name T2109
Test name
Test status
Simulation time 155939588 ps
CPU time 0.87 seconds
Started Jul 30 06:33:50 PM PDT 24
Finished Jul 30 06:33:51 PM PDT 24
Peak memory 206912 kb
Host smart-ceee55ee-8450-4b22-807c-b44920be8fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15834
34428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1583434428
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.782202256
Short name T1645
Test name
Test status
Simulation time 155136386 ps
CPU time 0.87 seconds
Started Jul 30 06:33:52 PM PDT 24
Finished Jul 30 06:33:53 PM PDT 24
Peak memory 206968 kb
Host smart-b4605794-1dbe-4306-8b43-d60f381c8860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78220
2256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.782202256
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.2191537171
Short name T2054
Test name
Test status
Simulation time 230989478 ps
CPU time 0.95 seconds
Started Jul 30 06:34:11 PM PDT 24
Finished Jul 30 06:34:12 PM PDT 24
Peak memory 206904 kb
Host smart-ea275745-7891-484e-81c8-dd37e50ff4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21915
37171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.2191537171
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.3210996803
Short name T2720
Test name
Test status
Simulation time 184724558 ps
CPU time 0.9 seconds
Started Jul 30 06:34:05 PM PDT 24
Finished Jul 30 06:34:06 PM PDT 24
Peak memory 206940 kb
Host smart-65c3d8c4-2b8d-4f59-9972-20d074d334fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32109
96803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3210996803
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.704668423
Short name T2831
Test name
Test status
Simulation time 174750717 ps
CPU time 0.86 seconds
Started Jul 30 06:33:55 PM PDT 24
Finished Jul 30 06:33:56 PM PDT 24
Peak memory 206884 kb
Host smart-7bd79954-6267-465f-ab8b-1212374e7da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70466
8423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.704668423
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3802466407
Short name T599
Test name
Test status
Simulation time 193994568 ps
CPU time 0.93 seconds
Started Jul 30 06:34:15 PM PDT 24
Finished Jul 30 06:34:16 PM PDT 24
Peak memory 206948 kb
Host smart-3a845cff-e654-4afb-8992-8b6270d48bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38024
66407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3802466407
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3026999202
Short name T732
Test name
Test status
Simulation time 155090729 ps
CPU time 0.82 seconds
Started Jul 30 06:33:54 PM PDT 24
Finished Jul 30 06:33:55 PM PDT 24
Peak memory 206904 kb
Host smart-ef332e37-92df-4fa9-a712-dbfabe547e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30269
99202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3026999202
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3818691053
Short name T1325
Test name
Test status
Simulation time 243130235 ps
CPU time 1.04 seconds
Started Jul 30 06:33:54 PM PDT 24
Finished Jul 30 06:33:55 PM PDT 24
Peak memory 206912 kb
Host smart-ab19846a-ad92-4979-acf6-ee9164cf7ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38186
91053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3818691053
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2001990386
Short name T612
Test name
Test status
Simulation time 5275429144 ps
CPU time 40.32 seconds
Started Jul 30 06:33:53 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 216588 kb
Host smart-71c999b0-7fdd-4ca5-ba04-e6325e82ec1e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2001990386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2001990386
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3309902946
Short name T1357
Test name
Test status
Simulation time 162760960 ps
CPU time 0.88 seconds
Started Jul 30 06:33:56 PM PDT 24
Finished Jul 30 06:33:57 PM PDT 24
Peak memory 206944 kb
Host smart-07b4c109-66e1-4c77-9f79-57b97b412cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33099
02946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3309902946
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2625687923
Short name T1449
Test name
Test status
Simulation time 181643229 ps
CPU time 0.96 seconds
Started Jul 30 06:33:56 PM PDT 24
Finished Jul 30 06:34:02 PM PDT 24
Peak memory 206908 kb
Host smart-009560dc-fa56-4fa3-a9d7-dc80c0598214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26256
87923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2625687923
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.772243074
Short name T2631
Test name
Test status
Simulation time 277348480 ps
CPU time 1.09 seconds
Started Jul 30 06:33:54 PM PDT 24
Finished Jul 30 06:33:55 PM PDT 24
Peak memory 206944 kb
Host smart-73bb041c-1657-4022-b05d-30fac17a3ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77224
3074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.772243074
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.1774338702
Short name T1517
Test name
Test status
Simulation time 2723774215 ps
CPU time 80.03 seconds
Started Jul 30 06:34:08 PM PDT 24
Finished Jul 30 06:35:28 PM PDT 24
Peak memory 215368 kb
Host smart-aa495286-b9f7-472a-a9aa-dff0bbc4cbb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17743
38702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.1774338702
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.79555517
Short name T1147
Test name
Test status
Simulation time 663447936 ps
CPU time 11.61 seconds
Started Jul 30 06:33:51 PM PDT 24
Finished Jul 30 06:34:02 PM PDT 24
Peak memory 207012 kb
Host smart-4a846fe5-7d88-45d6-89ca-af6e2f9c13de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79555517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_host_
handshake.79555517
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.4031835863
Short name T1230
Test name
Test status
Simulation time 55605060 ps
CPU time 0.7 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 207032 kb
Host smart-e61aa21a-76c0-4bd7-b2f0-acfa86783990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4031835863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.4031835863
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3221086525
Short name T196
Test name
Test status
Simulation time 3761716819 ps
CPU time 6.08 seconds
Started Jul 30 06:34:07 PM PDT 24
Finished Jul 30 06:34:13 PM PDT 24
Peak memory 207100 kb
Host smart-01369560-485f-4680-b3e5-bf3857bd84f8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221086525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.3221086525
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2452882168
Short name T904
Test name
Test status
Simulation time 13380843064 ps
CPU time 17.67 seconds
Started Jul 30 06:34:06 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 207100 kb
Host smart-fd64d0ad-f1cc-4245-a530-19feec3ddeeb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452882168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2452882168
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1272054111
Short name T2825
Test name
Test status
Simulation time 23390561891 ps
CPU time 29.37 seconds
Started Jul 30 06:34:18 PM PDT 24
Finished Jul 30 06:34:47 PM PDT 24
Peak memory 207132 kb
Host smart-d4e93b64-2f77-41f2-a2b4-0fe415df6d7c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272054111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.1272054111
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1061992330
Short name T884
Test name
Test status
Simulation time 185847085 ps
CPU time 0.99 seconds
Started Jul 30 06:34:04 PM PDT 24
Finished Jul 30 06:34:05 PM PDT 24
Peak memory 206932 kb
Host smart-a6c37bd4-f2d5-4007-a41d-7ab76f3c5ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10619
92330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1061992330
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.374687827
Short name T2397
Test name
Test status
Simulation time 159645569 ps
CPU time 0.89 seconds
Started Jul 30 06:33:57 PM PDT 24
Finished Jul 30 06:33:58 PM PDT 24
Peak memory 206876 kb
Host smart-248361f4-bc92-47ec-a81b-a76d97893090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37468
7827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.374687827
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.2118465460
Short name T2343
Test name
Test status
Simulation time 326980772 ps
CPU time 1.26 seconds
Started Jul 30 06:34:00 PM PDT 24
Finished Jul 30 06:34:01 PM PDT 24
Peak memory 206968 kb
Host smart-8862d3c3-df09-4f3e-b05a-07893a3f288b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21184
65460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.2118465460
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.104791925
Short name T1852
Test name
Test status
Simulation time 439128868 ps
CPU time 1.33 seconds
Started Jul 30 06:34:09 PM PDT 24
Finished Jul 30 06:34:11 PM PDT 24
Peak memory 206892 kb
Host smart-76d7ae74-c433-4069-9f68-24a216bb20c2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=104791925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.104791925
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.3986006728
Short name T2481
Test name
Test status
Simulation time 15446721771 ps
CPU time 34.6 seconds
Started Jul 30 06:34:15 PM PDT 24
Finished Jul 30 06:34:49 PM PDT 24
Peak memory 207164 kb
Host smart-2686de7d-9eef-49f2-9058-6f6aa4095000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39860
06728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.3986006728
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.880927700
Short name T589
Test name
Test status
Simulation time 1446152356 ps
CPU time 33.6 seconds
Started Jul 30 06:34:15 PM PDT 24
Finished Jul 30 06:34:49 PM PDT 24
Peak memory 207020 kb
Host smart-6d5cd377-adae-4c0c-b79b-1ab1f4bf5f8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880927700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.880927700
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3696344593
Short name T302
Test name
Test status
Simulation time 329697690 ps
CPU time 1.3 seconds
Started Jul 30 06:33:57 PM PDT 24
Finished Jul 30 06:33:59 PM PDT 24
Peak memory 206896 kb
Host smart-9a2ff6c6-edb8-4157-848f-6a973d1b8869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36963
44593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3696344593
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.4000153755
Short name T2049
Test name
Test status
Simulation time 141846045 ps
CPU time 0.86 seconds
Started Jul 30 06:33:57 PM PDT 24
Finished Jul 30 06:33:58 PM PDT 24
Peak memory 206912 kb
Host smart-0cd31711-06b7-44dc-948a-c3d6dd423368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40001
53755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.4000153755
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.569178243
Short name T479
Test name
Test status
Simulation time 49518400 ps
CPU time 0.74 seconds
Started Jul 30 06:34:03 PM PDT 24
Finished Jul 30 06:34:04 PM PDT 24
Peak memory 206872 kb
Host smart-bd9cec2e-016d-46a2-a923-f08dad0c7887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56917
8243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.569178243
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3802950654
Short name T339
Test name
Test status
Simulation time 871939222 ps
CPU time 2.31 seconds
Started Jul 30 06:34:13 PM PDT 24
Finished Jul 30 06:34:16 PM PDT 24
Peak memory 207048 kb
Host smart-be0ada08-82a6-4e2b-b431-93a6c1cfd968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38029
50654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3802950654
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3138463280
Short name T1297
Test name
Test status
Simulation time 193433234 ps
CPU time 2.41 seconds
Started Jul 30 06:34:18 PM PDT 24
Finished Jul 30 06:34:21 PM PDT 24
Peak memory 207032 kb
Host smart-df5e26b2-54e6-46c4-9bf7-43671c8ced42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31384
63280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3138463280
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1303419852
Short name T2387
Test name
Test status
Simulation time 173268880 ps
CPU time 0.98 seconds
Started Jul 30 06:33:58 PM PDT 24
Finished Jul 30 06:33:59 PM PDT 24
Peak memory 215240 kb
Host smart-216d0271-7856-4807-8a13-9104d7c6a8dc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1303419852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1303419852
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2510209214
Short name T1835
Test name
Test status
Simulation time 143077807 ps
CPU time 0.84 seconds
Started Jul 30 06:34:02 PM PDT 24
Finished Jul 30 06:34:03 PM PDT 24
Peak memory 206888 kb
Host smart-1575a532-c2d8-48fe-8eb5-98f48b4d2f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25102
09214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2510209214
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.297151186
Short name T1519
Test name
Test status
Simulation time 197469095 ps
CPU time 0.94 seconds
Started Jul 30 06:34:21 PM PDT 24
Finished Jul 30 06:34:22 PM PDT 24
Peak memory 206960 kb
Host smart-6e10d973-36ed-4c4d-ba20-e44d91581547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29715
1186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.297151186
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.2170041972
Short name T1744
Test name
Test status
Simulation time 5562744538 ps
CPU time 41.3 seconds
Started Jul 30 06:33:58 PM PDT 24
Finished Jul 30 06:34:39 PM PDT 24
Peak memory 215300 kb
Host smart-3ed2e093-0615-41b6-97b0-3dcbfba899a8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2170041972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.2170041972
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.3199676217
Short name T766
Test name
Test status
Simulation time 6304441621 ps
CPU time 43.63 seconds
Started Jul 30 06:34:18 PM PDT 24
Finished Jul 30 06:35:01 PM PDT 24
Peak memory 207116 kb
Host smart-c4361a0f-6257-4ad5-b4fb-17f46b344f0c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3199676217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.3199676217
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3290320066
Short name T1847
Test name
Test status
Simulation time 232933446 ps
CPU time 0.98 seconds
Started Jul 30 06:34:11 PM PDT 24
Finished Jul 30 06:34:12 PM PDT 24
Peak memory 206928 kb
Host smart-ace5e443-7d92-4671-a141-1b929406fb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32903
20066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3290320066
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1304290392
Short name T636
Test name
Test status
Simulation time 23287020246 ps
CPU time 30.07 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:34:54 PM PDT 24
Peak memory 207128 kb
Host smart-c00654c4-7c79-44a9-9774-fb4d3e7cd259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13042
90392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1304290392
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2612112291
Short name T2662
Test name
Test status
Simulation time 3303303946 ps
CPU time 5 seconds
Started Jul 30 06:34:14 PM PDT 24
Finished Jul 30 06:34:19 PM PDT 24
Peak memory 207048 kb
Host smart-4a3a3317-fc10-46e8-a239-b93a5388f934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26121
12291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2612112291
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.2800908694
Short name T1002
Test name
Test status
Simulation time 7771086060 ps
CPU time 61.67 seconds
Started Jul 30 06:34:15 PM PDT 24
Finished Jul 30 06:35:17 PM PDT 24
Peak memory 217104 kb
Host smart-5b3b684f-9e00-44c7-8542-1043ba2ea217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28009
08694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2800908694
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.24234204
Short name T1440
Test name
Test status
Simulation time 3954767026 ps
CPU time 29.05 seconds
Started Jul 30 06:34:17 PM PDT 24
Finished Jul 30 06:34:46 PM PDT 24
Peak memory 216728 kb
Host smart-ae31b3a8-cb64-4787-b064-db2733c6c11f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=24234204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.24234204
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.3900277001
Short name T1710
Test name
Test status
Simulation time 245887978 ps
CPU time 1.03 seconds
Started Jul 30 06:34:16 PM PDT 24
Finished Jul 30 06:34:17 PM PDT 24
Peak memory 206944 kb
Host smart-2d490da5-8de7-49d5-b27e-c0954f45dda7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3900277001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.3900277001
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2894089044
Short name T2058
Test name
Test status
Simulation time 220232715 ps
CPU time 1.02 seconds
Started Jul 30 06:34:19 PM PDT 24
Finished Jul 30 06:34:20 PM PDT 24
Peak memory 206912 kb
Host smart-2bbc89eb-521a-4dc7-ac90-f1ab6eca1d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28940
89044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2894089044
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.2210795119
Short name T1779
Test name
Test status
Simulation time 4406974749 ps
CPU time 33.93 seconds
Started Jul 30 06:34:13 PM PDT 24
Finished Jul 30 06:34:47 PM PDT 24
Peak memory 216916 kb
Host smart-3c7069d0-767b-43b4-90d3-c62f84753a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22107
95119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.2210795119
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.1260586124
Short name T1691
Test name
Test status
Simulation time 5400254650 ps
CPU time 43.2 seconds
Started Jul 30 06:34:07 PM PDT 24
Finished Jul 30 06:34:50 PM PDT 24
Peak memory 215332 kb
Host smart-f2cac114-300f-4503-befa-b1f4c786b90c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1260586124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.1260586124
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.1361758161
Short name T1446
Test name
Test status
Simulation time 149899216 ps
CPU time 0.86 seconds
Started Jul 30 06:34:14 PM PDT 24
Finished Jul 30 06:34:15 PM PDT 24
Peak memory 206940 kb
Host smart-faff79dd-886f-4832-a502-359a3dbdce7a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1361758161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.1361758161
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3684655267
Short name T2552
Test name
Test status
Simulation time 149291377 ps
CPU time 0.86 seconds
Started Jul 30 06:34:06 PM PDT 24
Finished Jul 30 06:34:07 PM PDT 24
Peak memory 206924 kb
Host smart-89d43d25-9e76-49ea-9c9a-e13c19714605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36846
55267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3684655267
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2449431800
Short name T125
Test name
Test status
Simulation time 193147386 ps
CPU time 0.98 seconds
Started Jul 30 06:34:17 PM PDT 24
Finished Jul 30 06:34:18 PM PDT 24
Peak memory 206924 kb
Host smart-cae6e6eb-1f58-4f6a-8721-c8179b3cfc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24494
31800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2449431800
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.1597703240
Short name T2393
Test name
Test status
Simulation time 150796712 ps
CPU time 0.91 seconds
Started Jul 30 06:34:19 PM PDT 24
Finished Jul 30 06:34:20 PM PDT 24
Peak memory 206952 kb
Host smart-1c52acf3-c8c2-4a7f-9fce-6505de801310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15977
03240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1597703240
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.4155360570
Short name T1602
Test name
Test status
Simulation time 184799787 ps
CPU time 0.86 seconds
Started Jul 30 06:34:19 PM PDT 24
Finished Jul 30 06:34:20 PM PDT 24
Peak memory 206940 kb
Host smart-80144e3b-429c-40f2-9d8d-f5ef01f06b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41553
60570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.4155360570
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2531901448
Short name T57
Test name
Test status
Simulation time 157939554 ps
CPU time 0.83 seconds
Started Jul 30 06:34:16 PM PDT 24
Finished Jul 30 06:34:17 PM PDT 24
Peak memory 206912 kb
Host smart-7a40a97c-8f4c-4c4d-8302-e82ffad397d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25319
01448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2531901448
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3854584322
Short name T2335
Test name
Test status
Simulation time 183464337 ps
CPU time 0.88 seconds
Started Jul 30 06:34:14 PM PDT 24
Finished Jul 30 06:34:15 PM PDT 24
Peak memory 206908 kb
Host smart-78654933-90f7-4dee-a0c8-2dbc4d9fda47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38545
84322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3854584322
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.710491806
Short name T2150
Test name
Test status
Simulation time 221153264 ps
CPU time 0.96 seconds
Started Jul 30 06:34:19 PM PDT 24
Finished Jul 30 06:34:20 PM PDT 24
Peak memory 206948 kb
Host smart-910b5d56-aafd-40ec-9c3d-5204e9fdd1b4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=710491806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.710491806
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2550917558
Short name T1669
Test name
Test status
Simulation time 152671588 ps
CPU time 0.85 seconds
Started Jul 30 06:34:03 PM PDT 24
Finished Jul 30 06:34:04 PM PDT 24
Peak memory 206900 kb
Host smart-e9118746-b65d-4395-8922-3bca30d78e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25509
17558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2550917558
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1654806747
Short name T1332
Test name
Test status
Simulation time 37704392 ps
CPU time 0.68 seconds
Started Jul 30 06:34:16 PM PDT 24
Finished Jul 30 06:34:17 PM PDT 24
Peak memory 206892 kb
Host smart-16bbaf90-3106-41dd-85f2-32cb7317325d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16548
06747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1654806747
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1324081429
Short name T2656
Test name
Test status
Simulation time 17972693289 ps
CPU time 44.51 seconds
Started Jul 30 06:34:12 PM PDT 24
Finished Jul 30 06:34:56 PM PDT 24
Peak memory 215108 kb
Host smart-58cb5c2c-73ea-48ab-9cd6-163d3a66cf6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13240
81429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1324081429
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1273003454
Short name T657
Test name
Test status
Simulation time 186268962 ps
CPU time 0.91 seconds
Started Jul 30 06:34:18 PM PDT 24
Finished Jul 30 06:34:19 PM PDT 24
Peak memory 206908 kb
Host smart-9a67f651-9d04-46d8-8987-d19463776ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12730
03454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1273003454
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3781007709
Short name T958
Test name
Test status
Simulation time 180461598 ps
CPU time 0.99 seconds
Started Jul 30 06:34:09 PM PDT 24
Finished Jul 30 06:34:10 PM PDT 24
Peak memory 206984 kb
Host smart-5f3b685d-5c70-42a9-afa7-9b6a83c25069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37810
07709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3781007709
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.4061882458
Short name T2617
Test name
Test status
Simulation time 227843254 ps
CPU time 0.97 seconds
Started Jul 30 06:34:11 PM PDT 24
Finished Jul 30 06:34:13 PM PDT 24
Peak memory 206988 kb
Host smart-ecfc119b-c07b-42b1-bfd8-6d93ba8a7666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40618
82458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.4061882458
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3974769946
Short name T760
Test name
Test status
Simulation time 157983511 ps
CPU time 0.94 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 206948 kb
Host smart-b4ac483d-66ec-4716-98ac-f732b0d18925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39747
69946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3974769946
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2909277183
Short name T1910
Test name
Test status
Simulation time 152962587 ps
CPU time 0.86 seconds
Started Jul 30 06:34:14 PM PDT 24
Finished Jul 30 06:34:15 PM PDT 24
Peak memory 206928 kb
Host smart-f5594267-fd33-46c6-92e3-eff9ce16d9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29092
77183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2909277183
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2697241891
Short name T1474
Test name
Test status
Simulation time 195446314 ps
CPU time 0.92 seconds
Started Jul 30 06:34:15 PM PDT 24
Finished Jul 30 06:34:16 PM PDT 24
Peak memory 206908 kb
Host smart-8c356f56-5116-469b-a7df-a1af5ab31ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26972
41891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2697241891
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2532126514
Short name T1616
Test name
Test status
Simulation time 188689750 ps
CPU time 0.95 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 206936 kb
Host smart-0e261c9f-b26d-4938-9c83-75729e9778df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25321
26514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2532126514
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1589633810
Short name T1078
Test name
Test status
Simulation time 6294995662 ps
CPU time 63 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:35:27 PM PDT 24
Peak memory 215340 kb
Host smart-270a60b2-eff2-451c-9cd6-1209a4bad186
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1589633810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1589633810
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2254655204
Short name T535
Test name
Test status
Simulation time 158338641 ps
CPU time 0.85 seconds
Started Jul 30 06:34:06 PM PDT 24
Finished Jul 30 06:34:07 PM PDT 24
Peak memory 206944 kb
Host smart-d4dce0b1-3a20-4035-b8ca-8879f0b243e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22546
55204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2254655204
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.1389767002
Short name T2673
Test name
Test status
Simulation time 165574461 ps
CPU time 0.89 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 206904 kb
Host smart-580eba0b-653b-456a-8bc2-d60444a64a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13897
67002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.1389767002
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.572963673
Short name T1699
Test name
Test status
Simulation time 937735977 ps
CPU time 2.54 seconds
Started Jul 30 06:34:18 PM PDT 24
Finished Jul 30 06:34:20 PM PDT 24
Peak memory 206964 kb
Host smart-1995e7a6-3345-491b-93c1-12dadc43db55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57296
3673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.572963673
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.819608271
Short name T2747
Test name
Test status
Simulation time 3075585019 ps
CPU time 23.62 seconds
Started Jul 30 06:34:21 PM PDT 24
Finished Jul 30 06:34:45 PM PDT 24
Peak memory 216748 kb
Host smart-b461c101-358c-4408-a2d2-b45796aadd74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81960
8271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.819608271
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.4204286369
Short name T1777
Test name
Test status
Simulation time 3609901607 ps
CPU time 23.43 seconds
Started Jul 30 06:34:03 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 207128 kb
Host smart-26150924-4e07-4697-9569-dd3c4ee1ed21
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204286369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.4204286369
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.818374768
Short name T1454
Test name
Test status
Simulation time 43054816 ps
CPU time 0.7 seconds
Started Jul 30 06:34:32 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 206928 kb
Host smart-675aa8d2-f091-4da9-aee3-c234db147d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=818374768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.818374768
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3774023612
Short name T1280
Test name
Test status
Simulation time 4418949927 ps
CPU time 5.96 seconds
Started Jul 30 06:34:20 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 207072 kb
Host smart-e8926686-8ea8-4da5-b89d-a67103af1d12
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774023612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.3774023612
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1665767308
Short name T15
Test name
Test status
Simulation time 13318081132 ps
CPU time 16.84 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:44 PM PDT 24
Peak memory 207156 kb
Host smart-11a2e16f-43da-4bf8-809f-b6d6eec78726
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665767308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1665767308
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.774044017
Short name T2493
Test name
Test status
Simulation time 23419500035 ps
CPU time 33.84 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:35:01 PM PDT 24
Peak memory 207136 kb
Host smart-ad2647da-9cf3-4d58-9e91-adf2d8a3ec50
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774044017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_ao
n_wake_resume.774044017
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2134854804
Short name T804
Test name
Test status
Simulation time 199646351 ps
CPU time 0.98 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 206928 kb
Host smart-aec784f3-1565-4416-bb1c-ae142c1b5967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21348
54804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2134854804
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.2894879994
Short name T412
Test name
Test status
Simulation time 177848154 ps
CPU time 0.89 seconds
Started Jul 30 06:34:11 PM PDT 24
Finished Jul 30 06:34:12 PM PDT 24
Peak memory 206884 kb
Host smart-71efcf92-e38d-4b18-bfa5-08f511e0dcb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28948
79994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.2894879994
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.534496793
Short name T2160
Test name
Test status
Simulation time 196637313 ps
CPU time 0.92 seconds
Started Jul 30 06:34:16 PM PDT 24
Finished Jul 30 06:34:17 PM PDT 24
Peak memory 207080 kb
Host smart-50d58e92-d0db-42e6-b962-7186ee89f878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53449
6793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.534496793
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1762068227
Short name T1209
Test name
Test status
Simulation time 308320416 ps
CPU time 1.06 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 206924 kb
Host smart-9ae9bd50-f6be-4cca-b609-9cbacd52475b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1762068227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1762068227
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.4243395243
Short name T1996
Test name
Test status
Simulation time 15962007984 ps
CPU time 32.46 seconds
Started Jul 30 06:34:16 PM PDT 24
Finished Jul 30 06:34:48 PM PDT 24
Peak memory 207152 kb
Host smart-ea643f5f-8e4f-4427-b422-0d13fb7e2f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42433
95243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.4243395243
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.473613152
Short name T390
Test name
Test status
Simulation time 1954919854 ps
CPU time 46.73 seconds
Started Jul 30 06:34:22 PM PDT 24
Finished Jul 30 06:35:09 PM PDT 24
Peak memory 206960 kb
Host smart-1731e6be-cad1-41f3-91d8-3e7df09b9e46
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473613152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.473613152
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3564175767
Short name T1029
Test name
Test status
Simulation time 451809525 ps
CPU time 1.43 seconds
Started Jul 30 06:34:13 PM PDT 24
Finished Jul 30 06:34:14 PM PDT 24
Peak memory 206904 kb
Host smart-2bdc9a60-a67d-4431-96be-3c081e37e90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35641
75767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3564175767
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1668793951
Short name T2189
Test name
Test status
Simulation time 138750405 ps
CPU time 0.85 seconds
Started Jul 30 06:34:20 PM PDT 24
Finished Jul 30 06:34:21 PM PDT 24
Peak memory 206896 kb
Host smart-05992520-6e3b-4f2f-86a5-db132f10fb22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16687
93951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1668793951
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.160945861
Short name T2685
Test name
Test status
Simulation time 38003921 ps
CPU time 0.7 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206916 kb
Host smart-e9af20f6-8935-4452-9a79-e2789efb8fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16094
5861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.160945861
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3415272307
Short name T821
Test name
Test status
Simulation time 1030335835 ps
CPU time 2.81 seconds
Started Jul 30 06:34:26 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 207028 kb
Host smart-afbc11a8-b6e9-4a7d-b5af-421fc073f473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34152
72307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3415272307
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.625344756
Short name T872
Test name
Test status
Simulation time 270975145 ps
CPU time 1.73 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 206968 kb
Host smart-1d89666d-8386-4054-a2ae-e0855c19a1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62534
4756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.625344756
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.227568606
Short name T2228
Test name
Test status
Simulation time 240199405 ps
CPU time 1.14 seconds
Started Jul 30 06:34:20 PM PDT 24
Finished Jul 30 06:34:21 PM PDT 24
Peak memory 207008 kb
Host smart-356333d3-dfed-4689-ac46-bc4f0586fccb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=227568606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.227568606
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1617397308
Short name T1019
Test name
Test status
Simulation time 142480673 ps
CPU time 0.85 seconds
Started Jul 30 06:34:17 PM PDT 24
Finished Jul 30 06:34:18 PM PDT 24
Peak memory 206952 kb
Host smart-9a7f5ff7-1f8b-4261-a689-81d7d14432c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16173
97308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1617397308
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.4162831846
Short name T1154
Test name
Test status
Simulation time 227939650 ps
CPU time 1.16 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 206916 kb
Host smart-afdcb0fd-d0d9-4ad4-a806-f34af3fabf10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41628
31846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.4162831846
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.1220380262
Short name T2504
Test name
Test status
Simulation time 7708807223 ps
CPU time 63.66 seconds
Started Jul 30 06:34:22 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 215352 kb
Host smart-b06e1861-77d4-4378-afe9-eeb1e1ab5915
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1220380262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.1220380262
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.3079745841
Short name T1820
Test name
Test status
Simulation time 10223639476 ps
CPU time 125.31 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:36:32 PM PDT 24
Peak memory 207156 kb
Host smart-4e57f531-e17c-45cd-8b23-07051e4806b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3079745841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.3079745841
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.2289241439
Short name T1841
Test name
Test status
Simulation time 246673283 ps
CPU time 1.1 seconds
Started Jul 30 06:34:20 PM PDT 24
Finished Jul 30 06:34:21 PM PDT 24
Peak memory 206948 kb
Host smart-ab488585-bec6-4eff-8a36-63df34bb0b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22892
41439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2289241439
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.2856539698
Short name T960
Test name
Test status
Simulation time 23323834942 ps
CPU time 28.09 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:53 PM PDT 24
Peak memory 207160 kb
Host smart-ca9da54b-07d8-4ac0-b982-2fa162e17e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28565
39698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.2856539698
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1486199721
Short name T1050
Test name
Test status
Simulation time 3281923022 ps
CPU time 5.28 seconds
Started Jul 30 06:34:17 PM PDT 24
Finished Jul 30 06:34:22 PM PDT 24
Peak memory 207040 kb
Host smart-8f08ce4f-6aad-4afc-a899-4d203b176194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14861
99721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1486199721
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.393014594
Short name T488
Test name
Test status
Simulation time 7822627646 ps
CPU time 82.39 seconds
Started Jul 30 06:34:16 PM PDT 24
Finished Jul 30 06:35:38 PM PDT 24
Peak memory 217116 kb
Host smart-b13c1826-384c-4792-8e94-b69a3adaa3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39301
4594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.393014594
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.3060984500
Short name T2057
Test name
Test status
Simulation time 3624010250 ps
CPU time 97.15 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:36:01 PM PDT 24
Peak memory 215356 kb
Host smart-d4ff1856-b88a-4789-a139-9feec3d1ad2e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3060984500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.3060984500
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2273636953
Short name T1366
Test name
Test status
Simulation time 238918147 ps
CPU time 1.18 seconds
Started Jul 30 06:35:53 PM PDT 24
Finished Jul 30 06:35:54 PM PDT 24
Peak memory 206956 kb
Host smart-86be2874-4073-4751-aa70-b76c8fe4b815
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2273636953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2273636953
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.4117620421
Short name T853
Test name
Test status
Simulation time 234293498 ps
CPU time 0.96 seconds
Started Jul 30 06:34:20 PM PDT 24
Finished Jul 30 06:34:22 PM PDT 24
Peak memory 206920 kb
Host smart-ad651ccc-64f9-4d93-b88e-b19f588b6895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41176
20421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.4117620421
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2325392605
Short name T2215
Test name
Test status
Simulation time 5018594847 ps
CPU time 141.29 seconds
Started Jul 30 06:34:20 PM PDT 24
Finished Jul 30 06:36:42 PM PDT 24
Peak memory 215300 kb
Host smart-406b4dbd-e424-4433-b203-541d61d3355f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23253
92605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2325392605
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3031633664
Short name T1582
Test name
Test status
Simulation time 6573986381 ps
CPU time 53.74 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:35:17 PM PDT 24
Peak memory 207144 kb
Host smart-87393605-349f-42b5-b8c4-a315ef58d3a4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3031633664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3031633664
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2871128207
Short name T739
Test name
Test status
Simulation time 209203481 ps
CPU time 0.9 seconds
Started Jul 30 06:34:16 PM PDT 24
Finished Jul 30 06:34:17 PM PDT 24
Peak memory 206936 kb
Host smart-d62ed34c-7d93-46b0-91b0-57cfcc6948f8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2871128207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2871128207
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2338486393
Short name T1333
Test name
Test status
Simulation time 147859675 ps
CPU time 0.84 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206972 kb
Host smart-c5e68590-0890-41b3-a935-64791a3c97a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23384
86393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2338486393
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3407736907
Short name T1907
Test name
Test status
Simulation time 207811881 ps
CPU time 0.97 seconds
Started Jul 30 06:34:14 PM PDT 24
Finished Jul 30 06:34:15 PM PDT 24
Peak memory 206948 kb
Host smart-6dbd7d1a-f311-45a5-bcbd-6061b7b7a8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34077
36907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3407736907
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.3792822722
Short name T1344
Test name
Test status
Simulation time 151014709 ps
CPU time 0.89 seconds
Started Jul 30 06:34:19 PM PDT 24
Finished Jul 30 06:34:20 PM PDT 24
Peak memory 206944 kb
Host smart-61eb3d93-9b23-4e37-ae45-50c2a7ea8ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37928
22722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.3792822722
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3701896416
Short name T800
Test name
Test status
Simulation time 216717257 ps
CPU time 0.95 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:34:25 PM PDT 24
Peak memory 206976 kb
Host smart-67283bdb-4fbb-4f97-9162-7a5ace63eb66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37018
96416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3701896416
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1146811910
Short name T1393
Test name
Test status
Simulation time 220769790 ps
CPU time 0.94 seconds
Started Jul 30 06:34:20 PM PDT 24
Finished Jul 30 06:34:21 PM PDT 24
Peak memory 206924 kb
Host smart-e536b5f4-a337-4506-a00c-2f722da6bb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11468
11910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1146811910
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1966010371
Short name T2101
Test name
Test status
Simulation time 158134235 ps
CPU time 0.84 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206928 kb
Host smart-38ee5ffb-e3dc-408d-aa90-fd84ed0ed2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19660
10371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1966010371
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3496110422
Short name T632
Test name
Test status
Simulation time 219359835 ps
CPU time 1.01 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 206928 kb
Host smart-94d12cb8-db23-44b1-bd03-7413d7412741
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3496110422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3496110422
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.616647675
Short name T1504
Test name
Test status
Simulation time 142265478 ps
CPU time 0.83 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 206876 kb
Host smart-ea85c327-8ab4-43ea-9d19-0387273b08f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61664
7675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.616647675
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.328145884
Short name T2849
Test name
Test status
Simulation time 71080224 ps
CPU time 0.73 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206928 kb
Host smart-f5142d41-5def-4c80-a8ad-7f248c91fa12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32814
5884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.328145884
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.3436282020
Short name T944
Test name
Test status
Simulation time 8192419888 ps
CPU time 20.73 seconds
Started Jul 30 06:34:19 PM PDT 24
Finished Jul 30 06:34:40 PM PDT 24
Peak memory 215296 kb
Host smart-ebdb7a2a-c593-4e66-a96a-d6bda2972a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34362
82020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.3436282020
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1057940921
Short name T2096
Test name
Test status
Simulation time 178023971 ps
CPU time 0.96 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206952 kb
Host smart-3f30a6ed-e707-4563-9e18-9712a15e02da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10579
40921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1057940921
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3396179575
Short name T2713
Test name
Test status
Simulation time 262359014 ps
CPU time 1.05 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206980 kb
Host smart-f3dc36b4-5d15-4509-b5e8-efb599c9a1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33961
79575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3396179575
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.867365209
Short name T2511
Test name
Test status
Simulation time 235017774 ps
CPU time 0.96 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 206920 kb
Host smart-0590ebe7-5750-4873-9786-5dcb7501e8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86736
5209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.867365209
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2129353957
Short name T2850
Test name
Test status
Simulation time 166384022 ps
CPU time 0.92 seconds
Started Jul 30 06:34:22 PM PDT 24
Finished Jul 30 06:34:23 PM PDT 24
Peak memory 206984 kb
Host smart-516d376d-3493-45a8-a9c1-d099fa7e21f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21293
53957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2129353957
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1042410905
Short name T2675
Test name
Test status
Simulation time 180570920 ps
CPU time 0.86 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:34:25 PM PDT 24
Peak memory 206976 kb
Host smart-af0f0b69-145d-406a-bc56-3315bd99ea59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10424
10905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1042410905
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.841812658
Short name T813
Test name
Test status
Simulation time 165377894 ps
CPU time 0.87 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206956 kb
Host smart-efc8e20e-0287-448b-8a26-ed2b88d26ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84181
2658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.841812658
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2599408056
Short name T2783
Test name
Test status
Simulation time 180640026 ps
CPU time 0.87 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 206920 kb
Host smart-f655ae4f-a30d-4cb9-838c-1509a930304a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25994
08056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2599408056
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1564365141
Short name T435
Test name
Test status
Simulation time 190403729 ps
CPU time 0.96 seconds
Started Jul 30 06:34:26 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 206912 kb
Host smart-d0ce69ff-ec25-48ff-8874-8471ea3b6a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15643
65141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1564365141
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.1365925689
Short name T1428
Test name
Test status
Simulation time 3418084435 ps
CPU time 34.6 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:35:06 PM PDT 24
Peak memory 216896 kb
Host smart-572c9f20-9fe9-477c-9ada-e599e38caf0f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1365925689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.1365925689
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1140470598
Short name T2128
Test name
Test status
Simulation time 146569501 ps
CPU time 0.87 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206964 kb
Host smart-91506256-3dfc-4a5d-a226-5bad6c0192d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11404
70598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1140470598
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.4039072916
Short name T280
Test name
Test status
Simulation time 186880855 ps
CPU time 0.92 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 206916 kb
Host smart-f88ea925-29da-46c0-b4d7-8c55de7938bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40390
72916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.4039072916
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.298606991
Short name T304
Test name
Test status
Simulation time 1328239214 ps
CPU time 3.12 seconds
Started Jul 30 06:34:20 PM PDT 24
Finished Jul 30 06:34:23 PM PDT 24
Peak memory 206968 kb
Host smart-74728242-b786-4285-89d4-180815272512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29860
6991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.298606991
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1313943406
Short name T2753
Test name
Test status
Simulation time 4820517916 ps
CPU time 142.18 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:36:47 PM PDT 24
Peak memory 215332 kb
Host smart-b1722078-b5d4-4a56-a797-4a1c919afe0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13139
43406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1313943406
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.515911937
Short name T2065
Test name
Test status
Simulation time 4338365364 ps
CPU time 30.09 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:55 PM PDT 24
Peak memory 207248 kb
Host smart-8fafc600-453d-4238-80e3-77e5b264e3ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515911937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_host
_handshake.515911937
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.1267991406
Short name T1488
Test name
Test status
Simulation time 43055468 ps
CPU time 0.7 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 207036 kb
Host smart-337508d2-f910-4294-a357-08da5d57dc34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1267991406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.1267991406
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2603466754
Short name T1799
Test name
Test status
Simulation time 3933310486 ps
CPU time 6.81 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:34:37 PM PDT 24
Peak memory 207072 kb
Host smart-a6877018-1772-43cd-9118-1f282c1f3df3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603466754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.2603466754
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1938340884
Short name T1281
Test name
Test status
Simulation time 13370990510 ps
CPU time 15.53 seconds
Started Jul 30 06:34:26 PM PDT 24
Finished Jul 30 06:34:41 PM PDT 24
Peak memory 207096 kb
Host smart-3daa7fda-2ade-4166-b7e0-52bf8ec1cd94
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938340884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1938340884
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.3114430640
Short name T427
Test name
Test status
Simulation time 23431505916 ps
CPU time 26.56 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:34:51 PM PDT 24
Peak memory 207124 kb
Host smart-f41ac8f7-c562-47dd-b319-1c92742887cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114430640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_resume.3114430640
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.889084893
Short name T1726
Test name
Test status
Simulation time 174943112 ps
CPU time 0.88 seconds
Started Jul 30 06:34:17 PM PDT 24
Finished Jul 30 06:34:18 PM PDT 24
Peak memory 206948 kb
Host smart-ff7937f4-1244-4337-8a2c-d90aa291ed01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88908
4893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.889084893
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.317294311
Short name T2050
Test name
Test status
Simulation time 200133366 ps
CPU time 0.9 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206896 kb
Host smart-4438d930-65e7-4822-991b-662c8dac13c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31729
4311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.317294311
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.4226086913
Short name T2716
Test name
Test status
Simulation time 389093087 ps
CPU time 1.48 seconds
Started Jul 30 06:34:22 PM PDT 24
Finished Jul 30 06:34:23 PM PDT 24
Peak memory 206924 kb
Host smart-ada3514c-511f-4986-b120-7ee098bda56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42260
86913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.4226086913
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.878491244
Short name T907
Test name
Test status
Simulation time 826029864 ps
CPU time 2.39 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 206984 kb
Host smart-1f6cbecb-d260-49f9-916b-a2ac91c110e7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=878491244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.878491244
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.760742236
Short name T931
Test name
Test status
Simulation time 7168685113 ps
CPU time 16.34 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:34:48 PM PDT 24
Peak memory 207156 kb
Host smart-0f9ae5aa-3a0e-459e-992c-a4a1c1404a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76074
2236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.760742236
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.1065326779
Short name T2582
Test name
Test status
Simulation time 6054338515 ps
CPU time 42.8 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:35:13 PM PDT 24
Peak memory 207084 kb
Host smart-e7ce957f-0cbb-403f-a971-ba388bb6efc6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065326779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.1065326779
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.3679184402
Short name T2077
Test name
Test status
Simulation time 390753985 ps
CPU time 1.31 seconds
Started Jul 30 06:34:21 PM PDT 24
Finished Jul 30 06:34:23 PM PDT 24
Peak memory 206896 kb
Host smart-e23bf64d-6632-4b5c-b73b-991731c5d24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36791
84402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.3679184402
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.1369474988
Short name T666
Test name
Test status
Simulation time 142073992 ps
CPU time 0.78 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206920 kb
Host smart-d2ec22be-464f-4277-ae07-6126fa5becb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13694
74988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.1369474988
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.255514929
Short name T1155
Test name
Test status
Simulation time 36432808 ps
CPU time 0.69 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 206868 kb
Host smart-2a728c55-51aa-4a10-ac54-9849c86cc9ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25551
4929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.255514929
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.3406724417
Short name T147
Test name
Test status
Simulation time 1051571537 ps
CPU time 2.68 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 207036 kb
Host smart-4dc880aa-b352-4c1f-950e-fc1b0aeb6e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34067
24417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.3406724417
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3259100764
Short name T425
Test name
Test status
Simulation time 162875352 ps
CPU time 1.28 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206964 kb
Host smart-ac300cb1-ab09-4039-859f-c52224bb7e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32591
00764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3259100764
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3329748381
Short name T967
Test name
Test status
Simulation time 240392261 ps
CPU time 1.18 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 207000 kb
Host smart-0d1448cb-c882-453e-90f6-f83ceab1fbd2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3329748381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3329748381
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3186924097
Short name T348
Test name
Test status
Simulation time 141177553 ps
CPU time 0.81 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:34:25 PM PDT 24
Peak memory 206872 kb
Host smart-717b6c43-ea33-4e07-b4a5-e5f3548a8952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31869
24097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3186924097
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1072464328
Short name T1054
Test name
Test status
Simulation time 298507870 ps
CPU time 1.06 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206904 kb
Host smart-7b651173-766e-401f-af1b-a902fe0cbd6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10724
64328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1072464328
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.1706054482
Short name T1998
Test name
Test status
Simulation time 5050450700 ps
CPU time 51.46 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:35:19 PM PDT 24
Peak memory 215376 kb
Host smart-bf9f9d6b-471f-4fda-9f22-c8275612a56a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1706054482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1706054482
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.3116399124
Short name T1636
Test name
Test status
Simulation time 4540335161 ps
CPU time 27.78 seconds
Started Jul 30 06:34:20 PM PDT 24
Finished Jul 30 06:34:48 PM PDT 24
Peak memory 207132 kb
Host smart-3632b328-eede-40cf-86d6-171867fd0a96
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3116399124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.3116399124
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.3975923079
Short name T298
Test name
Test status
Simulation time 230087516 ps
CPU time 1.07 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 206928 kb
Host smart-a292d17d-89b5-40d2-affc-8410d292c18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39759
23079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.3975923079
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.1370958644
Short name T959
Test name
Test status
Simulation time 23324543041 ps
CPU time 27.6 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:57 PM PDT 24
Peak memory 207124 kb
Host smart-afb2acec-673c-4101-bbb0-524139588726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13709
58644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.1370958644
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2751387897
Short name T609
Test name
Test status
Simulation time 3337940107 ps
CPU time 5.11 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 207056 kb
Host smart-9442bd98-2ff5-4a1d-b397-c289c7d660a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27513
87897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2751387897
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.3312913713
Short name T2119
Test name
Test status
Simulation time 4734674549 ps
CPU time 140.51 seconds
Started Jul 30 06:34:20 PM PDT 24
Finished Jul 30 06:36:40 PM PDT 24
Peak memory 215328 kb
Host smart-1b368cb1-e50a-42ff-abc1-d662e56e2b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33129
13713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.3312913713
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1619513277
Short name T2354
Test name
Test status
Simulation time 4338569041 ps
CPU time 127.42 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:36:31 PM PDT 24
Peak memory 215388 kb
Host smart-afbd47d0-e0f9-4ad0-a96e-ca197b4a22ce
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1619513277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1619513277
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.467646905
Short name T2775
Test name
Test status
Simulation time 246053661 ps
CPU time 1.09 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206948 kb
Host smart-f35aa7da-5449-4900-8c0b-da37597fb93f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=467646905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.467646905
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1795388424
Short name T2394
Test name
Test status
Simulation time 187284096 ps
CPU time 0.94 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206952 kb
Host smart-764166bd-3bb6-4b0b-8fdd-2766a603f8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17953
88424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1795388424
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3183702779
Short name T1416
Test name
Test status
Simulation time 3214188627 ps
CPU time 32.94 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:35:03 PM PDT 24
Peak memory 216852 kb
Host smart-8aa643e0-fa7a-4bab-ac65-5c82db18c44c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31837
02779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3183702779
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.4195933520
Short name T2368
Test name
Test status
Simulation time 4358375501 ps
CPU time 33.96 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:35:05 PM PDT 24
Peak memory 207124 kb
Host smart-67595bdc-b757-429a-8e84-66b5eaa70f66
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4195933520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.4195933520
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.1512645702
Short name T2142
Test name
Test status
Simulation time 156776835 ps
CPU time 0.85 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 206912 kb
Host smart-5d639f4b-4396-4dca-a238-0c85daaca83a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1512645702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1512645702
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3043604782
Short name T2352
Test name
Test status
Simulation time 156736855 ps
CPU time 0.87 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206904 kb
Host smart-b7cea1d2-0b4e-48ba-87a5-c845bdd4ef49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30436
04782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3043604782
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3968614823
Short name T2469
Test name
Test status
Simulation time 204793825 ps
CPU time 1 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 206944 kb
Host smart-19c72172-9d04-400f-9700-ca0e29830f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39686
14823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3968614823
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.1285689548
Short name T2755
Test name
Test status
Simulation time 163881962 ps
CPU time 0.88 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 206912 kb
Host smart-411acb03-c850-4a57-a19a-084098361f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12856
89548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.1285689548
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2875422746
Short name T720
Test name
Test status
Simulation time 200844726 ps
CPU time 1 seconds
Started Jul 30 06:34:26 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 206908 kb
Host smart-aac177d6-4e6e-454e-aa3a-bc3f4a91e552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28754
22746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2875422746
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2814894761
Short name T2079
Test name
Test status
Simulation time 161493095 ps
CPU time 0.83 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 206920 kb
Host smart-9235fe00-4fb6-4e6e-bf66-ddb2e89a4bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28148
94761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2814894761
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1267430047
Short name T2145
Test name
Test status
Simulation time 153954821 ps
CPU time 0.84 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 206904 kb
Host smart-cf1e05f3-1d4c-49ec-ba76-e7c2602351f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12674
30047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1267430047
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.3036977005
Short name T1551
Test name
Test status
Simulation time 267235372 ps
CPU time 1.02 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 206956 kb
Host smart-b67fbf9c-ec95-4472-9d1e-28ced5b62989
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3036977005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.3036977005
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3925813053
Short name T2184
Test name
Test status
Simulation time 143332275 ps
CPU time 0.83 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 206884 kb
Host smart-1c48468e-709f-423d-b7f9-21593f5668c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39258
13053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3925813053
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.992607086
Short name T855
Test name
Test status
Simulation time 40619565 ps
CPU time 0.69 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 206856 kb
Host smart-dbd5c828-6678-48ff-b06a-90ca9573e787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99260
7086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.992607086
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3958045676
Short name T2011
Test name
Test status
Simulation time 16690705290 ps
CPU time 38.65 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:35:06 PM PDT 24
Peak memory 215412 kb
Host smart-4ba583fb-5119-4ecf-8dd9-903ae6f138af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39580
45676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3958045676
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3187254018
Short name T1384
Test name
Test status
Simulation time 175436697 ps
CPU time 0.98 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 206952 kb
Host smart-fc53f64b-e7d2-416d-8083-5eac6e505a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31872
54018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3187254018
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.606366279
Short name T1800
Test name
Test status
Simulation time 194762727 ps
CPU time 0.88 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 206880 kb
Host smart-288bcd99-60a5-4662-8252-4dfa9336d61a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60636
6279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.606366279
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.3291904086
Short name T1295
Test name
Test status
Simulation time 172530911 ps
CPU time 0.88 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206908 kb
Host smart-ed182c5d-193d-454c-85f8-1d03346dfafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32919
04086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.3291904086
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3775035595
Short name T1034
Test name
Test status
Simulation time 182082905 ps
CPU time 0.91 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 206912 kb
Host smart-dfdc7238-6d0a-4a13-99af-e991eb39c2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37750
35595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3775035595
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.43337449
Short name T964
Test name
Test status
Simulation time 155459902 ps
CPU time 0.84 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206876 kb
Host smart-d24e9eb4-a3e8-4047-bcb6-ff2880bfaab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43337
449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.43337449
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.1595124763
Short name T2447
Test name
Test status
Simulation time 146334159 ps
CPU time 0.84 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:34:25 PM PDT 24
Peak memory 206884 kb
Host smart-365d6019-c4b8-467f-9567-bfbdb3bc5b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15951
24763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1595124763
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.737096593
Short name T564
Test name
Test status
Simulation time 146363439 ps
CPU time 0.83 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 206916 kb
Host smart-79a96d2e-fb5d-4c8f-8fbb-76805edc14b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73709
6593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.737096593
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1345883105
Short name T1081
Test name
Test status
Simulation time 218682553 ps
CPU time 0.98 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 206896 kb
Host smart-edcb0cea-72f6-4a78-a240-dbc1d6dd60ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13458
83105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1345883105
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.3018028071
Short name T1881
Test name
Test status
Simulation time 3832961897 ps
CPU time 38.3 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:35:08 PM PDT 24
Peak memory 215364 kb
Host smart-d0fae9c6-aeed-4be9-bae8-e0e7d4fd8a77
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3018028071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.3018028071
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2297572842
Short name T1007
Test name
Test status
Simulation time 189016697 ps
CPU time 0.91 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 206912 kb
Host smart-400a1dd7-e74f-4861-8d32-ec844f7221fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22975
72842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2297572842
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2172391040
Short name T2807
Test name
Test status
Simulation time 166041738 ps
CPU time 0.9 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 206960 kb
Host smart-3b2b84f5-c425-4a86-aa58-4a3233a6bfed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21723
91040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2172391040
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.3552442728
Short name T2822
Test name
Test status
Simulation time 931425555 ps
CPU time 2.32 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 206964 kb
Host smart-11bbb7d6-bd65-420b-8de7-a93a8348fa23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35524
42728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.3552442728
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.4256630735
Short name T2219
Test name
Test status
Simulation time 5811109484 ps
CPU time 57.89 seconds
Started Jul 30 06:34:19 PM PDT 24
Finished Jul 30 06:35:17 PM PDT 24
Peak memory 215356 kb
Host smart-967d1ebf-2e4b-4f23-8ea8-2ce0df37ea37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42566
30735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.4256630735
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.983551705
Short name T1041
Test name
Test status
Simulation time 1308787692 ps
CPU time 29.55 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:57 PM PDT 24
Peak memory 207016 kb
Host smart-be7029a5-78fe-40cc-b2fd-017b6baaad15
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983551705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_host
_handshake.983551705
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.2342046358
Short name T2665
Test name
Test status
Simulation time 60597990 ps
CPU time 0.67 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 207036 kb
Host smart-46ef9d39-e6a3-4719-b0dd-2a995e53c0be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2342046358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.2342046358
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.2199952443
Short name T1732
Test name
Test status
Simulation time 3940868620 ps
CPU time 6.6 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:35 PM PDT 24
Peak memory 207100 kb
Host smart-a722a77d-4ec4-4abd-8520-9fe3a6f5a826
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199952443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.2199952443
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.2918884620
Short name T12
Test name
Test status
Simulation time 13357282431 ps
CPU time 16.96 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:34:41 PM PDT 24
Peak memory 207168 kb
Host smart-b3c4d4a8-54af-45db-96d6-fdb49e9f0c88
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918884620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2918884620
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1204805766
Short name T14
Test name
Test status
Simulation time 23369977384 ps
CPU time 33.01 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:35:03 PM PDT 24
Peak memory 207160 kb
Host smart-defc4a53-3b24-49e9-a094-e65473ea31c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204805766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.1204805766
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1057973169
Short name T812
Test name
Test status
Simulation time 216971566 ps
CPU time 0.94 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 206672 kb
Host smart-51055da1-1849-4aeb-82b7-ee2c1584182c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10579
73169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1057973169
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.2930325624
Short name T336
Test name
Test status
Simulation time 153730392 ps
CPU time 0.91 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 206932 kb
Host smart-cc11fa90-5245-4b85-8ba3-907112652776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29303
25624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.2930325624
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2867563145
Short name T707
Test name
Test status
Simulation time 324288553 ps
CPU time 1.27 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 206940 kb
Host smart-84da4411-da83-404a-841e-17d2d4d75e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28675
63145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2867563145
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1032147556
Short name T541
Test name
Test status
Simulation time 782876406 ps
CPU time 2.14 seconds
Started Jul 30 06:34:22 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 207060 kb
Host smart-caa82e44-1788-43c4-8075-17993b3e343a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1032147556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1032147556
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.2055775998
Short name T1526
Test name
Test status
Simulation time 19806650042 ps
CPU time 42.84 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:35:10 PM PDT 24
Peak memory 207060 kb
Host smart-1e37e53e-2415-4137-a17e-7aca0631e56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20557
75998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.2055775998
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.3897184935
Short name T740
Test name
Test status
Simulation time 3651294249 ps
CPU time 24.26 seconds
Started Jul 30 06:34:32 PM PDT 24
Finished Jul 30 06:34:57 PM PDT 24
Peak memory 207128 kb
Host smart-a4a9e380-c1cf-4793-9f9d-c1706f1d6f09
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897184935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.3897184935
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.2439605689
Short name T2583
Test name
Test status
Simulation time 324429304 ps
CPU time 1.31 seconds
Started Jul 30 06:34:26 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 206888 kb
Host smart-137e17f2-54c0-415f-a80c-d8e82f5bcc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24396
05689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.2439605689
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2234316377
Short name T1484
Test name
Test status
Simulation time 138106789 ps
CPU time 0.79 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:34:25 PM PDT 24
Peak memory 206836 kb
Host smart-67ed58a2-6f4c-4d10-bd08-34d1f2057a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22343
16377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2234316377
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2003949665
Short name T1513
Test name
Test status
Simulation time 83965148 ps
CPU time 0.76 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206932 kb
Host smart-04b8d3c7-22ef-4970-86b8-de2d0bcb35b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20039
49665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2003949665
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3189956367
Short name T472
Test name
Test status
Simulation time 877744717 ps
CPU time 2.51 seconds
Started Jul 30 06:34:22 PM PDT 24
Finished Jul 30 06:34:25 PM PDT 24
Peak memory 207040 kb
Host smart-44c074c9-9255-4e22-b401-f00dbab18538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31899
56367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3189956367
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.332255313
Short name T1316
Test name
Test status
Simulation time 166715655 ps
CPU time 1.69 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 207084 kb
Host smart-2f92dc7c-7fa6-4d49-8ccd-4a95941c5708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33225
5313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.332255313
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2638972751
Short name T738
Test name
Test status
Simulation time 162640251 ps
CPU time 0.91 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:34:25 PM PDT 24
Peak memory 207012 kb
Host smart-242c3623-c24f-4b77-9e5a-1d8a86194247
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2638972751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2638972751
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3806011747
Short name T1888
Test name
Test status
Simulation time 151312259 ps
CPU time 0.8 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 206872 kb
Host smart-25fa20d5-feac-4577-aeb0-f46ed8523372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38060
11747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3806011747
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3732846566
Short name T1010
Test name
Test status
Simulation time 251301842 ps
CPU time 1 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:34:25 PM PDT 24
Peak memory 206800 kb
Host smart-23d1c734-b1a7-4606-94f0-fac5ee76e718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37328
46566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3732846566
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.2604493595
Short name T2340
Test name
Test status
Simulation time 7056541659 ps
CPU time 194.22 seconds
Started Jul 30 06:34:22 PM PDT 24
Finished Jul 30 06:37:36 PM PDT 24
Peak memory 215368 kb
Host smart-2c9d679e-c890-4e96-afa1-ebfea964c498
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2604493595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2604493595
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.4118277700
Short name T771
Test name
Test status
Simulation time 6790723823 ps
CPU time 44.67 seconds
Started Jul 30 06:34:26 PM PDT 24
Finished Jul 30 06:35:11 PM PDT 24
Peak memory 207128 kb
Host smart-f88d8c7d-d77c-4545-a63b-e9df19b22bdb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4118277700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.4118277700
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2970306499
Short name T955
Test name
Test status
Simulation time 170709198 ps
CPU time 0.82 seconds
Started Jul 30 06:35:48 PM PDT 24
Finished Jul 30 06:35:49 PM PDT 24
Peak memory 206744 kb
Host smart-e48c7b20-95b3-4b2c-bec7-e71f99b4017b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29703
06499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2970306499
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2243803538
Short name T2404
Test name
Test status
Simulation time 23324087191 ps
CPU time 29.9 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:35:00 PM PDT 24
Peak memory 207192 kb
Host smart-af3f4c77-203b-4bdb-bc19-f38e22eaa86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22438
03538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2243803538
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3812798532
Short name T367
Test name
Test status
Simulation time 3277005942 ps
CPU time 4.66 seconds
Started Jul 30 06:36:01 PM PDT 24
Finished Jul 30 06:36:06 PM PDT 24
Peak memory 206868 kb
Host smart-aece76e8-549e-479a-88e9-4db440c8ffd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38127
98532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3812798532
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1301464835
Short name T1170
Test name
Test status
Simulation time 7526876524 ps
CPU time 75.95 seconds
Started Jul 30 06:34:24 PM PDT 24
Finished Jul 30 06:35:40 PM PDT 24
Peak memory 223504 kb
Host smart-6f200168-d77c-40fe-bae1-f869e681ea0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13014
64835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1301464835
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.142136267
Short name T519
Test name
Test status
Simulation time 2999418823 ps
CPU time 22.38 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:47 PM PDT 24
Peak memory 215348 kb
Host smart-5cb99bb4-56ef-4fb0-b360-7b7697aa0456
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=142136267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.142136267
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.519837179
Short name T402
Test name
Test status
Simulation time 237341311 ps
CPU time 1.02 seconds
Started Jul 30 06:34:26 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 206948 kb
Host smart-14964bab-bba5-4bfb-a64d-f0723f99ed0c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=519837179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.519837179
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.884832589
Short name T538
Test name
Test status
Simulation time 217580019 ps
CPU time 0.95 seconds
Started Jul 30 06:35:47 PM PDT 24
Finished Jul 30 06:35:48 PM PDT 24
Peak memory 206744 kb
Host smart-7675b0cc-6adc-4b98-965f-80acfe14bce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88483
2589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.884832589
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.3986798237
Short name T1185
Test name
Test status
Simulation time 5357549646 ps
CPU time 39.13 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:35:10 PM PDT 24
Peak memory 216812 kb
Host smart-a8d39219-af30-4391-bf55-415f9e42d10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39867
98237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.3986798237
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.811262846
Short name T2446
Test name
Test status
Simulation time 5211721539 ps
CPU time 51.49 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 215380 kb
Host smart-f511dbd9-19c6-4508-9938-846f7c4d3cbb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=811262846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.811262846
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3756953072
Short name T2127
Test name
Test status
Simulation time 157487810 ps
CPU time 0.88 seconds
Started Jul 30 06:34:26 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 206936 kb
Host smart-629068b6-66a9-4254-bbb5-5a2b9762bcb8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3756953072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3756953072
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3273539094
Short name T540
Test name
Test status
Simulation time 182431689 ps
CPU time 0.81 seconds
Started Jul 30 06:35:48 PM PDT 24
Finished Jul 30 06:35:49 PM PDT 24
Peak memory 206740 kb
Host smart-ce5cb4e5-f46e-4f9f-9709-b0a6ca1a48dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32735
39094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3273539094
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1664622090
Short name T2299
Test name
Test status
Simulation time 212775942 ps
CPU time 0.94 seconds
Started Jul 30 06:34:26 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 206912 kb
Host smart-0bab3b2b-f11f-4403-a0f9-aea56e9ae65d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16646
22090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1664622090
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.412418647
Short name T768
Test name
Test status
Simulation time 180416308 ps
CPU time 0.88 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 206916 kb
Host smart-90cadcff-19e7-4b4b-b99c-c0e13c48d7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41241
8647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.412418647
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2744263566
Short name T1890
Test name
Test status
Simulation time 168799188 ps
CPU time 0.89 seconds
Started Jul 30 06:34:37 PM PDT 24
Finished Jul 30 06:34:38 PM PDT 24
Peak memory 206952 kb
Host smart-a47e7727-f3e8-492e-972a-355a864850f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27442
63566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2744263566
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.131687843
Short name T2501
Test name
Test status
Simulation time 162906534 ps
CPU time 0.86 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 206928 kb
Host smart-4ca7091a-cf57-4a26-b3b2-fe871a4df3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13168
7843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.131687843
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.4110977632
Short name T2678
Test name
Test status
Simulation time 158929890 ps
CPU time 0.84 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206904 kb
Host smart-285805c5-bf8e-4397-929f-36849a2e0d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41109
77632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.4110977632
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3436135671
Short name T495
Test name
Test status
Simulation time 217426101 ps
CPU time 1.01 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 206928 kb
Host smart-db7ebf4f-324c-4618-960a-7cde46b2c22f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3436135671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3436135671
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.544560954
Short name T906
Test name
Test status
Simulation time 157525549 ps
CPU time 0.88 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 206896 kb
Host smart-e7213387-23a3-4228-92a7-fa4fcdf91e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54456
0954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.544560954
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1976148945
Short name T2185
Test name
Test status
Simulation time 30943378 ps
CPU time 0.69 seconds
Started Jul 30 06:34:26 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 206868 kb
Host smart-76675dd2-0057-41ea-bf02-9aadb7af0107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19761
48945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1976148945
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3146721824
Short name T316
Test name
Test status
Simulation time 21541028514 ps
CPU time 56.82 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 219456 kb
Host smart-5bcef54a-4d08-4bb5-9f34-7a740dfca5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31467
21824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3146721824
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.649005397
Short name T1166
Test name
Test status
Simulation time 174516891 ps
CPU time 0.87 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206924 kb
Host smart-7d1ade16-e0de-4478-9ea8-cbccbc997bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64900
5397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.649005397
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2689711715
Short name T596
Test name
Test status
Simulation time 189295340 ps
CPU time 0.91 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:34:24 PM PDT 24
Peak memory 206872 kb
Host smart-abca24a4-aca6-4842-8b30-f8807d6da470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26897
11715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2689711715
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.160108493
Short name T1242
Test name
Test status
Simulation time 215400434 ps
CPU time 1.01 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206908 kb
Host smart-e16df2ef-477f-4304-b6ee-88e349e515a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16010
8493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.160108493
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.3631830544
Short name T2709
Test name
Test status
Simulation time 191040885 ps
CPU time 0.94 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 206912 kb
Host smart-1d46d008-b14e-4ae9-9b0a-40920afa98d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36318
30544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.3631830544
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.648967700
Short name T62
Test name
Test status
Simulation time 162069429 ps
CPU time 0.88 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 206888 kb
Host smart-08f15cd4-ffd9-45a3-b04b-5263dd1739f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64896
7700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.648967700
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2334217306
Short name T2344
Test name
Test status
Simulation time 148828554 ps
CPU time 0.88 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206912 kb
Host smart-b5bc5796-8844-41f9-a4b9-b0c1d390624b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23342
17306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2334217306
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3904085068
Short name T2400
Test name
Test status
Simulation time 164369274 ps
CPU time 0.87 seconds
Started Jul 30 06:35:32 PM PDT 24
Finished Jul 30 06:35:33 PM PDT 24
Peak memory 205544 kb
Host smart-08b103ca-0481-4b23-b591-eecb3073987d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39040
85068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3904085068
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.383574742
Short name T2092
Test name
Test status
Simulation time 240063073 ps
CPU time 1 seconds
Started Jul 30 06:35:32 PM PDT 24
Finished Jul 30 06:35:33 PM PDT 24
Peak memory 205532 kb
Host smart-f064d92d-a539-43d1-8485-c193e1ba17ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38357
4742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.383574742
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3761934230
Short name T1299
Test name
Test status
Simulation time 4904723797 ps
CPU time 141.04 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:36:51 PM PDT 24
Peak memory 215380 kb
Host smart-68a2a3fc-168e-4296-9474-86e1098c4afb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3761934230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3761934230
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3811061379
Short name T1009
Test name
Test status
Simulation time 161174698 ps
CPU time 0.87 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 206964 kb
Host smart-73c03a78-053f-426c-bdb9-81327b5ef822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38110
61379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3811061379
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.4062438193
Short name T1853
Test name
Test status
Simulation time 199068797 ps
CPU time 0.84 seconds
Started Jul 30 06:35:56 PM PDT 24
Finished Jul 30 06:35:57 PM PDT 24
Peak memory 206744 kb
Host smart-17dbbefa-2ba7-481c-bf41-5a8429738417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40624
38193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.4062438193
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.2046794416
Short name T1256
Test name
Test status
Simulation time 1268288888 ps
CPU time 2.98 seconds
Started Jul 30 06:34:33 PM PDT 24
Finished Jul 30 06:34:36 PM PDT 24
Peak memory 206996 kb
Host smart-1b248903-d265-463f-b5d3-e29f94b8c002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20467
94416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.2046794416
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1649891864
Short name T2308
Test name
Test status
Simulation time 4617305271 ps
CPU time 32.96 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:59 PM PDT 24
Peak memory 207160 kb
Host smart-054054a4-637f-4db7-8e02-b5ee52c2feb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16498
91864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1649891864
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.298556943
Short name T2312
Test name
Test status
Simulation time 795302756 ps
CPU time 5.5 seconds
Started Jul 30 06:34:26 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 207036 kb
Host smart-dd054b48-b1db-431f-88c8-fb1d7de7b725
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298556943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_host
_handshake.298556943
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.49248835
Short name T1653
Test name
Test status
Simulation time 35365387 ps
CPU time 0.68 seconds
Started Jul 30 06:34:32 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 207028 kb
Host smart-3a3bef9b-4286-4e97-9657-6be21ed112da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=49248835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.49248835
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.2313496793
Short name T1988
Test name
Test status
Simulation time 3557204037 ps
CPU time 5.22 seconds
Started Jul 30 06:34:23 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 207104 kb
Host smart-a3dbbf2d-526f-49b5-bdbf-942d249f785e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313496793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.2313496793
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2862263694
Short name T1573
Test name
Test status
Simulation time 13360243601 ps
CPU time 18.52 seconds
Started Jul 30 06:34:35 PM PDT 24
Finished Jul 30 06:34:54 PM PDT 24
Peak memory 207144 kb
Host smart-a01cac5b-d3e7-4f2c-8e26-c5e8ccbbc9f2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862263694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2862263694
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.1045392173
Short name T1245
Test name
Test status
Simulation time 23361534030 ps
CPU time 30.69 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:35:00 PM PDT 24
Peak memory 207104 kb
Host smart-e52193f2-e7fe-4ba4-9349-173714f216e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045392173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.1045392173
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3274652729
Short name T1698
Test name
Test status
Simulation time 152809049 ps
CPU time 0.87 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206928 kb
Host smart-32d384f2-cd5a-4b9d-aa18-4b244cb72427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32746
52729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3274652729
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.1691522672
Short name T2091
Test name
Test status
Simulation time 151294383 ps
CPU time 0.83 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 206876 kb
Host smart-72f0466b-72ca-4831-af58-71e74c5e6395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16915
22672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.1691522672
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.2243485039
Short name T1879
Test name
Test status
Simulation time 315213799 ps
CPU time 1.35 seconds
Started Jul 30 06:34:33 PM PDT 24
Finished Jul 30 06:34:34 PM PDT 24
Peak memory 206984 kb
Host smart-f4fef147-817f-4c34-a030-b3168a18a98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22434
85039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.2243485039
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1399962668
Short name T2462
Test name
Test status
Simulation time 631174127 ps
CPU time 1.91 seconds
Started Jul 30 06:35:32 PM PDT 24
Finished Jul 30 06:35:34 PM PDT 24
Peak memory 205192 kb
Host smart-48137256-fd2b-453e-abe0-da48cad3bb7e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1399962668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1399962668
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2715470873
Short name T2165
Test name
Test status
Simulation time 21517662704 ps
CPU time 46 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:35:15 PM PDT 24
Peak memory 207160 kb
Host smart-4b7d0c85-d74e-412f-917f-cfd3b09be178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27154
70873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2715470873
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.3156818170
Short name T2588
Test name
Test status
Simulation time 4811332027 ps
CPU time 41.75 seconds
Started Jul 30 06:34:33 PM PDT 24
Finished Jul 30 06:35:15 PM PDT 24
Peak memory 207120 kb
Host smart-7492ca8f-5aa4-4926-b517-194b76b79d47
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156818170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.3156818170
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3187894703
Short name T1955
Test name
Test status
Simulation time 495790176 ps
CPU time 1.62 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 206956 kb
Host smart-447a5b23-ac86-42f3-ae65-dda6dcf97dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31878
94703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3187894703
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.145374173
Short name T1199
Test name
Test status
Simulation time 189270029 ps
CPU time 0.83 seconds
Started Jul 30 06:35:32 PM PDT 24
Finished Jul 30 06:35:33 PM PDT 24
Peak memory 206416 kb
Host smart-f75630d2-6746-4071-8f52-6c12c4fd9d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14537
4173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.145374173
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2759675690
Short name T2234
Test name
Test status
Simulation time 43322743 ps
CPU time 0.74 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 206868 kb
Host smart-b5954b44-1f82-4184-96bc-318f82faac99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27596
75690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2759675690
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.337735983
Short name T811
Test name
Test status
Simulation time 959908680 ps
CPU time 2.55 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 207012 kb
Host smart-307c243b-58e3-410a-a089-657d4f262a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33773
5983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.337735983
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.602371006
Short name T2273
Test name
Test status
Simulation time 321112627 ps
CPU time 2.06 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 207008 kb
Host smart-8e19c640-c18f-4600-bf42-3acbde75ccee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60237
1006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.602371006
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1781169103
Short name T2813
Test name
Test status
Simulation time 182259414 ps
CPU time 0.99 seconds
Started Jul 30 06:34:34 PM PDT 24
Finished Jul 30 06:34:35 PM PDT 24
Peak memory 206992 kb
Host smart-434e5eb2-b994-44bf-90a5-e97281b34e16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1781169103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1781169103
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.4093045964
Short name T1262
Test name
Test status
Simulation time 198983640 ps
CPU time 0.87 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 206932 kb
Host smart-fab3dd34-4fc5-4e2a-9a4d-51c535bf7476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40930
45964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.4093045964
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2801311584
Short name T2272
Test name
Test status
Simulation time 207740748 ps
CPU time 0.95 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 206912 kb
Host smart-ea5a7d65-c057-42f5-8a06-440a787952b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28013
11584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2801311584
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.765014973
Short name T1951
Test name
Test status
Simulation time 6580151384 ps
CPU time 179.73 seconds
Started Jul 30 06:35:32 PM PDT 24
Finished Jul 30 06:38:32 PM PDT 24
Peak memory 213540 kb
Host smart-b630435b-246b-4e01-b2d7-f40f1f9bf39e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=765014973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.765014973
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.281544876
Short name T1265
Test name
Test status
Simulation time 12221089926 ps
CPU time 89.19 seconds
Started Jul 30 06:34:34 PM PDT 24
Finished Jul 30 06:36:03 PM PDT 24
Peak memory 207092 kb
Host smart-3b4d78ea-5739-4995-b4ba-c131504ca815
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=281544876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.281544876
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1734724562
Short name T2587
Test name
Test status
Simulation time 240366519 ps
CPU time 1 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:29 PM PDT 24
Peak memory 206924 kb
Host smart-1a76b172-f1c4-400f-99f1-2bd860556996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17347
24562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1734724562
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2394582996
Short name T2551
Test name
Test status
Simulation time 23328250501 ps
CPU time 29.75 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:35:01 PM PDT 24
Peak memory 207168 kb
Host smart-2062c18d-b994-4051-98b5-602ee4062413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23945
82996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2394582996
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.784332301
Short name T1952
Test name
Test status
Simulation time 3400892004 ps
CPU time 4.87 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 207068 kb
Host smart-ee120571-bbe5-423b-a8bb-6f0888ecee7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78433
2301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.784332301
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.2476224181
Short name T2452
Test name
Test status
Simulation time 6631880508 ps
CPU time 197.61 seconds
Started Jul 30 06:34:32 PM PDT 24
Finished Jul 30 06:37:50 PM PDT 24
Peak memory 215364 kb
Host smart-0bdbf1b4-b0f9-4e09-aff1-7aba7917e7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24762
24181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.2476224181
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.1149727287
Short name T840
Test name
Test status
Simulation time 3343409326 ps
CPU time 28.05 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:57 PM PDT 24
Peak memory 216568 kb
Host smart-aa35da8b-d0fb-4501-8b19-b6dec4020a29
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1149727287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.1149727287
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.1770215514
Short name T503
Test name
Test status
Simulation time 256445744 ps
CPU time 1.03 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206936 kb
Host smart-99710713-d323-4a7a-ba37-4220dbe14ece
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1770215514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.1770215514
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2112769130
Short name T2547
Test name
Test status
Simulation time 206324109 ps
CPU time 0.94 seconds
Started Jul 30 06:34:36 PM PDT 24
Finished Jul 30 06:34:37 PM PDT 24
Peak memory 206928 kb
Host smart-56e504a8-1291-499d-aeee-0225b0598adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21127
69130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2112769130
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.3031605811
Short name T2284
Test name
Test status
Simulation time 5144869706 ps
CPU time 150.66 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:37:00 PM PDT 24
Peak memory 215252 kb
Host smart-cf6a298b-bdf7-4221-858e-d092e05a067e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30316
05811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.3031605811
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.55454954
Short name T2762
Test name
Test status
Simulation time 4670037137 ps
CPU time 47.62 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:35:17 PM PDT 24
Peak memory 207156 kb
Host smart-a3ca76f5-c2b7-4a70-9e2f-3a08e892db07
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=55454954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.55454954
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.4228666011
Short name T1120
Test name
Test status
Simulation time 232196284 ps
CPU time 1 seconds
Started Jul 30 06:34:33 PM PDT 24
Finished Jul 30 06:34:34 PM PDT 24
Peak memory 206976 kb
Host smart-7b48f6d9-813f-42b6-b19f-33acbbc19c4c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4228666011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.4228666011
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.4052083458
Short name T1069
Test name
Test status
Simulation time 159356170 ps
CPU time 0.83 seconds
Started Jul 30 06:34:26 PM PDT 24
Finished Jul 30 06:34:27 PM PDT 24
Peak memory 206932 kb
Host smart-29f5a4a8-8d64-48c2-be09-33b368d504d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40520
83458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.4052083458
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2516075115
Short name T143
Test name
Test status
Simulation time 217910980 ps
CPU time 0.99 seconds
Started Jul 30 06:34:36 PM PDT 24
Finished Jul 30 06:34:38 PM PDT 24
Peak memory 206944 kb
Host smart-8ecf1da4-dee6-4c6e-85b4-8b2fc368e08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25160
75115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2516075115
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3046788699
Short name T2438
Test name
Test status
Simulation time 200492561 ps
CPU time 0.97 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 206952 kb
Host smart-56a5a260-25e8-48f1-aa96-1a408b3be804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30467
88699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3046788699
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2877361068
Short name T1743
Test name
Test status
Simulation time 164998411 ps
CPU time 0.85 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:28 PM PDT 24
Peak memory 206932 kb
Host smart-91ee60d5-bda6-4fec-83c0-8b1d3c3a4648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28773
61068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2877361068
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1634976297
Short name T2379
Test name
Test status
Simulation time 192357087 ps
CPU time 1 seconds
Started Jul 30 06:34:32 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 206828 kb
Host smart-b4c984cd-2c99-42c3-b87c-d69663a0584f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16349
76297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1634976297
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2573291242
Short name T894
Test name
Test status
Simulation time 187639838 ps
CPU time 0.89 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 206912 kb
Host smart-1639eaf1-d784-4150-82b8-1a6c1b154008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25732
91242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2573291242
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.961185316
Short name T940
Test name
Test status
Simulation time 248755856 ps
CPU time 1.03 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206936 kb
Host smart-a3472c3f-2082-4060-9921-37e913162b1c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=961185316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.961185316
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.550109734
Short name T320
Test name
Test status
Simulation time 200610326 ps
CPU time 0.92 seconds
Started Jul 30 06:34:25 PM PDT 24
Finished Jul 30 06:34:26 PM PDT 24
Peak memory 206912 kb
Host smart-0043f816-b053-4154-93e6-336afd85980a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55010
9734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.550109734
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1676013532
Short name T2136
Test name
Test status
Simulation time 27454557 ps
CPU time 0.66 seconds
Started Jul 30 06:34:22 PM PDT 24
Finished Jul 30 06:34:23 PM PDT 24
Peak memory 206848 kb
Host smart-d31c9a5f-3605-4386-8676-1bd41a3344ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16760
13532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1676013532
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.395822537
Short name T1396
Test name
Test status
Simulation time 15779060704 ps
CPU time 38.26 seconds
Started Jul 30 06:34:34 PM PDT 24
Finished Jul 30 06:35:12 PM PDT 24
Peak memory 215396 kb
Host smart-5cad954f-6001-4087-bde4-489c2ecf38f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39582
2537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.395822537
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3244232861
Short name T286
Test name
Test status
Simulation time 190339616 ps
CPU time 0.89 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 206800 kb
Host smart-da535846-75ea-4159-8fa7-da6b94d7c970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32442
32861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3244232861
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2471739229
Short name T2148
Test name
Test status
Simulation time 167971372 ps
CPU time 0.86 seconds
Started Jul 30 06:34:32 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 206888 kb
Host smart-08d9dcb6-4ec1-4416-b82e-32af796a95ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24717
39229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2471739229
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.4188651028
Short name T2296
Test name
Test status
Simulation time 185169316 ps
CPU time 0.89 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 206904 kb
Host smart-3d2e7125-ecc3-46cf-b6da-65792a04a87c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41886
51028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.4188651028
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.3111566844
Short name T2250
Test name
Test status
Simulation time 206131866 ps
CPU time 0.97 seconds
Started Jul 30 06:34:34 PM PDT 24
Finished Jul 30 06:34:35 PM PDT 24
Peak memory 206916 kb
Host smart-5c240c65-a39c-4c0f-a472-c5341a686b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31115
66844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3111566844
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.1331039768
Short name T1808
Test name
Test status
Simulation time 216095319 ps
CPU time 0.92 seconds
Started Jul 30 06:34:33 PM PDT 24
Finished Jul 30 06:34:34 PM PDT 24
Peak memory 206920 kb
Host smart-aa176a62-11a5-4f98-b304-1f834698a4c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13310
39768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1331039768
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.379126313
Short name T1398
Test name
Test status
Simulation time 193201070 ps
CPU time 0.89 seconds
Started Jul 30 06:34:32 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 206880 kb
Host smart-feeba231-21fd-423d-8a0e-6910f7e6d02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37912
6313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.379126313
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3810099671
Short name T108
Test name
Test status
Simulation time 173461872 ps
CPU time 0.86 seconds
Started Jul 30 06:34:32 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 206920 kb
Host smart-568f2c0d-8bf6-4207-948c-ed63256516b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38100
99671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3810099671
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.873829809
Short name T1340
Test name
Test status
Simulation time 218205998 ps
CPU time 1.13 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:30 PM PDT 24
Peak memory 206924 kb
Host smart-2f8476fb-1062-43f0-9feb-56e2d7b24934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87382
9809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.873829809
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.2998128114
Short name T2090
Test name
Test status
Simulation time 3637947355 ps
CPU time 100.6 seconds
Started Jul 30 06:34:33 PM PDT 24
Finished Jul 30 06:36:14 PM PDT 24
Peak memory 215324 kb
Host smart-301fad4d-a8cb-433d-8874-ce6c855c963f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2998128114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.2998128114
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3977147967
Short name T248
Test name
Test status
Simulation time 168071013 ps
CPU time 0.87 seconds
Started Jul 30 06:34:33 PM PDT 24
Finished Jul 30 06:34:34 PM PDT 24
Peak memory 206920 kb
Host smart-11f816bf-8fc5-4819-ae18-bf0529c28ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39771
47967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3977147967
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2346689871
Short name T1796
Test name
Test status
Simulation time 187639628 ps
CPU time 0.92 seconds
Started Jul 30 06:34:38 PM PDT 24
Finished Jul 30 06:34:39 PM PDT 24
Peak memory 206908 kb
Host smart-7a0f5597-120e-4b35-9bc4-7f558640a32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23466
89871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2346689871
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.1690577487
Short name T1441
Test name
Test status
Simulation time 451568549 ps
CPU time 1.39 seconds
Started Jul 30 06:34:34 PM PDT 24
Finished Jul 30 06:34:36 PM PDT 24
Peak memory 206880 kb
Host smart-0eb733ce-ce25-4c5c-b23a-7012bc778719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16905
77487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.1690577487
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.3496043674
Short name T1598
Test name
Test status
Simulation time 5692295843 ps
CPU time 41.42 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:35:12 PM PDT 24
Peak memory 207140 kb
Host smart-833b92fe-39d0-4428-84e8-15b25512bf9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34960
43674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3496043674
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.306887089
Short name T919
Test name
Test status
Simulation time 1254182552 ps
CPU time 30.43 seconds
Started Jul 30 06:34:28 PM PDT 24
Finished Jul 30 06:34:59 PM PDT 24
Peak memory 206988 kb
Host smart-ef23ae1b-25d4-4b54-9773-5449a48c39c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306887089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_host
_handshake.306887089
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.287682478
Short name T2217
Test name
Test status
Simulation time 130237147 ps
CPU time 0.73 seconds
Started Jul 30 06:34:47 PM PDT 24
Finished Jul 30 06:34:53 PM PDT 24
Peak memory 207024 kb
Host smart-5811ba28-52d2-4b63-98e2-7d5a393fb0dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=287682478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.287682478
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3401900641
Short name T569
Test name
Test status
Simulation time 3646181421 ps
CPU time 5.09 seconds
Started Jul 30 06:34:35 PM PDT 24
Finished Jul 30 06:34:40 PM PDT 24
Peak memory 207048 kb
Host smart-9e6a3ae0-ffb7-48db-8cde-2fdd17ee83c3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401900641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_disconnect.3401900641
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3183484653
Short name T7
Test name
Test status
Simulation time 13308817216 ps
CPU time 14.51 seconds
Started Jul 30 06:34:33 PM PDT 24
Finished Jul 30 06:34:48 PM PDT 24
Peak memory 207144 kb
Host smart-fbaf5409-cc38-43c5-abcf-6289784c56ca
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183484653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3183484653
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.3647138413
Short name T1555
Test name
Test status
Simulation time 23370619214 ps
CPU time 27.96 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:34:58 PM PDT 24
Peak memory 207120 kb
Host smart-17570868-376c-4cc4-8869-15bfc09697bc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647138413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.3647138413
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3309434773
Short name T591
Test name
Test status
Simulation time 223994974 ps
CPU time 0.9 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 206908 kb
Host smart-08bdeb0c-b8b6-4a5c-b3ab-a51bcff6e16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33094
34773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3309434773
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.1990035332
Short name T1650
Test name
Test status
Simulation time 150974141 ps
CPU time 0.92 seconds
Started Jul 30 06:34:32 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 206884 kb
Host smart-8e89cc44-6324-4030-8cb9-3050d915bb22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19900
35332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.1990035332
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.1226355332
Short name T677
Test name
Test status
Simulation time 208785846 ps
CPU time 1.07 seconds
Started Jul 30 06:34:29 PM PDT 24
Finished Jul 30 06:34:31 PM PDT 24
Peak memory 206932 kb
Host smart-10e2c1c2-c7dc-4ef8-927f-57b15f87d8bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12263
55332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.1226355332
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.232406255
Short name T1697
Test name
Test status
Simulation time 332491302 ps
CPU time 1.31 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 206904 kb
Host smart-9c47e9cc-8ee0-40e3-9be3-56f9c8bd7d75
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=232406255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.232406255
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.637894537
Short name T649
Test name
Test status
Simulation time 7692550860 ps
CPU time 16.82 seconds
Started Jul 30 06:34:38 PM PDT 24
Finished Jul 30 06:34:55 PM PDT 24
Peak memory 207092 kb
Host smart-6bc936d9-0a9a-4b1e-9ba0-4e64997e3a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63789
4537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.637894537
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.624418003
Short name T1116
Test name
Test status
Simulation time 600296006 ps
CPU time 5.04 seconds
Started Jul 30 06:34:27 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 206992 kb
Host smart-dc839ad9-b7c2-4a04-b9b5-01249545be09
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624418003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.624418003
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1090985029
Short name T2154
Test name
Test status
Simulation time 398508729 ps
CPU time 1.39 seconds
Started Jul 30 06:34:35 PM PDT 24
Finished Jul 30 06:34:37 PM PDT 24
Peak memory 206900 kb
Host smart-1b5e2a42-cae3-4c10-84b8-fcd6eb26e782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10909
85029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1090985029
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3067783250
Short name T2545
Test name
Test status
Simulation time 142205151 ps
CPU time 0.85 seconds
Started Jul 30 06:34:33 PM PDT 24
Finished Jul 30 06:34:34 PM PDT 24
Peak memory 206944 kb
Host smart-1ece0675-a40e-4af0-822a-9cece5fe98c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30677
83250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3067783250
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2315867827
Short name T2559
Test name
Test status
Simulation time 60332878 ps
CPU time 0.79 seconds
Started Jul 30 06:34:37 PM PDT 24
Finished Jul 30 06:34:38 PM PDT 24
Peak memory 206932 kb
Host smart-d2c9b14b-ff3d-4001-97bc-b3b0b6878a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23158
67827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2315867827
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.4215514377
Short name T1861
Test name
Test status
Simulation time 756033702 ps
CPU time 2.06 seconds
Started Jul 30 06:34:37 PM PDT 24
Finished Jul 30 06:34:39 PM PDT 24
Peak memory 207072 kb
Host smart-f04d328d-c394-48df-8978-dd3424dcbe34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42155
14377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.4215514377
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3472391349
Short name T978
Test name
Test status
Simulation time 196405612 ps
CPU time 2.2 seconds
Started Jul 30 06:34:34 PM PDT 24
Finished Jul 30 06:34:36 PM PDT 24
Peak memory 206992 kb
Host smart-082c370d-2bfd-4042-99f7-d304d5468c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34723
91349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3472391349
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2685159954
Short name T1937
Test name
Test status
Simulation time 169680234 ps
CPU time 0.96 seconds
Started Jul 30 06:34:36 PM PDT 24
Finished Jul 30 06:34:37 PM PDT 24
Peak memory 206920 kb
Host smart-d5be5069-5c00-4f67-a380-5e882fcfdd4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2685159954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2685159954
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2370907248
Short name T2007
Test name
Test status
Simulation time 150442218 ps
CPU time 0.83 seconds
Started Jul 30 06:34:39 PM PDT 24
Finished Jul 30 06:34:40 PM PDT 24
Peak memory 206916 kb
Host smart-d38463e2-a7da-4190-a1cb-c6266c20e333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23709
07248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2370907248
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.4239269751
Short name T1810
Test name
Test status
Simulation time 215538288 ps
CPU time 1.06 seconds
Started Jul 30 06:34:35 PM PDT 24
Finished Jul 30 06:34:36 PM PDT 24
Peak memory 206912 kb
Host smart-f21e5649-59af-41ba-86a9-f23f8d5ffd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42392
69751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.4239269751
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.633897364
Short name T1093
Test name
Test status
Simulation time 9992653684 ps
CPU time 100.7 seconds
Started Jul 30 06:34:37 PM PDT 24
Finished Jul 30 06:36:18 PM PDT 24
Peak memory 207136 kb
Host smart-30f00a3a-8e96-4b96-a9b9-521159460249
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=633897364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.633897364
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.4219425722
Short name T1915
Test name
Test status
Simulation time 13270561194 ps
CPU time 163.39 seconds
Started Jul 30 06:34:36 PM PDT 24
Finished Jul 30 06:37:20 PM PDT 24
Peak memory 207164 kb
Host smart-9fc24710-02b0-42e6-b5bb-a51369afe701
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4219425722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.4219425722
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.752293579
Short name T1444
Test name
Test status
Simulation time 241629560 ps
CPU time 1.1 seconds
Started Jul 30 06:34:35 PM PDT 24
Finished Jul 30 06:34:36 PM PDT 24
Peak memory 206900 kb
Host smart-88fe93b6-47e1-48ad-b28a-e328de9d7cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75229
3579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.752293579
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.431356177
Short name T1217
Test name
Test status
Simulation time 23324644237 ps
CPU time 29.25 seconds
Started Jul 30 06:34:30 PM PDT 24
Finished Jul 30 06:34:59 PM PDT 24
Peak memory 207100 kb
Host smart-5eec156b-4ad0-49bb-b922-40da2b6b7bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43135
6177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.431356177
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.2268045367
Short name T2093
Test name
Test status
Simulation time 3296129552 ps
CPU time 4.93 seconds
Started Jul 30 06:34:33 PM PDT 24
Finished Jul 30 06:34:38 PM PDT 24
Peak memory 207056 kb
Host smart-6ea4063e-cd54-4636-a171-a29efb42c163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22680
45367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2268045367
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.1452640214
Short name T2636
Test name
Test status
Simulation time 7929520571 ps
CPU time 234.8 seconds
Started Jul 30 06:34:34 PM PDT 24
Finished Jul 30 06:38:29 PM PDT 24
Peak memory 215328 kb
Host smart-36db2b43-47b8-4fc3-b719-45a51bb1f44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14526
40214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.1452640214
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.3770463304
Short name T2586
Test name
Test status
Simulation time 6853394085 ps
CPU time 207.54 seconds
Started Jul 30 06:34:37 PM PDT 24
Finished Jul 30 06:38:04 PM PDT 24
Peak memory 215320 kb
Host smart-a502f424-6ebc-4f6b-9d7a-ade87acc00a4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3770463304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.3770463304
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3270249503
Short name T2546
Test name
Test status
Simulation time 259686218 ps
CPU time 1.02 seconds
Started Jul 30 06:34:34 PM PDT 24
Finished Jul 30 06:34:35 PM PDT 24
Peak memory 206932 kb
Host smart-603a6f89-39b7-45d9-9543-a5ec78d68952
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3270249503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3270249503
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1509623568
Short name T514
Test name
Test status
Simulation time 233588498 ps
CPU time 0.95 seconds
Started Jul 30 06:34:41 PM PDT 24
Finished Jul 30 06:34:42 PM PDT 24
Peak memory 206908 kb
Host smart-747bb70a-7eb0-419c-aaf3-550af3b46027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096
23568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1509623568
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.4245577622
Short name T2286
Test name
Test status
Simulation time 4918963550 ps
CPU time 47.98 seconds
Started Jul 30 06:34:35 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 216780 kb
Host smart-739fd667-8f7b-48d7-ab8d-8284fe4e280a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42455
77622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.4245577622
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3370764430
Short name T1976
Test name
Test status
Simulation time 6668561949 ps
CPU time 67.78 seconds
Started Jul 30 06:34:40 PM PDT 24
Finished Jul 30 06:35:48 PM PDT 24
Peak memory 207152 kb
Host smart-fe913a09-172e-4838-9f74-959181d70401
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3370764430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3370764430
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.3493206045
Short name T2613
Test name
Test status
Simulation time 156720422 ps
CPU time 0.85 seconds
Started Jul 30 06:34:35 PM PDT 24
Finished Jul 30 06:34:36 PM PDT 24
Peak memory 206956 kb
Host smart-0ed8d878-1bc1-412e-9672-2a7623431141
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3493206045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.3493206045
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2176220934
Short name T598
Test name
Test status
Simulation time 195473261 ps
CPU time 0.9 seconds
Started Jul 30 06:34:38 PM PDT 24
Finished Jul 30 06:34:39 PM PDT 24
Peak memory 206984 kb
Host smart-49b95ad0-8d37-4ec9-b78b-bb12a240e812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21762
20934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2176220934
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.3883804352
Short name T141
Test name
Test status
Simulation time 207971133 ps
CPU time 0.94 seconds
Started Jul 30 06:34:43 PM PDT 24
Finished Jul 30 06:34:44 PM PDT 24
Peak memory 206940 kb
Host smart-17d64346-e8a3-4a3f-8584-fa6439a29968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38838
04352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.3883804352
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.511939191
Short name T1196
Test name
Test status
Simulation time 180587639 ps
CPU time 0.98 seconds
Started Jul 30 06:34:44 PM PDT 24
Finished Jul 30 06:34:45 PM PDT 24
Peak memory 206952 kb
Host smart-62974a6c-f389-45ff-bd73-2fa14a18c4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51193
9191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.511939191
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2405724549
Short name T494
Test name
Test status
Simulation time 186732699 ps
CPU time 0.95 seconds
Started Jul 30 06:34:34 PM PDT 24
Finished Jul 30 06:34:35 PM PDT 24
Peak memory 206948 kb
Host smart-c8a541df-f2e0-4bba-accf-0935c7dc0714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24057
24549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2405724549
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1553241443
Short name T361
Test name
Test status
Simulation time 200525794 ps
CPU time 0.94 seconds
Started Jul 30 06:34:36 PM PDT 24
Finished Jul 30 06:34:37 PM PDT 24
Peak memory 206964 kb
Host smart-b7f0a60b-4714-41cb-b037-61efeb18a8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15532
41443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1553241443
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.807977216
Short name T719
Test name
Test status
Simulation time 142861253 ps
CPU time 0.86 seconds
Started Jul 30 06:34:32 PM PDT 24
Finished Jul 30 06:34:33 PM PDT 24
Peak memory 206984 kb
Host smart-939231ab-4e1a-4893-9a0b-c1768eee2006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80797
7216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.807977216
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.1051621966
Short name T1633
Test name
Test status
Simulation time 204933495 ps
CPU time 1 seconds
Started Jul 30 06:34:35 PM PDT 24
Finished Jul 30 06:34:36 PM PDT 24
Peak memory 206916 kb
Host smart-822d334d-505c-446d-96bf-9c1c807a3232
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1051621966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.1051621966
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3079128594
Short name T1296
Test name
Test status
Simulation time 138858477 ps
CPU time 0.82 seconds
Started Jul 30 06:34:33 PM PDT 24
Finished Jul 30 06:34:34 PM PDT 24
Peak memory 206900 kb
Host smart-8ebe7aff-c9d7-41f0-ab82-74b65e2ea610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30791
28594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3079128594
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2212126471
Short name T2795
Test name
Test status
Simulation time 47038105 ps
CPU time 0.75 seconds
Started Jul 30 06:34:36 PM PDT 24
Finished Jul 30 06:34:37 PM PDT 24
Peak memory 206880 kb
Host smart-d3862a31-833a-4ea5-bcd2-15fd9d3ddc9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22121
26471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2212126471
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3961742854
Short name T256
Test name
Test status
Simulation time 7504405236 ps
CPU time 19.78 seconds
Started Jul 30 06:34:33 PM PDT 24
Finished Jul 30 06:34:53 PM PDT 24
Peak memory 215336 kb
Host smart-dfb62e0f-7ed7-4453-8a5d-90d600d461e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39617
42854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3961742854
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1557785997
Short name T2474
Test name
Test status
Simulation time 195488669 ps
CPU time 0.94 seconds
Started Jul 30 06:34:35 PM PDT 24
Finished Jul 30 06:34:36 PM PDT 24
Peak memory 206904 kb
Host smart-ce32dd19-eeea-4b32-a458-447e440b0ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15577
85997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1557785997
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.20206989
Short name T2021
Test name
Test status
Simulation time 176033459 ps
CPU time 0.93 seconds
Started Jul 30 06:34:35 PM PDT 24
Finished Jul 30 06:34:36 PM PDT 24
Peak memory 206888 kb
Host smart-145be717-ba5b-427e-86f1-c690d2b5db8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20206
989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.20206989
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.1741625027
Short name T1046
Test name
Test status
Simulation time 206356461 ps
CPU time 0.94 seconds
Started Jul 30 06:34:36 PM PDT 24
Finished Jul 30 06:34:37 PM PDT 24
Peak memory 206896 kb
Host smart-2b7b420d-b93b-4c6d-aee2-60b3f87ae578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17416
25027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1741625027
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.123320704
Short name T583
Test name
Test status
Simulation time 220002728 ps
CPU time 0.94 seconds
Started Jul 30 06:34:38 PM PDT 24
Finished Jul 30 06:34:39 PM PDT 24
Peak memory 206892 kb
Host smart-5fc66b57-c82a-4819-92ef-4816e01b30f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12332
0704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.123320704
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.4223730918
Short name T2528
Test name
Test status
Simulation time 180836483 ps
CPU time 0.87 seconds
Started Jul 30 06:34:39 PM PDT 24
Finished Jul 30 06:34:40 PM PDT 24
Peak memory 206884 kb
Host smart-1ff416ae-9b31-49ce-a0b7-ae26a75b8e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42237
30918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.4223730918
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1272432752
Short name T1349
Test name
Test status
Simulation time 160551107 ps
CPU time 0.88 seconds
Started Jul 30 06:34:39 PM PDT 24
Finished Jul 30 06:34:40 PM PDT 24
Peak memory 206880 kb
Host smart-4d68a087-bea7-495f-bca0-5c27e74c36f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12724
32752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1272432752
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1827483917
Short name T2699
Test name
Test status
Simulation time 143378800 ps
CPU time 0.85 seconds
Started Jul 30 06:34:39 PM PDT 24
Finished Jul 30 06:34:40 PM PDT 24
Peak memory 206964 kb
Host smart-52c841fe-33d9-4fee-8053-320241c58180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18274
83917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1827483917
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.971065024
Short name T2766
Test name
Test status
Simulation time 208564684 ps
CPU time 0.98 seconds
Started Jul 30 06:34:39 PM PDT 24
Finished Jul 30 06:34:41 PM PDT 24
Peak memory 206896 kb
Host smart-d677d844-73eb-422d-a2ef-c6ff420a0d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97106
5024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.971065024
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.3850083847
Short name T2575
Test name
Test status
Simulation time 4801479983 ps
CPU time 40.71 seconds
Started Jul 30 06:34:40 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 216568 kb
Host smart-e111b312-fcc9-4266-93ad-5a282d3004f2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3850083847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.3850083847
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1465530890
Short name T683
Test name
Test status
Simulation time 201530808 ps
CPU time 0.99 seconds
Started Jul 30 06:34:42 PM PDT 24
Finished Jul 30 06:34:43 PM PDT 24
Peak memory 206920 kb
Host smart-f7406260-e4dc-4313-9395-c74d4d9e01ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14655
30890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1465530890
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1074980786
Short name T1830
Test name
Test status
Simulation time 193375242 ps
CPU time 0.86 seconds
Started Jul 30 06:34:40 PM PDT 24
Finished Jul 30 06:34:41 PM PDT 24
Peak memory 206960 kb
Host smart-c25114a3-5470-4f1e-a485-5a683c5fb466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10749
80786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1074980786
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.1175157827
Short name T2334
Test name
Test status
Simulation time 611392318 ps
CPU time 1.68 seconds
Started Jul 30 06:34:41 PM PDT 24
Finished Jul 30 06:34:42 PM PDT 24
Peak memory 206952 kb
Host smart-fe17b37f-2190-4534-bb23-f8ec10ec5d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11751
57827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1175157827
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.3143204192
Short name T171
Test name
Test status
Simulation time 7314689564 ps
CPU time 212.37 seconds
Started Jul 30 06:34:39 PM PDT 24
Finished Jul 30 06:38:11 PM PDT 24
Peak memory 215340 kb
Host smart-376cca91-9fd8-4a82-b435-770d85f89979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31432
04192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.3143204192
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.3406607333
Short name T341
Test name
Test status
Simulation time 6174698993 ps
CPU time 54.06 seconds
Started Jul 30 06:34:31 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 207192 kb
Host smart-f5f25a23-c948-4d41-8f77-136e06d46e4f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406607333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos
t_handshake.3406607333
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.3543262820
Short name T2527
Test name
Test status
Simulation time 51851638 ps
CPU time 0.68 seconds
Started Jul 30 06:35:05 PM PDT 24
Finished Jul 30 06:35:06 PM PDT 24
Peak memory 207032 kb
Host smart-f6f93f6f-fa5e-4981-a6ee-05f40acb1833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3543262820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3543262820
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3904737029
Short name T1549
Test name
Test status
Simulation time 4353290014 ps
CPU time 6.12 seconds
Started Jul 30 06:34:44 PM PDT 24
Finished Jul 30 06:34:50 PM PDT 24
Peak memory 207164 kb
Host smart-f64870d4-282c-4a55-87b8-d3cb4d16970e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904737029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.3904737029
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1640761169
Short name T843
Test name
Test status
Simulation time 13384715804 ps
CPU time 16.46 seconds
Started Jul 30 06:34:43 PM PDT 24
Finished Jul 30 06:35:00 PM PDT 24
Peak memory 207132 kb
Host smart-30bd4f4b-cd89-4cfc-a73b-2b0052401f81
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640761169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1640761169
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.2954136358
Short name T1312
Test name
Test status
Simulation time 23391554511 ps
CPU time 33.8 seconds
Started Jul 30 06:34:53 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 207140 kb
Host smart-14a17e3d-c8bc-481c-bb26-bd420b4def8f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954136358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_resume.2954136358
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2070111383
Short name T1807
Test name
Test status
Simulation time 161075563 ps
CPU time 0.88 seconds
Started Jul 30 06:34:41 PM PDT 24
Finished Jul 30 06:34:42 PM PDT 24
Peak memory 206960 kb
Host smart-bf4027e1-b7c4-4038-8f59-95e13301a932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20701
11383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2070111383
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.3740754101
Short name T2244
Test name
Test status
Simulation time 149259419 ps
CPU time 0.89 seconds
Started Jul 30 06:34:38 PM PDT 24
Finished Jul 30 06:34:39 PM PDT 24
Peak memory 206916 kb
Host smart-919f6825-613b-4fc3-8872-a056b32a1359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37407
54101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.3740754101
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.627451067
Short name T834
Test name
Test status
Simulation time 510408494 ps
CPU time 1.75 seconds
Started Jul 30 06:34:42 PM PDT 24
Finished Jul 30 06:34:44 PM PDT 24
Peak memory 206968 kb
Host smart-d31beba7-eaea-4114-af01-2bc28b78908f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62745
1067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.627451067
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.636778459
Short name T2500
Test name
Test status
Simulation time 821025438 ps
CPU time 2.25 seconds
Started Jul 30 06:34:42 PM PDT 24
Finished Jul 30 06:34:49 PM PDT 24
Peak memory 207032 kb
Host smart-bc388e11-0a3c-4b79-a80e-72ba031c5364
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=636778459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.636778459
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.1344135742
Short name T2758
Test name
Test status
Simulation time 10126274967 ps
CPU time 23.92 seconds
Started Jul 30 06:34:41 PM PDT 24
Finished Jul 30 06:35:05 PM PDT 24
Peak memory 207100 kb
Host smart-12369a29-2667-4e80-8f41-697ea17ce8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13441
35742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.1344135742
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.3472393811
Short name T247
Test name
Test status
Simulation time 917145905 ps
CPU time 18.08 seconds
Started Jul 30 06:34:43 PM PDT 24
Finished Jul 30 06:35:01 PM PDT 24
Peak memory 207020 kb
Host smart-521dd4f8-3dc1-4b79-a026-ff5048402fdf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472393811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.3472393811
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.240835131
Short name T1929
Test name
Test status
Simulation time 364257591 ps
CPU time 1.27 seconds
Started Jul 30 06:34:42 PM PDT 24
Finished Jul 30 06:34:44 PM PDT 24
Peak memory 206924 kb
Host smart-525c1e5a-d5dd-4171-9487-b9646efd2ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24083
5131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.240835131
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.2564428578
Short name T1253
Test name
Test status
Simulation time 140211929 ps
CPU time 0.83 seconds
Started Jul 30 06:34:42 PM PDT 24
Finished Jul 30 06:34:43 PM PDT 24
Peak memory 206896 kb
Host smart-9cb15b03-c83a-4587-b5e3-924498c32c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25644
28578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.2564428578
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.4208077297
Short name T1990
Test name
Test status
Simulation time 73076772 ps
CPU time 0.74 seconds
Started Jul 30 06:34:42 PM PDT 24
Finished Jul 30 06:34:43 PM PDT 24
Peak memory 206924 kb
Host smart-d8b01450-7586-4197-b8ce-7bcd5bb84d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42080
77297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.4208077297
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.4133742733
Short name T2020
Test name
Test status
Simulation time 926469865 ps
CPU time 2.34 seconds
Started Jul 30 06:34:47 PM PDT 24
Finished Jul 30 06:34:50 PM PDT 24
Peak memory 207064 kb
Host smart-19b6fffb-1c37-43a3-afbf-526f8a366b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41337
42733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.4133742733
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1060143285
Short name T2231
Test name
Test status
Simulation time 221099299 ps
CPU time 1.84 seconds
Started Jul 30 06:34:46 PM PDT 24
Finished Jul 30 06:34:48 PM PDT 24
Peak memory 207000 kb
Host smart-24a386db-4f13-4765-9823-b2ce18308ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10601
43285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1060143285
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3433134046
Short name T637
Test name
Test status
Simulation time 249553951 ps
CPU time 1.26 seconds
Started Jul 30 06:35:04 PM PDT 24
Finished Jul 30 06:35:06 PM PDT 24
Peak memory 207020 kb
Host smart-ca1b6be7-a591-4b13-925c-07533817b01f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3433134046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3433134046
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2814048499
Short name T1374
Test name
Test status
Simulation time 186162084 ps
CPU time 0.85 seconds
Started Jul 30 06:34:47 PM PDT 24
Finished Jul 30 06:34:48 PM PDT 24
Peak memory 206888 kb
Host smart-fe627824-2a2d-401b-9513-e5fceed1e22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28140
48499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2814048499
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1565105345
Short name T662
Test name
Test status
Simulation time 177368792 ps
CPU time 0.9 seconds
Started Jul 30 06:34:51 PM PDT 24
Finished Jul 30 06:34:52 PM PDT 24
Peak memory 206912 kb
Host smart-71f4886c-d0f1-4848-9ca9-34f65a8b97e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15651
05345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1565105345
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.249502548
Short name T2829
Test name
Test status
Simulation time 5667799037 ps
CPU time 41.96 seconds
Started Jul 30 06:34:46 PM PDT 24
Finished Jul 30 06:35:28 PM PDT 24
Peak memory 215344 kb
Host smart-a6a57c5d-65e6-4215-92b4-38a0a2880871
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=249502548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.249502548
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.3789767369
Short name T442
Test name
Test status
Simulation time 7636107690 ps
CPU time 49.21 seconds
Started Jul 30 06:35:01 PM PDT 24
Finished Jul 30 06:35:56 PM PDT 24
Peak memory 207084 kb
Host smart-a337deff-f5c4-47f1-be3a-af1f4e3af12d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3789767369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.3789767369
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2260699654
Short name T334
Test name
Test status
Simulation time 224745113 ps
CPU time 0.93 seconds
Started Jul 30 06:34:46 PM PDT 24
Finished Jul 30 06:34:47 PM PDT 24
Peak memory 206920 kb
Host smart-82951316-f1a9-4349-9266-dafd82bf4e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22606
99654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2260699654
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3645719572
Short name T2769
Test name
Test status
Simulation time 23299828354 ps
CPU time 25.68 seconds
Started Jul 30 06:35:02 PM PDT 24
Finished Jul 30 06:35:28 PM PDT 24
Peak memory 207084 kb
Host smart-e6402c9c-54f0-45ab-b4fe-aa1e7181dfb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36457
19572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3645719572
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.4148695415
Short name T626
Test name
Test status
Simulation time 3390442190 ps
CPU time 5.52 seconds
Started Jul 30 06:34:47 PM PDT 24
Finished Jul 30 06:34:52 PM PDT 24
Peak memory 207104 kb
Host smart-cdcbf78f-9462-4897-895c-34ad56142b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41486
95415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.4148695415
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.3145639908
Short name T220
Test name
Test status
Simulation time 5853709734 ps
CPU time 44.42 seconds
Started Jul 30 06:34:53 PM PDT 24
Finished Jul 30 06:35:37 PM PDT 24
Peak memory 223440 kb
Host smart-bc668ce8-8f6e-418e-a6b1-0dff9c43d094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31456
39908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.3145639908
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.200487145
Short name T1181
Test name
Test status
Simulation time 5470165542 ps
CPU time 164.15 seconds
Started Jul 30 06:34:47 PM PDT 24
Finished Jul 30 06:37:31 PM PDT 24
Peak memory 215336 kb
Host smart-ce2400a7-e1bb-4015-9866-53a69ce5af68
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=200487145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.200487145
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.1357930821
Short name T2345
Test name
Test status
Simulation time 250864034 ps
CPU time 1.11 seconds
Started Jul 30 06:34:57 PM PDT 24
Finished Jul 30 06:34:59 PM PDT 24
Peak memory 206916 kb
Host smart-0bc1e8a6-755f-4f86-bfc4-17f89fc72981
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1357930821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1357930821
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.4152791988
Short name T1025
Test name
Test status
Simulation time 187696369 ps
CPU time 0.9 seconds
Started Jul 30 06:34:47 PM PDT 24
Finished Jul 30 06:34:48 PM PDT 24
Peak memory 206924 kb
Host smart-ba052084-a7bb-490f-a470-d2dee7bc0027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41527
91988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.4152791988
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.2244312665
Short name T2772
Test name
Test status
Simulation time 3806242223 ps
CPU time 112.36 seconds
Started Jul 30 06:35:01 PM PDT 24
Finished Jul 30 06:36:53 PM PDT 24
Peak memory 215352 kb
Host smart-2f5f564e-3307-4855-aadf-8fe2c78a3466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22443
12665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.2244312665
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.618254829
Short name T1614
Test name
Test status
Simulation time 6080589709 ps
CPU time 48.33 seconds
Started Jul 30 06:35:01 PM PDT 24
Finished Jul 30 06:35:54 PM PDT 24
Peak memory 207152 kb
Host smart-39f0436f-c1b9-4978-a030-f095652cb619
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=618254829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.618254829
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.885692368
Short name T465
Test name
Test status
Simulation time 218638353 ps
CPU time 0.9 seconds
Started Jul 30 06:34:49 PM PDT 24
Finished Jul 30 06:34:50 PM PDT 24
Peak memory 206920 kb
Host smart-517a6e7b-6bd6-4ac3-b4a6-c5fef318cf3d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=885692368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.885692368
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.28259474
Short name T2323
Test name
Test status
Simulation time 180157652 ps
CPU time 0.91 seconds
Started Jul 30 06:34:59 PM PDT 24
Finished Jul 30 06:35:00 PM PDT 24
Peak memory 206988 kb
Host smart-ab12635a-63f0-41b3-9f5e-1b894ce2ec84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28259
474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.28259474
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1888521347
Short name T133
Test name
Test status
Simulation time 209669680 ps
CPU time 1.07 seconds
Started Jul 30 06:34:58 PM PDT 24
Finished Jul 30 06:34:59 PM PDT 24
Peak memory 206928 kb
Host smart-934f4565-5a1b-4bfa-847d-282bb71167fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18885
21347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1888521347
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2082274449
Short name T1204
Test name
Test status
Simulation time 207265418 ps
CPU time 0.93 seconds
Started Jul 30 06:34:48 PM PDT 24
Finished Jul 30 06:34:49 PM PDT 24
Peak memory 206948 kb
Host smart-7f47b5f9-a810-4712-8a9a-08f7c83d947d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20822
74449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2082274449
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3781745782
Short name T2645
Test name
Test status
Simulation time 181441075 ps
CPU time 0.86 seconds
Started Jul 30 06:34:48 PM PDT 24
Finished Jul 30 06:34:49 PM PDT 24
Peak memory 206904 kb
Host smart-1cd3c794-1d38-4ddc-8f80-d74559ba764a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37817
45782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3781745782
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2137888649
Short name T1134
Test name
Test status
Simulation time 232734270 ps
CPU time 0.94 seconds
Started Jul 30 06:34:55 PM PDT 24
Finished Jul 30 06:34:56 PM PDT 24
Peak memory 206892 kb
Host smart-c05b10f7-7f0e-4b4a-baa6-a0dc6ea82fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21378
88649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2137888649
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.410871355
Short name T1039
Test name
Test status
Simulation time 203880818 ps
CPU time 0.93 seconds
Started Jul 30 06:34:58 PM PDT 24
Finished Jul 30 06:34:59 PM PDT 24
Peak memory 206908 kb
Host smart-b9dbaab5-d7cd-4ec7-b6f5-c11152f71040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41087
1355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.410871355
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1071596423
Short name T2086
Test name
Test status
Simulation time 241300670 ps
CPU time 1.16 seconds
Started Jul 30 06:35:00 PM PDT 24
Finished Jul 30 06:35:01 PM PDT 24
Peak memory 206912 kb
Host smart-f9ffac23-10bb-4867-a2a8-a4b47193af8b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1071596423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1071596423
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1523007774
Short name T2732
Test name
Test status
Simulation time 176029845 ps
CPU time 0.87 seconds
Started Jul 30 06:34:55 PM PDT 24
Finished Jul 30 06:34:56 PM PDT 24
Peak memory 206908 kb
Host smart-04fd6d01-1635-4634-b028-bb2b1c6a78fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15230
07774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1523007774
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2008513102
Short name T841
Test name
Test status
Simulation time 82922402 ps
CPU time 0.79 seconds
Started Jul 30 06:35:02 PM PDT 24
Finished Jul 30 06:35:03 PM PDT 24
Peak memory 206880 kb
Host smart-9b1ef3a2-fa08-456d-9b58-e09002e30b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20085
13102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2008513102
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.375027353
Short name T2158
Test name
Test status
Simulation time 12247127667 ps
CPU time 31.32 seconds
Started Jul 30 06:35:11 PM PDT 24
Finished Jul 30 06:35:42 PM PDT 24
Peak memory 215376 kb
Host smart-d3caa578-ae8f-4aad-a130-671f8e037d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37502
7353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.375027353
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3054822246
Short name T929
Test name
Test status
Simulation time 173603061 ps
CPU time 0.91 seconds
Started Jul 30 06:35:12 PM PDT 24
Finished Jul 30 06:35:13 PM PDT 24
Peak memory 206920 kb
Host smart-3ae992c2-3224-4cee-9043-de7646cfb058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30548
22246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3054822246
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2597771479
Short name T2725
Test name
Test status
Simulation time 170646503 ps
CPU time 0.95 seconds
Started Jul 30 06:35:05 PM PDT 24
Finished Jul 30 06:35:06 PM PDT 24
Peak memory 206904 kb
Host smart-0fe3cd72-0557-4213-a04a-2da5bb919c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25977
71479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2597771479
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.902278065
Short name T970
Test name
Test status
Simulation time 217626846 ps
CPU time 0.91 seconds
Started Jul 30 06:35:07 PM PDT 24
Finished Jul 30 06:35:08 PM PDT 24
Peak memory 206920 kb
Host smart-6717d3b7-3801-41ad-8dc1-a5f9ed27f188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90227
8065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.902278065
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.2099005966
Short name T2459
Test name
Test status
Simulation time 163084301 ps
CPU time 0.86 seconds
Started Jul 30 06:34:57 PM PDT 24
Finished Jul 30 06:34:58 PM PDT 24
Peak memory 206916 kb
Host smart-c0c31da6-dfa9-46c4-84d3-4b732e43bebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20990
05966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2099005966
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1774120695
Short name T1632
Test name
Test status
Simulation time 163187561 ps
CPU time 0.88 seconds
Started Jul 30 06:35:05 PM PDT 24
Finished Jul 30 06:35:06 PM PDT 24
Peak memory 206924 kb
Host smart-cf095b99-7665-4595-89e5-31b8dc09d284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17741
20695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1774120695
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.463344500
Short name T597
Test name
Test status
Simulation time 155226547 ps
CPU time 0.82 seconds
Started Jul 30 06:35:06 PM PDT 24
Finished Jul 30 06:35:07 PM PDT 24
Peak memory 206892 kb
Host smart-b815cc66-806b-42ab-bec2-866d9206cd08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46334
4500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.463344500
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.546316977
Short name T2681
Test name
Test status
Simulation time 184229035 ps
CPU time 0.89 seconds
Started Jul 30 06:34:59 PM PDT 24
Finished Jul 30 06:35:00 PM PDT 24
Peak memory 206988 kb
Host smart-9ef4107f-a2b6-44bc-8c58-513efe25ec5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54631
6977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.546316977
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.4234880081
Short name T152
Test name
Test status
Simulation time 259536427 ps
CPU time 1.1 seconds
Started Jul 30 06:35:04 PM PDT 24
Finished Jul 30 06:35:05 PM PDT 24
Peak memory 206916 kb
Host smart-9d8f31f2-5227-4a26-a020-63cfad3d8738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42348
80081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.4234880081
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2319101273
Short name T2277
Test name
Test status
Simulation time 3820506965 ps
CPU time 30.13 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:52 PM PDT 24
Peak memory 216864 kb
Host smart-286dcb42-e39d-40e3-a70c-b5852b1580a5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2319101273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2319101273
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3264524634
Short name T493
Test name
Test status
Simulation time 173303779 ps
CPU time 0.87 seconds
Started Jul 30 06:35:14 PM PDT 24
Finished Jul 30 06:35:15 PM PDT 24
Peak memory 206944 kb
Host smart-23c0c73e-8c74-4d54-96d7-0af39952366a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32645
24634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3264524634
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2831442063
Short name T505
Test name
Test status
Simulation time 186892658 ps
CPU time 0.87 seconds
Started Jul 30 06:34:54 PM PDT 24
Finished Jul 30 06:34:55 PM PDT 24
Peak memory 206908 kb
Host smart-7f4b8afb-ac78-4e2f-8d97-d9d06989bbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28314
42063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2831442063
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.3712462017
Short name T534
Test name
Test status
Simulation time 815931328 ps
CPU time 2.1 seconds
Started Jul 30 06:35:00 PM PDT 24
Finished Jul 30 06:35:02 PM PDT 24
Peak memory 206880 kb
Host smart-62cfdbfa-31bc-4f22-815c-3508e7f7deff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37124
62017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.3712462017
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.2706648443
Short name T2457
Test name
Test status
Simulation time 7009573470 ps
CPU time 208.29 seconds
Started Jul 30 06:35:06 PM PDT 24
Finished Jul 30 06:38:34 PM PDT 24
Peak memory 215312 kb
Host smart-b120eda2-fb6c-48e1-9f12-46a186534af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27066
48443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.2706648443
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.2209261617
Short name T1640
Test name
Test status
Simulation time 1435258054 ps
CPU time 33.93 seconds
Started Jul 30 06:34:44 PM PDT 24
Finished Jul 30 06:35:18 PM PDT 24
Peak memory 206992 kb
Host smart-c8ea89c6-7b09-4685-95cd-ea9c136546c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209261617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.2209261617
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.1887651036
Short name T2489
Test name
Test status
Simulation time 76275810 ps
CPU time 0.73 seconds
Started Jul 30 06:35:14 PM PDT 24
Finished Jul 30 06:35:14 PM PDT 24
Peak memory 207012 kb
Host smart-2877741c-778f-493c-8ba2-5d280cfe50b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1887651036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.1887651036
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1380805525
Short name T1287
Test name
Test status
Simulation time 3519118090 ps
CPU time 6.05 seconds
Started Jul 30 06:35:11 PM PDT 24
Finished Jul 30 06:35:17 PM PDT 24
Peak memory 207084 kb
Host smart-1aa71793-d31c-4d7d-81b0-1c806bc36132
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380805525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_disconnect.1380805525
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.1881053816
Short name T510
Test name
Test status
Simulation time 13482718045 ps
CPU time 16.42 seconds
Started Jul 30 06:35:07 PM PDT 24
Finished Jul 30 06:35:24 PM PDT 24
Peak memory 207124 kb
Host smart-8c2f22b7-1312-407e-9010-5a10ebdf40c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881053816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.1881053816
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.2220288432
Short name T779
Test name
Test status
Simulation time 23317477887 ps
CPU time 31.81 seconds
Started Jul 30 06:35:10 PM PDT 24
Finished Jul 30 06:35:42 PM PDT 24
Peak memory 207100 kb
Host smart-de57d13f-7959-480f-995d-08d690de8bcd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220288432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.2220288432
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.528448268
Short name T2407
Test name
Test status
Simulation time 175961452 ps
CPU time 0.87 seconds
Started Jul 30 06:35:00 PM PDT 24
Finished Jul 30 06:35:01 PM PDT 24
Peak memory 206916 kb
Host smart-7669818b-0cae-4d28-a691-37eeee506bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52844
8268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.528448268
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.1803689864
Short name T605
Test name
Test status
Simulation time 147818128 ps
CPU time 0.85 seconds
Started Jul 30 06:35:06 PM PDT 24
Finished Jul 30 06:35:07 PM PDT 24
Peak memory 206880 kb
Host smart-a813d756-6169-4533-a4da-d9485c0bcc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18036
89864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.1803689864
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.3085704872
Short name T1834
Test name
Test status
Simulation time 387076092 ps
CPU time 1.44 seconds
Started Jul 30 06:35:05 PM PDT 24
Finished Jul 30 06:35:06 PM PDT 24
Peak memory 206980 kb
Host smart-70570f0c-1d0e-4476-ba2d-7a39426174c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857
04872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.3085704872
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.77925590
Short name T671
Test name
Test status
Simulation time 490929884 ps
CPU time 1.64 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 206932 kb
Host smart-0dbb1cc3-cab9-4901-a301-5b5b3ab84618
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=77925590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.77925590
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.2034895148
Short name T2423
Test name
Test status
Simulation time 19452045542 ps
CPU time 43.2 seconds
Started Jul 30 06:35:15 PM PDT 24
Finished Jul 30 06:35:58 PM PDT 24
Peak memory 207088 kb
Host smart-d8bdf84f-88bc-4305-8f9c-b0841c4eb295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20348
95148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2034895148
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.2947604318
Short name T1490
Test name
Test status
Simulation time 582595718 ps
CPU time 12.11 seconds
Started Jul 30 06:34:59 PM PDT 24
Finished Jul 30 06:35:12 PM PDT 24
Peak memory 207024 kb
Host smart-2747bfa2-bff4-4610-b711-99d64ab9fbc6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947604318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.2947604318
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1467472956
Short name T308
Test name
Test status
Simulation time 512775405 ps
CPU time 1.6 seconds
Started Jul 30 06:35:03 PM PDT 24
Finished Jul 30 06:35:05 PM PDT 24
Peak memory 206900 kb
Host smart-72d1f071-8005-449f-9742-c8dbc52fd509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14674
72956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1467472956
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.2944329572
Short name T2385
Test name
Test status
Simulation time 165221683 ps
CPU time 0.89 seconds
Started Jul 30 06:35:13 PM PDT 24
Finished Jul 30 06:35:14 PM PDT 24
Peak memory 206880 kb
Host smart-5eb06151-1c5e-46f1-ab62-f5aa9bb4d7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29443
29572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2944329572
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3342849650
Short name T2110
Test name
Test status
Simulation time 66511840 ps
CPU time 0.72 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:17 PM PDT 24
Peak memory 206896 kb
Host smart-a7cf4ad9-30b0-4106-9e56-a49c925725fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33428
49650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3342849650
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3164899380
Short name T1687
Test name
Test status
Simulation time 879852632 ps
CPU time 2.55 seconds
Started Jul 30 06:35:14 PM PDT 24
Finished Jul 30 06:35:17 PM PDT 24
Peak memory 207068 kb
Host smart-ac0bf481-d727-4c0c-8c6d-d6bc7fb7a98b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31648
99380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3164899380
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.4052444994
Short name T691
Test name
Test status
Simulation time 238357237 ps
CPU time 1.59 seconds
Started Jul 30 06:35:06 PM PDT 24
Finished Jul 30 06:35:07 PM PDT 24
Peak memory 207016 kb
Host smart-c0d192a3-2e7f-459f-9f5b-378ce627abf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40524
44994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.4052444994
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1156841496
Short name T616
Test name
Test status
Simulation time 237892391 ps
CPU time 1.19 seconds
Started Jul 30 06:35:08 PM PDT 24
Finished Jul 30 06:35:09 PM PDT 24
Peak memory 215204 kb
Host smart-1d50b79e-9c36-4af0-b14f-7be6cd961c50
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1156841496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1156841496
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.252038167
Short name T1940
Test name
Test status
Simulation time 147403701 ps
CPU time 0.84 seconds
Started Jul 30 06:35:10 PM PDT 24
Finished Jul 30 06:35:11 PM PDT 24
Peak memory 206876 kb
Host smart-f70c7fca-fe6e-4883-b297-24305e2df6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25203
8167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.252038167
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3934480612
Short name T1476
Test name
Test status
Simulation time 163141423 ps
CPU time 0.87 seconds
Started Jul 30 06:35:10 PM PDT 24
Finished Jul 30 06:35:11 PM PDT 24
Peak memory 206904 kb
Host smart-bcb32ec9-e44c-46b7-adf8-6d350708acf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39344
80612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3934480612
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.3209801027
Short name T2256
Test name
Test status
Simulation time 5306115419 ps
CPU time 151.91 seconds
Started Jul 30 06:34:58 PM PDT 24
Finished Jul 30 06:37:30 PM PDT 24
Peak memory 223228 kb
Host smart-14616ba7-a71c-4203-8749-0f351fc6541d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3209801027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.3209801027
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1272092612
Short name T1085
Test name
Test status
Simulation time 178476565 ps
CPU time 0.92 seconds
Started Jul 30 06:35:06 PM PDT 24
Finished Jul 30 06:35:07 PM PDT 24
Peak memory 206908 kb
Host smart-67d0fcaa-02d6-48b8-a4af-7e8d147dddef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12720
92612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1272092612
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.170644154
Short name T2771
Test name
Test status
Simulation time 23345752568 ps
CPU time 28.63 seconds
Started Jul 30 06:35:14 PM PDT 24
Finished Jul 30 06:35:43 PM PDT 24
Peak memory 207160 kb
Host smart-cf276485-805f-405d-82b2-c52b8f4e0ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17064
4154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.170644154
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3298552516
Short name T2426
Test name
Test status
Simulation time 3313569708 ps
CPU time 5.33 seconds
Started Jul 30 06:35:23 PM PDT 24
Finished Jul 30 06:35:28 PM PDT 24
Peak memory 207072 kb
Host smart-3804a71d-9b73-46b0-ba4c-afe04a3af68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32985
52516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3298552516
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.315042205
Short name T2192
Test name
Test status
Simulation time 6922031559 ps
CPU time 67.81 seconds
Started Jul 30 06:35:13 PM PDT 24
Finished Jul 30 06:36:21 PM PDT 24
Peak memory 217088 kb
Host smart-275d7d9e-6272-4c70-b181-ff90b43f1aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31504
2205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.315042205
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.4129295119
Short name T434
Test name
Test status
Simulation time 4140892171 ps
CPU time 32.87 seconds
Started Jul 30 06:35:07 PM PDT 24
Finished Jul 30 06:35:40 PM PDT 24
Peak memory 207156 kb
Host smart-c937c53d-bc80-4d6b-bb17-e4087b388368
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4129295119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.4129295119
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2164355050
Short name T1826
Test name
Test status
Simulation time 232730798 ps
CPU time 1.02 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:22 PM PDT 24
Peak memory 206936 kb
Host smart-0c8ca50e-2c9b-4a42-9dce-35c60e60844a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2164355050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2164355050
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1090496278
Short name T946
Test name
Test status
Simulation time 186711770 ps
CPU time 1.04 seconds
Started Jul 30 06:35:05 PM PDT 24
Finished Jul 30 06:35:06 PM PDT 24
Peak memory 206932 kb
Host smart-b704122f-eab3-4b65-8223-993fea8ad926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10904
96278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1090496278
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1485939103
Short name T1434
Test name
Test status
Simulation time 5060072363 ps
CPU time 36.72 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:53 PM PDT 24
Peak memory 215376 kb
Host smart-fb15b0c8-84b8-4c13-a120-2f05601f228a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14859
39103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1485939103
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.215708168
Short name T2424
Test name
Test status
Simulation time 4588466409 ps
CPU time 131.04 seconds
Started Jul 30 06:35:04 PM PDT 24
Finished Jul 30 06:37:15 PM PDT 24
Peak memory 215320 kb
Host smart-fbd74228-9b05-4ded-b48a-c8121ae7e61a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=215708168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.215708168
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1965617607
Short name T1211
Test name
Test status
Simulation time 187067805 ps
CPU time 0.94 seconds
Started Jul 30 06:35:13 PM PDT 24
Finished Jul 30 06:35:14 PM PDT 24
Peak memory 206916 kb
Host smart-0a73c2b7-ae25-4b65-a8ef-c715736d4953
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1965617607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1965617607
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1950669486
Short name T1760
Test name
Test status
Simulation time 139451871 ps
CPU time 0.82 seconds
Started Jul 30 06:35:11 PM PDT 24
Finished Jul 30 06:35:12 PM PDT 24
Peak memory 206916 kb
Host smart-f4e7001d-8b23-4621-91ce-7dc14613f81e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19506
69486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1950669486
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2372290496
Short name T2271
Test name
Test status
Simulation time 241983994 ps
CPU time 1.01 seconds
Started Jul 30 06:35:00 PM PDT 24
Finished Jul 30 06:35:02 PM PDT 24
Peak memory 206976 kb
Host smart-de5bb997-55d6-4c37-ae58-c1bd111f4e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23722
90496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2372290496
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1387487004
Short name T553
Test name
Test status
Simulation time 156825709 ps
CPU time 0.87 seconds
Started Jul 30 06:35:02 PM PDT 24
Finished Jul 30 06:35:03 PM PDT 24
Peak memory 206904 kb
Host smart-27300f63-0eb7-4c2b-81f5-b7bd0daa6e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13874
87004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1387487004
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1448811945
Short name T791
Test name
Test status
Simulation time 144629152 ps
CPU time 0.82 seconds
Started Jul 30 06:35:11 PM PDT 24
Finished Jul 30 06:35:12 PM PDT 24
Peak memory 206924 kb
Host smart-d3287220-d278-428c-9c15-e5c4fe925fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14488
11945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1448811945
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1896607979
Short name T2133
Test name
Test status
Simulation time 196690695 ps
CPU time 0.96 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 206924 kb
Host smart-f7d4d8e6-f236-43e6-9505-190e4f9ee53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18966
07979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1896607979
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.842584794
Short name T1140
Test name
Test status
Simulation time 192545666 ps
CPU time 0.9 seconds
Started Jul 30 06:35:17 PM PDT 24
Finished Jul 30 06:35:18 PM PDT 24
Peak memory 206916 kb
Host smart-49c328a0-9078-453d-87ed-6b0ad924e7ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84258
4794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.842584794
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3802378291
Short name T799
Test name
Test status
Simulation time 202758821 ps
CPU time 0.95 seconds
Started Jul 30 06:35:15 PM PDT 24
Finished Jul 30 06:35:16 PM PDT 24
Peak memory 206904 kb
Host smart-c4e55fc7-7c22-464c-8671-7d1966e45980
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3802378291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3802378291
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.4024842831
Short name T2108
Test name
Test status
Simulation time 139643943 ps
CPU time 0.83 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 206912 kb
Host smart-9bf556c6-22e4-483a-99a9-287220905d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40248
42831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.4024842831
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.989577858
Short name T879
Test name
Test status
Simulation time 47177982 ps
CPU time 0.69 seconds
Started Jul 30 06:35:10 PM PDT 24
Finished Jul 30 06:35:11 PM PDT 24
Peak memory 206940 kb
Host smart-a56382dc-30ad-42ff-aeef-d9f2be398e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98957
7858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.989577858
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.4280602755
Short name T250
Test name
Test status
Simulation time 14739655585 ps
CPU time 34.89 seconds
Started Jul 30 06:35:11 PM PDT 24
Finished Jul 30 06:35:46 PM PDT 24
Peak memory 215316 kb
Host smart-3daf2463-91ef-4cb5-9cb5-9f495f27c6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42806
02755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.4280602755
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2829475841
Short name T1142
Test name
Test status
Simulation time 194144314 ps
CPU time 0.95 seconds
Started Jul 30 06:35:08 PM PDT 24
Finished Jul 30 06:35:09 PM PDT 24
Peak memory 206916 kb
Host smart-0447dc55-b3fb-4b0a-97d4-e7b2fb169dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28294
75841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2829475841
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.197498126
Short name T1618
Test name
Test status
Simulation time 228693371 ps
CPU time 0.99 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 206956 kb
Host smart-4b6eca7e-8b85-4243-9088-f9b61f831a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19749
8126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.197498126
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3074220931
Short name T2395
Test name
Test status
Simulation time 161466286 ps
CPU time 0.87 seconds
Started Jul 30 06:35:12 PM PDT 24
Finished Jul 30 06:35:13 PM PDT 24
Peak memory 206904 kb
Host smart-0c72076f-af53-48a2-bad2-de2d71a41bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30742
20931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3074220931
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.558108071
Short name T898
Test name
Test status
Simulation time 226191574 ps
CPU time 0.94 seconds
Started Jul 30 06:35:08 PM PDT 24
Finished Jul 30 06:35:09 PM PDT 24
Peak memory 206912 kb
Host smart-bc439e45-38fb-4c8a-b3ff-e087285376b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55810
8071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.558108071
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.1010325291
Short name T753
Test name
Test status
Simulation time 162002034 ps
CPU time 0.86 seconds
Started Jul 30 06:35:09 PM PDT 24
Finished Jul 30 06:35:10 PM PDT 24
Peak memory 206948 kb
Host smart-176b6b64-ff4b-4d87-b28f-691f64839459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10103
25291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.1010325291
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1550266323
Short name T752
Test name
Test status
Simulation time 175953733 ps
CPU time 0.87 seconds
Started Jul 30 06:35:08 PM PDT 24
Finished Jul 30 06:35:09 PM PDT 24
Peak memory 206884 kb
Host smart-c9b70f4e-4c33-4456-ae7e-543603860034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15502
66323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1550266323
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.4177614988
Short name T1801
Test name
Test status
Simulation time 147147801 ps
CPU time 0.83 seconds
Started Jul 30 06:35:15 PM PDT 24
Finished Jul 30 06:35:16 PM PDT 24
Peak memory 206912 kb
Host smart-6d344782-6849-41be-9461-c00dccaf09e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41776
14988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.4177614988
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1147452375
Short name T303
Test name
Test status
Simulation time 268913468 ps
CPU time 1.08 seconds
Started Jul 30 06:35:11 PM PDT 24
Finished Jul 30 06:35:12 PM PDT 24
Peak memory 206924 kb
Host smart-e6645685-1ed4-46ef-8feb-768bd4a935be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11474
52375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1147452375
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1330271292
Short name T1065
Test name
Test status
Simulation time 3484990660 ps
CPU time 26.72 seconds
Started Jul 30 06:35:06 PM PDT 24
Finished Jul 30 06:35:33 PM PDT 24
Peak memory 216880 kb
Host smart-0e378261-d8a3-4da4-a800-e6719e3b29f6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1330271292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1330271292
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.177022093
Short name T2806
Test name
Test status
Simulation time 189135612 ps
CPU time 0.88 seconds
Started Jul 30 06:35:11 PM PDT 24
Finished Jul 30 06:35:12 PM PDT 24
Peak memory 206944 kb
Host smart-9645569a-e674-48aa-9916-d2c9727b42b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17702
2093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.177022093
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.2328218725
Short name T2737
Test name
Test status
Simulation time 173879947 ps
CPU time 0.85 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:19 PM PDT 24
Peak memory 206924 kb
Host smart-1cc9b759-649d-451f-b892-5224e2990960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23282
18725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.2328218725
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.4043569126
Short name T1668
Test name
Test status
Simulation time 487359136 ps
CPU time 1.48 seconds
Started Jul 30 06:35:13 PM PDT 24
Finished Jul 30 06:35:15 PM PDT 24
Peak memory 207048 kb
Host smart-c543ac3a-4b5a-4dd8-bf83-8f2004d14ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40435
69126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.4043569126
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.952247751
Short name T1816
Test name
Test status
Simulation time 3571203578 ps
CPU time 100.64 seconds
Started Jul 30 06:35:14 PM PDT 24
Finished Jul 30 06:36:55 PM PDT 24
Peak memory 215332 kb
Host smart-7a5fbc66-55e2-4335-adaa-034511b47854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95224
7751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.952247751
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.1439341612
Short name T2062
Test name
Test status
Simulation time 287290001 ps
CPU time 4.48 seconds
Started Jul 30 06:35:12 PM PDT 24
Finished Jul 30 06:35:17 PM PDT 24
Peak memory 206988 kb
Host smart-b1d94aa6-1c86-402e-abf5-75bc31c74c6b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439341612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.1439341612
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.3597826976
Short name T787
Test name
Test status
Simulation time 67563122 ps
CPU time 0.69 seconds
Started Jul 30 06:28:42 PM PDT 24
Finished Jul 30 06:28:43 PM PDT 24
Peak memory 207076 kb
Host smart-a4aa54fc-42b0-4066-8641-4ed7af3250ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3597826976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3597826976
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.3380420948
Short name T1361
Test name
Test status
Simulation time 4171447100 ps
CPU time 5.63 seconds
Started Jul 30 06:28:31 PM PDT 24
Finished Jul 30 06:28:36 PM PDT 24
Peak memory 207104 kb
Host smart-fc660ed1-0c9a-467d-b087-980a2b55308b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380420948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.3380420948
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2631327483
Short name T1153
Test name
Test status
Simulation time 13435742216 ps
CPU time 15.78 seconds
Started Jul 30 06:28:46 PM PDT 24
Finished Jul 30 06:29:02 PM PDT 24
Peak memory 207156 kb
Host smart-7a59abeb-6123-4d94-a2a2-2cecbd5a75b0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631327483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2631327483
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2600477117
Short name T1075
Test name
Test status
Simulation time 23496606321 ps
CPU time 30.35 seconds
Started Jul 30 06:28:40 PM PDT 24
Finished Jul 30 06:29:10 PM PDT 24
Peak memory 207124 kb
Host smart-fd432989-6799-4cba-9fb2-7488a78b8317
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600477117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.2600477117
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3706015060
Short name T2712
Test name
Test status
Simulation time 159603497 ps
CPU time 0.83 seconds
Started Jul 30 06:28:25 PM PDT 24
Finished Jul 30 06:28:26 PM PDT 24
Peak memory 206988 kb
Host smart-95139d56-0f1b-4514-a556-13105c0adc41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37060
15060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3706015060
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.1137523204
Short name T593
Test name
Test status
Simulation time 144939885 ps
CPU time 0.81 seconds
Started Jul 30 06:28:32 PM PDT 24
Finished Jul 30 06:28:33 PM PDT 24
Peak memory 206888 kb
Host smart-752ec1f6-7b51-4d00-9bd0-e3177ab19c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11375
23204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.1137523204
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.1327255370
Short name T1789
Test name
Test status
Simulation time 353142116 ps
CPU time 1.35 seconds
Started Jul 30 06:28:46 PM PDT 24
Finished Jul 30 06:28:47 PM PDT 24
Peak memory 206936 kb
Host smart-d1cfcd2e-4186-4392-b9ad-bc394e23da00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13272
55370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.1327255370
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2243310621
Short name T2715
Test name
Test status
Simulation time 658563190 ps
CPU time 1.73 seconds
Started Jul 30 06:28:42 PM PDT 24
Finished Jul 30 06:28:44 PM PDT 24
Peak memory 206944 kb
Host smart-b2605910-4339-4de8-93b9-b0e9b30a4603
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2243310621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2243310621
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.497560041
Short name T1904
Test name
Test status
Simulation time 19778607729 ps
CPU time 42.11 seconds
Started Jul 30 06:28:37 PM PDT 24
Finished Jul 30 06:29:19 PM PDT 24
Peak memory 207136 kb
Host smart-a35d31d0-0048-4547-87b0-3cd6dfd033f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49756
0041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.497560041
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.2417639322
Short name T1501
Test name
Test status
Simulation time 1002019367 ps
CPU time 22.59 seconds
Started Jul 30 06:28:25 PM PDT 24
Finished Jul 30 06:28:47 PM PDT 24
Peak memory 206964 kb
Host smart-ae3ddd56-b50f-4e2c-a96c-8d71c2a8d71c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417639322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.2417639322
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.850519763
Short name T755
Test name
Test status
Simulation time 310048359 ps
CPU time 1.19 seconds
Started Jul 30 06:28:41 PM PDT 24
Finished Jul 30 06:28:43 PM PDT 24
Peak memory 206880 kb
Host smart-f115289f-45ba-4f2c-9223-45e5ec4a2010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85051
9763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.850519763
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2501953928
Short name T2094
Test name
Test status
Simulation time 156294040 ps
CPU time 0.9 seconds
Started Jul 30 06:28:30 PM PDT 24
Finished Jul 30 06:28:31 PM PDT 24
Peak memory 206876 kb
Host smart-8be604dd-b841-4bd9-a361-1b85d8b9bd0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25019
53928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2501953928
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.308731773
Short name T232
Test name
Test status
Simulation time 45182412 ps
CPU time 0.7 seconds
Started Jul 30 06:28:38 PM PDT 24
Finished Jul 30 06:28:39 PM PDT 24
Peak memory 206888 kb
Host smart-ebe12fcf-1482-4c48-870c-ce4c628b5182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30873
1773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.308731773
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.2434546232
Short name T1898
Test name
Test status
Simulation time 1031330267 ps
CPU time 2.57 seconds
Started Jul 30 06:28:42 PM PDT 24
Finished Jul 30 06:28:45 PM PDT 24
Peak memory 207060 kb
Host smart-91c30012-47aa-4e3c-9c73-3fad9be47d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24345
46232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.2434546232
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1769577823
Short name T1011
Test name
Test status
Simulation time 297606086 ps
CPU time 2.16 seconds
Started Jul 30 06:28:31 PM PDT 24
Finished Jul 30 06:28:34 PM PDT 24
Peak memory 207056 kb
Host smart-e8b29d56-c03d-4e58-9a60-9bfd16a2e968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17695
77823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1769577823
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.4053506482
Short name T639
Test name
Test status
Simulation time 242389879 ps
CPU time 0.99 seconds
Started Jul 30 06:28:40 PM PDT 24
Finished Jul 30 06:28:41 PM PDT 24
Peak memory 207004 kb
Host smart-bcb9422d-cea1-40b3-a905-02912c84a4bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4053506482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.4053506482
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2979054863
Short name T1132
Test name
Test status
Simulation time 146119268 ps
CPU time 0.86 seconds
Started Jul 30 06:28:39 PM PDT 24
Finished Jul 30 06:28:40 PM PDT 24
Peak memory 206872 kb
Host smart-ee62048f-4ff3-4f1a-8004-457e5928b5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29790
54863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2979054863
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3424495374
Short name T1048
Test name
Test status
Simulation time 240697646 ps
CPU time 1.02 seconds
Started Jul 30 06:28:48 PM PDT 24
Finished Jul 30 06:28:49 PM PDT 24
Peak memory 206920 kb
Host smart-d0358cd2-fc4e-47a8-8694-7b28d74a27d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34244
95374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3424495374
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.3617231161
Short name T764
Test name
Test status
Simulation time 7607207934 ps
CPU time 75.88 seconds
Started Jul 30 06:28:43 PM PDT 24
Finished Jul 30 06:30:00 PM PDT 24
Peak memory 216796 kb
Host smart-45f856f5-e0a7-4dda-ab00-c5f797d630fa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3617231161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.3617231161
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3475928434
Short name T1626
Test name
Test status
Simulation time 228700755 ps
CPU time 0.97 seconds
Started Jul 30 06:28:25 PM PDT 24
Finished Jul 30 06:28:26 PM PDT 24
Peak memory 206888 kb
Host smart-94ec35fc-9d2f-490e-8fed-c2f96814da34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34759
28434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3475928434
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.3011702945
Short name T477
Test name
Test status
Simulation time 23348834061 ps
CPU time 30.58 seconds
Started Jul 30 06:28:48 PM PDT 24
Finished Jul 30 06:29:19 PM PDT 24
Peak memory 207112 kb
Host smart-042fd8ac-908b-4df9-91cc-e69ea89c090c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30117
02945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.3011702945
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1768450931
Short name T608
Test name
Test status
Simulation time 3297163760 ps
CPU time 4.86 seconds
Started Jul 30 06:28:46 PM PDT 24
Finished Jul 30 06:28:51 PM PDT 24
Peak memory 207068 kb
Host smart-bb7164f9-30a1-4611-9688-e784f91b2170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17684
50931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1768450931
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.1042043275
Short name T2778
Test name
Test status
Simulation time 6794175754 ps
CPU time 193.69 seconds
Started Jul 30 06:28:48 PM PDT 24
Finished Jul 30 06:32:02 PM PDT 24
Peak memory 215284 kb
Host smart-047c1aff-2e7b-4e26-863d-9e846b6ecf84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10420
43275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1042043275
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3324645073
Short name T1461
Test name
Test status
Simulation time 6144166694 ps
CPU time 176.7 seconds
Started Jul 30 06:28:43 PM PDT 24
Finished Jul 30 06:31:40 PM PDT 24
Peak memory 215288 kb
Host smart-3947de0f-5068-4cac-9fda-ff02c6581a7b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3324645073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3324645073
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.3140104650
Short name T2243
Test name
Test status
Simulation time 309968307 ps
CPU time 1.15 seconds
Started Jul 30 06:28:39 PM PDT 24
Finished Jul 30 06:28:40 PM PDT 24
Peak memory 207004 kb
Host smart-c0f7c652-4650-42f8-a3e7-55510ffbf049
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3140104650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.3140104650
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3095710331
Short name T414
Test name
Test status
Simulation time 249109448 ps
CPU time 1 seconds
Started Jul 30 06:28:44 PM PDT 24
Finished Jul 30 06:28:45 PM PDT 24
Peak memory 206936 kb
Host smart-dcd12fa2-f382-4ac2-a091-b7c132f9c2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30957
10331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3095710331
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.3485600240
Short name T151
Test name
Test status
Simulation time 4129900129 ps
CPU time 31.71 seconds
Started Jul 30 06:28:47 PM PDT 24
Finished Jul 30 06:29:19 PM PDT 24
Peak memory 216628 kb
Host smart-f656e9d3-7f44-422a-ba82-a52a9cbcbfbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34856
00240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.3485600240
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.2677793230
Short name T1509
Test name
Test status
Simulation time 5334121210 ps
CPU time 55.85 seconds
Started Jul 30 06:28:44 PM PDT 24
Finished Jul 30 06:29:40 PM PDT 24
Peak memory 207100 kb
Host smart-84b3b7f5-4535-41bb-bc2c-ef6b257f4267
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2677793230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.2677793230
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.3793176137
Short name T2560
Test name
Test status
Simulation time 244457531 ps
CPU time 0.99 seconds
Started Jul 30 06:28:46 PM PDT 24
Finished Jul 30 06:28:47 PM PDT 24
Peak memory 206944 kb
Host smart-c5cb0ed3-1a68-478b-9543-3f72ac04c8c5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3793176137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.3793176137
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1586735005
Short name T1291
Test name
Test status
Simulation time 162302239 ps
CPU time 0.85 seconds
Started Jul 30 06:28:43 PM PDT 24
Finished Jul 30 06:28:44 PM PDT 24
Peak memory 206932 kb
Host smart-26bec957-51dd-4150-90c3-f78b5154f7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15867
35005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1586735005
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2715562865
Short name T126
Test name
Test status
Simulation time 296970439 ps
CPU time 1.16 seconds
Started Jul 30 06:28:42 PM PDT 24
Finished Jul 30 06:28:43 PM PDT 24
Peak memory 206928 kb
Host smart-357a63af-5b72-4476-96d1-dd291f9c8bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27155
62865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2715562865
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.442526262
Short name T1233
Test name
Test status
Simulation time 157235111 ps
CPU time 0.87 seconds
Started Jul 30 06:28:46 PM PDT 24
Finished Jul 30 06:28:47 PM PDT 24
Peak memory 206928 kb
Host smart-26dda1a3-0e65-411e-b30f-18ff9e578863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44252
6262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.442526262
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2248427973
Short name T1591
Test name
Test status
Simulation time 233760387 ps
CPU time 0.97 seconds
Started Jul 30 06:28:45 PM PDT 24
Finished Jul 30 06:28:46 PM PDT 24
Peak memory 206980 kb
Host smart-d5be60cc-25b7-452d-8c21-d557c765f886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22484
27973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2248427973
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1395176025
Short name T2453
Test name
Test status
Simulation time 265974553 ps
CPU time 0.99 seconds
Started Jul 30 06:28:49 PM PDT 24
Finished Jul 30 06:28:50 PM PDT 24
Peak memory 206888 kb
Host smart-be0bfc36-d663-44da-accf-23ca3c76b056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13951
76025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1395176025
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.264329569
Short name T1337
Test name
Test status
Simulation time 224007769 ps
CPU time 0.95 seconds
Started Jul 30 06:28:50 PM PDT 24
Finished Jul 30 06:28:51 PM PDT 24
Peak memory 206888 kb
Host smart-05247a88-28e3-4fa7-abdb-480d5a663aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26432
9569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.264329569
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.3681330738
Short name T1326
Test name
Test status
Simulation time 260965686 ps
CPU time 1.08 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 206956 kb
Host smart-1f83bbcf-8607-4af9-bee5-beb0a5028e9e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3681330738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.3681330738
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3128458848
Short name T2220
Test name
Test status
Simulation time 143060366 ps
CPU time 0.83 seconds
Started Jul 30 06:28:54 PM PDT 24
Finished Jul 30 06:28:55 PM PDT 24
Peak memory 206908 kb
Host smart-d98d99bf-1e74-4dd5-a077-a7df16767c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31284
58848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3128458848
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1071577381
Short name T2048
Test name
Test status
Simulation time 38536715 ps
CPU time 0.69 seconds
Started Jul 30 06:28:47 PM PDT 24
Finished Jul 30 06:28:48 PM PDT 24
Peak memory 206864 kb
Host smart-d9908c3a-275c-49a8-bff9-9705ea0e94fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10715
77381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1071577381
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2994725401
Short name T2046
Test name
Test status
Simulation time 20169090875 ps
CPU time 50.53 seconds
Started Jul 30 06:28:43 PM PDT 24
Finished Jul 30 06:29:33 PM PDT 24
Peak memory 215280 kb
Host smart-61c08208-af7e-44ab-ac71-472ca15ce7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29947
25401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2994725401
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.1412838656
Short name T682
Test name
Test status
Simulation time 167930818 ps
CPU time 0.92 seconds
Started Jul 30 06:28:53 PM PDT 24
Finished Jul 30 06:28:54 PM PDT 24
Peak memory 206944 kb
Host smart-c69a9128-2b89-46dc-9883-bb6ccc572715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14128
38656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.1412838656
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.4268085730
Short name T1922
Test name
Test status
Simulation time 156355940 ps
CPU time 0.89 seconds
Started Jul 30 06:28:45 PM PDT 24
Finished Jul 30 06:28:46 PM PDT 24
Peak memory 206908 kb
Host smart-0e8ae15d-a3bf-4916-8f8d-f4f06ea1db1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42680
85730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.4268085730
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.776149692
Short name T2840
Test name
Test status
Simulation time 13634848710 ps
CPU time 396.36 seconds
Started Jul 30 06:28:46 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 215384 kb
Host smart-ce56700f-9234-401a-a45e-e55bb86ed438
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=776149692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.776149692
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3703812015
Short name T2172
Test name
Test status
Simulation time 8143041576 ps
CPU time 40 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:29:32 PM PDT 24
Peak memory 223304 kb
Host smart-5190fcc3-0fe3-4270-bc6b-4177d0429bde
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3703812015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3703812015
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.1700662176
Short name T2443
Test name
Test status
Simulation time 13206857900 ps
CPU time 73.76 seconds
Started Jul 30 06:28:49 PM PDT 24
Finished Jul 30 06:30:03 PM PDT 24
Peak memory 217308 kb
Host smart-76eba98e-0790-475f-a4fb-dea430aca7e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700662176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.1700662176
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.215329311
Short name T1564
Test name
Test status
Simulation time 201382931 ps
CPU time 0.86 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 206988 kb
Host smart-7de1d30c-dc62-4d05-8a57-1838c5421adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21532
9311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.215329311
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.16968627
Short name T1088
Test name
Test status
Simulation time 184203639 ps
CPU time 0.89 seconds
Started Jul 30 06:28:46 PM PDT 24
Finished Jul 30 06:28:47 PM PDT 24
Peak memory 206888 kb
Host smart-933e1c84-4571-4158-be7c-43f7bef55b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16968
627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.16968627
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.632976920
Short name T2856
Test name
Test status
Simulation time 154145125 ps
CPU time 0.85 seconds
Started Jul 30 06:28:51 PM PDT 24
Finished Jul 30 06:28:52 PM PDT 24
Peak memory 206884 kb
Host smart-adc92849-e86d-4359-9b73-4fdd3edaf9ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63297
6920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.632976920
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3146660478
Short name T754
Test name
Test status
Simulation time 160387561 ps
CPU time 0.87 seconds
Started Jul 30 06:28:54 PM PDT 24
Finished Jul 30 06:28:55 PM PDT 24
Peak memory 206908 kb
Host smart-706943ac-7dcb-448e-a4e0-9ac9c5279eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31466
60478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3146660478
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.4140697438
Short name T856
Test name
Test status
Simulation time 156760486 ps
CPU time 0.85 seconds
Started Jul 30 06:28:47 PM PDT 24
Finished Jul 30 06:28:48 PM PDT 24
Peak memory 206944 kb
Host smart-cad454aa-7f1f-4df1-b57e-56feb1ffaf7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41406
97438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.4140697438
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1697551758
Short name T2639
Test name
Test status
Simulation time 292700769 ps
CPU time 1.1 seconds
Started Jul 30 06:28:44 PM PDT 24
Finished Jul 30 06:28:46 PM PDT 24
Peak memory 206972 kb
Host smart-a96e3ded-2bd2-4f1a-824a-af90e411c3cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16975
51758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1697551758
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.1222540050
Short name T150
Test name
Test status
Simulation time 4019079869 ps
CPU time 39.85 seconds
Started Jul 30 06:28:51 PM PDT 24
Finished Jul 30 06:29:31 PM PDT 24
Peak memory 215336 kb
Host smart-1b9a3ce8-4538-4c5a-b4be-a52766a46041
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1222540050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.1222540050
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3920297102
Short name T1492
Test name
Test status
Simulation time 192916346 ps
CPU time 0.9 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:58 PM PDT 24
Peak memory 206948 kb
Host smart-57697dda-578b-4dfd-ba7f-7425516225e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39202
97102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3920297102
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2843885240
Short name T2860
Test name
Test status
Simulation time 175561977 ps
CPU time 1.02 seconds
Started Jul 30 06:28:47 PM PDT 24
Finished Jul 30 06:28:48 PM PDT 24
Peak memory 206984 kb
Host smart-26e6bcdf-6b2a-4cef-9bab-5ab8dde59010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28438
85240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2843885240
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.1937294682
Short name T2484
Test name
Test status
Simulation time 1243096679 ps
CPU time 3.2 seconds
Started Jul 30 06:28:51 PM PDT 24
Finished Jul 30 06:28:55 PM PDT 24
Peak memory 206980 kb
Host smart-34f80e78-e407-416a-8b9b-79438363c720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19372
94682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.1937294682
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.533485985
Short name T1913
Test name
Test status
Simulation time 5868389561 ps
CPU time 168.63 seconds
Started Jul 30 06:28:45 PM PDT 24
Finished Jul 30 06:31:34 PM PDT 24
Peak memory 215332 kb
Host smart-5c2c3e6c-2837-4f28-be3f-7eafbaf90dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53348
5985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.533485985
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.193190695
Short name T17
Test name
Test status
Simulation time 760729928 ps
CPU time 15.3 seconds
Started Jul 30 06:28:36 PM PDT 24
Finished Jul 30 06:28:52 PM PDT 24
Peak memory 206988 kb
Host smart-3b59b8a2-a298-41e6-a0c6-e316d1d17f15
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193190695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host_
handshake.193190695
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.342303604
Short name T2442
Test name
Test status
Simulation time 44280479 ps
CPU time 0.67 seconds
Started Jul 30 06:28:59 PM PDT 24
Finished Jul 30 06:28:59 PM PDT 24
Peak memory 207056 kb
Host smart-e52f9331-17cb-4058-adc8-d603f4fe7106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=342303604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.342303604
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3353576954
Short name T1082
Test name
Test status
Simulation time 3521441053 ps
CPU time 5.53 seconds
Started Jul 30 06:28:53 PM PDT 24
Finished Jul 30 06:28:58 PM PDT 24
Peak memory 207080 kb
Host smart-40116a34-6baf-4969-8d28-14a9d3e55c15
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353576954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.3353576954
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.4239121704
Short name T1368
Test name
Test status
Simulation time 13355161613 ps
CPU time 18.8 seconds
Started Jul 30 06:28:48 PM PDT 24
Finished Jul 30 06:29:07 PM PDT 24
Peak memory 207148 kb
Host smart-9b2bbc30-1dbb-4cf5-982f-3ff934c33766
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239121704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.4239121704
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.29310118
Short name T915
Test name
Test status
Simulation time 23334345761 ps
CPU time 35.88 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:29:28 PM PDT 24
Peak memory 207120 kb
Host smart-2b779a5e-74d3-4bd7-a80a-4f3b7fd5ccd7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29310118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_
wake_resume.29310118
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1295593440
Short name T1376
Test name
Test status
Simulation time 210170450 ps
CPU time 0.9 seconds
Started Jul 30 06:28:49 PM PDT 24
Finished Jul 30 06:28:50 PM PDT 24
Peak memory 206868 kb
Host smart-3e2e4d9d-5b03-4a45-9c8e-8cbe01660e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12955
93440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1295593440
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.2718369312
Short name T375
Test name
Test status
Simulation time 149244714 ps
CPU time 0.85 seconds
Started Jul 30 06:28:50 PM PDT 24
Finished Jul 30 06:28:51 PM PDT 24
Peak memory 206896 kb
Host smart-688323b8-405a-47c2-afd0-e0b17c26157f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27183
69312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.2718369312
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.3989021438
Short name T1102
Test name
Test status
Simulation time 199292488 ps
CPU time 0.96 seconds
Started Jul 30 06:28:50 PM PDT 24
Finished Jul 30 06:28:51 PM PDT 24
Peak memory 206904 kb
Host smart-638ad295-e46b-4b29-9412-258adab64b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39890
21438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.3989021438
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.4114080662
Short name T77
Test name
Test status
Simulation time 843911770 ps
CPU time 2.31 seconds
Started Jul 30 06:28:53 PM PDT 24
Finished Jul 30 06:28:56 PM PDT 24
Peak memory 207036 kb
Host smart-1d56b88f-740c-4386-b35a-5835c3e5ee4f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4114080662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.4114080662
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.496688846
Short name T2482
Test name
Test status
Simulation time 15673672358 ps
CPU time 31.78 seconds
Started Jul 30 06:28:56 PM PDT 24
Finished Jul 30 06:29:28 PM PDT 24
Peak memory 207140 kb
Host smart-915946f4-4ea1-48a1-b43e-ed133e14ef08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49668
8846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.496688846
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.2171536883
Short name T1629
Test name
Test status
Simulation time 5702590415 ps
CPU time 40.17 seconds
Started Jul 30 06:28:48 PM PDT 24
Finished Jul 30 06:29:28 PM PDT 24
Peak memory 207164 kb
Host smart-61e33b42-4fd8-4293-b8df-654201fd1b70
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171536883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.2171536883
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3161349360
Short name T2508
Test name
Test status
Simulation time 449628495 ps
CPU time 1.77 seconds
Started Jul 30 06:28:53 PM PDT 24
Finished Jul 30 06:28:55 PM PDT 24
Peak memory 206880 kb
Host smart-82954b95-461e-440c-9660-56a57893b1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31613
49360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3161349360
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2127666134
Short name T2003
Test name
Test status
Simulation time 152296535 ps
CPU time 0.81 seconds
Started Jul 30 06:28:46 PM PDT 24
Finished Jul 30 06:28:47 PM PDT 24
Peak memory 206904 kb
Host smart-a2aa881f-95fd-4b92-8a70-2d40a49bd791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21276
66134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2127666134
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.436820937
Short name T1506
Test name
Test status
Simulation time 62017731 ps
CPU time 0.71 seconds
Started Jul 30 06:28:51 PM PDT 24
Finished Jul 30 06:28:52 PM PDT 24
Peak memory 206876 kb
Host smart-516833c8-95c7-49cd-a3fc-c2de43d5782a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43682
0937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.436820937
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.2878749497
Short name T1675
Test name
Test status
Simulation time 866912590 ps
CPU time 2.4 seconds
Started Jul 30 06:28:49 PM PDT 24
Finished Jul 30 06:28:52 PM PDT 24
Peak memory 207052 kb
Host smart-3a49528f-af5c-4737-9fa9-e5b620b6efab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28787
49497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2878749497
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2859486480
Short name T2262
Test name
Test status
Simulation time 209865480 ps
CPU time 2.43 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:55 PM PDT 24
Peak memory 206988 kb
Host smart-57a9a404-c081-46a3-bba4-9ab251da7ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28594
86480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2859486480
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.4073665974
Short name T848
Test name
Test status
Simulation time 186784272 ps
CPU time 1.04 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 207012 kb
Host smart-c569723e-5be7-409f-943b-4ecd42fe168b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4073665974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.4073665974
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2516746786
Short name T2346
Test name
Test status
Simulation time 189131763 ps
CPU time 0.83 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 206944 kb
Host smart-d4d8730c-946e-470d-a495-76c815e10752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25167
46786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2516746786
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2370239851
Short name T2819
Test name
Test status
Simulation time 227298485 ps
CPU time 0.94 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 206900 kb
Host smart-d18e4753-032b-45fa-af60-b0a00cea9fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23702
39851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2370239851
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.4045663011
Short name T2841
Test name
Test status
Simulation time 6471751421 ps
CPU time 67.98 seconds
Started Jul 30 06:28:50 PM PDT 24
Finished Jul 30 06:29:58 PM PDT 24
Peak memory 216872 kb
Host smart-3c50d60d-1e5c-45ca-a0af-63aa114880b7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4045663011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.4045663011
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.1583548683
Short name T2514
Test name
Test status
Simulation time 13410685386 ps
CPU time 81.49 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:30:14 PM PDT 24
Peak memory 207128 kb
Host smart-bd611fe9-a87f-45e9-a4e0-11c8f5d3cf48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1583548683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.1583548683
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.932236641
Short name T1338
Test name
Test status
Simulation time 208869952 ps
CPU time 0.94 seconds
Started Jul 30 06:28:49 PM PDT 24
Finished Jul 30 06:28:50 PM PDT 24
Peak memory 206912 kb
Host smart-14dd1e52-34b0-4b9a-b89e-6164676e191c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93223
6641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.932236641
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2691006760
Short name T2241
Test name
Test status
Simulation time 23254557224 ps
CPU time 26.3 seconds
Started Jul 30 06:28:47 PM PDT 24
Finished Jul 30 06:29:13 PM PDT 24
Peak memory 207180 kb
Host smart-04c80344-e666-4be1-9177-7c5ef5eee072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26910
06760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2691006760
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.897453519
Short name T2409
Test name
Test status
Simulation time 3336974722 ps
CPU time 5.73 seconds
Started Jul 30 06:28:57 PM PDT 24
Finished Jul 30 06:29:03 PM PDT 24
Peak memory 207052 kb
Host smart-e6fe0497-00d6-40a2-ac69-c54dd4e8caf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89745
3519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.897453519
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2190495070
Short name T2339
Test name
Test status
Simulation time 4565466618 ps
CPU time 130.98 seconds
Started Jul 30 06:28:53 PM PDT 24
Finished Jul 30 06:31:04 PM PDT 24
Peak memory 215292 kb
Host smart-0ca75740-f954-45b5-9449-9e019e7f18df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21904
95070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2190495070
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3169461151
Short name T1195
Test name
Test status
Simulation time 7103250245 ps
CPU time 198.2 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:32:16 PM PDT 24
Peak memory 215304 kb
Host smart-7fb6764d-748a-48f4-a590-2b66bc8b82fc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3169461151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3169461151
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.3099639634
Short name T1106
Test name
Test status
Simulation time 253541725 ps
CPU time 0.96 seconds
Started Jul 30 06:28:57 PM PDT 24
Finished Jul 30 06:28:58 PM PDT 24
Peak memory 206956 kb
Host smart-87fa34f6-d523-4198-be11-dc8e8b042daf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3099639634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.3099639634
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1907678327
Short name T364
Test name
Test status
Simulation time 207378289 ps
CPU time 1.05 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 206944 kb
Host smart-09d06dac-16bc-4753-bf9b-842e2708121b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19076
78327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1907678327
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2319572407
Short name T374
Test name
Test status
Simulation time 5419191551 ps
CPU time 50.42 seconds
Started Jul 30 06:28:50 PM PDT 24
Finished Jul 30 06:29:41 PM PDT 24
Peak memory 215352 kb
Host smart-299634a2-207a-4521-8982-a536547d4044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23195
72407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2319572407
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.554308104
Short name T2536
Test name
Test status
Simulation time 7309402840 ps
CPU time 72.4 seconds
Started Jul 30 06:28:53 PM PDT 24
Finished Jul 30 06:30:05 PM PDT 24
Peak memory 207092 kb
Host smart-7882d7c1-a413-4938-a5f9-bf458567bb81
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=554308104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.554308104
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2701353473
Short name T1588
Test name
Test status
Simulation time 161704061 ps
CPU time 0.86 seconds
Started Jul 30 06:28:53 PM PDT 24
Finished Jul 30 06:28:54 PM PDT 24
Peak memory 206908 kb
Host smart-5be20d5d-e758-4342-9162-4c49f2e3fef5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2701353473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2701353473
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1312421146
Short name T1742
Test name
Test status
Simulation time 155444006 ps
CPU time 0.9 seconds
Started Jul 30 06:28:46 PM PDT 24
Finished Jul 30 06:28:47 PM PDT 24
Peak memory 206944 kb
Host smart-0d613d64-f1e0-440d-98a1-175a637abae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13124
21146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1312421146
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.275066838
Short name T1921
Test name
Test status
Simulation time 210531328 ps
CPU time 0.93 seconds
Started Jul 30 06:28:53 PM PDT 24
Finished Jul 30 06:28:54 PM PDT 24
Peak memory 206908 kb
Host smart-e96b98a7-98eb-40b1-a610-4f24bbb20e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27506
6838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.275066838
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3434985394
Short name T956
Test name
Test status
Simulation time 186426182 ps
CPU time 0.91 seconds
Started Jul 30 06:28:53 PM PDT 24
Finished Jul 30 06:28:54 PM PDT 24
Peak memory 206908 kb
Host smart-5c0000cb-a0ae-4d4c-ba2b-0fc772d0d448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34349
85394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3434985394
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3031182664
Short name T1798
Test name
Test status
Simulation time 156701022 ps
CPU time 0.88 seconds
Started Jul 30 06:28:49 PM PDT 24
Finished Jul 30 06:28:50 PM PDT 24
Peak memory 206976 kb
Host smart-7f5cbef7-ba86-4384-a279-a80ce618f8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30311
82664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3031182664
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3865268828
Short name T986
Test name
Test status
Simulation time 161570703 ps
CPU time 0.9 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:28:59 PM PDT 24
Peak memory 206912 kb
Host smart-c2471a40-d0b1-41ea-86eb-21f75b309188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38652
68828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3865268828
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3369084469
Short name T785
Test name
Test status
Simulation time 171614905 ps
CPU time 0.85 seconds
Started Jul 30 06:28:55 PM PDT 24
Finished Jul 30 06:28:56 PM PDT 24
Peak memory 206932 kb
Host smart-84fc26c8-ff3d-424e-8bf5-acd1182415fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33690
84469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3369084469
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.665538779
Short name T926
Test name
Test status
Simulation time 222648466 ps
CPU time 0.98 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:28:59 PM PDT 24
Peak memory 206912 kb
Host smart-42511581-33da-4338-bd67-7d92622b8f6a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=665538779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.665538779
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2542314821
Short name T419
Test name
Test status
Simulation time 146874319 ps
CPU time 0.92 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:28:59 PM PDT 24
Peak memory 206892 kb
Host smart-cbe9334d-30a5-4dcd-9ecd-f6ea93fc9e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25423
14821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2542314821
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1887970404
Short name T1489
Test name
Test status
Simulation time 54170861 ps
CPU time 0.7 seconds
Started Jul 30 06:28:56 PM PDT 24
Finished Jul 30 06:28:57 PM PDT 24
Peak memory 206884 kb
Host smart-6d7e379a-a5ad-41db-acba-f8304e88933a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18879
70404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1887970404
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3205846998
Short name T2490
Test name
Test status
Simulation time 15941957754 ps
CPU time 38.3 seconds
Started Jul 30 06:28:56 PM PDT 24
Finished Jul 30 06:29:34 PM PDT 24
Peak memory 215388 kb
Host smart-aae79404-08c8-418a-af92-f6819269ebd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32058
46998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3205846998
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.4291523125
Short name T778
Test name
Test status
Simulation time 253291675 ps
CPU time 1.03 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 206940 kb
Host smart-6580910e-4ab8-42f4-8fa3-8cb273799871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42915
23125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.4291523125
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1315358896
Short name T858
Test name
Test status
Simulation time 219021874 ps
CPU time 0.99 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 206884 kb
Host smart-f259e739-37e6-4689-814c-d584a9dd9159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13153
58896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1315358896
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.1630925560
Short name T1926
Test name
Test status
Simulation time 13966814821 ps
CPU time 115.91 seconds
Started Jul 30 06:28:57 PM PDT 24
Finished Jul 30 06:30:53 PM PDT 24
Peak memory 217136 kb
Host smart-09d6f51c-5e98-4d96-95c1-3c795e0288cb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630925560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1630925560
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3287408521
Short name T1977
Test name
Test status
Simulation time 8941049622 ps
CPU time 82.64 seconds
Started Jul 30 06:28:50 PM PDT 24
Finished Jul 30 06:30:13 PM PDT 24
Peak memory 217316 kb
Host smart-2d5c3ad4-2ae9-4f0e-8780-680ffa5c9f5c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3287408521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3287408521
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.3989908849
Short name T2786
Test name
Test status
Simulation time 11044414828 ps
CPU time 75.28 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:30:07 PM PDT 24
Peak memory 223276 kb
Host smart-86775a40-9ba6-4e35-a7db-4742b417a62a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989908849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.3989908849
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2125388097
Short name T2629
Test name
Test status
Simulation time 176393441 ps
CPU time 0.87 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 206980 kb
Host smart-aa1916a5-0756-4e9a-baea-14e6eb6d3510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21253
88097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2125388097
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.4290050657
Short name T330
Test name
Test status
Simulation time 207005341 ps
CPU time 0.91 seconds
Started Jul 30 06:28:54 PM PDT 24
Finished Jul 30 06:28:55 PM PDT 24
Peak memory 206912 kb
Host smart-ab2eda35-cf81-4ed8-9ad4-a97902fe7d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42900
50657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.4290050657
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1189424757
Short name T2374
Test name
Test status
Simulation time 184517334 ps
CPU time 0.89 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 206672 kb
Host smart-41f64f35-68cd-43c8-9bc1-6c21605bd9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11894
24757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1189424757
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.2919514318
Short name T2417
Test name
Test status
Simulation time 151276983 ps
CPU time 0.85 seconds
Started Jul 30 06:28:46 PM PDT 24
Finished Jul 30 06:28:47 PM PDT 24
Peak memory 206876 kb
Host smart-1aeec489-fb35-4686-941b-e8c5c8a0ecb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29195
14318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2919514318
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1850170710
Short name T2598
Test name
Test status
Simulation time 152473612 ps
CPU time 0.85 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:28:59 PM PDT 24
Peak memory 206900 kb
Host smart-c0737673-d880-48c9-b619-62ec06873df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18501
70710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1850170710
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1871660723
Short name T962
Test name
Test status
Simulation time 214798352 ps
CPU time 0.93 seconds
Started Jul 30 06:28:56 PM PDT 24
Finished Jul 30 06:28:57 PM PDT 24
Peak memory 206652 kb
Host smart-654a66d9-1e16-456a-8743-f1b53469c34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18716
60723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1871660723
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3644553080
Short name T2200
Test name
Test status
Simulation time 3922853497 ps
CPU time 40.98 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:29:39 PM PDT 24
Peak memory 216528 kb
Host smart-9ec48648-8dbb-465b-9cb7-1a4eaac54a94
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3644553080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3644553080
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.1589428417
Short name T56
Test name
Test status
Simulation time 187494128 ps
CPU time 0.86 seconds
Started Jul 30 06:28:55 PM PDT 24
Finished Jul 30 06:28:56 PM PDT 24
Peak memory 206984 kb
Host smart-b1ad738b-b6c6-446a-9e52-6ccf8066b0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15894
28417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.1589428417
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2023778990
Short name T1837
Test name
Test status
Simulation time 172623599 ps
CPU time 0.91 seconds
Started Jul 30 06:28:49 PM PDT 24
Finished Jul 30 06:28:50 PM PDT 24
Peak memory 206976 kb
Host smart-fa22aea6-e67e-4e18-b028-69ecaf7558c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20237
78990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2023778990
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.1967275498
Short name T397
Test name
Test status
Simulation time 1014784687 ps
CPU time 2.79 seconds
Started Jul 30 06:28:54 PM PDT 24
Finished Jul 30 06:28:57 PM PDT 24
Peak memory 207028 kb
Host smart-c2a77589-09c1-432f-8660-08c161235fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19672
75498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.1967275498
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.26459163
Short name T2364
Test name
Test status
Simulation time 4389964616 ps
CPU time 43.97 seconds
Started Jul 30 06:29:09 PM PDT 24
Finished Jul 30 06:29:53 PM PDT 24
Peak memory 207172 kb
Host smart-80226ed7-7ce0-45f9-89a0-103de619c609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26459
163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.26459163
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.2426695933
Short name T2739
Test name
Test status
Simulation time 1560459184 ps
CPU time 36.15 seconds
Started Jul 30 06:28:50 PM PDT 24
Finished Jul 30 06:29:26 PM PDT 24
Peak memory 207004 kb
Host smart-eb661f64-231b-4470-912f-432faf3ef1b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426695933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host
_handshake.2426695933
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2081302646
Short name T631
Test name
Test status
Simulation time 34052477 ps
CPU time 0.72 seconds
Started Jul 30 06:29:02 PM PDT 24
Finished Jul 30 06:29:03 PM PDT 24
Peak memory 207024 kb
Host smart-a72eea00-569c-4a84-9ec1-4d38de3f6de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2081302646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2081302646
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.553439291
Short name T11
Test name
Test status
Simulation time 3648033323 ps
CPU time 6.09 seconds
Started Jul 30 06:28:55 PM PDT 24
Finished Jul 30 06:29:01 PM PDT 24
Peak memory 207100 kb
Host smart-3387a431-9ef6-4b2a-ae80-1e9f5c1c925a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553439291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon
_wake_disconnect.553439291
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3326060736
Short name T2095
Test name
Test status
Simulation time 13407071672 ps
CPU time 16.78 seconds
Started Jul 30 06:29:01 PM PDT 24
Finished Jul 30 06:29:18 PM PDT 24
Peak memory 207136 kb
Host smart-71119765-f528-4934-9731-e6790df7da7c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326060736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3326060736
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.2870933170
Short name T408
Test name
Test status
Simulation time 23421293710 ps
CPU time 35.51 seconds
Started Jul 30 06:28:56 PM PDT 24
Finished Jul 30 06:29:32 PM PDT 24
Peak memory 207156 kb
Host smart-57a64b6a-c7f2-41f5-a253-de40b1be2da7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870933170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.2870933170
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2449243516
Short name T1870
Test name
Test status
Simulation time 153299618 ps
CPU time 0.8 seconds
Started Jul 30 06:28:53 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 206928 kb
Host smart-4922fc0f-69af-497f-adb6-2d34d4c8d432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24492
43516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2449243516
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3320730449
Short name T1781
Test name
Test status
Simulation time 178525684 ps
CPU time 0.9 seconds
Started Jul 30 06:28:57 PM PDT 24
Finished Jul 30 06:28:58 PM PDT 24
Peak memory 206948 kb
Host smart-6f954f5d-eafb-4007-bdd6-17a22a7df479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33207
30449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3320730449
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.947737759
Short name T2341
Test name
Test status
Simulation time 478565779 ps
CPU time 1.7 seconds
Started Jul 30 06:28:56 PM PDT 24
Finished Jul 30 06:28:58 PM PDT 24
Peak memory 206904 kb
Host smart-62be7b0c-c7d2-4924-9984-12b9d81aa6a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94773
7759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.947737759
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.293642714
Short name T2361
Test name
Test status
Simulation time 721644245 ps
CPU time 2.05 seconds
Started Jul 30 06:28:49 PM PDT 24
Finished Jul 30 06:28:51 PM PDT 24
Peak memory 207052 kb
Host smart-04df97e5-6acd-407c-8728-b8fa0c8c12d7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=293642714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.293642714
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.1211058257
Short name T2224
Test name
Test status
Simulation time 7252179014 ps
CPU time 16.07 seconds
Started Jul 30 06:28:59 PM PDT 24
Finished Jul 30 06:29:15 PM PDT 24
Peak memory 207112 kb
Host smart-093bd4f4-14af-4b22-a9d3-119a2068ec93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12110
58257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.1211058257
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.4046408576
Short name T786
Test name
Test status
Simulation time 167747212 ps
CPU time 0.89 seconds
Started Jul 30 06:28:54 PM PDT 24
Finished Jul 30 06:28:55 PM PDT 24
Peak memory 206928 kb
Host smart-10fe0590-b0ba-41bf-8fe8-45ef99df6e3b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046408576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.4046408576
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.4218959093
Short name T2267
Test name
Test status
Simulation time 456992396 ps
CPU time 1.54 seconds
Started Jul 30 06:29:08 PM PDT 24
Finished Jul 30 06:29:10 PM PDT 24
Peak memory 206484 kb
Host smart-23bba832-5cef-4822-b6aa-94647214253f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42189
59093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.4218959093
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.2729543061
Short name T1572
Test name
Test status
Simulation time 138785432 ps
CPU time 0.83 seconds
Started Jul 30 06:29:00 PM PDT 24
Finished Jul 30 06:29:01 PM PDT 24
Peak memory 206876 kb
Host smart-8d07844d-73de-4b9a-81c3-643c144b4b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27295
43061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2729543061
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2639096134
Short name T1249
Test name
Test status
Simulation time 56223249 ps
CPU time 0.74 seconds
Started Jul 30 06:29:10 PM PDT 24
Finished Jul 30 06:29:11 PM PDT 24
Peak memory 206884 kb
Host smart-e165234c-3d7b-404a-8877-a8318ba25306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26390
96134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2639096134
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.3477666007
Short name T516
Test name
Test status
Simulation time 992200341 ps
CPU time 2.42 seconds
Started Jul 30 06:28:54 PM PDT 24
Finished Jul 30 06:28:57 PM PDT 24
Peak memory 207064 kb
Host smart-c71e3a54-5e7f-4d95-b198-148a7f9e5865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34776
66007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.3477666007
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1972989121
Short name T883
Test name
Test status
Simulation time 190289568 ps
CPU time 1.69 seconds
Started Jul 30 06:29:09 PM PDT 24
Finished Jul 30 06:29:11 PM PDT 24
Peak memory 206992 kb
Host smart-4182ca58-4415-44c4-a935-6a38376cd50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19729
89121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1972989121
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.450980843
Short name T880
Test name
Test status
Simulation time 238756296 ps
CPU time 1.36 seconds
Started Jul 30 06:29:00 PM PDT 24
Finished Jul 30 06:29:01 PM PDT 24
Peak memory 215184 kb
Host smart-716d1a06-608c-4fe6-8886-4937a7ca0fd9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=450980843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.450980843
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.114433402
Short name T635
Test name
Test status
Simulation time 155586179 ps
CPU time 0.85 seconds
Started Jul 30 06:29:11 PM PDT 24
Finished Jul 30 06:29:12 PM PDT 24
Peak memory 206916 kb
Host smart-a538377e-96e5-4050-9c31-800f70112a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11443
3402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.114433402
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.4151128799
Short name T645
Test name
Test status
Simulation time 234113564 ps
CPU time 1.01 seconds
Started Jul 30 06:28:59 PM PDT 24
Finished Jul 30 06:29:00 PM PDT 24
Peak memory 206916 kb
Host smart-2c64ccb3-1cc9-4509-9dce-2511cdf555ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41511
28799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.4151128799
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.3599504015
Short name T1359
Test name
Test status
Simulation time 9511460714 ps
CPU time 98.26 seconds
Started Jul 30 06:28:55 PM PDT 24
Finished Jul 30 06:30:33 PM PDT 24
Peak memory 216564 kb
Host smart-e635cf8b-fcea-4c53-882c-6b28fcc406b2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3599504015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.3599504015
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.369085108
Short name T2162
Test name
Test status
Simulation time 10707283726 ps
CPU time 68.27 seconds
Started Jul 30 06:28:55 PM PDT 24
Finished Jul 30 06:30:04 PM PDT 24
Peak memory 207100 kb
Host smart-da6d73af-790e-4a25-b03a-a24993107d79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=369085108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.369085108
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1560357986
Short name T2311
Test name
Test status
Simulation time 221033788 ps
CPU time 0.95 seconds
Started Jul 30 06:29:09 PM PDT 24
Finished Jul 30 06:29:10 PM PDT 24
Peak memory 206952 kb
Host smart-b3b885d9-66e2-47b3-90b1-752d20eb79a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15603
57986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1560357986
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.3384591016
Short name T35
Test name
Test status
Simulation time 23328774566 ps
CPU time 30.58 seconds
Started Jul 30 06:28:57 PM PDT 24
Finished Jul 30 06:29:28 PM PDT 24
Peak memory 207104 kb
Host smart-4304ee90-733f-48a0-aa16-8c40b99bd0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33845
91016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.3384591016
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1930984450
Short name T2814
Test name
Test status
Simulation time 3381682682 ps
CPU time 4.97 seconds
Started Jul 30 06:29:13 PM PDT 24
Finished Jul 30 06:29:18 PM PDT 24
Peak memory 207096 kb
Host smart-79f0380d-6398-4337-8703-44d2cfecfc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19309
84450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1930984450
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.1430747730
Short name T518
Test name
Test status
Simulation time 9429820941 ps
CPU time 275.36 seconds
Started Jul 30 06:29:11 PM PDT 24
Finished Jul 30 06:33:47 PM PDT 24
Peak memory 215368 kb
Host smart-552064f8-6ed2-494b-b68c-3ce5e379b389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14307
47730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1430747730
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.2579675204
Short name T2041
Test name
Test status
Simulation time 2964562198 ps
CPU time 24.2 seconds
Started Jul 30 06:28:50 PM PDT 24
Finished Jul 30 06:29:15 PM PDT 24
Peak memory 216824 kb
Host smart-99a8c148-422f-44ef-b6da-8089d149bcf6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2579675204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.2579675204
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2740912756
Short name T876
Test name
Test status
Simulation time 243893892 ps
CPU time 1.02 seconds
Started Jul 30 06:28:56 PM PDT 24
Finished Jul 30 06:28:57 PM PDT 24
Peak memory 206940 kb
Host smart-040e5b74-56d2-4aad-a4b0-78d81ac43600
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2740912756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2740912756
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3672496731
Short name T2129
Test name
Test status
Simulation time 249281297 ps
CPU time 1.05 seconds
Started Jul 30 06:29:01 PM PDT 24
Finished Jul 30 06:29:02 PM PDT 24
Peak memory 206960 kb
Host smart-9f261b77-ee83-45ba-9406-0d5a502f786b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36724
96731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3672496731
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1444001279
Short name T580
Test name
Test status
Simulation time 6821598197 ps
CPU time 71.04 seconds
Started Jul 30 06:28:54 PM PDT 24
Finished Jul 30 06:30:05 PM PDT 24
Peak memory 216792 kb
Host smart-b041d47d-6684-45f3-b9d5-8a8e59f8c7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14440
01279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1444001279
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.2013614724
Short name T342
Test name
Test status
Simulation time 6327100782 ps
CPU time 64.87 seconds
Started Jul 30 06:29:08 PM PDT 24
Finished Jul 30 06:30:13 PM PDT 24
Peak memory 207152 kb
Host smart-72e18628-e88b-4fdf-825e-1f84f12caff7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2013614724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.2013614724
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.3202218762
Short name T594
Test name
Test status
Simulation time 154294804 ps
CPU time 0.87 seconds
Started Jul 30 06:28:57 PM PDT 24
Finished Jul 30 06:28:58 PM PDT 24
Peak memory 206908 kb
Host smart-c4891cee-6a69-4c28-8d43-a9db98df9114
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3202218762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.3202218762
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1914703789
Short name T1024
Test name
Test status
Simulation time 166500173 ps
CPU time 0.83 seconds
Started Jul 30 06:28:59 PM PDT 24
Finished Jul 30 06:29:00 PM PDT 24
Peak memory 206936 kb
Host smart-955c30d3-e1af-4cd9-80eb-7bae73832e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19147
03789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1914703789
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.838023602
Short name T1099
Test name
Test status
Simulation time 146155267 ps
CPU time 0.84 seconds
Started Jul 30 06:29:08 PM PDT 24
Finished Jul 30 06:29:09 PM PDT 24
Peak memory 206440 kb
Host smart-69f5f4f9-d64e-4ddf-bd9b-8a7639c0e70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83802
3602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.838023602
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2817028241
Short name T2568
Test name
Test status
Simulation time 160295840 ps
CPU time 0.88 seconds
Started Jul 30 06:28:52 PM PDT 24
Finished Jul 30 06:28:53 PM PDT 24
Peak memory 206920 kb
Host smart-4459ceb3-c01d-4e21-95d6-702543696cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28170
28241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2817028241
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2764195127
Short name T372
Test name
Test status
Simulation time 172626131 ps
CPU time 0.85 seconds
Started Jul 30 06:28:59 PM PDT 24
Finished Jul 30 06:29:00 PM PDT 24
Peak memory 206924 kb
Host smart-a3801279-4847-41bf-87de-75a8d25acfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27641
95127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2764195127
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1298680877
Short name T1222
Test name
Test status
Simulation time 155770847 ps
CPU time 0.86 seconds
Started Jul 30 06:28:56 PM PDT 24
Finished Jul 30 06:28:57 PM PDT 24
Peak memory 206920 kb
Host smart-0c27ef8f-3eae-4ccc-830c-c1004f9c8758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12986
80877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1298680877
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.2087828252
Short name T1749
Test name
Test status
Simulation time 241773299 ps
CPU time 1.06 seconds
Started Jul 30 06:28:55 PM PDT 24
Finished Jul 30 06:28:56 PM PDT 24
Peak memory 206908 kb
Host smart-342c9d8b-5c58-4c6d-ab21-e9a00f610807
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2087828252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.2087828252
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2526107556
Short name T567
Test name
Test status
Simulation time 141137550 ps
CPU time 0.81 seconds
Started Jul 30 06:29:09 PM PDT 24
Finished Jul 30 06:29:10 PM PDT 24
Peak memory 206916 kb
Host smart-fcf9c02d-1444-412e-a59f-c517785eae73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25261
07556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2526107556
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.435784818
Short name T1062
Test name
Test status
Simulation time 37739739 ps
CPU time 0.7 seconds
Started Jul 30 06:28:56 PM PDT 24
Finished Jul 30 06:28:56 PM PDT 24
Peak memory 206884 kb
Host smart-73ba76e5-8bd1-474b-b2f5-63302652b4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43578
4818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.435784818
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.854483778
Short name T235
Test name
Test status
Simulation time 16455247947 ps
CPU time 39.57 seconds
Started Jul 30 06:28:59 PM PDT 24
Finished Jul 30 06:29:39 PM PDT 24
Peak memory 223568 kb
Host smart-2baae8f3-4d8a-4220-b62e-1625ebd22b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85448
3778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.854483778
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2480504595
Short name T794
Test name
Test status
Simulation time 175863258 ps
CPU time 0.97 seconds
Started Jul 30 06:29:10 PM PDT 24
Finished Jul 30 06:29:12 PM PDT 24
Peak memory 206984 kb
Host smart-3c0785df-b9b4-4715-93c5-e80457adf97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24805
04595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2480504595
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.486931420
Short name T1724
Test name
Test status
Simulation time 207703016 ps
CPU time 0.99 seconds
Started Jul 30 06:29:02 PM PDT 24
Finished Jul 30 06:29:03 PM PDT 24
Peak memory 206908 kb
Host smart-acafbb8f-1ad9-4fe0-a29f-6e737b9ccce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48693
1420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.486931420
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1612082817
Short name T957
Test name
Test status
Simulation time 11135537014 ps
CPU time 217 seconds
Started Jul 30 06:29:10 PM PDT 24
Finished Jul 30 06:32:47 PM PDT 24
Peak memory 215388 kb
Host smart-84b5ed64-caa1-452b-ac02-da5e80758158
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612082817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1612082817
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2744942824
Short name T163
Test name
Test status
Simulation time 9882977718 ps
CPU time 197.98 seconds
Started Jul 30 06:29:10 PM PDT 24
Finished Jul 30 06:32:28 PM PDT 24
Peak memory 215348 kb
Host smart-c2deb8bc-c96f-479e-9e0d-6690e3916312
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2744942824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2744942824
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.1778251830
Short name T1574
Test name
Test status
Simulation time 11979364404 ps
CPU time 82.16 seconds
Started Jul 30 06:29:01 PM PDT 24
Finished Jul 30 06:30:24 PM PDT 24
Peak memory 216980 kb
Host smart-8b478d04-4b29-4b71-9708-156c98fc4b61
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778251830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.1778251830
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.2421648357
Short name T1335
Test name
Test status
Simulation time 190387548 ps
CPU time 0.92 seconds
Started Jul 30 06:28:55 PM PDT 24
Finished Jul 30 06:28:56 PM PDT 24
Peak memory 206956 kb
Host smart-78c09561-ba2a-47ad-8338-3ffb8efacc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24216
48357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.2421648357
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2379840001
Short name T1925
Test name
Test status
Simulation time 188682157 ps
CPU time 0.96 seconds
Started Jul 30 06:29:00 PM PDT 24
Finished Jul 30 06:29:01 PM PDT 24
Peak memory 206972 kb
Host smart-cb5ac08f-f606-4f54-b23c-8049a3195714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23798
40001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2379840001
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1365329003
Short name T377
Test name
Test status
Simulation time 173649078 ps
CPU time 0.91 seconds
Started Jul 30 06:29:06 PM PDT 24
Finished Jul 30 06:29:07 PM PDT 24
Peak memory 206908 kb
Host smart-cd263171-20e7-414e-b495-f11092224b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13653
29003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1365329003
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3221987171
Short name T1516
Test name
Test status
Simulation time 142435563 ps
CPU time 0.85 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:28:59 PM PDT 24
Peak memory 206900 kb
Host smart-f00468c2-38e8-44f6-b143-19b8879c92cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32219
87171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3221987171
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.1976913063
Short name T1942
Test name
Test status
Simulation time 151200923 ps
CPU time 0.85 seconds
Started Jul 30 06:29:01 PM PDT 24
Finished Jul 30 06:29:02 PM PDT 24
Peak memory 206924 kb
Host smart-7308ccfe-8a1c-4af0-aae6-04e9f6addb56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19769
13063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.1976913063
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.822066683
Short name T2607
Test name
Test status
Simulation time 208977645 ps
CPU time 0.94 seconds
Started Jul 30 06:29:06 PM PDT 24
Finished Jul 30 06:29:07 PM PDT 24
Peak memory 206908 kb
Host smart-e1fcd17d-f3e5-4a6e-9282-5bae86afc31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82206
6683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.822066683
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.3852363496
Short name T1084
Test name
Test status
Simulation time 6424389737 ps
CPU time 67.48 seconds
Started Jul 30 06:28:57 PM PDT 24
Finished Jul 30 06:30:05 PM PDT 24
Peak memory 216908 kb
Host smart-fcc1ccde-8596-4a13-94aa-2be3f2b99b30
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3852363496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3852363496
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2893255709
Short name T565
Test name
Test status
Simulation time 179418723 ps
CPU time 0.91 seconds
Started Jul 30 06:28:55 PM PDT 24
Finished Jul 30 06:28:56 PM PDT 24
Peak memory 206920 kb
Host smart-e484d196-edb8-4b37-b565-d00186de8687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28932
55709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2893255709
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.801552499
Short name T795
Test name
Test status
Simulation time 179064325 ps
CPU time 0.85 seconds
Started Jul 30 06:29:06 PM PDT 24
Finished Jul 30 06:29:07 PM PDT 24
Peak memory 206908 kb
Host smart-61389928-999f-4c6e-9469-14060829759e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80155
2499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.801552499
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.2293975932
Short name T2619
Test name
Test status
Simulation time 328490929 ps
CPU time 1.2 seconds
Started Jul 30 06:29:03 PM PDT 24
Finished Jul 30 06:29:05 PM PDT 24
Peak memory 206916 kb
Host smart-addac538-ec16-4a36-9eb0-bd8eee79bed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22939
75932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2293975932
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.2002851684
Short name T1641
Test name
Test status
Simulation time 3239377441 ps
CPU time 93.76 seconds
Started Jul 30 06:29:05 PM PDT 24
Finished Jul 30 06:30:39 PM PDT 24
Peak memory 215284 kb
Host smart-cdc2a963-0b10-4d6c-aeeb-223b8c823e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20028
51684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.2002851684
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.1363097787
Short name T1803
Test name
Test status
Simulation time 177721666 ps
CPU time 0.92 seconds
Started Jul 30 06:28:55 PM PDT 24
Finished Jul 30 06:28:56 PM PDT 24
Peak memory 206892 kb
Host smart-83be0dc3-c123-460f-b534-9dfbb5028f8f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363097787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.1363097787
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.2755456353
Short name T1269
Test name
Test status
Simulation time 106464669 ps
CPU time 0.73 seconds
Started Jul 30 06:29:06 PM PDT 24
Finished Jul 30 06:29:07 PM PDT 24
Peak memory 207036 kb
Host smart-a3aecf26-4f48-44b6-a456-889e871bbf6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2755456353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.2755456353
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3529530436
Short name T1962
Test name
Test status
Simulation time 3806661761 ps
CPU time 6.44 seconds
Started Jul 30 06:29:05 PM PDT 24
Finished Jul 30 06:29:11 PM PDT 24
Peak memory 207048 kb
Host smart-83fda396-e3eb-4016-8c4e-6f873e168a3e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529530436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.3529530436
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3563716240
Short name T613
Test name
Test status
Simulation time 13343101200 ps
CPU time 16.46 seconds
Started Jul 30 06:29:11 PM PDT 24
Finished Jul 30 06:29:27 PM PDT 24
Peak memory 207132 kb
Host smart-ace6d133-9e09-4ccb-9069-3fe58fb0229b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563716240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3563716240
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.54783643
Short name T2705
Test name
Test status
Simulation time 23492949679 ps
CPU time 27.34 seconds
Started Jul 30 06:28:59 PM PDT 24
Finished Jul 30 06:29:27 PM PDT 24
Peak memory 207112 kb
Host smart-3c58ecf0-0236-469d-8713-2b3b261c6dc3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54783643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_
wake_resume.54783643
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3380452329
Short name T2045
Test name
Test status
Simulation time 160238837 ps
CPU time 0.8 seconds
Started Jul 30 06:29:00 PM PDT 24
Finished Jul 30 06:29:01 PM PDT 24
Peak memory 206924 kb
Host smart-7e769fba-a5b8-4e4a-9eec-93faa9fabe67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33804
52329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3380452329
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1975424875
Short name T433
Test name
Test status
Simulation time 154405986 ps
CPU time 0.87 seconds
Started Jul 30 06:29:02 PM PDT 24
Finished Jul 30 06:29:03 PM PDT 24
Peak memory 206924 kb
Host smart-28bbb70b-022d-44bb-9cf9-97c72b3cc37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19754
24875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1975424875
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.4275920900
Short name T806
Test name
Test status
Simulation time 505486808 ps
CPU time 1.72 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:29:00 PM PDT 24
Peak memory 206908 kb
Host smart-2ef50577-e42f-414a-8a52-b609aab9e89a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42759
20900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.4275920900
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.4148255375
Short name T769
Test name
Test status
Simulation time 550811336 ps
CPU time 1.61 seconds
Started Jul 30 06:29:03 PM PDT 24
Finished Jul 30 06:29:05 PM PDT 24
Peak memory 206912 kb
Host smart-3f326255-70ab-4149-9f1d-8b0765102011
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4148255375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.4148255375
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2217854912
Short name T2566
Test name
Test status
Simulation time 10846789392 ps
CPU time 23.43 seconds
Started Jul 30 06:28:59 PM PDT 24
Finished Jul 30 06:29:22 PM PDT 24
Peak memory 207116 kb
Host smart-f6e4f619-faca-4bec-8cb7-3c636faad1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22178
54912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2217854912
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.3784100690
Short name T2412
Test name
Test status
Simulation time 829083361 ps
CPU time 5.43 seconds
Started Jul 30 06:29:02 PM PDT 24
Finished Jul 30 06:29:08 PM PDT 24
Peak memory 206984 kb
Host smart-f1018599-c27c-408d-a70d-5f5dd3ae810e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784100690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.3784100690
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.636283587
Short name T1098
Test name
Test status
Simulation time 442633383 ps
CPU time 1.42 seconds
Started Jul 30 06:29:05 PM PDT 24
Finished Jul 30 06:29:07 PM PDT 24
Peak memory 206880 kb
Host smart-c057d478-7761-47d5-aaea-28107aaf1be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63628
3587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.636283587
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.1030314756
Short name T344
Test name
Test status
Simulation time 146912988 ps
CPU time 0.78 seconds
Started Jul 30 06:29:00 PM PDT 24
Finished Jul 30 06:29:01 PM PDT 24
Peak memory 206872 kb
Host smart-c6fe2a93-ca1d-44b7-b2a9-deab56f63378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10303
14756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1030314756
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.113247135
Short name T1457
Test name
Test status
Simulation time 46767769 ps
CPU time 0.77 seconds
Started Jul 30 06:29:02 PM PDT 24
Finished Jul 30 06:29:03 PM PDT 24
Peak memory 206908 kb
Host smart-95ffc028-83e4-419e-af4a-130ad643af53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11324
7135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.113247135
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3181385656
Short name T350
Test name
Test status
Simulation time 946478186 ps
CPU time 2.45 seconds
Started Jul 30 06:28:56 PM PDT 24
Finished Jul 30 06:28:59 PM PDT 24
Peak memory 207056 kb
Host smart-66d92357-204f-4a5f-b51f-e9b40fc99477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31813
85656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3181385656
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.3152743738
Short name T2476
Test name
Test status
Simulation time 409916796 ps
CPU time 2.87 seconds
Started Jul 30 06:28:56 PM PDT 24
Finished Jul 30 06:28:59 PM PDT 24
Peak memory 207024 kb
Host smart-91ddfc9b-7829-4649-8cb0-2b4103c8988d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31527
43738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3152743738
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.610313146
Short name T1251
Test name
Test status
Simulation time 170697814 ps
CPU time 0.94 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:28:59 PM PDT 24
Peak memory 206952 kb
Host smart-4206f617-f655-4bfb-ab92-52e81cd6f0bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=610313146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.610313146
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.2522023075
Short name T2852
Test name
Test status
Simulation time 133930177 ps
CPU time 0.86 seconds
Started Jul 30 06:29:09 PM PDT 24
Finished Jul 30 06:29:10 PM PDT 24
Peak memory 206884 kb
Host smart-25cc9e02-5ab6-462c-8cc8-4d86528a92f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25220
23075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2522023075
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2027635620
Short name T1993
Test name
Test status
Simulation time 191809805 ps
CPU time 0.94 seconds
Started Jul 30 06:28:56 PM PDT 24
Finished Jul 30 06:28:57 PM PDT 24
Peak memory 206924 kb
Host smart-9d283965-2090-4c1a-8fa4-71f20232b4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20276
35620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2027635620
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.3570150775
Short name T2646
Test name
Test status
Simulation time 4550788090 ps
CPU time 129.24 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:31:07 PM PDT 24
Peak memory 216748 kb
Host smart-d33bcd2b-3e08-4029-b310-7fae7db0dba4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3570150775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.3570150775
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.1478959247
Short name T2652
Test name
Test status
Simulation time 12684287983 ps
CPU time 154.94 seconds
Started Jul 30 06:29:05 PM PDT 24
Finished Jul 30 06:31:40 PM PDT 24
Peak memory 207092 kb
Host smart-3ffb7fd0-5752-4511-ac07-336ba71c1b2e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1478959247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.1478959247
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3461134617
Short name T1597
Test name
Test status
Simulation time 221657628 ps
CPU time 0.95 seconds
Started Jul 30 06:29:10 PM PDT 24
Finished Jul 30 06:29:11 PM PDT 24
Peak memory 206980 kb
Host smart-a58876f3-d70e-450d-9876-7831b41278bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34611
34617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3461134617
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.3412859261
Short name T1795
Test name
Test status
Simulation time 23344691338 ps
CPU time 27.12 seconds
Started Jul 30 06:28:59 PM PDT 24
Finished Jul 30 06:29:27 PM PDT 24
Peak memory 207096 kb
Host smart-ae8e65e7-fcf0-45c6-bf35-d8403ba44ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34128
59261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3412859261
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1665118404
Short name T1848
Test name
Test status
Simulation time 3313702028 ps
CPU time 5.92 seconds
Started Jul 30 06:29:06 PM PDT 24
Finished Jul 30 06:29:12 PM PDT 24
Peak memory 207028 kb
Host smart-428342a9-f76a-4317-a0f4-b84fe302162c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16651
18404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1665118404
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3039454404
Short name T1637
Test name
Test status
Simulation time 4568201145 ps
CPU time 130.64 seconds
Started Jul 30 06:29:04 PM PDT 24
Finished Jul 30 06:31:15 PM PDT 24
Peak memory 215304 kb
Host smart-0bb2b2af-62c9-4797-b1c0-3560b50a2c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30394
54404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3039454404
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.676034933
Short name T2056
Test name
Test status
Simulation time 4212937943 ps
CPU time 123.6 seconds
Started Jul 30 06:29:03 PM PDT 24
Finished Jul 30 06:31:07 PM PDT 24
Peak memory 215372 kb
Host smart-a753f255-77fc-42df-a170-fcf7af6a55df
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=676034933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.676034933
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1188779797
Short name T1648
Test name
Test status
Simulation time 233760206 ps
CPU time 0.99 seconds
Started Jul 30 06:29:00 PM PDT 24
Finished Jul 30 06:29:01 PM PDT 24
Peak memory 206936 kb
Host smart-e75f15c4-bab6-498a-b575-0732cd8f425d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1188779797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1188779797
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1660613116
Short name T2203
Test name
Test status
Simulation time 198877851 ps
CPU time 0.98 seconds
Started Jul 30 06:29:03 PM PDT 24
Finished Jul 30 06:29:04 PM PDT 24
Peak memory 206916 kb
Host smart-64efaef9-6281-4e2e-b319-4ca3d9393f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16606
13116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1660613116
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.3425036071
Short name T2510
Test name
Test status
Simulation time 3955211434 ps
CPU time 42.46 seconds
Started Jul 30 06:29:04 PM PDT 24
Finished Jul 30 06:29:46 PM PDT 24
Peak memory 215304 kb
Host smart-7781f559-f03f-4b63-83f7-b9ba4615ccfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34250
36071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.3425036071
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2733489533
Short name T1673
Test name
Test status
Simulation time 7905240972 ps
CPU time 57.52 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:29:56 PM PDT 24
Peak memory 207136 kb
Host smart-a406cdd9-bd60-48a2-a31b-3e2fb55501e0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2733489533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2733489533
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3960194785
Short name T1776
Test name
Test status
Simulation time 211078148 ps
CPU time 0.97 seconds
Started Jul 30 06:29:03 PM PDT 24
Finished Jul 30 06:29:04 PM PDT 24
Peak memory 206960 kb
Host smart-d7e404d0-4332-4af1-8b69-9d23b271cc22
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3960194785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3960194785
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2690946411
Short name T854
Test name
Test status
Simulation time 174195398 ps
CPU time 0.87 seconds
Started Jul 30 06:29:01 PM PDT 24
Finished Jul 30 06:29:02 PM PDT 24
Peak memory 206972 kb
Host smart-891bc926-697c-4397-9ec8-257014a6be8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26909
46411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2690946411
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2603678566
Short name T128
Test name
Test status
Simulation time 182901341 ps
CPU time 0.96 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:29:00 PM PDT 24
Peak memory 206900 kb
Host smart-15455fc6-2d47-4690-b13c-197b770691ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26036
78566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2603678566
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.2336250811
Short name T2137
Test name
Test status
Simulation time 162903760 ps
CPU time 0.91 seconds
Started Jul 30 06:29:02 PM PDT 24
Finished Jul 30 06:29:03 PM PDT 24
Peak memory 206908 kb
Host smart-0dc75bba-e858-413b-9240-99540301dfc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23362
50811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.2336250811
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3510513839
Short name T1471
Test name
Test status
Simulation time 164853726 ps
CPU time 0.84 seconds
Started Jul 30 06:29:03 PM PDT 24
Finished Jul 30 06:29:04 PM PDT 24
Peak memory 206980 kb
Host smart-0212044c-121c-4440-8576-7d023089b2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35105
13839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3510513839
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3278023388
Short name T110
Test name
Test status
Simulation time 181713558 ps
CPU time 0.86 seconds
Started Jul 30 06:29:00 PM PDT 24
Finished Jul 30 06:29:01 PM PDT 24
Peak memory 206912 kb
Host smart-b6cf7f2f-6ad2-4250-8e31-d97c0a236a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32780
23388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3278023388
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1990671937
Short name T1404
Test name
Test status
Simulation time 187138318 ps
CPU time 0.9 seconds
Started Jul 30 06:29:00 PM PDT 24
Finished Jul 30 06:29:01 PM PDT 24
Peak memory 206912 kb
Host smart-4a39ba73-82ef-4c3e-aaaf-b1dc89e9dc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19906
71937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1990671937
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.1842418819
Short name T1057
Test name
Test status
Simulation time 253031720 ps
CPU time 1.08 seconds
Started Jul 30 06:28:57 PM PDT 24
Finished Jul 30 06:28:58 PM PDT 24
Peak memory 206912 kb
Host smart-1e1ec91f-6a94-48d8-8c8e-24bd512c2d3b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1842418819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.1842418819
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3062922287
Short name T2005
Test name
Test status
Simulation time 145385171 ps
CPU time 0.86 seconds
Started Jul 30 06:28:55 PM PDT 24
Finished Jul 30 06:28:56 PM PDT 24
Peak memory 206880 kb
Host smart-e2463ed0-3d2b-4447-8f84-b460b5633c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30629
22287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3062922287
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2511314240
Short name T817
Test name
Test status
Simulation time 31018461 ps
CPU time 0.66 seconds
Started Jul 30 06:28:59 PM PDT 24
Finished Jul 30 06:29:00 PM PDT 24
Peak memory 206884 kb
Host smart-1a18b9dc-db81-4026-8da7-8276fe196c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25113
14240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2511314240
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.4142508767
Short name T1757
Test name
Test status
Simulation time 11077956916 ps
CPU time 27.4 seconds
Started Jul 30 06:28:59 PM PDT 24
Finished Jul 30 06:29:26 PM PDT 24
Peak memory 219416 kb
Host smart-6c55d3c3-4bbd-46b8-abb3-20961a9a58cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41425
08767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.4142508767
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2649324039
Short name T1381
Test name
Test status
Simulation time 233666553 ps
CPU time 0.96 seconds
Started Jul 30 06:28:58 PM PDT 24
Finished Jul 30 06:28:59 PM PDT 24
Peak memory 206900 kb
Host smart-de5c950d-0042-41ce-90e0-6be4c84be1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26493
24039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2649324039
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.982087638
Short name T2680
Test name
Test status
Simulation time 206542861 ps
CPU time 0.86 seconds
Started Jul 30 06:28:57 PM PDT 24
Finished Jul 30 06:28:58 PM PDT 24
Peak memory 206892 kb
Host smart-32212ea1-5086-45a9-9c0e-8da7ad9dd785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98208
7638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.982087638
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.989985572
Short name T1720
Test name
Test status
Simulation time 8451251940 ps
CPU time 232.92 seconds
Started Jul 30 06:29:02 PM PDT 24
Finished Jul 30 06:32:55 PM PDT 24
Peak memory 215404 kb
Host smart-30364ac5-68fa-4f10-90a4-a67b2c455cfb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=989985572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.989985572
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3269806683
Short name T157
Test name
Test status
Simulation time 11247643516 ps
CPU time 330.81 seconds
Started Jul 30 06:29:01 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 215328 kb
Host smart-03bd25dc-9932-43f6-a9f3-945cb00edc57
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3269806683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3269806683
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.588363701
Short name T950
Test name
Test status
Simulation time 16811839765 ps
CPU time 128.93 seconds
Started Jul 30 06:29:03 PM PDT 24
Finished Jul 30 06:31:12 PM PDT 24
Peak memory 223472 kb
Host smart-9d593d78-1d5f-4667-9502-81fe68374909
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=588363701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.588363701
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1800439275
Short name T1657
Test name
Test status
Simulation time 195482451 ps
CPU time 0.93 seconds
Started Jul 30 06:29:10 PM PDT 24
Finished Jul 30 06:29:11 PM PDT 24
Peak memory 206944 kb
Host smart-b3df3319-194e-4f44-88c3-0377a9dd39cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18004
39275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1800439275
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.3137381442
Short name T2571
Test name
Test status
Simulation time 207077069 ps
CPU time 0.94 seconds
Started Jul 30 06:28:59 PM PDT 24
Finished Jul 30 06:29:00 PM PDT 24
Peak memory 206952 kb
Host smart-5d5b1553-495d-4604-8ea5-cd8c90bd68e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31373
81442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.3137381442
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3231772738
Short name T72
Test name
Test status
Simulation time 139190771 ps
CPU time 0.79 seconds
Started Jul 30 06:29:01 PM PDT 24
Finished Jul 30 06:29:02 PM PDT 24
Peak memory 206876 kb
Host smart-4ae15e0e-c273-4e82-8612-3c786d4cd482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32317
72738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3231772738
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.1448640056
Short name T1306
Test name
Test status
Simulation time 159806627 ps
CPU time 0.84 seconds
Started Jul 30 06:29:01 PM PDT 24
Finished Jul 30 06:29:02 PM PDT 24
Peak memory 206880 kb
Host smart-51a38fdc-7eda-4e95-98fe-312ab6d6d65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14486
40056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1448640056
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1507676830
Short name T797
Test name
Test status
Simulation time 163040144 ps
CPU time 0.88 seconds
Started Jul 30 06:29:02 PM PDT 24
Finished Jul 30 06:29:03 PM PDT 24
Peak memory 206920 kb
Host smart-e32bccc7-7e53-48e8-ad20-51debe15bb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15076
76830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1507676830
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1167056778
Short name T866
Test name
Test status
Simulation time 183991471 ps
CPU time 0.92 seconds
Started Jul 30 06:29:02 PM PDT 24
Finished Jul 30 06:29:03 PM PDT 24
Peak memory 206912 kb
Host smart-85236335-c5c3-441d-a016-a11e4977ce72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670
56778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1167056778
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1973652567
Short name T2314
Test name
Test status
Simulation time 5164286734 ps
CPU time 40.3 seconds
Started Jul 30 06:29:02 PM PDT 24
Finished Jul 30 06:29:43 PM PDT 24
Peak memory 216496 kb
Host smart-20620e16-16b8-428e-b85b-dbf49178b6c3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1973652567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1973652567
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.81736224
Short name T2006
Test name
Test status
Simulation time 201243957 ps
CPU time 0.9 seconds
Started Jul 30 06:29:01 PM PDT 24
Finished Jul 30 06:29:02 PM PDT 24
Peak memory 206908 kb
Host smart-aa5e89c2-2817-4d0c-a303-c9fc7f22e8cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81736
224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.81736224
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2811835305
Short name T111
Test name
Test status
Simulation time 209867179 ps
CPU time 0.99 seconds
Started Jul 30 06:29:00 PM PDT 24
Finished Jul 30 06:29:02 PM PDT 24
Peak memory 206956 kb
Host smart-12e61fde-8fd8-4c28-9c83-4f51f5d54a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28118
35305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2811835305
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2568131038
Short name T2700
Test name
Test status
Simulation time 1321940749 ps
CPU time 3.14 seconds
Started Jul 30 06:29:02 PM PDT 24
Finished Jul 30 06:29:05 PM PDT 24
Peak memory 207048 kb
Host smart-ba79781a-5d01-49c9-9388-dffe88b31376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25681
31038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2568131038
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3985111072
Short name T1824
Test name
Test status
Simulation time 5695581592 ps
CPU time 41.78 seconds
Started Jul 30 06:29:01 PM PDT 24
Finished Jul 30 06:29:43 PM PDT 24
Peak memory 207136 kb
Host smart-6584fcb8-8897-47b3-8169-f29bdaa1a609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39851
11072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3985111072
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.529744226
Short name T1785
Test name
Test status
Simulation time 588239470 ps
CPU time 12.1 seconds
Started Jul 30 06:29:01 PM PDT 24
Finished Jul 30 06:29:13 PM PDT 24
Peak memory 207044 kb
Host smart-b97c05b0-e578-44b7-a0c6-116d70b28e04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529744226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host_
handshake.529744226
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.3992491620
Short name T2524
Test name
Test status
Simulation time 35357264 ps
CPU time 0.65 seconds
Started Jul 30 06:29:20 PM PDT 24
Finished Jul 30 06:29:20 PM PDT 24
Peak memory 207056 kb
Host smart-cf08379a-2a4e-4d2f-9b19-1e446b68e700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3992491620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.3992491620
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2598338753
Short name T2666
Test name
Test status
Simulation time 3605528119 ps
CPU time 5.12 seconds
Started Jul 30 06:29:04 PM PDT 24
Finished Jul 30 06:29:09 PM PDT 24
Peak memory 207044 kb
Host smart-e72be734-0f59-4e82-ad88-18b395ad8ba2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598338753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.2598338753
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.655923753
Short name T1044
Test name
Test status
Simulation time 13366988601 ps
CPU time 15.45 seconds
Started Jul 30 06:29:06 PM PDT 24
Finished Jul 30 06:29:21 PM PDT 24
Peak memory 207136 kb
Host smart-d9511130-0fb8-4fbd-9770-095c673e69da
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=655923753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.655923753
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.940187815
Short name T1182
Test name
Test status
Simulation time 23376167296 ps
CPU time 26.51 seconds
Started Jul 30 06:29:07 PM PDT 24
Finished Jul 30 06:29:33 PM PDT 24
Peak memory 207108 kb
Host smart-bff99251-21e7-4fc6-b4c8-9895bafe5202
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940187815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon
_wake_resume.940187815
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2904797006
Short name T2304
Test name
Test status
Simulation time 182837799 ps
CPU time 0.91 seconds
Started Jul 30 06:29:12 PM PDT 24
Finished Jul 30 06:29:13 PM PDT 24
Peak memory 206924 kb
Host smart-1eaffe5a-0fd6-444e-a08f-2fa4a6a77cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29047
97006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2904797006
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.4187844059
Short name T2816
Test name
Test status
Simulation time 150932255 ps
CPU time 0.82 seconds
Started Jul 30 06:29:05 PM PDT 24
Finished Jul 30 06:29:06 PM PDT 24
Peak memory 206928 kb
Host smart-c01d813e-47cc-40fb-b55b-0d2b07c8c434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41878
44059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.4187844059
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.1625491441
Short name T1239
Test name
Test status
Simulation time 299424961 ps
CPU time 1.19 seconds
Started Jul 30 06:29:06 PM PDT 24
Finished Jul 30 06:29:07 PM PDT 24
Peak memory 206968 kb
Host smart-54d9d4ef-0413-41eb-b131-de85718b44dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16254
91441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.1625491441
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1569502142
Short name T1040
Test name
Test status
Simulation time 926780499 ps
CPU time 2.51 seconds
Started Jul 30 06:29:11 PM PDT 24
Finished Jul 30 06:29:14 PM PDT 24
Peak memory 207120 kb
Host smart-ec631f74-854a-4c79-8903-a2fbf27f97ce
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1569502142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1569502142
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.63992266
Short name T2597
Test name
Test status
Simulation time 21012343204 ps
CPU time 46.43 seconds
Started Jul 30 06:29:08 PM PDT 24
Finished Jul 30 06:29:55 PM PDT 24
Peak memory 207148 kb
Host smart-34b034e8-352f-46b0-9261-046288ecf202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63992
266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.63992266
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.3644067848
Short name T1480
Test name
Test status
Simulation time 783352465 ps
CPU time 15.86 seconds
Started Jul 30 06:29:08 PM PDT 24
Finished Jul 30 06:29:24 PM PDT 24
Peak memory 207040 kb
Host smart-3f0a6da9-e325-46cf-9440-ac77b1e02393
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644067848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.3644067848
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.138392385
Short name T1605
Test name
Test status
Simulation time 437595145 ps
CPU time 1.42 seconds
Started Jul 30 06:29:06 PM PDT 24
Finished Jul 30 06:29:07 PM PDT 24
Peak memory 206868 kb
Host smart-0b2dc660-b369-4e21-af80-511ac13eac3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13839
2385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.138392385
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.670156390
Short name T40
Test name
Test status
Simulation time 139347681 ps
CPU time 0.81 seconds
Started Jul 30 06:29:10 PM PDT 24
Finished Jul 30 06:29:11 PM PDT 24
Peak memory 206920 kb
Host smart-bec8839e-c17f-4377-8fb4-0d175549c8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67015
6390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.670156390
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1582222678
Short name T1897
Test name
Test status
Simulation time 35445588 ps
CPU time 0.7 seconds
Started Jul 30 06:29:10 PM PDT 24
Finished Jul 30 06:29:11 PM PDT 24
Peak memory 206868 kb
Host smart-13eea7c0-5b9e-4147-9428-9f4152165d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15822
22678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1582222678
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.812238662
Short name T1080
Test name
Test status
Simulation time 909760565 ps
CPU time 2.52 seconds
Started Jul 30 06:29:13 PM PDT 24
Finished Jul 30 06:29:16 PM PDT 24
Peak memory 207004 kb
Host smart-c4ca5529-4cbb-48b2-9dea-0faf27912500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81223
8662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.812238662
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.271174466
Short name T825
Test name
Test status
Simulation time 262198276 ps
CPU time 1.72 seconds
Started Jul 30 06:29:11 PM PDT 24
Finished Jul 30 06:29:13 PM PDT 24
Peak memory 207032 kb
Host smart-b529fe97-d0d3-4227-9dcb-36a98f4383da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27117
4466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.271174466
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1781953729
Short name T2269
Test name
Test status
Simulation time 217931710 ps
CPU time 0.95 seconds
Started Jul 30 06:29:13 PM PDT 24
Finished Jul 30 06:29:15 PM PDT 24
Peak memory 206916 kb
Host smart-450179ea-7acb-45e7-8b35-d6f3026257e1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1781953729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1781953729
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.661196726
Short name T393
Test name
Test status
Simulation time 156726532 ps
CPU time 0.85 seconds
Started Jul 30 06:29:10 PM PDT 24
Finished Jul 30 06:29:11 PM PDT 24
Peak memory 206876 kb
Host smart-871f57c7-3947-4601-afea-abe0e81b400b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66119
6726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.661196726
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2562789611
Short name T998
Test name
Test status
Simulation time 235744640 ps
CPU time 1.01 seconds
Started Jul 30 06:29:10 PM PDT 24
Finished Jul 30 06:29:11 PM PDT 24
Peak memory 206920 kb
Host smart-4e1f58aa-434f-4761-8cde-5b590f5b66ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25627
89611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2562789611
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.2926779624
Short name T2126
Test name
Test status
Simulation time 8262830486 ps
CPU time 242.14 seconds
Started Jul 30 06:29:11 PM PDT 24
Finished Jul 30 06:33:13 PM PDT 24
Peak memory 215308 kb
Host smart-03bf8576-9c6a-4c42-b409-942c049e0af3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2926779624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.2926779624
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.1390480784
Short name T1439
Test name
Test status
Simulation time 8373419627 ps
CPU time 105.52 seconds
Started Jul 30 06:29:10 PM PDT 24
Finished Jul 30 06:30:56 PM PDT 24
Peak memory 207116 kb
Host smart-eb2d9842-3b54-42a5-bb2f-a1b2d01668ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1390480784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.1390480784
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1605982192
Short name T1584
Test name
Test status
Simulation time 220407403 ps
CPU time 0.98 seconds
Started Jul 30 06:29:13 PM PDT 24
Finished Jul 30 06:29:14 PM PDT 24
Peak memory 206908 kb
Host smart-1129835e-1e7f-4245-a081-2049d4d00779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16059
82192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1605982192
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.1866617431
Short name T2746
Test name
Test status
Simulation time 23300179460 ps
CPU time 33.63 seconds
Started Jul 30 06:29:14 PM PDT 24
Finished Jul 30 06:29:47 PM PDT 24
Peak memory 207096 kb
Host smart-2999b09b-e5d8-4109-a7aa-1878ad78ee04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18666
17431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.1866617431
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3390892733
Short name T2740
Test name
Test status
Simulation time 3311846111 ps
CPU time 5.61 seconds
Started Jul 30 06:29:12 PM PDT 24
Finished Jul 30 06:29:18 PM PDT 24
Peak memory 207072 kb
Host smart-742d9223-71e1-4af6-b0aa-84f3e82ff7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33908
92733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3390892733
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.2320646826
Short name T2199
Test name
Test status
Simulation time 6574265859 ps
CPU time 51.42 seconds
Started Jul 30 06:29:12 PM PDT 24
Finished Jul 30 06:30:04 PM PDT 24
Peak memory 217184 kb
Host smart-0c41a237-646f-48b8-9498-e7ed86539345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23206
46826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.2320646826
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.1989143201
Short name T850
Test name
Test status
Simulation time 5014236173 ps
CPU time 144 seconds
Started Jul 30 06:29:13 PM PDT 24
Finished Jul 30 06:31:37 PM PDT 24
Peak memory 215332 kb
Host smart-6a841dae-33a9-440d-9e04-bb72d0dd6551
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1989143201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.1989143201
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3611303085
Short name T1453
Test name
Test status
Simulation time 246143187 ps
CPU time 1.04 seconds
Started Jul 30 06:29:13 PM PDT 24
Finished Jul 30 06:29:14 PM PDT 24
Peak memory 206920 kb
Host smart-25391003-ae77-4d5f-8e08-c166a559328e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3611303085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3611303085
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3947094537
Short name T1203
Test name
Test status
Simulation time 197404462 ps
CPU time 0.91 seconds
Started Jul 30 06:29:17 PM PDT 24
Finished Jul 30 06:29:18 PM PDT 24
Peak memory 206960 kb
Host smart-8aeca728-b06a-4364-9044-0feb12f8b877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39470
94537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3947094537
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.769523304
Short name T418
Test name
Test status
Simulation time 4198900322 ps
CPU time 33.74 seconds
Started Jul 30 06:29:13 PM PDT 24
Finished Jul 30 06:29:46 PM PDT 24
Peak memory 216944 kb
Host smart-f28f699c-5681-4d8b-b972-d7225d2980ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76952
3304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.769523304
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3768995278
Short name T1606
Test name
Test status
Simulation time 4522863658 ps
CPU time 33.65 seconds
Started Jul 30 06:29:14 PM PDT 24
Finished Jul 30 06:29:47 PM PDT 24
Peak memory 216820 kb
Host smart-c136a0a3-7956-41c1-bfc3-abe57a64e946
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3768995278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3768995278
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3078633729
Short name T527
Test name
Test status
Simulation time 151030262 ps
CPU time 0.94 seconds
Started Jul 30 06:29:16 PM PDT 24
Finished Jul 30 06:29:17 PM PDT 24
Peak memory 206936 kb
Host smart-21a62e02-5265-4cfc-a38c-dda946d92943
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3078633729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3078633729
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.4205482830
Short name T99
Test name
Test status
Simulation time 168912386 ps
CPU time 0.91 seconds
Started Jul 30 06:29:18 PM PDT 24
Finished Jul 30 06:29:19 PM PDT 24
Peak memory 206948 kb
Host smart-825fd546-505e-4dfd-ba7e-27f5f7244441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42054
82830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.4205482830
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1889820925
Short name T145
Test name
Test status
Simulation time 204628442 ps
CPU time 0.94 seconds
Started Jul 30 06:29:22 PM PDT 24
Finished Jul 30 06:29:23 PM PDT 24
Peak memory 206952 kb
Host smart-1ae54ef9-5a12-4694-b2ef-78f8411f0b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18898
20925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1889820925
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.1710167626
Short name T1115
Test name
Test status
Simulation time 184971679 ps
CPU time 0.95 seconds
Started Jul 30 06:29:24 PM PDT 24
Finished Jul 30 06:29:26 PM PDT 24
Peak memory 206908 kb
Host smart-770f2fa4-b9b2-4123-ba98-eaf77bf8edb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17101
67626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.1710167626
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.475194209
Short name T1755
Test name
Test status
Simulation time 202443123 ps
CPU time 0.92 seconds
Started Jul 30 06:29:20 PM PDT 24
Finished Jul 30 06:29:21 PM PDT 24
Peak memory 206984 kb
Host smart-22b76a82-3b4d-4d1c-9587-86c0f59964c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47519
4209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.475194209
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.59129753
Short name T1006
Test name
Test status
Simulation time 186429511 ps
CPU time 0.86 seconds
Started Jul 30 06:29:16 PM PDT 24
Finished Jul 30 06:29:17 PM PDT 24
Peak memory 206900 kb
Host smart-05c669e6-a1a5-468c-914c-88318bb9c25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59129
753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.59129753
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3586867799
Short name T2859
Test name
Test status
Simulation time 143307817 ps
CPU time 0.84 seconds
Started Jul 30 06:29:17 PM PDT 24
Finished Jul 30 06:29:19 PM PDT 24
Peak memory 206968 kb
Host smart-50ddc344-e726-49e3-b11a-31fced75fcea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35868
67799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3586867799
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.325927082
Short name T1575
Test name
Test status
Simulation time 199558798 ps
CPU time 0.99 seconds
Started Jul 30 06:29:25 PM PDT 24
Finished Jul 30 06:29:26 PM PDT 24
Peak memory 206904 kb
Host smart-36abe1d8-dc58-4247-9cc5-d254e2061b23
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=325927082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.325927082
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1713380114
Short name T1556
Test name
Test status
Simulation time 146232894 ps
CPU time 0.84 seconds
Started Jul 30 06:29:18 PM PDT 24
Finished Jul 30 06:29:19 PM PDT 24
Peak memory 206912 kb
Host smart-99ec7f35-9bf3-42d6-81d5-38374cc4b39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17133
80114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1713380114
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.684045752
Short name T2338
Test name
Test status
Simulation time 39798693 ps
CPU time 0.71 seconds
Started Jul 30 06:29:19 PM PDT 24
Finished Jul 30 06:29:20 PM PDT 24
Peak memory 206872 kb
Host smart-17d3530f-75eb-4be5-97a6-ca6d5cebb13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68404
5752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.684045752
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2012424233
Short name T257
Test name
Test status
Simulation time 7088956797 ps
CPU time 18.53 seconds
Started Jul 30 06:29:20 PM PDT 24
Finished Jul 30 06:29:39 PM PDT 24
Peak memory 215368 kb
Host smart-5e1acf25-da94-4dae-8a5d-3b0a869c5c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20124
24233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2012424233
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.856650121
Short name T2801
Test name
Test status
Simulation time 176946517 ps
CPU time 0.88 seconds
Started Jul 30 06:29:19 PM PDT 24
Finished Jul 30 06:29:20 PM PDT 24
Peak memory 206924 kb
Host smart-13ea8a14-4c27-49de-8e92-27748934671c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85665
0121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.856650121
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.113322103
Short name T384
Test name
Test status
Simulation time 228696129 ps
CPU time 1.08 seconds
Started Jul 30 06:29:19 PM PDT 24
Finished Jul 30 06:29:20 PM PDT 24
Peak memory 206940 kb
Host smart-b1172586-964f-4d96-af3e-a73b03996329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11332
2103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.113322103
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.3028434982
Short name T158
Test name
Test status
Simulation time 5378004465 ps
CPU time 145.51 seconds
Started Jul 30 06:29:20 PM PDT 24
Finished Jul 30 06:31:45 PM PDT 24
Peak memory 215348 kb
Host smart-c2cb3885-1abe-4984-afb8-589cf00c9190
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028434982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.3028434982
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3219538294
Short name T2858
Test name
Test status
Simulation time 12928227860 ps
CPU time 290.9 seconds
Started Jul 30 06:29:18 PM PDT 24
Finished Jul 30 06:34:09 PM PDT 24
Peak memory 215332 kb
Host smart-49fc9c52-e8e5-4a7b-a277-e6168fc8c94a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3219538294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3219538294
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.1246934485
Short name T1464
Test name
Test status
Simulation time 16154215420 ps
CPU time 93.76 seconds
Started Jul 30 06:29:23 PM PDT 24
Finished Jul 30 06:30:57 PM PDT 24
Peak memory 223512 kb
Host smart-4adb56a0-0cce-40d6-b3c0-6fd7a2018a97
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246934485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1246934485
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.200168468
Short name T602
Test name
Test status
Simulation time 187368788 ps
CPU time 0.92 seconds
Started Jul 30 06:29:22 PM PDT 24
Finished Jul 30 06:29:23 PM PDT 24
Peak memory 206928 kb
Host smart-4d6e527f-e2b2-4581-9e1c-5ed73388f1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20016
8468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.200168468
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.1993610941
Short name T648
Test name
Test status
Simulation time 185774276 ps
CPU time 0.92 seconds
Started Jul 30 06:29:20 PM PDT 24
Finished Jul 30 06:29:21 PM PDT 24
Peak memory 206972 kb
Host smart-932aa814-0edb-4c81-8ee0-ff97948b92a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19936
10941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1993610941
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.4067592031
Short name T2596
Test name
Test status
Simulation time 201971524 ps
CPU time 0.88 seconds
Started Jul 30 06:29:23 PM PDT 24
Finished Jul 30 06:29:25 PM PDT 24
Peak memory 206924 kb
Host smart-efaee3ec-4325-4e55-b111-82b5aca91535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40675
92031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.4067592031
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1881106583
Short name T989
Test name
Test status
Simulation time 170570621 ps
CPU time 0.83 seconds
Started Jul 30 06:29:22 PM PDT 24
Finished Jul 30 06:29:22 PM PDT 24
Peak memory 206880 kb
Host smart-43efff16-e135-41e2-83ae-59105892eee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18811
06583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1881106583
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.56697668
Short name T1451
Test name
Test status
Simulation time 187017770 ps
CPU time 0.86 seconds
Started Jul 30 06:29:24 PM PDT 24
Finished Jul 30 06:29:25 PM PDT 24
Peak memory 206900 kb
Host smart-298e534b-4d3d-4b68-9d2a-4ef8e184fd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56697
668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.56697668
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.259940403
Short name T837
Test name
Test status
Simulation time 256943455 ps
CPU time 1.01 seconds
Started Jul 30 06:29:23 PM PDT 24
Finished Jul 30 06:29:25 PM PDT 24
Peak memory 206968 kb
Host smart-26a1cbfb-086a-43ca-ae54-9fd47c7d9461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25994
0403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.259940403
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.2800752394
Short name T2372
Test name
Test status
Simulation time 5211079683 ps
CPU time 50.61 seconds
Started Jul 30 06:29:22 PM PDT 24
Finished Jul 30 06:30:13 PM PDT 24
Peak memory 216872 kb
Host smart-d3991a9e-cd02-40df-aef4-61e66e35eb91
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2800752394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.2800752394
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.708187875
Short name T1015
Test name
Test status
Simulation time 193690080 ps
CPU time 0.86 seconds
Started Jul 30 06:29:23 PM PDT 24
Finished Jul 30 06:29:24 PM PDT 24
Peak memory 206876 kb
Host smart-9e788e0b-6e34-458b-a414-216eae5110f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70818
7875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.708187875
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1510256526
Short name T1275
Test name
Test status
Simulation time 203642327 ps
CPU time 0.87 seconds
Started Jul 30 06:29:20 PM PDT 24
Finished Jul 30 06:29:21 PM PDT 24
Peak memory 206912 kb
Host smart-2dd777a7-56c6-4661-8f58-ea67069f13b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15102
56526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1510256526
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.987513744
Short name T1012
Test name
Test status
Simulation time 813412061 ps
CPU time 2.39 seconds
Started Jul 30 06:29:22 PM PDT 24
Finished Jul 30 06:29:25 PM PDT 24
Peak memory 206884 kb
Host smart-aea372f8-57d1-4f38-8182-157dab386527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98751
3744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.987513744
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1478285711
Short name T1342
Test name
Test status
Simulation time 6450864193 ps
CPU time 50.91 seconds
Started Jul 30 06:29:23 PM PDT 24
Finished Jul 30 06:30:15 PM PDT 24
Peak memory 207212 kb
Host smart-69bd035f-79c6-4093-9a84-96fab2a1a484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14782
85711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1478285711
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.1380831267
Short name T2313
Test name
Test status
Simulation time 885697630 ps
CPU time 5.47 seconds
Started Jul 30 06:29:10 PM PDT 24
Finished Jul 30 06:29:16 PM PDT 24
Peak memory 207052 kb
Host smart-8e7db077-c0c5-4f39-88d1-825093ef89f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380831267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host
_handshake.1380831267
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest
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