Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	86882	1		T1	3		T2	5		T3	3
all_values[1]	86882	1		T1	3		T2	5		T3	3
all_values[2]	86882	1		T1	3		T2	5		T3	3
all_values[3]	86882	1		T1	3		T2	5		T3	3
all_values[4]	86882	1		T1	3		T2	5		T3	3
all_values[5]	86882	1		T1	3		T2	5		T3	3
all_values[6]	86882	1		T1	3		T2	5		T3	3
all_values[7]	86882	1		T1	3		T2	5		T3	3
all_values[8]	86882	1		T1	3		T2	5		T3	3
all_values[9]	86882	1		T1	3		T2	5		T3	3
all_values[10]	86882	1		T1	3		T2	5		T3	3
all_values[11]	86882	1		T1	3		T2	5		T3	3
all_values[12]	86882	1		T1	3		T2	5		T3	3
all_values[13]	86882	1		T1	3		T2	5		T3	3
all_values[14]	86882	1		T1	3		T2	5		T3	3
all_values[15]	86882	1		T1	3		T2	5		T3	3
all_values[16]	86882	1		T1	3		T2	5		T3	3
all_values[17]	86882	1		T1	3		T2	5		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2773238	1		T1	94		T2	158		T3	96
auto[1]	6986	1		T1	2		T2	2		T29	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2321304	1		T1	85		T2	131		T3	85
auto[1]	458920	1		T1	11		T2	29		T3	11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	62052	1		T1	3		T2	5		T3	2
all_values[0]	auto[0]	auto[1]	23988	1		T3	1		T21	2		T27	3
all_values[0]	auto[1]	auto[0]	728	1		T26	3		T45	3		T46	3
all_values[0]	auto[1]	auto[1]	114	1		T26	1		T45	1		T46	1
all_values[1]	auto[0]	auto[0]	83592	1		T1	3		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	1606	1		T4	2		T5	2		T6	2
all_values[1]	auto[1]	auto[0]	674	1		T2	1		T7	1		T22	2
all_values[1]	auto[1]	auto[1]	1010	1		T2	1		T7	1		T22	1
all_values[2]	auto[0]	auto[0]	2948	1		T1	1		T2	1		T3	3
all_values[2]	auto[0]	auto[1]	83664	1		T1	2		T2	4		T29	2
all_values[2]	auto[1]	auto[0]	142	1		T19	1		T36	1		T38	1
all_values[2]	auto[1]	auto[1]	128	1		T19	1		T36	1		T38	1
all_values[3]	auto[0]	auto[0]	84748	1		T1	3		T2	5		T3	3
all_values[3]	auto[0]	auto[1]	572	1		T4	1		T6	1		T20	1
all_values[3]	auto[1]	auto[0]	1498	1		T58	1407		T194	1		T195	4
all_values[3]	auto[1]	auto[1]	64	1		T58	1		T193	1		T196	1
all_values[4]	auto[0]	auto[0]	2939	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	83783	1		T1	2		T2	4		T3	2
all_values[4]	auto[1]	auto[0]	83	1		T59	1		T193	3		T196	3
all_values[4]	auto[1]	auto[1]	77	1		T59	1		T193	2		T194	2
all_values[5]	auto[0]	auto[0]	86349	1		T1	3		T2	4		T3	3
all_values[5]	auto[0]	auto[1]	350	1		T2	1		T7	1		T6	1
all_values[5]	auto[1]	auto[0]	108	1		T193	5		T196	5		T194	1
all_values[5]	auto[1]	auto[1]	75	1		T194	4		T195	3		T278	1
all_values[6]	auto[0]	auto[0]	86469	1		T1	3		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	272	1		T2	2		T7	1		T6	1
all_values[6]	auto[1]	auto[0]	88	1		T193	6		T194	2		T195	2
all_values[6]	auto[1]	auto[1]	53	1		T196	1		T194	2		T195	1
all_values[7]	auto[0]	auto[0]	34716	1		T1	3		T29	3		T23	2
all_values[7]	auto[0]	auto[1]	52013	1		T2	5		T3	3		T26	4
all_values[7]	auto[1]	auto[0]	93	1		T47	1		T48	1		T49	1
all_values[7]	auto[1]	auto[1]	60	1		T47	1		T48	1		T49	1
all_values[8]	auto[0]	auto[0]	86656	1		T1	3		T2	5		T3	3
all_values[8]	auto[0]	auto[1]	60	1		T193	2		T196	1		T195	3
all_values[8]	auto[1]	auto[0]	117	1		T44	10		T193	3		T196	1
all_values[8]	auto[1]	auto[1]	49	1		T193	1		T194	1		T195	1
all_values[9]	auto[0]	auto[0]	86621	1		T1	3		T2	5		T3	3
all_values[9]	auto[0]	auto[1]	61	1		T193	4		T196	1		T194	1
all_values[9]	auto[1]	auto[0]	119	1		T55	3		T56	3		T57	3
all_values[9]	auto[1]	auto[1]	81	1		T55	2		T56	2		T57	2
all_values[10]	auto[0]	auto[0]	86402	1		T1	3		T2	5		T3	3
all_values[10]	auto[0]	auto[1]	322	1		T52	1		T53	1		T54	2
all_values[10]	auto[1]	auto[0]	89	1		T193	4		T196	3		T194	2
all_values[10]	auto[1]	auto[1]	69	1		T193	2		T196	1		T194	2
all_values[11]	auto[0]	auto[0]	86461	1		T1	2		T2	5		T3	3
all_values[11]	auto[0]	auto[1]	138	1		T1	1		T65	1		T66	1
all_values[11]	auto[1]	auto[0]	151	1		T40	1		T67	1		T68	1
all_values[11]	auto[1]	auto[1]	132	1		T40	1		T67	1		T68	1
all_values[12]	auto[0]	auto[0]	86624	1		T1	3		T2	5		T3	3
all_values[12]	auto[0]	auto[1]	62	1		T69	1		T70	1		T73	1
all_values[12]	auto[1]	auto[0]	122	1		T29	2		T71	2		T72	2
all_values[12]	auto[1]	auto[1]	74	1		T29	1		T71	1		T72	1
all_values[13]	auto[0]	auto[0]	86522	1		T1	1		T2	5		T3	3
all_values[13]	auto[0]	auto[1]	79	1		T69	1		T70	1		T73	1
all_values[13]	auto[1]	auto[0]	148	1		T1	1		T65	1		T66	1
all_values[13]	auto[1]	auto[1]	133	1		T1	1		T65	1		T66	1
all_values[14]	auto[0]	auto[0]	14533	1		T1	3		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	72187	1		T2	3		T7	2		T4	1
all_values[14]	auto[1]	auto[0]	96	1		T193	2		T194	2		T278	5
all_values[14]	auto[1]	auto[1]	66	1		T193	5		T196	1		T194	2
all_values[15]	auto[0]	auto[0]	2983	1		T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	83720	1		T1	2		T2	4		T3	2
all_values[15]	auto[1]	auto[0]	102	1		T193	6		T196	1		T194	2
all_values[15]	auto[1]	auto[1]	77	1		T194	2		T297	2		T279	2
all_values[16]	auto[0]	auto[0]	86208	1		T1	3		T2	5		T3	3
all_values[16]	auto[0]	auto[1]	482	1		T18	1		T60	1		T61	1
all_values[16]	auto[1]	auto[0]	111	1		T62	4		T63	4		T64	4
all_values[16]	auto[1]	auto[1]	81	1		T62	4		T63	4		T64	4
all_values[17]	auto[0]	auto[0]	33552	1		T29	3		T23	2		T7	2
all_values[17]	auto[0]	auto[1]	53156	1		T1	3		T2	5		T3	3
all_values[17]	auto[1]	auto[0]	112	1		T50	1		T51	1		T193	2
all_values[17]	auto[1]	auto[1]	62	1		T50	1		T51	1		T193	2