Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	131778	1		T1	1		T2	1		T3	1
auto[1]	64089	1		T2	1		T7	1		T4	72

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	28830	1		T6	2		T20	5		T92	9
max_len_m1	1246	1		T4	2		T18	1		T5	2
max_len_m2	1262	1		T4	2		T5	6		T20	4
max_len_m3	1245	1		T4	4		T20	8		T213	2
five	1541	1		T4	4		T95	2		T10	2
four	1643	1		T5	2		T6	2		T20	1
three	1632	1		T5	4		T20	2		T95	3
one	1806	1		T4	2		T6	6		T20	5
zero	12858	1		T1	1		T5	8		T6	2

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23528	1		T6	1		T20	3		T92	9
max_len	auto[1]	5302	1		T6	1		T20	2		T37	133
max_len_m1	auto[0]	796	1		T4	1		T18	1		T5	1
max_len_m1	auto[1]	450	1		T4	1		T5	1		T6	1
max_len_m2	auto[0]	790	1		T4	1		T5	3		T20	3
max_len_m2	auto[1]	472	1		T4	1		T5	3		T20	1
max_len_m3	auto[0]	789	1		T4	2		T20	5		T213	1
max_len_m3	auto[1]	456	1		T4	2		T20	3		T213	1
five	auto[0]	814	1		T4	2		T95	2		T10	1
five	auto[1]	727	1		T4	2		T10	1		T213	4
four	auto[0]	845	1		T5	1		T6	1		T20	1
four	auto[1]	798	1		T5	1		T6	1		T95	3
three	auto[0]	836	1		T5	2		T20	1		T95	3
three	auto[1]	796	1		T5	2		T20	1		T213	2
one	auto[0]	873	1		T4	1		T6	3		T20	4
one	auto[1]	933	1		T4	1		T6	3		T20	1
zero	auto[0]	999	1		T1	1		T5	4		T6	1
zero	auto[1]	11859	1		T5	4		T6	1		T20	2