Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
56.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	96	48	48	50.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	2	2	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	48	48	50.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	89161	1		T2	1		T3	1		T26	1
auto[1]	58962	1		T2	1		T7	1		T4	72

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	14559	1		T3	1		T4	24		T6	38
endpoints[0x1]	13625	1		T4	24		T20	40		T60	1
endpoints[0x2]	10722	1		T6	38		T90	1		T137	2
endpoints[0x3]	9902	1		T74	24		T136	2		T85	1
endpoints[0x4]	13722	1		T4	24		T5	36		T20	40
endpoints[0x5]	11745	1		T2	2		T18	2		T27	2
endpoints[0x6]	13422	1		T7	2		T5	36		T6	38
endpoints[0x7]	11281	1		T5	36		T20	40		T21	1
endpoints[0x8]	11568	1		T4	24		T6	38		T20	40
endpoints[0x9]	12427	1		T26	1		T4	24		T6	38
endpoints[0xa]	13056	1		T4	24		T5	36		T20	40
endpoints[0xb]	12094	1		T5	36		T20	40		T74	29

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
nak	0	1	1
ack	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	69884	1		T4	72		T18	1		T5	79
data0	78215	1		T2	2		T3	1		T26	1

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	48	48	50.00	48

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER
[nak , ack]	*	*	--	--	48

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	auto[0]	endpoints[0x0]	4431	1		T4	6		T6	9		T74	6
data1	auto[0]	endpoints[0x1]	3725	1		T4	6		T20	10		T92	4
data1	auto[0]	endpoints[0x2]	2549	1		T6	6		T74	6		T95	17
data1	auto[0]	endpoints[0x3]	2113	1		T74	9		T138	10		T139	4
data1	auto[0]	endpoints[0x4]	3613	1		T4	6		T5	4		T20	10
data1	auto[0]	endpoints[0x5]	3037	1		T18	1		T74	13		T139	8
data1	auto[0]	endpoints[0x6]	3713	1		T5	7		T6	9		T138	9
data1	auto[0]	endpoints[0x7]	2619	1		T5	4		T20	10		T213	42
data1	auto[0]	endpoints[0x8]	2943	1		T4	6		T6	7		T20	7
data1	auto[0]	endpoints[0x9]	2877	1		T4	6		T6	6		T53	1
data1	auto[0]	endpoints[0xa]	3471	1		T4	4		T5	8		T20	6
data1	auto[0]	endpoints[0xb]	3054	1		T5	8		T20	7		T74	16
data1	auto[1]	endpoints[0x0]	2523	1		T4	6		T6	9		T53	1
data1	auto[1]	endpoints[0x1]	2773	1		T4	6		T20	10		T53	2
data1	auto[1]	endpoints[0x2]	2479	1		T6	13		T95	17		T145	1
data1	auto[1]	endpoints[0x3]	2501	1		T74	3		T138	14		T139	11
data1	auto[1]	endpoints[0x4]	2994	1		T4	6		T5	11		T20	10
data1	auto[1]	endpoints[0x5]	2468	1		T74	1		T139	8		T147	12
data1	auto[1]	endpoints[0x6]	2620	1		T5	8		T6	9		T74	4
data1	auto[1]	endpoints[0x7]	2661	1		T5	11		T20	10		T52	3
data1	auto[1]	endpoints[0x8]	2513	1		T4	6		T6	11		T20	13
data1	auto[1]	endpoints[0x9]	2926	1		T4	6		T6	13		T74	4
data1	auto[1]	endpoints[0xa]	2644	1		T4	8		T5	9		T20	14
data1	auto[1]	endpoints[0xb]	2637	1		T5	9		T20	12		T74	2
data0	auto[0]	endpoints[0x0]	5441	1		T3	1		T4	6		T6	10
data0	auto[0]	endpoints[0x1]	4765	1		T4	6		T20	10		T60	1
data0	auto[0]	endpoints[0x2]	3549	1		T6	13		T90	1		T137	1
data0	auto[0]	endpoints[0x3]	3116	1		T74	11		T136	1		T85	1
data0	auto[0]	endpoints[0x4]	4640	1		T4	6		T5	14		T20	10
data0	auto[0]	endpoints[0x5]	4057	1		T2	1		T18	1		T27	1
data0	auto[0]	endpoints[0x6]	4764	1		T7	1		T5	11		T6	10
data0	auto[0]	endpoints[0x7]	3791	1		T5	14		T20	10		T21	1
data0	auto[0]	endpoints[0x8]	3935	1		T4	6		T6	12		T20	13
data0	auto[0]	endpoints[0x9]	4167	1		T26	1		T4	6		T6	13
data0	auto[0]	endpoints[0xa]	4629	1		T4	8		T5	10		T20	14
data0	auto[0]	endpoints[0xb]	4138	1		T5	10		T20	13		T74	10
data0	auto[1]	endpoints[0x0]	2163	1		T4	6		T6	10		T53	1
data0	auto[1]	endpoints[0x1]	2362	1		T4	6		T20	10		T136	1
data0	auto[1]	endpoints[0x2]	2143	1		T6	6		T137	1		T95	17
data0	auto[1]	endpoints[0x3]	2171	1		T74	1		T136	1		T138	10
data0	auto[1]	endpoints[0x4]	2474	1		T4	6		T5	7		T20	10
data0	auto[1]	endpoints[0x5]	2180	1		T2	1		T27	1		T74	1
data0	auto[1]	endpoints[0x6]	2320	1		T7	1		T5	10		T6	10
data0	auto[1]	endpoints[0x7]	2209	1		T5	7		T20	10		T52	10
data0	auto[1]	endpoints[0x8]	2172	1		T4	6		T6	8		T20	7
data0	auto[1]	endpoints[0x9]	2456	1		T4	6		T6	6		T140	1
data0	auto[1]	endpoints[0xa]	2308	1		T4	4		T5	9		T20	6
data0	auto[1]	endpoints[0xb]	2265	1		T5	9		T20	8		T74	1