Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	9	7	43.75

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	9	7	43.75	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6177	1		T74	72		T95	11		T75	8
auto[1]	69830	1		T2	1		T7	1		T4	78

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	70880	1		T2	1		T7	1		T4	78
auto[1]	5127	1		T37	135		T86	1		T87	1

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	72044	1		T2	1		T7	1		T4	78
auto[1]	3963	1		T17	1		T74	1		T75	6

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
ignore_pre[PidTypePre]	621	1		T95	16		T138	9		T148	8
pkt_types[PidTypeInToken]	75386	1		T2	1		T7	1		T4	78

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	9	7	43.75	9

Automatically Generated Cross Bins for cr_pid_x_epconfig

Element holes

cp_pid	cp_in_enable	cp_in_iso	cp_in_stall	COUNT	AT LEAST	NUMBER
[ignore_pre[PidTypePre]]	*	[auto[0]]	[auto[1]]	--	--	2
[ignore_pre[PidTypePre]]	*	[auto[1]]	*	--	--	4
[pkt_types[PidTypeInToken]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_pid	cp_in_enable	cp_in_iso	cp_in_stall	COUNT	AT LEAST	NUMBER
[pkt_types[PidTypeInToken]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

305

1

T95

11

T138

7

T148

6

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

316

1

T95

5

T138

2

T148

2

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

3699

1

T74

72

T75

2

T69

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2173

1

T75

6

T82

59

T282

3

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

62597

1

T2

1

T7

1

T4

78

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

1790

1

T17

1

T74

1

T88

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

5127

1

T37

135

T86

1

T87

1