Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
26.57	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	192	152	40	20.83

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_out_enable	2	0	2	100.00	100	1	1	2
cp_out_iso	2	0	2	100.00	100	1	1	2
cp_out_stall	2	0	2	100.00	100	1	1	2
cp_pid	3	0	3	100.00	100	1	1	0
cp_rxenable_out	2	0	2	100.00	100	1	1	2
cp_rxenable_setup	2	0	2	100.00	100	1	1	2
cp_set_nak_out	2	0	2	100.00	100	1	1	2

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	192	152	40	20.83	100	1	1	0

Summary for Variable cp_out_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_enable

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	17208	1		T1	1		T74	231		T95	19
auto[1]	99221	1		T2	1		T3	1		T29	1

---

Summary for Variable cp_out_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_iso

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	116379	1		T1	1		T2	1		T29	1
auto[1]	50	1		T3	1		T90	1		T102	1

---

Summary for Variable cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_stall

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	104620	1		T1	1		T2	1		T3	1
auto[1]	11809	1		T60	1		T61	1		T74	83

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
ignore_pre[PidTypePre]	1240	1		T95	32		T138	26		T148	21
pkt_types[PidTypeSetupToken]	21112	1		T4	6		T5	25		T6	31
pkt_types[PidTypeOutToken]	94011	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_rxenable_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_out

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	17906	1		T1	1		T18	1		T21	1
auto[1]	98523	1		T2	1		T3	1		T29	1

---

Summary for Variable cp_rxenable_setup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_setup

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	76964	1		T1	1		T2	1		T3	1
auto[1]	39465	1		T29	1		T4	12		T5	54

---

Summary for Variable cp_set_nak_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_set_nak_out

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	116279	1		T1	1		T2	1		T3	1
auto[1]	150	1		T18	2		T135	1		T104	2

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_out_enable cp_rxenable_setup cp_rxenable_out cp_set_nak_out cp_out_iso cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	192	152	40	20.83	152

Automatically Generated Cross Bins for cr_pid_x_epconfig

Element holes

cp_pid	cp_out_enable	cp_rxenable_setup	cp_rxenable_out	cp_set_nak_out	cp_out_iso	cp_out_stall	COUNT	AT LEAST	NUMBER
[ignore_pre[PidTypePre]]	[auto[0]]	*	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	--	--	2
[ignore_pre[PidTypePre]]	[auto[0]]	*	[auto[0]]	[auto[0]]	[auto[1]]	*	--	--	4
[ignore_pre[PidTypePre]]	[auto[0]]	*	[auto[0]]	[auto[1]]	*	*	--	--	8
[ignore_pre[PidTypePre]]	[auto[0]]	*	[auto[1]]	*	*	*	--	--	16
[ignore_pre[PidTypePre]]	[auto[1]]	*	[auto[0]]	*	*	*	--	--	16
[ignore_pre[PidTypePre]]	[auto[1]]	*	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	--	--	2
[ignore_pre[PidTypePre]]	[auto[1]]	*	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	4
[ignore_pre[PidTypePre]]	[auto[1]]	*	[auto[1]]	[auto[1]]	*	*	--	--	8
[pkt_types[PidTypeSetupToken]]	*	*	*	[auto[0]]	[auto[1]]	*	--	--	16
[pkt_types[PidTypeSetupToken]]	*	*	*	[auto[1]]	*	*	--	--	32
[pkt_types[PidTypeOutToken]]	[auto[0]]	*	*	[auto[0]]	[auto[1]]	*	--	--	8
[pkt_types[PidTypeOutToken]]	[auto[0]]	*	*	[auto[1]]	*	*	--	--	16
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	--	--	2
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[1]]	*	[auto[0]]	[auto[1]]	*	--	--	4
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[1]]	*	[auto[1]]	*	*	--	--	8

Uncovered bins

cp_pid	cp_out_enable	cp_rxenable_setup	cp_rxenable_out	cp_set_nak_out	cp_out_iso	cp_out_stall	COUNT	AT LEAST	NUMBER
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_pid

cp_out_enable

cp_rxenable_setup

cp_rxenable_out

cp_set_nak_out

cp_out_iso

cp_out_stall

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

282

1

T95

6

T138

14

T148

7

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

316

1

T95

13

T138

4

T148

8

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

347

1

T95

13

T138

1

T141

2

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

295

1

T138

7

T148

6

T141

7

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

479

1

T74

9

T280

2

T70

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

534

1

T83

53

T281

10

T164

12

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

840

1

T74

15

T82

17

T83

45

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

518

1

T74

28

T75

1

T280

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

906

1

T74

17

T69

1

T282

3

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

672

1

T280

3

T83

20

T283

53

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

590

1

T74

7

T82

18

T283

35

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

886

1

T75

2

T284

6

T82

23

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

714

1

T100

1

T101

1

T285

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

655

1

T82

57

T83

22

T283

17

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

693

1

T69

2

T82

39

T281

53

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

489

1

T82

55

T283

20

T281

13

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1753

1

T21

1

T74

54

T85

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

39

1

T74

1

T50

1

T82

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

11188

1

T4

6

T5

25

T6

31

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

156

1

T74

1

T145

1

T99

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1147

1

T1

1

T74

19

T172

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

1042

1

T282

1

T83

86

T281

22

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1717

1

T74

24

T284

2

T82

60

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1059

1

T74

52

T75

1

T280

3

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1769

1

T74

24

T280

1

T69

3

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1422

1

T280

4

T282

1

T83

44

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1214

1

T74

36

T75

8

T82

51

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1786

1

T75

1

T284

7

T82

45

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1511

1

T103

1

T286

1

T287

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

1307

1

T82

112

T83

45

T283

40

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T18

1

T104

1

T119

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

62372

1

T2

1

T26

1

T7

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1027

1

T60

1

T61

1

T288

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

50

1

T3

1

T90

1

T102

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T18

1

T104

1

T119

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

50

1

T135

1

T289

1

T290

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

3208

1

T74

92

T82

61

T83

88

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

71

1

T291

2

T158

1

T292

8

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

13063

1

T4

6

T5

29

T6

26

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

96

1

T74

1

T82

3

T83

4