Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
32.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	1	10	90.91
Crosses	54	43	11	20.37

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	1	2	66.67	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	43	11	20.37	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	41076	1		T4	72		T5	90		T6	95
solo	87447	1		T1	1		T2	1		T3	1
empty	1904	1		T21	1		T74	13		T85	1

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	41071	1		T4	72		T5	90		T6	95
solo	42443	1		T21	1		T74	496		T85	1
empty	46974	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
out	105603	1		T1	1		T2	1		T3	1
setup	24893	1		T4	6		T5	25		T6	31

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_rx

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
full	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
solo	13	1		T41	2		T62	1		T42	2
empty	108194	1		T1	1		T2	1		T3	1

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	43	11	20.37	43

Automatically Generated Cross Bins for cr_fifo_X_pid

Element holes

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER
[full]	[full]	[full , solo]	*	--	--	4
[full]	[solo , empty]	*	*	--	--	12
[solo]	[full]	[full , solo]	*	--	--	4
[solo]	[solo]	[full]	*	--	--	2
[solo]	[empty]	[full , solo]	*	--	--	4
[empty]	[full]	*	*	--	--	6
[empty]	[solo]	[full , solo]	*	--	--	4
[empty]	[empty]	[full , solo]	*	--	--	4

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER
[solo]	[full]	[empty]	[setup]	0	1	1
[solo]	[empty]	[empty]	[out]	0	1	1
[empty]	[solo]	[empty]	[setup]	0	1	1

Covered bins

cp_avsetup

cp_avout

cp_rx

cp_pid

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

full

full

empty

out

31863

1

T4

66

T5

65

T6

64

full

full

empty

setup

9207

1

T4

6

T5

25

T6

31

solo

full

empty

out

5

1

T41

1

T42

1

T43

1

solo

solo

solo

out

5

1

T41

1

T42

1

T43

1

solo

solo

solo

setup

5

1

T41

1

T42

1

T43

1

solo

solo

empty

out

15664

1

T74

184

T75

7

T280

15

solo

solo

empty

setup

7945

1

T74

98

T75

3

T280

7

solo

empty

empty

setup

308

1

T21

1

T74

1

T85

1

empty

solo

empty

out

43004

1

T1

1

T2

1

T3

1

empty

empty

empty

out

135

1

T62

1

T63

1

T64

1

empty

empty

empty

setup

50

1

T100

1

T101

1

T285

1