Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	86882	1		T1	3		T2	5		T3	3
all_pins[1]	86882	1		T1	3		T2	5		T3	3
all_pins[2]	86882	1		T1	3		T2	5		T3	3
all_pins[3]	86882	1		T1	3		T2	5		T3	3
all_pins[4]	86882	1		T1	3		T2	5		T3	3
all_pins[5]	86882	1		T1	3		T2	5		T3	3
all_pins[6]	86882	1		T1	3		T2	5		T3	3
all_pins[7]	86882	1		T1	3		T2	5		T3	3
all_pins[8]	86882	1		T1	3		T2	5		T3	3
all_pins[9]	86882	1		T1	3		T2	5		T3	3
all_pins[10]	86882	1		T1	3		T2	5		T3	3
all_pins[11]	86882	1		T1	3		T2	5		T3	3
all_pins[12]	86882	1		T1	3		T2	5		T3	3
all_pins[13]	86882	1		T1	3		T2	5		T3	3
all_pins[14]	86882	1		T1	3		T2	5		T3	3
all_pins[15]	86882	1		T1	3		T2	5		T3	3
all_pins[16]	86882	1		T1	3		T2	5		T3	3
all_pins[17]	86882	1		T1	3		T2	5		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2777819	1		T1	95		T2	159		T3	96
values[0x1]	2405	1		T1	1		T2	1		T29	1
transitions[0x0=>0x1]	2109	1		T1	1		T2	1		T29	1
transitions[0x1=>0x0]	2109	1		T1	1		T2	1		T29	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	86768	1		T1	3		T2	5		T3	3
all_pins[0]	values[0x1]	114	1		T26	1		T45	1		T46	1
all_pins[0]	transitions[0x0=>0x1]	100	1		T26	1		T45	1		T46	1
all_pins[0]	transitions[0x1=>0x0]	996	1		T2	1		T7	1		T22	1
all_pins[1]	values[0x0]	85872	1		T1	3		T2	4		T3	3
all_pins[1]	values[0x1]	1010	1		T2	1		T7	1		T22	1
all_pins[1]	transitions[0x0=>0x1]	990	1		T2	1		T7	1		T22	1
all_pins[1]	transitions[0x1=>0x0]	108	1		T19	1		T36	1		T38	1
all_pins[2]	values[0x0]	86754	1		T1	3		T2	5		T3	3
all_pins[2]	values[0x1]	128	1		T19	1		T36	1		T38	1
all_pins[2]	transitions[0x0=>0x1]	114	1		T19	1		T36	1		T38	1
all_pins[2]	transitions[0x1=>0x0]	50	1		T58	1		T193	1		T196	1
all_pins[3]	values[0x0]	86818	1		T1	3		T2	5		T3	3
all_pins[3]	values[0x1]	64	1		T58	1		T193	1		T196	1
all_pins[3]	transitions[0x0=>0x1]	38	1		T58	1		T193	1		T196	1
all_pins[3]	transitions[0x1=>0x0]	51	1		T59	1		T193	2		T195	1
all_pins[4]	values[0x0]	86805	1		T1	3		T2	5		T3	3
all_pins[4]	values[0x1]	77	1		T59	1		T193	2		T194	2
all_pins[4]	transitions[0x0=>0x1]	56	1		T59	1		T193	2		T195	2
all_pins[4]	transitions[0x1=>0x0]	54	1		T194	2		T195	3		T297	2
all_pins[5]	values[0x0]	86807	1		T1	3		T2	5		T3	3
all_pins[5]	values[0x1]	75	1		T194	4		T195	3		T278	1
all_pins[5]	transitions[0x0=>0x1]	57	1		T194	2		T195	3		T278	1
all_pins[5]	transitions[0x1=>0x0]	35	1		T196	1		T195	1		T297	1
all_pins[6]	values[0x0]	86829	1		T1	3		T2	5		T3	3
all_pins[6]	values[0x1]	53	1		T196	1		T194	2		T195	1
all_pins[6]	transitions[0x0=>0x1]	43	1		T196	1		T194	2		T195	1
all_pins[6]	transitions[0x1=>0x0]	50	1		T47	1		T48	1		T49	1
all_pins[7]	values[0x0]	86822	1		T1	3		T2	5		T3	3
all_pins[7]	values[0x1]	60	1		T47	1		T48	1		T49	1
all_pins[7]	transitions[0x0=>0x1]	46	1		T47	1		T48	1		T49	1
all_pins[7]	transitions[0x1=>0x0]	35	1		T193	1		T194	1		T195	1
all_pins[8]	values[0x0]	86833	1		T1	3		T2	5		T3	3
all_pins[8]	values[0x1]	49	1		T193	1		T194	1		T195	1
all_pins[8]	transitions[0x0=>0x1]	35	1		T193	1		T194	1		T195	1
all_pins[8]	transitions[0x1=>0x0]	67	1		T55	2		T56	2		T57	2
all_pins[9]	values[0x0]	86801	1		T1	3		T2	5		T3	3
all_pins[9]	values[0x1]	81	1		T55	2		T56	2		T57	2
all_pins[9]	transitions[0x0=>0x1]	65	1		T55	2		T56	2		T57	2
all_pins[9]	transitions[0x1=>0x0]	53	1		T193	2		T196	1		T194	2
all_pins[10]	values[0x0]	86813	1		T1	3		T2	5		T3	3
all_pins[10]	values[0x1]	69	1		T193	2		T196	1		T194	2
all_pins[10]	transitions[0x0=>0x1]	52	1		T193	2		T196	1		T194	2
all_pins[10]	transitions[0x1=>0x0]	115	1		T40	1		T67	1		T68	1
all_pins[11]	values[0x0]	86750	1		T1	3		T2	5		T3	3
all_pins[11]	values[0x1]	132	1		T40	1		T67	1		T68	1
all_pins[11]	transitions[0x0=>0x1]	116	1		T40	1		T67	1		T68	1
all_pins[11]	transitions[0x1=>0x0]	58	1		T29	1		T71	1		T72	1
all_pins[12]	values[0x0]	86808	1		T1	3		T2	5		T3	3
all_pins[12]	values[0x1]	74	1		T29	1		T71	1		T72	1
all_pins[12]	transitions[0x0=>0x1]	58	1		T29	1		T71	1		T72	1
all_pins[12]	transitions[0x1=>0x0]	117	1		T1	1		T65	1		T66	1
all_pins[13]	values[0x0]	86749	1		T1	2		T2	5		T3	3
all_pins[13]	values[0x1]	133	1		T1	1		T65	1		T66	1
all_pins[13]	transitions[0x0=>0x1]	107	1		T1	1		T65	1		T66	1
all_pins[13]	transitions[0x1=>0x0]	40	1		T193	3		T297	1		T279	1
all_pins[14]	values[0x0]	86816	1		T1	3		T2	5		T3	3
all_pins[14]	values[0x1]	66	1		T193	5		T196	1		T194	2
all_pins[14]	transitions[0x0=>0x1]	48	1		T193	5		T196	1		T195	1
all_pins[14]	transitions[0x1=>0x0]	59	1		T297	2		T279	1		T298	2
all_pins[15]	values[0x0]	86805	1		T1	3		T2	5		T3	3
all_pins[15]	values[0x1]	77	1		T194	2		T297	2		T279	2
all_pins[15]	transitions[0x0=>0x1]	57	1		T194	2		T279	2		T298	2
all_pins[15]	transitions[0x1=>0x0]	61	1		T62	4		T63	4		T64	4
all_pins[16]	values[0x0]	86801	1		T1	3		T2	5		T3	3
all_pins[16]	values[0x1]	81	1		T62	4		T63	4		T64	4
all_pins[16]	transitions[0x0=>0x1]	65	1		T62	4		T63	4		T64	4
all_pins[16]	transitions[0x1=>0x0]	46	1		T50	1		T51	1		T193	1
all_pins[17]	values[0x0]	86820	1		T1	3		T2	5		T3	3
all_pins[17]	values[0x1]	62	1		T50	1		T51	1		T193	2
all_pins[17]	transitions[0x0=>0x1]	62	1		T50	1		T51	1		T193	2