Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4694	1		T20	21		T74	50		T79	10
invalid_ep[0xd]	4728	1		T20	37		T74	54		T79	13
invalid_ep[0xe]	4861	1		T20	26		T74	45		T79	13
invalid_ep[0xf]	4813	1		T20	24		T74	44		T79	15
endpoints[0x0]	18348	1		T1	1		T3	1		T4	25
endpoints[0x1]	17476	1		T4	25		T20	41		T60	1
endpoints[0x2]	14472	1		T6	39		T90	1		T137	2
endpoints[0x3]	13670	1		T74	49		T95	2		T136	2
endpoints[0x4]	17557	1		T4	25		T5	37		T20	41
endpoints[0x5]	15202	1		T2	2		T18	2		T27	2
endpoints[0x6]	17159	1		T7	2		T17	1		T5	37
endpoints[0x7]	14814	1		T29	1		T5	37		T20	41
endpoints[0x8]	14951	1		T4	25		T6	39		T20	41
endpoints[0x9]	16171	1		T26	1		T4	25		T6	39
endpoints[0xa]	16892	1		T4	25		T5	37		T20	41
endpoints[0xb]	15724	1		T5	37		T20	41		T74	51

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	24893	1		T4	6		T5	25		T6	31
pkt_types[PidTypeOutToken]	105603	1		T1	1		T2	1		T3	1
pkt_types[PidTypeInToken]	79109	1		T2	1		T7	1		T4	78

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	900	1		T74	10		T82	32		T83	21
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	937	1		T74	17		T82	21		T83	13
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	962	1		T74	11		T82	19		T83	16
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	982	1		T74	8		T82	27		T83	20
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1671	1		T74	15		T141	5		T142	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1842	1		T74	11		T143	1		T144	10
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1716	1		T6	10		T74	11		T75	2
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1686	1		T74	14		T85	1		T75	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1932	1		T5	10		T74	9		T146	7
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1618	1		T74	15		T147	10		T144	9
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1647	1		T74	12		T138	12		T139	8
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1882	1		T5	10		T21	1		T74	7
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1701	1		T6	9		T20	8		T74	17
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1912	1		T6	12		T74	16		T144	6
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1760	1		T4	6		T20	11		T74	15
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1745	1		T5	5		T20	9		T74	14
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	2877	1		T20	21		T74	25		T79	10
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	2860	1		T20	37		T74	22		T79	13
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	2958	1		T20	26		T74	22		T79	13
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	2897	1		T20	24		T74	20		T79	15
pkt_types[PidTypeOutToken]	endpoints[0x0]	10453	1		T1	1		T3	1		T4	12
pkt_types[PidTypeOutToken]	endpoints[0x1]	8803	1		T4	12		T20	20		T60	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	6558	1		T6	9		T90	1		T137	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	5733	1		T74	22		T136	1		T135	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	8579	1		T4	12		T5	8		T20	20
pkt_types[PidTypeOutToken]	endpoints[0x5]	7550	1		T2	1		T18	2		T27	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	9002	1		T7	1		T5	18		T6	19
pkt_types[PidTypeOutToken]	endpoints[0x7]	6647	1		T5	8		T20	20		T74	36
pkt_types[PidTypeOutToken]	endpoints[0x8]	7229	1		T4	12		T6	10		T20	12
pkt_types[PidTypeOutToken]	endpoints[0x9]	7236	1		T26	1		T4	12		T6	7
pkt_types[PidTypeOutToken]	endpoints[0xa]	8704	1		T4	6		T5	18		T20	9
pkt_types[PidTypeOutToken]	endpoints[0xb]	7517	1		T5	13		T20	11		T74	27
pkt_types[PidTypeInToken]	invalid_ep[0xc]	917	1		T74	15		T82	36		T83	25
pkt_types[PidTypeInToken]	invalid_ep[0xd]	931	1		T74	15		T82	23		T83	28
pkt_types[PidTypeInToken]	invalid_ep[0xe]	941	1		T74	12		T82	19		T83	29
pkt_types[PidTypeInToken]	invalid_ep[0xf]	934	1		T74	16		T82	36		T83	27
pkt_types[PidTypeInToken]	endpoints[0x0]	6060	1		T4	13		T6	20		T74	20
pkt_types[PidTypeInToken]	endpoints[0x1]	6643	1		T4	13		T20	21		T37	135
pkt_types[PidTypeInToken]	endpoints[0x2]	6066	1		T6	20		T137	1		T74	14
pkt_types[PidTypeInToken]	endpoints[0x3]	6105	1		T74	13		T136	1		T75	1
pkt_types[PidTypeInToken]	endpoints[0x4]	6885	1		T4	13		T5	19		T20	21
pkt_types[PidTypeInToken]	endpoints[0x5]	5864	1		T2	1		T27	1		T74	6
pkt_types[PidTypeInToken]	endpoints[0x6]	6361	1		T7	1		T17	1		T5	19
pkt_types[PidTypeInToken]	endpoints[0x7]	6105	1		T5	19		T20	21		T52	13
pkt_types[PidTypeInToken]	endpoints[0x8]	5851	1		T4	13		T6	20		T20	21
pkt_types[PidTypeInToken]	endpoints[0x9]	6846	1		T4	13		T6	20		T140	1
pkt_types[PidTypeInToken]	endpoints[0xa]	6272	1		T4	13		T5	19		T20	21
pkt_types[PidTypeInToken]	endpoints[0xb]	6328	1		T5	19		T20	21		T74	10