Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T193	7		T196	4		T194	4
all_values[1]	278	1		T193	7		T196	4		T194	4
all_values[2]	278	1		T193	7		T196	4		T194	4
all_values[3]	278	1		T193	7		T196	4		T194	4
all_values[4]	278	1		T193	7		T196	4		T194	4
all_values[5]	278	1		T193	7		T196	4		T194	4
all_values[6]	278	1		T193	7		T196	4		T194	4
all_values[7]	278	1		T193	7		T196	4		T194	4
all_values[8]	278	1		T193	7		T196	4		T194	4
all_values[9]	278	1		T193	7		T196	4		T194	4
all_values[10]	278	1		T193	7		T196	4		T194	4
all_values[11]	278	1		T193	7		T196	4		T194	4
all_values[12]	278	1		T193	7		T196	4		T194	4
all_values[13]	278	1		T193	7		T196	4		T194	4
all_values[14]	278	1		T193	7		T196	4		T194	4
all_values[15]	278	1		T193	7		T196	4		T194	4
all_values[16]	278	1		T193	7		T196	4		T194	4
all_values[17]	278	1		T193	7		T196	4		T194	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6529	1		T193	158		T196	98		T194	91
auto[1]	2367	1		T193	66		T196	30		T194	37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6075	1		T193	155		T196	91		T194	91
auto[1]	2821	1		T193	69		T196	37		T194	37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5209	1		T193	138		T196	86		T194	84
auto[1]	3687	1		T193	86		T196	42		T194	44

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	80	1		T193	4		T194	1		T195	3
all_values[0]	auto[0]	auto[1]	auto[0]	75	1		T196	2		T194	1		T195	3
all_values[0]	auto[1]	auto[0]	auto[1]	60	1		T196	2		T194	1		T195	1
all_values[0]	auto[1]	auto[1]	auto[1]	63	1		T193	3		T194	1		T297	1
all_values[1]	auto[0]	auto[0]	auto[0]	79	1		T193	1		T194	1		T278	1
all_values[1]	auto[0]	auto[1]	auto[0]	91	1		T193	2		T196	2		T194	1
all_values[1]	auto[1]	auto[0]	auto[1]	51	1		T193	2		T196	1		T194	2
all_values[1]	auto[1]	auto[1]	auto[1]	57	1		T193	2		T196	1		T195	3
all_values[2]	auto[0]	auto[0]	auto[0]	40	1		T193	1		T194	1		T195	3
all_values[2]	auto[0]	auto[0]	auto[1]	43	1		T193	1		T194	1		T195	1
all_values[2]	auto[0]	auto[1]	auto[0]	48	1		T193	3		T194	1		T278	4
all_values[2]	auto[0]	auto[1]	auto[1]	35	1		T193	1		T196	2		T194	1
all_values[2]	auto[1]	auto[0]	auto[1]	59	1		T193	1		T196	1		T195	1
all_values[2]	auto[1]	auto[1]	auto[1]	53	1		T196	1		T278	1		T297	3
all_values[3]	auto[0]	auto[0]	auto[0]	64	1		T193	1		T196	1		T278	1
all_values[3]	auto[0]	auto[0]	auto[1]	30	1		T193	1		T196	2		T298	1
all_values[3]	auto[0]	auto[1]	auto[0]	38	1		T195	1		T278	2		T297	2
all_values[3]	auto[0]	auto[1]	auto[1]	31	1		T194	2		T195	2		T279	1
all_values[3]	auto[1]	auto[0]	auto[1]	70	1		T193	4		T196	1		T194	1
all_values[3]	auto[1]	auto[1]	auto[1]	45	1		T193	1		T194	1		T195	2
all_values[4]	auto[0]	auto[0]	auto[0]	64	1		T193	1		T196	1		T195	3
all_values[4]	auto[0]	auto[0]	auto[1]	26	1		T193	1		T194	1		T278	1
all_values[4]	auto[0]	auto[1]	auto[0]	32	1		T193	2		T196	1		T278	1
all_values[4]	auto[0]	auto[1]	auto[1]	31	1		T193	1		T196	1		T194	1
all_values[4]	auto[1]	auto[0]	auto[1]	65	1		T196	1		T194	2		T195	2
all_values[4]	auto[1]	auto[1]	auto[1]	60	1		T193	2		T195	1		T278	3
all_values[5]	auto[0]	auto[0]	auto[0]	48	1		T196	1		T195	2		T278	1
all_values[5]	auto[0]	auto[0]	auto[1]	26	1		T278	1		T298	2		T299	2
all_values[5]	auto[0]	auto[1]	auto[0]	54	1		T193	3		T196	2		T278	1
all_values[5]	auto[0]	auto[1]	auto[1]	25	1		T194	1		T195	2		T298	1
all_values[5]	auto[1]	auto[0]	auto[1]	72	1		T193	4		T194	1		T195	2
all_values[5]	auto[1]	auto[1]	auto[1]	53	1		T196	1		T194	2		T195	1
all_values[6]	auto[0]	auto[0]	auto[0]	82	1		T196	1		T194	2		T195	2
all_values[6]	auto[0]	auto[0]	auto[1]	26	1		T196	1		T278	1		T297	1
all_values[6]	auto[0]	auto[1]	auto[0]	50	1		T193	3		T195	1		T297	1
all_values[6]	auto[0]	auto[1]	auto[1]	23	1		T193	1		T194	1		T195	1
all_values[6]	auto[1]	auto[0]	auto[1]	57	1		T193	1		T196	2		T194	1
all_values[6]	auto[1]	auto[1]	auto[1]	40	1		T193	2		T195	1		T297	1
all_values[7]	auto[0]	auto[0]	auto[0]	85	1		T193	4		T196	2		T194	3
all_values[7]	auto[0]	auto[1]	auto[0]	69	1		T193	1		T196	1		T195	1
all_values[7]	auto[1]	auto[0]	auto[1]	76	1		T196	1		T194	1		T195	3
all_values[7]	auto[1]	auto[1]	auto[1]	48	1		T193	2		T195	1		T297	2
all_values[8]	auto[0]	auto[0]	auto[0]	92	1		T193	2		T196	2		T194	1
all_values[8]	auto[0]	auto[1]	auto[0]	77	1		T193	2		T196	1		T194	2
all_values[8]	auto[1]	auto[0]	auto[1]	65	1		T193	2		T196	1		T195	2
all_values[8]	auto[1]	auto[1]	auto[1]	44	1		T193	1		T194	1		T195	2
all_values[9]	auto[0]	auto[0]	auto[0]	64	1		T193	3		T278	4		T279	2
all_values[9]	auto[0]	auto[0]	auto[1]	25	1		T193	1		T195	1		T297	1
all_values[9]	auto[0]	auto[1]	auto[0]	47	1		T196	1		T194	3		T195	4
all_values[9]	auto[0]	auto[1]	auto[1]	30	1		T196	1		T297	1		T279	2
all_values[9]	auto[1]	auto[0]	auto[1]	62	1		T193	3		T196	2		T194	1
all_values[9]	auto[1]	auto[1]	auto[1]	50	1		T195	1		T278	1		T297	2
all_values[10]	auto[0]	auto[0]	auto[0]	60	1		T194	1		T195	4		T278	3
all_values[10]	auto[0]	auto[0]	auto[1]	24	1		T297	1		T279	1		T300	1
all_values[10]	auto[0]	auto[1]	auto[0]	44	1		T193	2		T196	1		T194	1
all_values[10]	auto[0]	auto[1]	auto[1]	36	1		T193	2		T196	1		T194	1
all_values[10]	auto[1]	auto[0]	auto[1]	63	1		T193	2		T196	1		T278	2
all_values[10]	auto[1]	auto[1]	auto[1]	51	1		T193	1		T196	1		T194	1
all_values[11]	auto[0]	auto[0]	auto[0]	48	1		T193	1		T196	1		T194	3
all_values[11]	auto[0]	auto[0]	auto[1]	26	1		T193	1		T278	1		T279	1
all_values[11]	auto[0]	auto[1]	auto[0]	42	1		T193	3		T196	3		T194	1
all_values[11]	auto[0]	auto[1]	auto[1]	32	1		T193	1		T195	2		T297	1
all_values[11]	auto[1]	auto[0]	auto[1]	64	1		T193	1		T195	1		T278	2
all_values[11]	auto[1]	auto[1]	auto[1]	66	1		T195	3		T278	4		T297	4
all_values[12]	auto[0]	auto[0]	auto[0]	63	1		T193	2		T194	1		T195	1
all_values[12]	auto[0]	auto[0]	auto[1]	24	1		T193	1		T196	1		T194	1
all_values[12]	auto[0]	auto[1]	auto[0]	57	1		T193	2		T195	2		T278	2
all_values[12]	auto[0]	auto[1]	auto[1]	21	1		T194	1		T301	1		T302	1
all_values[12]	auto[1]	auto[0]	auto[1]	55	1		T193	1		T196	2		T194	1
all_values[12]	auto[1]	auto[1]	auto[1]	58	1		T193	1		T196	1		T297	1
all_values[13]	auto[0]	auto[0]	auto[0]	42	1		T193	2		T196	1		T278	2
all_values[13]	auto[0]	auto[0]	auto[1]	38	1		T196	2		T195	2		T278	2
all_values[13]	auto[0]	auto[1]	auto[0]	43	1		T193	1		T195	1		T279	3
all_values[13]	auto[0]	auto[1]	auto[1]	29	1		T193	1		T194	2		T278	1
all_values[13]	auto[1]	auto[0]	auto[1]	57	1		T193	2		T194	1		T195	2
all_values[13]	auto[1]	auto[1]	auto[1]	69	1		T193	1		T196	1		T194	1
all_values[14]	auto[0]	auto[0]	auto[0]	64	1		T196	1		T194	1		T195	3
all_values[14]	auto[0]	auto[0]	auto[1]	23	1		T196	1		T298	3		T303	2
all_values[14]	auto[0]	auto[1]	auto[0]	56	1		T193	1		T194	1		T278	4
all_values[14]	auto[0]	auto[1]	auto[1]	25	1		T193	2		T194	1		T279	1
all_values[14]	auto[1]	auto[0]	auto[1]	56	1		T193	1		T196	1		T195	3
all_values[14]	auto[1]	auto[1]	auto[1]	54	1		T193	3		T196	1		T194	1
all_values[15]	auto[0]	auto[0]	auto[0]	53	1		T193	1		T196	3		T194	2
all_values[15]	auto[0]	auto[0]	auto[1]	19	1		T195	2		T278	1		T297	2
all_values[15]	auto[0]	auto[1]	auto[0]	53	1		T193	4		T196	1		T195	1
all_values[15]	auto[0]	auto[1]	auto[1]	33	1		T193	1		T194	1		T297	1
all_values[15]	auto[1]	auto[0]	auto[1]	56	1		T193	1		T194	1		T195	3
all_values[15]	auto[1]	auto[1]	auto[1]	64	1		T195	1		T278	1		T297	2
all_values[16]	auto[0]	auto[0]	auto[0]	55	1		T193	1		T196	3		T194	1
all_values[16]	auto[0]	auto[0]	auto[1]	26	1		T193	2		T279	1		T298	1
all_values[16]	auto[0]	auto[1]	auto[0]	56	1		T194	2		T195	1		T278	2
all_values[16]	auto[0]	auto[1]	auto[1]	22	1		T195	3		T278	1		T297	2
all_values[16]	auto[1]	auto[0]	auto[1]	61	1		T196	1		T278	3		T298	1
all_values[16]	auto[1]	auto[1]	auto[1]	58	1		T193	4		T194	1		T195	3
all_values[17]	auto[0]	auto[0]	auto[0]	85	1		T193	2		T196	1		T194	1
all_values[17]	auto[0]	auto[1]	auto[0]	83	1		T193	2		T196	2		T194	3
all_values[17]	auto[1]	auto[0]	auto[1]	64	1		T193	1		T195	1		T278	2
all_values[17]	auto[1]	auto[1]	auto[1]	46	1		T193	2		T196	1		T195	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal